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at86rf230: mask irq's before deregister device
[deliverable/linux.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
1 /*
2 * Copyright (C) 2005 - 2013 Emulex
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@emulex.com
12 *
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
16 */
17
18 #include <linux/module.h>
19 #include "be.h"
20 #include "be_cmds.h"
21
22 static struct be_cmd_priv_map cmd_priv_map[] = {
23 {
24 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
25 CMD_SUBSYSTEM_ETH,
26 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
27 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
28 },
29 {
30 OPCODE_COMMON_GET_FLOW_CONTROL,
31 CMD_SUBSYSTEM_COMMON,
32 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
33 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
34 },
35 {
36 OPCODE_COMMON_SET_FLOW_CONTROL,
37 CMD_SUBSYSTEM_COMMON,
38 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
39 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
40 },
41 {
42 OPCODE_ETH_GET_PPORT_STATS,
43 CMD_SUBSYSTEM_ETH,
44 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
45 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
46 },
47 {
48 OPCODE_COMMON_GET_PHY_DETAILS,
49 CMD_SUBSYSTEM_COMMON,
50 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
51 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
52 }
53 };
54
55 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode,
56 u8 subsystem)
57 {
58 int i;
59 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
60 u32 cmd_privileges = adapter->cmd_privileges;
61
62 for (i = 0; i < num_entries; i++)
63 if (opcode == cmd_priv_map[i].opcode &&
64 subsystem == cmd_priv_map[i].subsystem)
65 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
66 return false;
67
68 return true;
69 }
70
71 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
72 {
73 return wrb->payload.embedded_payload;
74 }
75
76 static void be_mcc_notify(struct be_adapter *adapter)
77 {
78 struct be_queue_info *mccq = &adapter->mcc_obj.q;
79 u32 val = 0;
80
81 if (be_error(adapter))
82 return;
83
84 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
85 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
86
87 wmb();
88 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
89 }
90
91 /* To check if valid bit is set, check the entire word as we don't know
92 * the endianness of the data (old entry is host endian while a new entry is
93 * little endian) */
94 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
95 {
96 u32 flags;
97
98 if (compl->flags != 0) {
99 flags = le32_to_cpu(compl->flags);
100 if (flags & CQE_FLAGS_VALID_MASK) {
101 compl->flags = flags;
102 return true;
103 }
104 }
105 return false;
106 }
107
108 /* Need to reset the entire word that houses the valid bit */
109 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
110 {
111 compl->flags = 0;
112 }
113
114 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
115 {
116 unsigned long addr;
117
118 addr = tag1;
119 addr = ((addr << 16) << 16) | tag0;
120 return (void *)addr;
121 }
122
123 static int be_mcc_compl_process(struct be_adapter *adapter,
124 struct be_mcc_compl *compl)
125 {
126 u16 compl_status, extd_status;
127 struct be_cmd_resp_hdr *resp_hdr;
128 u8 opcode = 0, subsystem = 0;
129
130 /* Just swap the status to host endian; mcc tag is opaquely copied
131 * from mcc_wrb */
132 be_dws_le_to_cpu(compl, 4);
133
134 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
135 CQE_STATUS_COMPL_MASK;
136
137 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
138
139 if (resp_hdr) {
140 opcode = resp_hdr->opcode;
141 subsystem = resp_hdr->subsystem;
142 }
143
144 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
145 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
146 complete(&adapter->et_cmd_compl);
147 return 0;
148 }
149
150 if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
151 (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
152 (subsystem == CMD_SUBSYSTEM_COMMON)) {
153 adapter->flash_status = compl_status;
154 complete(&adapter->et_cmd_compl);
155 }
156
157 if (compl_status == MCC_STATUS_SUCCESS) {
158 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
159 (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
160 (subsystem == CMD_SUBSYSTEM_ETH)) {
161 be_parse_stats(adapter);
162 adapter->stats_cmd_sent = false;
163 }
164 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
165 subsystem == CMD_SUBSYSTEM_COMMON) {
166 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
167 (void *)resp_hdr;
168 adapter->drv_stats.be_on_die_temperature =
169 resp->on_die_temperature;
170 }
171 } else {
172 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
173 adapter->be_get_temp_freq = 0;
174
175 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
176 compl_status == MCC_STATUS_ILLEGAL_REQUEST)
177 goto done;
178
179 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
180 dev_warn(&adapter->pdev->dev,
181 "VF is not privileged to issue opcode %d-%d\n",
182 opcode, subsystem);
183 } else {
184 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
185 CQE_STATUS_EXTD_MASK;
186 dev_err(&adapter->pdev->dev,
187 "opcode %d-%d failed:status %d-%d\n",
188 opcode, subsystem, compl_status, extd_status);
189
190 if (extd_status == MCC_ADDL_STS_INSUFFICIENT_RESOURCES)
191 return extd_status;
192 }
193 }
194 done:
195 return compl_status;
196 }
197
198 /* Link state evt is a string of bytes; no need for endian swapping */
199 static void be_async_link_state_process(struct be_adapter *adapter,
200 struct be_async_event_link_state *evt)
201 {
202 /* When link status changes, link speed must be re-queried from FW */
203 adapter->phy.link_speed = -1;
204
205 /* Ignore physical link event */
206 if (lancer_chip(adapter) &&
207 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
208 return;
209
210 /* For the initial link status do not rely on the ASYNC event as
211 * it may not be received in some cases.
212 */
213 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
214 be_link_status_update(adapter, evt->port_link_status);
215 }
216
217 /* Grp5 CoS Priority evt */
218 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
219 struct be_async_event_grp5_cos_priority *evt)
220 {
221 if (evt->valid) {
222 adapter->vlan_prio_bmap = evt->available_priority_bmap;
223 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
224 adapter->recommended_prio =
225 evt->reco_default_priority << VLAN_PRIO_SHIFT;
226 }
227 }
228
229 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
230 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
231 struct be_async_event_grp5_qos_link_speed *evt)
232 {
233 if (adapter->phy.link_speed >= 0 &&
234 evt->physical_port == adapter->port_num)
235 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
236 }
237
238 /*Grp5 PVID evt*/
239 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
240 struct be_async_event_grp5_pvid_state *evt)
241 {
242 if (evt->enabled)
243 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
244 else
245 adapter->pvid = 0;
246 }
247
248 static void be_async_grp5_evt_process(struct be_adapter *adapter,
249 u32 trailer, struct be_mcc_compl *evt)
250 {
251 u8 event_type = 0;
252
253 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
254 ASYNC_TRAILER_EVENT_TYPE_MASK;
255
256 switch (event_type) {
257 case ASYNC_EVENT_COS_PRIORITY:
258 be_async_grp5_cos_priority_process(adapter,
259 (struct be_async_event_grp5_cos_priority *)evt);
260 break;
261 case ASYNC_EVENT_QOS_SPEED:
262 be_async_grp5_qos_speed_process(adapter,
263 (struct be_async_event_grp5_qos_link_speed *)evt);
264 break;
265 case ASYNC_EVENT_PVID_STATE:
266 be_async_grp5_pvid_state_process(adapter,
267 (struct be_async_event_grp5_pvid_state *)evt);
268 break;
269 default:
270 dev_warn(&adapter->pdev->dev, "Unknown grp5 event 0x%x!\n",
271 event_type);
272 break;
273 }
274 }
275
276 static void be_async_dbg_evt_process(struct be_adapter *adapter,
277 u32 trailer, struct be_mcc_compl *cmp)
278 {
279 u8 event_type = 0;
280 struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp;
281
282 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
283 ASYNC_TRAILER_EVENT_TYPE_MASK;
284
285 switch (event_type) {
286 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
287 if (evt->valid)
288 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
289 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
290 break;
291 default:
292 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
293 event_type);
294 break;
295 }
296 }
297
298 static inline bool is_link_state_evt(u32 trailer)
299 {
300 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
301 ASYNC_TRAILER_EVENT_CODE_MASK) ==
302 ASYNC_EVENT_CODE_LINK_STATE;
303 }
304
305 static inline bool is_grp5_evt(u32 trailer)
306 {
307 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
308 ASYNC_TRAILER_EVENT_CODE_MASK) ==
309 ASYNC_EVENT_CODE_GRP_5);
310 }
311
312 static inline bool is_dbg_evt(u32 trailer)
313 {
314 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
315 ASYNC_TRAILER_EVENT_CODE_MASK) ==
316 ASYNC_EVENT_CODE_QNQ);
317 }
318
319 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
320 {
321 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
322 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
323
324 if (be_mcc_compl_is_new(compl)) {
325 queue_tail_inc(mcc_cq);
326 return compl;
327 }
328 return NULL;
329 }
330
331 void be_async_mcc_enable(struct be_adapter *adapter)
332 {
333 spin_lock_bh(&adapter->mcc_cq_lock);
334
335 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
336 adapter->mcc_obj.rearm_cq = true;
337
338 spin_unlock_bh(&adapter->mcc_cq_lock);
339 }
340
341 void be_async_mcc_disable(struct be_adapter *adapter)
342 {
343 spin_lock_bh(&adapter->mcc_cq_lock);
344
345 adapter->mcc_obj.rearm_cq = false;
346 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
347
348 spin_unlock_bh(&adapter->mcc_cq_lock);
349 }
350
351 int be_process_mcc(struct be_adapter *adapter)
352 {
353 struct be_mcc_compl *compl;
354 int num = 0, status = 0;
355 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
356
357 spin_lock(&adapter->mcc_cq_lock);
358 while ((compl = be_mcc_compl_get(adapter))) {
359 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
360 /* Interpret flags as an async trailer */
361 if (is_link_state_evt(compl->flags))
362 be_async_link_state_process(adapter,
363 (struct be_async_event_link_state *) compl);
364 else if (is_grp5_evt(compl->flags))
365 be_async_grp5_evt_process(adapter,
366 compl->flags, compl);
367 else if (is_dbg_evt(compl->flags))
368 be_async_dbg_evt_process(adapter,
369 compl->flags, compl);
370 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
371 status = be_mcc_compl_process(adapter, compl);
372 atomic_dec(&mcc_obj->q.used);
373 }
374 be_mcc_compl_use(compl);
375 num++;
376 }
377
378 if (num)
379 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
380
381 spin_unlock(&adapter->mcc_cq_lock);
382 return status;
383 }
384
385 /* Wait till no more pending mcc requests are present */
386 static int be_mcc_wait_compl(struct be_adapter *adapter)
387 {
388 #define mcc_timeout 120000 /* 12s timeout */
389 int i, status = 0;
390 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
391
392 for (i = 0; i < mcc_timeout; i++) {
393 if (be_error(adapter))
394 return -EIO;
395
396 local_bh_disable();
397 status = be_process_mcc(adapter);
398 local_bh_enable();
399
400 if (atomic_read(&mcc_obj->q.used) == 0)
401 break;
402 udelay(100);
403 }
404 if (i == mcc_timeout) {
405 dev_err(&adapter->pdev->dev, "FW not responding\n");
406 adapter->fw_timeout = true;
407 return -EIO;
408 }
409 return status;
410 }
411
412 /* Notify MCC requests and wait for completion */
413 static int be_mcc_notify_wait(struct be_adapter *adapter)
414 {
415 int status;
416 struct be_mcc_wrb *wrb;
417 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
418 u16 index = mcc_obj->q.head;
419 struct be_cmd_resp_hdr *resp;
420
421 index_dec(&index, mcc_obj->q.len);
422 wrb = queue_index_node(&mcc_obj->q, index);
423
424 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
425
426 be_mcc_notify(adapter);
427
428 status = be_mcc_wait_compl(adapter);
429 if (status == -EIO)
430 goto out;
431
432 status = resp->status;
433 out:
434 return status;
435 }
436
437 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
438 {
439 int msecs = 0;
440 u32 ready;
441
442 do {
443 if (be_error(adapter))
444 return -EIO;
445
446 ready = ioread32(db);
447 if (ready == 0xffffffff)
448 return -1;
449
450 ready &= MPU_MAILBOX_DB_RDY_MASK;
451 if (ready)
452 break;
453
454 if (msecs > 4000) {
455 dev_err(&adapter->pdev->dev, "FW not responding\n");
456 adapter->fw_timeout = true;
457 be_detect_error(adapter);
458 return -1;
459 }
460
461 msleep(1);
462 msecs++;
463 } while (true);
464
465 return 0;
466 }
467
468 /*
469 * Insert the mailbox address into the doorbell in two steps
470 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
471 */
472 static int be_mbox_notify_wait(struct be_adapter *adapter)
473 {
474 int status;
475 u32 val = 0;
476 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
477 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
478 struct be_mcc_mailbox *mbox = mbox_mem->va;
479 struct be_mcc_compl *compl = &mbox->compl;
480
481 /* wait for ready to be set */
482 status = be_mbox_db_ready_wait(adapter, db);
483 if (status != 0)
484 return status;
485
486 val |= MPU_MAILBOX_DB_HI_MASK;
487 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
488 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
489 iowrite32(val, db);
490
491 /* wait for ready to be set */
492 status = be_mbox_db_ready_wait(adapter, db);
493 if (status != 0)
494 return status;
495
496 val = 0;
497 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
498 val |= (u32)(mbox_mem->dma >> 4) << 2;
499 iowrite32(val, db);
500
501 status = be_mbox_db_ready_wait(adapter, db);
502 if (status != 0)
503 return status;
504
505 /* A cq entry has been made now */
506 if (be_mcc_compl_is_new(compl)) {
507 status = be_mcc_compl_process(adapter, &mbox->compl);
508 be_mcc_compl_use(compl);
509 if (status)
510 return status;
511 } else {
512 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
513 return -1;
514 }
515 return 0;
516 }
517
518 static u16 be_POST_stage_get(struct be_adapter *adapter)
519 {
520 u32 sem;
521
522 if (BEx_chip(adapter))
523 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
524 else
525 pci_read_config_dword(adapter->pdev,
526 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
527
528 return sem & POST_STAGE_MASK;
529 }
530
531 static int lancer_wait_ready(struct be_adapter *adapter)
532 {
533 #define SLIPORT_READY_TIMEOUT 30
534 u32 sliport_status;
535 int status = 0, i;
536
537 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
538 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
539 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
540 break;
541
542 msleep(1000);
543 }
544
545 if (i == SLIPORT_READY_TIMEOUT)
546 status = -1;
547
548 return status;
549 }
550
551 static bool lancer_provisioning_error(struct be_adapter *adapter)
552 {
553 u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
554 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
555 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
556 sliport_err1 = ioread32(adapter->db +
557 SLIPORT_ERROR1_OFFSET);
558 sliport_err2 = ioread32(adapter->db +
559 SLIPORT_ERROR2_OFFSET);
560
561 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
562 sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
563 return true;
564 }
565 return false;
566 }
567
568 int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
569 {
570 int status;
571 u32 sliport_status, err, reset_needed;
572 bool resource_error;
573
574 resource_error = lancer_provisioning_error(adapter);
575 if (resource_error)
576 return -EAGAIN;
577
578 status = lancer_wait_ready(adapter);
579 if (!status) {
580 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
581 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
582 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
583 if (err && reset_needed) {
584 iowrite32(SLI_PORT_CONTROL_IP_MASK,
585 adapter->db + SLIPORT_CONTROL_OFFSET);
586
587 /* check adapter has corrected the error */
588 status = lancer_wait_ready(adapter);
589 sliport_status = ioread32(adapter->db +
590 SLIPORT_STATUS_OFFSET);
591 sliport_status &= (SLIPORT_STATUS_ERR_MASK |
592 SLIPORT_STATUS_RN_MASK);
593 if (status || sliport_status)
594 status = -1;
595 } else if (err || reset_needed) {
596 status = -1;
597 }
598 }
599 /* Stop error recovery if error is not recoverable.
600 * No resource error is temporary errors and will go away
601 * when PF provisions resources.
602 */
603 resource_error = lancer_provisioning_error(adapter);
604 if (resource_error)
605 status = -EAGAIN;
606
607 return status;
608 }
609
610 int be_fw_wait_ready(struct be_adapter *adapter)
611 {
612 u16 stage;
613 int status, timeout = 0;
614 struct device *dev = &adapter->pdev->dev;
615
616 if (lancer_chip(adapter)) {
617 status = lancer_wait_ready(adapter);
618 return status;
619 }
620
621 do {
622 stage = be_POST_stage_get(adapter);
623 if (stage == POST_STAGE_ARMFW_RDY)
624 return 0;
625
626 dev_info(dev, "Waiting for POST, %ds elapsed\n",
627 timeout);
628 if (msleep_interruptible(2000)) {
629 dev_err(dev, "Waiting for POST aborted\n");
630 return -EINTR;
631 }
632 timeout += 2;
633 } while (timeout < 60);
634
635 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
636 return -1;
637 }
638
639
640 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
641 {
642 return &wrb->payload.sgl[0];
643 }
644
645 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb,
646 unsigned long addr)
647 {
648 wrb->tag0 = addr & 0xFFFFFFFF;
649 wrb->tag1 = upper_32_bits(addr);
650 }
651
652 /* Don't touch the hdr after it's prepared */
653 /* mem will be NULL for embedded commands */
654 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
655 u8 subsystem, u8 opcode, int cmd_len,
656 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
657 {
658 struct be_sge *sge;
659
660 req_hdr->opcode = opcode;
661 req_hdr->subsystem = subsystem;
662 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
663 req_hdr->version = 0;
664 fill_wrb_tags(wrb, (ulong) req_hdr);
665 wrb->payload_length = cmd_len;
666 if (mem) {
667 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
668 MCC_WRB_SGE_CNT_SHIFT;
669 sge = nonembedded_sgl(wrb);
670 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
671 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
672 sge->len = cpu_to_le32(mem->size);
673 } else
674 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
675 be_dws_cpu_to_le(wrb, 8);
676 }
677
678 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
679 struct be_dma_mem *mem)
680 {
681 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
682 u64 dma = (u64)mem->dma;
683
684 for (i = 0; i < buf_pages; i++) {
685 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
686 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
687 dma += PAGE_SIZE_4K;
688 }
689 }
690
691 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
692 {
693 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
694 struct be_mcc_wrb *wrb
695 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
696 memset(wrb, 0, sizeof(*wrb));
697 return wrb;
698 }
699
700 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
701 {
702 struct be_queue_info *mccq = &adapter->mcc_obj.q;
703 struct be_mcc_wrb *wrb;
704
705 if (!mccq->created)
706 return NULL;
707
708 if (atomic_read(&mccq->used) >= mccq->len)
709 return NULL;
710
711 wrb = queue_head_node(mccq);
712 queue_head_inc(mccq);
713 atomic_inc(&mccq->used);
714 memset(wrb, 0, sizeof(*wrb));
715 return wrb;
716 }
717
718 static bool use_mcc(struct be_adapter *adapter)
719 {
720 return adapter->mcc_obj.q.created;
721 }
722
723 /* Must be used only in process context */
724 static int be_cmd_lock(struct be_adapter *adapter)
725 {
726 if (use_mcc(adapter)) {
727 spin_lock_bh(&adapter->mcc_lock);
728 return 0;
729 } else {
730 return mutex_lock_interruptible(&adapter->mbox_lock);
731 }
732 }
733
734 /* Must be used only in process context */
735 static void be_cmd_unlock(struct be_adapter *adapter)
736 {
737 if (use_mcc(adapter))
738 spin_unlock_bh(&adapter->mcc_lock);
739 else
740 return mutex_unlock(&adapter->mbox_lock);
741 }
742
743 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
744 struct be_mcc_wrb *wrb)
745 {
746 struct be_mcc_wrb *dest_wrb;
747
748 if (use_mcc(adapter)) {
749 dest_wrb = wrb_from_mccq(adapter);
750 if (!dest_wrb)
751 return NULL;
752 } else {
753 dest_wrb = wrb_from_mbox(adapter);
754 }
755
756 memcpy(dest_wrb, wrb, sizeof(*wrb));
757 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
758 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
759
760 return dest_wrb;
761 }
762
763 /* Must be used only in process context */
764 static int be_cmd_notify_wait(struct be_adapter *adapter,
765 struct be_mcc_wrb *wrb)
766 {
767 struct be_mcc_wrb *dest_wrb;
768 int status;
769
770 status = be_cmd_lock(adapter);
771 if (status)
772 return status;
773
774 dest_wrb = be_cmd_copy(adapter, wrb);
775 if (!dest_wrb)
776 return -EBUSY;
777
778 if (use_mcc(adapter))
779 status = be_mcc_notify_wait(adapter);
780 else
781 status = be_mbox_notify_wait(adapter);
782
783 if (!status)
784 memcpy(wrb, dest_wrb, sizeof(*wrb));
785
786 be_cmd_unlock(adapter);
787 return status;
788 }
789
790 /* Tell fw we're about to start firing cmds by writing a
791 * special pattern across the wrb hdr; uses mbox
792 */
793 int be_cmd_fw_init(struct be_adapter *adapter)
794 {
795 u8 *wrb;
796 int status;
797
798 if (lancer_chip(adapter))
799 return 0;
800
801 if (mutex_lock_interruptible(&adapter->mbox_lock))
802 return -1;
803
804 wrb = (u8 *)wrb_from_mbox(adapter);
805 *wrb++ = 0xFF;
806 *wrb++ = 0x12;
807 *wrb++ = 0x34;
808 *wrb++ = 0xFF;
809 *wrb++ = 0xFF;
810 *wrb++ = 0x56;
811 *wrb++ = 0x78;
812 *wrb = 0xFF;
813
814 status = be_mbox_notify_wait(adapter);
815
816 mutex_unlock(&adapter->mbox_lock);
817 return status;
818 }
819
820 /* Tell fw we're done with firing cmds by writing a
821 * special pattern across the wrb hdr; uses mbox
822 */
823 int be_cmd_fw_clean(struct be_adapter *adapter)
824 {
825 u8 *wrb;
826 int status;
827
828 if (lancer_chip(adapter))
829 return 0;
830
831 if (mutex_lock_interruptible(&adapter->mbox_lock))
832 return -1;
833
834 wrb = (u8 *)wrb_from_mbox(adapter);
835 *wrb++ = 0xFF;
836 *wrb++ = 0xAA;
837 *wrb++ = 0xBB;
838 *wrb++ = 0xFF;
839 *wrb++ = 0xFF;
840 *wrb++ = 0xCC;
841 *wrb++ = 0xDD;
842 *wrb = 0xFF;
843
844 status = be_mbox_notify_wait(adapter);
845
846 mutex_unlock(&adapter->mbox_lock);
847 return status;
848 }
849
850 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
851 {
852 struct be_mcc_wrb *wrb;
853 struct be_cmd_req_eq_create *req;
854 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
855 int status, ver = 0;
856
857 if (mutex_lock_interruptible(&adapter->mbox_lock))
858 return -1;
859
860 wrb = wrb_from_mbox(adapter);
861 req = embedded_payload(wrb);
862
863 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
864 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
865
866 /* Support for EQ_CREATEv2 available only SH-R onwards */
867 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
868 ver = 2;
869
870 req->hdr.version = ver;
871 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
872
873 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
874 /* 4byte eqe*/
875 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
876 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
877 __ilog2_u32(eqo->q.len / 256));
878 be_dws_cpu_to_le(req->context, sizeof(req->context));
879
880 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
881
882 status = be_mbox_notify_wait(adapter);
883 if (!status) {
884 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
885 eqo->q.id = le16_to_cpu(resp->eq_id);
886 eqo->msix_idx =
887 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
888 eqo->q.created = true;
889 }
890
891 mutex_unlock(&adapter->mbox_lock);
892 return status;
893 }
894
895 /* Use MCC */
896 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
897 bool permanent, u32 if_handle, u32 pmac_id)
898 {
899 struct be_mcc_wrb *wrb;
900 struct be_cmd_req_mac_query *req;
901 int status;
902
903 spin_lock_bh(&adapter->mcc_lock);
904
905 wrb = wrb_from_mccq(adapter);
906 if (!wrb) {
907 status = -EBUSY;
908 goto err;
909 }
910 req = embedded_payload(wrb);
911
912 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
913 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
914 req->type = MAC_ADDRESS_TYPE_NETWORK;
915 if (permanent) {
916 req->permanent = 1;
917 } else {
918 req->if_id = cpu_to_le16((u16) if_handle);
919 req->pmac_id = cpu_to_le32(pmac_id);
920 req->permanent = 0;
921 }
922
923 status = be_mcc_notify_wait(adapter);
924 if (!status) {
925 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
926 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
927 }
928
929 err:
930 spin_unlock_bh(&adapter->mcc_lock);
931 return status;
932 }
933
934 /* Uses synchronous MCCQ */
935 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
936 u32 if_id, u32 *pmac_id, u32 domain)
937 {
938 struct be_mcc_wrb *wrb;
939 struct be_cmd_req_pmac_add *req;
940 int status;
941
942 spin_lock_bh(&adapter->mcc_lock);
943
944 wrb = wrb_from_mccq(adapter);
945 if (!wrb) {
946 status = -EBUSY;
947 goto err;
948 }
949 req = embedded_payload(wrb);
950
951 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
952 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
953
954 req->hdr.domain = domain;
955 req->if_id = cpu_to_le32(if_id);
956 memcpy(req->mac_address, mac_addr, ETH_ALEN);
957
958 status = be_mcc_notify_wait(adapter);
959 if (!status) {
960 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
961 *pmac_id = le32_to_cpu(resp->pmac_id);
962 }
963
964 err:
965 spin_unlock_bh(&adapter->mcc_lock);
966
967 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
968 status = -EPERM;
969
970 return status;
971 }
972
973 /* Uses synchronous MCCQ */
974 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
975 {
976 struct be_mcc_wrb *wrb;
977 struct be_cmd_req_pmac_del *req;
978 int status;
979
980 if (pmac_id == -1)
981 return 0;
982
983 spin_lock_bh(&adapter->mcc_lock);
984
985 wrb = wrb_from_mccq(adapter);
986 if (!wrb) {
987 status = -EBUSY;
988 goto err;
989 }
990 req = embedded_payload(wrb);
991
992 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
993 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
994
995 req->hdr.domain = dom;
996 req->if_id = cpu_to_le32(if_id);
997 req->pmac_id = cpu_to_le32(pmac_id);
998
999 status = be_mcc_notify_wait(adapter);
1000
1001 err:
1002 spin_unlock_bh(&adapter->mcc_lock);
1003 return status;
1004 }
1005
1006 /* Uses Mbox */
1007 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1008 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1009 {
1010 struct be_mcc_wrb *wrb;
1011 struct be_cmd_req_cq_create *req;
1012 struct be_dma_mem *q_mem = &cq->dma_mem;
1013 void *ctxt;
1014 int status;
1015
1016 if (mutex_lock_interruptible(&adapter->mbox_lock))
1017 return -1;
1018
1019 wrb = wrb_from_mbox(adapter);
1020 req = embedded_payload(wrb);
1021 ctxt = &req->context;
1022
1023 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1024 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
1025
1026 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1027
1028 if (BEx_chip(adapter)) {
1029 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1030 coalesce_wm);
1031 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1032 ctxt, no_delay);
1033 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1034 __ilog2_u32(cq->len/256));
1035 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1036 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1037 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1038 } else {
1039 req->hdr.version = 2;
1040 req->page_size = 1; /* 1 for 4K */
1041
1042 /* coalesce-wm field in this cmd is not relevant to Lancer.
1043 * Lancer uses COMMON_MODIFY_CQ to set this field
1044 */
1045 if (!lancer_chip(adapter))
1046 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1047 ctxt, coalesce_wm);
1048 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1049 no_delay);
1050 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1051 __ilog2_u32(cq->len/256));
1052 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1053 AMAP_SET_BITS(struct amap_cq_context_v2, eventable,
1054 ctxt, 1);
1055 AMAP_SET_BITS(struct amap_cq_context_v2, eqid,
1056 ctxt, eq->id);
1057 }
1058
1059 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1060
1061 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1062
1063 status = be_mbox_notify_wait(adapter);
1064 if (!status) {
1065 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1066 cq->id = le16_to_cpu(resp->cq_id);
1067 cq->created = true;
1068 }
1069
1070 mutex_unlock(&adapter->mbox_lock);
1071
1072 return status;
1073 }
1074
1075 static u32 be_encoded_q_len(int q_len)
1076 {
1077 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1078 if (len_encoded == 16)
1079 len_encoded = 0;
1080 return len_encoded;
1081 }
1082
1083 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1084 struct be_queue_info *mccq,
1085 struct be_queue_info *cq)
1086 {
1087 struct be_mcc_wrb *wrb;
1088 struct be_cmd_req_mcc_ext_create *req;
1089 struct be_dma_mem *q_mem = &mccq->dma_mem;
1090 void *ctxt;
1091 int status;
1092
1093 if (mutex_lock_interruptible(&adapter->mbox_lock))
1094 return -1;
1095
1096 wrb = wrb_from_mbox(adapter);
1097 req = embedded_payload(wrb);
1098 ctxt = &req->context;
1099
1100 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1101 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
1102
1103 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1104 if (BEx_chip(adapter)) {
1105 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1106 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1107 be_encoded_q_len(mccq->len));
1108 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1109 } else {
1110 req->hdr.version = 1;
1111 req->cq_id = cpu_to_le16(cq->id);
1112
1113 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1114 be_encoded_q_len(mccq->len));
1115 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1116 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1117 ctxt, cq->id);
1118 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1119 ctxt, 1);
1120 }
1121
1122 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
1123 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
1124 req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ);
1125 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1126
1127 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1128
1129 status = be_mbox_notify_wait(adapter);
1130 if (!status) {
1131 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1132 mccq->id = le16_to_cpu(resp->id);
1133 mccq->created = true;
1134 }
1135 mutex_unlock(&adapter->mbox_lock);
1136
1137 return status;
1138 }
1139
1140 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1141 struct be_queue_info *mccq,
1142 struct be_queue_info *cq)
1143 {
1144 struct be_mcc_wrb *wrb;
1145 struct be_cmd_req_mcc_create *req;
1146 struct be_dma_mem *q_mem = &mccq->dma_mem;
1147 void *ctxt;
1148 int status;
1149
1150 if (mutex_lock_interruptible(&adapter->mbox_lock))
1151 return -1;
1152
1153 wrb = wrb_from_mbox(adapter);
1154 req = embedded_payload(wrb);
1155 ctxt = &req->context;
1156
1157 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1158 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
1159
1160 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1161
1162 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1163 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1164 be_encoded_q_len(mccq->len));
1165 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1166
1167 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1168
1169 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1170
1171 status = be_mbox_notify_wait(adapter);
1172 if (!status) {
1173 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1174 mccq->id = le16_to_cpu(resp->id);
1175 mccq->created = true;
1176 }
1177
1178 mutex_unlock(&adapter->mbox_lock);
1179 return status;
1180 }
1181
1182 int be_cmd_mccq_create(struct be_adapter *adapter,
1183 struct be_queue_info *mccq,
1184 struct be_queue_info *cq)
1185 {
1186 int status;
1187
1188 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1189 if (status && BEx_chip(adapter)) {
1190 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1191 "or newer to avoid conflicting priorities between NIC "
1192 "and FCoE traffic");
1193 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1194 }
1195 return status;
1196 }
1197
1198 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1199 {
1200 struct be_mcc_wrb wrb = {0};
1201 struct be_cmd_req_eth_tx_create *req;
1202 struct be_queue_info *txq = &txo->q;
1203 struct be_queue_info *cq = &txo->cq;
1204 struct be_dma_mem *q_mem = &txq->dma_mem;
1205 int status, ver = 0;
1206
1207 req = embedded_payload(&wrb);
1208 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1209 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1210
1211 if (lancer_chip(adapter)) {
1212 req->hdr.version = 1;
1213 } else if (BEx_chip(adapter)) {
1214 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1215 req->hdr.version = 2;
1216 } else { /* For SH */
1217 req->hdr.version = 2;
1218 }
1219
1220 if (req->hdr.version > 0)
1221 req->if_id = cpu_to_le16(adapter->if_handle);
1222 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1223 req->ulp_num = BE_ULP1_NUM;
1224 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1225 req->cq_id = cpu_to_le16(cq->id);
1226 req->queue_size = be_encoded_q_len(txq->len);
1227 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1228 ver = req->hdr.version;
1229
1230 status = be_cmd_notify_wait(adapter, &wrb);
1231 if (!status) {
1232 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1233 txq->id = le16_to_cpu(resp->cid);
1234 if (ver == 2)
1235 txo->db_offset = le32_to_cpu(resp->db_offset);
1236 else
1237 txo->db_offset = DB_TXULP1_OFFSET;
1238 txq->created = true;
1239 }
1240
1241 return status;
1242 }
1243
1244 /* Uses MCC */
1245 int be_cmd_rxq_create(struct be_adapter *adapter,
1246 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1247 u32 if_id, u32 rss, u8 *rss_id)
1248 {
1249 struct be_mcc_wrb *wrb;
1250 struct be_cmd_req_eth_rx_create *req;
1251 struct be_dma_mem *q_mem = &rxq->dma_mem;
1252 int status;
1253
1254 spin_lock_bh(&adapter->mcc_lock);
1255
1256 wrb = wrb_from_mccq(adapter);
1257 if (!wrb) {
1258 status = -EBUSY;
1259 goto err;
1260 }
1261 req = embedded_payload(wrb);
1262
1263 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1264 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1265
1266 req->cq_id = cpu_to_le16(cq_id);
1267 req->frag_size = fls(frag_size) - 1;
1268 req->num_pages = 2;
1269 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1270 req->interface_id = cpu_to_le32(if_id);
1271 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1272 req->rss_queue = cpu_to_le32(rss);
1273
1274 status = be_mcc_notify_wait(adapter);
1275 if (!status) {
1276 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1277 rxq->id = le16_to_cpu(resp->id);
1278 rxq->created = true;
1279 *rss_id = resp->rss_id;
1280 }
1281
1282 err:
1283 spin_unlock_bh(&adapter->mcc_lock);
1284 return status;
1285 }
1286
1287 /* Generic destroyer function for all types of queues
1288 * Uses Mbox
1289 */
1290 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1291 int queue_type)
1292 {
1293 struct be_mcc_wrb *wrb;
1294 struct be_cmd_req_q_destroy *req;
1295 u8 subsys = 0, opcode = 0;
1296 int status;
1297
1298 if (mutex_lock_interruptible(&adapter->mbox_lock))
1299 return -1;
1300
1301 wrb = wrb_from_mbox(adapter);
1302 req = embedded_payload(wrb);
1303
1304 switch (queue_type) {
1305 case QTYPE_EQ:
1306 subsys = CMD_SUBSYSTEM_COMMON;
1307 opcode = OPCODE_COMMON_EQ_DESTROY;
1308 break;
1309 case QTYPE_CQ:
1310 subsys = CMD_SUBSYSTEM_COMMON;
1311 opcode = OPCODE_COMMON_CQ_DESTROY;
1312 break;
1313 case QTYPE_TXQ:
1314 subsys = CMD_SUBSYSTEM_ETH;
1315 opcode = OPCODE_ETH_TX_DESTROY;
1316 break;
1317 case QTYPE_RXQ:
1318 subsys = CMD_SUBSYSTEM_ETH;
1319 opcode = OPCODE_ETH_RX_DESTROY;
1320 break;
1321 case QTYPE_MCCQ:
1322 subsys = CMD_SUBSYSTEM_COMMON;
1323 opcode = OPCODE_COMMON_MCC_DESTROY;
1324 break;
1325 default:
1326 BUG();
1327 }
1328
1329 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1330 NULL);
1331 req->id = cpu_to_le16(q->id);
1332
1333 status = be_mbox_notify_wait(adapter);
1334 q->created = false;
1335
1336 mutex_unlock(&adapter->mbox_lock);
1337 return status;
1338 }
1339
1340 /* Uses MCC */
1341 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1342 {
1343 struct be_mcc_wrb *wrb;
1344 struct be_cmd_req_q_destroy *req;
1345 int status;
1346
1347 spin_lock_bh(&adapter->mcc_lock);
1348
1349 wrb = wrb_from_mccq(adapter);
1350 if (!wrb) {
1351 status = -EBUSY;
1352 goto err;
1353 }
1354 req = embedded_payload(wrb);
1355
1356 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1357 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1358 req->id = cpu_to_le16(q->id);
1359
1360 status = be_mcc_notify_wait(adapter);
1361 q->created = false;
1362
1363 err:
1364 spin_unlock_bh(&adapter->mcc_lock);
1365 return status;
1366 }
1367
1368 /* Create an rx filtering policy configuration on an i/f
1369 * Will use MBOX only if MCCQ has not been created.
1370 */
1371 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1372 u32 *if_handle, u32 domain)
1373 {
1374 struct be_mcc_wrb wrb = {0};
1375 struct be_cmd_req_if_create *req;
1376 int status;
1377
1378 req = embedded_payload(&wrb);
1379 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1380 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), &wrb, NULL);
1381 req->hdr.domain = domain;
1382 req->capability_flags = cpu_to_le32(cap_flags);
1383 req->enable_flags = cpu_to_le32(en_flags);
1384 req->pmac_invalid = true;
1385
1386 status = be_cmd_notify_wait(adapter, &wrb);
1387 if (!status) {
1388 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1389 *if_handle = le32_to_cpu(resp->interface_id);
1390
1391 /* Hack to retrieve VF's pmac-id on BE3 */
1392 if (BE3_chip(adapter) && !be_physfn(adapter))
1393 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1394 }
1395 return status;
1396 }
1397
1398 /* Uses MCCQ */
1399 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1400 {
1401 struct be_mcc_wrb *wrb;
1402 struct be_cmd_req_if_destroy *req;
1403 int status;
1404
1405 if (interface_id == -1)
1406 return 0;
1407
1408 spin_lock_bh(&adapter->mcc_lock);
1409
1410 wrb = wrb_from_mccq(adapter);
1411 if (!wrb) {
1412 status = -EBUSY;
1413 goto err;
1414 }
1415 req = embedded_payload(wrb);
1416
1417 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1418 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1419 req->hdr.domain = domain;
1420 req->interface_id = cpu_to_le32(interface_id);
1421
1422 status = be_mcc_notify_wait(adapter);
1423 err:
1424 spin_unlock_bh(&adapter->mcc_lock);
1425 return status;
1426 }
1427
1428 /* Get stats is a non embedded command: the request is not embedded inside
1429 * WRB but is a separate dma memory block
1430 * Uses asynchronous MCC
1431 */
1432 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1433 {
1434 struct be_mcc_wrb *wrb;
1435 struct be_cmd_req_hdr *hdr;
1436 int status = 0;
1437
1438 spin_lock_bh(&adapter->mcc_lock);
1439
1440 wrb = wrb_from_mccq(adapter);
1441 if (!wrb) {
1442 status = -EBUSY;
1443 goto err;
1444 }
1445 hdr = nonemb_cmd->va;
1446
1447 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1448 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1449
1450 /* version 1 of the cmd is not supported only by BE2 */
1451 if (BE2_chip(adapter))
1452 hdr->version = 0;
1453 if (BE3_chip(adapter) || lancer_chip(adapter))
1454 hdr->version = 1;
1455 else
1456 hdr->version = 2;
1457
1458 be_mcc_notify(adapter);
1459 adapter->stats_cmd_sent = true;
1460
1461 err:
1462 spin_unlock_bh(&adapter->mcc_lock);
1463 return status;
1464 }
1465
1466 /* Lancer Stats */
1467 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1468 struct be_dma_mem *nonemb_cmd)
1469 {
1470
1471 struct be_mcc_wrb *wrb;
1472 struct lancer_cmd_req_pport_stats *req;
1473 int status = 0;
1474
1475 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1476 CMD_SUBSYSTEM_ETH))
1477 return -EPERM;
1478
1479 spin_lock_bh(&adapter->mcc_lock);
1480
1481 wrb = wrb_from_mccq(adapter);
1482 if (!wrb) {
1483 status = -EBUSY;
1484 goto err;
1485 }
1486 req = nonemb_cmd->va;
1487
1488 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1489 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1490 nonemb_cmd);
1491
1492 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1493 req->cmd_params.params.reset_stats = 0;
1494
1495 be_mcc_notify(adapter);
1496 adapter->stats_cmd_sent = true;
1497
1498 err:
1499 spin_unlock_bh(&adapter->mcc_lock);
1500 return status;
1501 }
1502
1503 static int be_mac_to_link_speed(int mac_speed)
1504 {
1505 switch (mac_speed) {
1506 case PHY_LINK_SPEED_ZERO:
1507 return 0;
1508 case PHY_LINK_SPEED_10MBPS:
1509 return 10;
1510 case PHY_LINK_SPEED_100MBPS:
1511 return 100;
1512 case PHY_LINK_SPEED_1GBPS:
1513 return 1000;
1514 case PHY_LINK_SPEED_10GBPS:
1515 return 10000;
1516 case PHY_LINK_SPEED_20GBPS:
1517 return 20000;
1518 case PHY_LINK_SPEED_25GBPS:
1519 return 25000;
1520 case PHY_LINK_SPEED_40GBPS:
1521 return 40000;
1522 }
1523 return 0;
1524 }
1525
1526 /* Uses synchronous mcc
1527 * Returns link_speed in Mbps
1528 */
1529 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1530 u8 *link_status, u32 dom)
1531 {
1532 struct be_mcc_wrb *wrb;
1533 struct be_cmd_req_link_status *req;
1534 int status;
1535
1536 spin_lock_bh(&adapter->mcc_lock);
1537
1538 if (link_status)
1539 *link_status = LINK_DOWN;
1540
1541 wrb = wrb_from_mccq(adapter);
1542 if (!wrb) {
1543 status = -EBUSY;
1544 goto err;
1545 }
1546 req = embedded_payload(wrb);
1547
1548 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1549 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1550
1551 /* version 1 of the cmd is not supported only by BE2 */
1552 if (!BE2_chip(adapter))
1553 req->hdr.version = 1;
1554
1555 req->hdr.domain = dom;
1556
1557 status = be_mcc_notify_wait(adapter);
1558 if (!status) {
1559 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1560 if (link_speed) {
1561 *link_speed = resp->link_speed ?
1562 le16_to_cpu(resp->link_speed) * 10 :
1563 be_mac_to_link_speed(resp->mac_speed);
1564
1565 if (!resp->logical_link_status)
1566 *link_speed = 0;
1567 }
1568 if (link_status)
1569 *link_status = resp->logical_link_status;
1570 }
1571
1572 err:
1573 spin_unlock_bh(&adapter->mcc_lock);
1574 return status;
1575 }
1576
1577 /* Uses synchronous mcc */
1578 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1579 {
1580 struct be_mcc_wrb *wrb;
1581 struct be_cmd_req_get_cntl_addnl_attribs *req;
1582 int status = 0;
1583
1584 spin_lock_bh(&adapter->mcc_lock);
1585
1586 wrb = wrb_from_mccq(adapter);
1587 if (!wrb) {
1588 status = -EBUSY;
1589 goto err;
1590 }
1591 req = embedded_payload(wrb);
1592
1593 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1594 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1595 wrb, NULL);
1596
1597 be_mcc_notify(adapter);
1598
1599 err:
1600 spin_unlock_bh(&adapter->mcc_lock);
1601 return status;
1602 }
1603
1604 /* Uses synchronous mcc */
1605 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1606 {
1607 struct be_mcc_wrb *wrb;
1608 struct be_cmd_req_get_fat *req;
1609 int status;
1610
1611 spin_lock_bh(&adapter->mcc_lock);
1612
1613 wrb = wrb_from_mccq(adapter);
1614 if (!wrb) {
1615 status = -EBUSY;
1616 goto err;
1617 }
1618 req = embedded_payload(wrb);
1619
1620 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1621 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1622 req->fat_operation = cpu_to_le32(QUERY_FAT);
1623 status = be_mcc_notify_wait(adapter);
1624 if (!status) {
1625 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1626 if (log_size && resp->log_size)
1627 *log_size = le32_to_cpu(resp->log_size) -
1628 sizeof(u32);
1629 }
1630 err:
1631 spin_unlock_bh(&adapter->mcc_lock);
1632 return status;
1633 }
1634
1635 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1636 {
1637 struct be_dma_mem get_fat_cmd;
1638 struct be_mcc_wrb *wrb;
1639 struct be_cmd_req_get_fat *req;
1640 u32 offset = 0, total_size, buf_size,
1641 log_offset = sizeof(u32), payload_len;
1642 int status;
1643
1644 if (buf_len == 0)
1645 return;
1646
1647 total_size = buf_len;
1648
1649 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1650 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1651 get_fat_cmd.size,
1652 &get_fat_cmd.dma);
1653 if (!get_fat_cmd.va) {
1654 status = -ENOMEM;
1655 dev_err(&adapter->pdev->dev,
1656 "Memory allocation failure while retrieving FAT data\n");
1657 return;
1658 }
1659
1660 spin_lock_bh(&adapter->mcc_lock);
1661
1662 while (total_size) {
1663 buf_size = min(total_size, (u32)60*1024);
1664 total_size -= buf_size;
1665
1666 wrb = wrb_from_mccq(adapter);
1667 if (!wrb) {
1668 status = -EBUSY;
1669 goto err;
1670 }
1671 req = get_fat_cmd.va;
1672
1673 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1674 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1675 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1676 &get_fat_cmd);
1677
1678 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1679 req->read_log_offset = cpu_to_le32(log_offset);
1680 req->read_log_length = cpu_to_le32(buf_size);
1681 req->data_buffer_size = cpu_to_le32(buf_size);
1682
1683 status = be_mcc_notify_wait(adapter);
1684 if (!status) {
1685 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1686 memcpy(buf + offset,
1687 resp->data_buffer,
1688 le32_to_cpu(resp->read_log_length));
1689 } else {
1690 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1691 goto err;
1692 }
1693 offset += buf_size;
1694 log_offset += buf_size;
1695 }
1696 err:
1697 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1698 get_fat_cmd.va,
1699 get_fat_cmd.dma);
1700 spin_unlock_bh(&adapter->mcc_lock);
1701 }
1702
1703 /* Uses synchronous mcc */
1704 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1705 char *fw_on_flash)
1706 {
1707 struct be_mcc_wrb *wrb;
1708 struct be_cmd_req_get_fw_version *req;
1709 int status;
1710
1711 spin_lock_bh(&adapter->mcc_lock);
1712
1713 wrb = wrb_from_mccq(adapter);
1714 if (!wrb) {
1715 status = -EBUSY;
1716 goto err;
1717 }
1718
1719 req = embedded_payload(wrb);
1720
1721 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1722 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1723 status = be_mcc_notify_wait(adapter);
1724 if (!status) {
1725 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1726 strcpy(fw_ver, resp->firmware_version_string);
1727 if (fw_on_flash)
1728 strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1729 }
1730 err:
1731 spin_unlock_bh(&adapter->mcc_lock);
1732 return status;
1733 }
1734
1735 /* set the EQ delay interval of an EQ to specified value
1736 * Uses async mcc
1737 */
1738 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1739 int num)
1740 {
1741 struct be_mcc_wrb *wrb;
1742 struct be_cmd_req_modify_eq_delay *req;
1743 int status = 0, i;
1744
1745 spin_lock_bh(&adapter->mcc_lock);
1746
1747 wrb = wrb_from_mccq(adapter);
1748 if (!wrb) {
1749 status = -EBUSY;
1750 goto err;
1751 }
1752 req = embedded_payload(wrb);
1753
1754 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1755 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1756
1757 req->num_eq = cpu_to_le32(num);
1758 for (i = 0; i < num; i++) {
1759 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1760 req->set_eqd[i].phase = 0;
1761 req->set_eqd[i].delay_multiplier =
1762 cpu_to_le32(set_eqd[i].delay_multiplier);
1763 }
1764
1765 be_mcc_notify(adapter);
1766 err:
1767 spin_unlock_bh(&adapter->mcc_lock);
1768 return status;
1769 }
1770
1771 /* Uses sycnhronous mcc */
1772 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1773 u32 num, bool promiscuous)
1774 {
1775 struct be_mcc_wrb *wrb;
1776 struct be_cmd_req_vlan_config *req;
1777 int status;
1778
1779 spin_lock_bh(&adapter->mcc_lock);
1780
1781 wrb = wrb_from_mccq(adapter);
1782 if (!wrb) {
1783 status = -EBUSY;
1784 goto err;
1785 }
1786 req = embedded_payload(wrb);
1787
1788 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1789 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1790
1791 req->interface_id = if_id;
1792 req->promiscuous = promiscuous;
1793 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
1794 req->num_vlan = num;
1795 if (!promiscuous) {
1796 memcpy(req->normal_vlan, vtag_array,
1797 req->num_vlan * sizeof(vtag_array[0]));
1798 }
1799
1800 status = be_mcc_notify_wait(adapter);
1801
1802 err:
1803 spin_unlock_bh(&adapter->mcc_lock);
1804 return status;
1805 }
1806
1807 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1808 {
1809 struct be_mcc_wrb *wrb;
1810 struct be_dma_mem *mem = &adapter->rx_filter;
1811 struct be_cmd_req_rx_filter *req = mem->va;
1812 int status;
1813
1814 spin_lock_bh(&adapter->mcc_lock);
1815
1816 wrb = wrb_from_mccq(adapter);
1817 if (!wrb) {
1818 status = -EBUSY;
1819 goto err;
1820 }
1821 memset(req, 0, sizeof(*req));
1822 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1823 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1824 wrb, mem);
1825
1826 req->if_id = cpu_to_le32(adapter->if_handle);
1827 if (flags & IFF_PROMISC) {
1828 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1829 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1830 BE_IF_FLAGS_MCAST_PROMISCUOUS);
1831 if (value == ON)
1832 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1833 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1834 BE_IF_FLAGS_MCAST_PROMISCUOUS);
1835 } else if (flags & IFF_ALLMULTI) {
1836 req->if_flags_mask = req->if_flags =
1837 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1838 } else if (flags & BE_FLAGS_VLAN_PROMISC) {
1839 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS);
1840
1841 if (value == ON)
1842 req->if_flags =
1843 cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS);
1844 } else {
1845 struct netdev_hw_addr *ha;
1846 int i = 0;
1847
1848 req->if_flags_mask = req->if_flags =
1849 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1850
1851 /* Reset mcast promisc mode if already set by setting mask
1852 * and not setting flags field
1853 */
1854 req->if_flags_mask |=
1855 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1856 be_if_cap_flags(adapter));
1857 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1858 netdev_for_each_mc_addr(ha, adapter->netdev)
1859 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1860 }
1861
1862 if ((req->if_flags_mask & cpu_to_le32(be_if_cap_flags(adapter))) !=
1863 req->if_flags_mask) {
1864 dev_warn(&adapter->pdev->dev,
1865 "Cannot set rx filter flags 0x%x\n",
1866 req->if_flags_mask);
1867 dev_warn(&adapter->pdev->dev,
1868 "Interface is capable of 0x%x flags only\n",
1869 be_if_cap_flags(adapter));
1870 }
1871 req->if_flags_mask &= cpu_to_le32(be_if_cap_flags(adapter));
1872
1873 status = be_mcc_notify_wait(adapter);
1874
1875 err:
1876 spin_unlock_bh(&adapter->mcc_lock);
1877 return status;
1878 }
1879
1880 /* Uses synchrounous mcc */
1881 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1882 {
1883 struct be_mcc_wrb *wrb;
1884 struct be_cmd_req_set_flow_control *req;
1885 int status;
1886
1887 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1888 CMD_SUBSYSTEM_COMMON))
1889 return -EPERM;
1890
1891 spin_lock_bh(&adapter->mcc_lock);
1892
1893 wrb = wrb_from_mccq(adapter);
1894 if (!wrb) {
1895 status = -EBUSY;
1896 goto err;
1897 }
1898 req = embedded_payload(wrb);
1899
1900 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1901 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1902
1903 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1904 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1905
1906 status = be_mcc_notify_wait(adapter);
1907
1908 err:
1909 spin_unlock_bh(&adapter->mcc_lock);
1910 return status;
1911 }
1912
1913 /* Uses sycn mcc */
1914 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1915 {
1916 struct be_mcc_wrb *wrb;
1917 struct be_cmd_req_get_flow_control *req;
1918 int status;
1919
1920 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
1921 CMD_SUBSYSTEM_COMMON))
1922 return -EPERM;
1923
1924 spin_lock_bh(&adapter->mcc_lock);
1925
1926 wrb = wrb_from_mccq(adapter);
1927 if (!wrb) {
1928 status = -EBUSY;
1929 goto err;
1930 }
1931 req = embedded_payload(wrb);
1932
1933 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1934 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1935
1936 status = be_mcc_notify_wait(adapter);
1937 if (!status) {
1938 struct be_cmd_resp_get_flow_control *resp =
1939 embedded_payload(wrb);
1940 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1941 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1942 }
1943
1944 err:
1945 spin_unlock_bh(&adapter->mcc_lock);
1946 return status;
1947 }
1948
1949 /* Uses mbox */
1950 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1951 u32 *mode, u32 *caps, u16 *asic_rev)
1952 {
1953 struct be_mcc_wrb *wrb;
1954 struct be_cmd_req_query_fw_cfg *req;
1955 int status;
1956
1957 if (mutex_lock_interruptible(&adapter->mbox_lock))
1958 return -1;
1959
1960 wrb = wrb_from_mbox(adapter);
1961 req = embedded_payload(wrb);
1962
1963 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1964 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1965
1966 status = be_mbox_notify_wait(adapter);
1967 if (!status) {
1968 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1969 *port_num = le32_to_cpu(resp->phys_port);
1970 *mode = le32_to_cpu(resp->function_mode);
1971 *caps = le32_to_cpu(resp->function_caps);
1972 *asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
1973 }
1974
1975 mutex_unlock(&adapter->mbox_lock);
1976 return status;
1977 }
1978
1979 /* Uses mbox */
1980 int be_cmd_reset_function(struct be_adapter *adapter)
1981 {
1982 struct be_mcc_wrb *wrb;
1983 struct be_cmd_req_hdr *req;
1984 int status;
1985
1986 if (lancer_chip(adapter)) {
1987 status = lancer_wait_ready(adapter);
1988 if (!status) {
1989 iowrite32(SLI_PORT_CONTROL_IP_MASK,
1990 adapter->db + SLIPORT_CONTROL_OFFSET);
1991 status = lancer_test_and_set_rdy_state(adapter);
1992 }
1993 if (status) {
1994 dev_err(&adapter->pdev->dev,
1995 "Adapter in non recoverable error\n");
1996 }
1997 return status;
1998 }
1999
2000 if (mutex_lock_interruptible(&adapter->mbox_lock))
2001 return -1;
2002
2003 wrb = wrb_from_mbox(adapter);
2004 req = embedded_payload(wrb);
2005
2006 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2007 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
2008
2009 status = be_mbox_notify_wait(adapter);
2010
2011 mutex_unlock(&adapter->mbox_lock);
2012 return status;
2013 }
2014
2015 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2016 u32 rss_hash_opts, u16 table_size)
2017 {
2018 struct be_mcc_wrb *wrb;
2019 struct be_cmd_req_rss_config *req;
2020 u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
2021 0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
2022 0x3ea83c02, 0x4a110304};
2023 int status;
2024
2025 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2026 return 0;
2027
2028 if (mutex_lock_interruptible(&adapter->mbox_lock))
2029 return -1;
2030
2031 wrb = wrb_from_mbox(adapter);
2032 req = embedded_payload(wrb);
2033
2034 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2035 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2036
2037 req->if_id = cpu_to_le32(adapter->if_handle);
2038 req->enable_rss = cpu_to_le16(rss_hash_opts);
2039 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2040
2041 if (lancer_chip(adapter) || skyhawk_chip(adapter))
2042 req->hdr.version = 1;
2043
2044 memcpy(req->cpu_table, rsstable, table_size);
2045 memcpy(req->hash, myhash, sizeof(myhash));
2046 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2047
2048 status = be_mbox_notify_wait(adapter);
2049
2050 mutex_unlock(&adapter->mbox_lock);
2051 return status;
2052 }
2053
2054 /* Uses sync mcc */
2055 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2056 u8 bcn, u8 sts, u8 state)
2057 {
2058 struct be_mcc_wrb *wrb;
2059 struct be_cmd_req_enable_disable_beacon *req;
2060 int status;
2061
2062 spin_lock_bh(&adapter->mcc_lock);
2063
2064 wrb = wrb_from_mccq(adapter);
2065 if (!wrb) {
2066 status = -EBUSY;
2067 goto err;
2068 }
2069 req = embedded_payload(wrb);
2070
2071 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2072 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
2073
2074 req->port_num = port_num;
2075 req->beacon_state = state;
2076 req->beacon_duration = bcn;
2077 req->status_duration = sts;
2078
2079 status = be_mcc_notify_wait(adapter);
2080
2081 err:
2082 spin_unlock_bh(&adapter->mcc_lock);
2083 return status;
2084 }
2085
2086 /* Uses sync mcc */
2087 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2088 {
2089 struct be_mcc_wrb *wrb;
2090 struct be_cmd_req_get_beacon_state *req;
2091 int status;
2092
2093 spin_lock_bh(&adapter->mcc_lock);
2094
2095 wrb = wrb_from_mccq(adapter);
2096 if (!wrb) {
2097 status = -EBUSY;
2098 goto err;
2099 }
2100 req = embedded_payload(wrb);
2101
2102 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2103 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
2104
2105 req->port_num = port_num;
2106
2107 status = be_mcc_notify_wait(adapter);
2108 if (!status) {
2109 struct be_cmd_resp_get_beacon_state *resp =
2110 embedded_payload(wrb);
2111 *state = resp->beacon_state;
2112 }
2113
2114 err:
2115 spin_unlock_bh(&adapter->mcc_lock);
2116 return status;
2117 }
2118
2119 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2120 u32 data_size, u32 data_offset,
2121 const char *obj_name, u32 *data_written,
2122 u8 *change_status, u8 *addn_status)
2123 {
2124 struct be_mcc_wrb *wrb;
2125 struct lancer_cmd_req_write_object *req;
2126 struct lancer_cmd_resp_write_object *resp;
2127 void *ctxt = NULL;
2128 int status;
2129
2130 spin_lock_bh(&adapter->mcc_lock);
2131 adapter->flash_status = 0;
2132
2133 wrb = wrb_from_mccq(adapter);
2134 if (!wrb) {
2135 status = -EBUSY;
2136 goto err_unlock;
2137 }
2138
2139 req = embedded_payload(wrb);
2140
2141 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2142 OPCODE_COMMON_WRITE_OBJECT,
2143 sizeof(struct lancer_cmd_req_write_object), wrb,
2144 NULL);
2145
2146 ctxt = &req->context;
2147 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2148 write_length, ctxt, data_size);
2149
2150 if (data_size == 0)
2151 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2152 eof, ctxt, 1);
2153 else
2154 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2155 eof, ctxt, 0);
2156
2157 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2158 req->write_offset = cpu_to_le32(data_offset);
2159 strcpy(req->object_name, obj_name);
2160 req->descriptor_count = cpu_to_le32(1);
2161 req->buf_len = cpu_to_le32(data_size);
2162 req->addr_low = cpu_to_le32((cmd->dma +
2163 sizeof(struct lancer_cmd_req_write_object))
2164 & 0xFFFFFFFF);
2165 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2166 sizeof(struct lancer_cmd_req_write_object)));
2167
2168 be_mcc_notify(adapter);
2169 spin_unlock_bh(&adapter->mcc_lock);
2170
2171 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2172 msecs_to_jiffies(60000)))
2173 status = -1;
2174 else
2175 status = adapter->flash_status;
2176
2177 resp = embedded_payload(wrb);
2178 if (!status) {
2179 *data_written = le32_to_cpu(resp->actual_write_len);
2180 *change_status = resp->change_status;
2181 } else {
2182 *addn_status = resp->additional_status;
2183 }
2184
2185 return status;
2186
2187 err_unlock:
2188 spin_unlock_bh(&adapter->mcc_lock);
2189 return status;
2190 }
2191
2192 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2193 u32 data_size, u32 data_offset, const char *obj_name,
2194 u32 *data_read, u32 *eof, u8 *addn_status)
2195 {
2196 struct be_mcc_wrb *wrb;
2197 struct lancer_cmd_req_read_object *req;
2198 struct lancer_cmd_resp_read_object *resp;
2199 int status;
2200
2201 spin_lock_bh(&adapter->mcc_lock);
2202
2203 wrb = wrb_from_mccq(adapter);
2204 if (!wrb) {
2205 status = -EBUSY;
2206 goto err_unlock;
2207 }
2208
2209 req = embedded_payload(wrb);
2210
2211 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2212 OPCODE_COMMON_READ_OBJECT,
2213 sizeof(struct lancer_cmd_req_read_object), wrb,
2214 NULL);
2215
2216 req->desired_read_len = cpu_to_le32(data_size);
2217 req->read_offset = cpu_to_le32(data_offset);
2218 strcpy(req->object_name, obj_name);
2219 req->descriptor_count = cpu_to_le32(1);
2220 req->buf_len = cpu_to_le32(data_size);
2221 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2222 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2223
2224 status = be_mcc_notify_wait(adapter);
2225
2226 resp = embedded_payload(wrb);
2227 if (!status) {
2228 *data_read = le32_to_cpu(resp->actual_read_len);
2229 *eof = le32_to_cpu(resp->eof);
2230 } else {
2231 *addn_status = resp->additional_status;
2232 }
2233
2234 err_unlock:
2235 spin_unlock_bh(&adapter->mcc_lock);
2236 return status;
2237 }
2238
2239 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2240 u32 flash_type, u32 flash_opcode, u32 buf_size)
2241 {
2242 struct be_mcc_wrb *wrb;
2243 struct be_cmd_write_flashrom *req;
2244 int status;
2245
2246 spin_lock_bh(&adapter->mcc_lock);
2247 adapter->flash_status = 0;
2248
2249 wrb = wrb_from_mccq(adapter);
2250 if (!wrb) {
2251 status = -EBUSY;
2252 goto err_unlock;
2253 }
2254 req = cmd->va;
2255
2256 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2257 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
2258
2259 req->params.op_type = cpu_to_le32(flash_type);
2260 req->params.op_code = cpu_to_le32(flash_opcode);
2261 req->params.data_buf_size = cpu_to_le32(buf_size);
2262
2263 be_mcc_notify(adapter);
2264 spin_unlock_bh(&adapter->mcc_lock);
2265
2266 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2267 msecs_to_jiffies(40000)))
2268 status = -1;
2269 else
2270 status = adapter->flash_status;
2271
2272 return status;
2273
2274 err_unlock:
2275 spin_unlock_bh(&adapter->mcc_lock);
2276 return status;
2277 }
2278
2279 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2280 int offset)
2281 {
2282 struct be_mcc_wrb *wrb;
2283 struct be_cmd_read_flash_crc *req;
2284 int status;
2285
2286 spin_lock_bh(&adapter->mcc_lock);
2287
2288 wrb = wrb_from_mccq(adapter);
2289 if (!wrb) {
2290 status = -EBUSY;
2291 goto err;
2292 }
2293 req = embedded_payload(wrb);
2294
2295 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2296 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2297 wrb, NULL);
2298
2299 req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
2300 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2301 req->params.offset = cpu_to_le32(offset);
2302 req->params.data_buf_size = cpu_to_le32(0x4);
2303
2304 status = be_mcc_notify_wait(adapter);
2305 if (!status)
2306 memcpy(flashed_crc, req->crc, 4);
2307
2308 err:
2309 spin_unlock_bh(&adapter->mcc_lock);
2310 return status;
2311 }
2312
2313 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2314 struct be_dma_mem *nonemb_cmd)
2315 {
2316 struct be_mcc_wrb *wrb;
2317 struct be_cmd_req_acpi_wol_magic_config *req;
2318 int status;
2319
2320 spin_lock_bh(&adapter->mcc_lock);
2321
2322 wrb = wrb_from_mccq(adapter);
2323 if (!wrb) {
2324 status = -EBUSY;
2325 goto err;
2326 }
2327 req = nonemb_cmd->va;
2328
2329 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2330 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2331 nonemb_cmd);
2332 memcpy(req->magic_mac, mac, ETH_ALEN);
2333
2334 status = be_mcc_notify_wait(adapter);
2335
2336 err:
2337 spin_unlock_bh(&adapter->mcc_lock);
2338 return status;
2339 }
2340
2341 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2342 u8 loopback_type, u8 enable)
2343 {
2344 struct be_mcc_wrb *wrb;
2345 struct be_cmd_req_set_lmode *req;
2346 int status;
2347
2348 spin_lock_bh(&adapter->mcc_lock);
2349
2350 wrb = wrb_from_mccq(adapter);
2351 if (!wrb) {
2352 status = -EBUSY;
2353 goto err;
2354 }
2355
2356 req = embedded_payload(wrb);
2357
2358 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2359 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2360 NULL);
2361
2362 req->src_port = port_num;
2363 req->dest_port = port_num;
2364 req->loopback_type = loopback_type;
2365 req->loopback_state = enable;
2366
2367 status = be_mcc_notify_wait(adapter);
2368 err:
2369 spin_unlock_bh(&adapter->mcc_lock);
2370 return status;
2371 }
2372
2373 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2374 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2375 {
2376 struct be_mcc_wrb *wrb;
2377 struct be_cmd_req_loopback_test *req;
2378 struct be_cmd_resp_loopback_test *resp;
2379 int status;
2380
2381 spin_lock_bh(&adapter->mcc_lock);
2382
2383 wrb = wrb_from_mccq(adapter);
2384 if (!wrb) {
2385 status = -EBUSY;
2386 goto err;
2387 }
2388
2389 req = embedded_payload(wrb);
2390
2391 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2392 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2393
2394 req->hdr.timeout = cpu_to_le32(15);
2395 req->pattern = cpu_to_le64(pattern);
2396 req->src_port = cpu_to_le32(port_num);
2397 req->dest_port = cpu_to_le32(port_num);
2398 req->pkt_size = cpu_to_le32(pkt_size);
2399 req->num_pkts = cpu_to_le32(num_pkts);
2400 req->loopback_type = cpu_to_le32(loopback_type);
2401
2402 be_mcc_notify(adapter);
2403
2404 spin_unlock_bh(&adapter->mcc_lock);
2405
2406 wait_for_completion(&adapter->et_cmd_compl);
2407 resp = embedded_payload(wrb);
2408 status = le32_to_cpu(resp->status);
2409
2410 return status;
2411 err:
2412 spin_unlock_bh(&adapter->mcc_lock);
2413 return status;
2414 }
2415
2416 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2417 u32 byte_cnt, struct be_dma_mem *cmd)
2418 {
2419 struct be_mcc_wrb *wrb;
2420 struct be_cmd_req_ddrdma_test *req;
2421 int status;
2422 int i, j = 0;
2423
2424 spin_lock_bh(&adapter->mcc_lock);
2425
2426 wrb = wrb_from_mccq(adapter);
2427 if (!wrb) {
2428 status = -EBUSY;
2429 goto err;
2430 }
2431 req = cmd->va;
2432 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2433 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2434
2435 req->pattern = cpu_to_le64(pattern);
2436 req->byte_count = cpu_to_le32(byte_cnt);
2437 for (i = 0; i < byte_cnt; i++) {
2438 req->snd_buff[i] = (u8)(pattern >> (j*8));
2439 j++;
2440 if (j > 7)
2441 j = 0;
2442 }
2443
2444 status = be_mcc_notify_wait(adapter);
2445
2446 if (!status) {
2447 struct be_cmd_resp_ddrdma_test *resp;
2448 resp = cmd->va;
2449 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2450 resp->snd_err) {
2451 status = -1;
2452 }
2453 }
2454
2455 err:
2456 spin_unlock_bh(&adapter->mcc_lock);
2457 return status;
2458 }
2459
2460 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2461 struct be_dma_mem *nonemb_cmd)
2462 {
2463 struct be_mcc_wrb *wrb;
2464 struct be_cmd_req_seeprom_read *req;
2465 int status;
2466
2467 spin_lock_bh(&adapter->mcc_lock);
2468
2469 wrb = wrb_from_mccq(adapter);
2470 if (!wrb) {
2471 status = -EBUSY;
2472 goto err;
2473 }
2474 req = nonemb_cmd->va;
2475
2476 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2477 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2478 nonemb_cmd);
2479
2480 status = be_mcc_notify_wait(adapter);
2481
2482 err:
2483 spin_unlock_bh(&adapter->mcc_lock);
2484 return status;
2485 }
2486
2487 int be_cmd_get_phy_info(struct be_adapter *adapter)
2488 {
2489 struct be_mcc_wrb *wrb;
2490 struct be_cmd_req_get_phy_info *req;
2491 struct be_dma_mem cmd;
2492 int status;
2493
2494 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2495 CMD_SUBSYSTEM_COMMON))
2496 return -EPERM;
2497
2498 spin_lock_bh(&adapter->mcc_lock);
2499
2500 wrb = wrb_from_mccq(adapter);
2501 if (!wrb) {
2502 status = -EBUSY;
2503 goto err;
2504 }
2505 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2506 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2507 &cmd.dma);
2508 if (!cmd.va) {
2509 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2510 status = -ENOMEM;
2511 goto err;
2512 }
2513
2514 req = cmd.va;
2515
2516 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2517 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2518 wrb, &cmd);
2519
2520 status = be_mcc_notify_wait(adapter);
2521 if (!status) {
2522 struct be_phy_info *resp_phy_info =
2523 cmd.va + sizeof(struct be_cmd_req_hdr);
2524 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2525 adapter->phy.interface_type =
2526 le16_to_cpu(resp_phy_info->interface_type);
2527 adapter->phy.auto_speeds_supported =
2528 le16_to_cpu(resp_phy_info->auto_speeds_supported);
2529 adapter->phy.fixed_speeds_supported =
2530 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2531 adapter->phy.misc_params =
2532 le32_to_cpu(resp_phy_info->misc_params);
2533
2534 if (BE2_chip(adapter)) {
2535 adapter->phy.fixed_speeds_supported =
2536 BE_SUPPORTED_SPEED_10GBPS |
2537 BE_SUPPORTED_SPEED_1GBPS;
2538 }
2539 }
2540 pci_free_consistent(adapter->pdev, cmd.size,
2541 cmd.va, cmd.dma);
2542 err:
2543 spin_unlock_bh(&adapter->mcc_lock);
2544 return status;
2545 }
2546
2547 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2548 {
2549 struct be_mcc_wrb *wrb;
2550 struct be_cmd_req_set_qos *req;
2551 int status;
2552
2553 spin_lock_bh(&adapter->mcc_lock);
2554
2555 wrb = wrb_from_mccq(adapter);
2556 if (!wrb) {
2557 status = -EBUSY;
2558 goto err;
2559 }
2560
2561 req = embedded_payload(wrb);
2562
2563 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2564 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2565
2566 req->hdr.domain = domain;
2567 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2568 req->max_bps_nic = cpu_to_le32(bps);
2569
2570 status = be_mcc_notify_wait(adapter);
2571
2572 err:
2573 spin_unlock_bh(&adapter->mcc_lock);
2574 return status;
2575 }
2576
2577 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2578 {
2579 struct be_mcc_wrb *wrb;
2580 struct be_cmd_req_cntl_attribs *req;
2581 struct be_cmd_resp_cntl_attribs *resp;
2582 int status;
2583 int payload_len = max(sizeof(*req), sizeof(*resp));
2584 struct mgmt_controller_attrib *attribs;
2585 struct be_dma_mem attribs_cmd;
2586
2587 if (mutex_lock_interruptible(&adapter->mbox_lock))
2588 return -1;
2589
2590 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2591 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2592 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2593 &attribs_cmd.dma);
2594 if (!attribs_cmd.va) {
2595 dev_err(&adapter->pdev->dev,
2596 "Memory allocation failure\n");
2597 status = -ENOMEM;
2598 goto err;
2599 }
2600
2601 wrb = wrb_from_mbox(adapter);
2602 if (!wrb) {
2603 status = -EBUSY;
2604 goto err;
2605 }
2606 req = attribs_cmd.va;
2607
2608 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2609 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2610 &attribs_cmd);
2611
2612 status = be_mbox_notify_wait(adapter);
2613 if (!status) {
2614 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2615 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2616 }
2617
2618 err:
2619 mutex_unlock(&adapter->mbox_lock);
2620 if (attribs_cmd.va)
2621 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2622 attribs_cmd.va, attribs_cmd.dma);
2623 return status;
2624 }
2625
2626 /* Uses mbox */
2627 int be_cmd_req_native_mode(struct be_adapter *adapter)
2628 {
2629 struct be_mcc_wrb *wrb;
2630 struct be_cmd_req_set_func_cap *req;
2631 int status;
2632
2633 if (mutex_lock_interruptible(&adapter->mbox_lock))
2634 return -1;
2635
2636 wrb = wrb_from_mbox(adapter);
2637 if (!wrb) {
2638 status = -EBUSY;
2639 goto err;
2640 }
2641
2642 req = embedded_payload(wrb);
2643
2644 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2645 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2646
2647 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2648 CAPABILITY_BE3_NATIVE_ERX_API);
2649 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2650
2651 status = be_mbox_notify_wait(adapter);
2652 if (!status) {
2653 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2654 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2655 CAPABILITY_BE3_NATIVE_ERX_API;
2656 if (!adapter->be3_native)
2657 dev_warn(&adapter->pdev->dev,
2658 "adapter not in advanced mode\n");
2659 }
2660 err:
2661 mutex_unlock(&adapter->mbox_lock);
2662 return status;
2663 }
2664
2665 /* Get privilege(s) for a function */
2666 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2667 u32 domain)
2668 {
2669 struct be_mcc_wrb *wrb;
2670 struct be_cmd_req_get_fn_privileges *req;
2671 int status;
2672
2673 spin_lock_bh(&adapter->mcc_lock);
2674
2675 wrb = wrb_from_mccq(adapter);
2676 if (!wrb) {
2677 status = -EBUSY;
2678 goto err;
2679 }
2680
2681 req = embedded_payload(wrb);
2682
2683 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2684 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2685 wrb, NULL);
2686
2687 req->hdr.domain = domain;
2688
2689 status = be_mcc_notify_wait(adapter);
2690 if (!status) {
2691 struct be_cmd_resp_get_fn_privileges *resp =
2692 embedded_payload(wrb);
2693 *privilege = le32_to_cpu(resp->privilege_mask);
2694
2695 /* In UMC mode FW does not return right privileges.
2696 * Override with correct privilege equivalent to PF.
2697 */
2698 if (BEx_chip(adapter) && be_is_mc(adapter) &&
2699 be_physfn(adapter))
2700 *privilege = MAX_PRIVILEGES;
2701 }
2702
2703 err:
2704 spin_unlock_bh(&adapter->mcc_lock);
2705 return status;
2706 }
2707
2708 /* Set privilege(s) for a function */
2709 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2710 u32 domain)
2711 {
2712 struct be_mcc_wrb *wrb;
2713 struct be_cmd_req_set_fn_privileges *req;
2714 int status;
2715
2716 spin_lock_bh(&adapter->mcc_lock);
2717
2718 wrb = wrb_from_mccq(adapter);
2719 if (!wrb) {
2720 status = -EBUSY;
2721 goto err;
2722 }
2723
2724 req = embedded_payload(wrb);
2725 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2726 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
2727 wrb, NULL);
2728 req->hdr.domain = domain;
2729 if (lancer_chip(adapter))
2730 req->privileges_lancer = cpu_to_le32(privileges);
2731 else
2732 req->privileges = cpu_to_le32(privileges);
2733
2734 status = be_mcc_notify_wait(adapter);
2735 err:
2736 spin_unlock_bh(&adapter->mcc_lock);
2737 return status;
2738 }
2739
2740 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
2741 * pmac_id_valid: false => pmac_id or MAC address is requested.
2742 * If pmac_id is returned, pmac_id_valid is returned as true
2743 */
2744 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2745 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
2746 u8 domain)
2747 {
2748 struct be_mcc_wrb *wrb;
2749 struct be_cmd_req_get_mac_list *req;
2750 int status;
2751 int mac_count;
2752 struct be_dma_mem get_mac_list_cmd;
2753 int i;
2754
2755 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2756 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2757 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2758 get_mac_list_cmd.size,
2759 &get_mac_list_cmd.dma);
2760
2761 if (!get_mac_list_cmd.va) {
2762 dev_err(&adapter->pdev->dev,
2763 "Memory allocation failure during GET_MAC_LIST\n");
2764 return -ENOMEM;
2765 }
2766
2767 spin_lock_bh(&adapter->mcc_lock);
2768
2769 wrb = wrb_from_mccq(adapter);
2770 if (!wrb) {
2771 status = -EBUSY;
2772 goto out;
2773 }
2774
2775 req = get_mac_list_cmd.va;
2776
2777 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2778 OPCODE_COMMON_GET_MAC_LIST,
2779 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
2780 req->hdr.domain = domain;
2781 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2782 if (*pmac_id_valid) {
2783 req->mac_id = cpu_to_le32(*pmac_id);
2784 req->iface_id = cpu_to_le16(if_handle);
2785 req->perm_override = 0;
2786 } else {
2787 req->perm_override = 1;
2788 }
2789
2790 status = be_mcc_notify_wait(adapter);
2791 if (!status) {
2792 struct be_cmd_resp_get_mac_list *resp =
2793 get_mac_list_cmd.va;
2794
2795 if (*pmac_id_valid) {
2796 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
2797 ETH_ALEN);
2798 goto out;
2799 }
2800
2801 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2802 /* Mac list returned could contain one or more active mac_ids
2803 * or one or more true or pseudo permanant mac addresses.
2804 * If an active mac_id is present, return first active mac_id
2805 * found.
2806 */
2807 for (i = 0; i < mac_count; i++) {
2808 struct get_list_macaddr *mac_entry;
2809 u16 mac_addr_size;
2810 u32 mac_id;
2811
2812 mac_entry = &resp->macaddr_list[i];
2813 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2814 /* mac_id is a 32 bit value and mac_addr size
2815 * is 6 bytes
2816 */
2817 if (mac_addr_size == sizeof(u32)) {
2818 *pmac_id_valid = true;
2819 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2820 *pmac_id = le32_to_cpu(mac_id);
2821 goto out;
2822 }
2823 }
2824 /* If no active mac_id found, return first mac addr */
2825 *pmac_id_valid = false;
2826 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2827 ETH_ALEN);
2828 }
2829
2830 out:
2831 spin_unlock_bh(&adapter->mcc_lock);
2832 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2833 get_mac_list_cmd.va, get_mac_list_cmd.dma);
2834 return status;
2835 }
2836
2837 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id, u8 *mac,
2838 u32 if_handle, bool active, u32 domain)
2839 {
2840
2841 if (!active)
2842 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
2843 if_handle, domain);
2844 if (BEx_chip(adapter))
2845 return be_cmd_mac_addr_query(adapter, mac, false,
2846 if_handle, curr_pmac_id);
2847 else
2848 /* Fetch the MAC address using pmac_id */
2849 return be_cmd_get_mac_from_list(adapter, mac, &active,
2850 &curr_pmac_id,
2851 if_handle, domain);
2852 }
2853
2854 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
2855 {
2856 int status;
2857 bool pmac_valid = false;
2858
2859 memset(mac, 0, ETH_ALEN);
2860
2861 if (BEx_chip(adapter)) {
2862 if (be_physfn(adapter))
2863 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
2864 0);
2865 else
2866 status = be_cmd_mac_addr_query(adapter, mac, false,
2867 adapter->if_handle, 0);
2868 } else {
2869 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
2870 NULL, adapter->if_handle, 0);
2871 }
2872
2873 return status;
2874 }
2875
2876 /* Uses synchronous MCCQ */
2877 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2878 u8 mac_count, u32 domain)
2879 {
2880 struct be_mcc_wrb *wrb;
2881 struct be_cmd_req_set_mac_list *req;
2882 int status;
2883 struct be_dma_mem cmd;
2884
2885 memset(&cmd, 0, sizeof(struct be_dma_mem));
2886 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2887 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2888 &cmd.dma, GFP_KERNEL);
2889 if (!cmd.va)
2890 return -ENOMEM;
2891
2892 spin_lock_bh(&adapter->mcc_lock);
2893
2894 wrb = wrb_from_mccq(adapter);
2895 if (!wrb) {
2896 status = -EBUSY;
2897 goto err;
2898 }
2899
2900 req = cmd.va;
2901 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2902 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2903 wrb, &cmd);
2904
2905 req->hdr.domain = domain;
2906 req->mac_count = mac_count;
2907 if (mac_count)
2908 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2909
2910 status = be_mcc_notify_wait(adapter);
2911
2912 err:
2913 dma_free_coherent(&adapter->pdev->dev, cmd.size,
2914 cmd.va, cmd.dma);
2915 spin_unlock_bh(&adapter->mcc_lock);
2916 return status;
2917 }
2918
2919 /* Wrapper to delete any active MACs and provision the new mac.
2920 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
2921 * current list are active.
2922 */
2923 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
2924 {
2925 bool active_mac = false;
2926 u8 old_mac[ETH_ALEN];
2927 u32 pmac_id;
2928 int status;
2929
2930 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
2931 &pmac_id, if_id, dom);
2932
2933 if (!status && active_mac)
2934 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
2935
2936 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
2937 }
2938
2939 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2940 u32 domain, u16 intf_id, u16 hsw_mode)
2941 {
2942 struct be_mcc_wrb *wrb;
2943 struct be_cmd_req_set_hsw_config *req;
2944 void *ctxt;
2945 int status;
2946
2947 spin_lock_bh(&adapter->mcc_lock);
2948
2949 wrb = wrb_from_mccq(adapter);
2950 if (!wrb) {
2951 status = -EBUSY;
2952 goto err;
2953 }
2954
2955 req = embedded_payload(wrb);
2956 ctxt = &req->context;
2957
2958 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2959 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2960
2961 req->hdr.domain = domain;
2962 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2963 if (pvid) {
2964 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2965 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2966 }
2967 if (!BEx_chip(adapter) && hsw_mode) {
2968 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
2969 ctxt, adapter->hba_port_num);
2970 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
2971 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
2972 ctxt, hsw_mode);
2973 }
2974
2975 be_dws_cpu_to_le(req->context, sizeof(req->context));
2976 status = be_mcc_notify_wait(adapter);
2977
2978 err:
2979 spin_unlock_bh(&adapter->mcc_lock);
2980 return status;
2981 }
2982
2983 /* Get Hyper switch config */
2984 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2985 u32 domain, u16 intf_id, u8 *mode)
2986 {
2987 struct be_mcc_wrb *wrb;
2988 struct be_cmd_req_get_hsw_config *req;
2989 void *ctxt;
2990 int status;
2991 u16 vid;
2992
2993 spin_lock_bh(&adapter->mcc_lock);
2994
2995 wrb = wrb_from_mccq(adapter);
2996 if (!wrb) {
2997 status = -EBUSY;
2998 goto err;
2999 }
3000
3001 req = embedded_payload(wrb);
3002 ctxt = &req->context;
3003
3004 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3005 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
3006
3007 req->hdr.domain = domain;
3008 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3009 ctxt, intf_id);
3010 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
3011
3012 if (!BEx_chip(adapter) && mode) {
3013 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3014 ctxt, adapter->hba_port_num);
3015 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3016 }
3017 be_dws_cpu_to_le(req->context, sizeof(req->context));
3018
3019 status = be_mcc_notify_wait(adapter);
3020 if (!status) {
3021 struct be_cmd_resp_get_hsw_config *resp =
3022 embedded_payload(wrb);
3023 be_dws_le_to_cpu(&resp->context,
3024 sizeof(resp->context));
3025 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3026 pvid, &resp->context);
3027 if (pvid)
3028 *pvid = le16_to_cpu(vid);
3029 if (mode)
3030 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3031 port_fwd_type, &resp->context);
3032 }
3033
3034 err:
3035 spin_unlock_bh(&adapter->mcc_lock);
3036 return status;
3037 }
3038
3039 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3040 {
3041 struct be_mcc_wrb *wrb;
3042 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
3043 int status = 0;
3044 struct be_dma_mem cmd;
3045
3046 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3047 CMD_SUBSYSTEM_ETH))
3048 return -EPERM;
3049
3050 if (be_is_wol_excluded(adapter))
3051 return status;
3052
3053 if (mutex_lock_interruptible(&adapter->mbox_lock))
3054 return -1;
3055
3056 memset(&cmd, 0, sizeof(struct be_dma_mem));
3057 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
3058 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3059 &cmd.dma);
3060 if (!cmd.va) {
3061 dev_err(&adapter->pdev->dev,
3062 "Memory allocation failure\n");
3063 status = -ENOMEM;
3064 goto err;
3065 }
3066
3067 wrb = wrb_from_mbox(adapter);
3068 if (!wrb) {
3069 status = -EBUSY;
3070 goto err;
3071 }
3072
3073 req = cmd.va;
3074
3075 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3076 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3077 sizeof(*req), wrb, &cmd);
3078
3079 req->hdr.version = 1;
3080 req->query_options = BE_GET_WOL_CAP;
3081
3082 status = be_mbox_notify_wait(adapter);
3083 if (!status) {
3084 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
3085 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
3086
3087 adapter->wol_cap = resp->wol_settings;
3088 if (adapter->wol_cap & BE_WOL_CAP)
3089 adapter->wol_en = true;
3090 }
3091 err:
3092 mutex_unlock(&adapter->mbox_lock);
3093 if (cmd.va)
3094 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3095 return status;
3096
3097 }
3098
3099 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
3100 {
3101 struct be_dma_mem extfat_cmd;
3102 struct be_fat_conf_params *cfgs;
3103 int status;
3104 int i, j;
3105
3106 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3107 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3108 extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3109 &extfat_cmd.dma);
3110 if (!extfat_cmd.va)
3111 return -ENOMEM;
3112
3113 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3114 if (status)
3115 goto err;
3116
3117 cfgs = (struct be_fat_conf_params *)
3118 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
3119 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
3120 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
3121 for (j = 0; j < num_modes; j++) {
3122 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
3123 cfgs->module[i].trace_lvl[j].dbg_lvl =
3124 cpu_to_le32(level);
3125 }
3126 }
3127
3128 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
3129 err:
3130 pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3131 extfat_cmd.dma);
3132 return status;
3133 }
3134
3135 int be_cmd_get_fw_log_level(struct be_adapter *adapter)
3136 {
3137 struct be_dma_mem extfat_cmd;
3138 struct be_fat_conf_params *cfgs;
3139 int status, j;
3140 int level = 0;
3141
3142 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3143 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3144 extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3145 &extfat_cmd.dma);
3146
3147 if (!extfat_cmd.va) {
3148 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
3149 __func__);
3150 goto err;
3151 }
3152
3153 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3154 if (!status) {
3155 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
3156 sizeof(struct be_cmd_resp_hdr));
3157 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
3158 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
3159 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
3160 }
3161 }
3162 pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3163 extfat_cmd.dma);
3164 err:
3165 return level;
3166 }
3167
3168 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
3169 struct be_dma_mem *cmd)
3170 {
3171 struct be_mcc_wrb *wrb;
3172 struct be_cmd_req_get_ext_fat_caps *req;
3173 int status;
3174
3175 if (mutex_lock_interruptible(&adapter->mbox_lock))
3176 return -1;
3177
3178 wrb = wrb_from_mbox(adapter);
3179 if (!wrb) {
3180 status = -EBUSY;
3181 goto err;
3182 }
3183
3184 req = cmd->va;
3185 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3186 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
3187 cmd->size, wrb, cmd);
3188 req->parameter_type = cpu_to_le32(1);
3189
3190 status = be_mbox_notify_wait(adapter);
3191 err:
3192 mutex_unlock(&adapter->mbox_lock);
3193 return status;
3194 }
3195
3196 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3197 struct be_dma_mem *cmd,
3198 struct be_fat_conf_params *configs)
3199 {
3200 struct be_mcc_wrb *wrb;
3201 struct be_cmd_req_set_ext_fat_caps *req;
3202 int status;
3203
3204 spin_lock_bh(&adapter->mcc_lock);
3205
3206 wrb = wrb_from_mccq(adapter);
3207 if (!wrb) {
3208 status = -EBUSY;
3209 goto err;
3210 }
3211
3212 req = cmd->va;
3213 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3214 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3215 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3216 cmd->size, wrb, cmd);
3217
3218 status = be_mcc_notify_wait(adapter);
3219 err:
3220 spin_unlock_bh(&adapter->mcc_lock);
3221 return status;
3222 }
3223
3224 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
3225 {
3226 struct be_mcc_wrb *wrb;
3227 struct be_cmd_req_get_port_name *req;
3228 int status;
3229
3230 if (!lancer_chip(adapter)) {
3231 *port_name = adapter->hba_port_num + '0';
3232 return 0;
3233 }
3234
3235 spin_lock_bh(&adapter->mcc_lock);
3236
3237 wrb = wrb_from_mccq(adapter);
3238 if (!wrb) {
3239 status = -EBUSY;
3240 goto err;
3241 }
3242
3243 req = embedded_payload(wrb);
3244
3245 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3246 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3247 NULL);
3248 req->hdr.version = 1;
3249
3250 status = be_mcc_notify_wait(adapter);
3251 if (!status) {
3252 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
3253 *port_name = resp->port_name[adapter->hba_port_num];
3254 } else {
3255 *port_name = adapter->hba_port_num + '0';
3256 }
3257 err:
3258 spin_unlock_bh(&adapter->mcc_lock);
3259 return status;
3260 }
3261
3262 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count)
3263 {
3264 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3265 int i;
3266
3267 for (i = 0; i < desc_count; i++) {
3268 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
3269 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1)
3270 return (struct be_nic_res_desc *)hdr;
3271
3272 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3273 hdr = (void *)hdr + hdr->desc_len;
3274 }
3275 return NULL;
3276 }
3277
3278 static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
3279 u32 desc_count)
3280 {
3281 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3282 struct be_pcie_res_desc *pcie;
3283 int i;
3284
3285 for (i = 0; i < desc_count; i++) {
3286 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
3287 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
3288 pcie = (struct be_pcie_res_desc *)hdr;
3289 if (pcie->pf_num == devfn)
3290 return pcie;
3291 }
3292
3293 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3294 hdr = (void *)hdr + hdr->desc_len;
3295 }
3296 return NULL;
3297 }
3298
3299 static void be_copy_nic_desc(struct be_resources *res,
3300 struct be_nic_res_desc *desc)
3301 {
3302 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
3303 res->max_vlans = le16_to_cpu(desc->vlan_count);
3304 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3305 res->max_tx_qs = le16_to_cpu(desc->txq_count);
3306 res->max_rss_qs = le16_to_cpu(desc->rssq_count);
3307 res->max_rx_qs = le16_to_cpu(desc->rq_count);
3308 res->max_evt_qs = le16_to_cpu(desc->eq_count);
3309 /* Clear flags that driver is not interested in */
3310 res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
3311 BE_IF_CAP_FLAGS_WANT;
3312 /* Need 1 RXQ as the default RXQ */
3313 if (res->max_rss_qs && res->max_rss_qs == res->max_rx_qs)
3314 res->max_rss_qs -= 1;
3315 }
3316
3317 /* Uses Mbox */
3318 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
3319 {
3320 struct be_mcc_wrb *wrb;
3321 struct be_cmd_req_get_func_config *req;
3322 int status;
3323 struct be_dma_mem cmd;
3324
3325 if (mutex_lock_interruptible(&adapter->mbox_lock))
3326 return -1;
3327
3328 memset(&cmd, 0, sizeof(struct be_dma_mem));
3329 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
3330 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3331 &cmd.dma);
3332 if (!cmd.va) {
3333 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3334 status = -ENOMEM;
3335 goto err;
3336 }
3337
3338 wrb = wrb_from_mbox(adapter);
3339 if (!wrb) {
3340 status = -EBUSY;
3341 goto err;
3342 }
3343
3344 req = cmd.va;
3345
3346 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3347 OPCODE_COMMON_GET_FUNC_CONFIG,
3348 cmd.size, wrb, &cmd);
3349
3350 if (skyhawk_chip(adapter))
3351 req->hdr.version = 1;
3352
3353 status = be_mbox_notify_wait(adapter);
3354 if (!status) {
3355 struct be_cmd_resp_get_func_config *resp = cmd.va;
3356 u32 desc_count = le32_to_cpu(resp->desc_count);
3357 struct be_nic_res_desc *desc;
3358
3359 desc = be_get_nic_desc(resp->func_param, desc_count);
3360 if (!desc) {
3361 status = -EINVAL;
3362 goto err;
3363 }
3364
3365 adapter->pf_number = desc->pf_num;
3366 be_copy_nic_desc(res, desc);
3367 }
3368 err:
3369 mutex_unlock(&adapter->mbox_lock);
3370 if (cmd.va)
3371 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3372 return status;
3373 }
3374
3375 /* Uses mbox */
3376 static int be_cmd_get_profile_config_mbox(struct be_adapter *adapter,
3377 u8 domain, struct be_dma_mem *cmd)
3378 {
3379 struct be_mcc_wrb *wrb;
3380 struct be_cmd_req_get_profile_config *req;
3381 int status;
3382
3383 if (mutex_lock_interruptible(&adapter->mbox_lock))
3384 return -1;
3385 wrb = wrb_from_mbox(adapter);
3386
3387 req = cmd->va;
3388 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3389 OPCODE_COMMON_GET_PROFILE_CONFIG,
3390 cmd->size, wrb, cmd);
3391
3392 req->type = ACTIVE_PROFILE_TYPE;
3393 req->hdr.domain = domain;
3394 if (!lancer_chip(adapter))
3395 req->hdr.version = 1;
3396
3397 status = be_mbox_notify_wait(adapter);
3398
3399 mutex_unlock(&adapter->mbox_lock);
3400 return status;
3401 }
3402
3403 /* Uses sync mcc */
3404 static int be_cmd_get_profile_config_mccq(struct be_adapter *adapter,
3405 u8 domain, struct be_dma_mem *cmd)
3406 {
3407 struct be_mcc_wrb *wrb;
3408 struct be_cmd_req_get_profile_config *req;
3409 int status;
3410
3411 spin_lock_bh(&adapter->mcc_lock);
3412
3413 wrb = wrb_from_mccq(adapter);
3414 if (!wrb) {
3415 status = -EBUSY;
3416 goto err;
3417 }
3418
3419 req = cmd->va;
3420 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3421 OPCODE_COMMON_GET_PROFILE_CONFIG,
3422 cmd->size, wrb, cmd);
3423
3424 req->type = ACTIVE_PROFILE_TYPE;
3425 req->hdr.domain = domain;
3426 if (!lancer_chip(adapter))
3427 req->hdr.version = 1;
3428
3429 status = be_mcc_notify_wait(adapter);
3430
3431 err:
3432 spin_unlock_bh(&adapter->mcc_lock);
3433 return status;
3434 }
3435
3436 /* Uses sync mcc, if MCCQ is already created otherwise mbox */
3437 int be_cmd_get_profile_config(struct be_adapter *adapter,
3438 struct be_resources *res, u8 domain)
3439 {
3440 struct be_cmd_resp_get_profile_config *resp;
3441 struct be_pcie_res_desc *pcie;
3442 struct be_nic_res_desc *nic;
3443 struct be_queue_info *mccq = &adapter->mcc_obj.q;
3444 struct be_dma_mem cmd;
3445 u32 desc_count;
3446 int status;
3447
3448 memset(&cmd, 0, sizeof(struct be_dma_mem));
3449 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3450 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3451 if (!cmd.va)
3452 return -ENOMEM;
3453
3454 if (!mccq->created)
3455 status = be_cmd_get_profile_config_mbox(adapter, domain, &cmd);
3456 else
3457 status = be_cmd_get_profile_config_mccq(adapter, domain, &cmd);
3458 if (status)
3459 goto err;
3460
3461 resp = cmd.va;
3462 desc_count = le32_to_cpu(resp->desc_count);
3463
3464 pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
3465 desc_count);
3466 if (pcie)
3467 res->max_vfs = le16_to_cpu(pcie->num_vfs);
3468
3469 nic = be_get_nic_desc(resp->func_param, desc_count);
3470 if (nic)
3471 be_copy_nic_desc(res, nic);
3472
3473 err:
3474 if (cmd.va)
3475 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3476 return status;
3477 }
3478
3479 /* Currently only Lancer uses this command and it supports version 0 only
3480 * Uses sync mcc
3481 */
3482 int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps,
3483 u8 domain)
3484 {
3485 struct be_mcc_wrb *wrb;
3486 struct be_cmd_req_set_profile_config *req;
3487 int status;
3488
3489 spin_lock_bh(&adapter->mcc_lock);
3490
3491 wrb = wrb_from_mccq(adapter);
3492 if (!wrb) {
3493 status = -EBUSY;
3494 goto err;
3495 }
3496
3497 req = embedded_payload(wrb);
3498
3499 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3500 OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req),
3501 wrb, NULL);
3502 req->hdr.domain = domain;
3503 req->desc_count = cpu_to_le32(1);
3504 req->nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3505 req->nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
3506 req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV);
3507 req->nic_desc.pf_num = adapter->pf_number;
3508 req->nic_desc.vf_num = domain;
3509
3510 /* Mark fields invalid */
3511 req->nic_desc.unicast_mac_count = 0xFFFF;
3512 req->nic_desc.mcc_count = 0xFFFF;
3513 req->nic_desc.vlan_count = 0xFFFF;
3514 req->nic_desc.mcast_mac_count = 0xFFFF;
3515 req->nic_desc.txq_count = 0xFFFF;
3516 req->nic_desc.rq_count = 0xFFFF;
3517 req->nic_desc.rssq_count = 0xFFFF;
3518 req->nic_desc.lro_count = 0xFFFF;
3519 req->nic_desc.cq_count = 0xFFFF;
3520 req->nic_desc.toe_conn_count = 0xFFFF;
3521 req->nic_desc.eq_count = 0xFFFF;
3522 req->nic_desc.link_param = 0xFF;
3523 req->nic_desc.bw_min = 0xFFFFFFFF;
3524 req->nic_desc.acpi_params = 0xFF;
3525 req->nic_desc.wol_param = 0x0F;
3526
3527 /* Change BW */
3528 req->nic_desc.bw_min = cpu_to_le32(bps);
3529 req->nic_desc.bw_max = cpu_to_le32(bps);
3530 status = be_mcc_notify_wait(adapter);
3531 err:
3532 spin_unlock_bh(&adapter->mcc_lock);
3533 return status;
3534 }
3535
3536 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3537 int vf_num)
3538 {
3539 struct be_mcc_wrb *wrb;
3540 struct be_cmd_req_get_iface_list *req;
3541 struct be_cmd_resp_get_iface_list *resp;
3542 int status;
3543
3544 spin_lock_bh(&adapter->mcc_lock);
3545
3546 wrb = wrb_from_mccq(adapter);
3547 if (!wrb) {
3548 status = -EBUSY;
3549 goto err;
3550 }
3551 req = embedded_payload(wrb);
3552
3553 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3554 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3555 wrb, NULL);
3556 req->hdr.domain = vf_num + 1;
3557
3558 status = be_mcc_notify_wait(adapter);
3559 if (!status) {
3560 resp = (struct be_cmd_resp_get_iface_list *)req;
3561 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3562 }
3563
3564 err:
3565 spin_unlock_bh(&adapter->mcc_lock);
3566 return status;
3567 }
3568
3569 static int lancer_wait_idle(struct be_adapter *adapter)
3570 {
3571 #define SLIPORT_IDLE_TIMEOUT 30
3572 u32 reg_val;
3573 int status = 0, i;
3574
3575 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
3576 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
3577 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
3578 break;
3579
3580 ssleep(1);
3581 }
3582
3583 if (i == SLIPORT_IDLE_TIMEOUT)
3584 status = -1;
3585
3586 return status;
3587 }
3588
3589 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
3590 {
3591 int status = 0;
3592
3593 status = lancer_wait_idle(adapter);
3594 if (status)
3595 return status;
3596
3597 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
3598
3599 return status;
3600 }
3601
3602 /* Routine to check whether dump image is present or not */
3603 bool dump_present(struct be_adapter *adapter)
3604 {
3605 u32 sliport_status = 0;
3606
3607 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
3608 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
3609 }
3610
3611 int lancer_initiate_dump(struct be_adapter *adapter)
3612 {
3613 int status;
3614
3615 /* give firmware reset and diagnostic dump */
3616 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
3617 PHYSDEV_CONTROL_DD_MASK);
3618 if (status < 0) {
3619 dev_err(&adapter->pdev->dev, "Firmware reset failed\n");
3620 return status;
3621 }
3622
3623 status = lancer_wait_idle(adapter);
3624 if (status)
3625 return status;
3626
3627 if (!dump_present(adapter)) {
3628 dev_err(&adapter->pdev->dev, "Dump image not present\n");
3629 return -1;
3630 }
3631
3632 return 0;
3633 }
3634
3635 /* Uses sync mcc */
3636 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
3637 {
3638 struct be_mcc_wrb *wrb;
3639 struct be_cmd_enable_disable_vf *req;
3640 int status;
3641
3642 if (BEx_chip(adapter))
3643 return 0;
3644
3645 spin_lock_bh(&adapter->mcc_lock);
3646
3647 wrb = wrb_from_mccq(adapter);
3648 if (!wrb) {
3649 status = -EBUSY;
3650 goto err;
3651 }
3652
3653 req = embedded_payload(wrb);
3654
3655 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3656 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
3657 wrb, NULL);
3658
3659 req->hdr.domain = domain;
3660 req->enable = 1;
3661 status = be_mcc_notify_wait(adapter);
3662 err:
3663 spin_unlock_bh(&adapter->mcc_lock);
3664 return status;
3665 }
3666
3667 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
3668 {
3669 struct be_mcc_wrb *wrb;
3670 struct be_cmd_req_intr_set *req;
3671 int status;
3672
3673 if (mutex_lock_interruptible(&adapter->mbox_lock))
3674 return -1;
3675
3676 wrb = wrb_from_mbox(adapter);
3677
3678 req = embedded_payload(wrb);
3679
3680 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3681 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
3682 wrb, NULL);
3683
3684 req->intr_enabled = intr_enable;
3685
3686 status = be_mbox_notify_wait(adapter);
3687
3688 mutex_unlock(&adapter->mbox_lock);
3689 return status;
3690 }
3691
3692 /* Uses MBOX */
3693 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
3694 {
3695 struct be_cmd_req_get_active_profile *req;
3696 struct be_mcc_wrb *wrb;
3697 int status;
3698
3699 if (mutex_lock_interruptible(&adapter->mbox_lock))
3700 return -1;
3701
3702 wrb = wrb_from_mbox(adapter);
3703 if (!wrb) {
3704 status = -EBUSY;
3705 goto err;
3706 }
3707
3708 req = embedded_payload(wrb);
3709
3710 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3711 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
3712 wrb, NULL);
3713
3714 status = be_mbox_notify_wait(adapter);
3715 if (!status) {
3716 struct be_cmd_resp_get_active_profile *resp =
3717 embedded_payload(wrb);
3718 *profile_id = le16_to_cpu(resp->active_profile_id);
3719 }
3720
3721 err:
3722 mutex_unlock(&adapter->mbox_lock);
3723 return status;
3724 }
3725
3726 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
3727 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
3728 {
3729 struct be_adapter *adapter = netdev_priv(netdev_handle);
3730 struct be_mcc_wrb *wrb;
3731 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
3732 struct be_cmd_req_hdr *req;
3733 struct be_cmd_resp_hdr *resp;
3734 int status;
3735
3736 spin_lock_bh(&adapter->mcc_lock);
3737
3738 wrb = wrb_from_mccq(adapter);
3739 if (!wrb) {
3740 status = -EBUSY;
3741 goto err;
3742 }
3743 req = embedded_payload(wrb);
3744 resp = embedded_payload(wrb);
3745
3746 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
3747 hdr->opcode, wrb_payload_size, wrb, NULL);
3748 memcpy(req, wrb_payload, wrb_payload_size);
3749 be_dws_cpu_to_le(req, wrb_payload_size);
3750
3751 status = be_mcc_notify_wait(adapter);
3752 if (cmd_status)
3753 *cmd_status = (status & 0xffff);
3754 if (ext_status)
3755 *ext_status = 0;
3756 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
3757 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
3758 err:
3759 spin_unlock_bh(&adapter->mcc_lock);
3760 return status;
3761 }
3762 EXPORT_SYMBOL(be_roce_mcc_cmd);
Linux kernel - Deliverables
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