2 * Copyright (C) 2005 - 2014 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
18 #include <linux/module.h>
22 static char *be_port_misconfig_evt_desc
[] = {
23 "A valid SFP module detected",
24 "Optics faulted/ incorrectly installed/ not installed.",
25 "Optics of two types installed.",
26 "Incompatible optics.",
27 "Unknown port SFP status"
30 static char *be_port_misconfig_remedy_desc
[] = {
32 "Reseat optics. If issue not resolved, replace",
33 "Remove one optic or install matching pair of optics",
34 "Replace with compatible optics for card to function",
38 static struct be_cmd_priv_map cmd_priv_map
[] = {
40 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
,
42 BE_PRIV_LNKMGMT
| BE_PRIV_VHADM
|
43 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
46 OPCODE_COMMON_GET_FLOW_CONTROL
,
48 BE_PRIV_LNKQUERY
| BE_PRIV_VHADM
|
49 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
52 OPCODE_COMMON_SET_FLOW_CONTROL
,
54 BE_PRIV_LNKMGMT
| BE_PRIV_VHADM
|
55 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
58 OPCODE_ETH_GET_PPORT_STATS
,
60 BE_PRIV_LNKMGMT
| BE_PRIV_VHADM
|
61 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
64 OPCODE_COMMON_GET_PHY_DETAILS
,
66 BE_PRIV_LNKMGMT
| BE_PRIV_VHADM
|
67 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
71 static bool be_cmd_allowed(struct be_adapter
*adapter
, u8 opcode
, u8 subsystem
)
74 int num_entries
= sizeof(cmd_priv_map
)/sizeof(struct be_cmd_priv_map
);
75 u32 cmd_privileges
= adapter
->cmd_privileges
;
77 for (i
= 0; i
< num_entries
; i
++)
78 if (opcode
== cmd_priv_map
[i
].opcode
&&
79 subsystem
== cmd_priv_map
[i
].subsystem
)
80 if (!(cmd_privileges
& cmd_priv_map
[i
].priv_mask
))
86 static inline void *embedded_payload(struct be_mcc_wrb
*wrb
)
88 return wrb
->payload
.embedded_payload
;
91 static void be_mcc_notify(struct be_adapter
*adapter
)
93 struct be_queue_info
*mccq
= &adapter
->mcc_obj
.q
;
96 if (be_error(adapter
))
99 val
|= mccq
->id
& DB_MCCQ_RING_ID_MASK
;
100 val
|= 1 << DB_MCCQ_NUM_POSTED_SHIFT
;
103 iowrite32(val
, adapter
->db
+ DB_MCCQ_OFFSET
);
106 /* To check if valid bit is set, check the entire word as we don't know
107 * the endianness of the data (old entry is host endian while a new entry is
109 static inline bool be_mcc_compl_is_new(struct be_mcc_compl
*compl)
113 if (compl->flags
!= 0) {
114 flags
= le32_to_cpu(compl->flags
);
115 if (flags
& CQE_FLAGS_VALID_MASK
) {
116 compl->flags
= flags
;
123 /* Need to reset the entire word that houses the valid bit */
124 static inline void be_mcc_compl_use(struct be_mcc_compl
*compl)
129 static struct be_cmd_resp_hdr
*be_decode_resp_hdr(u32 tag0
, u32 tag1
)
134 addr
= ((addr
<< 16) << 16) | tag0
;
138 static bool be_skip_err_log(u8 opcode
, u16 base_status
, u16 addl_status
)
140 if (base_status
== MCC_STATUS_NOT_SUPPORTED
||
141 base_status
== MCC_STATUS_ILLEGAL_REQUEST
||
142 addl_status
== MCC_ADDL_STATUS_TOO_MANY_INTERFACES
||
143 (opcode
== OPCODE_COMMON_WRITE_FLASHROM
&&
144 (base_status
== MCC_STATUS_ILLEGAL_FIELD
||
145 addl_status
== MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH
)))
151 /* Place holder for all the async MCC cmds wherein the caller is not in a busy
152 * loop (has not issued be_mcc_notify_wait())
154 static void be_async_cmd_process(struct be_adapter
*adapter
,
155 struct be_mcc_compl
*compl,
156 struct be_cmd_resp_hdr
*resp_hdr
)
158 enum mcc_base_status base_status
= base_status(compl->status
);
159 u8 opcode
= 0, subsystem
= 0;
162 opcode
= resp_hdr
->opcode
;
163 subsystem
= resp_hdr
->subsystem
;
166 if (opcode
== OPCODE_LOWLEVEL_LOOPBACK_TEST
&&
167 subsystem
== CMD_SUBSYSTEM_LOWLEVEL
) {
168 complete(&adapter
->et_cmd_compl
);
172 if ((opcode
== OPCODE_COMMON_WRITE_FLASHROM
||
173 opcode
== OPCODE_COMMON_WRITE_OBJECT
) &&
174 subsystem
== CMD_SUBSYSTEM_COMMON
) {
175 adapter
->flash_status
= compl->status
;
176 complete(&adapter
->et_cmd_compl
);
180 if ((opcode
== OPCODE_ETH_GET_STATISTICS
||
181 opcode
== OPCODE_ETH_GET_PPORT_STATS
) &&
182 subsystem
== CMD_SUBSYSTEM_ETH
&&
183 base_status
== MCC_STATUS_SUCCESS
) {
184 be_parse_stats(adapter
);
185 adapter
->stats_cmd_sent
= false;
189 if (opcode
== OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES
&&
190 subsystem
== CMD_SUBSYSTEM_COMMON
) {
191 if (base_status
== MCC_STATUS_SUCCESS
) {
192 struct be_cmd_resp_get_cntl_addnl_attribs
*resp
=
194 adapter
->drv_stats
.be_on_die_temperature
=
195 resp
->on_die_temperature
;
197 adapter
->be_get_temp_freq
= 0;
203 static int be_mcc_compl_process(struct be_adapter
*adapter
,
204 struct be_mcc_compl
*compl)
206 enum mcc_base_status base_status
;
207 enum mcc_addl_status addl_status
;
208 struct be_cmd_resp_hdr
*resp_hdr
;
209 u8 opcode
= 0, subsystem
= 0;
211 /* Just swap the status to host endian; mcc tag is opaquely copied
213 be_dws_le_to_cpu(compl, 4);
215 base_status
= base_status(compl->status
);
216 addl_status
= addl_status(compl->status
);
218 resp_hdr
= be_decode_resp_hdr(compl->tag0
, compl->tag1
);
220 opcode
= resp_hdr
->opcode
;
221 subsystem
= resp_hdr
->subsystem
;
224 be_async_cmd_process(adapter
, compl, resp_hdr
);
226 if (base_status
!= MCC_STATUS_SUCCESS
&&
227 !be_skip_err_log(opcode
, base_status
, addl_status
)) {
228 if (base_status
== MCC_STATUS_UNAUTHORIZED_REQUEST
) {
229 dev_warn(&adapter
->pdev
->dev
,
230 "VF is not privileged to issue opcode %d-%d\n",
233 dev_err(&adapter
->pdev
->dev
,
234 "opcode %d-%d failed:status %d-%d\n",
235 opcode
, subsystem
, base_status
, addl_status
);
238 return compl->status
;
241 /* Link state evt is a string of bytes; no need for endian swapping */
242 static void be_async_link_state_process(struct be_adapter
*adapter
,
243 struct be_mcc_compl
*compl)
245 struct be_async_event_link_state
*evt
=
246 (struct be_async_event_link_state
*)compl;
248 /* When link status changes, link speed must be re-queried from FW */
249 adapter
->phy
.link_speed
= -1;
251 /* On BEx the FW does not send a separate link status
252 * notification for physical and logical link.
253 * On other chips just process the logical link
254 * status notification
256 if (!BEx_chip(adapter
) &&
257 !(evt
->port_link_status
& LOGICAL_LINK_STATUS_MASK
))
260 /* For the initial link status do not rely on the ASYNC event as
261 * it may not be received in some cases.
263 if (adapter
->flags
& BE_FLAGS_LINK_STATUS_INIT
)
264 be_link_status_update(adapter
,
265 evt
->port_link_status
& LINK_STATUS_MASK
);
268 static void be_async_port_misconfig_event_process(struct be_adapter
*adapter
,
269 struct be_mcc_compl
*compl)
271 struct be_async_event_misconfig_port
*evt
=
272 (struct be_async_event_misconfig_port
*)compl;
273 u32 sfp_mismatch_evt
= le32_to_cpu(evt
->event_data_word1
);
274 struct device
*dev
= &adapter
->pdev
->dev
;
275 u8 port_misconfig_evt
;
278 ((sfp_mismatch_evt
>> (adapter
->hba_port_num
* 8)) & 0xff);
280 /* Log an error message that would allow a user to determine
281 * whether the SFPs have an issue
283 dev_info(dev
, "Port %c: %s %s", adapter
->port_name
,
284 be_port_misconfig_evt_desc
[port_misconfig_evt
],
285 be_port_misconfig_remedy_desc
[port_misconfig_evt
]);
287 if (port_misconfig_evt
== INCOMPATIBLE_SFP
)
288 adapter
->flags
|= BE_FLAGS_EVT_INCOMPATIBLE_SFP
;
291 /* Grp5 CoS Priority evt */
292 static void be_async_grp5_cos_priority_process(struct be_adapter
*adapter
,
293 struct be_mcc_compl
*compl)
295 struct be_async_event_grp5_cos_priority
*evt
=
296 (struct be_async_event_grp5_cos_priority
*)compl;
299 adapter
->vlan_prio_bmap
= evt
->available_priority_bmap
;
300 adapter
->recommended_prio
&= ~VLAN_PRIO_MASK
;
301 adapter
->recommended_prio
=
302 evt
->reco_default_priority
<< VLAN_PRIO_SHIFT
;
306 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
307 static void be_async_grp5_qos_speed_process(struct be_adapter
*adapter
,
308 struct be_mcc_compl
*compl)
310 struct be_async_event_grp5_qos_link_speed
*evt
=
311 (struct be_async_event_grp5_qos_link_speed
*)compl;
313 if (adapter
->phy
.link_speed
>= 0 &&
314 evt
->physical_port
== adapter
->port_num
)
315 adapter
->phy
.link_speed
= le16_to_cpu(evt
->qos_link_speed
) * 10;
319 static void be_async_grp5_pvid_state_process(struct be_adapter
*adapter
,
320 struct be_mcc_compl
*compl)
322 struct be_async_event_grp5_pvid_state
*evt
=
323 (struct be_async_event_grp5_pvid_state
*)compl;
326 adapter
->pvid
= le16_to_cpu(evt
->tag
) & VLAN_VID_MASK
;
327 dev_info(&adapter
->pdev
->dev
, "LPVID: %d\n", adapter
->pvid
);
333 static void be_async_grp5_evt_process(struct be_adapter
*adapter
,
334 struct be_mcc_compl
*compl)
336 u8 event_type
= (compl->flags
>> ASYNC_EVENT_TYPE_SHIFT
) &
337 ASYNC_EVENT_TYPE_MASK
;
339 switch (event_type
) {
340 case ASYNC_EVENT_COS_PRIORITY
:
341 be_async_grp5_cos_priority_process(adapter
, compl);
343 case ASYNC_EVENT_QOS_SPEED
:
344 be_async_grp5_qos_speed_process(adapter
, compl);
346 case ASYNC_EVENT_PVID_STATE
:
347 be_async_grp5_pvid_state_process(adapter
, compl);
354 static void be_async_dbg_evt_process(struct be_adapter
*adapter
,
355 struct be_mcc_compl
*cmp
)
358 struct be_async_event_qnq
*evt
= (struct be_async_event_qnq
*)cmp
;
360 event_type
= (cmp
->flags
>> ASYNC_EVENT_TYPE_SHIFT
) &
361 ASYNC_EVENT_TYPE_MASK
;
363 switch (event_type
) {
364 case ASYNC_DEBUG_EVENT_TYPE_QNQ
:
366 adapter
->qnq_vid
= le16_to_cpu(evt
->vlan_tag
);
367 adapter
->flags
|= BE_FLAGS_QNQ_ASYNC_EVT_RCVD
;
370 dev_warn(&adapter
->pdev
->dev
, "Unknown debug event 0x%x!\n",
376 static void be_async_sliport_evt_process(struct be_adapter
*adapter
,
377 struct be_mcc_compl
*cmp
)
379 u8 event_type
= (cmp
->flags
>> ASYNC_EVENT_TYPE_SHIFT
) &
380 ASYNC_EVENT_TYPE_MASK
;
382 if (event_type
== ASYNC_EVENT_PORT_MISCONFIG
)
383 be_async_port_misconfig_event_process(adapter
, cmp
);
386 static inline bool is_link_state_evt(u32 flags
)
388 return ((flags
>> ASYNC_EVENT_CODE_SHIFT
) & ASYNC_EVENT_CODE_MASK
) ==
389 ASYNC_EVENT_CODE_LINK_STATE
;
392 static inline bool is_grp5_evt(u32 flags
)
394 return ((flags
>> ASYNC_EVENT_CODE_SHIFT
) & ASYNC_EVENT_CODE_MASK
) ==
395 ASYNC_EVENT_CODE_GRP_5
;
398 static inline bool is_dbg_evt(u32 flags
)
400 return ((flags
>> ASYNC_EVENT_CODE_SHIFT
) & ASYNC_EVENT_CODE_MASK
) ==
401 ASYNC_EVENT_CODE_QNQ
;
404 static inline bool is_sliport_evt(u32 flags
)
406 return ((flags
>> ASYNC_EVENT_CODE_SHIFT
) & ASYNC_EVENT_CODE_MASK
) ==
407 ASYNC_EVENT_CODE_SLIPORT
;
410 static void be_mcc_event_process(struct be_adapter
*adapter
,
411 struct be_mcc_compl
*compl)
413 if (is_link_state_evt(compl->flags
))
414 be_async_link_state_process(adapter
, compl);
415 else if (is_grp5_evt(compl->flags
))
416 be_async_grp5_evt_process(adapter
, compl);
417 else if (is_dbg_evt(compl->flags
))
418 be_async_dbg_evt_process(adapter
, compl);
419 else if (is_sliport_evt(compl->flags
))
420 be_async_sliport_evt_process(adapter
, compl);
423 static struct be_mcc_compl
*be_mcc_compl_get(struct be_adapter
*adapter
)
425 struct be_queue_info
*mcc_cq
= &adapter
->mcc_obj
.cq
;
426 struct be_mcc_compl
*compl = queue_tail_node(mcc_cq
);
428 if (be_mcc_compl_is_new(compl)) {
429 queue_tail_inc(mcc_cq
);
435 void be_async_mcc_enable(struct be_adapter
*adapter
)
437 spin_lock_bh(&adapter
->mcc_cq_lock
);
439 be_cq_notify(adapter
, adapter
->mcc_obj
.cq
.id
, true, 0);
440 adapter
->mcc_obj
.rearm_cq
= true;
442 spin_unlock_bh(&adapter
->mcc_cq_lock
);
445 void be_async_mcc_disable(struct be_adapter
*adapter
)
447 spin_lock_bh(&adapter
->mcc_cq_lock
);
449 adapter
->mcc_obj
.rearm_cq
= false;
450 be_cq_notify(adapter
, adapter
->mcc_obj
.cq
.id
, false, 0);
452 spin_unlock_bh(&adapter
->mcc_cq_lock
);
455 int be_process_mcc(struct be_adapter
*adapter
)
457 struct be_mcc_compl
*compl;
458 int num
= 0, status
= 0;
459 struct be_mcc_obj
*mcc_obj
= &adapter
->mcc_obj
;
461 spin_lock(&adapter
->mcc_cq_lock
);
463 while ((compl = be_mcc_compl_get(adapter
))) {
464 if (compl->flags
& CQE_FLAGS_ASYNC_MASK
) {
465 be_mcc_event_process(adapter
, compl);
466 } else if (compl->flags
& CQE_FLAGS_COMPLETED_MASK
) {
467 status
= be_mcc_compl_process(adapter
, compl);
468 atomic_dec(&mcc_obj
->q
.used
);
470 be_mcc_compl_use(compl);
475 be_cq_notify(adapter
, mcc_obj
->cq
.id
, mcc_obj
->rearm_cq
, num
);
477 spin_unlock(&adapter
->mcc_cq_lock
);
481 /* Wait till no more pending mcc requests are present */
482 static int be_mcc_wait_compl(struct be_adapter
*adapter
)
484 #define mcc_timeout 120000 /* 12s timeout */
486 struct be_mcc_obj
*mcc_obj
= &adapter
->mcc_obj
;
488 for (i
= 0; i
< mcc_timeout
; i
++) {
489 if (be_error(adapter
))
493 status
= be_process_mcc(adapter
);
496 if (atomic_read(&mcc_obj
->q
.used
) == 0)
500 if (i
== mcc_timeout
) {
501 dev_err(&adapter
->pdev
->dev
, "FW not responding\n");
502 adapter
->fw_timeout
= true;
508 /* Notify MCC requests and wait for completion */
509 static int be_mcc_notify_wait(struct be_adapter
*adapter
)
512 struct be_mcc_wrb
*wrb
;
513 struct be_mcc_obj
*mcc_obj
= &adapter
->mcc_obj
;
514 u16 index
= mcc_obj
->q
.head
;
515 struct be_cmd_resp_hdr
*resp
;
517 index_dec(&index
, mcc_obj
->q
.len
);
518 wrb
= queue_index_node(&mcc_obj
->q
, index
);
520 resp
= be_decode_resp_hdr(wrb
->tag0
, wrb
->tag1
);
522 be_mcc_notify(adapter
);
524 status
= be_mcc_wait_compl(adapter
);
528 status
= (resp
->base_status
|
529 ((resp
->addl_status
& CQE_ADDL_STATUS_MASK
) <<
530 CQE_ADDL_STATUS_SHIFT
));
535 static int be_mbox_db_ready_wait(struct be_adapter
*adapter
, void __iomem
*db
)
541 if (be_error(adapter
))
544 ready
= ioread32(db
);
545 if (ready
== 0xffffffff)
548 ready
&= MPU_MAILBOX_DB_RDY_MASK
;
553 dev_err(&adapter
->pdev
->dev
, "FW not responding\n");
554 adapter
->fw_timeout
= true;
555 be_detect_error(adapter
);
567 * Insert the mailbox address into the doorbell in two steps
568 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
570 static int be_mbox_notify_wait(struct be_adapter
*adapter
)
574 void __iomem
*db
= adapter
->db
+ MPU_MAILBOX_DB_OFFSET
;
575 struct be_dma_mem
*mbox_mem
= &adapter
->mbox_mem
;
576 struct be_mcc_mailbox
*mbox
= mbox_mem
->va
;
577 struct be_mcc_compl
*compl = &mbox
->compl;
579 /* wait for ready to be set */
580 status
= be_mbox_db_ready_wait(adapter
, db
);
584 val
|= MPU_MAILBOX_DB_HI_MASK
;
585 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
586 val
|= (upper_32_bits(mbox_mem
->dma
) >> 2) << 2;
589 /* wait for ready to be set */
590 status
= be_mbox_db_ready_wait(adapter
, db
);
595 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
596 val
|= (u32
)(mbox_mem
->dma
>> 4) << 2;
599 status
= be_mbox_db_ready_wait(adapter
, db
);
603 /* A cq entry has been made now */
604 if (be_mcc_compl_is_new(compl)) {
605 status
= be_mcc_compl_process(adapter
, &mbox
->compl);
606 be_mcc_compl_use(compl);
610 dev_err(&adapter
->pdev
->dev
, "invalid mailbox completion\n");
616 static u16
be_POST_stage_get(struct be_adapter
*adapter
)
620 if (BEx_chip(adapter
))
621 sem
= ioread32(adapter
->csr
+ SLIPORT_SEMAPHORE_OFFSET_BEx
);
623 pci_read_config_dword(adapter
->pdev
,
624 SLIPORT_SEMAPHORE_OFFSET_SH
, &sem
);
626 return sem
& POST_STAGE_MASK
;
629 static int lancer_wait_ready(struct be_adapter
*adapter
)
631 #define SLIPORT_READY_TIMEOUT 30
635 for (i
= 0; i
< SLIPORT_READY_TIMEOUT
; i
++) {
636 sliport_status
= ioread32(adapter
->db
+ SLIPORT_STATUS_OFFSET
);
637 if (sliport_status
& SLIPORT_STATUS_RDY_MASK
)
643 if (i
== SLIPORT_READY_TIMEOUT
)
644 return sliport_status
? : -1;
649 static bool lancer_provisioning_error(struct be_adapter
*adapter
)
651 u32 sliport_status
= 0, sliport_err1
= 0, sliport_err2
= 0;
653 sliport_status
= ioread32(adapter
->db
+ SLIPORT_STATUS_OFFSET
);
654 if (sliport_status
& SLIPORT_STATUS_ERR_MASK
) {
655 sliport_err1
= ioread32(adapter
->db
+ SLIPORT_ERROR1_OFFSET
);
656 sliport_err2
= ioread32(adapter
->db
+ SLIPORT_ERROR2_OFFSET
);
658 if (sliport_err1
== SLIPORT_ERROR_NO_RESOURCE1
&&
659 sliport_err2
== SLIPORT_ERROR_NO_RESOURCE2
)
665 int lancer_test_and_set_rdy_state(struct be_adapter
*adapter
)
668 u32 sliport_status
, err
, reset_needed
;
671 resource_error
= lancer_provisioning_error(adapter
);
675 status
= lancer_wait_ready(adapter
);
677 sliport_status
= ioread32(adapter
->db
+ SLIPORT_STATUS_OFFSET
);
678 err
= sliport_status
& SLIPORT_STATUS_ERR_MASK
;
679 reset_needed
= sliport_status
& SLIPORT_STATUS_RN_MASK
;
680 if (err
&& reset_needed
) {
681 iowrite32(SLI_PORT_CONTROL_IP_MASK
,
682 adapter
->db
+ SLIPORT_CONTROL_OFFSET
);
684 /* check if adapter has corrected the error */
685 status
= lancer_wait_ready(adapter
);
686 sliport_status
= ioread32(adapter
->db
+
687 SLIPORT_STATUS_OFFSET
);
688 sliport_status
&= (SLIPORT_STATUS_ERR_MASK
|
689 SLIPORT_STATUS_RN_MASK
);
690 if (status
|| sliport_status
)
692 } else if (err
|| reset_needed
) {
696 /* Stop error recovery if error is not recoverable.
697 * No resource error is temporary errors and will go away
698 * when PF provisions resources.
700 resource_error
= lancer_provisioning_error(adapter
);
707 int be_fw_wait_ready(struct be_adapter
*adapter
)
710 int status
, timeout
= 0;
711 struct device
*dev
= &adapter
->pdev
->dev
;
713 if (lancer_chip(adapter
)) {
714 status
= lancer_wait_ready(adapter
);
723 stage
= be_POST_stage_get(adapter
);
724 if (stage
== POST_STAGE_ARMFW_RDY
)
727 dev_info(dev
, "Waiting for POST, %ds elapsed\n", timeout
);
728 if (msleep_interruptible(2000)) {
729 dev_err(dev
, "Waiting for POST aborted\n");
733 } while (timeout
< 60);
736 dev_err(dev
, "POST timeout; stage=%#x\n", stage
);
740 static inline struct be_sge
*nonembedded_sgl(struct be_mcc_wrb
*wrb
)
742 return &wrb
->payload
.sgl
[0];
745 static inline void fill_wrb_tags(struct be_mcc_wrb
*wrb
, unsigned long addr
)
747 wrb
->tag0
= addr
& 0xFFFFFFFF;
748 wrb
->tag1
= upper_32_bits(addr
);
751 /* Don't touch the hdr after it's prepared */
752 /* mem will be NULL for embedded commands */
753 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr
*req_hdr
,
754 u8 subsystem
, u8 opcode
, int cmd_len
,
755 struct be_mcc_wrb
*wrb
,
756 struct be_dma_mem
*mem
)
760 req_hdr
->opcode
= opcode
;
761 req_hdr
->subsystem
= subsystem
;
762 req_hdr
->request_length
= cpu_to_le32(cmd_len
- sizeof(*req_hdr
));
763 req_hdr
->version
= 0;
764 fill_wrb_tags(wrb
, (ulong
) req_hdr
);
765 wrb
->payload_length
= cmd_len
;
767 wrb
->embedded
|= (1 & MCC_WRB_SGE_CNT_MASK
) <<
768 MCC_WRB_SGE_CNT_SHIFT
;
769 sge
= nonembedded_sgl(wrb
);
770 sge
->pa_hi
= cpu_to_le32(upper_32_bits(mem
->dma
));
771 sge
->pa_lo
= cpu_to_le32(mem
->dma
& 0xFFFFFFFF);
772 sge
->len
= cpu_to_le32(mem
->size
);
774 wrb
->embedded
|= MCC_WRB_EMBEDDED_MASK
;
775 be_dws_cpu_to_le(wrb
, 8);
778 static void be_cmd_page_addrs_prepare(struct phys_addr
*pages
, u32 max_pages
,
779 struct be_dma_mem
*mem
)
781 int i
, buf_pages
= min(PAGES_4K_SPANNED(mem
->va
, mem
->size
), max_pages
);
782 u64 dma
= (u64
)mem
->dma
;
784 for (i
= 0; i
< buf_pages
; i
++) {
785 pages
[i
].lo
= cpu_to_le32(dma
& 0xFFFFFFFF);
786 pages
[i
].hi
= cpu_to_le32(upper_32_bits(dma
));
791 static inline struct be_mcc_wrb
*wrb_from_mbox(struct be_adapter
*adapter
)
793 struct be_dma_mem
*mbox_mem
= &adapter
->mbox_mem
;
794 struct be_mcc_wrb
*wrb
795 = &((struct be_mcc_mailbox
*)(mbox_mem
->va
))->wrb
;
796 memset(wrb
, 0, sizeof(*wrb
));
800 static struct be_mcc_wrb
*wrb_from_mccq(struct be_adapter
*adapter
)
802 struct be_queue_info
*mccq
= &adapter
->mcc_obj
.q
;
803 struct be_mcc_wrb
*wrb
;
808 if (atomic_read(&mccq
->used
) >= mccq
->len
)
811 wrb
= queue_head_node(mccq
);
812 queue_head_inc(mccq
);
813 atomic_inc(&mccq
->used
);
814 memset(wrb
, 0, sizeof(*wrb
));
818 static bool use_mcc(struct be_adapter
*adapter
)
820 return adapter
->mcc_obj
.q
.created
;
823 /* Must be used only in process context */
824 static int be_cmd_lock(struct be_adapter
*adapter
)
826 if (use_mcc(adapter
)) {
827 spin_lock_bh(&adapter
->mcc_lock
);
830 return mutex_lock_interruptible(&adapter
->mbox_lock
);
834 /* Must be used only in process context */
835 static void be_cmd_unlock(struct be_adapter
*adapter
)
837 if (use_mcc(adapter
))
838 spin_unlock_bh(&adapter
->mcc_lock
);
840 return mutex_unlock(&adapter
->mbox_lock
);
843 static struct be_mcc_wrb
*be_cmd_copy(struct be_adapter
*adapter
,
844 struct be_mcc_wrb
*wrb
)
846 struct be_mcc_wrb
*dest_wrb
;
848 if (use_mcc(adapter
)) {
849 dest_wrb
= wrb_from_mccq(adapter
);
853 dest_wrb
= wrb_from_mbox(adapter
);
856 memcpy(dest_wrb
, wrb
, sizeof(*wrb
));
857 if (wrb
->embedded
& cpu_to_le32(MCC_WRB_EMBEDDED_MASK
))
858 fill_wrb_tags(dest_wrb
, (ulong
) embedded_payload(wrb
));
863 /* Must be used only in process context */
864 static int be_cmd_notify_wait(struct be_adapter
*adapter
,
865 struct be_mcc_wrb
*wrb
)
867 struct be_mcc_wrb
*dest_wrb
;
870 status
= be_cmd_lock(adapter
);
874 dest_wrb
= be_cmd_copy(adapter
, wrb
);
878 if (use_mcc(adapter
))
879 status
= be_mcc_notify_wait(adapter
);
881 status
= be_mbox_notify_wait(adapter
);
884 memcpy(wrb
, dest_wrb
, sizeof(*wrb
));
886 be_cmd_unlock(adapter
);
890 /* Tell fw we're about to start firing cmds by writing a
891 * special pattern across the wrb hdr; uses mbox
893 int be_cmd_fw_init(struct be_adapter
*adapter
)
898 if (lancer_chip(adapter
))
901 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
904 wrb
= (u8
*)wrb_from_mbox(adapter
);
914 status
= be_mbox_notify_wait(adapter
);
916 mutex_unlock(&adapter
->mbox_lock
);
920 /* Tell fw we're done with firing cmds by writing a
921 * special pattern across the wrb hdr; uses mbox
923 int be_cmd_fw_clean(struct be_adapter
*adapter
)
928 if (lancer_chip(adapter
))
931 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
934 wrb
= (u8
*)wrb_from_mbox(adapter
);
944 status
= be_mbox_notify_wait(adapter
);
946 mutex_unlock(&adapter
->mbox_lock
);
950 int be_cmd_eq_create(struct be_adapter
*adapter
, struct be_eq_obj
*eqo
)
952 struct be_mcc_wrb
*wrb
;
953 struct be_cmd_req_eq_create
*req
;
954 struct be_dma_mem
*q_mem
= &eqo
->q
.dma_mem
;
957 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
960 wrb
= wrb_from_mbox(adapter
);
961 req
= embedded_payload(wrb
);
963 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
964 OPCODE_COMMON_EQ_CREATE
, sizeof(*req
), wrb
,
967 /* Support for EQ_CREATEv2 available only SH-R onwards */
968 if (!(BEx_chip(adapter
) || lancer_chip(adapter
)))
971 req
->hdr
.version
= ver
;
972 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
974 AMAP_SET_BITS(struct amap_eq_context
, valid
, req
->context
, 1);
976 AMAP_SET_BITS(struct amap_eq_context
, size
, req
->context
, 0);
977 AMAP_SET_BITS(struct amap_eq_context
, count
, req
->context
,
978 __ilog2_u32(eqo
->q
.len
/ 256));
979 be_dws_cpu_to_le(req
->context
, sizeof(req
->context
));
981 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
983 status
= be_mbox_notify_wait(adapter
);
985 struct be_cmd_resp_eq_create
*resp
= embedded_payload(wrb
);
987 eqo
->q
.id
= le16_to_cpu(resp
->eq_id
);
989 (ver
== 2) ? le16_to_cpu(resp
->msix_idx
) : eqo
->idx
;
990 eqo
->q
.created
= true;
993 mutex_unlock(&adapter
->mbox_lock
);
998 int be_cmd_mac_addr_query(struct be_adapter
*adapter
, u8
*mac_addr
,
999 bool permanent
, u32 if_handle
, u32 pmac_id
)
1001 struct be_mcc_wrb
*wrb
;
1002 struct be_cmd_req_mac_query
*req
;
1005 spin_lock_bh(&adapter
->mcc_lock
);
1007 wrb
= wrb_from_mccq(adapter
);
1012 req
= embedded_payload(wrb
);
1014 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1015 OPCODE_COMMON_NTWK_MAC_QUERY
, sizeof(*req
), wrb
,
1017 req
->type
= MAC_ADDRESS_TYPE_NETWORK
;
1021 req
->if_id
= cpu_to_le16((u16
)if_handle
);
1022 req
->pmac_id
= cpu_to_le32(pmac_id
);
1026 status
= be_mcc_notify_wait(adapter
);
1028 struct be_cmd_resp_mac_query
*resp
= embedded_payload(wrb
);
1030 memcpy(mac_addr
, resp
->mac
.addr
, ETH_ALEN
);
1034 spin_unlock_bh(&adapter
->mcc_lock
);
1038 /* Uses synchronous MCCQ */
1039 int be_cmd_pmac_add(struct be_adapter
*adapter
, u8
*mac_addr
,
1040 u32 if_id
, u32
*pmac_id
, u32 domain
)
1042 struct be_mcc_wrb
*wrb
;
1043 struct be_cmd_req_pmac_add
*req
;
1046 spin_lock_bh(&adapter
->mcc_lock
);
1048 wrb
= wrb_from_mccq(adapter
);
1053 req
= embedded_payload(wrb
);
1055 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1056 OPCODE_COMMON_NTWK_PMAC_ADD
, sizeof(*req
), wrb
,
1059 req
->hdr
.domain
= domain
;
1060 req
->if_id
= cpu_to_le32(if_id
);
1061 memcpy(req
->mac_address
, mac_addr
, ETH_ALEN
);
1063 status
= be_mcc_notify_wait(adapter
);
1065 struct be_cmd_resp_pmac_add
*resp
= embedded_payload(wrb
);
1067 *pmac_id
= le32_to_cpu(resp
->pmac_id
);
1071 spin_unlock_bh(&adapter
->mcc_lock
);
1073 if (status
== MCC_STATUS_UNAUTHORIZED_REQUEST
)
1079 /* Uses synchronous MCCQ */
1080 int be_cmd_pmac_del(struct be_adapter
*adapter
, u32 if_id
, int pmac_id
, u32 dom
)
1082 struct be_mcc_wrb
*wrb
;
1083 struct be_cmd_req_pmac_del
*req
;
1089 spin_lock_bh(&adapter
->mcc_lock
);
1091 wrb
= wrb_from_mccq(adapter
);
1096 req
= embedded_payload(wrb
);
1098 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1099 OPCODE_COMMON_NTWK_PMAC_DEL
, sizeof(*req
),
1102 req
->hdr
.domain
= dom
;
1103 req
->if_id
= cpu_to_le32(if_id
);
1104 req
->pmac_id
= cpu_to_le32(pmac_id
);
1106 status
= be_mcc_notify_wait(adapter
);
1109 spin_unlock_bh(&adapter
->mcc_lock
);
1114 int be_cmd_cq_create(struct be_adapter
*adapter
, struct be_queue_info
*cq
,
1115 struct be_queue_info
*eq
, bool no_delay
, int coalesce_wm
)
1117 struct be_mcc_wrb
*wrb
;
1118 struct be_cmd_req_cq_create
*req
;
1119 struct be_dma_mem
*q_mem
= &cq
->dma_mem
;
1123 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1126 wrb
= wrb_from_mbox(adapter
);
1127 req
= embedded_payload(wrb
);
1128 ctxt
= &req
->context
;
1130 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1131 OPCODE_COMMON_CQ_CREATE
, sizeof(*req
), wrb
,
1134 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
1136 if (BEx_chip(adapter
)) {
1137 AMAP_SET_BITS(struct amap_cq_context_be
, coalescwm
, ctxt
,
1139 AMAP_SET_BITS(struct amap_cq_context_be
, nodelay
,
1141 AMAP_SET_BITS(struct amap_cq_context_be
, count
, ctxt
,
1142 __ilog2_u32(cq
->len
/ 256));
1143 AMAP_SET_BITS(struct amap_cq_context_be
, valid
, ctxt
, 1);
1144 AMAP_SET_BITS(struct amap_cq_context_be
, eventable
, ctxt
, 1);
1145 AMAP_SET_BITS(struct amap_cq_context_be
, eqid
, ctxt
, eq
->id
);
1147 req
->hdr
.version
= 2;
1148 req
->page_size
= 1; /* 1 for 4K */
1150 /* coalesce-wm field in this cmd is not relevant to Lancer.
1151 * Lancer uses COMMON_MODIFY_CQ to set this field
1153 if (!lancer_chip(adapter
))
1154 AMAP_SET_BITS(struct amap_cq_context_v2
, coalescwm
,
1156 AMAP_SET_BITS(struct amap_cq_context_v2
, nodelay
, ctxt
,
1158 AMAP_SET_BITS(struct amap_cq_context_v2
, count
, ctxt
,
1159 __ilog2_u32(cq
->len
/ 256));
1160 AMAP_SET_BITS(struct amap_cq_context_v2
, valid
, ctxt
, 1);
1161 AMAP_SET_BITS(struct amap_cq_context_v2
, eventable
, ctxt
, 1);
1162 AMAP_SET_BITS(struct amap_cq_context_v2
, eqid
, ctxt
, eq
->id
);
1165 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
1167 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
1169 status
= be_mbox_notify_wait(adapter
);
1171 struct be_cmd_resp_cq_create
*resp
= embedded_payload(wrb
);
1173 cq
->id
= le16_to_cpu(resp
->cq_id
);
1177 mutex_unlock(&adapter
->mbox_lock
);
1182 static u32
be_encoded_q_len(int q_len
)
1184 u32 len_encoded
= fls(q_len
); /* log2(len) + 1 */
1186 if (len_encoded
== 16)
1191 static int be_cmd_mccq_ext_create(struct be_adapter
*adapter
,
1192 struct be_queue_info
*mccq
,
1193 struct be_queue_info
*cq
)
1195 struct be_mcc_wrb
*wrb
;
1196 struct be_cmd_req_mcc_ext_create
*req
;
1197 struct be_dma_mem
*q_mem
= &mccq
->dma_mem
;
1201 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1204 wrb
= wrb_from_mbox(adapter
);
1205 req
= embedded_payload(wrb
);
1206 ctxt
= &req
->context
;
1208 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1209 OPCODE_COMMON_MCC_CREATE_EXT
, sizeof(*req
), wrb
,
1212 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
1213 if (BEx_chip(adapter
)) {
1214 AMAP_SET_BITS(struct amap_mcc_context_be
, valid
, ctxt
, 1);
1215 AMAP_SET_BITS(struct amap_mcc_context_be
, ring_size
, ctxt
,
1216 be_encoded_q_len(mccq
->len
));
1217 AMAP_SET_BITS(struct amap_mcc_context_be
, cq_id
, ctxt
, cq
->id
);
1219 req
->hdr
.version
= 1;
1220 req
->cq_id
= cpu_to_le16(cq
->id
);
1222 AMAP_SET_BITS(struct amap_mcc_context_v1
, ring_size
, ctxt
,
1223 be_encoded_q_len(mccq
->len
));
1224 AMAP_SET_BITS(struct amap_mcc_context_v1
, valid
, ctxt
, 1);
1225 AMAP_SET_BITS(struct amap_mcc_context_v1
, async_cq_id
,
1227 AMAP_SET_BITS(struct amap_mcc_context_v1
, async_cq_valid
,
1231 /* Subscribe to Link State, Sliport Event and Group 5 Events
1232 * (bits 1, 5 and 17 set)
1234 req
->async_event_bitmap
[0] =
1235 cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE
) |
1236 BIT(ASYNC_EVENT_CODE_GRP_5
) |
1237 BIT(ASYNC_EVENT_CODE_QNQ
) |
1238 BIT(ASYNC_EVENT_CODE_SLIPORT
));
1240 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
1242 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
1244 status
= be_mbox_notify_wait(adapter
);
1246 struct be_cmd_resp_mcc_create
*resp
= embedded_payload(wrb
);
1248 mccq
->id
= le16_to_cpu(resp
->id
);
1249 mccq
->created
= true;
1251 mutex_unlock(&adapter
->mbox_lock
);
1256 static int be_cmd_mccq_org_create(struct be_adapter
*adapter
,
1257 struct be_queue_info
*mccq
,
1258 struct be_queue_info
*cq
)
1260 struct be_mcc_wrb
*wrb
;
1261 struct be_cmd_req_mcc_create
*req
;
1262 struct be_dma_mem
*q_mem
= &mccq
->dma_mem
;
1266 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1269 wrb
= wrb_from_mbox(adapter
);
1270 req
= embedded_payload(wrb
);
1271 ctxt
= &req
->context
;
1273 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1274 OPCODE_COMMON_MCC_CREATE
, sizeof(*req
), wrb
,
1277 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
1279 AMAP_SET_BITS(struct amap_mcc_context_be
, valid
, ctxt
, 1);
1280 AMAP_SET_BITS(struct amap_mcc_context_be
, ring_size
, ctxt
,
1281 be_encoded_q_len(mccq
->len
));
1282 AMAP_SET_BITS(struct amap_mcc_context_be
, cq_id
, ctxt
, cq
->id
);
1284 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
1286 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
1288 status
= be_mbox_notify_wait(adapter
);
1290 struct be_cmd_resp_mcc_create
*resp
= embedded_payload(wrb
);
1292 mccq
->id
= le16_to_cpu(resp
->id
);
1293 mccq
->created
= true;
1296 mutex_unlock(&adapter
->mbox_lock
);
1300 int be_cmd_mccq_create(struct be_adapter
*adapter
,
1301 struct be_queue_info
*mccq
, struct be_queue_info
*cq
)
1305 status
= be_cmd_mccq_ext_create(adapter
, mccq
, cq
);
1306 if (status
&& BEx_chip(adapter
)) {
1307 dev_warn(&adapter
->pdev
->dev
, "Upgrade to F/W ver 2.102.235.0 "
1308 "or newer to avoid conflicting priorities between NIC "
1309 "and FCoE traffic");
1310 status
= be_cmd_mccq_org_create(adapter
, mccq
, cq
);
1315 int be_cmd_txq_create(struct be_adapter
*adapter
, struct be_tx_obj
*txo
)
1317 struct be_mcc_wrb wrb
= {0};
1318 struct be_cmd_req_eth_tx_create
*req
;
1319 struct be_queue_info
*txq
= &txo
->q
;
1320 struct be_queue_info
*cq
= &txo
->cq
;
1321 struct be_dma_mem
*q_mem
= &txq
->dma_mem
;
1322 int status
, ver
= 0;
1324 req
= embedded_payload(&wrb
);
1325 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1326 OPCODE_ETH_TX_CREATE
, sizeof(*req
), &wrb
, NULL
);
1328 if (lancer_chip(adapter
)) {
1329 req
->hdr
.version
= 1;
1330 } else if (BEx_chip(adapter
)) {
1331 if (adapter
->function_caps
& BE_FUNCTION_CAPS_SUPER_NIC
)
1332 req
->hdr
.version
= 2;
1333 } else { /* For SH */
1334 req
->hdr
.version
= 2;
1337 if (req
->hdr
.version
> 0)
1338 req
->if_id
= cpu_to_le16(adapter
->if_handle
);
1339 req
->num_pages
= PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
);
1340 req
->ulp_num
= BE_ULP1_NUM
;
1341 req
->type
= BE_ETH_TX_RING_TYPE_STANDARD
;
1342 req
->cq_id
= cpu_to_le16(cq
->id
);
1343 req
->queue_size
= be_encoded_q_len(txq
->len
);
1344 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
1345 ver
= req
->hdr
.version
;
1347 status
= be_cmd_notify_wait(adapter
, &wrb
);
1349 struct be_cmd_resp_eth_tx_create
*resp
= embedded_payload(&wrb
);
1351 txq
->id
= le16_to_cpu(resp
->cid
);
1353 txo
->db_offset
= le32_to_cpu(resp
->db_offset
);
1355 txo
->db_offset
= DB_TXULP1_OFFSET
;
1356 txq
->created
= true;
1363 int be_cmd_rxq_create(struct be_adapter
*adapter
,
1364 struct be_queue_info
*rxq
, u16 cq_id
, u16 frag_size
,
1365 u32 if_id
, u32 rss
, u8
*rss_id
)
1367 struct be_mcc_wrb
*wrb
;
1368 struct be_cmd_req_eth_rx_create
*req
;
1369 struct be_dma_mem
*q_mem
= &rxq
->dma_mem
;
1372 spin_lock_bh(&adapter
->mcc_lock
);
1374 wrb
= wrb_from_mccq(adapter
);
1379 req
= embedded_payload(wrb
);
1381 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1382 OPCODE_ETH_RX_CREATE
, sizeof(*req
), wrb
, NULL
);
1384 req
->cq_id
= cpu_to_le16(cq_id
);
1385 req
->frag_size
= fls(frag_size
) - 1;
1387 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
1388 req
->interface_id
= cpu_to_le32(if_id
);
1389 req
->max_frame_size
= cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE
);
1390 req
->rss_queue
= cpu_to_le32(rss
);
1392 status
= be_mcc_notify_wait(adapter
);
1394 struct be_cmd_resp_eth_rx_create
*resp
= embedded_payload(wrb
);
1396 rxq
->id
= le16_to_cpu(resp
->id
);
1397 rxq
->created
= true;
1398 *rss_id
= resp
->rss_id
;
1402 spin_unlock_bh(&adapter
->mcc_lock
);
1406 /* Generic destroyer function for all types of queues
1409 int be_cmd_q_destroy(struct be_adapter
*adapter
, struct be_queue_info
*q
,
1412 struct be_mcc_wrb
*wrb
;
1413 struct be_cmd_req_q_destroy
*req
;
1414 u8 subsys
= 0, opcode
= 0;
1417 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1420 wrb
= wrb_from_mbox(adapter
);
1421 req
= embedded_payload(wrb
);
1423 switch (queue_type
) {
1425 subsys
= CMD_SUBSYSTEM_COMMON
;
1426 opcode
= OPCODE_COMMON_EQ_DESTROY
;
1429 subsys
= CMD_SUBSYSTEM_COMMON
;
1430 opcode
= OPCODE_COMMON_CQ_DESTROY
;
1433 subsys
= CMD_SUBSYSTEM_ETH
;
1434 opcode
= OPCODE_ETH_TX_DESTROY
;
1437 subsys
= CMD_SUBSYSTEM_ETH
;
1438 opcode
= OPCODE_ETH_RX_DESTROY
;
1441 subsys
= CMD_SUBSYSTEM_COMMON
;
1442 opcode
= OPCODE_COMMON_MCC_DESTROY
;
1448 be_wrb_cmd_hdr_prepare(&req
->hdr
, subsys
, opcode
, sizeof(*req
), wrb
,
1450 req
->id
= cpu_to_le16(q
->id
);
1452 status
= be_mbox_notify_wait(adapter
);
1455 mutex_unlock(&adapter
->mbox_lock
);
1460 int be_cmd_rxq_destroy(struct be_adapter
*adapter
, struct be_queue_info
*q
)
1462 struct be_mcc_wrb
*wrb
;
1463 struct be_cmd_req_q_destroy
*req
;
1466 spin_lock_bh(&adapter
->mcc_lock
);
1468 wrb
= wrb_from_mccq(adapter
);
1473 req
= embedded_payload(wrb
);
1475 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1476 OPCODE_ETH_RX_DESTROY
, sizeof(*req
), wrb
, NULL
);
1477 req
->id
= cpu_to_le16(q
->id
);
1479 status
= be_mcc_notify_wait(adapter
);
1483 spin_unlock_bh(&adapter
->mcc_lock
);
1487 /* Create an rx filtering policy configuration on an i/f
1488 * Will use MBOX only if MCCQ has not been created.
1490 int be_cmd_if_create(struct be_adapter
*adapter
, u32 cap_flags
, u32 en_flags
,
1491 u32
*if_handle
, u32 domain
)
1493 struct be_mcc_wrb wrb
= {0};
1494 struct be_cmd_req_if_create
*req
;
1497 req
= embedded_payload(&wrb
);
1498 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1499 OPCODE_COMMON_NTWK_INTERFACE_CREATE
,
1500 sizeof(*req
), &wrb
, NULL
);
1501 req
->hdr
.domain
= domain
;
1502 req
->capability_flags
= cpu_to_le32(cap_flags
);
1503 req
->enable_flags
= cpu_to_le32(en_flags
);
1504 req
->pmac_invalid
= true;
1506 status
= be_cmd_notify_wait(adapter
, &wrb
);
1508 struct be_cmd_resp_if_create
*resp
= embedded_payload(&wrb
);
1510 *if_handle
= le32_to_cpu(resp
->interface_id
);
1512 /* Hack to retrieve VF's pmac-id on BE3 */
1513 if (BE3_chip(adapter
) && !be_physfn(adapter
))
1514 adapter
->pmac_id
[0] = le32_to_cpu(resp
->pmac_id
);
1520 int be_cmd_if_destroy(struct be_adapter
*adapter
, int interface_id
, u32 domain
)
1522 struct be_mcc_wrb
*wrb
;
1523 struct be_cmd_req_if_destroy
*req
;
1526 if (interface_id
== -1)
1529 spin_lock_bh(&adapter
->mcc_lock
);
1531 wrb
= wrb_from_mccq(adapter
);
1536 req
= embedded_payload(wrb
);
1538 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1539 OPCODE_COMMON_NTWK_INTERFACE_DESTROY
,
1540 sizeof(*req
), wrb
, NULL
);
1541 req
->hdr
.domain
= domain
;
1542 req
->interface_id
= cpu_to_le32(interface_id
);
1544 status
= be_mcc_notify_wait(adapter
);
1546 spin_unlock_bh(&adapter
->mcc_lock
);
1550 /* Get stats is a non embedded command: the request is not embedded inside
1551 * WRB but is a separate dma memory block
1552 * Uses asynchronous MCC
1554 int be_cmd_get_stats(struct be_adapter
*adapter
, struct be_dma_mem
*nonemb_cmd
)
1556 struct be_mcc_wrb
*wrb
;
1557 struct be_cmd_req_hdr
*hdr
;
1560 spin_lock_bh(&adapter
->mcc_lock
);
1562 wrb
= wrb_from_mccq(adapter
);
1567 hdr
= nonemb_cmd
->va
;
1569 be_wrb_cmd_hdr_prepare(hdr
, CMD_SUBSYSTEM_ETH
,
1570 OPCODE_ETH_GET_STATISTICS
, nonemb_cmd
->size
, wrb
,
1573 /* version 1 of the cmd is not supported only by BE2 */
1574 if (BE2_chip(adapter
))
1576 if (BE3_chip(adapter
) || lancer_chip(adapter
))
1581 be_mcc_notify(adapter
);
1582 adapter
->stats_cmd_sent
= true;
1585 spin_unlock_bh(&adapter
->mcc_lock
);
1590 int lancer_cmd_get_pport_stats(struct be_adapter
*adapter
,
1591 struct be_dma_mem
*nonemb_cmd
)
1593 struct be_mcc_wrb
*wrb
;
1594 struct lancer_cmd_req_pport_stats
*req
;
1597 if (!be_cmd_allowed(adapter
, OPCODE_ETH_GET_PPORT_STATS
,
1601 spin_lock_bh(&adapter
->mcc_lock
);
1603 wrb
= wrb_from_mccq(adapter
);
1608 req
= nonemb_cmd
->va
;
1610 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1611 OPCODE_ETH_GET_PPORT_STATS
, nonemb_cmd
->size
,
1614 req
->cmd_params
.params
.pport_num
= cpu_to_le16(adapter
->hba_port_num
);
1615 req
->cmd_params
.params
.reset_stats
= 0;
1617 be_mcc_notify(adapter
);
1618 adapter
->stats_cmd_sent
= true;
1621 spin_unlock_bh(&adapter
->mcc_lock
);
1625 static int be_mac_to_link_speed(int mac_speed
)
1627 switch (mac_speed
) {
1628 case PHY_LINK_SPEED_ZERO
:
1630 case PHY_LINK_SPEED_10MBPS
:
1632 case PHY_LINK_SPEED_100MBPS
:
1634 case PHY_LINK_SPEED_1GBPS
:
1636 case PHY_LINK_SPEED_10GBPS
:
1638 case PHY_LINK_SPEED_20GBPS
:
1640 case PHY_LINK_SPEED_25GBPS
:
1642 case PHY_LINK_SPEED_40GBPS
:
1648 /* Uses synchronous mcc
1649 * Returns link_speed in Mbps
1651 int be_cmd_link_status_query(struct be_adapter
*adapter
, u16
*link_speed
,
1652 u8
*link_status
, u32 dom
)
1654 struct be_mcc_wrb
*wrb
;
1655 struct be_cmd_req_link_status
*req
;
1658 spin_lock_bh(&adapter
->mcc_lock
);
1661 *link_status
= LINK_DOWN
;
1663 wrb
= wrb_from_mccq(adapter
);
1668 req
= embedded_payload(wrb
);
1670 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1671 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY
,
1672 sizeof(*req
), wrb
, NULL
);
1674 /* version 1 of the cmd is not supported only by BE2 */
1675 if (!BE2_chip(adapter
))
1676 req
->hdr
.version
= 1;
1678 req
->hdr
.domain
= dom
;
1680 status
= be_mcc_notify_wait(adapter
);
1682 struct be_cmd_resp_link_status
*resp
= embedded_payload(wrb
);
1685 *link_speed
= resp
->link_speed
?
1686 le16_to_cpu(resp
->link_speed
) * 10 :
1687 be_mac_to_link_speed(resp
->mac_speed
);
1689 if (!resp
->logical_link_status
)
1693 *link_status
= resp
->logical_link_status
;
1697 spin_unlock_bh(&adapter
->mcc_lock
);
1701 /* Uses synchronous mcc */
1702 int be_cmd_get_die_temperature(struct be_adapter
*adapter
)
1704 struct be_mcc_wrb
*wrb
;
1705 struct be_cmd_req_get_cntl_addnl_attribs
*req
;
1708 spin_lock_bh(&adapter
->mcc_lock
);
1710 wrb
= wrb_from_mccq(adapter
);
1715 req
= embedded_payload(wrb
);
1717 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1718 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES
,
1719 sizeof(*req
), wrb
, NULL
);
1721 be_mcc_notify(adapter
);
1724 spin_unlock_bh(&adapter
->mcc_lock
);
1728 /* Uses synchronous mcc */
1729 int be_cmd_get_reg_len(struct be_adapter
*adapter
, u32
*log_size
)
1731 struct be_mcc_wrb
*wrb
;
1732 struct be_cmd_req_get_fat
*req
;
1735 spin_lock_bh(&adapter
->mcc_lock
);
1737 wrb
= wrb_from_mccq(adapter
);
1742 req
= embedded_payload(wrb
);
1744 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1745 OPCODE_COMMON_MANAGE_FAT
, sizeof(*req
), wrb
,
1747 req
->fat_operation
= cpu_to_le32(QUERY_FAT
);
1748 status
= be_mcc_notify_wait(adapter
);
1750 struct be_cmd_resp_get_fat
*resp
= embedded_payload(wrb
);
1752 if (log_size
&& resp
->log_size
)
1753 *log_size
= le32_to_cpu(resp
->log_size
) -
1757 spin_unlock_bh(&adapter
->mcc_lock
);
1761 int be_cmd_get_regs(struct be_adapter
*adapter
, u32 buf_len
, void *buf
)
1763 struct be_dma_mem get_fat_cmd
;
1764 struct be_mcc_wrb
*wrb
;
1765 struct be_cmd_req_get_fat
*req
;
1766 u32 offset
= 0, total_size
, buf_size
,
1767 log_offset
= sizeof(u32
), payload_len
;
1773 total_size
= buf_len
;
1775 get_fat_cmd
.size
= sizeof(struct be_cmd_req_get_fat
) + 60*1024;
1776 get_fat_cmd
.va
= pci_alloc_consistent(adapter
->pdev
,
1779 if (!get_fat_cmd
.va
) {
1780 dev_err(&adapter
->pdev
->dev
,
1781 "Memory allocation failure while reading FAT data\n");
1785 spin_lock_bh(&adapter
->mcc_lock
);
1787 while (total_size
) {
1788 buf_size
= min(total_size
, (u32
)60*1024);
1789 total_size
-= buf_size
;
1791 wrb
= wrb_from_mccq(adapter
);
1796 req
= get_fat_cmd
.va
;
1798 payload_len
= sizeof(struct be_cmd_req_get_fat
) + buf_size
;
1799 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1800 OPCODE_COMMON_MANAGE_FAT
, payload_len
,
1803 req
->fat_operation
= cpu_to_le32(RETRIEVE_FAT
);
1804 req
->read_log_offset
= cpu_to_le32(log_offset
);
1805 req
->read_log_length
= cpu_to_le32(buf_size
);
1806 req
->data_buffer_size
= cpu_to_le32(buf_size
);
1808 status
= be_mcc_notify_wait(adapter
);
1810 struct be_cmd_resp_get_fat
*resp
= get_fat_cmd
.va
;
1812 memcpy(buf
+ offset
,
1814 le32_to_cpu(resp
->read_log_length
));
1816 dev_err(&adapter
->pdev
->dev
, "FAT Table Retrieve error\n");
1820 log_offset
+= buf_size
;
1823 pci_free_consistent(adapter
->pdev
, get_fat_cmd
.size
,
1824 get_fat_cmd
.va
, get_fat_cmd
.dma
);
1825 spin_unlock_bh(&adapter
->mcc_lock
);
1829 /* Uses synchronous mcc */
1830 int be_cmd_get_fw_ver(struct be_adapter
*adapter
)
1832 struct be_mcc_wrb
*wrb
;
1833 struct be_cmd_req_get_fw_version
*req
;
1836 spin_lock_bh(&adapter
->mcc_lock
);
1838 wrb
= wrb_from_mccq(adapter
);
1844 req
= embedded_payload(wrb
);
1846 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1847 OPCODE_COMMON_GET_FW_VERSION
, sizeof(*req
), wrb
,
1849 status
= be_mcc_notify_wait(adapter
);
1851 struct be_cmd_resp_get_fw_version
*resp
= embedded_payload(wrb
);
1853 strlcpy(adapter
->fw_ver
, resp
->firmware_version_string
,
1854 sizeof(adapter
->fw_ver
));
1855 strlcpy(adapter
->fw_on_flash
, resp
->fw_on_flash_version_string
,
1856 sizeof(adapter
->fw_on_flash
));
1859 spin_unlock_bh(&adapter
->mcc_lock
);
1863 /* set the EQ delay interval of an EQ to specified value
1866 static int __be_cmd_modify_eqd(struct be_adapter
*adapter
,
1867 struct be_set_eqd
*set_eqd
, int num
)
1869 struct be_mcc_wrb
*wrb
;
1870 struct be_cmd_req_modify_eq_delay
*req
;
1873 spin_lock_bh(&adapter
->mcc_lock
);
1875 wrb
= wrb_from_mccq(adapter
);
1880 req
= embedded_payload(wrb
);
1882 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1883 OPCODE_COMMON_MODIFY_EQ_DELAY
, sizeof(*req
), wrb
,
1886 req
->num_eq
= cpu_to_le32(num
);
1887 for (i
= 0; i
< num
; i
++) {
1888 req
->set_eqd
[i
].eq_id
= cpu_to_le32(set_eqd
[i
].eq_id
);
1889 req
->set_eqd
[i
].phase
= 0;
1890 req
->set_eqd
[i
].delay_multiplier
=
1891 cpu_to_le32(set_eqd
[i
].delay_multiplier
);
1894 be_mcc_notify(adapter
);
1896 spin_unlock_bh(&adapter
->mcc_lock
);
1900 int be_cmd_modify_eqd(struct be_adapter
*adapter
, struct be_set_eqd
*set_eqd
,
1906 num_eqs
= min(num
, 8);
1907 __be_cmd_modify_eqd(adapter
, &set_eqd
[i
], num_eqs
);
1915 /* Uses sycnhronous mcc */
1916 int be_cmd_vlan_config(struct be_adapter
*adapter
, u32 if_id
, u16
*vtag_array
,
1917 u32 num
, u32 domain
)
1919 struct be_mcc_wrb
*wrb
;
1920 struct be_cmd_req_vlan_config
*req
;
1923 spin_lock_bh(&adapter
->mcc_lock
);
1925 wrb
= wrb_from_mccq(adapter
);
1930 req
= embedded_payload(wrb
);
1932 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1933 OPCODE_COMMON_NTWK_VLAN_CONFIG
, sizeof(*req
),
1935 req
->hdr
.domain
= domain
;
1937 req
->interface_id
= if_id
;
1938 req
->untagged
= BE_IF_FLAGS_UNTAGGED
& be_if_cap_flags(adapter
) ? 1 : 0;
1939 req
->num_vlan
= num
;
1940 memcpy(req
->normal_vlan
, vtag_array
,
1941 req
->num_vlan
* sizeof(vtag_array
[0]));
1943 status
= be_mcc_notify_wait(adapter
);
1945 spin_unlock_bh(&adapter
->mcc_lock
);
1949 static int __be_cmd_rx_filter(struct be_adapter
*adapter
, u32 flags
, u32 value
)
1951 struct be_mcc_wrb
*wrb
;
1952 struct be_dma_mem
*mem
= &adapter
->rx_filter
;
1953 struct be_cmd_req_rx_filter
*req
= mem
->va
;
1956 spin_lock_bh(&adapter
->mcc_lock
);
1958 wrb
= wrb_from_mccq(adapter
);
1963 memset(req
, 0, sizeof(*req
));
1964 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1965 OPCODE_COMMON_NTWK_RX_FILTER
, sizeof(*req
),
1968 req
->if_id
= cpu_to_le32(adapter
->if_handle
);
1969 req
->if_flags_mask
= cpu_to_le32(flags
);
1970 req
->if_flags
= (value
== ON
) ? req
->if_flags_mask
: 0;
1972 if (flags
& BE_IF_FLAGS_MULTICAST
) {
1973 struct netdev_hw_addr
*ha
;
1976 /* Reset mcast promisc mode if already set by setting mask
1977 * and not setting flags field
1979 req
->if_flags_mask
|=
1980 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS
&
1981 be_if_cap_flags(adapter
));
1982 req
->mcast_num
= cpu_to_le32(netdev_mc_count(adapter
->netdev
));
1983 netdev_for_each_mc_addr(ha
, adapter
->netdev
)
1984 memcpy(req
->mcast_mac
[i
++].byte
, ha
->addr
, ETH_ALEN
);
1987 status
= be_mcc_notify_wait(adapter
);
1989 spin_unlock_bh(&adapter
->mcc_lock
);
1993 int be_cmd_rx_filter(struct be_adapter
*adapter
, u32 flags
, u32 value
)
1995 struct device
*dev
= &adapter
->pdev
->dev
;
1997 if ((flags
& be_if_cap_flags(adapter
)) != flags
) {
1998 dev_warn(dev
, "Cannot set rx filter flags 0x%x\n", flags
);
1999 dev_warn(dev
, "Interface is capable of 0x%x flags only\n",
2000 be_if_cap_flags(adapter
));
2002 flags
&= be_if_cap_flags(adapter
);
2004 return __be_cmd_rx_filter(adapter
, flags
, value
);
2007 /* Uses synchrounous mcc */
2008 int be_cmd_set_flow_control(struct be_adapter
*adapter
, u32 tx_fc
, u32 rx_fc
)
2010 struct be_mcc_wrb
*wrb
;
2011 struct be_cmd_req_set_flow_control
*req
;
2014 if (!be_cmd_allowed(adapter
, OPCODE_COMMON_SET_FLOW_CONTROL
,
2015 CMD_SUBSYSTEM_COMMON
))
2018 spin_lock_bh(&adapter
->mcc_lock
);
2020 wrb
= wrb_from_mccq(adapter
);
2025 req
= embedded_payload(wrb
);
2027 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2028 OPCODE_COMMON_SET_FLOW_CONTROL
, sizeof(*req
),
2031 req
->hdr
.version
= 1;
2032 req
->tx_flow_control
= cpu_to_le16((u16
)tx_fc
);
2033 req
->rx_flow_control
= cpu_to_le16((u16
)rx_fc
);
2035 status
= be_mcc_notify_wait(adapter
);
2038 spin_unlock_bh(&adapter
->mcc_lock
);
2040 if (base_status(status
) == MCC_STATUS_FEATURE_NOT_SUPPORTED
)
2047 int be_cmd_get_flow_control(struct be_adapter
*adapter
, u32
*tx_fc
, u32
*rx_fc
)
2049 struct be_mcc_wrb
*wrb
;
2050 struct be_cmd_req_get_flow_control
*req
;
2053 if (!be_cmd_allowed(adapter
, OPCODE_COMMON_GET_FLOW_CONTROL
,
2054 CMD_SUBSYSTEM_COMMON
))
2057 spin_lock_bh(&adapter
->mcc_lock
);
2059 wrb
= wrb_from_mccq(adapter
);
2064 req
= embedded_payload(wrb
);
2066 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2067 OPCODE_COMMON_GET_FLOW_CONTROL
, sizeof(*req
),
2070 status
= be_mcc_notify_wait(adapter
);
2072 struct be_cmd_resp_get_flow_control
*resp
=
2073 embedded_payload(wrb
);
2075 *tx_fc
= le16_to_cpu(resp
->tx_flow_control
);
2076 *rx_fc
= le16_to_cpu(resp
->rx_flow_control
);
2080 spin_unlock_bh(&adapter
->mcc_lock
);
2085 int be_cmd_query_fw_cfg(struct be_adapter
*adapter
)
2087 struct be_mcc_wrb
*wrb
;
2088 struct be_cmd_req_query_fw_cfg
*req
;
2091 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
2094 wrb
= wrb_from_mbox(adapter
);
2095 req
= embedded_payload(wrb
);
2097 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2098 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG
,
2099 sizeof(*req
), wrb
, NULL
);
2101 status
= be_mbox_notify_wait(adapter
);
2103 struct be_cmd_resp_query_fw_cfg
*resp
= embedded_payload(wrb
);
2105 adapter
->port_num
= le32_to_cpu(resp
->phys_port
);
2106 adapter
->function_mode
= le32_to_cpu(resp
->function_mode
);
2107 adapter
->function_caps
= le32_to_cpu(resp
->function_caps
);
2108 adapter
->asic_rev
= le32_to_cpu(resp
->asic_revision
) & 0xFF;
2109 dev_info(&adapter
->pdev
->dev
,
2110 "FW config: function_mode=0x%x, function_caps=0x%x\n",
2111 adapter
->function_mode
, adapter
->function_caps
);
2114 mutex_unlock(&adapter
->mbox_lock
);
2119 int be_cmd_reset_function(struct be_adapter
*adapter
)
2121 struct be_mcc_wrb
*wrb
;
2122 struct be_cmd_req_hdr
*req
;
2125 if (lancer_chip(adapter
)) {
2126 status
= lancer_wait_ready(adapter
);
2128 iowrite32(SLI_PORT_CONTROL_IP_MASK
,
2129 adapter
->db
+ SLIPORT_CONTROL_OFFSET
);
2130 status
= lancer_test_and_set_rdy_state(adapter
);
2133 dev_err(&adapter
->pdev
->dev
,
2134 "Adapter in non recoverable error\n");
2139 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
2142 wrb
= wrb_from_mbox(adapter
);
2143 req
= embedded_payload(wrb
);
2145 be_wrb_cmd_hdr_prepare(req
, CMD_SUBSYSTEM_COMMON
,
2146 OPCODE_COMMON_FUNCTION_RESET
, sizeof(*req
), wrb
,
2149 status
= be_mbox_notify_wait(adapter
);
2151 mutex_unlock(&adapter
->mbox_lock
);
2155 int be_cmd_rss_config(struct be_adapter
*adapter
, u8
*rsstable
,
2156 u32 rss_hash_opts
, u16 table_size
, const u8
*rss_hkey
)
2158 struct be_mcc_wrb
*wrb
;
2159 struct be_cmd_req_rss_config
*req
;
2162 if (!(be_if_cap_flags(adapter
) & BE_IF_FLAGS_RSS
))
2165 spin_lock_bh(&adapter
->mcc_lock
);
2167 wrb
= wrb_from_mccq(adapter
);
2172 req
= embedded_payload(wrb
);
2174 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
2175 OPCODE_ETH_RSS_CONFIG
, sizeof(*req
), wrb
, NULL
);
2177 req
->if_id
= cpu_to_le32(adapter
->if_handle
);
2178 req
->enable_rss
= cpu_to_le16(rss_hash_opts
);
2179 req
->cpu_table_size_log2
= cpu_to_le16(fls(table_size
) - 1);
2181 if (!BEx_chip(adapter
))
2182 req
->hdr
.version
= 1;
2184 memcpy(req
->cpu_table
, rsstable
, table_size
);
2185 memcpy(req
->hash
, rss_hkey
, RSS_HASH_KEY_LEN
);
2186 be_dws_cpu_to_le(req
->hash
, sizeof(req
->hash
));
2188 status
= be_mcc_notify_wait(adapter
);
2190 spin_unlock_bh(&adapter
->mcc_lock
);
2195 int be_cmd_set_beacon_state(struct be_adapter
*adapter
, u8 port_num
,
2196 u8 bcn
, u8 sts
, u8 state
)
2198 struct be_mcc_wrb
*wrb
;
2199 struct be_cmd_req_enable_disable_beacon
*req
;
2202 spin_lock_bh(&adapter
->mcc_lock
);
2204 wrb
= wrb_from_mccq(adapter
);
2209 req
= embedded_payload(wrb
);
2211 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2212 OPCODE_COMMON_ENABLE_DISABLE_BEACON
,
2213 sizeof(*req
), wrb
, NULL
);
2215 req
->port_num
= port_num
;
2216 req
->beacon_state
= state
;
2217 req
->beacon_duration
= bcn
;
2218 req
->status_duration
= sts
;
2220 status
= be_mcc_notify_wait(adapter
);
2223 spin_unlock_bh(&adapter
->mcc_lock
);
2228 int be_cmd_get_beacon_state(struct be_adapter
*adapter
, u8 port_num
, u32
*state
)
2230 struct be_mcc_wrb
*wrb
;
2231 struct be_cmd_req_get_beacon_state
*req
;
2234 spin_lock_bh(&adapter
->mcc_lock
);
2236 wrb
= wrb_from_mccq(adapter
);
2241 req
= embedded_payload(wrb
);
2243 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2244 OPCODE_COMMON_GET_BEACON_STATE
, sizeof(*req
),
2247 req
->port_num
= port_num
;
2249 status
= be_mcc_notify_wait(adapter
);
2251 struct be_cmd_resp_get_beacon_state
*resp
=
2252 embedded_payload(wrb
);
2254 *state
= resp
->beacon_state
;
2258 spin_unlock_bh(&adapter
->mcc_lock
);
2263 int be_cmd_read_port_transceiver_data(struct be_adapter
*adapter
,
2264 u8 page_num
, u8
*data
)
2266 struct be_dma_mem cmd
;
2267 struct be_mcc_wrb
*wrb
;
2268 struct be_cmd_req_port_type
*req
;
2271 if (page_num
> TR_PAGE_A2
)
2274 cmd
.size
= sizeof(struct be_cmd_resp_port_type
);
2275 cmd
.va
= pci_alloc_consistent(adapter
->pdev
, cmd
.size
, &cmd
.dma
);
2277 dev_err(&adapter
->pdev
->dev
, "Memory allocation failed\n");
2280 memset(cmd
.va
, 0, cmd
.size
);
2282 spin_lock_bh(&adapter
->mcc_lock
);
2284 wrb
= wrb_from_mccq(adapter
);
2291 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2292 OPCODE_COMMON_READ_TRANSRECV_DATA
,
2293 cmd
.size
, wrb
, &cmd
);
2295 req
->port
= cpu_to_le32(adapter
->hba_port_num
);
2296 req
->page_num
= cpu_to_le32(page_num
);
2297 status
= be_mcc_notify_wait(adapter
);
2299 struct be_cmd_resp_port_type
*resp
= cmd
.va
;
2301 memcpy(data
, resp
->page_data
, PAGE_DATA_LEN
);
2304 spin_unlock_bh(&adapter
->mcc_lock
);
2305 pci_free_consistent(adapter
->pdev
, cmd
.size
, cmd
.va
, cmd
.dma
);
2309 int lancer_cmd_write_object(struct be_adapter
*adapter
, struct be_dma_mem
*cmd
,
2310 u32 data_size
, u32 data_offset
,
2311 const char *obj_name
, u32
*data_written
,
2312 u8
*change_status
, u8
*addn_status
)
2314 struct be_mcc_wrb
*wrb
;
2315 struct lancer_cmd_req_write_object
*req
;
2316 struct lancer_cmd_resp_write_object
*resp
;
2320 spin_lock_bh(&adapter
->mcc_lock
);
2321 adapter
->flash_status
= 0;
2323 wrb
= wrb_from_mccq(adapter
);
2329 req
= embedded_payload(wrb
);
2331 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2332 OPCODE_COMMON_WRITE_OBJECT
,
2333 sizeof(struct lancer_cmd_req_write_object
), wrb
,
2336 ctxt
= &req
->context
;
2337 AMAP_SET_BITS(struct amap_lancer_write_obj_context
,
2338 write_length
, ctxt
, data_size
);
2341 AMAP_SET_BITS(struct amap_lancer_write_obj_context
,
2344 AMAP_SET_BITS(struct amap_lancer_write_obj_context
,
2347 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
2348 req
->write_offset
= cpu_to_le32(data_offset
);
2349 strlcpy(req
->object_name
, obj_name
, sizeof(req
->object_name
));
2350 req
->descriptor_count
= cpu_to_le32(1);
2351 req
->buf_len
= cpu_to_le32(data_size
);
2352 req
->addr_low
= cpu_to_le32((cmd
->dma
+
2353 sizeof(struct lancer_cmd_req_write_object
))
2355 req
->addr_high
= cpu_to_le32(upper_32_bits(cmd
->dma
+
2356 sizeof(struct lancer_cmd_req_write_object
)));
2358 be_mcc_notify(adapter
);
2359 spin_unlock_bh(&adapter
->mcc_lock
);
2361 if (!wait_for_completion_timeout(&adapter
->et_cmd_compl
,
2362 msecs_to_jiffies(60000)))
2363 status
= -ETIMEDOUT
;
2365 status
= adapter
->flash_status
;
2367 resp
= embedded_payload(wrb
);
2369 *data_written
= le32_to_cpu(resp
->actual_write_len
);
2370 *change_status
= resp
->change_status
;
2372 *addn_status
= resp
->additional_status
;
2378 spin_unlock_bh(&adapter
->mcc_lock
);
2382 int be_cmd_query_cable_type(struct be_adapter
*adapter
)
2384 u8 page_data
[PAGE_DATA_LEN
];
2387 status
= be_cmd_read_port_transceiver_data(adapter
, TR_PAGE_A0
,
2390 switch (adapter
->phy
.interface_type
) {
2392 adapter
->phy
.cable_type
=
2393 page_data
[QSFP_PLUS_CABLE_TYPE_OFFSET
];
2395 case PHY_TYPE_SFP_PLUS_10GB
:
2396 adapter
->phy
.cable_type
=
2397 page_data
[SFP_PLUS_CABLE_TYPE_OFFSET
];
2400 adapter
->phy
.cable_type
= 0;
2407 int be_cmd_query_sfp_info(struct be_adapter
*adapter
)
2409 u8 page_data
[PAGE_DATA_LEN
];
2412 status
= be_cmd_read_port_transceiver_data(adapter
, TR_PAGE_A0
,
2415 strlcpy(adapter
->phy
.vendor_name
, page_data
+
2416 SFP_VENDOR_NAME_OFFSET
, SFP_VENDOR_NAME_LEN
- 1);
2417 strlcpy(adapter
->phy
.vendor_pn
,
2418 page_data
+ SFP_VENDOR_PN_OFFSET
,
2419 SFP_VENDOR_NAME_LEN
- 1);
2425 int lancer_cmd_delete_object(struct be_adapter
*adapter
, const char *obj_name
)
2427 struct lancer_cmd_req_delete_object
*req
;
2428 struct be_mcc_wrb
*wrb
;
2431 spin_lock_bh(&adapter
->mcc_lock
);
2433 wrb
= wrb_from_mccq(adapter
);
2439 req
= embedded_payload(wrb
);
2441 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2442 OPCODE_COMMON_DELETE_OBJECT
,
2443 sizeof(*req
), wrb
, NULL
);
2445 strlcpy(req
->object_name
, obj_name
, sizeof(req
->object_name
));
2447 status
= be_mcc_notify_wait(adapter
);
2449 spin_unlock_bh(&adapter
->mcc_lock
);
2453 int lancer_cmd_read_object(struct be_adapter
*adapter
, struct be_dma_mem
*cmd
,
2454 u32 data_size
, u32 data_offset
, const char *obj_name
,
2455 u32
*data_read
, u32
*eof
, u8
*addn_status
)
2457 struct be_mcc_wrb
*wrb
;
2458 struct lancer_cmd_req_read_object
*req
;
2459 struct lancer_cmd_resp_read_object
*resp
;
2462 spin_lock_bh(&adapter
->mcc_lock
);
2464 wrb
= wrb_from_mccq(adapter
);
2470 req
= embedded_payload(wrb
);
2472 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2473 OPCODE_COMMON_READ_OBJECT
,
2474 sizeof(struct lancer_cmd_req_read_object
), wrb
,
2477 req
->desired_read_len
= cpu_to_le32(data_size
);
2478 req
->read_offset
= cpu_to_le32(data_offset
);
2479 strcpy(req
->object_name
, obj_name
);
2480 req
->descriptor_count
= cpu_to_le32(1);
2481 req
->buf_len
= cpu_to_le32(data_size
);
2482 req
->addr_low
= cpu_to_le32((cmd
->dma
& 0xFFFFFFFF));
2483 req
->addr_high
= cpu_to_le32(upper_32_bits(cmd
->dma
));
2485 status
= be_mcc_notify_wait(adapter
);
2487 resp
= embedded_payload(wrb
);
2489 *data_read
= le32_to_cpu(resp
->actual_read_len
);
2490 *eof
= le32_to_cpu(resp
->eof
);
2492 *addn_status
= resp
->additional_status
;
2496 spin_unlock_bh(&adapter
->mcc_lock
);
2500 int be_cmd_write_flashrom(struct be_adapter
*adapter
, struct be_dma_mem
*cmd
,
2501 u32 flash_type
, u32 flash_opcode
, u32 img_offset
,
2504 struct be_mcc_wrb
*wrb
;
2505 struct be_cmd_write_flashrom
*req
;
2508 spin_lock_bh(&adapter
->mcc_lock
);
2509 adapter
->flash_status
= 0;
2511 wrb
= wrb_from_mccq(adapter
);
2518 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2519 OPCODE_COMMON_WRITE_FLASHROM
, cmd
->size
, wrb
,
2522 req
->params
.op_type
= cpu_to_le32(flash_type
);
2523 if (flash_type
== OPTYPE_OFFSET_SPECIFIED
)
2524 req
->params
.offset
= cpu_to_le32(img_offset
);
2526 req
->params
.op_code
= cpu_to_le32(flash_opcode
);
2527 req
->params
.data_buf_size
= cpu_to_le32(buf_size
);
2529 be_mcc_notify(adapter
);
2530 spin_unlock_bh(&adapter
->mcc_lock
);
2532 if (!wait_for_completion_timeout(&adapter
->et_cmd_compl
,
2533 msecs_to_jiffies(40000)))
2534 status
= -ETIMEDOUT
;
2536 status
= adapter
->flash_status
;
2541 spin_unlock_bh(&adapter
->mcc_lock
);
2545 int be_cmd_get_flash_crc(struct be_adapter
*adapter
, u8
*flashed_crc
,
2546 u16 img_optype
, u32 img_offset
, u32 crc_offset
)
2548 struct be_cmd_read_flash_crc
*req
;
2549 struct be_mcc_wrb
*wrb
;
2552 spin_lock_bh(&adapter
->mcc_lock
);
2554 wrb
= wrb_from_mccq(adapter
);
2559 req
= embedded_payload(wrb
);
2561 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2562 OPCODE_COMMON_READ_FLASHROM
, sizeof(*req
),
2565 req
->params
.op_type
= cpu_to_le32(img_optype
);
2566 if (img_optype
== OPTYPE_OFFSET_SPECIFIED
)
2567 req
->params
.offset
= cpu_to_le32(img_offset
+ crc_offset
);
2569 req
->params
.offset
= cpu_to_le32(crc_offset
);
2571 req
->params
.op_code
= cpu_to_le32(FLASHROM_OPER_REPORT
);
2572 req
->params
.data_buf_size
= cpu_to_le32(0x4);
2574 status
= be_mcc_notify_wait(adapter
);
2576 memcpy(flashed_crc
, req
->crc
, 4);
2579 spin_unlock_bh(&adapter
->mcc_lock
);
2583 int be_cmd_enable_magic_wol(struct be_adapter
*adapter
, u8
*mac
,
2584 struct be_dma_mem
*nonemb_cmd
)
2586 struct be_mcc_wrb
*wrb
;
2587 struct be_cmd_req_acpi_wol_magic_config
*req
;
2590 spin_lock_bh(&adapter
->mcc_lock
);
2592 wrb
= wrb_from_mccq(adapter
);
2597 req
= nonemb_cmd
->va
;
2599 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
2600 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
, sizeof(*req
),
2602 memcpy(req
->magic_mac
, mac
, ETH_ALEN
);
2604 status
= be_mcc_notify_wait(adapter
);
2607 spin_unlock_bh(&adapter
->mcc_lock
);
2611 int be_cmd_set_loopback(struct be_adapter
*adapter
, u8 port_num
,
2612 u8 loopback_type
, u8 enable
)
2614 struct be_mcc_wrb
*wrb
;
2615 struct be_cmd_req_set_lmode
*req
;
2618 spin_lock_bh(&adapter
->mcc_lock
);
2620 wrb
= wrb_from_mccq(adapter
);
2626 req
= embedded_payload(wrb
);
2628 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_LOWLEVEL
,
2629 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE
, sizeof(*req
),
2632 req
->src_port
= port_num
;
2633 req
->dest_port
= port_num
;
2634 req
->loopback_type
= loopback_type
;
2635 req
->loopback_state
= enable
;
2637 status
= be_mcc_notify_wait(adapter
);
2639 spin_unlock_bh(&adapter
->mcc_lock
);
2643 int be_cmd_loopback_test(struct be_adapter
*adapter
, u32 port_num
,
2644 u32 loopback_type
, u32 pkt_size
, u32 num_pkts
,
2647 struct be_mcc_wrb
*wrb
;
2648 struct be_cmd_req_loopback_test
*req
;
2649 struct be_cmd_resp_loopback_test
*resp
;
2652 spin_lock_bh(&adapter
->mcc_lock
);
2654 wrb
= wrb_from_mccq(adapter
);
2660 req
= embedded_payload(wrb
);
2662 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_LOWLEVEL
,
2663 OPCODE_LOWLEVEL_LOOPBACK_TEST
, sizeof(*req
), wrb
,
2666 req
->hdr
.timeout
= cpu_to_le32(15);
2667 req
->pattern
= cpu_to_le64(pattern
);
2668 req
->src_port
= cpu_to_le32(port_num
);
2669 req
->dest_port
= cpu_to_le32(port_num
);
2670 req
->pkt_size
= cpu_to_le32(pkt_size
);
2671 req
->num_pkts
= cpu_to_le32(num_pkts
);
2672 req
->loopback_type
= cpu_to_le32(loopback_type
);
2674 be_mcc_notify(adapter
);
2676 spin_unlock_bh(&adapter
->mcc_lock
);
2678 wait_for_completion(&adapter
->et_cmd_compl
);
2679 resp
= embedded_payload(wrb
);
2680 status
= le32_to_cpu(resp
->status
);
2684 spin_unlock_bh(&adapter
->mcc_lock
);
2688 int be_cmd_ddr_dma_test(struct be_adapter
*adapter
, u64 pattern
,
2689 u32 byte_cnt
, struct be_dma_mem
*cmd
)
2691 struct be_mcc_wrb
*wrb
;
2692 struct be_cmd_req_ddrdma_test
*req
;
2696 spin_lock_bh(&adapter
->mcc_lock
);
2698 wrb
= wrb_from_mccq(adapter
);
2704 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_LOWLEVEL
,
2705 OPCODE_LOWLEVEL_HOST_DDR_DMA
, cmd
->size
, wrb
,
2708 req
->pattern
= cpu_to_le64(pattern
);
2709 req
->byte_count
= cpu_to_le32(byte_cnt
);
2710 for (i
= 0; i
< byte_cnt
; i
++) {
2711 req
->snd_buff
[i
] = (u8
)(pattern
>> (j
*8));
2717 status
= be_mcc_notify_wait(adapter
);
2720 struct be_cmd_resp_ddrdma_test
*resp
;
2723 if ((memcmp(resp
->rcv_buff
, req
->snd_buff
, byte_cnt
) != 0) ||
2730 spin_unlock_bh(&adapter
->mcc_lock
);
2734 int be_cmd_get_seeprom_data(struct be_adapter
*adapter
,
2735 struct be_dma_mem
*nonemb_cmd
)
2737 struct be_mcc_wrb
*wrb
;
2738 struct be_cmd_req_seeprom_read
*req
;
2741 spin_lock_bh(&adapter
->mcc_lock
);
2743 wrb
= wrb_from_mccq(adapter
);
2748 req
= nonemb_cmd
->va
;
2750 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2751 OPCODE_COMMON_SEEPROM_READ
, sizeof(*req
), wrb
,
2754 status
= be_mcc_notify_wait(adapter
);
2757 spin_unlock_bh(&adapter
->mcc_lock
);
2761 int be_cmd_get_phy_info(struct be_adapter
*adapter
)
2763 struct be_mcc_wrb
*wrb
;
2764 struct be_cmd_req_get_phy_info
*req
;
2765 struct be_dma_mem cmd
;
2768 if (!be_cmd_allowed(adapter
, OPCODE_COMMON_GET_PHY_DETAILS
,
2769 CMD_SUBSYSTEM_COMMON
))
2772 spin_lock_bh(&adapter
->mcc_lock
);
2774 wrb
= wrb_from_mccq(adapter
);
2779 cmd
.size
= sizeof(struct be_cmd_req_get_phy_info
);
2780 cmd
.va
= pci_alloc_consistent(adapter
->pdev
, cmd
.size
, &cmd
.dma
);
2782 dev_err(&adapter
->pdev
->dev
, "Memory alloc failure\n");
2789 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2790 OPCODE_COMMON_GET_PHY_DETAILS
, sizeof(*req
),
2793 status
= be_mcc_notify_wait(adapter
);
2795 struct be_phy_info
*resp_phy_info
=
2796 cmd
.va
+ sizeof(struct be_cmd_req_hdr
);
2798 adapter
->phy
.phy_type
= le16_to_cpu(resp_phy_info
->phy_type
);
2799 adapter
->phy
.interface_type
=
2800 le16_to_cpu(resp_phy_info
->interface_type
);
2801 adapter
->phy
.auto_speeds_supported
=
2802 le16_to_cpu(resp_phy_info
->auto_speeds_supported
);
2803 adapter
->phy
.fixed_speeds_supported
=
2804 le16_to_cpu(resp_phy_info
->fixed_speeds_supported
);
2805 adapter
->phy
.misc_params
=
2806 le32_to_cpu(resp_phy_info
->misc_params
);
2808 if (BE2_chip(adapter
)) {
2809 adapter
->phy
.fixed_speeds_supported
=
2810 BE_SUPPORTED_SPEED_10GBPS
|
2811 BE_SUPPORTED_SPEED_1GBPS
;
2814 pci_free_consistent(adapter
->pdev
, cmd
.size
, cmd
.va
, cmd
.dma
);
2816 spin_unlock_bh(&adapter
->mcc_lock
);
2820 static int be_cmd_set_qos(struct be_adapter
*adapter
, u32 bps
, u32 domain
)
2822 struct be_mcc_wrb
*wrb
;
2823 struct be_cmd_req_set_qos
*req
;
2826 spin_lock_bh(&adapter
->mcc_lock
);
2828 wrb
= wrb_from_mccq(adapter
);
2834 req
= embedded_payload(wrb
);
2836 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2837 OPCODE_COMMON_SET_QOS
, sizeof(*req
), wrb
, NULL
);
2839 req
->hdr
.domain
= domain
;
2840 req
->valid_bits
= cpu_to_le32(BE_QOS_BITS_NIC
);
2841 req
->max_bps_nic
= cpu_to_le32(bps
);
2843 status
= be_mcc_notify_wait(adapter
);
2846 spin_unlock_bh(&adapter
->mcc_lock
);
2850 int be_cmd_get_cntl_attributes(struct be_adapter
*adapter
)
2852 struct be_mcc_wrb
*wrb
;
2853 struct be_cmd_req_cntl_attribs
*req
;
2854 struct be_cmd_resp_cntl_attribs
*resp
;
2856 int payload_len
= max(sizeof(*req
), sizeof(*resp
));
2857 struct mgmt_controller_attrib
*attribs
;
2858 struct be_dma_mem attribs_cmd
;
2860 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
2863 memset(&attribs_cmd
, 0, sizeof(struct be_dma_mem
));
2864 attribs_cmd
.size
= sizeof(struct be_cmd_resp_cntl_attribs
);
2865 attribs_cmd
.va
= pci_alloc_consistent(adapter
->pdev
, attribs_cmd
.size
,
2867 if (!attribs_cmd
.va
) {
2868 dev_err(&adapter
->pdev
->dev
, "Memory allocation failure\n");
2873 wrb
= wrb_from_mbox(adapter
);
2878 req
= attribs_cmd
.va
;
2880 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2881 OPCODE_COMMON_GET_CNTL_ATTRIBUTES
, payload_len
,
2884 status
= be_mbox_notify_wait(adapter
);
2886 attribs
= attribs_cmd
.va
+ sizeof(struct be_cmd_resp_hdr
);
2887 adapter
->hba_port_num
= attribs
->hba_attribs
.phy_port
;
2891 mutex_unlock(&adapter
->mbox_lock
);
2893 pci_free_consistent(adapter
->pdev
, attribs_cmd
.size
,
2894 attribs_cmd
.va
, attribs_cmd
.dma
);
2899 int be_cmd_req_native_mode(struct be_adapter
*adapter
)
2901 struct be_mcc_wrb
*wrb
;
2902 struct be_cmd_req_set_func_cap
*req
;
2905 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
2908 wrb
= wrb_from_mbox(adapter
);
2914 req
= embedded_payload(wrb
);
2916 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2917 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP
,
2918 sizeof(*req
), wrb
, NULL
);
2920 req
->valid_cap_flags
= cpu_to_le32(CAPABILITY_SW_TIMESTAMPS
|
2921 CAPABILITY_BE3_NATIVE_ERX_API
);
2922 req
->cap_flags
= cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API
);
2924 status
= be_mbox_notify_wait(adapter
);
2926 struct be_cmd_resp_set_func_cap
*resp
= embedded_payload(wrb
);
2928 adapter
->be3_native
= le32_to_cpu(resp
->cap_flags
) &
2929 CAPABILITY_BE3_NATIVE_ERX_API
;
2930 if (!adapter
->be3_native
)
2931 dev_warn(&adapter
->pdev
->dev
,
2932 "adapter not in advanced mode\n");
2935 mutex_unlock(&adapter
->mbox_lock
);
2939 /* Get privilege(s) for a function */
2940 int be_cmd_get_fn_privileges(struct be_adapter
*adapter
, u32
*privilege
,
2943 struct be_mcc_wrb
*wrb
;
2944 struct be_cmd_req_get_fn_privileges
*req
;
2947 spin_lock_bh(&adapter
->mcc_lock
);
2949 wrb
= wrb_from_mccq(adapter
);
2955 req
= embedded_payload(wrb
);
2957 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2958 OPCODE_COMMON_GET_FN_PRIVILEGES
, sizeof(*req
),
2961 req
->hdr
.domain
= domain
;
2963 status
= be_mcc_notify_wait(adapter
);
2965 struct be_cmd_resp_get_fn_privileges
*resp
=
2966 embedded_payload(wrb
);
2968 *privilege
= le32_to_cpu(resp
->privilege_mask
);
2970 /* In UMC mode FW does not return right privileges.
2971 * Override with correct privilege equivalent to PF.
2973 if (BEx_chip(adapter
) && be_is_mc(adapter
) &&
2975 *privilege
= MAX_PRIVILEGES
;
2979 spin_unlock_bh(&adapter
->mcc_lock
);
2983 /* Set privilege(s) for a function */
2984 int be_cmd_set_fn_privileges(struct be_adapter
*adapter
, u32 privileges
,
2987 struct be_mcc_wrb
*wrb
;
2988 struct be_cmd_req_set_fn_privileges
*req
;
2991 spin_lock_bh(&adapter
->mcc_lock
);
2993 wrb
= wrb_from_mccq(adapter
);
2999 req
= embedded_payload(wrb
);
3000 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3001 OPCODE_COMMON_SET_FN_PRIVILEGES
, sizeof(*req
),
3003 req
->hdr
.domain
= domain
;
3004 if (lancer_chip(adapter
))
3005 req
->privileges_lancer
= cpu_to_le32(privileges
);
3007 req
->privileges
= cpu_to_le32(privileges
);
3009 status
= be_mcc_notify_wait(adapter
);
3011 spin_unlock_bh(&adapter
->mcc_lock
);
3015 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3016 * pmac_id_valid: false => pmac_id or MAC address is requested.
3017 * If pmac_id is returned, pmac_id_valid is returned as true
3019 int be_cmd_get_mac_from_list(struct be_adapter
*adapter
, u8
*mac
,
3020 bool *pmac_id_valid
, u32
*pmac_id
, u32 if_handle
,
3023 struct be_mcc_wrb
*wrb
;
3024 struct be_cmd_req_get_mac_list
*req
;
3027 struct be_dma_mem get_mac_list_cmd
;
3030 memset(&get_mac_list_cmd
, 0, sizeof(struct be_dma_mem
));
3031 get_mac_list_cmd
.size
= sizeof(struct be_cmd_resp_get_mac_list
);
3032 get_mac_list_cmd
.va
= pci_alloc_consistent(adapter
->pdev
,
3033 get_mac_list_cmd
.size
,
3034 &get_mac_list_cmd
.dma
);
3036 if (!get_mac_list_cmd
.va
) {
3037 dev_err(&adapter
->pdev
->dev
,
3038 "Memory allocation failure during GET_MAC_LIST\n");
3042 spin_lock_bh(&adapter
->mcc_lock
);
3044 wrb
= wrb_from_mccq(adapter
);
3050 req
= get_mac_list_cmd
.va
;
3052 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3053 OPCODE_COMMON_GET_MAC_LIST
,
3054 get_mac_list_cmd
.size
, wrb
, &get_mac_list_cmd
);
3055 req
->hdr
.domain
= domain
;
3056 req
->mac_type
= MAC_ADDRESS_TYPE_NETWORK
;
3057 if (*pmac_id_valid
) {
3058 req
->mac_id
= cpu_to_le32(*pmac_id
);
3059 req
->iface_id
= cpu_to_le16(if_handle
);
3060 req
->perm_override
= 0;
3062 req
->perm_override
= 1;
3065 status
= be_mcc_notify_wait(adapter
);
3067 struct be_cmd_resp_get_mac_list
*resp
=
3068 get_mac_list_cmd
.va
;
3070 if (*pmac_id_valid
) {
3071 memcpy(mac
, resp
->macid_macaddr
.mac_addr_id
.macaddr
,
3076 mac_count
= resp
->true_mac_count
+ resp
->pseudo_mac_count
;
3077 /* Mac list returned could contain one or more active mac_ids
3078 * or one or more true or pseudo permanant mac addresses.
3079 * If an active mac_id is present, return first active mac_id
3082 for (i
= 0; i
< mac_count
; i
++) {
3083 struct get_list_macaddr
*mac_entry
;
3087 mac_entry
= &resp
->macaddr_list
[i
];
3088 mac_addr_size
= le16_to_cpu(mac_entry
->mac_addr_size
);
3089 /* mac_id is a 32 bit value and mac_addr size
3092 if (mac_addr_size
== sizeof(u32
)) {
3093 *pmac_id_valid
= true;
3094 mac_id
= mac_entry
->mac_addr_id
.s_mac_id
.mac_id
;
3095 *pmac_id
= le32_to_cpu(mac_id
);
3099 /* If no active mac_id found, return first mac addr */
3100 *pmac_id_valid
= false;
3101 memcpy(mac
, resp
->macaddr_list
[0].mac_addr_id
.macaddr
,
3106 spin_unlock_bh(&adapter
->mcc_lock
);
3107 pci_free_consistent(adapter
->pdev
, get_mac_list_cmd
.size
,
3108 get_mac_list_cmd
.va
, get_mac_list_cmd
.dma
);
3112 int be_cmd_get_active_mac(struct be_adapter
*adapter
, u32 curr_pmac_id
,
3113 u8
*mac
, u32 if_handle
, bool active
, u32 domain
)
3116 be_cmd_get_mac_from_list(adapter
, mac
, &active
, &curr_pmac_id
,
3118 if (BEx_chip(adapter
))
3119 return be_cmd_mac_addr_query(adapter
, mac
, false,
3120 if_handle
, curr_pmac_id
);
3122 /* Fetch the MAC address using pmac_id */
3123 return be_cmd_get_mac_from_list(adapter
, mac
, &active
,
3128 int be_cmd_get_perm_mac(struct be_adapter
*adapter
, u8
*mac
)
3131 bool pmac_valid
= false;
3133 memset(mac
, 0, ETH_ALEN
);
3135 if (BEx_chip(adapter
)) {
3136 if (be_physfn(adapter
))
3137 status
= be_cmd_mac_addr_query(adapter
, mac
, true, 0,
3140 status
= be_cmd_mac_addr_query(adapter
, mac
, false,
3141 adapter
->if_handle
, 0);
3143 status
= be_cmd_get_mac_from_list(adapter
, mac
, &pmac_valid
,
3144 NULL
, adapter
->if_handle
, 0);
3150 /* Uses synchronous MCCQ */
3151 int be_cmd_set_mac_list(struct be_adapter
*adapter
, u8
*mac_array
,
3152 u8 mac_count
, u32 domain
)
3154 struct be_mcc_wrb
*wrb
;
3155 struct be_cmd_req_set_mac_list
*req
;
3157 struct be_dma_mem cmd
;
3159 memset(&cmd
, 0, sizeof(struct be_dma_mem
));
3160 cmd
.size
= sizeof(struct be_cmd_req_set_mac_list
);
3161 cmd
.va
= dma_alloc_coherent(&adapter
->pdev
->dev
, cmd
.size
,
3162 &cmd
.dma
, GFP_KERNEL
);
3166 spin_lock_bh(&adapter
->mcc_lock
);
3168 wrb
= wrb_from_mccq(adapter
);
3175 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3176 OPCODE_COMMON_SET_MAC_LIST
, sizeof(*req
),
3179 req
->hdr
.domain
= domain
;
3180 req
->mac_count
= mac_count
;
3182 memcpy(req
->mac
, mac_array
, ETH_ALEN
*mac_count
);
3184 status
= be_mcc_notify_wait(adapter
);
3187 dma_free_coherent(&adapter
->pdev
->dev
, cmd
.size
, cmd
.va
, cmd
.dma
);
3188 spin_unlock_bh(&adapter
->mcc_lock
);
3192 /* Wrapper to delete any active MACs and provision the new mac.
3193 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3194 * current list are active.
3196 int be_cmd_set_mac(struct be_adapter
*adapter
, u8
*mac
, int if_id
, u32 dom
)
3198 bool active_mac
= false;
3199 u8 old_mac
[ETH_ALEN
];
3203 status
= be_cmd_get_mac_from_list(adapter
, old_mac
, &active_mac
,
3204 &pmac_id
, if_id
, dom
);
3206 if (!status
&& active_mac
)
3207 be_cmd_pmac_del(adapter
, if_id
, pmac_id
, dom
);
3209 return be_cmd_set_mac_list(adapter
, mac
, mac
? 1 : 0, dom
);
3212 int be_cmd_set_hsw_config(struct be_adapter
*adapter
, u16 pvid
,
3213 u32 domain
, u16 intf_id
, u16 hsw_mode
)
3215 struct be_mcc_wrb
*wrb
;
3216 struct be_cmd_req_set_hsw_config
*req
;
3220 spin_lock_bh(&adapter
->mcc_lock
);
3222 wrb
= wrb_from_mccq(adapter
);
3228 req
= embedded_payload(wrb
);
3229 ctxt
= &req
->context
;
3231 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3232 OPCODE_COMMON_SET_HSW_CONFIG
, sizeof(*req
), wrb
,
3235 req
->hdr
.domain
= domain
;
3236 AMAP_SET_BITS(struct amap_set_hsw_context
, interface_id
, ctxt
, intf_id
);
3238 AMAP_SET_BITS(struct amap_set_hsw_context
, pvid_valid
, ctxt
, 1);
3239 AMAP_SET_BITS(struct amap_set_hsw_context
, pvid
, ctxt
, pvid
);
3241 if (!BEx_chip(adapter
) && hsw_mode
) {
3242 AMAP_SET_BITS(struct amap_set_hsw_context
, interface_id
,
3243 ctxt
, adapter
->hba_port_num
);
3244 AMAP_SET_BITS(struct amap_set_hsw_context
, pport
, ctxt
, 1);
3245 AMAP_SET_BITS(struct amap_set_hsw_context
, port_fwd_type
,
3249 be_dws_cpu_to_le(req
->context
, sizeof(req
->context
));
3250 status
= be_mcc_notify_wait(adapter
);
3253 spin_unlock_bh(&adapter
->mcc_lock
);
3257 /* Get Hyper switch config */
3258 int be_cmd_get_hsw_config(struct be_adapter
*adapter
, u16
*pvid
,
3259 u32 domain
, u16 intf_id
, u8
*mode
)
3261 struct be_mcc_wrb
*wrb
;
3262 struct be_cmd_req_get_hsw_config
*req
;
3267 spin_lock_bh(&adapter
->mcc_lock
);
3269 wrb
= wrb_from_mccq(adapter
);
3275 req
= embedded_payload(wrb
);
3276 ctxt
= &req
->context
;
3278 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3279 OPCODE_COMMON_GET_HSW_CONFIG
, sizeof(*req
), wrb
,
3282 req
->hdr
.domain
= domain
;
3283 AMAP_SET_BITS(struct amap_get_hsw_req_context
, interface_id
,
3285 AMAP_SET_BITS(struct amap_get_hsw_req_context
, pvid_valid
, ctxt
, 1);
3287 if (!BEx_chip(adapter
) && mode
) {
3288 AMAP_SET_BITS(struct amap_get_hsw_req_context
, interface_id
,
3289 ctxt
, adapter
->hba_port_num
);
3290 AMAP_SET_BITS(struct amap_get_hsw_req_context
, pport
, ctxt
, 1);
3292 be_dws_cpu_to_le(req
->context
, sizeof(req
->context
));
3294 status
= be_mcc_notify_wait(adapter
);
3296 struct be_cmd_resp_get_hsw_config
*resp
=
3297 embedded_payload(wrb
);
3299 be_dws_le_to_cpu(&resp
->context
, sizeof(resp
->context
));
3300 vid
= AMAP_GET_BITS(struct amap_get_hsw_resp_context
,
3301 pvid
, &resp
->context
);
3303 *pvid
= le16_to_cpu(vid
);
3305 *mode
= AMAP_GET_BITS(struct amap_get_hsw_resp_context
,
3306 port_fwd_type
, &resp
->context
);
3310 spin_unlock_bh(&adapter
->mcc_lock
);
3314 static bool be_is_wol_excluded(struct be_adapter
*adapter
)
3316 struct pci_dev
*pdev
= adapter
->pdev
;
3318 if (!be_physfn(adapter
))
3321 switch (pdev
->subsystem_device
) {
3322 case OC_SUBSYS_DEVICE_ID1
:
3323 case OC_SUBSYS_DEVICE_ID2
:
3324 case OC_SUBSYS_DEVICE_ID3
:
3325 case OC_SUBSYS_DEVICE_ID4
:
3332 int be_cmd_get_acpi_wol_cap(struct be_adapter
*adapter
)
3334 struct be_mcc_wrb
*wrb
;
3335 struct be_cmd_req_acpi_wol_magic_config_v1
*req
;
3337 struct be_dma_mem cmd
;
3339 if (!be_cmd_allowed(adapter
, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
,
3343 if (be_is_wol_excluded(adapter
))
3346 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
3349 memset(&cmd
, 0, sizeof(struct be_dma_mem
));
3350 cmd
.size
= sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1
);
3351 cmd
.va
= pci_alloc_consistent(adapter
->pdev
, cmd
.size
, &cmd
.dma
);
3353 dev_err(&adapter
->pdev
->dev
, "Memory allocation failure\n");
3358 wrb
= wrb_from_mbox(adapter
);
3366 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
3367 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
,
3368 sizeof(*req
), wrb
, &cmd
);
3370 req
->hdr
.version
= 1;
3371 req
->query_options
= BE_GET_WOL_CAP
;
3373 status
= be_mbox_notify_wait(adapter
);
3375 struct be_cmd_resp_acpi_wol_magic_config_v1
*resp
;
3377 resp
= (struct be_cmd_resp_acpi_wol_magic_config_v1
*)cmd
.va
;
3379 adapter
->wol_cap
= resp
->wol_settings
;
3380 if (adapter
->wol_cap
& BE_WOL_CAP
)
3381 adapter
->wol_en
= true;
3384 mutex_unlock(&adapter
->mbox_lock
);
3386 pci_free_consistent(adapter
->pdev
, cmd
.size
, cmd
.va
, cmd
.dma
);
3391 int be_cmd_set_fw_log_level(struct be_adapter
*adapter
, u32 level
)
3393 struct be_dma_mem extfat_cmd
;
3394 struct be_fat_conf_params
*cfgs
;
3398 memset(&extfat_cmd
, 0, sizeof(struct be_dma_mem
));
3399 extfat_cmd
.size
= sizeof(struct be_cmd_resp_get_ext_fat_caps
);
3400 extfat_cmd
.va
= pci_alloc_consistent(adapter
->pdev
, extfat_cmd
.size
,
3405 status
= be_cmd_get_ext_fat_capabilites(adapter
, &extfat_cmd
);
3409 cfgs
= (struct be_fat_conf_params
*)
3410 (extfat_cmd
.va
+ sizeof(struct be_cmd_resp_hdr
));
3411 for (i
= 0; i
< le32_to_cpu(cfgs
->num_modules
); i
++) {
3412 u32 num_modes
= le32_to_cpu(cfgs
->module
[i
].num_modes
);
3414 for (j
= 0; j
< num_modes
; j
++) {
3415 if (cfgs
->module
[i
].trace_lvl
[j
].mode
== MODE_UART
)
3416 cfgs
->module
[i
].trace_lvl
[j
].dbg_lvl
=
3421 status
= be_cmd_set_ext_fat_capabilites(adapter
, &extfat_cmd
, cfgs
);
3423 pci_free_consistent(adapter
->pdev
, extfat_cmd
.size
, extfat_cmd
.va
,
3428 int be_cmd_get_fw_log_level(struct be_adapter
*adapter
)
3430 struct be_dma_mem extfat_cmd
;
3431 struct be_fat_conf_params
*cfgs
;
3435 memset(&extfat_cmd
, 0, sizeof(struct be_dma_mem
));
3436 extfat_cmd
.size
= sizeof(struct be_cmd_resp_get_ext_fat_caps
);
3437 extfat_cmd
.va
= pci_alloc_consistent(adapter
->pdev
, extfat_cmd
.size
,
3440 if (!extfat_cmd
.va
) {
3441 dev_err(&adapter
->pdev
->dev
, "%s: Memory allocation failure\n",
3446 status
= be_cmd_get_ext_fat_capabilites(adapter
, &extfat_cmd
);
3448 cfgs
= (struct be_fat_conf_params
*)(extfat_cmd
.va
+
3449 sizeof(struct be_cmd_resp_hdr
));
3451 for (j
= 0; j
< le32_to_cpu(cfgs
->module
[0].num_modes
); j
++) {
3452 if (cfgs
->module
[0].trace_lvl
[j
].mode
== MODE_UART
)
3453 level
= cfgs
->module
[0].trace_lvl
[j
].dbg_lvl
;
3456 pci_free_consistent(adapter
->pdev
, extfat_cmd
.size
, extfat_cmd
.va
,
3462 int be_cmd_get_ext_fat_capabilites(struct be_adapter
*adapter
,
3463 struct be_dma_mem
*cmd
)
3465 struct be_mcc_wrb
*wrb
;
3466 struct be_cmd_req_get_ext_fat_caps
*req
;
3469 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
3472 wrb
= wrb_from_mbox(adapter
);
3479 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3480 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES
,
3481 cmd
->size
, wrb
, cmd
);
3482 req
->parameter_type
= cpu_to_le32(1);
3484 status
= be_mbox_notify_wait(adapter
);
3486 mutex_unlock(&adapter
->mbox_lock
);
3490 int be_cmd_set_ext_fat_capabilites(struct be_adapter
*adapter
,
3491 struct be_dma_mem
*cmd
,
3492 struct be_fat_conf_params
*configs
)
3494 struct be_mcc_wrb
*wrb
;
3495 struct be_cmd_req_set_ext_fat_caps
*req
;
3498 spin_lock_bh(&adapter
->mcc_lock
);
3500 wrb
= wrb_from_mccq(adapter
);
3507 memcpy(&req
->set_params
, configs
, sizeof(struct be_fat_conf_params
));
3508 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3509 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES
,
3510 cmd
->size
, wrb
, cmd
);
3512 status
= be_mcc_notify_wait(adapter
);
3514 spin_unlock_bh(&adapter
->mcc_lock
);
3518 int be_cmd_query_port_name(struct be_adapter
*adapter
)
3520 struct be_cmd_req_get_port_name
*req
;
3521 struct be_mcc_wrb
*wrb
;
3524 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
3527 wrb
= wrb_from_mbox(adapter
);
3528 req
= embedded_payload(wrb
);
3530 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3531 OPCODE_COMMON_GET_PORT_NAME
, sizeof(*req
), wrb
,
3533 if (!BEx_chip(adapter
))
3534 req
->hdr
.version
= 1;
3536 status
= be_mbox_notify_wait(adapter
);
3538 struct be_cmd_resp_get_port_name
*resp
= embedded_payload(wrb
);
3540 adapter
->port_name
= resp
->port_name
[adapter
->hba_port_num
];
3542 adapter
->port_name
= adapter
->hba_port_num
+ '0';
3545 mutex_unlock(&adapter
->mbox_lock
);
3549 /* Descriptor type */
3555 static struct be_nic_res_desc
*be_get_nic_desc(u8
*buf
, u32 desc_count
,
3558 struct be_res_desc_hdr
*hdr
= (struct be_res_desc_hdr
*)buf
;
3559 struct be_nic_res_desc
*nic
;
3562 for (i
= 0; i
< desc_count
; i
++) {
3563 if (hdr
->desc_type
== NIC_RESOURCE_DESC_TYPE_V0
||
3564 hdr
->desc_type
== NIC_RESOURCE_DESC_TYPE_V1
) {
3565 nic
= (struct be_nic_res_desc
*)hdr
;
3566 if (desc_type
== FUNC_DESC
||
3567 (desc_type
== VFT_DESC
&&
3568 nic
->flags
& (1 << VFT_SHIFT
)))
3572 hdr
->desc_len
= hdr
->desc_len
? : RESOURCE_DESC_SIZE_V0
;
3573 hdr
= (void *)hdr
+ hdr
->desc_len
;
3578 static struct be_nic_res_desc
*be_get_vft_desc(u8
*buf
, u32 desc_count
)
3580 return be_get_nic_desc(buf
, desc_count
, VFT_DESC
);
3583 static struct be_nic_res_desc
*be_get_func_nic_desc(u8
*buf
, u32 desc_count
)
3585 return be_get_nic_desc(buf
, desc_count
, FUNC_DESC
);
3588 static struct be_pcie_res_desc
*be_get_pcie_desc(u8 devfn
, u8
*buf
,
3591 struct be_res_desc_hdr
*hdr
= (struct be_res_desc_hdr
*)buf
;
3592 struct be_pcie_res_desc
*pcie
;
3595 for (i
= 0; i
< desc_count
; i
++) {
3596 if ((hdr
->desc_type
== PCIE_RESOURCE_DESC_TYPE_V0
||
3597 hdr
->desc_type
== PCIE_RESOURCE_DESC_TYPE_V1
)) {
3598 pcie
= (struct be_pcie_res_desc
*)hdr
;
3599 if (pcie
->pf_num
== devfn
)
3603 hdr
->desc_len
= hdr
->desc_len
? : RESOURCE_DESC_SIZE_V0
;
3604 hdr
= (void *)hdr
+ hdr
->desc_len
;
3609 static struct be_port_res_desc
*be_get_port_desc(u8
*buf
, u32 desc_count
)
3611 struct be_res_desc_hdr
*hdr
= (struct be_res_desc_hdr
*)buf
;
3614 for (i
= 0; i
< desc_count
; i
++) {
3615 if (hdr
->desc_type
== PORT_RESOURCE_DESC_TYPE_V1
)
3616 return (struct be_port_res_desc
*)hdr
;
3618 hdr
->desc_len
= hdr
->desc_len
? : RESOURCE_DESC_SIZE_V0
;
3619 hdr
= (void *)hdr
+ hdr
->desc_len
;
3624 static void be_copy_nic_desc(struct be_resources
*res
,
3625 struct be_nic_res_desc
*desc
)
3627 res
->max_uc_mac
= le16_to_cpu(desc
->unicast_mac_count
);
3628 res
->max_vlans
= le16_to_cpu(desc
->vlan_count
);
3629 res
->max_mcast_mac
= le16_to_cpu(desc
->mcast_mac_count
);
3630 res
->max_tx_qs
= le16_to_cpu(desc
->txq_count
);
3631 res
->max_rss_qs
= le16_to_cpu(desc
->rssq_count
);
3632 res
->max_rx_qs
= le16_to_cpu(desc
->rq_count
);
3633 res
->max_evt_qs
= le16_to_cpu(desc
->eq_count
);
3634 /* Clear flags that driver is not interested in */
3635 res
->if_cap_flags
= le32_to_cpu(desc
->cap_flags
) &
3636 BE_IF_CAP_FLAGS_WANT
;
3637 /* Need 1 RXQ as the default RXQ */
3638 if (res
->max_rss_qs
&& res
->max_rss_qs
== res
->max_rx_qs
)
3639 res
->max_rss_qs
-= 1;
3643 int be_cmd_get_func_config(struct be_adapter
*adapter
, struct be_resources
*res
)
3645 struct be_mcc_wrb
*wrb
;
3646 struct be_cmd_req_get_func_config
*req
;
3648 struct be_dma_mem cmd
;
3650 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
3653 memset(&cmd
, 0, sizeof(struct be_dma_mem
));
3654 cmd
.size
= sizeof(struct be_cmd_resp_get_func_config
);
3655 cmd
.va
= pci_alloc_consistent(adapter
->pdev
, cmd
.size
, &cmd
.dma
);
3657 dev_err(&adapter
->pdev
->dev
, "Memory alloc failure\n");
3662 wrb
= wrb_from_mbox(adapter
);
3670 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3671 OPCODE_COMMON_GET_FUNC_CONFIG
,
3672 cmd
.size
, wrb
, &cmd
);
3674 if (skyhawk_chip(adapter
))
3675 req
->hdr
.version
= 1;
3677 status
= be_mbox_notify_wait(adapter
);
3679 struct be_cmd_resp_get_func_config
*resp
= cmd
.va
;
3680 u32 desc_count
= le32_to_cpu(resp
->desc_count
);
3681 struct be_nic_res_desc
*desc
;
3683 desc
= be_get_func_nic_desc(resp
->func_param
, desc_count
);
3689 adapter
->pf_number
= desc
->pf_num
;
3690 be_copy_nic_desc(res
, desc
);
3693 mutex_unlock(&adapter
->mbox_lock
);
3695 pci_free_consistent(adapter
->pdev
, cmd
.size
, cmd
.va
, cmd
.dma
);
3699 /* Will use MBOX only if MCCQ has not been created */
3700 int be_cmd_get_profile_config(struct be_adapter
*adapter
,
3701 struct be_resources
*res
, u8 domain
)
3703 struct be_cmd_resp_get_profile_config
*resp
;
3704 struct be_cmd_req_get_profile_config
*req
;
3705 struct be_nic_res_desc
*vf_res
;
3706 struct be_pcie_res_desc
*pcie
;
3707 struct be_port_res_desc
*port
;
3708 struct be_nic_res_desc
*nic
;
3709 struct be_mcc_wrb wrb
= {0};
3710 struct be_dma_mem cmd
;
3714 memset(&cmd
, 0, sizeof(struct be_dma_mem
));
3715 cmd
.size
= sizeof(struct be_cmd_resp_get_profile_config
);
3716 cmd
.va
= pci_alloc_consistent(adapter
->pdev
, cmd
.size
, &cmd
.dma
);
3721 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3722 OPCODE_COMMON_GET_PROFILE_CONFIG
,
3723 cmd
.size
, &wrb
, &cmd
);
3725 req
->hdr
.domain
= domain
;
3726 if (!lancer_chip(adapter
))
3727 req
->hdr
.version
= 1;
3728 req
->type
= ACTIVE_PROFILE_TYPE
;
3730 status
= be_cmd_notify_wait(adapter
, &wrb
);
3735 desc_count
= le32_to_cpu(resp
->desc_count
);
3737 pcie
= be_get_pcie_desc(adapter
->pdev
->devfn
, resp
->func_param
,
3740 res
->max_vfs
= le16_to_cpu(pcie
->num_vfs
);
3742 port
= be_get_port_desc(resp
->func_param
, desc_count
);
3744 adapter
->mc_type
= port
->mc_type
;
3746 nic
= be_get_func_nic_desc(resp
->func_param
, desc_count
);
3748 be_copy_nic_desc(res
, nic
);
3750 vf_res
= be_get_vft_desc(resp
->func_param
, desc_count
);
3752 res
->vf_if_cap_flags
= vf_res
->cap_flags
;
3755 pci_free_consistent(adapter
->pdev
, cmd
.size
, cmd
.va
, cmd
.dma
);
3759 /* Will use MBOX only if MCCQ has not been created */
3760 static int be_cmd_set_profile_config(struct be_adapter
*adapter
, void *desc
,
3761 int size
, int count
, u8 version
, u8 domain
)
3763 struct be_cmd_req_set_profile_config
*req
;
3764 struct be_mcc_wrb wrb
= {0};
3765 struct be_dma_mem cmd
;
3768 memset(&cmd
, 0, sizeof(struct be_dma_mem
));
3769 cmd
.size
= sizeof(struct be_cmd_req_set_profile_config
);
3770 cmd
.va
= pci_alloc_consistent(adapter
->pdev
, cmd
.size
, &cmd
.dma
);
3775 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3776 OPCODE_COMMON_SET_PROFILE_CONFIG
, cmd
.size
,
3778 req
->hdr
.version
= version
;
3779 req
->hdr
.domain
= domain
;
3780 req
->desc_count
= cpu_to_le32(count
);
3781 memcpy(req
->desc
, desc
, size
);
3783 status
= be_cmd_notify_wait(adapter
, &wrb
);
3786 pci_free_consistent(adapter
->pdev
, cmd
.size
, cmd
.va
, cmd
.dma
);
3790 /* Mark all fields invalid */
3791 static void be_reset_nic_desc(struct be_nic_res_desc
*nic
)
3793 memset(nic
, 0, sizeof(*nic
));
3794 nic
->unicast_mac_count
= 0xFFFF;
3795 nic
->mcc_count
= 0xFFFF;
3796 nic
->vlan_count
= 0xFFFF;
3797 nic
->mcast_mac_count
= 0xFFFF;
3798 nic
->txq_count
= 0xFFFF;
3799 nic
->rq_count
= 0xFFFF;
3800 nic
->rssq_count
= 0xFFFF;
3801 nic
->lro_count
= 0xFFFF;
3802 nic
->cq_count
= 0xFFFF;
3803 nic
->toe_conn_count
= 0xFFFF;
3804 nic
->eq_count
= 0xFFFF;
3805 nic
->iface_count
= 0xFFFF;
3806 nic
->link_param
= 0xFF;
3807 nic
->channel_id_param
= cpu_to_le16(0xF000);
3808 nic
->acpi_params
= 0xFF;
3809 nic
->wol_param
= 0x0F;
3810 nic
->tunnel_iface_count
= 0xFFFF;
3811 nic
->direct_tenant_iface_count
= 0xFFFF;
3812 nic
->bw_min
= 0xFFFFFFFF;
3813 nic
->bw_max
= 0xFFFFFFFF;
3816 /* Mark all fields invalid */
3817 static void be_reset_pcie_desc(struct be_pcie_res_desc
*pcie
)
3819 memset(pcie
, 0, sizeof(*pcie
));
3820 pcie
->sriov_state
= 0xFF;
3821 pcie
->pf_state
= 0xFF;
3822 pcie
->pf_type
= 0xFF;
3823 pcie
->num_vfs
= 0xFFFF;
3826 int be_cmd_config_qos(struct be_adapter
*adapter
, u32 max_rate
, u16 link_speed
,
3829 struct be_nic_res_desc nic_desc
;
3833 if (BE3_chip(adapter
))
3834 return be_cmd_set_qos(adapter
, max_rate
/ 10, domain
);
3836 be_reset_nic_desc(&nic_desc
);
3837 nic_desc
.pf_num
= adapter
->pf_number
;
3838 nic_desc
.vf_num
= domain
;
3839 nic_desc
.bw_min
= 0;
3840 if (lancer_chip(adapter
)) {
3841 nic_desc
.hdr
.desc_type
= NIC_RESOURCE_DESC_TYPE_V0
;
3842 nic_desc
.hdr
.desc_len
= RESOURCE_DESC_SIZE_V0
;
3843 nic_desc
.flags
= (1 << QUN_SHIFT
) | (1 << IMM_SHIFT
) |
3845 nic_desc
.bw_max
= cpu_to_le32(max_rate
/ 10);
3848 nic_desc
.hdr
.desc_type
= NIC_RESOURCE_DESC_TYPE_V1
;
3849 nic_desc
.hdr
.desc_len
= RESOURCE_DESC_SIZE_V1
;
3850 nic_desc
.flags
= (1 << IMM_SHIFT
) | (1 << NOSV_SHIFT
);
3851 bw_percent
= max_rate
? (max_rate
* 100) / link_speed
: 100;
3852 nic_desc
.bw_max
= cpu_to_le32(bw_percent
);
3855 return be_cmd_set_profile_config(adapter
, &nic_desc
,
3856 nic_desc
.hdr
.desc_len
,
3857 1, version
, domain
);
3860 int be_cmd_set_sriov_config(struct be_adapter
*adapter
,
3861 struct be_resources res
, u16 num_vfs
)
3864 struct be_pcie_res_desc pcie
;
3865 struct be_nic_res_desc nic_vft
;
3869 if (BEx_chip(adapter
) || lancer_chip(adapter
))
3872 /* PF PCIE descriptor */
3873 be_reset_pcie_desc(&desc
.pcie
);
3874 desc
.pcie
.hdr
.desc_type
= PCIE_RESOURCE_DESC_TYPE_V1
;
3875 desc
.pcie
.hdr
.desc_len
= RESOURCE_DESC_SIZE_V1
;
3876 desc
.pcie
.flags
= (1 << IMM_SHIFT
) | (1 << NOSV_SHIFT
);
3877 desc
.pcie
.pf_num
= adapter
->pdev
->devfn
;
3878 desc
.pcie
.sriov_state
= num_vfs
? 1 : 0;
3879 desc
.pcie
.num_vfs
= cpu_to_le16(num_vfs
);
3881 /* VF NIC Template descriptor */
3882 be_reset_nic_desc(&desc
.nic_vft
);
3883 desc
.nic_vft
.hdr
.desc_type
= NIC_RESOURCE_DESC_TYPE_V1
;
3884 desc
.nic_vft
.hdr
.desc_len
= RESOURCE_DESC_SIZE_V1
;
3885 desc
.nic_vft
.flags
= (1 << VFT_SHIFT
) | (1 << IMM_SHIFT
) |
3887 desc
.nic_vft
.pf_num
= adapter
->pdev
->devfn
;
3888 desc
.nic_vft
.vf_num
= 0;
3890 if (num_vfs
&& res
.vf_if_cap_flags
& BE_IF_FLAGS_RSS
) {
3891 /* If number of VFs requested is 8 less than max supported,
3892 * assign 8 queue pairs to the PF and divide the remaining
3893 * resources evenly among the VFs
3895 if (num_vfs
< (be_max_vfs(adapter
) - 8))
3896 vf_q_count
= (res
.max_rss_qs
- 8) / num_vfs
;
3898 vf_q_count
= res
.max_rss_qs
/ num_vfs
;
3900 desc
.nic_vft
.rq_count
= cpu_to_le16(vf_q_count
);
3901 desc
.nic_vft
.txq_count
= cpu_to_le16(vf_q_count
);
3902 desc
.nic_vft
.rssq_count
= cpu_to_le16(vf_q_count
- 1);
3903 desc
.nic_vft
.cq_count
= cpu_to_le16(3 * vf_q_count
);
3905 desc
.nic_vft
.txq_count
= cpu_to_le16(1);
3906 desc
.nic_vft
.rq_count
= cpu_to_le16(1);
3907 desc
.nic_vft
.rssq_count
= cpu_to_le16(0);
3908 /* One CQ for each TX, RX and MCCQ */
3909 desc
.nic_vft
.cq_count
= cpu_to_le16(3);
3912 return be_cmd_set_profile_config(adapter
, &desc
,
3913 2 * RESOURCE_DESC_SIZE_V1
, 2, 1, 0);
3916 int be_cmd_manage_iface(struct be_adapter
*adapter
, u32 iface
, u8 op
)
3918 struct be_mcc_wrb
*wrb
;
3919 struct be_cmd_req_manage_iface_filters
*req
;
3922 if (iface
== 0xFFFFFFFF)
3925 spin_lock_bh(&adapter
->mcc_lock
);
3927 wrb
= wrb_from_mccq(adapter
);
3932 req
= embedded_payload(wrb
);
3934 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3935 OPCODE_COMMON_MANAGE_IFACE_FILTERS
, sizeof(*req
),
3938 req
->target_iface_id
= cpu_to_le32(iface
);
3940 status
= be_mcc_notify_wait(adapter
);
3942 spin_unlock_bh(&adapter
->mcc_lock
);
3946 int be_cmd_set_vxlan_port(struct be_adapter
*adapter
, __be16 port
)
3948 struct be_port_res_desc port_desc
;
3950 memset(&port_desc
, 0, sizeof(port_desc
));
3951 port_desc
.hdr
.desc_type
= PORT_RESOURCE_DESC_TYPE_V1
;
3952 port_desc
.hdr
.desc_len
= RESOURCE_DESC_SIZE_V1
;
3953 port_desc
.flags
= (1 << IMM_SHIFT
) | (1 << NOSV_SHIFT
);
3954 port_desc
.link_num
= adapter
->hba_port_num
;
3956 port_desc
.nv_flags
= NV_TYPE_VXLAN
| (1 << SOCVID_SHIFT
) |
3958 port_desc
.nv_port
= swab16(port
);
3960 port_desc
.nv_flags
= NV_TYPE_DISABLED
;
3961 port_desc
.nv_port
= 0;
3964 return be_cmd_set_profile_config(adapter
, &port_desc
,
3965 RESOURCE_DESC_SIZE_V1
, 1, 1, 0);
3968 int be_cmd_get_if_id(struct be_adapter
*adapter
, struct be_vf_cfg
*vf_cfg
,
3971 struct be_mcc_wrb
*wrb
;
3972 struct be_cmd_req_get_iface_list
*req
;
3973 struct be_cmd_resp_get_iface_list
*resp
;
3976 spin_lock_bh(&adapter
->mcc_lock
);
3978 wrb
= wrb_from_mccq(adapter
);
3983 req
= embedded_payload(wrb
);
3985 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3986 OPCODE_COMMON_GET_IFACE_LIST
, sizeof(*resp
),
3988 req
->hdr
.domain
= vf_num
+ 1;
3990 status
= be_mcc_notify_wait(adapter
);
3992 resp
= (struct be_cmd_resp_get_iface_list
*)req
;
3993 vf_cfg
->if_handle
= le32_to_cpu(resp
->if_desc
.if_id
);
3997 spin_unlock_bh(&adapter
->mcc_lock
);
4001 static int lancer_wait_idle(struct be_adapter
*adapter
)
4003 #define SLIPORT_IDLE_TIMEOUT 30
4007 for (i
= 0; i
< SLIPORT_IDLE_TIMEOUT
; i
++) {
4008 reg_val
= ioread32(adapter
->db
+ PHYSDEV_CONTROL_OFFSET
);
4009 if ((reg_val
& PHYSDEV_CONTROL_INP_MASK
) == 0)
4015 if (i
== SLIPORT_IDLE_TIMEOUT
)
4021 int lancer_physdev_ctrl(struct be_adapter
*adapter
, u32 mask
)
4025 status
= lancer_wait_idle(adapter
);
4029 iowrite32(mask
, adapter
->db
+ PHYSDEV_CONTROL_OFFSET
);
4034 /* Routine to check whether dump image is present or not */
4035 bool dump_present(struct be_adapter
*adapter
)
4037 u32 sliport_status
= 0;
4039 sliport_status
= ioread32(adapter
->db
+ SLIPORT_STATUS_OFFSET
);
4040 return !!(sliport_status
& SLIPORT_STATUS_DIP_MASK
);
4043 int lancer_initiate_dump(struct be_adapter
*adapter
)
4045 struct device
*dev
= &adapter
->pdev
->dev
;
4048 if (dump_present(adapter
)) {
4049 dev_info(dev
, "Previous dump not cleared, not forcing dump\n");
4053 /* give firmware reset and diagnostic dump */
4054 status
= lancer_physdev_ctrl(adapter
, PHYSDEV_CONTROL_FW_RESET_MASK
|
4055 PHYSDEV_CONTROL_DD_MASK
);
4057 dev_err(dev
, "FW reset failed\n");
4061 status
= lancer_wait_idle(adapter
);
4065 if (!dump_present(adapter
)) {
4066 dev_err(dev
, "FW dump not generated\n");
4073 int lancer_delete_dump(struct be_adapter
*adapter
)
4077 status
= lancer_cmd_delete_object(adapter
, LANCER_FW_DUMP_FILE
);
4078 return be_cmd_status(status
);
4082 int be_cmd_enable_vf(struct be_adapter
*adapter
, u8 domain
)
4084 struct be_mcc_wrb
*wrb
;
4085 struct be_cmd_enable_disable_vf
*req
;
4088 if (BEx_chip(adapter
))
4091 spin_lock_bh(&adapter
->mcc_lock
);
4093 wrb
= wrb_from_mccq(adapter
);
4099 req
= embedded_payload(wrb
);
4101 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
4102 OPCODE_COMMON_ENABLE_DISABLE_VF
, sizeof(*req
),
4105 req
->hdr
.domain
= domain
;
4107 status
= be_mcc_notify_wait(adapter
);
4109 spin_unlock_bh(&adapter
->mcc_lock
);
4113 int be_cmd_intr_set(struct be_adapter
*adapter
, bool intr_enable
)
4115 struct be_mcc_wrb
*wrb
;
4116 struct be_cmd_req_intr_set
*req
;
4119 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
4122 wrb
= wrb_from_mbox(adapter
);
4124 req
= embedded_payload(wrb
);
4126 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
4127 OPCODE_COMMON_SET_INTERRUPT_ENABLE
, sizeof(*req
),
4130 req
->intr_enabled
= intr_enable
;
4132 status
= be_mbox_notify_wait(adapter
);
4134 mutex_unlock(&adapter
->mbox_lock
);
4139 int be_cmd_get_active_profile(struct be_adapter
*adapter
, u16
*profile_id
)
4141 struct be_cmd_req_get_active_profile
*req
;
4142 struct be_mcc_wrb
*wrb
;
4145 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
4148 wrb
= wrb_from_mbox(adapter
);
4154 req
= embedded_payload(wrb
);
4156 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
4157 OPCODE_COMMON_GET_ACTIVE_PROFILE
, sizeof(*req
),
4160 status
= be_mbox_notify_wait(adapter
);
4162 struct be_cmd_resp_get_active_profile
*resp
=
4163 embedded_payload(wrb
);
4165 *profile_id
= le16_to_cpu(resp
->active_profile_id
);
4169 mutex_unlock(&adapter
->mbox_lock
);
4173 int be_cmd_set_logical_link_config(struct be_adapter
*adapter
,
4174 int link_state
, u8 domain
)
4176 struct be_mcc_wrb
*wrb
;
4177 struct be_cmd_req_set_ll_link
*req
;
4180 if (BEx_chip(adapter
) || lancer_chip(adapter
))
4183 spin_lock_bh(&adapter
->mcc_lock
);
4185 wrb
= wrb_from_mccq(adapter
);
4191 req
= embedded_payload(wrb
);
4193 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
4194 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG
,
4195 sizeof(*req
), wrb
, NULL
);
4197 req
->hdr
.version
= 1;
4198 req
->hdr
.domain
= domain
;
4200 if (link_state
== IFLA_VF_LINK_STATE_ENABLE
)
4201 req
->link_config
|= 1;
4203 if (link_state
== IFLA_VF_LINK_STATE_AUTO
)
4204 req
->link_config
|= 1 << PLINK_TRACK_SHIFT
;
4206 status
= be_mcc_notify_wait(adapter
);
4208 spin_unlock_bh(&adapter
->mcc_lock
);
4212 int be_roce_mcc_cmd(void *netdev_handle
, void *wrb_payload
,
4213 int wrb_payload_size
, u16
*cmd_status
, u16
*ext_status
)
4215 struct be_adapter
*adapter
= netdev_priv(netdev_handle
);
4216 struct be_mcc_wrb
*wrb
;
4217 struct be_cmd_req_hdr
*hdr
= (struct be_cmd_req_hdr
*)wrb_payload
;
4218 struct be_cmd_req_hdr
*req
;
4219 struct be_cmd_resp_hdr
*resp
;
4222 spin_lock_bh(&adapter
->mcc_lock
);
4224 wrb
= wrb_from_mccq(adapter
);
4229 req
= embedded_payload(wrb
);
4230 resp
= embedded_payload(wrb
);
4232 be_wrb_cmd_hdr_prepare(req
, hdr
->subsystem
,
4233 hdr
->opcode
, wrb_payload_size
, wrb
, NULL
);
4234 memcpy(req
, wrb_payload
, wrb_payload_size
);
4235 be_dws_cpu_to_le(req
, wrb_payload_size
);
4237 status
= be_mcc_notify_wait(adapter
);
4239 *cmd_status
= (status
& 0xffff);
4242 memcpy(wrb_payload
, resp
, sizeof(*resp
) + resp
->response_length
);
4243 be_dws_le_to_cpu(wrb_payload
, sizeof(*resp
) + resp
->response_length
);
4245 spin_unlock_bh(&adapter
->mcc_lock
);
4248 EXPORT_SYMBOL(be_roce_mcc_cmd
);