2 * Copyright (C) 2005 - 2013 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
18 #include <linux/module.h>
22 static struct be_cmd_priv_map cmd_priv_map
[] = {
24 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
,
26 BE_PRIV_LNKMGMT
| BE_PRIV_VHADM
|
27 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
30 OPCODE_COMMON_GET_FLOW_CONTROL
,
32 BE_PRIV_LNKQUERY
| BE_PRIV_VHADM
|
33 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
36 OPCODE_COMMON_SET_FLOW_CONTROL
,
38 BE_PRIV_LNKMGMT
| BE_PRIV_VHADM
|
39 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
42 OPCODE_ETH_GET_PPORT_STATS
,
44 BE_PRIV_LNKMGMT
| BE_PRIV_VHADM
|
45 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
48 OPCODE_COMMON_GET_PHY_DETAILS
,
50 BE_PRIV_LNKMGMT
| BE_PRIV_VHADM
|
51 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
55 static bool be_cmd_allowed(struct be_adapter
*adapter
, u8 opcode
,
59 int num_entries
= sizeof(cmd_priv_map
)/sizeof(struct be_cmd_priv_map
);
60 u32 cmd_privileges
= adapter
->cmd_privileges
;
62 for (i
= 0; i
< num_entries
; i
++)
63 if (opcode
== cmd_priv_map
[i
].opcode
&&
64 subsystem
== cmd_priv_map
[i
].subsystem
)
65 if (!(cmd_privileges
& cmd_priv_map
[i
].priv_mask
))
71 static inline void *embedded_payload(struct be_mcc_wrb
*wrb
)
73 return wrb
->payload
.embedded_payload
;
76 static void be_mcc_notify(struct be_adapter
*adapter
)
78 struct be_queue_info
*mccq
= &adapter
->mcc_obj
.q
;
81 if (be_error(adapter
))
84 val
|= mccq
->id
& DB_MCCQ_RING_ID_MASK
;
85 val
|= 1 << DB_MCCQ_NUM_POSTED_SHIFT
;
88 iowrite32(val
, adapter
->db
+ DB_MCCQ_OFFSET
);
91 /* To check if valid bit is set, check the entire word as we don't know
92 * the endianness of the data (old entry is host endian while a new entry is
94 static inline bool be_mcc_compl_is_new(struct be_mcc_compl
*compl)
98 if (compl->flags
!= 0) {
99 flags
= le32_to_cpu(compl->flags
);
100 if (flags
& CQE_FLAGS_VALID_MASK
) {
101 compl->flags
= flags
;
108 /* Need to reset the entire word that houses the valid bit */
109 static inline void be_mcc_compl_use(struct be_mcc_compl
*compl)
114 static struct be_cmd_resp_hdr
*be_decode_resp_hdr(u32 tag0
, u32 tag1
)
119 addr
= ((addr
<< 16) << 16) | tag0
;
123 static int be_mcc_compl_process(struct be_adapter
*adapter
,
124 struct be_mcc_compl
*compl)
126 u16 compl_status
, extd_status
;
127 struct be_cmd_resp_hdr
*resp_hdr
;
128 u8 opcode
= 0, subsystem
= 0;
130 /* Just swap the status to host endian; mcc tag is opaquely copied
132 be_dws_le_to_cpu(compl, 4);
134 compl_status
= (compl->status
>> CQE_STATUS_COMPL_SHIFT
) &
135 CQE_STATUS_COMPL_MASK
;
137 resp_hdr
= be_decode_resp_hdr(compl->tag0
, compl->tag1
);
140 opcode
= resp_hdr
->opcode
;
141 subsystem
= resp_hdr
->subsystem
;
144 if (((opcode
== OPCODE_COMMON_WRITE_FLASHROM
) ||
145 (opcode
== OPCODE_COMMON_WRITE_OBJECT
)) &&
146 (subsystem
== CMD_SUBSYSTEM_COMMON
)) {
147 adapter
->flash_status
= compl_status
;
148 complete(&adapter
->flash_compl
);
151 if (compl_status
== MCC_STATUS_SUCCESS
) {
152 if (((opcode
== OPCODE_ETH_GET_STATISTICS
) ||
153 (opcode
== OPCODE_ETH_GET_PPORT_STATS
)) &&
154 (subsystem
== CMD_SUBSYSTEM_ETH
)) {
155 be_parse_stats(adapter
);
156 adapter
->stats_cmd_sent
= false;
158 if (opcode
== OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES
&&
159 subsystem
== CMD_SUBSYSTEM_COMMON
) {
160 struct be_cmd_resp_get_cntl_addnl_attribs
*resp
=
162 adapter
->drv_stats
.be_on_die_temperature
=
163 resp
->on_die_temperature
;
166 if (opcode
== OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES
)
167 adapter
->be_get_temp_freq
= 0;
169 if (compl_status
== MCC_STATUS_NOT_SUPPORTED
||
170 compl_status
== MCC_STATUS_ILLEGAL_REQUEST
)
173 if (compl_status
== MCC_STATUS_UNAUTHORIZED_REQUEST
) {
174 dev_warn(&adapter
->pdev
->dev
,
175 "VF is not privileged to issue opcode %d-%d\n",
178 extd_status
= (compl->status
>> CQE_STATUS_EXTD_SHIFT
) &
179 CQE_STATUS_EXTD_MASK
;
180 dev_err(&adapter
->pdev
->dev
,
181 "opcode %d-%d failed:status %d-%d\n",
182 opcode
, subsystem
, compl_status
, extd_status
);
189 /* Link state evt is a string of bytes; no need for endian swapping */
190 static void be_async_link_state_process(struct be_adapter
*adapter
,
191 struct be_async_event_link_state
*evt
)
193 /* When link status changes, link speed must be re-queried from FW */
194 adapter
->phy
.link_speed
= -1;
196 /* Ignore physical link event */
197 if (lancer_chip(adapter
) &&
198 !(evt
->port_link_status
& LOGICAL_LINK_STATUS_MASK
))
201 /* For the initial link status do not rely on the ASYNC event as
202 * it may not be received in some cases.
204 if (adapter
->flags
& BE_FLAGS_LINK_STATUS_INIT
)
205 be_link_status_update(adapter
, evt
->port_link_status
);
208 /* Grp5 CoS Priority evt */
209 static void be_async_grp5_cos_priority_process(struct be_adapter
*adapter
,
210 struct be_async_event_grp5_cos_priority
*evt
)
213 adapter
->vlan_prio_bmap
= evt
->available_priority_bmap
;
214 adapter
->recommended_prio
&= ~VLAN_PRIO_MASK
;
215 adapter
->recommended_prio
=
216 evt
->reco_default_priority
<< VLAN_PRIO_SHIFT
;
220 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
221 static void be_async_grp5_qos_speed_process(struct be_adapter
*adapter
,
222 struct be_async_event_grp5_qos_link_speed
*evt
)
224 if (adapter
->phy
.link_speed
>= 0 &&
225 evt
->physical_port
== adapter
->port_num
)
226 adapter
->phy
.link_speed
= le16_to_cpu(evt
->qos_link_speed
) * 10;
230 static void be_async_grp5_pvid_state_process(struct be_adapter
*adapter
,
231 struct be_async_event_grp5_pvid_state
*evt
)
234 adapter
->pvid
= le16_to_cpu(evt
->tag
) & VLAN_VID_MASK
;
239 static void be_async_grp5_evt_process(struct be_adapter
*adapter
,
240 u32 trailer
, struct be_mcc_compl
*evt
)
244 event_type
= (trailer
>> ASYNC_TRAILER_EVENT_TYPE_SHIFT
) &
245 ASYNC_TRAILER_EVENT_TYPE_MASK
;
247 switch (event_type
) {
248 case ASYNC_EVENT_COS_PRIORITY
:
249 be_async_grp5_cos_priority_process(adapter
,
250 (struct be_async_event_grp5_cos_priority
*)evt
);
252 case ASYNC_EVENT_QOS_SPEED
:
253 be_async_grp5_qos_speed_process(adapter
,
254 (struct be_async_event_grp5_qos_link_speed
*)evt
);
256 case ASYNC_EVENT_PVID_STATE
:
257 be_async_grp5_pvid_state_process(adapter
,
258 (struct be_async_event_grp5_pvid_state
*)evt
);
261 dev_warn(&adapter
->pdev
->dev
, "Unknown grp5 event!\n");
266 static void be_async_dbg_evt_process(struct be_adapter
*adapter
,
267 u32 trailer
, struct be_mcc_compl
*cmp
)
270 struct be_async_event_qnq
*evt
= (struct be_async_event_qnq
*) cmp
;
272 event_type
= (trailer
>> ASYNC_TRAILER_EVENT_TYPE_SHIFT
) &
273 ASYNC_TRAILER_EVENT_TYPE_MASK
;
275 switch (event_type
) {
276 case ASYNC_DEBUG_EVENT_TYPE_QNQ
:
278 adapter
->qnq_vid
= le16_to_cpu(evt
->vlan_tag
);
279 adapter
->flags
|= BE_FLAGS_QNQ_ASYNC_EVT_RCVD
;
282 dev_warn(&adapter
->pdev
->dev
, "Unknown debug event\n");
287 static inline bool is_link_state_evt(u32 trailer
)
289 return ((trailer
>> ASYNC_TRAILER_EVENT_CODE_SHIFT
) &
290 ASYNC_TRAILER_EVENT_CODE_MASK
) ==
291 ASYNC_EVENT_CODE_LINK_STATE
;
294 static inline bool is_grp5_evt(u32 trailer
)
296 return (((trailer
>> ASYNC_TRAILER_EVENT_CODE_SHIFT
) &
297 ASYNC_TRAILER_EVENT_CODE_MASK
) ==
298 ASYNC_EVENT_CODE_GRP_5
);
301 static inline bool is_dbg_evt(u32 trailer
)
303 return (((trailer
>> ASYNC_TRAILER_EVENT_CODE_SHIFT
) &
304 ASYNC_TRAILER_EVENT_CODE_MASK
) ==
305 ASYNC_EVENT_CODE_QNQ
);
308 static struct be_mcc_compl
*be_mcc_compl_get(struct be_adapter
*adapter
)
310 struct be_queue_info
*mcc_cq
= &adapter
->mcc_obj
.cq
;
311 struct be_mcc_compl
*compl = queue_tail_node(mcc_cq
);
313 if (be_mcc_compl_is_new(compl)) {
314 queue_tail_inc(mcc_cq
);
320 void be_async_mcc_enable(struct be_adapter
*adapter
)
322 spin_lock_bh(&adapter
->mcc_cq_lock
);
324 be_cq_notify(adapter
, adapter
->mcc_obj
.cq
.id
, true, 0);
325 adapter
->mcc_obj
.rearm_cq
= true;
327 spin_unlock_bh(&adapter
->mcc_cq_lock
);
330 void be_async_mcc_disable(struct be_adapter
*adapter
)
332 spin_lock_bh(&adapter
->mcc_cq_lock
);
334 adapter
->mcc_obj
.rearm_cq
= false;
335 be_cq_notify(adapter
, adapter
->mcc_obj
.cq
.id
, false, 0);
337 spin_unlock_bh(&adapter
->mcc_cq_lock
);
340 int be_process_mcc(struct be_adapter
*adapter
)
342 struct be_mcc_compl
*compl;
343 int num
= 0, status
= 0;
344 struct be_mcc_obj
*mcc_obj
= &adapter
->mcc_obj
;
346 spin_lock(&adapter
->mcc_cq_lock
);
347 while ((compl = be_mcc_compl_get(adapter
))) {
348 if (compl->flags
& CQE_FLAGS_ASYNC_MASK
) {
349 /* Interpret flags as an async trailer */
350 if (is_link_state_evt(compl->flags
))
351 be_async_link_state_process(adapter
,
352 (struct be_async_event_link_state
*) compl);
353 else if (is_grp5_evt(compl->flags
))
354 be_async_grp5_evt_process(adapter
,
355 compl->flags
, compl);
356 else if (is_dbg_evt(compl->flags
))
357 be_async_dbg_evt_process(adapter
,
358 compl->flags
, compl);
359 } else if (compl->flags
& CQE_FLAGS_COMPLETED_MASK
) {
360 status
= be_mcc_compl_process(adapter
, compl);
361 atomic_dec(&mcc_obj
->q
.used
);
363 be_mcc_compl_use(compl);
368 be_cq_notify(adapter
, mcc_obj
->cq
.id
, mcc_obj
->rearm_cq
, num
);
370 spin_unlock(&adapter
->mcc_cq_lock
);
374 /* Wait till no more pending mcc requests are present */
375 static int be_mcc_wait_compl(struct be_adapter
*adapter
)
377 #define mcc_timeout 120000 /* 12s timeout */
379 struct be_mcc_obj
*mcc_obj
= &adapter
->mcc_obj
;
381 for (i
= 0; i
< mcc_timeout
; i
++) {
382 if (be_error(adapter
))
386 status
= be_process_mcc(adapter
);
389 if (atomic_read(&mcc_obj
->q
.used
) == 0)
393 if (i
== mcc_timeout
) {
394 dev_err(&adapter
->pdev
->dev
, "FW not responding\n");
395 adapter
->fw_timeout
= true;
401 /* Notify MCC requests and wait for completion */
402 static int be_mcc_notify_wait(struct be_adapter
*adapter
)
405 struct be_mcc_wrb
*wrb
;
406 struct be_mcc_obj
*mcc_obj
= &adapter
->mcc_obj
;
407 u16 index
= mcc_obj
->q
.head
;
408 struct be_cmd_resp_hdr
*resp
;
410 index_dec(&index
, mcc_obj
->q
.len
);
411 wrb
= queue_index_node(&mcc_obj
->q
, index
);
413 resp
= be_decode_resp_hdr(wrb
->tag0
, wrb
->tag1
);
415 be_mcc_notify(adapter
);
417 status
= be_mcc_wait_compl(adapter
);
421 status
= resp
->status
;
426 static int be_mbox_db_ready_wait(struct be_adapter
*adapter
, void __iomem
*db
)
432 if (be_error(adapter
))
435 ready
= ioread32(db
);
436 if (ready
== 0xffffffff)
439 ready
&= MPU_MAILBOX_DB_RDY_MASK
;
444 dev_err(&adapter
->pdev
->dev
, "FW not responding\n");
445 adapter
->fw_timeout
= true;
446 be_detect_error(adapter
);
458 * Insert the mailbox address into the doorbell in two steps
459 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
461 static int be_mbox_notify_wait(struct be_adapter
*adapter
)
465 void __iomem
*db
= adapter
->db
+ MPU_MAILBOX_DB_OFFSET
;
466 struct be_dma_mem
*mbox_mem
= &adapter
->mbox_mem
;
467 struct be_mcc_mailbox
*mbox
= mbox_mem
->va
;
468 struct be_mcc_compl
*compl = &mbox
->compl;
470 /* wait for ready to be set */
471 status
= be_mbox_db_ready_wait(adapter
, db
);
475 val
|= MPU_MAILBOX_DB_HI_MASK
;
476 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
477 val
|= (upper_32_bits(mbox_mem
->dma
) >> 2) << 2;
480 /* wait for ready to be set */
481 status
= be_mbox_db_ready_wait(adapter
, db
);
486 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
487 val
|= (u32
)(mbox_mem
->dma
>> 4) << 2;
490 status
= be_mbox_db_ready_wait(adapter
, db
);
494 /* A cq entry has been made now */
495 if (be_mcc_compl_is_new(compl)) {
496 status
= be_mcc_compl_process(adapter
, &mbox
->compl);
497 be_mcc_compl_use(compl);
501 dev_err(&adapter
->pdev
->dev
, "invalid mailbox completion\n");
507 static u16
be_POST_stage_get(struct be_adapter
*adapter
)
511 if (BEx_chip(adapter
))
512 sem
= ioread32(adapter
->csr
+ SLIPORT_SEMAPHORE_OFFSET_BEx
);
514 pci_read_config_dword(adapter
->pdev
,
515 SLIPORT_SEMAPHORE_OFFSET_SH
, &sem
);
517 return sem
& POST_STAGE_MASK
;
520 int lancer_wait_ready(struct be_adapter
*adapter
)
522 #define SLIPORT_READY_TIMEOUT 30
526 for (i
= 0; i
< SLIPORT_READY_TIMEOUT
; i
++) {
527 sliport_status
= ioread32(adapter
->db
+ SLIPORT_STATUS_OFFSET
);
528 if (sliport_status
& SLIPORT_STATUS_RDY_MASK
)
534 if (i
== SLIPORT_READY_TIMEOUT
)
540 static bool lancer_provisioning_error(struct be_adapter
*adapter
)
542 u32 sliport_status
= 0, sliport_err1
= 0, sliport_err2
= 0;
543 sliport_status
= ioread32(adapter
->db
+ SLIPORT_STATUS_OFFSET
);
544 if (sliport_status
& SLIPORT_STATUS_ERR_MASK
) {
545 sliport_err1
= ioread32(adapter
->db
+
546 SLIPORT_ERROR1_OFFSET
);
547 sliport_err2
= ioread32(adapter
->db
+
548 SLIPORT_ERROR2_OFFSET
);
550 if (sliport_err1
== SLIPORT_ERROR_NO_RESOURCE1
&&
551 sliport_err2
== SLIPORT_ERROR_NO_RESOURCE2
)
557 int lancer_test_and_set_rdy_state(struct be_adapter
*adapter
)
560 u32 sliport_status
, err
, reset_needed
;
563 resource_error
= lancer_provisioning_error(adapter
);
567 status
= lancer_wait_ready(adapter
);
569 sliport_status
= ioread32(adapter
->db
+ SLIPORT_STATUS_OFFSET
);
570 err
= sliport_status
& SLIPORT_STATUS_ERR_MASK
;
571 reset_needed
= sliport_status
& SLIPORT_STATUS_RN_MASK
;
572 if (err
&& reset_needed
) {
573 iowrite32(SLI_PORT_CONTROL_IP_MASK
,
574 adapter
->db
+ SLIPORT_CONTROL_OFFSET
);
576 /* check adapter has corrected the error */
577 status
= lancer_wait_ready(adapter
);
578 sliport_status
= ioread32(adapter
->db
+
579 SLIPORT_STATUS_OFFSET
);
580 sliport_status
&= (SLIPORT_STATUS_ERR_MASK
|
581 SLIPORT_STATUS_RN_MASK
);
582 if (status
|| sliport_status
)
584 } else if (err
|| reset_needed
) {
588 /* Stop error recovery if error is not recoverable.
589 * No resource error is temporary errors and will go away
590 * when PF provisions resources.
592 resource_error
= lancer_provisioning_error(adapter
);
593 if (status
== -1 && !resource_error
)
594 adapter
->eeh_error
= true;
599 int be_fw_wait_ready(struct be_adapter
*adapter
)
602 int status
, timeout
= 0;
603 struct device
*dev
= &adapter
->pdev
->dev
;
605 if (lancer_chip(adapter
)) {
606 status
= lancer_wait_ready(adapter
);
611 stage
= be_POST_stage_get(adapter
);
612 if (stage
== POST_STAGE_ARMFW_RDY
)
615 dev_info(dev
, "Waiting for POST, %ds elapsed\n",
617 if (msleep_interruptible(2000)) {
618 dev_err(dev
, "Waiting for POST aborted\n");
622 } while (timeout
< 60);
624 dev_err(dev
, "POST timeout; stage=0x%x\n", stage
);
629 static inline struct be_sge
*nonembedded_sgl(struct be_mcc_wrb
*wrb
)
631 return &wrb
->payload
.sgl
[0];
635 /* Don't touch the hdr after it's prepared */
636 /* mem will be NULL for embedded commands */
637 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr
*req_hdr
,
638 u8 subsystem
, u8 opcode
, int cmd_len
,
639 struct be_mcc_wrb
*wrb
, struct be_dma_mem
*mem
)
642 unsigned long addr
= (unsigned long)req_hdr
;
645 req_hdr
->opcode
= opcode
;
646 req_hdr
->subsystem
= subsystem
;
647 req_hdr
->request_length
= cpu_to_le32(cmd_len
- sizeof(*req_hdr
));
648 req_hdr
->version
= 0;
650 wrb
->tag0
= req_addr
& 0xFFFFFFFF;
651 wrb
->tag1
= upper_32_bits(req_addr
);
653 wrb
->payload_length
= cmd_len
;
655 wrb
->embedded
|= (1 & MCC_WRB_SGE_CNT_MASK
) <<
656 MCC_WRB_SGE_CNT_SHIFT
;
657 sge
= nonembedded_sgl(wrb
);
658 sge
->pa_hi
= cpu_to_le32(upper_32_bits(mem
->dma
));
659 sge
->pa_lo
= cpu_to_le32(mem
->dma
& 0xFFFFFFFF);
660 sge
->len
= cpu_to_le32(mem
->size
);
662 wrb
->embedded
|= MCC_WRB_EMBEDDED_MASK
;
663 be_dws_cpu_to_le(wrb
, 8);
666 static void be_cmd_page_addrs_prepare(struct phys_addr
*pages
, u32 max_pages
,
667 struct be_dma_mem
*mem
)
669 int i
, buf_pages
= min(PAGES_4K_SPANNED(mem
->va
, mem
->size
), max_pages
);
670 u64 dma
= (u64
)mem
->dma
;
672 for (i
= 0; i
< buf_pages
; i
++) {
673 pages
[i
].lo
= cpu_to_le32(dma
& 0xFFFFFFFF);
674 pages
[i
].hi
= cpu_to_le32(upper_32_bits(dma
));
679 /* Converts interrupt delay in microseconds to multiplier value */
680 static u32
eq_delay_to_mult(u32 usec_delay
)
682 #define MAX_INTR_RATE 651042
683 const u32 round
= 10;
689 u32 interrupt_rate
= 1000000 / usec_delay
;
690 /* Max delay, corresponding to the lowest interrupt rate */
691 if (interrupt_rate
== 0)
694 multiplier
= (MAX_INTR_RATE
- interrupt_rate
) * round
;
695 multiplier
/= interrupt_rate
;
696 /* Round the multiplier to the closest value.*/
697 multiplier
= (multiplier
+ round
/2) / round
;
698 multiplier
= min(multiplier
, (u32
)1023);
704 static inline struct be_mcc_wrb
*wrb_from_mbox(struct be_adapter
*adapter
)
706 struct be_dma_mem
*mbox_mem
= &adapter
->mbox_mem
;
707 struct be_mcc_wrb
*wrb
708 = &((struct be_mcc_mailbox
*)(mbox_mem
->va
))->wrb
;
709 memset(wrb
, 0, sizeof(*wrb
));
713 static struct be_mcc_wrb
*wrb_from_mccq(struct be_adapter
*adapter
)
715 struct be_queue_info
*mccq
= &adapter
->mcc_obj
.q
;
716 struct be_mcc_wrb
*wrb
;
721 if (atomic_read(&mccq
->used
) >= mccq
->len
)
724 wrb
= queue_head_node(mccq
);
725 queue_head_inc(mccq
);
726 atomic_inc(&mccq
->used
);
727 memset(wrb
, 0, sizeof(*wrb
));
731 /* Tell fw we're about to start firing cmds by writing a
732 * special pattern across the wrb hdr; uses mbox
734 int be_cmd_fw_init(struct be_adapter
*adapter
)
739 if (lancer_chip(adapter
))
742 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
745 wrb
= (u8
*)wrb_from_mbox(adapter
);
755 status
= be_mbox_notify_wait(adapter
);
757 mutex_unlock(&adapter
->mbox_lock
);
761 /* Tell fw we're done with firing cmds by writing a
762 * special pattern across the wrb hdr; uses mbox
764 int be_cmd_fw_clean(struct be_adapter
*adapter
)
769 if (lancer_chip(adapter
))
772 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
775 wrb
= (u8
*)wrb_from_mbox(adapter
);
785 status
= be_mbox_notify_wait(adapter
);
787 mutex_unlock(&adapter
->mbox_lock
);
791 int be_cmd_eq_create(struct be_adapter
*adapter
,
792 struct be_queue_info
*eq
, int eq_delay
)
794 struct be_mcc_wrb
*wrb
;
795 struct be_cmd_req_eq_create
*req
;
796 struct be_dma_mem
*q_mem
= &eq
->dma_mem
;
799 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
802 wrb
= wrb_from_mbox(adapter
);
803 req
= embedded_payload(wrb
);
805 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
806 OPCODE_COMMON_EQ_CREATE
, sizeof(*req
), wrb
, NULL
);
808 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
810 AMAP_SET_BITS(struct amap_eq_context
, valid
, req
->context
, 1);
812 AMAP_SET_BITS(struct amap_eq_context
, size
, req
->context
, 0);
813 AMAP_SET_BITS(struct amap_eq_context
, count
, req
->context
,
814 __ilog2_u32(eq
->len
/256));
815 AMAP_SET_BITS(struct amap_eq_context
, delaymult
, req
->context
,
816 eq_delay_to_mult(eq_delay
));
817 be_dws_cpu_to_le(req
->context
, sizeof(req
->context
));
819 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
821 status
= be_mbox_notify_wait(adapter
);
823 struct be_cmd_resp_eq_create
*resp
= embedded_payload(wrb
);
824 eq
->id
= le16_to_cpu(resp
->eq_id
);
828 mutex_unlock(&adapter
->mbox_lock
);
833 int be_cmd_mac_addr_query(struct be_adapter
*adapter
, u8
*mac_addr
,
834 bool permanent
, u32 if_handle
, u32 pmac_id
)
836 struct be_mcc_wrb
*wrb
;
837 struct be_cmd_req_mac_query
*req
;
840 spin_lock_bh(&adapter
->mcc_lock
);
842 wrb
= wrb_from_mccq(adapter
);
847 req
= embedded_payload(wrb
);
849 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
850 OPCODE_COMMON_NTWK_MAC_QUERY
, sizeof(*req
), wrb
, NULL
);
851 req
->type
= MAC_ADDRESS_TYPE_NETWORK
;
855 req
->if_id
= cpu_to_le16((u16
) if_handle
);
856 req
->pmac_id
= cpu_to_le32(pmac_id
);
860 status
= be_mcc_notify_wait(adapter
);
862 struct be_cmd_resp_mac_query
*resp
= embedded_payload(wrb
);
863 memcpy(mac_addr
, resp
->mac
.addr
, ETH_ALEN
);
867 spin_unlock_bh(&adapter
->mcc_lock
);
871 /* Uses synchronous MCCQ */
872 int be_cmd_pmac_add(struct be_adapter
*adapter
, u8
*mac_addr
,
873 u32 if_id
, u32
*pmac_id
, u32 domain
)
875 struct be_mcc_wrb
*wrb
;
876 struct be_cmd_req_pmac_add
*req
;
879 spin_lock_bh(&adapter
->mcc_lock
);
881 wrb
= wrb_from_mccq(adapter
);
886 req
= embedded_payload(wrb
);
888 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
889 OPCODE_COMMON_NTWK_PMAC_ADD
, sizeof(*req
), wrb
, NULL
);
891 req
->hdr
.domain
= domain
;
892 req
->if_id
= cpu_to_le32(if_id
);
893 memcpy(req
->mac_address
, mac_addr
, ETH_ALEN
);
895 status
= be_mcc_notify_wait(adapter
);
897 struct be_cmd_resp_pmac_add
*resp
= embedded_payload(wrb
);
898 *pmac_id
= le32_to_cpu(resp
->pmac_id
);
902 spin_unlock_bh(&adapter
->mcc_lock
);
904 if (status
== MCC_STATUS_UNAUTHORIZED_REQUEST
)
910 /* Uses synchronous MCCQ */
911 int be_cmd_pmac_del(struct be_adapter
*adapter
, u32 if_id
, int pmac_id
, u32 dom
)
913 struct be_mcc_wrb
*wrb
;
914 struct be_cmd_req_pmac_del
*req
;
920 spin_lock_bh(&adapter
->mcc_lock
);
922 wrb
= wrb_from_mccq(adapter
);
927 req
= embedded_payload(wrb
);
929 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
930 OPCODE_COMMON_NTWK_PMAC_DEL
, sizeof(*req
), wrb
, NULL
);
932 req
->hdr
.domain
= dom
;
933 req
->if_id
= cpu_to_le32(if_id
);
934 req
->pmac_id
= cpu_to_le32(pmac_id
);
936 status
= be_mcc_notify_wait(adapter
);
939 spin_unlock_bh(&adapter
->mcc_lock
);
944 int be_cmd_cq_create(struct be_adapter
*adapter
, struct be_queue_info
*cq
,
945 struct be_queue_info
*eq
, bool no_delay
, int coalesce_wm
)
947 struct be_mcc_wrb
*wrb
;
948 struct be_cmd_req_cq_create
*req
;
949 struct be_dma_mem
*q_mem
= &cq
->dma_mem
;
953 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
956 wrb
= wrb_from_mbox(adapter
);
957 req
= embedded_payload(wrb
);
958 ctxt
= &req
->context
;
960 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
961 OPCODE_COMMON_CQ_CREATE
, sizeof(*req
), wrb
, NULL
);
963 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
965 if (BEx_chip(adapter
)) {
966 AMAP_SET_BITS(struct amap_cq_context_be
, coalescwm
, ctxt
,
968 AMAP_SET_BITS(struct amap_cq_context_be
, nodelay
,
970 AMAP_SET_BITS(struct amap_cq_context_be
, count
, ctxt
,
971 __ilog2_u32(cq
->len
/256));
972 AMAP_SET_BITS(struct amap_cq_context_be
, valid
, ctxt
, 1);
973 AMAP_SET_BITS(struct amap_cq_context_be
, eventable
, ctxt
, 1);
974 AMAP_SET_BITS(struct amap_cq_context_be
, eqid
, ctxt
, eq
->id
);
976 req
->hdr
.version
= 2;
977 req
->page_size
= 1; /* 1 for 4K */
978 AMAP_SET_BITS(struct amap_cq_context_v2
, nodelay
, ctxt
,
980 AMAP_SET_BITS(struct amap_cq_context_v2
, count
, ctxt
,
981 __ilog2_u32(cq
->len
/256));
982 AMAP_SET_BITS(struct amap_cq_context_v2
, valid
, ctxt
, 1);
983 AMAP_SET_BITS(struct amap_cq_context_v2
, eventable
,
985 AMAP_SET_BITS(struct amap_cq_context_v2
, eqid
,
989 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
991 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
993 status
= be_mbox_notify_wait(adapter
);
995 struct be_cmd_resp_cq_create
*resp
= embedded_payload(wrb
);
996 cq
->id
= le16_to_cpu(resp
->cq_id
);
1000 mutex_unlock(&adapter
->mbox_lock
);
1005 static u32
be_encoded_q_len(int q_len
)
1007 u32 len_encoded
= fls(q_len
); /* log2(len) + 1 */
1008 if (len_encoded
== 16)
1013 int be_cmd_mccq_ext_create(struct be_adapter
*adapter
,
1014 struct be_queue_info
*mccq
,
1015 struct be_queue_info
*cq
)
1017 struct be_mcc_wrb
*wrb
;
1018 struct be_cmd_req_mcc_ext_create
*req
;
1019 struct be_dma_mem
*q_mem
= &mccq
->dma_mem
;
1023 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1026 wrb
= wrb_from_mbox(adapter
);
1027 req
= embedded_payload(wrb
);
1028 ctxt
= &req
->context
;
1030 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1031 OPCODE_COMMON_MCC_CREATE_EXT
, sizeof(*req
), wrb
, NULL
);
1033 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
1034 if (lancer_chip(adapter
)) {
1035 req
->hdr
.version
= 1;
1036 req
->cq_id
= cpu_to_le16(cq
->id
);
1038 AMAP_SET_BITS(struct amap_mcc_context_lancer
, ring_size
, ctxt
,
1039 be_encoded_q_len(mccq
->len
));
1040 AMAP_SET_BITS(struct amap_mcc_context_lancer
, valid
, ctxt
, 1);
1041 AMAP_SET_BITS(struct amap_mcc_context_lancer
, async_cq_id
,
1043 AMAP_SET_BITS(struct amap_mcc_context_lancer
, async_cq_valid
,
1047 AMAP_SET_BITS(struct amap_mcc_context_be
, valid
, ctxt
, 1);
1048 AMAP_SET_BITS(struct amap_mcc_context_be
, ring_size
, ctxt
,
1049 be_encoded_q_len(mccq
->len
));
1050 AMAP_SET_BITS(struct amap_mcc_context_be
, cq_id
, ctxt
, cq
->id
);
1053 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
1054 req
->async_event_bitmap
[0] = cpu_to_le32(0x00000022);
1055 req
->async_event_bitmap
[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ
);
1056 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
1058 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
1060 status
= be_mbox_notify_wait(adapter
);
1062 struct be_cmd_resp_mcc_create
*resp
= embedded_payload(wrb
);
1063 mccq
->id
= le16_to_cpu(resp
->id
);
1064 mccq
->created
= true;
1066 mutex_unlock(&adapter
->mbox_lock
);
1071 int be_cmd_mccq_org_create(struct be_adapter
*adapter
,
1072 struct be_queue_info
*mccq
,
1073 struct be_queue_info
*cq
)
1075 struct be_mcc_wrb
*wrb
;
1076 struct be_cmd_req_mcc_create
*req
;
1077 struct be_dma_mem
*q_mem
= &mccq
->dma_mem
;
1081 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1084 wrb
= wrb_from_mbox(adapter
);
1085 req
= embedded_payload(wrb
);
1086 ctxt
= &req
->context
;
1088 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1089 OPCODE_COMMON_MCC_CREATE
, sizeof(*req
), wrb
, NULL
);
1091 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
1093 AMAP_SET_BITS(struct amap_mcc_context_be
, valid
, ctxt
, 1);
1094 AMAP_SET_BITS(struct amap_mcc_context_be
, ring_size
, ctxt
,
1095 be_encoded_q_len(mccq
->len
));
1096 AMAP_SET_BITS(struct amap_mcc_context_be
, cq_id
, ctxt
, cq
->id
);
1098 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
1100 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
1102 status
= be_mbox_notify_wait(adapter
);
1104 struct be_cmd_resp_mcc_create
*resp
= embedded_payload(wrb
);
1105 mccq
->id
= le16_to_cpu(resp
->id
);
1106 mccq
->created
= true;
1109 mutex_unlock(&adapter
->mbox_lock
);
1113 int be_cmd_mccq_create(struct be_adapter
*adapter
,
1114 struct be_queue_info
*mccq
,
1115 struct be_queue_info
*cq
)
1119 status
= be_cmd_mccq_ext_create(adapter
, mccq
, cq
);
1120 if (status
&& !lancer_chip(adapter
)) {
1121 dev_warn(&adapter
->pdev
->dev
, "Upgrade to F/W ver 2.102.235.0 "
1122 "or newer to avoid conflicting priorities between NIC "
1123 "and FCoE traffic");
1124 status
= be_cmd_mccq_org_create(adapter
, mccq
, cq
);
1129 int be_cmd_txq_create(struct be_adapter
*adapter
, struct be_tx_obj
*txo
)
1131 struct be_mcc_wrb
*wrb
;
1132 struct be_cmd_req_eth_tx_create
*req
;
1133 struct be_queue_info
*txq
= &txo
->q
;
1134 struct be_queue_info
*cq
= &txo
->cq
;
1135 struct be_dma_mem
*q_mem
= &txq
->dma_mem
;
1136 int status
, ver
= 0;
1138 spin_lock_bh(&adapter
->mcc_lock
);
1140 wrb
= wrb_from_mccq(adapter
);
1146 req
= embedded_payload(wrb
);
1148 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1149 OPCODE_ETH_TX_CREATE
, sizeof(*req
), wrb
, NULL
);
1151 if (lancer_chip(adapter
)) {
1152 req
->hdr
.version
= 1;
1153 req
->if_id
= cpu_to_le16(adapter
->if_handle
);
1154 } else if (BEx_chip(adapter
)) {
1155 if (adapter
->function_caps
& BE_FUNCTION_CAPS_SUPER_NIC
)
1156 req
->hdr
.version
= 2;
1157 } else { /* For SH */
1158 req
->hdr
.version
= 2;
1161 req
->num_pages
= PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
);
1162 req
->ulp_num
= BE_ULP1_NUM
;
1163 req
->type
= BE_ETH_TX_RING_TYPE_STANDARD
;
1164 req
->cq_id
= cpu_to_le16(cq
->id
);
1165 req
->queue_size
= be_encoded_q_len(txq
->len
);
1166 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
1168 ver
= req
->hdr
.version
;
1170 status
= be_mcc_notify_wait(adapter
);
1172 struct be_cmd_resp_eth_tx_create
*resp
= embedded_payload(wrb
);
1173 txq
->id
= le16_to_cpu(resp
->cid
);
1175 txo
->db_offset
= le32_to_cpu(resp
->db_offset
);
1177 txo
->db_offset
= DB_TXULP1_OFFSET
;
1178 txq
->created
= true;
1182 spin_unlock_bh(&adapter
->mcc_lock
);
1188 int be_cmd_rxq_create(struct be_adapter
*adapter
,
1189 struct be_queue_info
*rxq
, u16 cq_id
, u16 frag_size
,
1190 u32 if_id
, u32 rss
, u8
*rss_id
)
1192 struct be_mcc_wrb
*wrb
;
1193 struct be_cmd_req_eth_rx_create
*req
;
1194 struct be_dma_mem
*q_mem
= &rxq
->dma_mem
;
1197 spin_lock_bh(&adapter
->mcc_lock
);
1199 wrb
= wrb_from_mccq(adapter
);
1204 req
= embedded_payload(wrb
);
1206 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1207 OPCODE_ETH_RX_CREATE
, sizeof(*req
), wrb
, NULL
);
1209 req
->cq_id
= cpu_to_le16(cq_id
);
1210 req
->frag_size
= fls(frag_size
) - 1;
1212 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
1213 req
->interface_id
= cpu_to_le32(if_id
);
1214 req
->max_frame_size
= cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE
);
1215 req
->rss_queue
= cpu_to_le32(rss
);
1217 status
= be_mcc_notify_wait(adapter
);
1219 struct be_cmd_resp_eth_rx_create
*resp
= embedded_payload(wrb
);
1220 rxq
->id
= le16_to_cpu(resp
->id
);
1221 rxq
->created
= true;
1222 *rss_id
= resp
->rss_id
;
1226 spin_unlock_bh(&adapter
->mcc_lock
);
1230 /* Generic destroyer function for all types of queues
1233 int be_cmd_q_destroy(struct be_adapter
*adapter
, struct be_queue_info
*q
,
1236 struct be_mcc_wrb
*wrb
;
1237 struct be_cmd_req_q_destroy
*req
;
1238 u8 subsys
= 0, opcode
= 0;
1241 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1244 wrb
= wrb_from_mbox(adapter
);
1245 req
= embedded_payload(wrb
);
1247 switch (queue_type
) {
1249 subsys
= CMD_SUBSYSTEM_COMMON
;
1250 opcode
= OPCODE_COMMON_EQ_DESTROY
;
1253 subsys
= CMD_SUBSYSTEM_COMMON
;
1254 opcode
= OPCODE_COMMON_CQ_DESTROY
;
1257 subsys
= CMD_SUBSYSTEM_ETH
;
1258 opcode
= OPCODE_ETH_TX_DESTROY
;
1261 subsys
= CMD_SUBSYSTEM_ETH
;
1262 opcode
= OPCODE_ETH_RX_DESTROY
;
1265 subsys
= CMD_SUBSYSTEM_COMMON
;
1266 opcode
= OPCODE_COMMON_MCC_DESTROY
;
1272 be_wrb_cmd_hdr_prepare(&req
->hdr
, subsys
, opcode
, sizeof(*req
), wrb
,
1274 req
->id
= cpu_to_le16(q
->id
);
1276 status
= be_mbox_notify_wait(adapter
);
1279 mutex_unlock(&adapter
->mbox_lock
);
1284 int be_cmd_rxq_destroy(struct be_adapter
*adapter
, struct be_queue_info
*q
)
1286 struct be_mcc_wrb
*wrb
;
1287 struct be_cmd_req_q_destroy
*req
;
1290 spin_lock_bh(&adapter
->mcc_lock
);
1292 wrb
= wrb_from_mccq(adapter
);
1297 req
= embedded_payload(wrb
);
1299 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1300 OPCODE_ETH_RX_DESTROY
, sizeof(*req
), wrb
, NULL
);
1301 req
->id
= cpu_to_le16(q
->id
);
1303 status
= be_mcc_notify_wait(adapter
);
1307 spin_unlock_bh(&adapter
->mcc_lock
);
1311 /* Create an rx filtering policy configuration on an i/f
1314 int be_cmd_if_create(struct be_adapter
*adapter
, u32 cap_flags
, u32 en_flags
,
1315 u32
*if_handle
, u32 domain
)
1317 struct be_mcc_wrb
*wrb
;
1318 struct be_cmd_req_if_create
*req
;
1321 spin_lock_bh(&adapter
->mcc_lock
);
1323 wrb
= wrb_from_mccq(adapter
);
1328 req
= embedded_payload(wrb
);
1330 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1331 OPCODE_COMMON_NTWK_INTERFACE_CREATE
, sizeof(*req
), wrb
, NULL
);
1332 req
->hdr
.domain
= domain
;
1333 req
->capability_flags
= cpu_to_le32(cap_flags
);
1334 req
->enable_flags
= cpu_to_le32(en_flags
);
1336 req
->pmac_invalid
= true;
1338 status
= be_mcc_notify_wait(adapter
);
1340 struct be_cmd_resp_if_create
*resp
= embedded_payload(wrb
);
1341 *if_handle
= le32_to_cpu(resp
->interface_id
);
1345 spin_unlock_bh(&adapter
->mcc_lock
);
1350 int be_cmd_if_destroy(struct be_adapter
*adapter
, int interface_id
, u32 domain
)
1352 struct be_mcc_wrb
*wrb
;
1353 struct be_cmd_req_if_destroy
*req
;
1356 if (interface_id
== -1)
1359 spin_lock_bh(&adapter
->mcc_lock
);
1361 wrb
= wrb_from_mccq(adapter
);
1366 req
= embedded_payload(wrb
);
1368 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1369 OPCODE_COMMON_NTWK_INTERFACE_DESTROY
, sizeof(*req
), wrb
, NULL
);
1370 req
->hdr
.domain
= domain
;
1371 req
->interface_id
= cpu_to_le32(interface_id
);
1373 status
= be_mcc_notify_wait(adapter
);
1375 spin_unlock_bh(&adapter
->mcc_lock
);
1379 /* Get stats is a non embedded command: the request is not embedded inside
1380 * WRB but is a separate dma memory block
1381 * Uses asynchronous MCC
1383 int be_cmd_get_stats(struct be_adapter
*adapter
, struct be_dma_mem
*nonemb_cmd
)
1385 struct be_mcc_wrb
*wrb
;
1386 struct be_cmd_req_hdr
*hdr
;
1389 spin_lock_bh(&adapter
->mcc_lock
);
1391 wrb
= wrb_from_mccq(adapter
);
1396 hdr
= nonemb_cmd
->va
;
1398 be_wrb_cmd_hdr_prepare(hdr
, CMD_SUBSYSTEM_ETH
,
1399 OPCODE_ETH_GET_STATISTICS
, nonemb_cmd
->size
, wrb
, nonemb_cmd
);
1401 /* version 1 of the cmd is not supported only by BE2 */
1402 if (!BE2_chip(adapter
))
1405 be_mcc_notify(adapter
);
1406 adapter
->stats_cmd_sent
= true;
1409 spin_unlock_bh(&adapter
->mcc_lock
);
1414 int lancer_cmd_get_pport_stats(struct be_adapter
*adapter
,
1415 struct be_dma_mem
*nonemb_cmd
)
1418 struct be_mcc_wrb
*wrb
;
1419 struct lancer_cmd_req_pport_stats
*req
;
1422 if (!be_cmd_allowed(adapter
, OPCODE_ETH_GET_PPORT_STATS
,
1426 spin_lock_bh(&adapter
->mcc_lock
);
1428 wrb
= wrb_from_mccq(adapter
);
1433 req
= nonemb_cmd
->va
;
1435 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1436 OPCODE_ETH_GET_PPORT_STATS
, nonemb_cmd
->size
, wrb
,
1439 req
->cmd_params
.params
.pport_num
= cpu_to_le16(adapter
->hba_port_num
);
1440 req
->cmd_params
.params
.reset_stats
= 0;
1442 be_mcc_notify(adapter
);
1443 adapter
->stats_cmd_sent
= true;
1446 spin_unlock_bh(&adapter
->mcc_lock
);
1450 static int be_mac_to_link_speed(int mac_speed
)
1452 switch (mac_speed
) {
1453 case PHY_LINK_SPEED_ZERO
:
1455 case PHY_LINK_SPEED_10MBPS
:
1457 case PHY_LINK_SPEED_100MBPS
:
1459 case PHY_LINK_SPEED_1GBPS
:
1461 case PHY_LINK_SPEED_10GBPS
:
1467 /* Uses synchronous mcc
1468 * Returns link_speed in Mbps
1470 int be_cmd_link_status_query(struct be_adapter
*adapter
, u16
*link_speed
,
1471 u8
*link_status
, u32 dom
)
1473 struct be_mcc_wrb
*wrb
;
1474 struct be_cmd_req_link_status
*req
;
1477 spin_lock_bh(&adapter
->mcc_lock
);
1480 *link_status
= LINK_DOWN
;
1482 wrb
= wrb_from_mccq(adapter
);
1487 req
= embedded_payload(wrb
);
1489 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1490 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY
, sizeof(*req
), wrb
, NULL
);
1492 /* version 1 of the cmd is not supported only by BE2 */
1493 if (!BE2_chip(adapter
))
1494 req
->hdr
.version
= 1;
1496 req
->hdr
.domain
= dom
;
1498 status
= be_mcc_notify_wait(adapter
);
1500 struct be_cmd_resp_link_status
*resp
= embedded_payload(wrb
);
1502 *link_speed
= resp
->link_speed
?
1503 le16_to_cpu(resp
->link_speed
) * 10 :
1504 be_mac_to_link_speed(resp
->mac_speed
);
1506 if (!resp
->logical_link_status
)
1510 *link_status
= resp
->logical_link_status
;
1514 spin_unlock_bh(&adapter
->mcc_lock
);
1518 /* Uses synchronous mcc */
1519 int be_cmd_get_die_temperature(struct be_adapter
*adapter
)
1521 struct be_mcc_wrb
*wrb
;
1522 struct be_cmd_req_get_cntl_addnl_attribs
*req
;
1525 spin_lock_bh(&adapter
->mcc_lock
);
1527 wrb
= wrb_from_mccq(adapter
);
1532 req
= embedded_payload(wrb
);
1534 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1535 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES
, sizeof(*req
),
1538 be_mcc_notify(adapter
);
1541 spin_unlock_bh(&adapter
->mcc_lock
);
1545 /* Uses synchronous mcc */
1546 int be_cmd_get_reg_len(struct be_adapter
*adapter
, u32
*log_size
)
1548 struct be_mcc_wrb
*wrb
;
1549 struct be_cmd_req_get_fat
*req
;
1552 spin_lock_bh(&adapter
->mcc_lock
);
1554 wrb
= wrb_from_mccq(adapter
);
1559 req
= embedded_payload(wrb
);
1561 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1562 OPCODE_COMMON_MANAGE_FAT
, sizeof(*req
), wrb
, NULL
);
1563 req
->fat_operation
= cpu_to_le32(QUERY_FAT
);
1564 status
= be_mcc_notify_wait(adapter
);
1566 struct be_cmd_resp_get_fat
*resp
= embedded_payload(wrb
);
1567 if (log_size
&& resp
->log_size
)
1568 *log_size
= le32_to_cpu(resp
->log_size
) -
1572 spin_unlock_bh(&adapter
->mcc_lock
);
1576 void be_cmd_get_regs(struct be_adapter
*adapter
, u32 buf_len
, void *buf
)
1578 struct be_dma_mem get_fat_cmd
;
1579 struct be_mcc_wrb
*wrb
;
1580 struct be_cmd_req_get_fat
*req
;
1581 u32 offset
= 0, total_size
, buf_size
,
1582 log_offset
= sizeof(u32
), payload_len
;
1588 total_size
= buf_len
;
1590 get_fat_cmd
.size
= sizeof(struct be_cmd_req_get_fat
) + 60*1024;
1591 get_fat_cmd
.va
= pci_alloc_consistent(adapter
->pdev
,
1594 if (!get_fat_cmd
.va
) {
1596 dev_err(&adapter
->pdev
->dev
,
1597 "Memory allocation failure while retrieving FAT data\n");
1601 spin_lock_bh(&adapter
->mcc_lock
);
1603 while (total_size
) {
1604 buf_size
= min(total_size
, (u32
)60*1024);
1605 total_size
-= buf_size
;
1607 wrb
= wrb_from_mccq(adapter
);
1612 req
= get_fat_cmd
.va
;
1614 payload_len
= sizeof(struct be_cmd_req_get_fat
) + buf_size
;
1615 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1616 OPCODE_COMMON_MANAGE_FAT
, payload_len
, wrb
,
1619 req
->fat_operation
= cpu_to_le32(RETRIEVE_FAT
);
1620 req
->read_log_offset
= cpu_to_le32(log_offset
);
1621 req
->read_log_length
= cpu_to_le32(buf_size
);
1622 req
->data_buffer_size
= cpu_to_le32(buf_size
);
1624 status
= be_mcc_notify_wait(adapter
);
1626 struct be_cmd_resp_get_fat
*resp
= get_fat_cmd
.va
;
1627 memcpy(buf
+ offset
,
1629 le32_to_cpu(resp
->read_log_length
));
1631 dev_err(&adapter
->pdev
->dev
, "FAT Table Retrieve error\n");
1635 log_offset
+= buf_size
;
1638 pci_free_consistent(adapter
->pdev
, get_fat_cmd
.size
,
1641 spin_unlock_bh(&adapter
->mcc_lock
);
1644 /* Uses synchronous mcc */
1645 int be_cmd_get_fw_ver(struct be_adapter
*adapter
, char *fw_ver
,
1648 struct be_mcc_wrb
*wrb
;
1649 struct be_cmd_req_get_fw_version
*req
;
1652 spin_lock_bh(&adapter
->mcc_lock
);
1654 wrb
= wrb_from_mccq(adapter
);
1660 req
= embedded_payload(wrb
);
1662 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1663 OPCODE_COMMON_GET_FW_VERSION
, sizeof(*req
), wrb
, NULL
);
1664 status
= be_mcc_notify_wait(adapter
);
1666 struct be_cmd_resp_get_fw_version
*resp
= embedded_payload(wrb
);
1667 strcpy(fw_ver
, resp
->firmware_version_string
);
1669 strcpy(fw_on_flash
, resp
->fw_on_flash_version_string
);
1672 spin_unlock_bh(&adapter
->mcc_lock
);
1676 /* set the EQ delay interval of an EQ to specified value
1679 int be_cmd_modify_eqd(struct be_adapter
*adapter
, u32 eq_id
, u32 eqd
)
1681 struct be_mcc_wrb
*wrb
;
1682 struct be_cmd_req_modify_eq_delay
*req
;
1685 spin_lock_bh(&adapter
->mcc_lock
);
1687 wrb
= wrb_from_mccq(adapter
);
1692 req
= embedded_payload(wrb
);
1694 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1695 OPCODE_COMMON_MODIFY_EQ_DELAY
, sizeof(*req
), wrb
, NULL
);
1697 req
->num_eq
= cpu_to_le32(1);
1698 req
->delay
[0].eq_id
= cpu_to_le32(eq_id
);
1699 req
->delay
[0].phase
= 0;
1700 req
->delay
[0].delay_multiplier
= cpu_to_le32(eqd
);
1702 be_mcc_notify(adapter
);
1705 spin_unlock_bh(&adapter
->mcc_lock
);
1709 /* Uses sycnhronous mcc */
1710 int be_cmd_vlan_config(struct be_adapter
*adapter
, u32 if_id
, u16
*vtag_array
,
1711 u32 num
, bool untagged
, bool promiscuous
)
1713 struct be_mcc_wrb
*wrb
;
1714 struct be_cmd_req_vlan_config
*req
;
1717 spin_lock_bh(&adapter
->mcc_lock
);
1719 wrb
= wrb_from_mccq(adapter
);
1724 req
= embedded_payload(wrb
);
1726 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1727 OPCODE_COMMON_NTWK_VLAN_CONFIG
, sizeof(*req
), wrb
, NULL
);
1729 req
->interface_id
= if_id
;
1730 req
->promiscuous
= promiscuous
;
1731 req
->untagged
= untagged
;
1732 req
->num_vlan
= num
;
1734 memcpy(req
->normal_vlan
, vtag_array
,
1735 req
->num_vlan
* sizeof(vtag_array
[0]));
1738 status
= be_mcc_notify_wait(adapter
);
1741 spin_unlock_bh(&adapter
->mcc_lock
);
1745 int be_cmd_rx_filter(struct be_adapter
*adapter
, u32 flags
, u32 value
)
1747 struct be_mcc_wrb
*wrb
;
1748 struct be_dma_mem
*mem
= &adapter
->rx_filter
;
1749 struct be_cmd_req_rx_filter
*req
= mem
->va
;
1752 spin_lock_bh(&adapter
->mcc_lock
);
1754 wrb
= wrb_from_mccq(adapter
);
1759 memset(req
, 0, sizeof(*req
));
1760 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1761 OPCODE_COMMON_NTWK_RX_FILTER
, sizeof(*req
),
1764 req
->if_id
= cpu_to_le32(adapter
->if_handle
);
1765 if (flags
& IFF_PROMISC
) {
1766 req
->if_flags_mask
= cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS
|
1767 BE_IF_FLAGS_VLAN_PROMISCUOUS
|
1768 BE_IF_FLAGS_MCAST_PROMISCUOUS
);
1770 req
->if_flags
= cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS
|
1771 BE_IF_FLAGS_VLAN_PROMISCUOUS
|
1772 BE_IF_FLAGS_MCAST_PROMISCUOUS
);
1773 } else if (flags
& IFF_ALLMULTI
) {
1774 req
->if_flags_mask
= req
->if_flags
=
1775 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS
);
1777 struct netdev_hw_addr
*ha
;
1780 req
->if_flags_mask
= req
->if_flags
=
1781 cpu_to_le32(BE_IF_FLAGS_MULTICAST
);
1783 /* Reset mcast promisc mode if already set by setting mask
1784 * and not setting flags field
1786 req
->if_flags_mask
|=
1787 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS
&
1788 adapter
->if_cap_flags
);
1790 req
->mcast_num
= cpu_to_le32(netdev_mc_count(adapter
->netdev
));
1791 netdev_for_each_mc_addr(ha
, adapter
->netdev
)
1792 memcpy(req
->mcast_mac
[i
++].byte
, ha
->addr
, ETH_ALEN
);
1795 status
= be_mcc_notify_wait(adapter
);
1797 spin_unlock_bh(&adapter
->mcc_lock
);
1801 /* Uses synchrounous mcc */
1802 int be_cmd_set_flow_control(struct be_adapter
*adapter
, u32 tx_fc
, u32 rx_fc
)
1804 struct be_mcc_wrb
*wrb
;
1805 struct be_cmd_req_set_flow_control
*req
;
1808 if (!be_cmd_allowed(adapter
, OPCODE_COMMON_SET_FLOW_CONTROL
,
1809 CMD_SUBSYSTEM_COMMON
))
1812 spin_lock_bh(&adapter
->mcc_lock
);
1814 wrb
= wrb_from_mccq(adapter
);
1819 req
= embedded_payload(wrb
);
1821 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1822 OPCODE_COMMON_SET_FLOW_CONTROL
, sizeof(*req
), wrb
, NULL
);
1824 req
->tx_flow_control
= cpu_to_le16((u16
)tx_fc
);
1825 req
->rx_flow_control
= cpu_to_le16((u16
)rx_fc
);
1827 status
= be_mcc_notify_wait(adapter
);
1830 spin_unlock_bh(&adapter
->mcc_lock
);
1835 int be_cmd_get_flow_control(struct be_adapter
*adapter
, u32
*tx_fc
, u32
*rx_fc
)
1837 struct be_mcc_wrb
*wrb
;
1838 struct be_cmd_req_get_flow_control
*req
;
1841 if (!be_cmd_allowed(adapter
, OPCODE_COMMON_GET_FLOW_CONTROL
,
1842 CMD_SUBSYSTEM_COMMON
))
1845 spin_lock_bh(&adapter
->mcc_lock
);
1847 wrb
= wrb_from_mccq(adapter
);
1852 req
= embedded_payload(wrb
);
1854 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1855 OPCODE_COMMON_GET_FLOW_CONTROL
, sizeof(*req
), wrb
, NULL
);
1857 status
= be_mcc_notify_wait(adapter
);
1859 struct be_cmd_resp_get_flow_control
*resp
=
1860 embedded_payload(wrb
);
1861 *tx_fc
= le16_to_cpu(resp
->tx_flow_control
);
1862 *rx_fc
= le16_to_cpu(resp
->rx_flow_control
);
1866 spin_unlock_bh(&adapter
->mcc_lock
);
1871 int be_cmd_query_fw_cfg(struct be_adapter
*adapter
, u32
*port_num
,
1872 u32
*mode
, u32
*caps
, u16
*asic_rev
)
1874 struct be_mcc_wrb
*wrb
;
1875 struct be_cmd_req_query_fw_cfg
*req
;
1878 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1881 wrb
= wrb_from_mbox(adapter
);
1882 req
= embedded_payload(wrb
);
1884 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1885 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG
, sizeof(*req
), wrb
, NULL
);
1887 status
= be_mbox_notify_wait(adapter
);
1889 struct be_cmd_resp_query_fw_cfg
*resp
= embedded_payload(wrb
);
1890 *port_num
= le32_to_cpu(resp
->phys_port
);
1891 *mode
= le32_to_cpu(resp
->function_mode
);
1892 *caps
= le32_to_cpu(resp
->function_caps
);
1893 *asic_rev
= le32_to_cpu(resp
->asic_revision
) & 0xFF;
1896 mutex_unlock(&adapter
->mbox_lock
);
1901 int be_cmd_reset_function(struct be_adapter
*adapter
)
1903 struct be_mcc_wrb
*wrb
;
1904 struct be_cmd_req_hdr
*req
;
1907 if (lancer_chip(adapter
)) {
1908 status
= lancer_wait_ready(adapter
);
1910 iowrite32(SLI_PORT_CONTROL_IP_MASK
,
1911 adapter
->db
+ SLIPORT_CONTROL_OFFSET
);
1912 status
= lancer_test_and_set_rdy_state(adapter
);
1915 dev_err(&adapter
->pdev
->dev
,
1916 "Adapter in non recoverable error\n");
1921 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1924 wrb
= wrb_from_mbox(adapter
);
1925 req
= embedded_payload(wrb
);
1927 be_wrb_cmd_hdr_prepare(req
, CMD_SUBSYSTEM_COMMON
,
1928 OPCODE_COMMON_FUNCTION_RESET
, sizeof(*req
), wrb
, NULL
);
1930 status
= be_mbox_notify_wait(adapter
);
1932 mutex_unlock(&adapter
->mbox_lock
);
1936 int be_cmd_rss_config(struct be_adapter
*adapter
, u8
*rsstable
,
1937 u32 rss_hash_opts
, u16 table_size
)
1939 struct be_mcc_wrb
*wrb
;
1940 struct be_cmd_req_rss_config
*req
;
1941 u32 myhash
[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1942 0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1943 0x3ea83c02, 0x4a110304};
1946 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1949 wrb
= wrb_from_mbox(adapter
);
1950 req
= embedded_payload(wrb
);
1952 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1953 OPCODE_ETH_RSS_CONFIG
, sizeof(*req
), wrb
, NULL
);
1955 req
->if_id
= cpu_to_le32(adapter
->if_handle
);
1956 req
->enable_rss
= cpu_to_le16(rss_hash_opts
);
1957 req
->cpu_table_size_log2
= cpu_to_le16(fls(table_size
) - 1);
1959 if (lancer_chip(adapter
) || skyhawk_chip(adapter
))
1960 req
->hdr
.version
= 1;
1962 memcpy(req
->cpu_table
, rsstable
, table_size
);
1963 memcpy(req
->hash
, myhash
, sizeof(myhash
));
1964 be_dws_cpu_to_le(req
->hash
, sizeof(req
->hash
));
1966 status
= be_mbox_notify_wait(adapter
);
1968 mutex_unlock(&adapter
->mbox_lock
);
1973 int be_cmd_set_beacon_state(struct be_adapter
*adapter
, u8 port_num
,
1974 u8 bcn
, u8 sts
, u8 state
)
1976 struct be_mcc_wrb
*wrb
;
1977 struct be_cmd_req_enable_disable_beacon
*req
;
1980 spin_lock_bh(&adapter
->mcc_lock
);
1982 wrb
= wrb_from_mccq(adapter
);
1987 req
= embedded_payload(wrb
);
1989 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1990 OPCODE_COMMON_ENABLE_DISABLE_BEACON
, sizeof(*req
), wrb
, NULL
);
1992 req
->port_num
= port_num
;
1993 req
->beacon_state
= state
;
1994 req
->beacon_duration
= bcn
;
1995 req
->status_duration
= sts
;
1997 status
= be_mcc_notify_wait(adapter
);
2000 spin_unlock_bh(&adapter
->mcc_lock
);
2005 int be_cmd_get_beacon_state(struct be_adapter
*adapter
, u8 port_num
, u32
*state
)
2007 struct be_mcc_wrb
*wrb
;
2008 struct be_cmd_req_get_beacon_state
*req
;
2011 spin_lock_bh(&adapter
->mcc_lock
);
2013 wrb
= wrb_from_mccq(adapter
);
2018 req
= embedded_payload(wrb
);
2020 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2021 OPCODE_COMMON_GET_BEACON_STATE
, sizeof(*req
), wrb
, NULL
);
2023 req
->port_num
= port_num
;
2025 status
= be_mcc_notify_wait(adapter
);
2027 struct be_cmd_resp_get_beacon_state
*resp
=
2028 embedded_payload(wrb
);
2029 *state
= resp
->beacon_state
;
2033 spin_unlock_bh(&adapter
->mcc_lock
);
2037 int lancer_cmd_write_object(struct be_adapter
*adapter
, struct be_dma_mem
*cmd
,
2038 u32 data_size
, u32 data_offset
,
2039 const char *obj_name
, u32
*data_written
,
2040 u8
*change_status
, u8
*addn_status
)
2042 struct be_mcc_wrb
*wrb
;
2043 struct lancer_cmd_req_write_object
*req
;
2044 struct lancer_cmd_resp_write_object
*resp
;
2048 spin_lock_bh(&adapter
->mcc_lock
);
2049 adapter
->flash_status
= 0;
2051 wrb
= wrb_from_mccq(adapter
);
2057 req
= embedded_payload(wrb
);
2059 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2060 OPCODE_COMMON_WRITE_OBJECT
,
2061 sizeof(struct lancer_cmd_req_write_object
), wrb
,
2064 ctxt
= &req
->context
;
2065 AMAP_SET_BITS(struct amap_lancer_write_obj_context
,
2066 write_length
, ctxt
, data_size
);
2069 AMAP_SET_BITS(struct amap_lancer_write_obj_context
,
2072 AMAP_SET_BITS(struct amap_lancer_write_obj_context
,
2075 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
2076 req
->write_offset
= cpu_to_le32(data_offset
);
2077 strcpy(req
->object_name
, obj_name
);
2078 req
->descriptor_count
= cpu_to_le32(1);
2079 req
->buf_len
= cpu_to_le32(data_size
);
2080 req
->addr_low
= cpu_to_le32((cmd
->dma
+
2081 sizeof(struct lancer_cmd_req_write_object
))
2083 req
->addr_high
= cpu_to_le32(upper_32_bits(cmd
->dma
+
2084 sizeof(struct lancer_cmd_req_write_object
)));
2086 be_mcc_notify(adapter
);
2087 spin_unlock_bh(&adapter
->mcc_lock
);
2089 if (!wait_for_completion_timeout(&adapter
->flash_compl
,
2090 msecs_to_jiffies(60000)))
2093 status
= adapter
->flash_status
;
2095 resp
= embedded_payload(wrb
);
2097 *data_written
= le32_to_cpu(resp
->actual_write_len
);
2098 *change_status
= resp
->change_status
;
2100 *addn_status
= resp
->additional_status
;
2106 spin_unlock_bh(&adapter
->mcc_lock
);
2110 int lancer_cmd_read_object(struct be_adapter
*adapter
, struct be_dma_mem
*cmd
,
2111 u32 data_size
, u32 data_offset
, const char *obj_name
,
2112 u32
*data_read
, u32
*eof
, u8
*addn_status
)
2114 struct be_mcc_wrb
*wrb
;
2115 struct lancer_cmd_req_read_object
*req
;
2116 struct lancer_cmd_resp_read_object
*resp
;
2119 spin_lock_bh(&adapter
->mcc_lock
);
2121 wrb
= wrb_from_mccq(adapter
);
2127 req
= embedded_payload(wrb
);
2129 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2130 OPCODE_COMMON_READ_OBJECT
,
2131 sizeof(struct lancer_cmd_req_read_object
), wrb
,
2134 req
->desired_read_len
= cpu_to_le32(data_size
);
2135 req
->read_offset
= cpu_to_le32(data_offset
);
2136 strcpy(req
->object_name
, obj_name
);
2137 req
->descriptor_count
= cpu_to_le32(1);
2138 req
->buf_len
= cpu_to_le32(data_size
);
2139 req
->addr_low
= cpu_to_le32((cmd
->dma
& 0xFFFFFFFF));
2140 req
->addr_high
= cpu_to_le32(upper_32_bits(cmd
->dma
));
2142 status
= be_mcc_notify_wait(adapter
);
2144 resp
= embedded_payload(wrb
);
2146 *data_read
= le32_to_cpu(resp
->actual_read_len
);
2147 *eof
= le32_to_cpu(resp
->eof
);
2149 *addn_status
= resp
->additional_status
;
2153 spin_unlock_bh(&adapter
->mcc_lock
);
2157 int be_cmd_write_flashrom(struct be_adapter
*adapter
, struct be_dma_mem
*cmd
,
2158 u32 flash_type
, u32 flash_opcode
, u32 buf_size
)
2160 struct be_mcc_wrb
*wrb
;
2161 struct be_cmd_write_flashrom
*req
;
2164 spin_lock_bh(&adapter
->mcc_lock
);
2165 adapter
->flash_status
= 0;
2167 wrb
= wrb_from_mccq(adapter
);
2174 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2175 OPCODE_COMMON_WRITE_FLASHROM
, cmd
->size
, wrb
, cmd
);
2177 req
->params
.op_type
= cpu_to_le32(flash_type
);
2178 req
->params
.op_code
= cpu_to_le32(flash_opcode
);
2179 req
->params
.data_buf_size
= cpu_to_le32(buf_size
);
2181 be_mcc_notify(adapter
);
2182 spin_unlock_bh(&adapter
->mcc_lock
);
2184 if (!wait_for_completion_timeout(&adapter
->flash_compl
,
2185 msecs_to_jiffies(40000)))
2188 status
= adapter
->flash_status
;
2193 spin_unlock_bh(&adapter
->mcc_lock
);
2197 int be_cmd_get_flash_crc(struct be_adapter
*adapter
, u8
*flashed_crc
,
2200 struct be_mcc_wrb
*wrb
;
2201 struct be_cmd_read_flash_crc
*req
;
2204 spin_lock_bh(&adapter
->mcc_lock
);
2206 wrb
= wrb_from_mccq(adapter
);
2211 req
= embedded_payload(wrb
);
2213 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2214 OPCODE_COMMON_READ_FLASHROM
, sizeof(*req
),
2217 req
->params
.op_type
= cpu_to_le32(OPTYPE_REDBOOT
);
2218 req
->params
.op_code
= cpu_to_le32(FLASHROM_OPER_REPORT
);
2219 req
->params
.offset
= cpu_to_le32(offset
);
2220 req
->params
.data_buf_size
= cpu_to_le32(0x4);
2222 status
= be_mcc_notify_wait(adapter
);
2224 memcpy(flashed_crc
, req
->crc
, 4);
2227 spin_unlock_bh(&adapter
->mcc_lock
);
2231 int be_cmd_enable_magic_wol(struct be_adapter
*adapter
, u8
*mac
,
2232 struct be_dma_mem
*nonemb_cmd
)
2234 struct be_mcc_wrb
*wrb
;
2235 struct be_cmd_req_acpi_wol_magic_config
*req
;
2238 spin_lock_bh(&adapter
->mcc_lock
);
2240 wrb
= wrb_from_mccq(adapter
);
2245 req
= nonemb_cmd
->va
;
2247 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
2248 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
, sizeof(*req
), wrb
,
2250 memcpy(req
->magic_mac
, mac
, ETH_ALEN
);
2252 status
= be_mcc_notify_wait(adapter
);
2255 spin_unlock_bh(&adapter
->mcc_lock
);
2259 int be_cmd_set_loopback(struct be_adapter
*adapter
, u8 port_num
,
2260 u8 loopback_type
, u8 enable
)
2262 struct be_mcc_wrb
*wrb
;
2263 struct be_cmd_req_set_lmode
*req
;
2266 spin_lock_bh(&adapter
->mcc_lock
);
2268 wrb
= wrb_from_mccq(adapter
);
2274 req
= embedded_payload(wrb
);
2276 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_LOWLEVEL
,
2277 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE
, sizeof(*req
), wrb
,
2280 req
->src_port
= port_num
;
2281 req
->dest_port
= port_num
;
2282 req
->loopback_type
= loopback_type
;
2283 req
->loopback_state
= enable
;
2285 status
= be_mcc_notify_wait(adapter
);
2287 spin_unlock_bh(&adapter
->mcc_lock
);
2291 int be_cmd_loopback_test(struct be_adapter
*adapter
, u32 port_num
,
2292 u32 loopback_type
, u32 pkt_size
, u32 num_pkts
, u64 pattern
)
2294 struct be_mcc_wrb
*wrb
;
2295 struct be_cmd_req_loopback_test
*req
;
2298 spin_lock_bh(&adapter
->mcc_lock
);
2300 wrb
= wrb_from_mccq(adapter
);
2306 req
= embedded_payload(wrb
);
2308 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_LOWLEVEL
,
2309 OPCODE_LOWLEVEL_LOOPBACK_TEST
, sizeof(*req
), wrb
, NULL
);
2310 req
->hdr
.timeout
= cpu_to_le32(4);
2312 req
->pattern
= cpu_to_le64(pattern
);
2313 req
->src_port
= cpu_to_le32(port_num
);
2314 req
->dest_port
= cpu_to_le32(port_num
);
2315 req
->pkt_size
= cpu_to_le32(pkt_size
);
2316 req
->num_pkts
= cpu_to_le32(num_pkts
);
2317 req
->loopback_type
= cpu_to_le32(loopback_type
);
2319 status
= be_mcc_notify_wait(adapter
);
2321 struct be_cmd_resp_loopback_test
*resp
= embedded_payload(wrb
);
2322 status
= le32_to_cpu(resp
->status
);
2326 spin_unlock_bh(&adapter
->mcc_lock
);
2330 int be_cmd_ddr_dma_test(struct be_adapter
*adapter
, u64 pattern
,
2331 u32 byte_cnt
, struct be_dma_mem
*cmd
)
2333 struct be_mcc_wrb
*wrb
;
2334 struct be_cmd_req_ddrdma_test
*req
;
2338 spin_lock_bh(&adapter
->mcc_lock
);
2340 wrb
= wrb_from_mccq(adapter
);
2346 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_LOWLEVEL
,
2347 OPCODE_LOWLEVEL_HOST_DDR_DMA
, cmd
->size
, wrb
, cmd
);
2349 req
->pattern
= cpu_to_le64(pattern
);
2350 req
->byte_count
= cpu_to_le32(byte_cnt
);
2351 for (i
= 0; i
< byte_cnt
; i
++) {
2352 req
->snd_buff
[i
] = (u8
)(pattern
>> (j
*8));
2358 status
= be_mcc_notify_wait(adapter
);
2361 struct be_cmd_resp_ddrdma_test
*resp
;
2363 if ((memcmp(resp
->rcv_buff
, req
->snd_buff
, byte_cnt
) != 0) ||
2370 spin_unlock_bh(&adapter
->mcc_lock
);
2374 int be_cmd_get_seeprom_data(struct be_adapter
*adapter
,
2375 struct be_dma_mem
*nonemb_cmd
)
2377 struct be_mcc_wrb
*wrb
;
2378 struct be_cmd_req_seeprom_read
*req
;
2381 spin_lock_bh(&adapter
->mcc_lock
);
2383 wrb
= wrb_from_mccq(adapter
);
2388 req
= nonemb_cmd
->va
;
2390 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2391 OPCODE_COMMON_SEEPROM_READ
, sizeof(*req
), wrb
,
2394 status
= be_mcc_notify_wait(adapter
);
2397 spin_unlock_bh(&adapter
->mcc_lock
);
2401 int be_cmd_get_phy_info(struct be_adapter
*adapter
)
2403 struct be_mcc_wrb
*wrb
;
2404 struct be_cmd_req_get_phy_info
*req
;
2405 struct be_dma_mem cmd
;
2408 if (!be_cmd_allowed(adapter
, OPCODE_COMMON_GET_PHY_DETAILS
,
2409 CMD_SUBSYSTEM_COMMON
))
2412 spin_lock_bh(&adapter
->mcc_lock
);
2414 wrb
= wrb_from_mccq(adapter
);
2419 cmd
.size
= sizeof(struct be_cmd_req_get_phy_info
);
2420 cmd
.va
= pci_alloc_consistent(adapter
->pdev
, cmd
.size
,
2423 dev_err(&adapter
->pdev
->dev
, "Memory alloc failure\n");
2430 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2431 OPCODE_COMMON_GET_PHY_DETAILS
, sizeof(*req
),
2434 status
= be_mcc_notify_wait(adapter
);
2436 struct be_phy_info
*resp_phy_info
=
2437 cmd
.va
+ sizeof(struct be_cmd_req_hdr
);
2438 adapter
->phy
.phy_type
= le16_to_cpu(resp_phy_info
->phy_type
);
2439 adapter
->phy
.interface_type
=
2440 le16_to_cpu(resp_phy_info
->interface_type
);
2441 adapter
->phy
.auto_speeds_supported
=
2442 le16_to_cpu(resp_phy_info
->auto_speeds_supported
);
2443 adapter
->phy
.fixed_speeds_supported
=
2444 le16_to_cpu(resp_phy_info
->fixed_speeds_supported
);
2445 adapter
->phy
.misc_params
=
2446 le32_to_cpu(resp_phy_info
->misc_params
);
2448 pci_free_consistent(adapter
->pdev
, cmd
.size
,
2451 spin_unlock_bh(&adapter
->mcc_lock
);
2455 int be_cmd_set_qos(struct be_adapter
*adapter
, u32 bps
, u32 domain
)
2457 struct be_mcc_wrb
*wrb
;
2458 struct be_cmd_req_set_qos
*req
;
2461 spin_lock_bh(&adapter
->mcc_lock
);
2463 wrb
= wrb_from_mccq(adapter
);
2469 req
= embedded_payload(wrb
);
2471 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2472 OPCODE_COMMON_SET_QOS
, sizeof(*req
), wrb
, NULL
);
2474 req
->hdr
.domain
= domain
;
2475 req
->valid_bits
= cpu_to_le32(BE_QOS_BITS_NIC
);
2476 req
->max_bps_nic
= cpu_to_le32(bps
);
2478 status
= be_mcc_notify_wait(adapter
);
2481 spin_unlock_bh(&adapter
->mcc_lock
);
2485 int be_cmd_get_cntl_attributes(struct be_adapter
*adapter
)
2487 struct be_mcc_wrb
*wrb
;
2488 struct be_cmd_req_cntl_attribs
*req
;
2489 struct be_cmd_resp_cntl_attribs
*resp
;
2491 int payload_len
= max(sizeof(*req
), sizeof(*resp
));
2492 struct mgmt_controller_attrib
*attribs
;
2493 struct be_dma_mem attribs_cmd
;
2495 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
2498 memset(&attribs_cmd
, 0, sizeof(struct be_dma_mem
));
2499 attribs_cmd
.size
= sizeof(struct be_cmd_resp_cntl_attribs
);
2500 attribs_cmd
.va
= pci_alloc_consistent(adapter
->pdev
, attribs_cmd
.size
,
2502 if (!attribs_cmd
.va
) {
2503 dev_err(&adapter
->pdev
->dev
,
2504 "Memory allocation failure\n");
2509 wrb
= wrb_from_mbox(adapter
);
2514 req
= attribs_cmd
.va
;
2516 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2517 OPCODE_COMMON_GET_CNTL_ATTRIBUTES
, payload_len
, wrb
,
2520 status
= be_mbox_notify_wait(adapter
);
2522 attribs
= attribs_cmd
.va
+ sizeof(struct be_cmd_resp_hdr
);
2523 adapter
->hba_port_num
= attribs
->hba_attribs
.phy_port
;
2527 mutex_unlock(&adapter
->mbox_lock
);
2529 pci_free_consistent(adapter
->pdev
, attribs_cmd
.size
,
2530 attribs_cmd
.va
, attribs_cmd
.dma
);
2535 int be_cmd_req_native_mode(struct be_adapter
*adapter
)
2537 struct be_mcc_wrb
*wrb
;
2538 struct be_cmd_req_set_func_cap
*req
;
2541 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
2544 wrb
= wrb_from_mbox(adapter
);
2550 req
= embedded_payload(wrb
);
2552 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2553 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP
, sizeof(*req
), wrb
, NULL
);
2555 req
->valid_cap_flags
= cpu_to_le32(CAPABILITY_SW_TIMESTAMPS
|
2556 CAPABILITY_BE3_NATIVE_ERX_API
);
2557 req
->cap_flags
= cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API
);
2559 status
= be_mbox_notify_wait(adapter
);
2561 struct be_cmd_resp_set_func_cap
*resp
= embedded_payload(wrb
);
2562 adapter
->be3_native
= le32_to_cpu(resp
->cap_flags
) &
2563 CAPABILITY_BE3_NATIVE_ERX_API
;
2564 if (!adapter
->be3_native
)
2565 dev_warn(&adapter
->pdev
->dev
,
2566 "adapter not in advanced mode\n");
2569 mutex_unlock(&adapter
->mbox_lock
);
2573 /* Get privilege(s) for a function */
2574 int be_cmd_get_fn_privileges(struct be_adapter
*adapter
, u32
*privilege
,
2577 struct be_mcc_wrb
*wrb
;
2578 struct be_cmd_req_get_fn_privileges
*req
;
2581 spin_lock_bh(&adapter
->mcc_lock
);
2583 wrb
= wrb_from_mccq(adapter
);
2589 req
= embedded_payload(wrb
);
2591 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2592 OPCODE_COMMON_GET_FN_PRIVILEGES
, sizeof(*req
),
2595 req
->hdr
.domain
= domain
;
2597 status
= be_mcc_notify_wait(adapter
);
2599 struct be_cmd_resp_get_fn_privileges
*resp
=
2600 embedded_payload(wrb
);
2601 *privilege
= le32_to_cpu(resp
->privilege_mask
);
2605 spin_unlock_bh(&adapter
->mcc_lock
);
2609 /* Uses synchronous MCCQ */
2610 int be_cmd_get_mac_from_list(struct be_adapter
*adapter
, u8
*mac
,
2611 bool *pmac_id_active
, u32
*pmac_id
, u8 domain
)
2613 struct be_mcc_wrb
*wrb
;
2614 struct be_cmd_req_get_mac_list
*req
;
2617 struct be_dma_mem get_mac_list_cmd
;
2620 memset(&get_mac_list_cmd
, 0, sizeof(struct be_dma_mem
));
2621 get_mac_list_cmd
.size
= sizeof(struct be_cmd_resp_get_mac_list
);
2622 get_mac_list_cmd
.va
= pci_alloc_consistent(adapter
->pdev
,
2623 get_mac_list_cmd
.size
,
2624 &get_mac_list_cmd
.dma
);
2626 if (!get_mac_list_cmd
.va
) {
2627 dev_err(&adapter
->pdev
->dev
,
2628 "Memory allocation failure during GET_MAC_LIST\n");
2632 spin_lock_bh(&adapter
->mcc_lock
);
2634 wrb
= wrb_from_mccq(adapter
);
2640 req
= get_mac_list_cmd
.va
;
2642 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2643 OPCODE_COMMON_GET_MAC_LIST
, sizeof(*req
),
2644 wrb
, &get_mac_list_cmd
);
2646 req
->hdr
.domain
= domain
;
2647 req
->mac_type
= MAC_ADDRESS_TYPE_NETWORK
;
2648 req
->perm_override
= 1;
2650 status
= be_mcc_notify_wait(adapter
);
2652 struct be_cmd_resp_get_mac_list
*resp
=
2653 get_mac_list_cmd
.va
;
2654 mac_count
= resp
->true_mac_count
+ resp
->pseudo_mac_count
;
2655 /* Mac list returned could contain one or more active mac_ids
2656 * or one or more true or pseudo permanant mac addresses.
2657 * If an active mac_id is present, return first active mac_id
2660 for (i
= 0; i
< mac_count
; i
++) {
2661 struct get_list_macaddr
*mac_entry
;
2665 mac_entry
= &resp
->macaddr_list
[i
];
2666 mac_addr_size
= le16_to_cpu(mac_entry
->mac_addr_size
);
2667 /* mac_id is a 32 bit value and mac_addr size
2670 if (mac_addr_size
== sizeof(u32
)) {
2671 *pmac_id_active
= true;
2672 mac_id
= mac_entry
->mac_addr_id
.s_mac_id
.mac_id
;
2673 *pmac_id
= le32_to_cpu(mac_id
);
2677 /* If no active mac_id found, return first mac addr */
2678 *pmac_id_active
= false;
2679 memcpy(mac
, resp
->macaddr_list
[0].mac_addr_id
.macaddr
,
2684 spin_unlock_bh(&adapter
->mcc_lock
);
2685 pci_free_consistent(adapter
->pdev
, get_mac_list_cmd
.size
,
2686 get_mac_list_cmd
.va
, get_mac_list_cmd
.dma
);
2690 /* Uses synchronous MCCQ */
2691 int be_cmd_set_mac_list(struct be_adapter
*adapter
, u8
*mac_array
,
2692 u8 mac_count
, u32 domain
)
2694 struct be_mcc_wrb
*wrb
;
2695 struct be_cmd_req_set_mac_list
*req
;
2697 struct be_dma_mem cmd
;
2699 memset(&cmd
, 0, sizeof(struct be_dma_mem
));
2700 cmd
.size
= sizeof(struct be_cmd_req_set_mac_list
);
2701 cmd
.va
= dma_alloc_coherent(&adapter
->pdev
->dev
, cmd
.size
,
2702 &cmd
.dma
, GFP_KERNEL
);
2706 spin_lock_bh(&adapter
->mcc_lock
);
2708 wrb
= wrb_from_mccq(adapter
);
2715 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2716 OPCODE_COMMON_SET_MAC_LIST
, sizeof(*req
),
2719 req
->hdr
.domain
= domain
;
2720 req
->mac_count
= mac_count
;
2722 memcpy(req
->mac
, mac_array
, ETH_ALEN
*mac_count
);
2724 status
= be_mcc_notify_wait(adapter
);
2727 dma_free_coherent(&adapter
->pdev
->dev
, cmd
.size
,
2729 spin_unlock_bh(&adapter
->mcc_lock
);
2733 int be_cmd_set_hsw_config(struct be_adapter
*adapter
, u16 pvid
,
2734 u32 domain
, u16 intf_id
)
2736 struct be_mcc_wrb
*wrb
;
2737 struct be_cmd_req_set_hsw_config
*req
;
2741 spin_lock_bh(&adapter
->mcc_lock
);
2743 wrb
= wrb_from_mccq(adapter
);
2749 req
= embedded_payload(wrb
);
2750 ctxt
= &req
->context
;
2752 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2753 OPCODE_COMMON_SET_HSW_CONFIG
, sizeof(*req
), wrb
, NULL
);
2755 req
->hdr
.domain
= domain
;
2756 AMAP_SET_BITS(struct amap_set_hsw_context
, interface_id
, ctxt
, intf_id
);
2758 AMAP_SET_BITS(struct amap_set_hsw_context
, pvid_valid
, ctxt
, 1);
2759 AMAP_SET_BITS(struct amap_set_hsw_context
, pvid
, ctxt
, pvid
);
2762 be_dws_cpu_to_le(req
->context
, sizeof(req
->context
));
2763 status
= be_mcc_notify_wait(adapter
);
2766 spin_unlock_bh(&adapter
->mcc_lock
);
2770 /* Get Hyper switch config */
2771 int be_cmd_get_hsw_config(struct be_adapter
*adapter
, u16
*pvid
,
2772 u32 domain
, u16 intf_id
)
2774 struct be_mcc_wrb
*wrb
;
2775 struct be_cmd_req_get_hsw_config
*req
;
2780 spin_lock_bh(&adapter
->mcc_lock
);
2782 wrb
= wrb_from_mccq(adapter
);
2788 req
= embedded_payload(wrb
);
2789 ctxt
= &req
->context
;
2791 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2792 OPCODE_COMMON_GET_HSW_CONFIG
, sizeof(*req
), wrb
, NULL
);
2794 req
->hdr
.domain
= domain
;
2795 AMAP_SET_BITS(struct amap_get_hsw_req_context
, interface_id
, ctxt
,
2797 AMAP_SET_BITS(struct amap_get_hsw_req_context
, pvid_valid
, ctxt
, 1);
2798 be_dws_cpu_to_le(req
->context
, sizeof(req
->context
));
2800 status
= be_mcc_notify_wait(adapter
);
2802 struct be_cmd_resp_get_hsw_config
*resp
=
2803 embedded_payload(wrb
);
2804 be_dws_le_to_cpu(&resp
->context
,
2805 sizeof(resp
->context
));
2806 vid
= AMAP_GET_BITS(struct amap_get_hsw_resp_context
,
2807 pvid
, &resp
->context
);
2808 *pvid
= le16_to_cpu(vid
);
2812 spin_unlock_bh(&adapter
->mcc_lock
);
2816 int be_cmd_get_acpi_wol_cap(struct be_adapter
*adapter
)
2818 struct be_mcc_wrb
*wrb
;
2819 struct be_cmd_req_acpi_wol_magic_config_v1
*req
;
2821 int payload_len
= sizeof(*req
);
2822 struct be_dma_mem cmd
;
2824 if (!be_cmd_allowed(adapter
, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
,
2828 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
2831 memset(&cmd
, 0, sizeof(struct be_dma_mem
));
2832 cmd
.size
= sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1
);
2833 cmd
.va
= pci_alloc_consistent(adapter
->pdev
, cmd
.size
,
2836 dev_err(&adapter
->pdev
->dev
,
2837 "Memory allocation failure\n");
2842 wrb
= wrb_from_mbox(adapter
);
2850 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
2851 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
,
2852 payload_len
, wrb
, &cmd
);
2854 req
->hdr
.version
= 1;
2855 req
->query_options
= BE_GET_WOL_CAP
;
2857 status
= be_mbox_notify_wait(adapter
);
2859 struct be_cmd_resp_acpi_wol_magic_config_v1
*resp
;
2860 resp
= (struct be_cmd_resp_acpi_wol_magic_config_v1
*) cmd
.va
;
2862 /* the command could succeed misleadingly on old f/w
2863 * which is not aware of the V1 version. fake an error. */
2864 if (resp
->hdr
.response_length
< payload_len
) {
2868 adapter
->wol_cap
= resp
->wol_settings
;
2871 mutex_unlock(&adapter
->mbox_lock
);
2873 pci_free_consistent(adapter
->pdev
, cmd
.size
, cmd
.va
, cmd
.dma
);
2877 int be_cmd_get_ext_fat_capabilites(struct be_adapter
*adapter
,
2878 struct be_dma_mem
*cmd
)
2880 struct be_mcc_wrb
*wrb
;
2881 struct be_cmd_req_get_ext_fat_caps
*req
;
2884 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
2887 wrb
= wrb_from_mbox(adapter
);
2894 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2895 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES
,
2896 cmd
->size
, wrb
, cmd
);
2897 req
->parameter_type
= cpu_to_le32(1);
2899 status
= be_mbox_notify_wait(adapter
);
2901 mutex_unlock(&adapter
->mbox_lock
);
2905 int be_cmd_set_ext_fat_capabilites(struct be_adapter
*adapter
,
2906 struct be_dma_mem
*cmd
,
2907 struct be_fat_conf_params
*configs
)
2909 struct be_mcc_wrb
*wrb
;
2910 struct be_cmd_req_set_ext_fat_caps
*req
;
2913 spin_lock_bh(&adapter
->mcc_lock
);
2915 wrb
= wrb_from_mccq(adapter
);
2922 memcpy(&req
->set_params
, configs
, sizeof(struct be_fat_conf_params
));
2923 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2924 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES
,
2925 cmd
->size
, wrb
, cmd
);
2927 status
= be_mcc_notify_wait(adapter
);
2929 spin_unlock_bh(&adapter
->mcc_lock
);
2933 int be_cmd_query_port_name(struct be_adapter
*adapter
, u8
*port_name
)
2935 struct be_mcc_wrb
*wrb
;
2936 struct be_cmd_req_get_port_name
*req
;
2939 if (!lancer_chip(adapter
)) {
2940 *port_name
= adapter
->hba_port_num
+ '0';
2944 spin_lock_bh(&adapter
->mcc_lock
);
2946 wrb
= wrb_from_mccq(adapter
);
2952 req
= embedded_payload(wrb
);
2954 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2955 OPCODE_COMMON_GET_PORT_NAME
, sizeof(*req
), wrb
,
2957 req
->hdr
.version
= 1;
2959 status
= be_mcc_notify_wait(adapter
);
2961 struct be_cmd_resp_get_port_name
*resp
= embedded_payload(wrb
);
2962 *port_name
= resp
->port_name
[adapter
->hba_port_num
];
2964 *port_name
= adapter
->hba_port_num
+ '0';
2967 spin_unlock_bh(&adapter
->mcc_lock
);
2971 static struct be_nic_resource_desc
*be_get_nic_desc(u8
*buf
, u32 desc_count
,
2974 struct be_nic_resource_desc
*desc
= (struct be_nic_resource_desc
*)buf
;
2977 for (i
= 0; i
< desc_count
; i
++) {
2978 desc
->desc_len
= desc
->desc_len
? : RESOURCE_DESC_SIZE
;
2979 if (((void *)desc
+ desc
->desc_len
) >
2980 (void *)(buf
+ max_buf_size
)) {
2985 if (desc
->desc_type
== NIC_RESOURCE_DESC_TYPE_V0
||
2986 desc
->desc_type
== NIC_RESOURCE_DESC_TYPE_V1
)
2989 desc
= (void *)desc
+ desc
->desc_len
;
2992 if (!desc
|| i
== MAX_RESOURCE_DESC
)
2999 int be_cmd_get_func_config(struct be_adapter
*adapter
)
3001 struct be_mcc_wrb
*wrb
;
3002 struct be_cmd_req_get_func_config
*req
;
3004 struct be_dma_mem cmd
;
3006 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
3009 memset(&cmd
, 0, sizeof(struct be_dma_mem
));
3010 cmd
.size
= sizeof(struct be_cmd_resp_get_func_config
);
3011 cmd
.va
= pci_alloc_consistent(adapter
->pdev
, cmd
.size
,
3014 dev_err(&adapter
->pdev
->dev
, "Memory alloc failure\n");
3019 wrb
= wrb_from_mbox(adapter
);
3027 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3028 OPCODE_COMMON_GET_FUNC_CONFIG
,
3029 cmd
.size
, wrb
, &cmd
);
3031 if (skyhawk_chip(adapter
))
3032 req
->hdr
.version
= 1;
3034 status
= be_mbox_notify_wait(adapter
);
3036 struct be_cmd_resp_get_func_config
*resp
= cmd
.va
;
3037 u32 desc_count
= le32_to_cpu(resp
->desc_count
);
3038 struct be_nic_resource_desc
*desc
;
3040 desc
= be_get_nic_desc(resp
->func_param
, desc_count
,
3041 sizeof(resp
->func_param
));
3047 adapter
->pf_number
= desc
->pf_num
;
3048 adapter
->max_pmac_cnt
= le16_to_cpu(desc
->unicast_mac_count
);
3049 adapter
->max_vlans
= le16_to_cpu(desc
->vlan_count
);
3050 adapter
->max_mcast_mac
= le16_to_cpu(desc
->mcast_mac_count
);
3051 adapter
->max_tx_queues
= le16_to_cpu(desc
->txq_count
);
3052 adapter
->max_rss_queues
= le16_to_cpu(desc
->rssq_count
);
3053 adapter
->max_rx_queues
= le16_to_cpu(desc
->rq_count
);
3055 adapter
->max_event_queues
= le16_to_cpu(desc
->eq_count
);
3056 adapter
->if_cap_flags
= le32_to_cpu(desc
->cap_flags
);
3059 mutex_unlock(&adapter
->mbox_lock
);
3061 pci_free_consistent(adapter
->pdev
, cmd
.size
, cmd
.va
, cmd
.dma
);
3066 int be_cmd_get_profile_config_mbox(struct be_adapter
*adapter
,
3067 u8 domain
, struct be_dma_mem
*cmd
)
3069 struct be_mcc_wrb
*wrb
;
3070 struct be_cmd_req_get_profile_config
*req
;
3073 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
3075 wrb
= wrb_from_mbox(adapter
);
3078 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3079 OPCODE_COMMON_GET_PROFILE_CONFIG
,
3080 cmd
->size
, wrb
, cmd
);
3082 req
->type
= ACTIVE_PROFILE_TYPE
;
3083 req
->hdr
.domain
= domain
;
3084 if (!lancer_chip(adapter
))
3085 req
->hdr
.version
= 1;
3087 status
= be_mbox_notify_wait(adapter
);
3089 mutex_unlock(&adapter
->mbox_lock
);
3094 int be_cmd_get_profile_config_mccq(struct be_adapter
*adapter
,
3095 u8 domain
, struct be_dma_mem
*cmd
)
3097 struct be_mcc_wrb
*wrb
;
3098 struct be_cmd_req_get_profile_config
*req
;
3101 spin_lock_bh(&adapter
->mcc_lock
);
3103 wrb
= wrb_from_mccq(adapter
);
3110 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3111 OPCODE_COMMON_GET_PROFILE_CONFIG
,
3112 cmd
->size
, wrb
, cmd
);
3114 req
->type
= ACTIVE_PROFILE_TYPE
;
3115 req
->hdr
.domain
= domain
;
3116 if (!lancer_chip(adapter
))
3117 req
->hdr
.version
= 1;
3119 status
= be_mcc_notify_wait(adapter
);
3122 spin_unlock_bh(&adapter
->mcc_lock
);
3126 /* Uses sync mcc, if MCCQ is already created otherwise mbox */
3127 int be_cmd_get_profile_config(struct be_adapter
*adapter
, u32
*cap_flags
,
3128 u16
*txq_count
, u8 domain
)
3130 struct be_queue_info
*mccq
= &adapter
->mcc_obj
.q
;
3131 struct be_dma_mem cmd
;
3134 memset(&cmd
, 0, sizeof(struct be_dma_mem
));
3135 if (!lancer_chip(adapter
))
3136 cmd
.size
= sizeof(struct be_cmd_resp_get_profile_config_v1
);
3138 cmd
.size
= sizeof(struct be_cmd_resp_get_profile_config
);
3139 cmd
.va
= pci_alloc_consistent(adapter
->pdev
, cmd
.size
,
3142 dev_err(&adapter
->pdev
->dev
, "Memory alloc failure\n");
3147 status
= be_cmd_get_profile_config_mbox(adapter
, domain
, &cmd
);
3149 status
= be_cmd_get_profile_config_mccq(adapter
, domain
, &cmd
);
3151 struct be_cmd_resp_get_profile_config
*resp
= cmd
.va
;
3152 u32 desc_count
= le32_to_cpu(resp
->desc_count
);
3153 struct be_nic_resource_desc
*desc
;
3155 desc
= be_get_nic_desc(resp
->func_param
, desc_count
,
3156 sizeof(resp
->func_param
));
3163 *cap_flags
= le32_to_cpu(desc
->cap_flags
);
3165 *txq_count
= le32_to_cpu(desc
->txq_count
);
3169 pci_free_consistent(adapter
->pdev
, cmd
.size
,
3175 int be_cmd_set_profile_config(struct be_adapter
*adapter
, u32 bps
,
3178 struct be_mcc_wrb
*wrb
;
3179 struct be_cmd_req_set_profile_config
*req
;
3182 spin_lock_bh(&adapter
->mcc_lock
);
3184 wrb
= wrb_from_mccq(adapter
);
3190 req
= embedded_payload(wrb
);
3192 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3193 OPCODE_COMMON_SET_PROFILE_CONFIG
, sizeof(*req
),
3196 req
->hdr
.domain
= domain
;
3197 req
->desc_count
= cpu_to_le32(1);
3199 req
->nic_desc
.desc_type
= NIC_RESOURCE_DESC_TYPE_V0
;
3200 req
->nic_desc
.desc_len
= RESOURCE_DESC_SIZE
;
3201 req
->nic_desc
.flags
= (1 << QUN
) | (1 << IMM
) | (1 << NOSV
);
3202 req
->nic_desc
.pf_num
= adapter
->pf_number
;
3203 req
->nic_desc
.vf_num
= domain
;
3205 /* Mark fields invalid */
3206 req
->nic_desc
.unicast_mac_count
= 0xFFFF;
3207 req
->nic_desc
.mcc_count
= 0xFFFF;
3208 req
->nic_desc
.vlan_count
= 0xFFFF;
3209 req
->nic_desc
.mcast_mac_count
= 0xFFFF;
3210 req
->nic_desc
.txq_count
= 0xFFFF;
3211 req
->nic_desc
.rq_count
= 0xFFFF;
3212 req
->nic_desc
.rssq_count
= 0xFFFF;
3213 req
->nic_desc
.lro_count
= 0xFFFF;
3214 req
->nic_desc
.cq_count
= 0xFFFF;
3215 req
->nic_desc
.toe_conn_count
= 0xFFFF;
3216 req
->nic_desc
.eq_count
= 0xFFFF;
3217 req
->nic_desc
.link_param
= 0xFF;
3218 req
->nic_desc
.bw_min
= 0xFFFFFFFF;
3219 req
->nic_desc
.acpi_params
= 0xFF;
3220 req
->nic_desc
.wol_param
= 0x0F;
3223 req
->nic_desc
.bw_min
= cpu_to_le32(bps
);
3224 req
->nic_desc
.bw_max
= cpu_to_le32(bps
);
3225 status
= be_mcc_notify_wait(adapter
);
3227 spin_unlock_bh(&adapter
->mcc_lock
);
3231 int be_cmd_get_if_id(struct be_adapter
*adapter
, struct be_vf_cfg
*vf_cfg
,
3234 struct be_mcc_wrb
*wrb
;
3235 struct be_cmd_req_get_iface_list
*req
;
3236 struct be_cmd_resp_get_iface_list
*resp
;
3239 spin_lock_bh(&adapter
->mcc_lock
);
3241 wrb
= wrb_from_mccq(adapter
);
3246 req
= embedded_payload(wrb
);
3248 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3249 OPCODE_COMMON_GET_IFACE_LIST
, sizeof(*resp
),
3251 req
->hdr
.domain
= vf_num
+ 1;
3253 status
= be_mcc_notify_wait(adapter
);
3255 resp
= (struct be_cmd_resp_get_iface_list
*)req
;
3256 vf_cfg
->if_handle
= le32_to_cpu(resp
->if_desc
.if_id
);
3260 spin_unlock_bh(&adapter
->mcc_lock
);
3265 int be_cmd_enable_vf(struct be_adapter
*adapter
, u8 domain
)
3267 struct be_mcc_wrb
*wrb
;
3268 struct be_cmd_enable_disable_vf
*req
;
3271 if (!lancer_chip(adapter
))
3274 spin_lock_bh(&adapter
->mcc_lock
);
3276 wrb
= wrb_from_mccq(adapter
);
3282 req
= embedded_payload(wrb
);
3284 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3285 OPCODE_COMMON_ENABLE_DISABLE_VF
, sizeof(*req
),
3288 req
->hdr
.domain
= domain
;
3290 status
= be_mcc_notify_wait(adapter
);
3292 spin_unlock_bh(&adapter
->mcc_lock
);
3296 int be_cmd_intr_set(struct be_adapter
*adapter
, bool intr_enable
)
3298 struct be_mcc_wrb
*wrb
;
3299 struct be_cmd_req_intr_set
*req
;
3302 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
3305 wrb
= wrb_from_mbox(adapter
);
3307 req
= embedded_payload(wrb
);
3309 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3310 OPCODE_COMMON_SET_INTERRUPT_ENABLE
, sizeof(*req
),
3313 req
->intr_enabled
= intr_enable
;
3315 status
= be_mbox_notify_wait(adapter
);
3317 mutex_unlock(&adapter
->mbox_lock
);
3321 int be_roce_mcc_cmd(void *netdev_handle
, void *wrb_payload
,
3322 int wrb_payload_size
, u16
*cmd_status
, u16
*ext_status
)
3324 struct be_adapter
*adapter
= netdev_priv(netdev_handle
);
3325 struct be_mcc_wrb
*wrb
;
3326 struct be_cmd_req_hdr
*hdr
= (struct be_cmd_req_hdr
*) wrb_payload
;
3327 struct be_cmd_req_hdr
*req
;
3328 struct be_cmd_resp_hdr
*resp
;
3331 spin_lock_bh(&adapter
->mcc_lock
);
3333 wrb
= wrb_from_mccq(adapter
);
3338 req
= embedded_payload(wrb
);
3339 resp
= embedded_payload(wrb
);
3341 be_wrb_cmd_hdr_prepare(req
, hdr
->subsystem
,
3342 hdr
->opcode
, wrb_payload_size
, wrb
, NULL
);
3343 memcpy(req
, wrb_payload
, wrb_payload_size
);
3344 be_dws_cpu_to_le(req
, wrb_payload_size
);
3346 status
= be_mcc_notify_wait(adapter
);
3348 *cmd_status
= (status
& 0xffff);
3351 memcpy(wrb_payload
, resp
, sizeof(*resp
) + resp
->response_length
);
3352 be_dws_le_to_cpu(wrb_payload
, sizeof(*resp
) + resp
->response_length
);
3354 spin_unlock_bh(&adapter
->mcc_lock
);
3357 EXPORT_SYMBOL(be_roce_mcc_cmd
);