2 * Copyright (C) 2005 - 2013 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
32 #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
36 u32 embedded
; /* dword 0 */
37 u32 payload_length
; /* dword 1 */
38 u32 tag0
; /* dword 2 */
39 u32 tag1
; /* dword 3 */
40 u32 rsvd
; /* dword 4 */
42 u8 embedded_payload
[236]; /* used by embedded cmds */
43 struct be_sge sgl
[19]; /* used by non-embedded cmds */
47 #define CQE_FLAGS_VALID_MASK (1 << 31)
48 #define CQE_FLAGS_ASYNC_MASK (1 << 30)
49 #define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50 #define CQE_FLAGS_CONSUMED_MASK (1 << 27)
52 /* Completion Status */
54 MCC_STATUS_SUCCESS
= 0,
55 MCC_STATUS_FAILED
= 1,
56 MCC_STATUS_ILLEGAL_REQUEST
= 2,
57 MCC_STATUS_ILLEGAL_FIELD
= 3,
58 MCC_STATUS_INSUFFICIENT_BUFFER
= 4,
59 MCC_STATUS_UNAUTHORIZED_REQUEST
= 5,
60 MCC_STATUS_NOT_SUPPORTED
= 66
63 #define CQE_STATUS_COMPL_MASK 0xFFFF
64 #define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
65 #define CQE_STATUS_EXTD_MASK 0xFFFF
66 #define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */
69 u32 status
; /* dword 0 */
70 u32 tag0
; /* dword 1 */
71 u32 tag1
; /* dword 2 */
72 u32 flags
; /* dword 3 */
75 /* When the async bit of mcc_compl is set, the last 4 bytes of
76 * mcc_compl is interpreted as follows:
78 #define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
79 #define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
80 #define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16
81 #define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF
82 #define ASYNC_EVENT_CODE_LINK_STATE 0x1
83 #define ASYNC_EVENT_CODE_GRP_5 0x5
84 #define ASYNC_EVENT_QOS_SPEED 0x1
85 #define ASYNC_EVENT_COS_PRIORITY 0x2
86 #define ASYNC_EVENT_PVID_STATE 0x3
87 #define ASYNC_EVENT_CODE_QNQ 0x6
88 #define ASYNC_DEBUG_EVENT_TYPE_QNQ 1
90 struct be_async_event_trailer
{
98 #define LINK_STATUS_MASK 0x1
99 #define LOGICAL_LINK_STATUS_MASK 0x2
101 /* When the event code of an async trailer is link-state, the mcc_compl
102 * must be interpreted as follows
104 struct be_async_event_link_state
{
111 struct be_async_event_trailer trailer
;
114 /* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
115 * the mcc_compl must be interpreted as follows
117 struct be_async_event_grp5_qos_link_speed
{
122 struct be_async_event_trailer trailer
;
125 /* When the event code of an async trailer is GRP5 and event type is
126 * CoS-Priority, the mcc_compl must be interpreted as follows
128 struct be_async_event_grp5_cos_priority
{
130 u8 available_priority_bmap
;
131 u8 reco_default_priority
;
135 struct be_async_event_trailer trailer
;
138 /* When the event code of an async trailer is GRP5 and event type is
139 * PVID state, the mcc_compl must be interpreted as follows
141 struct be_async_event_grp5_pvid_state
{
147 struct be_async_event_trailer trailer
;
150 /* async event indicating outer VLAN tag in QnQ */
151 struct be_async_event_qnq
{
152 u8 valid
; /* Indicates if outer VLAN is valid */
157 struct be_async_event_trailer trailer
;
160 struct be_mcc_mailbox
{
161 struct be_mcc_wrb wrb
;
162 struct be_mcc_compl
compl;
165 #define CMD_SUBSYSTEM_COMMON 0x1
166 #define CMD_SUBSYSTEM_ETH 0x3
167 #define CMD_SUBSYSTEM_LOWLEVEL 0xb
169 #define OPCODE_COMMON_NTWK_MAC_QUERY 1
170 #define OPCODE_COMMON_NTWK_MAC_SET 2
171 #define OPCODE_COMMON_NTWK_MULTICAST_SET 3
172 #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
173 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
174 #define OPCODE_COMMON_READ_FLASHROM 6
175 #define OPCODE_COMMON_WRITE_FLASHROM 7
176 #define OPCODE_COMMON_CQ_CREATE 12
177 #define OPCODE_COMMON_EQ_CREATE 13
178 #define OPCODE_COMMON_MCC_CREATE 21
179 #define OPCODE_COMMON_SET_QOS 28
180 #define OPCODE_COMMON_MCC_CREATE_EXT 90
181 #define OPCODE_COMMON_SEEPROM_READ 30
182 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32
183 #define OPCODE_COMMON_NTWK_RX_FILTER 34
184 #define OPCODE_COMMON_GET_FW_VERSION 35
185 #define OPCODE_COMMON_SET_FLOW_CONTROL 36
186 #define OPCODE_COMMON_GET_FLOW_CONTROL 37
187 #define OPCODE_COMMON_SET_FRAME_SIZE 39
188 #define OPCODE_COMMON_MODIFY_EQ_DELAY 41
189 #define OPCODE_COMMON_FIRMWARE_CONFIG 42
190 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
191 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
192 #define OPCODE_COMMON_MCC_DESTROY 53
193 #define OPCODE_COMMON_CQ_DESTROY 54
194 #define OPCODE_COMMON_EQ_DESTROY 55
195 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
196 #define OPCODE_COMMON_NTWK_PMAC_ADD 59
197 #define OPCODE_COMMON_NTWK_PMAC_DEL 60
198 #define OPCODE_COMMON_FUNCTION_RESET 61
199 #define OPCODE_COMMON_MANAGE_FAT 68
200 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
201 #define OPCODE_COMMON_GET_BEACON_STATE 70
202 #define OPCODE_COMMON_READ_TRANSRECV_DATA 73
203 #define OPCODE_COMMON_GET_PORT_NAME 77
204 #define OPCODE_COMMON_SET_INTERRUPT_ENABLE 89
205 #define OPCODE_COMMON_GET_PHY_DETAILS 102
206 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103
207 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121
208 #define OPCODE_COMMON_GET_EXT_FAT_CAPABILITES 125
209 #define OPCODE_COMMON_SET_EXT_FAT_CAPABILITES 126
210 #define OPCODE_COMMON_GET_MAC_LIST 147
211 #define OPCODE_COMMON_SET_MAC_LIST 148
212 #define OPCODE_COMMON_GET_HSW_CONFIG 152
213 #define OPCODE_COMMON_GET_FUNC_CONFIG 160
214 #define OPCODE_COMMON_GET_PROFILE_CONFIG 164
215 #define OPCODE_COMMON_SET_PROFILE_CONFIG 165
216 #define OPCODE_COMMON_SET_HSW_CONFIG 153
217 #define OPCODE_COMMON_GET_FN_PRIVILEGES 170
218 #define OPCODE_COMMON_READ_OBJECT 171
219 #define OPCODE_COMMON_WRITE_OBJECT 172
220 #define OPCODE_COMMON_GET_IFACE_LIST 194
221 #define OPCODE_COMMON_ENABLE_DISABLE_VF 196
223 #define OPCODE_ETH_RSS_CONFIG 1
224 #define OPCODE_ETH_ACPI_CONFIG 2
225 #define OPCODE_ETH_PROMISCUOUS 3
226 #define OPCODE_ETH_GET_STATISTICS 4
227 #define OPCODE_ETH_TX_CREATE 7
228 #define OPCODE_ETH_RX_CREATE 8
229 #define OPCODE_ETH_TX_DESTROY 9
230 #define OPCODE_ETH_RX_DESTROY 10
231 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
232 #define OPCODE_ETH_GET_PPORT_STATS 18
234 #define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
235 #define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
236 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
238 struct be_cmd_req_hdr
{
239 u8 opcode
; /* dword 0 */
240 u8 subsystem
; /* dword 0 */
241 u8 port_number
; /* dword 0 */
242 u8 domain
; /* dword 0 */
243 u32 timeout
; /* dword 1 */
244 u32 request_length
; /* dword 2 */
245 u8 version
; /* dword 3 */
246 u8 rsvd
[3]; /* dword 3 */
249 #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
250 #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
251 struct be_cmd_resp_hdr
{
252 u8 opcode
; /* dword 0 */
253 u8 subsystem
; /* dword 0 */
254 u8 rsvd
[2]; /* dword 0 */
255 u8 status
; /* dword 1 */
256 u8 add_status
; /* dword 1 */
257 u8 rsvd1
[2]; /* dword 1 */
258 u32 response_length
; /* dword 2 */
259 u32 actual_resp_len
; /* dword 3 */
267 /**************************
268 * BE Command definitions *
269 **************************/
271 /* Pseudo amap definition in which each bit of the actual structure is defined
272 * as a byte: used to calculate offset/shift/mask of each field */
273 struct amap_eq_context
{
274 u8 cidx
[13]; /* dword 0*/
275 u8 rsvd0
[3]; /* dword 0*/
276 u8 epidx
[13]; /* dword 0*/
277 u8 valid
; /* dword 0*/
278 u8 rsvd1
; /* dword 0*/
279 u8 size
; /* dword 0*/
280 u8 pidx
[13]; /* dword 1*/
281 u8 rsvd2
[3]; /* dword 1*/
282 u8 pd
[10]; /* dword 1*/
283 u8 count
[3]; /* dword 1*/
284 u8 solevent
; /* dword 1*/
285 u8 stalled
; /* dword 1*/
286 u8 armed
; /* dword 1*/
287 u8 rsvd3
[4]; /* dword 2*/
288 u8 func
[8]; /* dword 2*/
289 u8 rsvd4
; /* dword 2*/
290 u8 delaymult
[10]; /* dword 2*/
291 u8 rsvd5
[2]; /* dword 2*/
292 u8 phase
[2]; /* dword 2*/
293 u8 nodelay
; /* dword 2*/
294 u8 rsvd6
[4]; /* dword 2*/
295 u8 rsvd7
[32]; /* dword 3*/
298 struct be_cmd_req_eq_create
{
299 struct be_cmd_req_hdr hdr
;
300 u16 num_pages
; /* sword */
301 u16 rsvd0
; /* sword */
302 u8 context
[sizeof(struct amap_eq_context
) / 8];
303 struct phys_addr pages
[8];
306 struct be_cmd_resp_eq_create
{
307 struct be_cmd_resp_hdr resp_hdr
;
308 u16 eq_id
; /* sword */
309 u16 rsvd0
; /* sword */
312 /******************** Mac query ***************************/
314 MAC_ADDRESS_TYPE_STORAGE
= 0x0,
315 MAC_ADDRESS_TYPE_NETWORK
= 0x1,
316 MAC_ADDRESS_TYPE_PD
= 0x2,
317 MAC_ADDRESS_TYPE_MANAGEMENT
= 0x3
325 struct be_cmd_req_mac_query
{
326 struct be_cmd_req_hdr hdr
;
333 struct be_cmd_resp_mac_query
{
334 struct be_cmd_resp_hdr hdr
;
338 /******************** PMac Add ***************************/
339 struct be_cmd_req_pmac_add
{
340 struct be_cmd_req_hdr hdr
;
342 u8 mac_address
[ETH_ALEN
];
346 struct be_cmd_resp_pmac_add
{
347 struct be_cmd_resp_hdr hdr
;
351 /******************** PMac Del ***************************/
352 struct be_cmd_req_pmac_del
{
353 struct be_cmd_req_hdr hdr
;
358 /******************** Create CQ ***************************/
359 /* Pseudo amap definition in which each bit of the actual structure is defined
360 * as a byte: used to calculate offset/shift/mask of each field */
361 struct amap_cq_context_be
{
362 u8 cidx
[11]; /* dword 0*/
363 u8 rsvd0
; /* dword 0*/
364 u8 coalescwm
[2]; /* dword 0*/
365 u8 nodelay
; /* dword 0*/
366 u8 epidx
[11]; /* dword 0*/
367 u8 rsvd1
; /* dword 0*/
368 u8 count
[2]; /* dword 0*/
369 u8 valid
; /* dword 0*/
370 u8 solevent
; /* dword 0*/
371 u8 eventable
; /* dword 0*/
372 u8 pidx
[11]; /* dword 1*/
373 u8 rsvd2
; /* dword 1*/
374 u8 pd
[10]; /* dword 1*/
375 u8 eqid
[8]; /* dword 1*/
376 u8 stalled
; /* dword 1*/
377 u8 armed
; /* dword 1*/
378 u8 rsvd3
[4]; /* dword 2*/
379 u8 func
[8]; /* dword 2*/
380 u8 rsvd4
[20]; /* dword 2*/
381 u8 rsvd5
[32]; /* dword 3*/
384 struct amap_cq_context_v2
{
385 u8 rsvd0
[12]; /* dword 0*/
386 u8 coalescwm
[2]; /* dword 0*/
387 u8 nodelay
; /* dword 0*/
388 u8 rsvd1
[12]; /* dword 0*/
389 u8 count
[2]; /* dword 0*/
390 u8 valid
; /* dword 0*/
391 u8 rsvd2
; /* dword 0*/
392 u8 eventable
; /* dword 0*/
393 u8 eqid
[16]; /* dword 1*/
394 u8 rsvd3
[15]; /* dword 1*/
395 u8 armed
; /* dword 1*/
396 u8 rsvd4
[32]; /* dword 2*/
397 u8 rsvd5
[32]; /* dword 3*/
400 struct be_cmd_req_cq_create
{
401 struct be_cmd_req_hdr hdr
;
405 u8 context
[sizeof(struct amap_cq_context_be
) / 8];
406 struct phys_addr pages
[8];
410 struct be_cmd_resp_cq_create
{
411 struct be_cmd_resp_hdr hdr
;
416 struct be_cmd_req_get_fat
{
417 struct be_cmd_req_hdr hdr
;
421 u32 data_buffer_size
;
425 struct be_cmd_resp_get_fat
{
426 struct be_cmd_resp_hdr hdr
;
434 /******************** Create MCCQ ***************************/
435 /* Pseudo amap definition in which each bit of the actual structure is defined
436 * as a byte: used to calculate offset/shift/mask of each field */
437 struct amap_mcc_context_be
{
452 struct amap_mcc_context_lancer
{
458 u8 async_cq_valid
[1];
463 struct be_cmd_req_mcc_create
{
464 struct be_cmd_req_hdr hdr
;
467 u8 context
[sizeof(struct amap_mcc_context_be
) / 8];
468 struct phys_addr pages
[8];
471 struct be_cmd_req_mcc_ext_create
{
472 struct be_cmd_req_hdr hdr
;
475 u32 async_event_bitmap
[1];
476 u8 context
[sizeof(struct amap_mcc_context_be
) / 8];
477 struct phys_addr pages
[8];
480 struct be_cmd_resp_mcc_create
{
481 struct be_cmd_resp_hdr hdr
;
486 /******************** Create TxQ ***************************/
487 #define BE_ETH_TX_RING_TYPE_STANDARD 2
488 #define BE_ULP1_NUM 1
490 struct be_cmd_req_eth_tx_create
{
491 struct be_cmd_req_hdr hdr
;
502 struct phys_addr pages
[8];
505 struct be_cmd_resp_eth_tx_create
{
506 struct be_cmd_resp_hdr hdr
;
513 /******************** Create RxQ ***************************/
514 struct be_cmd_req_eth_rx_create
{
515 struct be_cmd_req_hdr hdr
;
519 struct phys_addr pages
[2];
526 struct be_cmd_resp_eth_rx_create
{
527 struct be_cmd_resp_hdr hdr
;
533 /******************** Q Destroy ***************************/
534 /* Type of Queue to be destroyed */
543 struct be_cmd_req_q_destroy
{
544 struct be_cmd_req_hdr hdr
;
546 u16 bypass_flush
; /* valid only for rx q destroy */
549 /************ I/f Create (it's actually I/f Config Create)**********/
551 /* Capability flags for the i/f */
553 BE_IF_FLAGS_RSS
= 0x4,
554 BE_IF_FLAGS_PROMISCUOUS
= 0x8,
555 BE_IF_FLAGS_BROADCAST
= 0x10,
556 BE_IF_FLAGS_UNTAGGED
= 0x20,
557 BE_IF_FLAGS_ULP
= 0x40,
558 BE_IF_FLAGS_VLAN_PROMISCUOUS
= 0x80,
559 BE_IF_FLAGS_VLAN
= 0x100,
560 BE_IF_FLAGS_MCAST_PROMISCUOUS
= 0x200,
561 BE_IF_FLAGS_PASS_L2_ERRORS
= 0x400,
562 BE_IF_FLAGS_PASS_L3L4_ERRORS
= 0x800,
563 BE_IF_FLAGS_MULTICAST
= 0x1000
566 /* An RX interface is an object with one or more MAC addresses and
567 * filtering capabilities. */
568 struct be_cmd_req_if_create
{
569 struct be_cmd_req_hdr hdr
;
570 u32 version
; /* ignore currently */
571 u32 capability_flags
;
573 u8 mac_addr
[ETH_ALEN
];
575 u8 pmac_invalid
; /* if set, don't attach the mac addr to the i/f */
576 u32 vlan_tag
; /* not used currently */
579 struct be_cmd_resp_if_create
{
580 struct be_cmd_resp_hdr hdr
;
585 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
586 struct be_cmd_req_if_destroy
{
587 struct be_cmd_req_hdr hdr
;
591 /*************** HW Stats Get **********************************/
592 struct be_port_rxf_stats_v0
{
593 u32 rx_bytes_lsd
; /* dword 0*/
594 u32 rx_bytes_msd
; /* dword 1*/
595 u32 rx_total_frames
; /* dword 2*/
596 u32 rx_unicast_frames
; /* dword 3*/
597 u32 rx_multicast_frames
; /* dword 4*/
598 u32 rx_broadcast_frames
; /* dword 5*/
599 u32 rx_crc_errors
; /* dword 6*/
600 u32 rx_alignment_symbol_errors
; /* dword 7*/
601 u32 rx_pause_frames
; /* dword 8*/
602 u32 rx_control_frames
; /* dword 9*/
603 u32 rx_in_range_errors
; /* dword 10*/
604 u32 rx_out_range_errors
; /* dword 11*/
605 u32 rx_frame_too_long
; /* dword 12*/
606 u32 rx_address_filtered
; /* dword 13*/
607 u32 rx_vlan_filtered
; /* dword 14*/
608 u32 rx_dropped_too_small
; /* dword 15*/
609 u32 rx_dropped_too_short
; /* dword 16*/
610 u32 rx_dropped_header_too_small
; /* dword 17*/
611 u32 rx_dropped_tcp_length
; /* dword 18*/
612 u32 rx_dropped_runt
; /* dword 19*/
613 u32 rx_64_byte_packets
; /* dword 20*/
614 u32 rx_65_127_byte_packets
; /* dword 21*/
615 u32 rx_128_256_byte_packets
; /* dword 22*/
616 u32 rx_256_511_byte_packets
; /* dword 23*/
617 u32 rx_512_1023_byte_packets
; /* dword 24*/
618 u32 rx_1024_1518_byte_packets
; /* dword 25*/
619 u32 rx_1519_2047_byte_packets
; /* dword 26*/
620 u32 rx_2048_4095_byte_packets
; /* dword 27*/
621 u32 rx_4096_8191_byte_packets
; /* dword 28*/
622 u32 rx_8192_9216_byte_packets
; /* dword 29*/
623 u32 rx_ip_checksum_errs
; /* dword 30*/
624 u32 rx_tcp_checksum_errs
; /* dword 31*/
625 u32 rx_udp_checksum_errs
; /* dword 32*/
626 u32 rx_non_rss_packets
; /* dword 33*/
627 u32 rx_ipv4_packets
; /* dword 34*/
628 u32 rx_ipv6_packets
; /* dword 35*/
629 u32 rx_ipv4_bytes_lsd
; /* dword 36*/
630 u32 rx_ipv4_bytes_msd
; /* dword 37*/
631 u32 rx_ipv6_bytes_lsd
; /* dword 38*/
632 u32 rx_ipv6_bytes_msd
; /* dword 39*/
633 u32 rx_chute1_packets
; /* dword 40*/
634 u32 rx_chute2_packets
; /* dword 41*/
635 u32 rx_chute3_packets
; /* dword 42*/
636 u32 rx_management_packets
; /* dword 43*/
637 u32 rx_switched_unicast_packets
; /* dword 44*/
638 u32 rx_switched_multicast_packets
; /* dword 45*/
639 u32 rx_switched_broadcast_packets
; /* dword 46*/
640 u32 tx_bytes_lsd
; /* dword 47*/
641 u32 tx_bytes_msd
; /* dword 48*/
642 u32 tx_unicastframes
; /* dword 49*/
643 u32 tx_multicastframes
; /* dword 50*/
644 u32 tx_broadcastframes
; /* dword 51*/
645 u32 tx_pauseframes
; /* dword 52*/
646 u32 tx_controlframes
; /* dword 53*/
647 u32 tx_64_byte_packets
; /* dword 54*/
648 u32 tx_65_127_byte_packets
; /* dword 55*/
649 u32 tx_128_256_byte_packets
; /* dword 56*/
650 u32 tx_256_511_byte_packets
; /* dword 57*/
651 u32 tx_512_1023_byte_packets
; /* dword 58*/
652 u32 tx_1024_1518_byte_packets
; /* dword 59*/
653 u32 tx_1519_2047_byte_packets
; /* dword 60*/
654 u32 tx_2048_4095_byte_packets
; /* dword 61*/
655 u32 tx_4096_8191_byte_packets
; /* dword 62*/
656 u32 tx_8192_9216_byte_packets
; /* dword 63*/
657 u32 rx_fifo_overflow
; /* dword 64*/
658 u32 rx_input_fifo_overflow
; /* dword 65*/
661 struct be_rxf_stats_v0
{
662 struct be_port_rxf_stats_v0 port
[2];
663 u32 rx_drops_no_pbuf
; /* dword 132*/
664 u32 rx_drops_no_txpb
; /* dword 133*/
665 u32 rx_drops_no_erx_descr
; /* dword 134*/
666 u32 rx_drops_no_tpre_descr
; /* dword 135*/
667 u32 management_rx_port_packets
; /* dword 136*/
668 u32 management_rx_port_bytes
; /* dword 137*/
669 u32 management_rx_port_pause_frames
; /* dword 138*/
670 u32 management_rx_port_errors
; /* dword 139*/
671 u32 management_tx_port_packets
; /* dword 140*/
672 u32 management_tx_port_bytes
; /* dword 141*/
673 u32 management_tx_port_pause
; /* dword 142*/
674 u32 management_rx_port_rxfifo_overflow
; /* dword 143*/
675 u32 rx_drops_too_many_frags
; /* dword 144*/
676 u32 rx_drops_invalid_ring
; /* dword 145*/
677 u32 forwarded_packets
; /* dword 146*/
678 u32 rx_drops_mtu
; /* dword 147*/
680 u32 port0_jabber_events
;
681 u32 port1_jabber_events
;
685 struct be_erx_stats_v0
{
686 u32 rx_drops_no_fragments
[44]; /* dwordS 0 to 43*/
690 struct be_pmem_stats
{
695 struct be_hw_stats_v0
{
696 struct be_rxf_stats_v0 rxf
;
698 struct be_erx_stats_v0 erx
;
699 struct be_pmem_stats pmem
;
702 struct be_cmd_req_get_stats_v0
{
703 struct be_cmd_req_hdr hdr
;
704 u8 rsvd
[sizeof(struct be_hw_stats_v0
)];
707 struct be_cmd_resp_get_stats_v0
{
708 struct be_cmd_resp_hdr hdr
;
709 struct be_hw_stats_v0 hw_stats
;
712 struct lancer_pport_stats
{
715 u32 tx_unicast_packets_lo
;
716 u32 tx_unicast_packets_hi
;
717 u32 tx_multicast_packets_lo
;
718 u32 tx_multicast_packets_hi
;
719 u32 tx_broadcast_packets_lo
;
720 u32 tx_broadcast_packets_hi
;
723 u32 tx_unicast_bytes_lo
;
724 u32 tx_unicast_bytes_hi
;
725 u32 tx_multicast_bytes_lo
;
726 u32 tx_multicast_bytes_hi
;
727 u32 tx_broadcast_bytes_lo
;
728 u32 tx_broadcast_bytes_hi
;
733 u32 tx_pause_frames_lo
;
734 u32 tx_pause_frames_hi
;
735 u32 tx_pause_on_frames_lo
;
736 u32 tx_pause_on_frames_hi
;
737 u32 tx_pause_off_frames_lo
;
738 u32 tx_pause_off_frames_hi
;
739 u32 tx_internal_mac_errors_lo
;
740 u32 tx_internal_mac_errors_hi
;
741 u32 tx_control_frames_lo
;
742 u32 tx_control_frames_hi
;
743 u32 tx_packets_64_bytes_lo
;
744 u32 tx_packets_64_bytes_hi
;
745 u32 tx_packets_65_to_127_bytes_lo
;
746 u32 tx_packets_65_to_127_bytes_hi
;
747 u32 tx_packets_128_to_255_bytes_lo
;
748 u32 tx_packets_128_to_255_bytes_hi
;
749 u32 tx_packets_256_to_511_bytes_lo
;
750 u32 tx_packets_256_to_511_bytes_hi
;
751 u32 tx_packets_512_to_1023_bytes_lo
;
752 u32 tx_packets_512_to_1023_bytes_hi
;
753 u32 tx_packets_1024_to_1518_bytes_lo
;
754 u32 tx_packets_1024_to_1518_bytes_hi
;
755 u32 tx_packets_1519_to_2047_bytes_lo
;
756 u32 tx_packets_1519_to_2047_bytes_hi
;
757 u32 tx_packets_2048_to_4095_bytes_lo
;
758 u32 tx_packets_2048_to_4095_bytes_hi
;
759 u32 tx_packets_4096_to_8191_bytes_lo
;
760 u32 tx_packets_4096_to_8191_bytes_hi
;
761 u32 tx_packets_8192_to_9216_bytes_lo
;
762 u32 tx_packets_8192_to_9216_bytes_hi
;
763 u32 tx_lso_packets_lo
;
764 u32 tx_lso_packets_hi
;
767 u32 rx_unicast_packets_lo
;
768 u32 rx_unicast_packets_hi
;
769 u32 rx_multicast_packets_lo
;
770 u32 rx_multicast_packets_hi
;
771 u32 rx_broadcast_packets_lo
;
772 u32 rx_broadcast_packets_hi
;
775 u32 rx_unicast_bytes_lo
;
776 u32 rx_unicast_bytes_hi
;
777 u32 rx_multicast_bytes_lo
;
778 u32 rx_multicast_bytes_hi
;
779 u32 rx_broadcast_bytes_lo
;
780 u32 rx_broadcast_bytes_hi
;
781 u32 rx_unknown_protos
;
782 u32 rsvd_69
; /* Word 69 is reserved */
787 u32 rx_crc_errors_lo
;
788 u32 rx_crc_errors_hi
;
789 u32 rx_alignment_errors_lo
;
790 u32 rx_alignment_errors_hi
;
791 u32 rx_symbol_errors_lo
;
792 u32 rx_symbol_errors_hi
;
793 u32 rx_pause_frames_lo
;
794 u32 rx_pause_frames_hi
;
795 u32 rx_pause_on_frames_lo
;
796 u32 rx_pause_on_frames_hi
;
797 u32 rx_pause_off_frames_lo
;
798 u32 rx_pause_off_frames_hi
;
799 u32 rx_frames_too_long_lo
;
800 u32 rx_frames_too_long_hi
;
801 u32 rx_internal_mac_errors_lo
;
802 u32 rx_internal_mac_errors_hi
;
803 u32 rx_undersize_packets
;
804 u32 rx_oversize_packets
;
805 u32 rx_fragment_packets
;
807 u32 rx_control_frames_lo
;
808 u32 rx_control_frames_hi
;
809 u32 rx_control_frames_unknown_opcode_lo
;
810 u32 rx_control_frames_unknown_opcode_hi
;
811 u32 rx_in_range_errors
;
812 u32 rx_out_of_range_errors
;
813 u32 rx_address_filtered
;
814 u32 rx_vlan_filtered
;
815 u32 rx_dropped_too_small
;
816 u32 rx_dropped_too_short
;
817 u32 rx_dropped_header_too_small
;
818 u32 rx_dropped_invalid_tcp_length
;
820 u32 rx_ip_checksum_errors
;
821 u32 rx_tcp_checksum_errors
;
822 u32 rx_udp_checksum_errors
;
823 u32 rx_non_rss_packets
;
825 u32 rx_ipv4_packets_lo
;
826 u32 rx_ipv4_packets_hi
;
827 u32 rx_ipv6_packets_lo
;
828 u32 rx_ipv6_packets_hi
;
829 u32 rx_ipv4_bytes_lo
;
830 u32 rx_ipv4_bytes_hi
;
831 u32 rx_ipv6_bytes_lo
;
832 u32 rx_ipv6_bytes_hi
;
833 u32 rx_nic_packets_lo
;
834 u32 rx_nic_packets_hi
;
835 u32 rx_tcp_packets_lo
;
836 u32 rx_tcp_packets_hi
;
837 u32 rx_iscsi_packets_lo
;
838 u32 rx_iscsi_packets_hi
;
839 u32 rx_management_packets_lo
;
840 u32 rx_management_packets_hi
;
841 u32 rx_switched_unicast_packets_lo
;
842 u32 rx_switched_unicast_packets_hi
;
843 u32 rx_switched_multicast_packets_lo
;
844 u32 rx_switched_multicast_packets_hi
;
845 u32 rx_switched_broadcast_packets_lo
;
846 u32 rx_switched_broadcast_packets_hi
;
849 u32 rx_fifo_overflow
;
850 u32 rx_input_fifo_overflow
;
851 u32 rx_drops_too_many_frags_lo
;
852 u32 rx_drops_too_many_frags_hi
;
853 u32 rx_drops_invalid_queue
;
857 u32 rx_packets_64_bytes_lo
;
858 u32 rx_packets_64_bytes_hi
;
859 u32 rx_packets_65_to_127_bytes_lo
;
860 u32 rx_packets_65_to_127_bytes_hi
;
861 u32 rx_packets_128_to_255_bytes_lo
;
862 u32 rx_packets_128_to_255_bytes_hi
;
863 u32 rx_packets_256_to_511_bytes_lo
;
864 u32 rx_packets_256_to_511_bytes_hi
;
865 u32 rx_packets_512_to_1023_bytes_lo
;
866 u32 rx_packets_512_to_1023_bytes_hi
;
867 u32 rx_packets_1024_to_1518_bytes_lo
;
868 u32 rx_packets_1024_to_1518_bytes_hi
;
869 u32 rx_packets_1519_to_2047_bytes_lo
;
870 u32 rx_packets_1519_to_2047_bytes_hi
;
871 u32 rx_packets_2048_to_4095_bytes_lo
;
872 u32 rx_packets_2048_to_4095_bytes_hi
;
873 u32 rx_packets_4096_to_8191_bytes_lo
;
874 u32 rx_packets_4096_to_8191_bytes_hi
;
875 u32 rx_packets_8192_to_9216_bytes_lo
;
876 u32 rx_packets_8192_to_9216_bytes_hi
;
879 struct pport_stats_params
{
885 struct lancer_cmd_req_pport_stats
{
886 struct be_cmd_req_hdr hdr
;
888 struct pport_stats_params params
;
889 u8 rsvd
[sizeof(struct lancer_pport_stats
)];
893 struct lancer_cmd_resp_pport_stats
{
894 struct be_cmd_resp_hdr hdr
;
895 struct lancer_pport_stats pport_stats
;
898 static inline struct lancer_pport_stats
*
899 pport_stats_from_cmd(struct be_adapter
*adapter
)
901 struct lancer_cmd_resp_pport_stats
*cmd
= adapter
->stats_cmd
.va
;
902 return &cmd
->pport_stats
;
905 struct be_cmd_req_get_cntl_addnl_attribs
{
906 struct be_cmd_req_hdr hdr
;
910 struct be_cmd_resp_get_cntl_addnl_attribs
{
911 struct be_cmd_resp_hdr hdr
;
915 u8 on_die_temperature
; /* in degrees centigrade*/
919 struct be_cmd_req_vlan_config
{
920 struct be_cmd_req_hdr hdr
;
928 /******************* RX FILTER ******************************/
929 #define BE_MAX_MC 64 /* set mcast promisc if > 64 */
934 struct be_cmd_req_rx_filter
{
935 struct be_cmd_req_hdr hdr
;
936 u32 global_flags_mask
;
942 struct macaddr mcast_mac
[BE_MAX_MC
];
945 /******************** Link Status Query *******************/
946 struct be_cmd_req_link_status
{
947 struct be_cmd_req_hdr hdr
;
952 PHY_LINK_DUPLEX_NONE
= 0x0,
953 PHY_LINK_DUPLEX_HALF
= 0x1,
954 PHY_LINK_DUPLEX_FULL
= 0x2
958 PHY_LINK_SPEED_ZERO
= 0x0, /* => No link */
959 PHY_LINK_SPEED_10MBPS
= 0x1,
960 PHY_LINK_SPEED_100MBPS
= 0x2,
961 PHY_LINK_SPEED_1GBPS
= 0x3,
962 PHY_LINK_SPEED_10GBPS
= 0x4
965 struct be_cmd_resp_link_status
{
966 struct be_cmd_resp_hdr hdr
;
974 u8 logical_link_status
;
978 /******************** Port Identification ***************************/
979 /* Identifies the type of port attached to NIC */
980 struct be_cmd_req_port_type
{
981 struct be_cmd_req_hdr hdr
;
991 struct be_cmd_resp_port_type
{
992 struct be_cmd_resp_hdr hdr
;
1015 /******************** Get FW Version *******************/
1016 struct be_cmd_req_get_fw_version
{
1017 struct be_cmd_req_hdr hdr
;
1018 u8 rsvd0
[FW_VER_LEN
];
1019 u8 rsvd1
[FW_VER_LEN
];
1022 struct be_cmd_resp_get_fw_version
{
1023 struct be_cmd_resp_hdr hdr
;
1024 u8 firmware_version_string
[FW_VER_LEN
];
1025 u8 fw_on_flash_version_string
[FW_VER_LEN
];
1028 /******************** Set Flow Contrl *******************/
1029 struct be_cmd_req_set_flow_control
{
1030 struct be_cmd_req_hdr hdr
;
1031 u16 tx_flow_control
;
1032 u16 rx_flow_control
;
1035 /******************** Get Flow Contrl *******************/
1036 struct be_cmd_req_get_flow_control
{
1037 struct be_cmd_req_hdr hdr
;
1041 struct be_cmd_resp_get_flow_control
{
1042 struct be_cmd_resp_hdr hdr
;
1043 u16 tx_flow_control
;
1044 u16 rx_flow_control
;
1047 /******************** Modify EQ Delay *******************/
1048 struct be_cmd_req_modify_eq_delay
{
1049 struct be_cmd_req_hdr hdr
;
1054 u32 delay_multiplier
;
1058 struct be_cmd_resp_modify_eq_delay
{
1059 struct be_cmd_resp_hdr hdr
;
1063 /******************** Get FW Config *******************/
1064 /* The HW can come up in either of the following multi-channel modes
1065 * based on the skew/IPL.
1067 #define RDMA_ENABLED 0x4
1068 #define FLEX10_MODE 0x400
1069 #define VNIC_MODE 0x20000
1070 #define UMC_ENABLED 0x1000000
1071 struct be_cmd_req_query_fw_cfg
{
1072 struct be_cmd_req_hdr hdr
;
1076 struct be_cmd_resp_query_fw_cfg
{
1077 struct be_cmd_resp_hdr hdr
;
1078 u32 be_config_number
;
1086 /******************** RSS Config ****************************************/
1087 /* RSS type Input parameters used to compute RX hash
1088 * RSS_ENABLE_IPV4 SRC IPv4, DST IPv4
1089 * RSS_ENABLE_TCP_IPV4 SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT
1090 * RSS_ENABLE_IPV6 SRC IPv6, DST IPv6
1091 * RSS_ENABLE_TCP_IPV6 SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT
1092 * RSS_ENABLE_UDP_IPV4 SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT
1093 * RSS_ENABLE_UDP_IPV6 SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT
1095 * When multiple RSS types are enabled, HW picks the best hash policy
1096 * based on the type of the received packet.
1098 #define RSS_ENABLE_NONE 0x0
1099 #define RSS_ENABLE_IPV4 0x1
1100 #define RSS_ENABLE_TCP_IPV4 0x2
1101 #define RSS_ENABLE_IPV6 0x4
1102 #define RSS_ENABLE_TCP_IPV6 0x8
1103 #define RSS_ENABLE_UDP_IPV4 0x10
1104 #define RSS_ENABLE_UDP_IPV6 0x20
1106 #define L3_RSS_FLAGS (RXH_IP_DST | RXH_IP_SRC)
1107 #define L4_RSS_FLAGS (RXH_L4_B_0_1 | RXH_L4_B_2_3)
1109 struct be_cmd_req_rss_config
{
1110 struct be_cmd_req_hdr hdr
;
1113 u16 cpu_table_size_log2
;
1120 /******************** Port Beacon ***************************/
1122 #define BEACON_STATE_ENABLED 0x1
1123 #define BEACON_STATE_DISABLED 0x0
1125 struct be_cmd_req_enable_disable_beacon
{
1126 struct be_cmd_req_hdr hdr
;
1133 struct be_cmd_resp_enable_disable_beacon
{
1134 struct be_cmd_resp_hdr resp_hdr
;
1138 struct be_cmd_req_get_beacon_state
{
1139 struct be_cmd_req_hdr hdr
;
1145 struct be_cmd_resp_get_beacon_state
{
1146 struct be_cmd_resp_hdr resp_hdr
;
1151 /****************** Firmware Flash ******************/
1152 struct flashrom_params
{
1159 struct be_cmd_write_flashrom
{
1160 struct be_cmd_req_hdr hdr
;
1161 struct flashrom_params params
;
1166 /* cmd to read flash crc */
1167 struct be_cmd_read_flash_crc
{
1168 struct be_cmd_req_hdr hdr
;
1169 struct flashrom_params params
;
1173 /**************** Lancer Firmware Flash ************/
1174 struct amap_lancer_write_obj_context
{
1175 u8 write_length
[24];
1180 struct lancer_cmd_req_write_object
{
1181 struct be_cmd_req_hdr hdr
;
1182 u8 context
[sizeof(struct amap_lancer_write_obj_context
) / 8];
1184 u8 object_name
[104];
1185 u32 descriptor_count
;
1191 #define LANCER_NO_RESET_NEEDED 0x00
1192 #define LANCER_FW_RESET_NEEDED 0x02
1193 struct lancer_cmd_resp_write_object
{
1198 u8 additional_status
;
1201 u32 actual_resp_len
;
1202 u32 actual_write_len
;
1207 /************************ Lancer Read FW info **************/
1208 #define LANCER_READ_FILE_CHUNK (32*1024)
1209 #define LANCER_READ_FILE_EOF_MASK 0x80000000
1211 #define LANCER_FW_DUMP_FILE "/dbg/dump.bin"
1212 #define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd"
1213 #define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd"
1215 struct lancer_cmd_req_read_object
{
1216 struct be_cmd_req_hdr hdr
;
1217 u32 desired_read_len
;
1219 u8 object_name
[104];
1220 u32 descriptor_count
;
1226 struct lancer_cmd_resp_read_object
{
1231 u8 additional_status
;
1234 u32 actual_resp_len
;
1235 u32 actual_read_len
;
1239 /************************ WOL *******************************/
1240 struct be_cmd_req_acpi_wol_magic_config
{
1241 struct be_cmd_req_hdr hdr
;
1247 struct be_cmd_req_acpi_wol_magic_config_v1
{
1248 struct be_cmd_req_hdr hdr
;
1257 struct be_cmd_resp_acpi_wol_magic_config_v1
{
1258 struct be_cmd_resp_hdr hdr
;
1265 #define BE_GET_WOL_CAP 2
1267 #define BE_WOL_CAP 0x1
1268 #define BE_PME_D0_CAP 0x8
1269 #define BE_PME_D1_CAP 0x10
1270 #define BE_PME_D2_CAP 0x20
1271 #define BE_PME_D3HOT_CAP 0x40
1272 #define BE_PME_D3COLD_CAP 0x80
1274 /********************** LoopBack test *********************/
1275 struct be_cmd_req_loopback_test
{
1276 struct be_cmd_req_hdr hdr
;
1285 struct be_cmd_resp_loopback_test
{
1286 struct be_cmd_resp_hdr resp_hdr
;
1294 struct be_cmd_req_set_lmode
{
1295 struct be_cmd_req_hdr hdr
;
1302 struct be_cmd_resp_set_lmode
{
1303 struct be_cmd_resp_hdr resp_hdr
;
1307 /********************** DDR DMA test *********************/
1308 struct be_cmd_req_ddrdma_test
{
1309 struct be_cmd_req_hdr hdr
;
1317 struct be_cmd_resp_ddrdma_test
{
1318 struct be_cmd_resp_hdr hdr
;
1326 /*********************** SEEPROM Read ***********************/
1328 #define BE_READ_SEEPROM_LEN 1024
1329 struct be_cmd_req_seeprom_read
{
1330 struct be_cmd_req_hdr hdr
;
1331 u8 rsvd0
[BE_READ_SEEPROM_LEN
];
1334 struct be_cmd_resp_seeprom_read
{
1335 struct be_cmd_req_hdr hdr
;
1336 u8 seeprom_data
[BE_READ_SEEPROM_LEN
];
1340 PHY_TYPE_CX4_10GB
= 0,
1343 PHY_TYPE_SFP_PLUS_10GB
,
1346 PHY_TYPE_BASET_10GB
,
1350 PHY_TYPE_DISABLED
= 255
1353 #define BE_SUPPORTED_SPEED_NONE 0
1354 #define BE_SUPPORTED_SPEED_10MBPS 1
1355 #define BE_SUPPORTED_SPEED_100MBPS 2
1356 #define BE_SUPPORTED_SPEED_1GBPS 4
1357 #define BE_SUPPORTED_SPEED_10GBPS 8
1359 #define BE_AN_EN 0x2
1360 #define BE_PAUSE_SYM_EN 0x80
1362 /* MAC speed valid values */
1363 #define SPEED_DEFAULT 0x0
1364 #define SPEED_FORCED_10GB 0x1
1365 #define SPEED_FORCED_1GB 0x2
1366 #define SPEED_AUTONEG_10GB 0x3
1367 #define SPEED_AUTONEG_1GB 0x4
1368 #define SPEED_AUTONEG_100MB 0x5
1369 #define SPEED_AUTONEG_10GB_1GB 0x6
1370 #define SPEED_AUTONEG_10GB_1GB_100MB 0x7
1371 #define SPEED_AUTONEG_1GB_100MB 0x8
1372 #define SPEED_AUTONEG_10MB 0x9
1373 #define SPEED_AUTONEG_1GB_100MB_10MB 0xa
1374 #define SPEED_AUTONEG_100MB_10MB 0xb
1375 #define SPEED_FORCED_100MB 0xc
1376 #define SPEED_FORCED_10MB 0xd
1378 struct be_cmd_req_get_phy_info
{
1379 struct be_cmd_req_hdr hdr
;
1383 struct be_phy_info
{
1387 u16 ext_phy_details
;
1389 u16 auto_speeds_supported
;
1390 u16 fixed_speeds_supported
;
1394 struct be_cmd_resp_get_phy_info
{
1395 struct be_cmd_req_hdr hdr
;
1396 struct be_phy_info phy_info
;
1399 /*********************** Set QOS ***********************/
1401 #define BE_QOS_BITS_NIC 1
1403 struct be_cmd_req_set_qos
{
1404 struct be_cmd_req_hdr hdr
;
1410 struct be_cmd_resp_set_qos
{
1411 struct be_cmd_resp_hdr hdr
;
1415 /*********************** Controller Attributes ***********************/
1416 struct be_cmd_req_cntl_attribs
{
1417 struct be_cmd_req_hdr hdr
;
1420 struct be_cmd_resp_cntl_attribs
{
1421 struct be_cmd_resp_hdr hdr
;
1422 struct mgmt_controller_attrib attribs
;
1425 /*********************** Set driver function ***********************/
1426 #define CAPABILITY_SW_TIMESTAMPS 2
1427 #define CAPABILITY_BE3_NATIVE_ERX_API 4
1429 struct be_cmd_req_set_func_cap
{
1430 struct be_cmd_req_hdr hdr
;
1431 u32 valid_cap_flags
;
1436 struct be_cmd_resp_set_func_cap
{
1437 struct be_cmd_resp_hdr hdr
;
1438 u32 valid_cap_flags
;
1443 /*********************** Function Privileges ***********************/
1445 BE_PRIV_DEFAULT
= 0x1,
1446 BE_PRIV_LNKQUERY
= 0x2,
1447 BE_PRIV_LNKSTATS
= 0x4,
1448 BE_PRIV_LNKMGMT
= 0x8,
1449 BE_PRIV_LNKDIAG
= 0x10,
1450 BE_PRIV_UTILQUERY
= 0x20,
1451 BE_PRIV_FILTMGMT
= 0x40,
1452 BE_PRIV_IFACEMGMT
= 0x80,
1453 BE_PRIV_VHADM
= 0x100,
1454 BE_PRIV_DEVCFG
= 0x200,
1455 BE_PRIV_DEVSEC
= 0x400
1457 #define MAX_PRIVILEGES (BE_PRIV_VHADM | BE_PRIV_DEVCFG | \
1459 #define MIN_PRIVILEGES BE_PRIV_DEFAULT
1461 struct be_cmd_priv_map
{
1467 struct be_cmd_req_get_fn_privileges
{
1468 struct be_cmd_req_hdr hdr
;
1472 struct be_cmd_resp_get_fn_privileges
{
1473 struct be_cmd_resp_hdr hdr
;
1478 /******************** GET/SET_MACLIST **************************/
1479 #define BE_MAX_MAC 64
1480 struct be_cmd_req_get_mac_list
{
1481 struct be_cmd_req_hdr hdr
;
1489 struct get_list_macaddr
{
1496 } __packed s_mac_id
;
1497 } __packed mac_addr_id
;
1500 struct be_cmd_resp_get_mac_list
{
1501 struct be_cmd_resp_hdr hdr
;
1502 struct get_list_macaddr fd_macaddr
; /* Factory default mac */
1503 struct get_list_macaddr macid_macaddr
; /* soft mac */
1505 u8 pseudo_mac_count
;
1508 /* perm override mac */
1509 struct get_list_macaddr macaddr_list
[BE_MAX_MAC
];
1512 struct be_cmd_req_set_mac_list
{
1513 struct be_cmd_req_hdr hdr
;
1517 struct macaddr mac
[BE_MAX_MAC
];
1520 /*********************** HSW Config ***********************/
1521 struct amap_set_hsw_context
{
1522 u8 interface_id
[16];
1533 struct be_cmd_req_set_hsw_config
{
1534 struct be_cmd_req_hdr hdr
;
1535 u8 context
[sizeof(struct amap_set_hsw_context
) / 8];
1538 struct be_cmd_resp_set_hsw_config
{
1539 struct be_cmd_resp_hdr hdr
;
1543 struct amap_get_hsw_req_context
{
1544 u8 interface_id
[16];
1550 struct amap_get_hsw_resp_context
{
1558 struct be_cmd_req_get_hsw_config
{
1559 struct be_cmd_req_hdr hdr
;
1560 u8 context
[sizeof(struct amap_get_hsw_req_context
) / 8];
1563 struct be_cmd_resp_get_hsw_config
{
1564 struct be_cmd_resp_hdr hdr
;
1565 u8 context
[sizeof(struct amap_get_hsw_resp_context
) / 8];
1569 /******************* get port names ***************/
1570 struct be_cmd_req_get_port_name
{
1571 struct be_cmd_req_hdr hdr
;
1575 struct be_cmd_resp_get_port_name
{
1576 struct be_cmd_req_hdr hdr
;
1580 /*************** HW Stats Get v1 **********************************/
1581 #define BE_TXP_SW_SZ 48
1582 struct be_port_rxf_stats_v1
{
1585 u32 rx_alignment_symbol_errors
;
1586 u32 rx_pause_frames
;
1587 u32 rx_priority_pause_frames
;
1588 u32 rx_control_frames
;
1589 u32 rx_in_range_errors
;
1590 u32 rx_out_range_errors
;
1591 u32 rx_frame_too_long
;
1592 u32 rx_address_filtered
;
1593 u32 rx_dropped_too_small
;
1594 u32 rx_dropped_too_short
;
1595 u32 rx_dropped_header_too_small
;
1596 u32 rx_dropped_tcp_length
;
1597 u32 rx_dropped_runt
;
1599 u32 rx_ip_checksum_errs
;
1600 u32 rx_tcp_checksum_errs
;
1601 u32 rx_udp_checksum_errs
;
1603 u32 rx_switched_unicast_packets
;
1604 u32 rx_switched_multicast_packets
;
1605 u32 rx_switched_broadcast_packets
;
1608 u32 tx_priority_pauseframes
;
1609 u32 tx_controlframes
;
1611 u32 rxpp_fifo_overflow_drop
;
1612 u32 rx_input_fifo_overflow_drop
;
1613 u32 pmem_fifo_overflow_drop
;
1619 struct be_rxf_stats_v1
{
1620 struct be_port_rxf_stats_v1 port
[4];
1622 u32 rx_drops_no_pbuf
;
1623 u32 rx_drops_no_txpb
;
1624 u32 rx_drops_no_erx_descr
;
1625 u32 rx_drops_no_tpre_descr
;
1627 u32 rx_drops_too_many_frags
;
1628 u32 rx_drops_invalid_ring
;
1629 u32 forwarded_packets
;
1634 struct be_erx_stats_v1
{
1635 u32 rx_drops_no_fragments
[68]; /* dwordS 0 to 67*/
1639 struct be_hw_stats_v1
{
1640 struct be_rxf_stats_v1 rxf
;
1641 u32 rsvd0
[BE_TXP_SW_SZ
];
1642 struct be_erx_stats_v1 erx
;
1643 struct be_pmem_stats pmem
;
1647 struct be_cmd_req_get_stats_v1
{
1648 struct be_cmd_req_hdr hdr
;
1649 u8 rsvd
[sizeof(struct be_hw_stats_v1
)];
1652 struct be_cmd_resp_get_stats_v1
{
1653 struct be_cmd_resp_hdr hdr
;
1654 struct be_hw_stats_v1 hw_stats
;
1657 /************** get fat capabilites *******************/
1658 #define MAX_MODULES 27
1661 #define FW_LOG_LEVEL_DEFAULT 48
1662 #define FW_LOG_LEVEL_FATAL 64
1664 struct ext_fat_mode
{
1672 struct ext_fat_modules
{
1676 struct ext_fat_mode trace_lvl
[MAX_MODES
];
1679 struct be_fat_conf_params
{
1680 u32 max_log_entries
;
1688 struct ext_fat_modules module
[MAX_MODULES
];
1691 struct be_cmd_req_get_ext_fat_caps
{
1692 struct be_cmd_req_hdr hdr
;
1696 struct be_cmd_resp_get_ext_fat_caps
{
1697 struct be_cmd_resp_hdr hdr
;
1698 struct be_fat_conf_params get_params
;
1701 struct be_cmd_req_set_ext_fat_caps
{
1702 struct be_cmd_req_hdr hdr
;
1703 struct be_fat_conf_params set_params
;
1706 #define RESOURCE_DESC_SIZE 88
1707 #define NIC_RESOURCE_DESC_TYPE_V0 0x41
1708 #define NIC_RESOURCE_DESC_TYPE_V1 0x51
1709 #define MAX_RESOURCE_DESC 4
1710 #define MAX_RESOURCE_DESC_V1 32
1712 /* QOS unit number */
1719 struct be_nic_resource_desc
{
1728 u16 unicast_mac_count
;
1732 u16 mcast_mac_count
;
1752 struct be_cmd_req_get_func_config
{
1753 struct be_cmd_req_hdr hdr
;
1756 struct be_cmd_resp_get_func_config
{
1757 struct be_cmd_resp_hdr hdr
;
1759 u8 func_param
[MAX_RESOURCE_DESC
* RESOURCE_DESC_SIZE
];
1762 #define ACTIVE_PROFILE_TYPE 0x2
1763 struct be_cmd_req_get_profile_config
{
1764 struct be_cmd_req_hdr hdr
;
1770 struct be_cmd_resp_get_profile_config
{
1771 struct be_cmd_req_hdr hdr
;
1773 u8 func_param
[MAX_RESOURCE_DESC
* RESOURCE_DESC_SIZE
];
1776 struct be_cmd_resp_get_profile_config_v1
{
1777 struct be_cmd_req_hdr hdr
;
1779 u8 func_param
[MAX_RESOURCE_DESC_V1
* RESOURCE_DESC_SIZE
];
1782 struct be_cmd_req_set_profile_config
{
1783 struct be_cmd_req_hdr hdr
;
1786 struct be_nic_resource_desc nic_desc
;
1789 struct be_cmd_resp_set_profile_config
{
1790 struct be_cmd_req_hdr hdr
;
1793 struct be_cmd_enable_disable_vf
{
1794 struct be_cmd_req_hdr hdr
;
1799 struct be_cmd_req_intr_set
{
1800 struct be_cmd_req_hdr hdr
;
1805 static inline bool check_privilege(struct be_adapter
*adapter
, u32 flags
)
1807 return flags
& adapter
->cmd_privileges
? true : false;
1810 /************** Get IFACE LIST *******************/
1817 struct be_cmd_req_get_iface_list
{
1818 struct be_cmd_req_hdr hdr
;
1821 struct be_cmd_resp_get_iface_list
{
1822 struct be_cmd_req_hdr hdr
;
1824 struct be_if_desc if_desc
;
1827 extern int be_pci_fnum_get(struct be_adapter
*adapter
);
1828 extern int be_fw_wait_ready(struct be_adapter
*adapter
);
1829 extern int be_cmd_mac_addr_query(struct be_adapter
*adapter
, u8
*mac_addr
,
1830 bool permanent
, u32 if_handle
, u32 pmac_id
);
1831 extern int be_cmd_pmac_add(struct be_adapter
*adapter
, u8
*mac_addr
,
1832 u32 if_id
, u32
*pmac_id
, u32 domain
);
1833 extern int be_cmd_pmac_del(struct be_adapter
*adapter
, u32 if_id
,
1834 int pmac_id
, u32 domain
);
1835 extern int be_cmd_if_create(struct be_adapter
*adapter
, u32 cap_flags
,
1836 u32 en_flags
, u32
*if_handle
, u32 domain
);
1837 extern int be_cmd_if_destroy(struct be_adapter
*adapter
, int if_handle
,
1839 extern int be_cmd_eq_create(struct be_adapter
*adapter
,
1840 struct be_queue_info
*eq
, int eq_delay
);
1841 extern int be_cmd_cq_create(struct be_adapter
*adapter
,
1842 struct be_queue_info
*cq
, struct be_queue_info
*eq
,
1843 bool no_delay
, int num_cqe_dma_coalesce
);
1844 extern int be_cmd_mccq_create(struct be_adapter
*adapter
,
1845 struct be_queue_info
*mccq
,
1846 struct be_queue_info
*cq
);
1847 extern int be_cmd_txq_create(struct be_adapter
*adapter
,
1848 struct be_tx_obj
*txo
);
1849 extern int be_cmd_rxq_create(struct be_adapter
*adapter
,
1850 struct be_queue_info
*rxq
, u16 cq_id
,
1851 u16 frag_size
, u32 if_id
, u32 rss
, u8
*rss_id
);
1852 extern int be_cmd_q_destroy(struct be_adapter
*adapter
, struct be_queue_info
*q
,
1854 extern int be_cmd_rxq_destroy(struct be_adapter
*adapter
,
1855 struct be_queue_info
*q
);
1856 extern int be_cmd_link_status_query(struct be_adapter
*adapter
, u16
*link_speed
,
1857 u8
*link_status
, u32 dom
);
1858 extern int be_cmd_reset(struct be_adapter
*adapter
);
1859 extern int be_cmd_get_stats(struct be_adapter
*adapter
,
1860 struct be_dma_mem
*nonemb_cmd
);
1861 extern int lancer_cmd_get_pport_stats(struct be_adapter
*adapter
,
1862 struct be_dma_mem
*nonemb_cmd
);
1863 extern int be_cmd_get_fw_ver(struct be_adapter
*adapter
, char *fw_ver
,
1866 extern int be_cmd_modify_eqd(struct be_adapter
*adapter
, u32 eq_id
, u32 eqd
);
1867 extern int be_cmd_vlan_config(struct be_adapter
*adapter
, u32 if_id
,
1868 u16
*vtag_array
, u32 num
, bool untagged
,
1870 extern int be_cmd_rx_filter(struct be_adapter
*adapter
, u32 flags
, u32 status
);
1871 extern int be_cmd_set_flow_control(struct be_adapter
*adapter
,
1872 u32 tx_fc
, u32 rx_fc
);
1873 extern int be_cmd_get_flow_control(struct be_adapter
*adapter
,
1874 u32
*tx_fc
, u32
*rx_fc
);
1875 extern int be_cmd_query_fw_cfg(struct be_adapter
*adapter
, u32
*port_num
,
1876 u32
*function_mode
, u32
*function_caps
, u16
*asic_rev
);
1877 extern int be_cmd_reset_function(struct be_adapter
*adapter
);
1878 extern int be_cmd_rss_config(struct be_adapter
*adapter
, u8
*rsstable
,
1879 u32 rss_hash_opts
, u16 table_size
);
1880 extern int be_process_mcc(struct be_adapter
*adapter
);
1881 extern int be_cmd_set_beacon_state(struct be_adapter
*adapter
,
1882 u8 port_num
, u8 beacon
, u8 status
, u8 state
);
1883 extern int be_cmd_get_beacon_state(struct be_adapter
*adapter
,
1884 u8 port_num
, u32
*state
);
1885 extern int be_cmd_write_flashrom(struct be_adapter
*adapter
,
1886 struct be_dma_mem
*cmd
, u32 flash_oper
,
1887 u32 flash_opcode
, u32 buf_size
);
1888 extern int lancer_cmd_write_object(struct be_adapter
*adapter
,
1889 struct be_dma_mem
*cmd
,
1890 u32 data_size
, u32 data_offset
,
1891 const char *obj_name
,
1892 u32
*data_written
, u8
*change_status
,
1894 int lancer_cmd_read_object(struct be_adapter
*adapter
, struct be_dma_mem
*cmd
,
1895 u32 data_size
, u32 data_offset
, const char *obj_name
,
1896 u32
*data_read
, u32
*eof
, u8
*addn_status
);
1897 int be_cmd_get_flash_crc(struct be_adapter
*adapter
, u8
*flashed_crc
,
1899 extern int be_cmd_enable_magic_wol(struct be_adapter
*adapter
, u8
*mac
,
1900 struct be_dma_mem
*nonemb_cmd
);
1901 extern int be_cmd_fw_init(struct be_adapter
*adapter
);
1902 extern int be_cmd_fw_clean(struct be_adapter
*adapter
);
1903 extern void be_async_mcc_enable(struct be_adapter
*adapter
);
1904 extern void be_async_mcc_disable(struct be_adapter
*adapter
);
1905 extern int be_cmd_loopback_test(struct be_adapter
*adapter
, u32 port_num
,
1906 u32 loopback_type
, u32 pkt_size
,
1907 u32 num_pkts
, u64 pattern
);
1908 extern int be_cmd_ddr_dma_test(struct be_adapter
*adapter
, u64 pattern
,
1909 u32 byte_cnt
, struct be_dma_mem
*cmd
);
1910 extern int be_cmd_get_seeprom_data(struct be_adapter
*adapter
,
1911 struct be_dma_mem
*nonemb_cmd
);
1912 extern int be_cmd_set_loopback(struct be_adapter
*adapter
, u8 port_num
,
1913 u8 loopback_type
, u8 enable
);
1914 extern int be_cmd_get_phy_info(struct be_adapter
*adapter
);
1915 extern int be_cmd_set_qos(struct be_adapter
*adapter
, u32 bps
, u32 domain
);
1916 extern void be_detect_error(struct be_adapter
*adapter
);
1917 extern int be_cmd_get_die_temperature(struct be_adapter
*adapter
);
1918 extern int be_cmd_get_cntl_attributes(struct be_adapter
*adapter
);
1919 extern int be_cmd_req_native_mode(struct be_adapter
*adapter
);
1920 extern int be_cmd_get_reg_len(struct be_adapter
*adapter
, u32
*log_size
);
1921 extern void be_cmd_get_regs(struct be_adapter
*adapter
, u32 buf_len
, void *buf
);
1922 extern int be_cmd_get_fn_privileges(struct be_adapter
*adapter
,
1923 u32
*privilege
, u32 domain
);
1924 extern int be_cmd_get_mac_from_list(struct be_adapter
*adapter
, u8
*mac
,
1925 bool *pmac_id_active
, u32
*pmac_id
,
1927 extern int be_cmd_set_mac_list(struct be_adapter
*adapter
, u8
*mac_array
,
1928 u8 mac_count
, u32 domain
);
1929 extern int be_cmd_set_hsw_config(struct be_adapter
*adapter
, u16 pvid
,
1930 u32 domain
, u16 intf_id
);
1931 extern int be_cmd_get_hsw_config(struct be_adapter
*adapter
, u16
*pvid
,
1932 u32 domain
, u16 intf_id
);
1933 extern int be_cmd_get_acpi_wol_cap(struct be_adapter
*adapter
);
1934 extern int be_cmd_get_ext_fat_capabilites(struct be_adapter
*adapter
,
1935 struct be_dma_mem
*cmd
);
1936 extern int be_cmd_set_ext_fat_capabilites(struct be_adapter
*adapter
,
1937 struct be_dma_mem
*cmd
,
1938 struct be_fat_conf_params
*cfgs
);
1939 extern int lancer_wait_ready(struct be_adapter
*adapter
);
1940 extern int lancer_physdev_ctrl(struct be_adapter
*adapter
, u32 mask
);
1941 extern int lancer_initiate_dump(struct be_adapter
*adapter
);
1942 extern bool dump_present(struct be_adapter
*adapter
);
1943 extern int lancer_test_and_set_rdy_state(struct be_adapter
*adapter
);
1944 extern int be_cmd_query_port_name(struct be_adapter
*adapter
, u8
*port_name
);
1945 extern int be_cmd_get_func_config(struct be_adapter
*adapter
);
1946 extern int be_cmd_get_profile_config(struct be_adapter
*adapter
, u32
*cap_flags
,
1947 u16
*txq_count
, u8 domain
);
1949 extern int be_cmd_set_profile_config(struct be_adapter
*adapter
, u32 bps
,
1951 extern int be_cmd_get_if_id(struct be_adapter
*adapter
,
1952 struct be_vf_cfg
*vf_cfg
, int vf_num
);
1953 extern int be_cmd_enable_vf(struct be_adapter
*adapter
, u8 domain
);
1954 extern int be_cmd_intr_set(struct be_adapter
*adapter
, bool intr_enable
);