regulator: da9063: Add missing initialization of da9063_reg_matches
[deliverable/linux.git] / drivers / net / ethernet / emulex / benet / be_cmds.h
1 /*
2 * Copyright (C) 2005 - 2013 Emulex
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@emulex.com
12 *
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
16 */
17
18 /*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26 struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30 };
31
32 #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35 struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45 };
46
47 #define CQE_FLAGS_VALID_MASK (1 << 31)
48 #define CQE_FLAGS_ASYNC_MASK (1 << 30)
49 #define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50 #define CQE_FLAGS_CONSUMED_MASK (1 << 27)
51
52 /* Completion Status */
53 enum {
54 MCC_STATUS_SUCCESS = 0,
55 MCC_STATUS_FAILED = 1,
56 MCC_STATUS_ILLEGAL_REQUEST = 2,
57 MCC_STATUS_ILLEGAL_FIELD = 3,
58 MCC_STATUS_INSUFFICIENT_BUFFER = 4,
59 MCC_STATUS_UNAUTHORIZED_REQUEST = 5,
60 MCC_STATUS_NOT_SUPPORTED = 66
61 };
62
63 #define CQE_STATUS_COMPL_MASK 0xFFFF
64 #define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
65 #define CQE_STATUS_EXTD_MASK 0xFFFF
66 #define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */
67
68 struct be_mcc_compl {
69 u32 status; /* dword 0 */
70 u32 tag0; /* dword 1 */
71 u32 tag1; /* dword 2 */
72 u32 flags; /* dword 3 */
73 };
74
75 /* When the async bit of mcc_compl is set, the last 4 bytes of
76 * mcc_compl is interpreted as follows:
77 */
78 #define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
79 #define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
80 #define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16
81 #define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF
82 #define ASYNC_EVENT_CODE_LINK_STATE 0x1
83 #define ASYNC_EVENT_CODE_GRP_5 0x5
84 #define ASYNC_EVENT_QOS_SPEED 0x1
85 #define ASYNC_EVENT_COS_PRIORITY 0x2
86 #define ASYNC_EVENT_PVID_STATE 0x3
87 #define ASYNC_EVENT_CODE_QNQ 0x6
88 #define ASYNC_DEBUG_EVENT_TYPE_QNQ 1
89
90 struct be_async_event_trailer {
91 u32 code;
92 };
93
94 enum {
95 LINK_DOWN = 0x0,
96 LINK_UP = 0x1
97 };
98 #define LINK_STATUS_MASK 0x1
99 #define LOGICAL_LINK_STATUS_MASK 0x2
100
101 /* When the event code of an async trailer is link-state, the mcc_compl
102 * must be interpreted as follows
103 */
104 struct be_async_event_link_state {
105 u8 physical_port;
106 u8 port_link_status;
107 u8 port_duplex;
108 u8 port_speed;
109 u8 port_fault;
110 u8 rsvd0[7];
111 struct be_async_event_trailer trailer;
112 } __packed;
113
114 /* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
115 * the mcc_compl must be interpreted as follows
116 */
117 struct be_async_event_grp5_qos_link_speed {
118 u8 physical_port;
119 u8 rsvd[5];
120 u16 qos_link_speed;
121 u32 event_tag;
122 struct be_async_event_trailer trailer;
123 } __packed;
124
125 /* When the event code of an async trailer is GRP5 and event type is
126 * CoS-Priority, the mcc_compl must be interpreted as follows
127 */
128 struct be_async_event_grp5_cos_priority {
129 u8 physical_port;
130 u8 available_priority_bmap;
131 u8 reco_default_priority;
132 u8 valid;
133 u8 rsvd0;
134 u8 event_tag;
135 struct be_async_event_trailer trailer;
136 } __packed;
137
138 /* When the event code of an async trailer is GRP5 and event type is
139 * PVID state, the mcc_compl must be interpreted as follows
140 */
141 struct be_async_event_grp5_pvid_state {
142 u8 enabled;
143 u8 rsvd0;
144 u16 tag;
145 u32 event_tag;
146 u32 rsvd1;
147 struct be_async_event_trailer trailer;
148 } __packed;
149
150 /* async event indicating outer VLAN tag in QnQ */
151 struct be_async_event_qnq {
152 u8 valid; /* Indicates if outer VLAN is valid */
153 u8 rsvd0;
154 u16 vlan_tag;
155 u32 event_tag;
156 u8 rsvd1[4];
157 struct be_async_event_trailer trailer;
158 } __packed;
159
160 struct be_mcc_mailbox {
161 struct be_mcc_wrb wrb;
162 struct be_mcc_compl compl;
163 };
164
165 #define CMD_SUBSYSTEM_COMMON 0x1
166 #define CMD_SUBSYSTEM_ETH 0x3
167 #define CMD_SUBSYSTEM_LOWLEVEL 0xb
168
169 #define OPCODE_COMMON_NTWK_MAC_QUERY 1
170 #define OPCODE_COMMON_NTWK_MAC_SET 2
171 #define OPCODE_COMMON_NTWK_MULTICAST_SET 3
172 #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
173 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
174 #define OPCODE_COMMON_READ_FLASHROM 6
175 #define OPCODE_COMMON_WRITE_FLASHROM 7
176 #define OPCODE_COMMON_CQ_CREATE 12
177 #define OPCODE_COMMON_EQ_CREATE 13
178 #define OPCODE_COMMON_MCC_CREATE 21
179 #define OPCODE_COMMON_SET_QOS 28
180 #define OPCODE_COMMON_MCC_CREATE_EXT 90
181 #define OPCODE_COMMON_SEEPROM_READ 30
182 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32
183 #define OPCODE_COMMON_NTWK_RX_FILTER 34
184 #define OPCODE_COMMON_GET_FW_VERSION 35
185 #define OPCODE_COMMON_SET_FLOW_CONTROL 36
186 #define OPCODE_COMMON_GET_FLOW_CONTROL 37
187 #define OPCODE_COMMON_SET_FRAME_SIZE 39
188 #define OPCODE_COMMON_MODIFY_EQ_DELAY 41
189 #define OPCODE_COMMON_FIRMWARE_CONFIG 42
190 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
191 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
192 #define OPCODE_COMMON_MCC_DESTROY 53
193 #define OPCODE_COMMON_CQ_DESTROY 54
194 #define OPCODE_COMMON_EQ_DESTROY 55
195 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
196 #define OPCODE_COMMON_NTWK_PMAC_ADD 59
197 #define OPCODE_COMMON_NTWK_PMAC_DEL 60
198 #define OPCODE_COMMON_FUNCTION_RESET 61
199 #define OPCODE_COMMON_MANAGE_FAT 68
200 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
201 #define OPCODE_COMMON_GET_BEACON_STATE 70
202 #define OPCODE_COMMON_READ_TRANSRECV_DATA 73
203 #define OPCODE_COMMON_GET_PORT_NAME 77
204 #define OPCODE_COMMON_SET_INTERRUPT_ENABLE 89
205 #define OPCODE_COMMON_SET_FN_PRIVILEGES 100
206 #define OPCODE_COMMON_GET_PHY_DETAILS 102
207 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103
208 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121
209 #define OPCODE_COMMON_GET_EXT_FAT_CAPABILITES 125
210 #define OPCODE_COMMON_SET_EXT_FAT_CAPABILITES 126
211 #define OPCODE_COMMON_GET_MAC_LIST 147
212 #define OPCODE_COMMON_SET_MAC_LIST 148
213 #define OPCODE_COMMON_GET_HSW_CONFIG 152
214 #define OPCODE_COMMON_GET_FUNC_CONFIG 160
215 #define OPCODE_COMMON_GET_PROFILE_CONFIG 164
216 #define OPCODE_COMMON_SET_PROFILE_CONFIG 165
217 #define OPCODE_COMMON_SET_HSW_CONFIG 153
218 #define OPCODE_COMMON_GET_FN_PRIVILEGES 170
219 #define OPCODE_COMMON_READ_OBJECT 171
220 #define OPCODE_COMMON_WRITE_OBJECT 172
221 #define OPCODE_COMMON_GET_IFACE_LIST 194
222 #define OPCODE_COMMON_ENABLE_DISABLE_VF 196
223
224 #define OPCODE_ETH_RSS_CONFIG 1
225 #define OPCODE_ETH_ACPI_CONFIG 2
226 #define OPCODE_ETH_PROMISCUOUS 3
227 #define OPCODE_ETH_GET_STATISTICS 4
228 #define OPCODE_ETH_TX_CREATE 7
229 #define OPCODE_ETH_RX_CREATE 8
230 #define OPCODE_ETH_TX_DESTROY 9
231 #define OPCODE_ETH_RX_DESTROY 10
232 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
233 #define OPCODE_ETH_GET_PPORT_STATS 18
234
235 #define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
236 #define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
237 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
238
239 struct be_cmd_req_hdr {
240 u8 opcode; /* dword 0 */
241 u8 subsystem; /* dword 0 */
242 u8 port_number; /* dword 0 */
243 u8 domain; /* dword 0 */
244 u32 timeout; /* dword 1 */
245 u32 request_length; /* dword 2 */
246 u8 version; /* dword 3 */
247 u8 rsvd[3]; /* dword 3 */
248 };
249
250 #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
251 #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
252 struct be_cmd_resp_hdr {
253 u8 opcode; /* dword 0 */
254 u8 subsystem; /* dword 0 */
255 u8 rsvd[2]; /* dword 0 */
256 u8 status; /* dword 1 */
257 u8 add_status; /* dword 1 */
258 u8 rsvd1[2]; /* dword 1 */
259 u32 response_length; /* dword 2 */
260 u32 actual_resp_len; /* dword 3 */
261 };
262
263 struct phys_addr {
264 u32 lo;
265 u32 hi;
266 };
267
268 /**************************
269 * BE Command definitions *
270 **************************/
271
272 /* Pseudo amap definition in which each bit of the actual structure is defined
273 * as a byte: used to calculate offset/shift/mask of each field */
274 struct amap_eq_context {
275 u8 cidx[13]; /* dword 0*/
276 u8 rsvd0[3]; /* dword 0*/
277 u8 epidx[13]; /* dword 0*/
278 u8 valid; /* dword 0*/
279 u8 rsvd1; /* dword 0*/
280 u8 size; /* dword 0*/
281 u8 pidx[13]; /* dword 1*/
282 u8 rsvd2[3]; /* dword 1*/
283 u8 pd[10]; /* dword 1*/
284 u8 count[3]; /* dword 1*/
285 u8 solevent; /* dword 1*/
286 u8 stalled; /* dword 1*/
287 u8 armed; /* dword 1*/
288 u8 rsvd3[4]; /* dword 2*/
289 u8 func[8]; /* dword 2*/
290 u8 rsvd4; /* dword 2*/
291 u8 delaymult[10]; /* dword 2*/
292 u8 rsvd5[2]; /* dword 2*/
293 u8 phase[2]; /* dword 2*/
294 u8 nodelay; /* dword 2*/
295 u8 rsvd6[4]; /* dword 2*/
296 u8 rsvd7[32]; /* dword 3*/
297 } __packed;
298
299 struct be_cmd_req_eq_create {
300 struct be_cmd_req_hdr hdr;
301 u16 num_pages; /* sword */
302 u16 rsvd0; /* sword */
303 u8 context[sizeof(struct amap_eq_context) / 8];
304 struct phys_addr pages[8];
305 } __packed;
306
307 struct be_cmd_resp_eq_create {
308 struct be_cmd_resp_hdr resp_hdr;
309 u16 eq_id; /* sword */
310 u16 msix_idx; /* available only in v2 */
311 } __packed;
312
313 /******************** Mac query ***************************/
314 enum {
315 MAC_ADDRESS_TYPE_STORAGE = 0x0,
316 MAC_ADDRESS_TYPE_NETWORK = 0x1,
317 MAC_ADDRESS_TYPE_PD = 0x2,
318 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
319 };
320
321 struct mac_addr {
322 u16 size_of_struct;
323 u8 addr[ETH_ALEN];
324 } __packed;
325
326 struct be_cmd_req_mac_query {
327 struct be_cmd_req_hdr hdr;
328 u8 type;
329 u8 permanent;
330 u16 if_id;
331 u32 pmac_id;
332 } __packed;
333
334 struct be_cmd_resp_mac_query {
335 struct be_cmd_resp_hdr hdr;
336 struct mac_addr mac;
337 };
338
339 /******************** PMac Add ***************************/
340 struct be_cmd_req_pmac_add {
341 struct be_cmd_req_hdr hdr;
342 u32 if_id;
343 u8 mac_address[ETH_ALEN];
344 u8 rsvd0[2];
345 } __packed;
346
347 struct be_cmd_resp_pmac_add {
348 struct be_cmd_resp_hdr hdr;
349 u32 pmac_id;
350 };
351
352 /******************** PMac Del ***************************/
353 struct be_cmd_req_pmac_del {
354 struct be_cmd_req_hdr hdr;
355 u32 if_id;
356 u32 pmac_id;
357 };
358
359 /******************** Create CQ ***************************/
360 /* Pseudo amap definition in which each bit of the actual structure is defined
361 * as a byte: used to calculate offset/shift/mask of each field */
362 struct amap_cq_context_be {
363 u8 cidx[11]; /* dword 0*/
364 u8 rsvd0; /* dword 0*/
365 u8 coalescwm[2]; /* dword 0*/
366 u8 nodelay; /* dword 0*/
367 u8 epidx[11]; /* dword 0*/
368 u8 rsvd1; /* dword 0*/
369 u8 count[2]; /* dword 0*/
370 u8 valid; /* dword 0*/
371 u8 solevent; /* dword 0*/
372 u8 eventable; /* dword 0*/
373 u8 pidx[11]; /* dword 1*/
374 u8 rsvd2; /* dword 1*/
375 u8 pd[10]; /* dword 1*/
376 u8 eqid[8]; /* dword 1*/
377 u8 stalled; /* dword 1*/
378 u8 armed; /* dword 1*/
379 u8 rsvd3[4]; /* dword 2*/
380 u8 func[8]; /* dword 2*/
381 u8 rsvd4[20]; /* dword 2*/
382 u8 rsvd5[32]; /* dword 3*/
383 } __packed;
384
385 struct amap_cq_context_v2 {
386 u8 rsvd0[12]; /* dword 0*/
387 u8 coalescwm[2]; /* dword 0*/
388 u8 nodelay; /* dword 0*/
389 u8 rsvd1[12]; /* dword 0*/
390 u8 count[2]; /* dword 0*/
391 u8 valid; /* dword 0*/
392 u8 rsvd2; /* dword 0*/
393 u8 eventable; /* dword 0*/
394 u8 eqid[16]; /* dword 1*/
395 u8 rsvd3[15]; /* dword 1*/
396 u8 armed; /* dword 1*/
397 u8 rsvd4[32]; /* dword 2*/
398 u8 rsvd5[32]; /* dword 3*/
399 } __packed;
400
401 struct be_cmd_req_cq_create {
402 struct be_cmd_req_hdr hdr;
403 u16 num_pages;
404 u8 page_size;
405 u8 rsvd0;
406 u8 context[sizeof(struct amap_cq_context_be) / 8];
407 struct phys_addr pages[8];
408 } __packed;
409
410
411 struct be_cmd_resp_cq_create {
412 struct be_cmd_resp_hdr hdr;
413 u16 cq_id;
414 u16 rsvd0;
415 } __packed;
416
417 struct be_cmd_req_get_fat {
418 struct be_cmd_req_hdr hdr;
419 u32 fat_operation;
420 u32 read_log_offset;
421 u32 read_log_length;
422 u32 data_buffer_size;
423 u32 data_buffer[1];
424 } __packed;
425
426 struct be_cmd_resp_get_fat {
427 struct be_cmd_resp_hdr hdr;
428 u32 log_size;
429 u32 read_log_length;
430 u32 rsvd[2];
431 u32 data_buffer[1];
432 } __packed;
433
434
435 /******************** Create MCCQ ***************************/
436 /* Pseudo amap definition in which each bit of the actual structure is defined
437 * as a byte: used to calculate offset/shift/mask of each field */
438 struct amap_mcc_context_be {
439 u8 con_index[14];
440 u8 rsvd0[2];
441 u8 ring_size[4];
442 u8 fetch_wrb;
443 u8 fetch_r2t;
444 u8 cq_id[10];
445 u8 prod_index[14];
446 u8 fid[8];
447 u8 pdid[9];
448 u8 valid;
449 u8 rsvd1[32];
450 u8 rsvd2[32];
451 } __packed;
452
453 struct amap_mcc_context_lancer {
454 u8 async_cq_id[16];
455 u8 ring_size[4];
456 u8 rsvd0[12];
457 u8 rsvd1[31];
458 u8 valid;
459 u8 async_cq_valid[1];
460 u8 rsvd2[31];
461 u8 rsvd3[32];
462 } __packed;
463
464 struct be_cmd_req_mcc_create {
465 struct be_cmd_req_hdr hdr;
466 u16 num_pages;
467 u16 cq_id;
468 u8 context[sizeof(struct amap_mcc_context_be) / 8];
469 struct phys_addr pages[8];
470 } __packed;
471
472 struct be_cmd_req_mcc_ext_create {
473 struct be_cmd_req_hdr hdr;
474 u16 num_pages;
475 u16 cq_id;
476 u32 async_event_bitmap[1];
477 u8 context[sizeof(struct amap_mcc_context_be) / 8];
478 struct phys_addr pages[8];
479 } __packed;
480
481 struct be_cmd_resp_mcc_create {
482 struct be_cmd_resp_hdr hdr;
483 u16 id;
484 u16 rsvd0;
485 } __packed;
486
487 /******************** Create TxQ ***************************/
488 #define BE_ETH_TX_RING_TYPE_STANDARD 2
489 #define BE_ULP1_NUM 1
490
491 struct be_cmd_req_eth_tx_create {
492 struct be_cmd_req_hdr hdr;
493 u8 num_pages;
494 u8 ulp_num;
495 u16 type;
496 u16 if_id;
497 u8 queue_size;
498 u8 rsvd0;
499 u32 rsvd1;
500 u16 cq_id;
501 u16 rsvd2;
502 u32 rsvd3[13];
503 struct phys_addr pages[8];
504 } __packed;
505
506 struct be_cmd_resp_eth_tx_create {
507 struct be_cmd_resp_hdr hdr;
508 u16 cid;
509 u16 rid;
510 u32 db_offset;
511 u32 rsvd0[4];
512 } __packed;
513
514 /******************** Create RxQ ***************************/
515 struct be_cmd_req_eth_rx_create {
516 struct be_cmd_req_hdr hdr;
517 u16 cq_id;
518 u8 frag_size;
519 u8 num_pages;
520 struct phys_addr pages[2];
521 u32 interface_id;
522 u16 max_frame_size;
523 u16 rsvd0;
524 u32 rss_queue;
525 } __packed;
526
527 struct be_cmd_resp_eth_rx_create {
528 struct be_cmd_resp_hdr hdr;
529 u16 id;
530 u8 rss_id;
531 u8 rsvd0;
532 } __packed;
533
534 /******************** Q Destroy ***************************/
535 /* Type of Queue to be destroyed */
536 enum {
537 QTYPE_EQ = 1,
538 QTYPE_CQ,
539 QTYPE_TXQ,
540 QTYPE_RXQ,
541 QTYPE_MCCQ
542 };
543
544 struct be_cmd_req_q_destroy {
545 struct be_cmd_req_hdr hdr;
546 u16 id;
547 u16 bypass_flush; /* valid only for rx q destroy */
548 } __packed;
549
550 /************ I/f Create (it's actually I/f Config Create)**********/
551
552 /* Capability flags for the i/f */
553 enum be_if_flags {
554 BE_IF_FLAGS_RSS = 0x4,
555 BE_IF_FLAGS_PROMISCUOUS = 0x8,
556 BE_IF_FLAGS_BROADCAST = 0x10,
557 BE_IF_FLAGS_UNTAGGED = 0x20,
558 BE_IF_FLAGS_ULP = 0x40,
559 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
560 BE_IF_FLAGS_VLAN = 0x100,
561 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
562 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
563 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
564 BE_IF_FLAGS_MULTICAST = 0x1000
565 };
566
567 #define BE_IF_CAP_FLAGS_WANT (BE_IF_FLAGS_RSS | BE_IF_FLAGS_PROMISCUOUS |\
568 BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_VLAN_PROMISCUOUS |\
569 BE_IF_FLAGS_VLAN | BE_IF_FLAGS_MCAST_PROMISCUOUS |\
570 BE_IF_FLAGS_PASS_L3L4_ERRORS | BE_IF_FLAGS_MULTICAST |\
571 BE_IF_FLAGS_UNTAGGED)
572
573 /* An RX interface is an object with one or more MAC addresses and
574 * filtering capabilities. */
575 struct be_cmd_req_if_create {
576 struct be_cmd_req_hdr hdr;
577 u32 version; /* ignore currently */
578 u32 capability_flags;
579 u32 enable_flags;
580 u8 mac_addr[ETH_ALEN];
581 u8 rsvd0;
582 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
583 u32 vlan_tag; /* not used currently */
584 } __packed;
585
586 struct be_cmd_resp_if_create {
587 struct be_cmd_resp_hdr hdr;
588 u32 interface_id;
589 u32 pmac_id;
590 };
591
592 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
593 struct be_cmd_req_if_destroy {
594 struct be_cmd_req_hdr hdr;
595 u32 interface_id;
596 };
597
598 /*************** HW Stats Get **********************************/
599 struct be_port_rxf_stats_v0 {
600 u32 rx_bytes_lsd; /* dword 0*/
601 u32 rx_bytes_msd; /* dword 1*/
602 u32 rx_total_frames; /* dword 2*/
603 u32 rx_unicast_frames; /* dword 3*/
604 u32 rx_multicast_frames; /* dword 4*/
605 u32 rx_broadcast_frames; /* dword 5*/
606 u32 rx_crc_errors; /* dword 6*/
607 u32 rx_alignment_symbol_errors; /* dword 7*/
608 u32 rx_pause_frames; /* dword 8*/
609 u32 rx_control_frames; /* dword 9*/
610 u32 rx_in_range_errors; /* dword 10*/
611 u32 rx_out_range_errors; /* dword 11*/
612 u32 rx_frame_too_long; /* dword 12*/
613 u32 rx_address_filtered; /* dword 13*/
614 u32 rx_vlan_filtered; /* dword 14*/
615 u32 rx_dropped_too_small; /* dword 15*/
616 u32 rx_dropped_too_short; /* dword 16*/
617 u32 rx_dropped_header_too_small; /* dword 17*/
618 u32 rx_dropped_tcp_length; /* dword 18*/
619 u32 rx_dropped_runt; /* dword 19*/
620 u32 rx_64_byte_packets; /* dword 20*/
621 u32 rx_65_127_byte_packets; /* dword 21*/
622 u32 rx_128_256_byte_packets; /* dword 22*/
623 u32 rx_256_511_byte_packets; /* dword 23*/
624 u32 rx_512_1023_byte_packets; /* dword 24*/
625 u32 rx_1024_1518_byte_packets; /* dword 25*/
626 u32 rx_1519_2047_byte_packets; /* dword 26*/
627 u32 rx_2048_4095_byte_packets; /* dword 27*/
628 u32 rx_4096_8191_byte_packets; /* dword 28*/
629 u32 rx_8192_9216_byte_packets; /* dword 29*/
630 u32 rx_ip_checksum_errs; /* dword 30*/
631 u32 rx_tcp_checksum_errs; /* dword 31*/
632 u32 rx_udp_checksum_errs; /* dword 32*/
633 u32 rx_non_rss_packets; /* dword 33*/
634 u32 rx_ipv4_packets; /* dword 34*/
635 u32 rx_ipv6_packets; /* dword 35*/
636 u32 rx_ipv4_bytes_lsd; /* dword 36*/
637 u32 rx_ipv4_bytes_msd; /* dword 37*/
638 u32 rx_ipv6_bytes_lsd; /* dword 38*/
639 u32 rx_ipv6_bytes_msd; /* dword 39*/
640 u32 rx_chute1_packets; /* dword 40*/
641 u32 rx_chute2_packets; /* dword 41*/
642 u32 rx_chute3_packets; /* dword 42*/
643 u32 rx_management_packets; /* dword 43*/
644 u32 rx_switched_unicast_packets; /* dword 44*/
645 u32 rx_switched_multicast_packets; /* dword 45*/
646 u32 rx_switched_broadcast_packets; /* dword 46*/
647 u32 tx_bytes_lsd; /* dword 47*/
648 u32 tx_bytes_msd; /* dword 48*/
649 u32 tx_unicastframes; /* dword 49*/
650 u32 tx_multicastframes; /* dword 50*/
651 u32 tx_broadcastframes; /* dword 51*/
652 u32 tx_pauseframes; /* dword 52*/
653 u32 tx_controlframes; /* dword 53*/
654 u32 tx_64_byte_packets; /* dword 54*/
655 u32 tx_65_127_byte_packets; /* dword 55*/
656 u32 tx_128_256_byte_packets; /* dword 56*/
657 u32 tx_256_511_byte_packets; /* dword 57*/
658 u32 tx_512_1023_byte_packets; /* dword 58*/
659 u32 tx_1024_1518_byte_packets; /* dword 59*/
660 u32 tx_1519_2047_byte_packets; /* dword 60*/
661 u32 tx_2048_4095_byte_packets; /* dword 61*/
662 u32 tx_4096_8191_byte_packets; /* dword 62*/
663 u32 tx_8192_9216_byte_packets; /* dword 63*/
664 u32 rx_fifo_overflow; /* dword 64*/
665 u32 rx_input_fifo_overflow; /* dword 65*/
666 };
667
668 struct be_rxf_stats_v0 {
669 struct be_port_rxf_stats_v0 port[2];
670 u32 rx_drops_no_pbuf; /* dword 132*/
671 u32 rx_drops_no_txpb; /* dword 133*/
672 u32 rx_drops_no_erx_descr; /* dword 134*/
673 u32 rx_drops_no_tpre_descr; /* dword 135*/
674 u32 management_rx_port_packets; /* dword 136*/
675 u32 management_rx_port_bytes; /* dword 137*/
676 u32 management_rx_port_pause_frames; /* dword 138*/
677 u32 management_rx_port_errors; /* dword 139*/
678 u32 management_tx_port_packets; /* dword 140*/
679 u32 management_tx_port_bytes; /* dword 141*/
680 u32 management_tx_port_pause; /* dword 142*/
681 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
682 u32 rx_drops_too_many_frags; /* dword 144*/
683 u32 rx_drops_invalid_ring; /* dword 145*/
684 u32 forwarded_packets; /* dword 146*/
685 u32 rx_drops_mtu; /* dword 147*/
686 u32 rsvd0[7];
687 u32 port0_jabber_events;
688 u32 port1_jabber_events;
689 u32 rsvd1[6];
690 };
691
692 struct be_erx_stats_v0 {
693 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
694 u32 rsvd[4];
695 };
696
697 struct be_pmem_stats {
698 u32 eth_red_drops;
699 u32 rsvd[5];
700 };
701
702 struct be_hw_stats_v0 {
703 struct be_rxf_stats_v0 rxf;
704 u32 rsvd[48];
705 struct be_erx_stats_v0 erx;
706 struct be_pmem_stats pmem;
707 };
708
709 struct be_cmd_req_get_stats_v0 {
710 struct be_cmd_req_hdr hdr;
711 u8 rsvd[sizeof(struct be_hw_stats_v0)];
712 };
713
714 struct be_cmd_resp_get_stats_v0 {
715 struct be_cmd_resp_hdr hdr;
716 struct be_hw_stats_v0 hw_stats;
717 };
718
719 struct lancer_pport_stats {
720 u32 tx_packets_lo;
721 u32 tx_packets_hi;
722 u32 tx_unicast_packets_lo;
723 u32 tx_unicast_packets_hi;
724 u32 tx_multicast_packets_lo;
725 u32 tx_multicast_packets_hi;
726 u32 tx_broadcast_packets_lo;
727 u32 tx_broadcast_packets_hi;
728 u32 tx_bytes_lo;
729 u32 tx_bytes_hi;
730 u32 tx_unicast_bytes_lo;
731 u32 tx_unicast_bytes_hi;
732 u32 tx_multicast_bytes_lo;
733 u32 tx_multicast_bytes_hi;
734 u32 tx_broadcast_bytes_lo;
735 u32 tx_broadcast_bytes_hi;
736 u32 tx_discards_lo;
737 u32 tx_discards_hi;
738 u32 tx_errors_lo;
739 u32 tx_errors_hi;
740 u32 tx_pause_frames_lo;
741 u32 tx_pause_frames_hi;
742 u32 tx_pause_on_frames_lo;
743 u32 tx_pause_on_frames_hi;
744 u32 tx_pause_off_frames_lo;
745 u32 tx_pause_off_frames_hi;
746 u32 tx_internal_mac_errors_lo;
747 u32 tx_internal_mac_errors_hi;
748 u32 tx_control_frames_lo;
749 u32 tx_control_frames_hi;
750 u32 tx_packets_64_bytes_lo;
751 u32 tx_packets_64_bytes_hi;
752 u32 tx_packets_65_to_127_bytes_lo;
753 u32 tx_packets_65_to_127_bytes_hi;
754 u32 tx_packets_128_to_255_bytes_lo;
755 u32 tx_packets_128_to_255_bytes_hi;
756 u32 tx_packets_256_to_511_bytes_lo;
757 u32 tx_packets_256_to_511_bytes_hi;
758 u32 tx_packets_512_to_1023_bytes_lo;
759 u32 tx_packets_512_to_1023_bytes_hi;
760 u32 tx_packets_1024_to_1518_bytes_lo;
761 u32 tx_packets_1024_to_1518_bytes_hi;
762 u32 tx_packets_1519_to_2047_bytes_lo;
763 u32 tx_packets_1519_to_2047_bytes_hi;
764 u32 tx_packets_2048_to_4095_bytes_lo;
765 u32 tx_packets_2048_to_4095_bytes_hi;
766 u32 tx_packets_4096_to_8191_bytes_lo;
767 u32 tx_packets_4096_to_8191_bytes_hi;
768 u32 tx_packets_8192_to_9216_bytes_lo;
769 u32 tx_packets_8192_to_9216_bytes_hi;
770 u32 tx_lso_packets_lo;
771 u32 tx_lso_packets_hi;
772 u32 rx_packets_lo;
773 u32 rx_packets_hi;
774 u32 rx_unicast_packets_lo;
775 u32 rx_unicast_packets_hi;
776 u32 rx_multicast_packets_lo;
777 u32 rx_multicast_packets_hi;
778 u32 rx_broadcast_packets_lo;
779 u32 rx_broadcast_packets_hi;
780 u32 rx_bytes_lo;
781 u32 rx_bytes_hi;
782 u32 rx_unicast_bytes_lo;
783 u32 rx_unicast_bytes_hi;
784 u32 rx_multicast_bytes_lo;
785 u32 rx_multicast_bytes_hi;
786 u32 rx_broadcast_bytes_lo;
787 u32 rx_broadcast_bytes_hi;
788 u32 rx_unknown_protos;
789 u32 rsvd_69; /* Word 69 is reserved */
790 u32 rx_discards_lo;
791 u32 rx_discards_hi;
792 u32 rx_errors_lo;
793 u32 rx_errors_hi;
794 u32 rx_crc_errors_lo;
795 u32 rx_crc_errors_hi;
796 u32 rx_alignment_errors_lo;
797 u32 rx_alignment_errors_hi;
798 u32 rx_symbol_errors_lo;
799 u32 rx_symbol_errors_hi;
800 u32 rx_pause_frames_lo;
801 u32 rx_pause_frames_hi;
802 u32 rx_pause_on_frames_lo;
803 u32 rx_pause_on_frames_hi;
804 u32 rx_pause_off_frames_lo;
805 u32 rx_pause_off_frames_hi;
806 u32 rx_frames_too_long_lo;
807 u32 rx_frames_too_long_hi;
808 u32 rx_internal_mac_errors_lo;
809 u32 rx_internal_mac_errors_hi;
810 u32 rx_undersize_packets;
811 u32 rx_oversize_packets;
812 u32 rx_fragment_packets;
813 u32 rx_jabbers;
814 u32 rx_control_frames_lo;
815 u32 rx_control_frames_hi;
816 u32 rx_control_frames_unknown_opcode_lo;
817 u32 rx_control_frames_unknown_opcode_hi;
818 u32 rx_in_range_errors;
819 u32 rx_out_of_range_errors;
820 u32 rx_address_filtered;
821 u32 rx_vlan_filtered;
822 u32 rx_dropped_too_small;
823 u32 rx_dropped_too_short;
824 u32 rx_dropped_header_too_small;
825 u32 rx_dropped_invalid_tcp_length;
826 u32 rx_dropped_runt;
827 u32 rx_ip_checksum_errors;
828 u32 rx_tcp_checksum_errors;
829 u32 rx_udp_checksum_errors;
830 u32 rx_non_rss_packets;
831 u32 rsvd_111;
832 u32 rx_ipv4_packets_lo;
833 u32 rx_ipv4_packets_hi;
834 u32 rx_ipv6_packets_lo;
835 u32 rx_ipv6_packets_hi;
836 u32 rx_ipv4_bytes_lo;
837 u32 rx_ipv4_bytes_hi;
838 u32 rx_ipv6_bytes_lo;
839 u32 rx_ipv6_bytes_hi;
840 u32 rx_nic_packets_lo;
841 u32 rx_nic_packets_hi;
842 u32 rx_tcp_packets_lo;
843 u32 rx_tcp_packets_hi;
844 u32 rx_iscsi_packets_lo;
845 u32 rx_iscsi_packets_hi;
846 u32 rx_management_packets_lo;
847 u32 rx_management_packets_hi;
848 u32 rx_switched_unicast_packets_lo;
849 u32 rx_switched_unicast_packets_hi;
850 u32 rx_switched_multicast_packets_lo;
851 u32 rx_switched_multicast_packets_hi;
852 u32 rx_switched_broadcast_packets_lo;
853 u32 rx_switched_broadcast_packets_hi;
854 u32 num_forwards_lo;
855 u32 num_forwards_hi;
856 u32 rx_fifo_overflow;
857 u32 rx_input_fifo_overflow;
858 u32 rx_drops_too_many_frags_lo;
859 u32 rx_drops_too_many_frags_hi;
860 u32 rx_drops_invalid_queue;
861 u32 rsvd_141;
862 u32 rx_drops_mtu_lo;
863 u32 rx_drops_mtu_hi;
864 u32 rx_packets_64_bytes_lo;
865 u32 rx_packets_64_bytes_hi;
866 u32 rx_packets_65_to_127_bytes_lo;
867 u32 rx_packets_65_to_127_bytes_hi;
868 u32 rx_packets_128_to_255_bytes_lo;
869 u32 rx_packets_128_to_255_bytes_hi;
870 u32 rx_packets_256_to_511_bytes_lo;
871 u32 rx_packets_256_to_511_bytes_hi;
872 u32 rx_packets_512_to_1023_bytes_lo;
873 u32 rx_packets_512_to_1023_bytes_hi;
874 u32 rx_packets_1024_to_1518_bytes_lo;
875 u32 rx_packets_1024_to_1518_bytes_hi;
876 u32 rx_packets_1519_to_2047_bytes_lo;
877 u32 rx_packets_1519_to_2047_bytes_hi;
878 u32 rx_packets_2048_to_4095_bytes_lo;
879 u32 rx_packets_2048_to_4095_bytes_hi;
880 u32 rx_packets_4096_to_8191_bytes_lo;
881 u32 rx_packets_4096_to_8191_bytes_hi;
882 u32 rx_packets_8192_to_9216_bytes_lo;
883 u32 rx_packets_8192_to_9216_bytes_hi;
884 };
885
886 struct pport_stats_params {
887 u16 pport_num;
888 u8 rsvd;
889 u8 reset_stats;
890 };
891
892 struct lancer_cmd_req_pport_stats {
893 struct be_cmd_req_hdr hdr;
894 union {
895 struct pport_stats_params params;
896 u8 rsvd[sizeof(struct lancer_pport_stats)];
897 } cmd_params;
898 };
899
900 struct lancer_cmd_resp_pport_stats {
901 struct be_cmd_resp_hdr hdr;
902 struct lancer_pport_stats pport_stats;
903 };
904
905 static inline struct lancer_pport_stats*
906 pport_stats_from_cmd(struct be_adapter *adapter)
907 {
908 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va;
909 return &cmd->pport_stats;
910 }
911
912 struct be_cmd_req_get_cntl_addnl_attribs {
913 struct be_cmd_req_hdr hdr;
914 u8 rsvd[8];
915 };
916
917 struct be_cmd_resp_get_cntl_addnl_attribs {
918 struct be_cmd_resp_hdr hdr;
919 u16 ipl_file_number;
920 u8 ipl_file_version;
921 u8 rsvd0;
922 u8 on_die_temperature; /* in degrees centigrade*/
923 u8 rsvd1[3];
924 };
925
926 struct be_cmd_req_vlan_config {
927 struct be_cmd_req_hdr hdr;
928 u8 interface_id;
929 u8 promiscuous;
930 u8 untagged;
931 u8 num_vlan;
932 u16 normal_vlan[64];
933 } __packed;
934
935 /******************* RX FILTER ******************************/
936 #define BE_MAX_MC 64 /* set mcast promisc if > 64 */
937 struct macaddr {
938 u8 byte[ETH_ALEN];
939 };
940
941 struct be_cmd_req_rx_filter {
942 struct be_cmd_req_hdr hdr;
943 u32 global_flags_mask;
944 u32 global_flags;
945 u32 if_flags_mask;
946 u32 if_flags;
947 u32 if_id;
948 u32 mcast_num;
949 struct macaddr mcast_mac[BE_MAX_MC];
950 };
951
952 /******************** Link Status Query *******************/
953 struct be_cmd_req_link_status {
954 struct be_cmd_req_hdr hdr;
955 u32 rsvd;
956 };
957
958 enum {
959 PHY_LINK_DUPLEX_NONE = 0x0,
960 PHY_LINK_DUPLEX_HALF = 0x1,
961 PHY_LINK_DUPLEX_FULL = 0x2
962 };
963
964 enum {
965 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
966 PHY_LINK_SPEED_10MBPS = 0x1,
967 PHY_LINK_SPEED_100MBPS = 0x2,
968 PHY_LINK_SPEED_1GBPS = 0x3,
969 PHY_LINK_SPEED_10GBPS = 0x4,
970 PHY_LINK_SPEED_20GBPS = 0x5,
971 PHY_LINK_SPEED_25GBPS = 0x6,
972 PHY_LINK_SPEED_40GBPS = 0x7
973 };
974
975 struct be_cmd_resp_link_status {
976 struct be_cmd_resp_hdr hdr;
977 u8 physical_port;
978 u8 mac_duplex;
979 u8 mac_speed;
980 u8 mac_fault;
981 u8 mgmt_mac_duplex;
982 u8 mgmt_mac_speed;
983 u16 link_speed;
984 u8 logical_link_status;
985 u8 rsvd1[3];
986 } __packed;
987
988 /******************** Port Identification ***************************/
989 /* Identifies the type of port attached to NIC */
990 struct be_cmd_req_port_type {
991 struct be_cmd_req_hdr hdr;
992 u32 page_num;
993 u32 port;
994 };
995
996 enum {
997 TR_PAGE_A0 = 0xa0,
998 TR_PAGE_A2 = 0xa2
999 };
1000
1001 struct be_cmd_resp_port_type {
1002 struct be_cmd_resp_hdr hdr;
1003 u32 page_num;
1004 u32 port;
1005 struct data {
1006 u8 identifier;
1007 u8 identifier_ext;
1008 u8 connector;
1009 u8 transceiver[8];
1010 u8 rsvd0[3];
1011 u8 length_km;
1012 u8 length_hm;
1013 u8 length_om1;
1014 u8 length_om2;
1015 u8 length_cu;
1016 u8 length_cu_m;
1017 u8 vendor_name[16];
1018 u8 rsvd;
1019 u8 vendor_oui[3];
1020 u8 vendor_pn[16];
1021 u8 vendor_rev[4];
1022 } data;
1023 };
1024
1025 /******************** Get FW Version *******************/
1026 struct be_cmd_req_get_fw_version {
1027 struct be_cmd_req_hdr hdr;
1028 u8 rsvd0[FW_VER_LEN];
1029 u8 rsvd1[FW_VER_LEN];
1030 } __packed;
1031
1032 struct be_cmd_resp_get_fw_version {
1033 struct be_cmd_resp_hdr hdr;
1034 u8 firmware_version_string[FW_VER_LEN];
1035 u8 fw_on_flash_version_string[FW_VER_LEN];
1036 } __packed;
1037
1038 /******************** Set Flow Contrl *******************/
1039 struct be_cmd_req_set_flow_control {
1040 struct be_cmd_req_hdr hdr;
1041 u16 tx_flow_control;
1042 u16 rx_flow_control;
1043 } __packed;
1044
1045 /******************** Get Flow Contrl *******************/
1046 struct be_cmd_req_get_flow_control {
1047 struct be_cmd_req_hdr hdr;
1048 u32 rsvd;
1049 };
1050
1051 struct be_cmd_resp_get_flow_control {
1052 struct be_cmd_resp_hdr hdr;
1053 u16 tx_flow_control;
1054 u16 rx_flow_control;
1055 } __packed;
1056
1057 /******************** Modify EQ Delay *******************/
1058 struct be_cmd_req_modify_eq_delay {
1059 struct be_cmd_req_hdr hdr;
1060 u32 num_eq;
1061 struct {
1062 u32 eq_id;
1063 u32 phase;
1064 u32 delay_multiplier;
1065 } delay[8];
1066 } __packed;
1067
1068 struct be_cmd_resp_modify_eq_delay {
1069 struct be_cmd_resp_hdr hdr;
1070 u32 rsvd0;
1071 } __packed;
1072
1073 /******************** Get FW Config *******************/
1074 /* The HW can come up in either of the following multi-channel modes
1075 * based on the skew/IPL.
1076 */
1077 #define RDMA_ENABLED 0x4
1078 #define FLEX10_MODE 0x400
1079 #define VNIC_MODE 0x20000
1080 #define UMC_ENABLED 0x1000000
1081 struct be_cmd_req_query_fw_cfg {
1082 struct be_cmd_req_hdr hdr;
1083 u32 rsvd[31];
1084 };
1085
1086 struct be_cmd_resp_query_fw_cfg {
1087 struct be_cmd_resp_hdr hdr;
1088 u32 be_config_number;
1089 u32 asic_revision;
1090 u32 phys_port;
1091 u32 function_mode;
1092 u32 rsvd[26];
1093 u32 function_caps;
1094 };
1095
1096 /******************** RSS Config ****************************************/
1097 /* RSS type Input parameters used to compute RX hash
1098 * RSS_ENABLE_IPV4 SRC IPv4, DST IPv4
1099 * RSS_ENABLE_TCP_IPV4 SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT
1100 * RSS_ENABLE_IPV6 SRC IPv6, DST IPv6
1101 * RSS_ENABLE_TCP_IPV6 SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT
1102 * RSS_ENABLE_UDP_IPV4 SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT
1103 * RSS_ENABLE_UDP_IPV6 SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT
1104 *
1105 * When multiple RSS types are enabled, HW picks the best hash policy
1106 * based on the type of the received packet.
1107 */
1108 #define RSS_ENABLE_NONE 0x0
1109 #define RSS_ENABLE_IPV4 0x1
1110 #define RSS_ENABLE_TCP_IPV4 0x2
1111 #define RSS_ENABLE_IPV6 0x4
1112 #define RSS_ENABLE_TCP_IPV6 0x8
1113 #define RSS_ENABLE_UDP_IPV4 0x10
1114 #define RSS_ENABLE_UDP_IPV6 0x20
1115
1116 #define L3_RSS_FLAGS (RXH_IP_DST | RXH_IP_SRC)
1117 #define L4_RSS_FLAGS (RXH_L4_B_0_1 | RXH_L4_B_2_3)
1118
1119 struct be_cmd_req_rss_config {
1120 struct be_cmd_req_hdr hdr;
1121 u32 if_id;
1122 u16 enable_rss;
1123 u16 cpu_table_size_log2;
1124 u32 hash[10];
1125 u8 cpu_table[128];
1126 u8 flush;
1127 u8 rsvd0[3];
1128 };
1129
1130 /******************** Port Beacon ***************************/
1131
1132 #define BEACON_STATE_ENABLED 0x1
1133 #define BEACON_STATE_DISABLED 0x0
1134
1135 struct be_cmd_req_enable_disable_beacon {
1136 struct be_cmd_req_hdr hdr;
1137 u8 port_num;
1138 u8 beacon_state;
1139 u8 beacon_duration;
1140 u8 status_duration;
1141 } __packed;
1142
1143 struct be_cmd_resp_enable_disable_beacon {
1144 struct be_cmd_resp_hdr resp_hdr;
1145 u32 rsvd0;
1146 } __packed;
1147
1148 struct be_cmd_req_get_beacon_state {
1149 struct be_cmd_req_hdr hdr;
1150 u8 port_num;
1151 u8 rsvd0;
1152 u16 rsvd1;
1153 } __packed;
1154
1155 struct be_cmd_resp_get_beacon_state {
1156 struct be_cmd_resp_hdr resp_hdr;
1157 u8 beacon_state;
1158 u8 rsvd0[3];
1159 } __packed;
1160
1161 /****************** Firmware Flash ******************/
1162 struct flashrom_params {
1163 u32 op_code;
1164 u32 op_type;
1165 u32 data_buf_size;
1166 u32 offset;
1167 };
1168
1169 struct be_cmd_write_flashrom {
1170 struct be_cmd_req_hdr hdr;
1171 struct flashrom_params params;
1172 u8 data_buf[32768];
1173 u8 rsvd[4];
1174 } __packed;
1175
1176 /* cmd to read flash crc */
1177 struct be_cmd_read_flash_crc {
1178 struct be_cmd_req_hdr hdr;
1179 struct flashrom_params params;
1180 u8 crc[4];
1181 u8 rsvd[4];
1182 };
1183 /**************** Lancer Firmware Flash ************/
1184 struct amap_lancer_write_obj_context {
1185 u8 write_length[24];
1186 u8 reserved1[7];
1187 u8 eof;
1188 } __packed;
1189
1190 struct lancer_cmd_req_write_object {
1191 struct be_cmd_req_hdr hdr;
1192 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8];
1193 u32 write_offset;
1194 u8 object_name[104];
1195 u32 descriptor_count;
1196 u32 buf_len;
1197 u32 addr_low;
1198 u32 addr_high;
1199 };
1200
1201 #define LANCER_NO_RESET_NEEDED 0x00
1202 #define LANCER_FW_RESET_NEEDED 0x02
1203 struct lancer_cmd_resp_write_object {
1204 u8 opcode;
1205 u8 subsystem;
1206 u8 rsvd1[2];
1207 u8 status;
1208 u8 additional_status;
1209 u8 rsvd2[2];
1210 u32 resp_len;
1211 u32 actual_resp_len;
1212 u32 actual_write_len;
1213 u8 change_status;
1214 u8 rsvd3[3];
1215 };
1216
1217 /************************ Lancer Read FW info **************/
1218 #define LANCER_READ_FILE_CHUNK (32*1024)
1219 #define LANCER_READ_FILE_EOF_MASK 0x80000000
1220
1221 #define LANCER_FW_DUMP_FILE "/dbg/dump.bin"
1222 #define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd"
1223 #define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd"
1224
1225 struct lancer_cmd_req_read_object {
1226 struct be_cmd_req_hdr hdr;
1227 u32 desired_read_len;
1228 u32 read_offset;
1229 u8 object_name[104];
1230 u32 descriptor_count;
1231 u32 buf_len;
1232 u32 addr_low;
1233 u32 addr_high;
1234 };
1235
1236 struct lancer_cmd_resp_read_object {
1237 u8 opcode;
1238 u8 subsystem;
1239 u8 rsvd1[2];
1240 u8 status;
1241 u8 additional_status;
1242 u8 rsvd2[2];
1243 u32 resp_len;
1244 u32 actual_resp_len;
1245 u32 actual_read_len;
1246 u32 eof;
1247 };
1248
1249 /************************ WOL *******************************/
1250 struct be_cmd_req_acpi_wol_magic_config{
1251 struct be_cmd_req_hdr hdr;
1252 u32 rsvd0[145];
1253 u8 magic_mac[6];
1254 u8 rsvd2[2];
1255 } __packed;
1256
1257 struct be_cmd_req_acpi_wol_magic_config_v1 {
1258 struct be_cmd_req_hdr hdr;
1259 u8 rsvd0[2];
1260 u8 query_options;
1261 u8 rsvd1[5];
1262 u32 rsvd2[288];
1263 u8 magic_mac[6];
1264 u8 rsvd3[22];
1265 } __packed;
1266
1267 struct be_cmd_resp_acpi_wol_magic_config_v1 {
1268 struct be_cmd_resp_hdr hdr;
1269 u8 rsvd0[2];
1270 u8 wol_settings;
1271 u8 rsvd1[5];
1272 u32 rsvd2[295];
1273 } __packed;
1274
1275 #define BE_GET_WOL_CAP 2
1276
1277 #define BE_WOL_CAP 0x1
1278 #define BE_PME_D0_CAP 0x8
1279 #define BE_PME_D1_CAP 0x10
1280 #define BE_PME_D2_CAP 0x20
1281 #define BE_PME_D3HOT_CAP 0x40
1282 #define BE_PME_D3COLD_CAP 0x80
1283
1284 /********************** LoopBack test *********************/
1285 struct be_cmd_req_loopback_test {
1286 struct be_cmd_req_hdr hdr;
1287 u32 loopback_type;
1288 u32 num_pkts;
1289 u64 pattern;
1290 u32 src_port;
1291 u32 dest_port;
1292 u32 pkt_size;
1293 };
1294
1295 struct be_cmd_resp_loopback_test {
1296 struct be_cmd_resp_hdr resp_hdr;
1297 u32 status;
1298 u32 num_txfer;
1299 u32 num_rx;
1300 u32 miscomp_off;
1301 u32 ticks_compl;
1302 };
1303
1304 struct be_cmd_req_set_lmode {
1305 struct be_cmd_req_hdr hdr;
1306 u8 src_port;
1307 u8 dest_port;
1308 u8 loopback_type;
1309 u8 loopback_state;
1310 };
1311
1312 struct be_cmd_resp_set_lmode {
1313 struct be_cmd_resp_hdr resp_hdr;
1314 u8 rsvd0[4];
1315 };
1316
1317 /********************** DDR DMA test *********************/
1318 struct be_cmd_req_ddrdma_test {
1319 struct be_cmd_req_hdr hdr;
1320 u64 pattern;
1321 u32 byte_count;
1322 u32 rsvd0;
1323 u8 snd_buff[4096];
1324 u8 rsvd1[4096];
1325 };
1326
1327 struct be_cmd_resp_ddrdma_test {
1328 struct be_cmd_resp_hdr hdr;
1329 u64 pattern;
1330 u32 byte_cnt;
1331 u32 snd_err;
1332 u8 rsvd0[4096];
1333 u8 rcv_buff[4096];
1334 };
1335
1336 /*********************** SEEPROM Read ***********************/
1337
1338 #define BE_READ_SEEPROM_LEN 1024
1339 struct be_cmd_req_seeprom_read {
1340 struct be_cmd_req_hdr hdr;
1341 u8 rsvd0[BE_READ_SEEPROM_LEN];
1342 };
1343
1344 struct be_cmd_resp_seeprom_read {
1345 struct be_cmd_req_hdr hdr;
1346 u8 seeprom_data[BE_READ_SEEPROM_LEN];
1347 };
1348
1349 enum {
1350 PHY_TYPE_CX4_10GB = 0,
1351 PHY_TYPE_XFP_10GB,
1352 PHY_TYPE_SFP_1GB,
1353 PHY_TYPE_SFP_PLUS_10GB,
1354 PHY_TYPE_KR_10GB,
1355 PHY_TYPE_KX4_10GB,
1356 PHY_TYPE_BASET_10GB,
1357 PHY_TYPE_BASET_1GB,
1358 PHY_TYPE_BASEX_1GB,
1359 PHY_TYPE_SGMII,
1360 PHY_TYPE_DISABLED = 255
1361 };
1362
1363 #define BE_SUPPORTED_SPEED_NONE 0
1364 #define BE_SUPPORTED_SPEED_10MBPS 1
1365 #define BE_SUPPORTED_SPEED_100MBPS 2
1366 #define BE_SUPPORTED_SPEED_1GBPS 4
1367 #define BE_SUPPORTED_SPEED_10GBPS 8
1368
1369 #define BE_AN_EN 0x2
1370 #define BE_PAUSE_SYM_EN 0x80
1371
1372 /* MAC speed valid values */
1373 #define SPEED_DEFAULT 0x0
1374 #define SPEED_FORCED_10GB 0x1
1375 #define SPEED_FORCED_1GB 0x2
1376 #define SPEED_AUTONEG_10GB 0x3
1377 #define SPEED_AUTONEG_1GB 0x4
1378 #define SPEED_AUTONEG_100MB 0x5
1379 #define SPEED_AUTONEG_10GB_1GB 0x6
1380 #define SPEED_AUTONEG_10GB_1GB_100MB 0x7
1381 #define SPEED_AUTONEG_1GB_100MB 0x8
1382 #define SPEED_AUTONEG_10MB 0x9
1383 #define SPEED_AUTONEG_1GB_100MB_10MB 0xa
1384 #define SPEED_AUTONEG_100MB_10MB 0xb
1385 #define SPEED_FORCED_100MB 0xc
1386 #define SPEED_FORCED_10MB 0xd
1387
1388 struct be_cmd_req_get_phy_info {
1389 struct be_cmd_req_hdr hdr;
1390 u8 rsvd0[24];
1391 };
1392
1393 struct be_phy_info {
1394 u16 phy_type;
1395 u16 interface_type;
1396 u32 misc_params;
1397 u16 ext_phy_details;
1398 u16 rsvd;
1399 u16 auto_speeds_supported;
1400 u16 fixed_speeds_supported;
1401 u32 future_use[2];
1402 };
1403
1404 struct be_cmd_resp_get_phy_info {
1405 struct be_cmd_req_hdr hdr;
1406 struct be_phy_info phy_info;
1407 };
1408
1409 /*********************** Set QOS ***********************/
1410
1411 #define BE_QOS_BITS_NIC 1
1412
1413 struct be_cmd_req_set_qos {
1414 struct be_cmd_req_hdr hdr;
1415 u32 valid_bits;
1416 u32 max_bps_nic;
1417 u32 rsvd[7];
1418 };
1419
1420 struct be_cmd_resp_set_qos {
1421 struct be_cmd_resp_hdr hdr;
1422 u32 rsvd;
1423 };
1424
1425 /*********************** Controller Attributes ***********************/
1426 struct be_cmd_req_cntl_attribs {
1427 struct be_cmd_req_hdr hdr;
1428 };
1429
1430 struct be_cmd_resp_cntl_attribs {
1431 struct be_cmd_resp_hdr hdr;
1432 struct mgmt_controller_attrib attribs;
1433 };
1434
1435 /*********************** Set driver function ***********************/
1436 #define CAPABILITY_SW_TIMESTAMPS 2
1437 #define CAPABILITY_BE3_NATIVE_ERX_API 4
1438
1439 struct be_cmd_req_set_func_cap {
1440 struct be_cmd_req_hdr hdr;
1441 u32 valid_cap_flags;
1442 u32 cap_flags;
1443 u8 rsvd[212];
1444 };
1445
1446 struct be_cmd_resp_set_func_cap {
1447 struct be_cmd_resp_hdr hdr;
1448 u32 valid_cap_flags;
1449 u32 cap_flags;
1450 u8 rsvd[212];
1451 };
1452
1453 /*********************** Function Privileges ***********************/
1454 enum {
1455 BE_PRIV_DEFAULT = 0x1,
1456 BE_PRIV_LNKQUERY = 0x2,
1457 BE_PRIV_LNKSTATS = 0x4,
1458 BE_PRIV_LNKMGMT = 0x8,
1459 BE_PRIV_LNKDIAG = 0x10,
1460 BE_PRIV_UTILQUERY = 0x20,
1461 BE_PRIV_FILTMGMT = 0x40,
1462 BE_PRIV_IFACEMGMT = 0x80,
1463 BE_PRIV_VHADM = 0x100,
1464 BE_PRIV_DEVCFG = 0x200,
1465 BE_PRIV_DEVSEC = 0x400
1466 };
1467 #define MAX_PRIVILEGES (BE_PRIV_VHADM | BE_PRIV_DEVCFG | \
1468 BE_PRIV_DEVSEC)
1469 #define MIN_PRIVILEGES BE_PRIV_DEFAULT
1470
1471 struct be_cmd_priv_map {
1472 u8 opcode;
1473 u8 subsystem;
1474 u32 priv_mask;
1475 };
1476
1477 struct be_cmd_req_get_fn_privileges {
1478 struct be_cmd_req_hdr hdr;
1479 u32 rsvd;
1480 };
1481
1482 struct be_cmd_resp_get_fn_privileges {
1483 struct be_cmd_resp_hdr hdr;
1484 u32 privilege_mask;
1485 };
1486
1487 struct be_cmd_req_set_fn_privileges {
1488 struct be_cmd_req_hdr hdr;
1489 u32 privileges; /* Used by BE3, SH-R */
1490 u32 privileges_lancer; /* Used by Lancer */
1491 };
1492
1493 /******************** GET/SET_MACLIST **************************/
1494 #define BE_MAX_MAC 64
1495 struct be_cmd_req_get_mac_list {
1496 struct be_cmd_req_hdr hdr;
1497 u8 mac_type;
1498 u8 perm_override;
1499 u16 iface_id;
1500 u32 mac_id;
1501 u32 rsvd[3];
1502 } __packed;
1503
1504 struct get_list_macaddr {
1505 u16 mac_addr_size;
1506 union {
1507 u8 macaddr[6];
1508 struct {
1509 u8 rsvd[2];
1510 u32 mac_id;
1511 } __packed s_mac_id;
1512 } __packed mac_addr_id;
1513 } __packed;
1514
1515 struct be_cmd_resp_get_mac_list {
1516 struct be_cmd_resp_hdr hdr;
1517 struct get_list_macaddr fd_macaddr; /* Factory default mac */
1518 struct get_list_macaddr macid_macaddr; /* soft mac */
1519 u8 true_mac_count;
1520 u8 pseudo_mac_count;
1521 u8 mac_list_size;
1522 u8 rsvd;
1523 /* perm override mac */
1524 struct get_list_macaddr macaddr_list[BE_MAX_MAC];
1525 } __packed;
1526
1527 struct be_cmd_req_set_mac_list {
1528 struct be_cmd_req_hdr hdr;
1529 u8 mac_count;
1530 u8 rsvd1;
1531 u16 rsvd2;
1532 struct macaddr mac[BE_MAX_MAC];
1533 } __packed;
1534
1535 /*********************** HSW Config ***********************/
1536 #define PORT_FWD_TYPE_VEPA 0x3
1537 #define PORT_FWD_TYPE_VEB 0x2
1538
1539 struct amap_set_hsw_context {
1540 u8 interface_id[16];
1541 u8 rsvd0[14];
1542 u8 pvid_valid;
1543 u8 pport;
1544 u8 rsvd1[6];
1545 u8 port_fwd_type[3];
1546 u8 rsvd2[7];
1547 u8 pvid[16];
1548 u8 rsvd3[32];
1549 u8 rsvd4[32];
1550 u8 rsvd5[32];
1551 } __packed;
1552
1553 struct be_cmd_req_set_hsw_config {
1554 struct be_cmd_req_hdr hdr;
1555 u8 context[sizeof(struct amap_set_hsw_context) / 8];
1556 } __packed;
1557
1558 struct be_cmd_resp_set_hsw_config {
1559 struct be_cmd_resp_hdr hdr;
1560 u32 rsvd;
1561 };
1562
1563 struct amap_get_hsw_req_context {
1564 u8 interface_id[16];
1565 u8 rsvd0[14];
1566 u8 pvid_valid;
1567 u8 pport;
1568 } __packed;
1569
1570 struct amap_get_hsw_resp_context {
1571 u8 rsvd0[6];
1572 u8 port_fwd_type[3];
1573 u8 rsvd1[7];
1574 u8 pvid[16];
1575 u8 rsvd2[32];
1576 u8 rsvd3[32];
1577 u8 rsvd4[32];
1578 } __packed;
1579
1580 struct be_cmd_req_get_hsw_config {
1581 struct be_cmd_req_hdr hdr;
1582 u8 context[sizeof(struct amap_get_hsw_req_context) / 8];
1583 } __packed;
1584
1585 struct be_cmd_resp_get_hsw_config {
1586 struct be_cmd_resp_hdr hdr;
1587 u8 context[sizeof(struct amap_get_hsw_resp_context) / 8];
1588 u32 rsvd;
1589 };
1590
1591 /******************* get port names ***************/
1592 struct be_cmd_req_get_port_name {
1593 struct be_cmd_req_hdr hdr;
1594 u32 rsvd0;
1595 };
1596
1597 struct be_cmd_resp_get_port_name {
1598 struct be_cmd_req_hdr hdr;
1599 u8 port_name[4];
1600 };
1601
1602 /*************** HW Stats Get v1 **********************************/
1603 #define BE_TXP_SW_SZ 48
1604 struct be_port_rxf_stats_v1 {
1605 u32 rsvd0[12];
1606 u32 rx_crc_errors;
1607 u32 rx_alignment_symbol_errors;
1608 u32 rx_pause_frames;
1609 u32 rx_priority_pause_frames;
1610 u32 rx_control_frames;
1611 u32 rx_in_range_errors;
1612 u32 rx_out_range_errors;
1613 u32 rx_frame_too_long;
1614 u32 rx_address_filtered;
1615 u32 rx_dropped_too_small;
1616 u32 rx_dropped_too_short;
1617 u32 rx_dropped_header_too_small;
1618 u32 rx_dropped_tcp_length;
1619 u32 rx_dropped_runt;
1620 u32 rsvd1[10];
1621 u32 rx_ip_checksum_errs;
1622 u32 rx_tcp_checksum_errs;
1623 u32 rx_udp_checksum_errs;
1624 u32 rsvd2[7];
1625 u32 rx_switched_unicast_packets;
1626 u32 rx_switched_multicast_packets;
1627 u32 rx_switched_broadcast_packets;
1628 u32 rsvd3[3];
1629 u32 tx_pauseframes;
1630 u32 tx_priority_pauseframes;
1631 u32 tx_controlframes;
1632 u32 rsvd4[10];
1633 u32 rxpp_fifo_overflow_drop;
1634 u32 rx_input_fifo_overflow_drop;
1635 u32 pmem_fifo_overflow_drop;
1636 u32 jabber_events;
1637 u32 rsvd5[3];
1638 };
1639
1640
1641 struct be_rxf_stats_v1 {
1642 struct be_port_rxf_stats_v1 port[4];
1643 u32 rsvd0[2];
1644 u32 rx_drops_no_pbuf;
1645 u32 rx_drops_no_txpb;
1646 u32 rx_drops_no_erx_descr;
1647 u32 rx_drops_no_tpre_descr;
1648 u32 rsvd1[6];
1649 u32 rx_drops_too_many_frags;
1650 u32 rx_drops_invalid_ring;
1651 u32 forwarded_packets;
1652 u32 rx_drops_mtu;
1653 u32 rsvd2[14];
1654 };
1655
1656 struct be_erx_stats_v1 {
1657 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/
1658 u32 rsvd[4];
1659 };
1660
1661 struct be_hw_stats_v1 {
1662 struct be_rxf_stats_v1 rxf;
1663 u32 rsvd0[BE_TXP_SW_SZ];
1664 struct be_erx_stats_v1 erx;
1665 struct be_pmem_stats pmem;
1666 u32 rsvd1[18];
1667 };
1668
1669 struct be_cmd_req_get_stats_v1 {
1670 struct be_cmd_req_hdr hdr;
1671 u8 rsvd[sizeof(struct be_hw_stats_v1)];
1672 };
1673
1674 struct be_cmd_resp_get_stats_v1 {
1675 struct be_cmd_resp_hdr hdr;
1676 struct be_hw_stats_v1 hw_stats;
1677 };
1678
1679 /************** get fat capabilites *******************/
1680 #define MAX_MODULES 27
1681 #define MAX_MODES 4
1682 #define MODE_UART 0
1683 #define FW_LOG_LEVEL_DEFAULT 48
1684 #define FW_LOG_LEVEL_FATAL 64
1685
1686 struct ext_fat_mode {
1687 u8 mode;
1688 u8 rsvd0;
1689 u16 port_mask;
1690 u32 dbg_lvl;
1691 u64 fun_mask;
1692 } __packed;
1693
1694 struct ext_fat_modules {
1695 u8 modules_str[32];
1696 u32 modules_id;
1697 u32 num_modes;
1698 struct ext_fat_mode trace_lvl[MAX_MODES];
1699 } __packed;
1700
1701 struct be_fat_conf_params {
1702 u32 max_log_entries;
1703 u32 log_entry_size;
1704 u8 log_type;
1705 u8 max_log_funs;
1706 u8 max_log_ports;
1707 u8 rsvd0;
1708 u32 supp_modes;
1709 u32 num_modules;
1710 struct ext_fat_modules module[MAX_MODULES];
1711 } __packed;
1712
1713 struct be_cmd_req_get_ext_fat_caps {
1714 struct be_cmd_req_hdr hdr;
1715 u32 parameter_type;
1716 };
1717
1718 struct be_cmd_resp_get_ext_fat_caps {
1719 struct be_cmd_resp_hdr hdr;
1720 struct be_fat_conf_params get_params;
1721 };
1722
1723 struct be_cmd_req_set_ext_fat_caps {
1724 struct be_cmd_req_hdr hdr;
1725 struct be_fat_conf_params set_params;
1726 };
1727
1728 #define RESOURCE_DESC_SIZE_V0 72
1729 #define RESOURCE_DESC_SIZE_V1 88
1730 #define PCIE_RESOURCE_DESC_TYPE_V0 0x40
1731 #define NIC_RESOURCE_DESC_TYPE_V0 0x41
1732 #define PCIE_RESOURCE_DESC_TYPE_V1 0x50
1733 #define NIC_RESOURCE_DESC_TYPE_V1 0x51
1734 #define MAX_RESOURCE_DESC 264
1735
1736 /* QOS unit number */
1737 #define QUN 4
1738 /* Immediate */
1739 #define IMM 6
1740 /* No save */
1741 #define NOSV 7
1742
1743 struct be_res_desc_hdr {
1744 u8 desc_type;
1745 u8 desc_len;
1746 } __packed;
1747
1748 struct be_pcie_res_desc {
1749 struct be_res_desc_hdr hdr;
1750 u8 rsvd0;
1751 u8 flags;
1752 u16 rsvd1;
1753 u8 pf_num;
1754 u8 rsvd2;
1755 u32 rsvd3;
1756 u8 sriov_state;
1757 u8 pf_state;
1758 u8 pf_type;
1759 u8 rsvd4;
1760 u16 num_vfs;
1761 u16 rsvd5;
1762 u32 rsvd6[17];
1763 } __packed;
1764
1765 struct be_nic_res_desc {
1766 struct be_res_desc_hdr hdr;
1767 u8 rsvd1;
1768 u8 flags;
1769 u8 vf_num;
1770 u8 rsvd2;
1771 u8 pf_num;
1772 u8 rsvd3;
1773 u16 unicast_mac_count;
1774 u8 rsvd4[6];
1775 u16 mcc_count;
1776 u16 vlan_count;
1777 u16 mcast_mac_count;
1778 u16 txq_count;
1779 u16 rq_count;
1780 u16 rssq_count;
1781 u16 lro_count;
1782 u16 cq_count;
1783 u16 toe_conn_count;
1784 u16 eq_count;
1785 u32 rsvd5;
1786 u32 cap_flags;
1787 u8 link_param;
1788 u8 rsvd6[3];
1789 u32 bw_min;
1790 u32 bw_max;
1791 u8 acpi_params;
1792 u8 wol_param;
1793 u16 rsvd7;
1794 u32 rsvd8[3];
1795 } __packed;
1796
1797 struct be_cmd_req_get_func_config {
1798 struct be_cmd_req_hdr hdr;
1799 };
1800
1801 struct be_cmd_resp_get_func_config {
1802 struct be_cmd_resp_hdr hdr;
1803 u32 desc_count;
1804 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1];
1805 };
1806
1807 #define ACTIVE_PROFILE_TYPE 0x2
1808 struct be_cmd_req_get_profile_config {
1809 struct be_cmd_req_hdr hdr;
1810 u8 rsvd;
1811 u8 type;
1812 u16 rsvd1;
1813 };
1814
1815 struct be_cmd_resp_get_profile_config {
1816 struct be_cmd_resp_hdr hdr;
1817 u32 desc_count;
1818 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1];
1819 };
1820
1821 struct be_cmd_req_set_profile_config {
1822 struct be_cmd_req_hdr hdr;
1823 u32 rsvd;
1824 u32 desc_count;
1825 struct be_nic_res_desc nic_desc;
1826 };
1827
1828 struct be_cmd_resp_set_profile_config {
1829 struct be_cmd_resp_hdr hdr;
1830 };
1831
1832 struct be_cmd_enable_disable_vf {
1833 struct be_cmd_req_hdr hdr;
1834 u8 enable;
1835 u8 rsvd[3];
1836 };
1837
1838 struct be_cmd_req_intr_set {
1839 struct be_cmd_req_hdr hdr;
1840 u8 intr_enabled;
1841 u8 rsvd[3];
1842 };
1843
1844 static inline bool check_privilege(struct be_adapter *adapter, u32 flags)
1845 {
1846 return flags & adapter->cmd_privileges ? true : false;
1847 }
1848
1849 /************** Get IFACE LIST *******************/
1850 struct be_if_desc {
1851 u32 if_id;
1852 u32 cap_flags;
1853 u32 en_flags;
1854 };
1855
1856 struct be_cmd_req_get_iface_list {
1857 struct be_cmd_req_hdr hdr;
1858 };
1859
1860 struct be_cmd_resp_get_iface_list {
1861 struct be_cmd_req_hdr hdr;
1862 u32 if_cnt;
1863 struct be_if_desc if_desc;
1864 };
1865
1866 extern int be_pci_fnum_get(struct be_adapter *adapter);
1867 extern int be_fw_wait_ready(struct be_adapter *adapter);
1868 extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1869 bool permanent, u32 if_handle, u32 pmac_id);
1870 extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1871 u32 if_id, u32 *pmac_id, u32 domain);
1872 extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id,
1873 int pmac_id, u32 domain);
1874 extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
1875 u32 en_flags, u32 *if_handle, u32 domain);
1876 extern int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle,
1877 u32 domain);
1878 extern int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo);
1879 extern int be_cmd_cq_create(struct be_adapter *adapter,
1880 struct be_queue_info *cq, struct be_queue_info *eq,
1881 bool no_delay, int num_cqe_dma_coalesce);
1882 extern int be_cmd_mccq_create(struct be_adapter *adapter,
1883 struct be_queue_info *mccq,
1884 struct be_queue_info *cq);
1885 extern int be_cmd_txq_create(struct be_adapter *adapter,
1886 struct be_tx_obj *txo);
1887 extern int be_cmd_rxq_create(struct be_adapter *adapter,
1888 struct be_queue_info *rxq, u16 cq_id,
1889 u16 frag_size, u32 if_id, u32 rss, u8 *rss_id);
1890 extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1891 int type);
1892 extern int be_cmd_rxq_destroy(struct be_adapter *adapter,
1893 struct be_queue_info *q);
1894 extern int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1895 u8 *link_status, u32 dom);
1896 extern int be_cmd_reset(struct be_adapter *adapter);
1897 extern int be_cmd_get_stats(struct be_adapter *adapter,
1898 struct be_dma_mem *nonemb_cmd);
1899 extern int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1900 struct be_dma_mem *nonemb_cmd);
1901 extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1902 char *fw_on_flash);
1903
1904 extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
1905 extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
1906 u16 *vtag_array, u32 num, bool untagged,
1907 bool promiscuous);
1908 extern int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status);
1909 extern int be_cmd_set_flow_control(struct be_adapter *adapter,
1910 u32 tx_fc, u32 rx_fc);
1911 extern int be_cmd_get_flow_control(struct be_adapter *adapter,
1912 u32 *tx_fc, u32 *rx_fc);
1913 extern int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1914 u32 *function_mode, u32 *function_caps, u16 *asic_rev);
1915 extern int be_cmd_reset_function(struct be_adapter *adapter);
1916 extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1917 u32 rss_hash_opts, u16 table_size);
1918 extern int be_process_mcc(struct be_adapter *adapter);
1919 extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
1920 u8 port_num, u8 beacon, u8 status, u8 state);
1921 extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
1922 u8 port_num, u32 *state);
1923 extern int be_cmd_write_flashrom(struct be_adapter *adapter,
1924 struct be_dma_mem *cmd, u32 flash_oper,
1925 u32 flash_opcode, u32 buf_size);
1926 extern int lancer_cmd_write_object(struct be_adapter *adapter,
1927 struct be_dma_mem *cmd,
1928 u32 data_size, u32 data_offset,
1929 const char *obj_name,
1930 u32 *data_written, u8 *change_status,
1931 u8 *addn_status);
1932 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1933 u32 data_size, u32 data_offset, const char *obj_name,
1934 u32 *data_read, u32 *eof, u8 *addn_status);
1935 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1936 int offset);
1937 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1938 struct be_dma_mem *nonemb_cmd);
1939 extern int be_cmd_fw_init(struct be_adapter *adapter);
1940 extern int be_cmd_fw_clean(struct be_adapter *adapter);
1941 extern void be_async_mcc_enable(struct be_adapter *adapter);
1942 extern void be_async_mcc_disable(struct be_adapter *adapter);
1943 extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1944 u32 loopback_type, u32 pkt_size,
1945 u32 num_pkts, u64 pattern);
1946 extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1947 u32 byte_cnt, struct be_dma_mem *cmd);
1948 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1949 struct be_dma_mem *nonemb_cmd);
1950 extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1951 u8 loopback_type, u8 enable);
1952 extern int be_cmd_get_phy_info(struct be_adapter *adapter);
1953 extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
1954 extern void be_detect_error(struct be_adapter *adapter);
1955 extern int be_cmd_get_die_temperature(struct be_adapter *adapter);
1956 extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
1957 extern int be_cmd_req_native_mode(struct be_adapter *adapter);
1958 extern int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size);
1959 extern void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf);
1960 extern int be_cmd_get_fn_privileges(struct be_adapter *adapter,
1961 u32 *privilege, u32 domain);
1962 extern int be_cmd_set_fn_privileges(struct be_adapter *adapter,
1963 u32 privileges, u32 vf_num);
1964 extern int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
1965 bool *pmac_id_active, u32 *pmac_id,
1966 u8 domain);
1967 extern int be_cmd_get_active_mac(struct be_adapter *adapter, u32 pmac_id,
1968 u8 *mac);
1969 extern int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac);
1970 extern int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
1971 u8 mac_count, u32 domain);
1972 extern int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id,
1973 u32 dom);
1974 extern int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
1975 u32 domain, u16 intf_id, u16 hsw_mode);
1976 extern int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
1977 u32 domain, u16 intf_id, u8 *mode);
1978 extern int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter);
1979 extern int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
1980 struct be_dma_mem *cmd);
1981 extern int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
1982 struct be_dma_mem *cmd,
1983 struct be_fat_conf_params *cfgs);
1984 extern int lancer_wait_ready(struct be_adapter *adapter);
1985 extern int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask);
1986 extern int lancer_initiate_dump(struct be_adapter *adapter);
1987 extern bool dump_present(struct be_adapter *adapter);
1988 extern int lancer_test_and_set_rdy_state(struct be_adapter *adapter);
1989 extern int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name);
1990 int be_cmd_get_func_config(struct be_adapter *adapter,
1991 struct be_resources *res);
1992 int be_cmd_get_profile_config(struct be_adapter *adapter,
1993 struct be_resources *res, u8 domain);
1994 extern int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps,
1995 u8 domain);
1996 extern int be_cmd_get_if_id(struct be_adapter *adapter,
1997 struct be_vf_cfg *vf_cfg, int vf_num);
1998 extern int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain);
1999 extern int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable);
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