drivers/net/ethernet/emulex/benet/be_cmds.h

   1 /*
   2  * Copyright (C) 2005 - 2011 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 /*
  19  * The driver sends configuration and managements command requests to the
  20  * firmware in the BE. These requests are communicated to the processor
  21  * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
  22  * WRB inside a MAILBOX.
  23  * The commands are serviced by the ARM processor in the BladeEngine's MPU.
  24  */
  25
  26 struct be_sge {
  27         u32 pa_lo;
  28         u32 pa_hi;
  29         u32 len;
  30 };
  31
  32 #define MCC_WRB_EMBEDDED_MASK   1       /* bit 0 of dword 0*/
  33 #define MCC_WRB_SGE_CNT_SHIFT   3       /* bits 3 - 7 of dword 0 */
  34 #define MCC_WRB_SGE_CNT_MASK    0x1F    /* bits 3 - 7 of dword 0 */
  35 struct be_mcc_wrb {
  36         u32 embedded;           /* dword 0 */
  37         u32 payload_length;     /* dword 1 */
  38         u32 tag0;               /* dword 2 */
  39         u32 tag1;               /* dword 3 */
  40         u32 rsvd;               /* dword 4 */
  41         union {
  42                 u8 embedded_payload[236]; /* used by embedded cmds */
  43                 struct be_sge sgl[19];    /* used by non-embedded cmds */
  44         } payload;
  45 };
  46
  47 #define CQE_FLAGS_VALID_MASK            (1 << 31)
  48 #define CQE_FLAGS_ASYNC_MASK            (1 << 30)
  49 #define CQE_FLAGS_COMPLETED_MASK        (1 << 28)
  50 #define CQE_FLAGS_CONSUMED_MASK         (1 << 27)
  51
  52 /* Completion Status */
  53 enum {
  54         MCC_STATUS_SUCCESS = 0,
  55         MCC_STATUS_FAILED = 1,
  56         MCC_STATUS_ILLEGAL_REQUEST = 2,
  57         MCC_STATUS_ILLEGAL_FIELD = 3,
  58         MCC_STATUS_INSUFFICIENT_BUFFER = 4,
  59         MCC_STATUS_UNAUTHORIZED_REQUEST = 5,
  60         MCC_STATUS_NOT_SUPPORTED = 66
  61 };
  62
  63 #define CQE_STATUS_COMPL_MASK           0xFFFF
  64 #define CQE_STATUS_COMPL_SHIFT          0       /* bits 0 - 15 */
  65 #define CQE_STATUS_EXTD_MASK            0xFFFF
  66 #define CQE_STATUS_EXTD_SHIFT           16      /* bits 16 - 31 */
  67
  68 struct be_mcc_compl {
  69         u32 status;             /* dword 0 */
  70         u32 tag0;               /* dword 1 */
  71         u32 tag1;               /* dword 2 */
  72         u32 flags;              /* dword 3 */
  73 };
  74
  75 /* When the async bit of mcc_compl is set, the last 4 bytes of
  76  * mcc_compl is interpreted as follows:
  77  */
  78 #define ASYNC_TRAILER_EVENT_CODE_SHIFT  8       /* bits 8 - 15 */
  79 #define ASYNC_TRAILER_EVENT_CODE_MASK   0xFF
  80 #define ASYNC_TRAILER_EVENT_TYPE_SHIFT  16
  81 #define ASYNC_TRAILER_EVENT_TYPE_MASK   0xFF
  82 #define ASYNC_EVENT_CODE_LINK_STATE     0x1
  83 #define ASYNC_EVENT_CODE_GRP_5          0x5
  84 #define ASYNC_EVENT_QOS_SPEED           0x1
  85 #define ASYNC_EVENT_COS_PRIORITY        0x2
  86 #define ASYNC_EVENT_PVID_STATE          0x3
  87 struct be_async_event_trailer {
  88         u32 code;
  89 };
  90
  91 enum {
  92         LINK_DOWN       = 0x0,
  93         LINK_UP         = 0x1
  94 };
  95 #define LINK_STATUS_MASK                        0x1
  96
  97 /* When the event code of an async trailer is link-state, the mcc_compl
  98  * must be interpreted as follows
  99  */
 100 struct be_async_event_link_state {
 101         u8 physical_port;
 102         u8 port_link_status;
 103         u8 port_duplex;
 104         u8 port_speed;
 105         u8 port_fault;
 106         u8 rsvd0[7];
 107         struct be_async_event_trailer trailer;
 108 } __packed;
 109
 110 /* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
 111  * the mcc_compl must be interpreted as follows
 112  */
 113 struct be_async_event_grp5_qos_link_speed {
 114         u8 physical_port;
 115         u8 rsvd[5];
 116         u16 qos_link_speed;
 117         u32 event_tag;
 118         struct be_async_event_trailer trailer;
 119 } __packed;
 120
 121 /* When the event code of an async trailer is GRP5 and event type is
 122  * CoS-Priority, the mcc_compl must be interpreted as follows
 123  */
 124 struct be_async_event_grp5_cos_priority {
 125         u8 physical_port;
 126         u8 available_priority_bmap;
 127         u8 reco_default_priority;
 128         u8 valid;
 129         u8 rsvd0;
 130         u8 event_tag;
 131         struct be_async_event_trailer trailer;
 132 } __packed;
 133
 134 /* When the event code of an async trailer is GRP5 and event type is
 135  * PVID state, the mcc_compl must be interpreted as follows
 136  */
 137 struct be_async_event_grp5_pvid_state {
 138         u8 enabled;
 139         u8 rsvd0;
 140         u16 tag;
 141         u32 event_tag;
 142         u32 rsvd1;
 143         struct be_async_event_trailer trailer;
 144 } __packed;
 145
 146 struct be_mcc_mailbox {
 147         struct be_mcc_wrb wrb;
 148         struct be_mcc_compl compl;
 149 };
 150
 151 #define CMD_SUBSYSTEM_COMMON    0x1
 152 #define CMD_SUBSYSTEM_ETH       0x3
 153 #define CMD_SUBSYSTEM_LOWLEVEL  0xb
 154
 155 #define OPCODE_COMMON_NTWK_MAC_QUERY                    1
 156 #define OPCODE_COMMON_NTWK_MAC_SET                      2
 157 #define OPCODE_COMMON_NTWK_MULTICAST_SET                3
 158 #define OPCODE_COMMON_NTWK_VLAN_CONFIG                  4
 159 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY            5
 160 #define OPCODE_COMMON_READ_FLASHROM                     6
 161 #define OPCODE_COMMON_WRITE_FLASHROM                    7
 162 #define OPCODE_COMMON_CQ_CREATE                         12
 163 #define OPCODE_COMMON_EQ_CREATE                         13
 164 #define OPCODE_COMMON_MCC_CREATE                        21
 165 #define OPCODE_COMMON_SET_QOS                           28
 166 #define OPCODE_COMMON_MCC_CREATE_EXT                    90
 167 #define OPCODE_COMMON_SEEPROM_READ                      30
 168 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES               32
 169 #define OPCODE_COMMON_NTWK_RX_FILTER                    34
 170 #define OPCODE_COMMON_GET_FW_VERSION                    35
 171 #define OPCODE_COMMON_SET_FLOW_CONTROL                  36
 172 #define OPCODE_COMMON_GET_FLOW_CONTROL                  37
 173 #define OPCODE_COMMON_SET_FRAME_SIZE                    39
 174 #define OPCODE_COMMON_MODIFY_EQ_DELAY                   41
 175 #define OPCODE_COMMON_FIRMWARE_CONFIG                   42
 176 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE             50
 177 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY            51
 178 #define OPCODE_COMMON_MCC_DESTROY                       53
 179 #define OPCODE_COMMON_CQ_DESTROY                        54
 180 #define OPCODE_COMMON_EQ_DESTROY                        55
 181 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG             58
 182 #define OPCODE_COMMON_NTWK_PMAC_ADD                     59
 183 #define OPCODE_COMMON_NTWK_PMAC_DEL                     60
 184 #define OPCODE_COMMON_FUNCTION_RESET                    61
 185 #define OPCODE_COMMON_MANAGE_FAT                        68
 186 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON             69
 187 #define OPCODE_COMMON_GET_BEACON_STATE                  70
 188 #define OPCODE_COMMON_READ_TRANSRECV_DATA               73
 189 #define OPCODE_COMMON_GET_PHY_DETAILS                   102
 190 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP           103
 191 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES    121
 192 #define OPCODE_COMMON_GET_MAC_LIST                      147
 193 #define OPCODE_COMMON_SET_MAC_LIST                      148
 194 #define OPCODE_COMMON_GET_HSW_CONFIG                    152
 195 #define OPCODE_COMMON_SET_HSW_CONFIG                    153
 196 #define OPCODE_COMMON_READ_OBJECT                       171
 197 #define OPCODE_COMMON_WRITE_OBJECT                      172
 198
 199 #define OPCODE_ETH_RSS_CONFIG                           1
 200 #define OPCODE_ETH_ACPI_CONFIG                          2
 201 #define OPCODE_ETH_PROMISCUOUS                          3
 202 #define OPCODE_ETH_GET_STATISTICS                       4
 203 #define OPCODE_ETH_TX_CREATE                            7
 204 #define OPCODE_ETH_RX_CREATE                            8
 205 #define OPCODE_ETH_TX_DESTROY                           9
 206 #define OPCODE_ETH_RX_DESTROY                           10
 207 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG                12
 208 #define OPCODE_ETH_GET_PPORT_STATS                      18
 209
 210 #define OPCODE_LOWLEVEL_HOST_DDR_DMA                    17
 211 #define OPCODE_LOWLEVEL_LOOPBACK_TEST                   18
 212 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE               19
 213
 214 struct be_cmd_req_hdr {
 215         u8 opcode;              /* dword 0 */
 216         u8 subsystem;           /* dword 0 */
 217         u8 port_number;         /* dword 0 */
 218         u8 domain;              /* dword 0 */
 219         u32 timeout;            /* dword 1 */
 220         u32 request_length;     /* dword 2 */
 221         u8 version;             /* dword 3 */
 222         u8 rsvd[3];             /* dword 3 */
 223 };
 224
 225 #define RESP_HDR_INFO_OPCODE_SHIFT      0       /* bits 0 - 7 */
 226 #define RESP_HDR_INFO_SUBSYS_SHIFT      8       /* bits 8 - 15 */
 227 struct be_cmd_resp_hdr {
 228         u32 info;               /* dword 0 */
 229         u32 status;             /* dword 1 */
 230         u32 response_length;    /* dword 2 */
 231         u32 actual_resp_len;    /* dword 3 */
 232 };
 233
 234 struct phys_addr {
 235         u32 lo;
 236         u32 hi;
 237 };
 238
 239 /**************************
 240  * BE Command definitions *
 241  **************************/
 242
 243 /* Pseudo amap definition in which each bit of the actual structure is defined
 244  * as a byte: used to calculate offset/shift/mask of each field */
 245 struct amap_eq_context {
 246         u8 cidx[13];            /* dword 0*/
 247         u8 rsvd0[3];            /* dword 0*/
 248         u8 epidx[13];           /* dword 0*/
 249         u8 valid;               /* dword 0*/
 250         u8 rsvd1;               /* dword 0*/
 251         u8 size;                /* dword 0*/
 252         u8 pidx[13];            /* dword 1*/
 253         u8 rsvd2[3];            /* dword 1*/
 254         u8 pd[10];              /* dword 1*/
 255         u8 count[3];            /* dword 1*/
 256         u8 solevent;            /* dword 1*/
 257         u8 stalled;             /* dword 1*/
 258         u8 armed;               /* dword 1*/
 259         u8 rsvd3[4];            /* dword 2*/
 260         u8 func[8];             /* dword 2*/
 261         u8 rsvd4;               /* dword 2*/
 262         u8 delaymult[10];       /* dword 2*/
 263         u8 rsvd5[2];            /* dword 2*/
 264         u8 phase[2];            /* dword 2*/
 265         u8 nodelay;             /* dword 2*/
 266         u8 rsvd6[4];            /* dword 2*/
 267         u8 rsvd7[32];           /* dword 3*/
 268 } __packed;
 269
 270 struct be_cmd_req_eq_create {
 271         struct be_cmd_req_hdr hdr;
 272         u16 num_pages;          /* sword */
 273         u16 rsvd0;              /* sword */
 274         u8 context[sizeof(struct amap_eq_context) / 8];
 275         struct phys_addr pages[8];
 276 } __packed;
 277
 278 struct be_cmd_resp_eq_create {
 279         struct be_cmd_resp_hdr resp_hdr;
 280         u16 eq_id;              /* sword */
 281         u16 rsvd0;              /* sword */
 282 } __packed;
 283
 284 /******************** Mac query ***************************/
 285 enum {
 286         MAC_ADDRESS_TYPE_STORAGE = 0x0,
 287         MAC_ADDRESS_TYPE_NETWORK = 0x1,
 288         MAC_ADDRESS_TYPE_PD = 0x2,
 289         MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
 290 };
 291
 292 struct mac_addr {
 293         u16 size_of_struct;
 294         u8 addr[ETH_ALEN];
 295 } __packed;
 296
 297 struct be_cmd_req_mac_query {
 298         struct be_cmd_req_hdr hdr;
 299         u8 type;
 300         u8 permanent;
 301         u16 if_id;
 302         u32 pmac_id;
 303 } __packed;
 304
 305 struct be_cmd_resp_mac_query {
 306         struct be_cmd_resp_hdr hdr;
 307         struct mac_addr mac;
 308 };
 309
 310 /******************** PMac Add ***************************/
 311 struct be_cmd_req_pmac_add {
 312         struct be_cmd_req_hdr hdr;
 313         u32 if_id;
 314         u8 mac_address[ETH_ALEN];
 315         u8 rsvd0[2];
 316 } __packed;
 317
 318 struct be_cmd_resp_pmac_add {
 319         struct be_cmd_resp_hdr hdr;
 320         u32 pmac_id;
 321 };
 322
 323 /******************** PMac Del ***************************/
 324 struct be_cmd_req_pmac_del {
 325         struct be_cmd_req_hdr hdr;
 326         u32 if_id;
 327         u32 pmac_id;
 328 };
 329
 330 /******************** Create CQ ***************************/
 331 /* Pseudo amap definition in which each bit of the actual structure is defined
 332  * as a byte: used to calculate offset/shift/mask of each field */
 333 struct amap_cq_context_be {
 334         u8 cidx[11];            /* dword 0*/
 335         u8 rsvd0;               /* dword 0*/
 336         u8 coalescwm[2];        /* dword 0*/
 337         u8 nodelay;             /* dword 0*/
 338         u8 epidx[11];           /* dword 0*/
 339         u8 rsvd1;               /* dword 0*/
 340         u8 count[2];            /* dword 0*/
 341         u8 valid;               /* dword 0*/
 342         u8 solevent;            /* dword 0*/
 343         u8 eventable;           /* dword 0*/
 344         u8 pidx[11];            /* dword 1*/
 345         u8 rsvd2;               /* dword 1*/
 346         u8 pd[10];              /* dword 1*/
 347         u8 eqid[8];             /* dword 1*/
 348         u8 stalled;             /* dword 1*/
 349         u8 armed;               /* dword 1*/
 350         u8 rsvd3[4];            /* dword 2*/
 351         u8 func[8];             /* dword 2*/
 352         u8 rsvd4[20];           /* dword 2*/
 353         u8 rsvd5[32];           /* dword 3*/
 354 } __packed;
 355
 356 struct amap_cq_context_lancer {
 357         u8 rsvd0[12];           /* dword 0*/
 358         u8 coalescwm[2];        /* dword 0*/
 359         u8 nodelay;             /* dword 0*/
 360         u8 rsvd1[12];           /* dword 0*/
 361         u8 count[2];            /* dword 0*/
 362         u8 valid;               /* dword 0*/
 363         u8 rsvd2;               /* dword 0*/
 364         u8 eventable;           /* dword 0*/
 365         u8 eqid[16];            /* dword 1*/
 366         u8 rsvd3[15];           /* dword 1*/
 367         u8 armed;               /* dword 1*/
 368         u8 rsvd4[32];           /* dword 2*/
 369         u8 rsvd5[32];           /* dword 3*/
 370 } __packed;
 371
 372 struct be_cmd_req_cq_create {
 373         struct be_cmd_req_hdr hdr;
 374         u16 num_pages;
 375         u8 page_size;
 376         u8 rsvd0;
 377         u8 context[sizeof(struct amap_cq_context_be) / 8];
 378         struct phys_addr pages[8];
 379 } __packed;
 380
 381
 382 struct be_cmd_resp_cq_create {
 383         struct be_cmd_resp_hdr hdr;
 384         u16 cq_id;
 385         u16 rsvd0;
 386 } __packed;
 387
 388 struct be_cmd_req_get_fat {
 389         struct be_cmd_req_hdr hdr;
 390         u32 fat_operation;
 391         u32 read_log_offset;
 392         u32 read_log_length;
 393         u32 data_buffer_size;
 394         u32 data_buffer[1];
 395 } __packed;
 396
 397 struct be_cmd_resp_get_fat {
 398         struct be_cmd_resp_hdr hdr;
 399         u32 log_size;
 400         u32 read_log_length;
 401         u32 rsvd[2];
 402         u32 data_buffer[1];
 403 } __packed;
 404
 405
 406 /******************** Create MCCQ ***************************/
 407 /* Pseudo amap definition in which each bit of the actual structure is defined
 408  * as a byte: used to calculate offset/shift/mask of each field */
 409 struct amap_mcc_context_be {
 410         u8 con_index[14];
 411         u8 rsvd0[2];
 412         u8 ring_size[4];
 413         u8 fetch_wrb;
 414         u8 fetch_r2t;
 415         u8 cq_id[10];
 416         u8 prod_index[14];
 417         u8 fid[8];
 418         u8 pdid[9];
 419         u8 valid;
 420         u8 rsvd1[32];
 421         u8 rsvd2[32];
 422 } __packed;
 423
 424 struct amap_mcc_context_lancer {
 425         u8 async_cq_id[16];
 426         u8 ring_size[4];
 427         u8 rsvd0[12];
 428         u8 rsvd1[31];
 429         u8 valid;
 430         u8 async_cq_valid[1];
 431         u8 rsvd2[31];
 432         u8 rsvd3[32];
 433 } __packed;
 434
 435 struct be_cmd_req_mcc_create {
 436         struct be_cmd_req_hdr hdr;
 437         u16 num_pages;
 438         u16 cq_id;
 439         u8 context[sizeof(struct amap_mcc_context_be) / 8];
 440         struct phys_addr pages[8];
 441 } __packed;
 442
 443 struct be_cmd_req_mcc_ext_create {
 444         struct be_cmd_req_hdr hdr;
 445         u16 num_pages;
 446         u16 cq_id;
 447         u32 async_event_bitmap[1];
 448         u8 context[sizeof(struct amap_mcc_context_be) / 8];
 449         struct phys_addr pages[8];
 450 } __packed;
 451
 452 struct be_cmd_resp_mcc_create {
 453         struct be_cmd_resp_hdr hdr;
 454         u16 id;
 455         u16 rsvd0;
 456 } __packed;
 457
 458 /******************** Create TxQ ***************************/
 459 #define BE_ETH_TX_RING_TYPE_STANDARD            2
 460 #define BE_ULP1_NUM                             1
 461
 462 /* Pseudo amap definition in which each bit of the actual structure is defined
 463  * as a byte: used to calculate offset/shift/mask of each field */
 464 struct amap_tx_context {
 465         u8 if_id[16];           /* dword 0 */
 466         u8 tx_ring_size[4];     /* dword 0 */
 467         u8 rsvd1[26];           /* dword 0 */
 468         u8 pci_func_id[8];      /* dword 1 */
 469         u8 rsvd2[9];            /* dword 1 */
 470         u8 ctx_valid;           /* dword 1 */
 471         u8 cq_id_send[16];      /* dword 2 */
 472         u8 rsvd3[16];           /* dword 2 */
 473         u8 rsvd4[32];           /* dword 3 */
 474         u8 rsvd5[32];           /* dword 4 */
 475         u8 rsvd6[32];           /* dword 5 */
 476         u8 rsvd7[32];           /* dword 6 */
 477         u8 rsvd8[32];           /* dword 7 */
 478         u8 rsvd9[32];           /* dword 8 */
 479         u8 rsvd10[32];          /* dword 9 */
 480         u8 rsvd11[32];          /* dword 10 */
 481         u8 rsvd12[32];          /* dword 11 */
 482         u8 rsvd13[32];          /* dword 12 */
 483         u8 rsvd14[32];          /* dword 13 */
 484         u8 rsvd15[32];          /* dword 14 */
 485         u8 rsvd16[32];          /* dword 15 */
 486 } __packed;
 487
 488 struct be_cmd_req_eth_tx_create {
 489         struct be_cmd_req_hdr hdr;
 490         u8 num_pages;
 491         u8 ulp_num;
 492         u8 type;
 493         u8 bound_port;
 494         u8 context[sizeof(struct amap_tx_context) / 8];
 495         struct phys_addr pages[8];
 496 } __packed;
 497
 498 struct be_cmd_resp_eth_tx_create {
 499         struct be_cmd_resp_hdr hdr;
 500         u16 cid;
 501         u16 rsvd0;
 502 } __packed;
 503
 504 /******************** Create RxQ ***************************/
 505 struct be_cmd_req_eth_rx_create {
 506         struct be_cmd_req_hdr hdr;
 507         u16 cq_id;
 508         u8 frag_size;
 509         u8 num_pages;
 510         struct phys_addr pages[2];
 511         u32 interface_id;
 512         u16 max_frame_size;
 513         u16 rsvd0;
 514         u32 rss_queue;
 515 } __packed;
 516
 517 struct be_cmd_resp_eth_rx_create {
 518         struct be_cmd_resp_hdr hdr;
 519         u16 id;
 520         u8 rss_id;
 521         u8 rsvd0;
 522 } __packed;
 523
 524 /******************** Q Destroy  ***************************/
 525 /* Type of Queue to be destroyed */
 526 enum {
 527         QTYPE_EQ = 1,
 528         QTYPE_CQ,
 529         QTYPE_TXQ,
 530         QTYPE_RXQ,
 531         QTYPE_MCCQ
 532 };
 533
 534 struct be_cmd_req_q_destroy {
 535         struct be_cmd_req_hdr hdr;
 536         u16 id;
 537         u16 bypass_flush;       /* valid only for rx q destroy */
 538 } __packed;
 539
 540 /************ I/f Create (it's actually I/f Config Create)**********/
 541
 542 /* Capability flags for the i/f */
 543 enum be_if_flags {
 544         BE_IF_FLAGS_RSS = 0x4,
 545         BE_IF_FLAGS_PROMISCUOUS = 0x8,
 546         BE_IF_FLAGS_BROADCAST = 0x10,
 547         BE_IF_FLAGS_UNTAGGED = 0x20,
 548         BE_IF_FLAGS_ULP = 0x40,
 549         BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
 550         BE_IF_FLAGS_VLAN = 0x100,
 551         BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
 552         BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
 553         BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
 554         BE_IF_FLAGS_MULTICAST = 0x1000
 555 };
 556
 557 /* An RX interface is an object with one or more MAC addresses and
 558  * filtering capabilities. */
 559 struct be_cmd_req_if_create {
 560         struct be_cmd_req_hdr hdr;
 561         u32 version;            /* ignore currently */
 562         u32 capability_flags;
 563         u32 enable_flags;
 564         u8 mac_addr[ETH_ALEN];
 565         u8 rsvd0;
 566         u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
 567         u32 vlan_tag;    /* not used currently */
 568 } __packed;
 569
 570 struct be_cmd_resp_if_create {
 571         struct be_cmd_resp_hdr hdr;
 572         u32 interface_id;
 573         u32 pmac_id;
 574 };
 575
 576 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
 577 struct be_cmd_req_if_destroy {
 578         struct be_cmd_req_hdr hdr;
 579         u32 interface_id;
 580 };
 581
 582 /*************** HW Stats Get **********************************/
 583 struct be_port_rxf_stats_v0 {
 584         u32 rx_bytes_lsd;       /* dword 0*/
 585         u32 rx_bytes_msd;       /* dword 1*/
 586         u32 rx_total_frames;    /* dword 2*/
 587         u32 rx_unicast_frames;  /* dword 3*/
 588         u32 rx_multicast_frames;        /* dword 4*/
 589         u32 rx_broadcast_frames;        /* dword 5*/
 590         u32 rx_crc_errors;      /* dword 6*/
 591         u32 rx_alignment_symbol_errors; /* dword 7*/
 592         u32 rx_pause_frames;    /* dword 8*/
 593         u32 rx_control_frames;  /* dword 9*/
 594         u32 rx_in_range_errors; /* dword 10*/
 595         u32 rx_out_range_errors;        /* dword 11*/
 596         u32 rx_frame_too_long;  /* dword 12*/
 597         u32 rx_address_mismatch_drops;  /* dword 13*/
 598         u32 rx_vlan_mismatch_drops;     /* dword 14*/
 599         u32 rx_dropped_too_small;       /* dword 15*/
 600         u32 rx_dropped_too_short;       /* dword 16*/
 601         u32 rx_dropped_header_too_small;        /* dword 17*/
 602         u32 rx_dropped_tcp_length;      /* dword 18*/
 603         u32 rx_dropped_runt;    /* dword 19*/
 604         u32 rx_64_byte_packets; /* dword 20*/
 605         u32 rx_65_127_byte_packets;     /* dword 21*/
 606         u32 rx_128_256_byte_packets;    /* dword 22*/
 607         u32 rx_256_511_byte_packets;    /* dword 23*/
 608         u32 rx_512_1023_byte_packets;   /* dword 24*/
 609         u32 rx_1024_1518_byte_packets;  /* dword 25*/
 610         u32 rx_1519_2047_byte_packets;  /* dword 26*/
 611         u32 rx_2048_4095_byte_packets;  /* dword 27*/
 612         u32 rx_4096_8191_byte_packets;  /* dword 28*/
 613         u32 rx_8192_9216_byte_packets;  /* dword 29*/
 614         u32 rx_ip_checksum_errs;        /* dword 30*/
 615         u32 rx_tcp_checksum_errs;       /* dword 31*/
 616         u32 rx_udp_checksum_errs;       /* dword 32*/
 617         u32 rx_non_rss_packets; /* dword 33*/
 618         u32 rx_ipv4_packets;    /* dword 34*/
 619         u32 rx_ipv6_packets;    /* dword 35*/
 620         u32 rx_ipv4_bytes_lsd;  /* dword 36*/
 621         u32 rx_ipv4_bytes_msd;  /* dword 37*/
 622         u32 rx_ipv6_bytes_lsd;  /* dword 38*/
 623         u32 rx_ipv6_bytes_msd;  /* dword 39*/
 624         u32 rx_chute1_packets;  /* dword 40*/
 625         u32 rx_chute2_packets;  /* dword 41*/
 626         u32 rx_chute3_packets;  /* dword 42*/
 627         u32 rx_management_packets;      /* dword 43*/
 628         u32 rx_switched_unicast_packets;        /* dword 44*/
 629         u32 rx_switched_multicast_packets;      /* dword 45*/
 630         u32 rx_switched_broadcast_packets;      /* dword 46*/
 631         u32 tx_bytes_lsd;       /* dword 47*/
 632         u32 tx_bytes_msd;       /* dword 48*/
 633         u32 tx_unicastframes;   /* dword 49*/
 634         u32 tx_multicastframes; /* dword 50*/
 635         u32 tx_broadcastframes; /* dword 51*/
 636         u32 tx_pauseframes;     /* dword 52*/
 637         u32 tx_controlframes;   /* dword 53*/
 638         u32 tx_64_byte_packets; /* dword 54*/
 639         u32 tx_65_127_byte_packets;     /* dword 55*/
 640         u32 tx_128_256_byte_packets;    /* dword 56*/
 641         u32 tx_256_511_byte_packets;    /* dword 57*/
 642         u32 tx_512_1023_byte_packets;   /* dword 58*/
 643         u32 tx_1024_1518_byte_packets;  /* dword 59*/
 644         u32 tx_1519_2047_byte_packets;  /* dword 60*/
 645         u32 tx_2048_4095_byte_packets;  /* dword 61*/
 646         u32 tx_4096_8191_byte_packets;  /* dword 62*/
 647         u32 tx_8192_9216_byte_packets;  /* dword 63*/
 648         u32 rx_fifo_overflow;   /* dword 64*/
 649         u32 rx_input_fifo_overflow;     /* dword 65*/
 650 };
 651
 652 struct be_rxf_stats_v0 {
 653         struct be_port_rxf_stats_v0 port[2];
 654         u32 rx_drops_no_pbuf;   /* dword 132*/
 655         u32 rx_drops_no_txpb;   /* dword 133*/
 656         u32 rx_drops_no_erx_descr;      /* dword 134*/
 657         u32 rx_drops_no_tpre_descr;     /* dword 135*/
 658         u32 management_rx_port_packets; /* dword 136*/
 659         u32 management_rx_port_bytes;   /* dword 137*/
 660         u32 management_rx_port_pause_frames;    /* dword 138*/
 661         u32 management_rx_port_errors;  /* dword 139*/
 662         u32 management_tx_port_packets; /* dword 140*/
 663         u32 management_tx_port_bytes;   /* dword 141*/
 664         u32 management_tx_port_pause;   /* dword 142*/
 665         u32 management_rx_port_rxfifo_overflow; /* dword 143*/
 666         u32 rx_drops_too_many_frags;    /* dword 144*/
 667         u32 rx_drops_invalid_ring;      /* dword 145*/
 668         u32 forwarded_packets;  /* dword 146*/
 669         u32 rx_drops_mtu;       /* dword 147*/
 670         u32 rsvd0[7];
 671         u32 port0_jabber_events;
 672         u32 port1_jabber_events;
 673         u32 rsvd1[6];
 674 };
 675
 676 struct be_erx_stats_v0 {
 677         u32 rx_drops_no_fragments[44];     /* dwordS 0 to 43*/
 678         u32 rsvd[4];
 679 };
 680
 681 struct be_pmem_stats {
 682         u32 eth_red_drops;
 683         u32 rsvd[5];
 684 };
 685
 686 struct be_hw_stats_v0 {
 687         struct be_rxf_stats_v0 rxf;
 688         u32 rsvd[48];
 689         struct be_erx_stats_v0 erx;
 690         struct be_pmem_stats pmem;
 691 };
 692
 693 struct be_cmd_req_get_stats_v0 {
 694         struct be_cmd_req_hdr hdr;
 695         u8 rsvd[sizeof(struct be_hw_stats_v0)];
 696 };
 697
 698 struct be_cmd_resp_get_stats_v0 {
 699         struct be_cmd_resp_hdr hdr;
 700         struct be_hw_stats_v0 hw_stats;
 701 };
 702
 703 struct lancer_pport_stats {
 704         u32 tx_packets_lo;
 705         u32 tx_packets_hi;
 706         u32 tx_unicast_packets_lo;
 707         u32 tx_unicast_packets_hi;
 708         u32 tx_multicast_packets_lo;
 709         u32 tx_multicast_packets_hi;
 710         u32 tx_broadcast_packets_lo;
 711         u32 tx_broadcast_packets_hi;
 712         u32 tx_bytes_lo;
 713         u32 tx_bytes_hi;
 714         u32 tx_unicast_bytes_lo;
 715         u32 tx_unicast_bytes_hi;
 716         u32 tx_multicast_bytes_lo;
 717         u32 tx_multicast_bytes_hi;
 718         u32 tx_broadcast_bytes_lo;
 719         u32 tx_broadcast_bytes_hi;
 720         u32 tx_discards_lo;
 721         u32 tx_discards_hi;
 722         u32 tx_errors_lo;
 723         u32 tx_errors_hi;
 724         u32 tx_pause_frames_lo;
 725         u32 tx_pause_frames_hi;
 726         u32 tx_pause_on_frames_lo;
 727         u32 tx_pause_on_frames_hi;
 728         u32 tx_pause_off_frames_lo;
 729         u32 tx_pause_off_frames_hi;
 730         u32 tx_internal_mac_errors_lo;
 731         u32 tx_internal_mac_errors_hi;
 732         u32 tx_control_frames_lo;
 733         u32 tx_control_frames_hi;
 734         u32 tx_packets_64_bytes_lo;
 735         u32 tx_packets_64_bytes_hi;
 736         u32 tx_packets_65_to_127_bytes_lo;
 737         u32 tx_packets_65_to_127_bytes_hi;
 738         u32 tx_packets_128_to_255_bytes_lo;
 739         u32 tx_packets_128_to_255_bytes_hi;
 740         u32 tx_packets_256_to_511_bytes_lo;
 741         u32 tx_packets_256_to_511_bytes_hi;
 742         u32 tx_packets_512_to_1023_bytes_lo;
 743         u32 tx_packets_512_to_1023_bytes_hi;
 744         u32 tx_packets_1024_to_1518_bytes_lo;
 745         u32 tx_packets_1024_to_1518_bytes_hi;
 746         u32 tx_packets_1519_to_2047_bytes_lo;
 747         u32 tx_packets_1519_to_2047_bytes_hi;
 748         u32 tx_packets_2048_to_4095_bytes_lo;
 749         u32 tx_packets_2048_to_4095_bytes_hi;
 750         u32 tx_packets_4096_to_8191_bytes_lo;
 751         u32 tx_packets_4096_to_8191_bytes_hi;
 752         u32 tx_packets_8192_to_9216_bytes_lo;
 753         u32 tx_packets_8192_to_9216_bytes_hi;
 754         u32 tx_lso_packets_lo;
 755         u32 tx_lso_packets_hi;
 756         u32 rx_packets_lo;
 757         u32 rx_packets_hi;
 758         u32 rx_unicast_packets_lo;
 759         u32 rx_unicast_packets_hi;
 760         u32 rx_multicast_packets_lo;
 761         u32 rx_multicast_packets_hi;
 762         u32 rx_broadcast_packets_lo;
 763         u32 rx_broadcast_packets_hi;
 764         u32 rx_bytes_lo;
 765         u32 rx_bytes_hi;
 766         u32 rx_unicast_bytes_lo;
 767         u32 rx_unicast_bytes_hi;
 768         u32 rx_multicast_bytes_lo;
 769         u32 rx_multicast_bytes_hi;
 770         u32 rx_broadcast_bytes_lo;
 771         u32 rx_broadcast_bytes_hi;
 772         u32 rx_unknown_protos;
 773         u32 rsvd_69; /* Word 69 is reserved */
 774         u32 rx_discards_lo;
 775         u32 rx_discards_hi;
 776         u32 rx_errors_lo;
 777         u32 rx_errors_hi;
 778         u32 rx_crc_errors_lo;
 779         u32 rx_crc_errors_hi;
 780         u32 rx_alignment_errors_lo;
 781         u32 rx_alignment_errors_hi;
 782         u32 rx_symbol_errors_lo;
 783         u32 rx_symbol_errors_hi;
 784         u32 rx_pause_frames_lo;
 785         u32 rx_pause_frames_hi;
 786         u32 rx_pause_on_frames_lo;
 787         u32 rx_pause_on_frames_hi;
 788         u32 rx_pause_off_frames_lo;
 789         u32 rx_pause_off_frames_hi;
 790         u32 rx_frames_too_long_lo;
 791         u32 rx_frames_too_long_hi;
 792         u32 rx_internal_mac_errors_lo;
 793         u32 rx_internal_mac_errors_hi;
 794         u32 rx_undersize_packets;
 795         u32 rx_oversize_packets;
 796         u32 rx_fragment_packets;
 797         u32 rx_jabbers;
 798         u32 rx_control_frames_lo;
 799         u32 rx_control_frames_hi;
 800         u32 rx_control_frames_unknown_opcode_lo;
 801         u32 rx_control_frames_unknown_opcode_hi;
 802         u32 rx_in_range_errors;
 803         u32 rx_out_of_range_errors;
 804         u32 rx_address_mismatch_drops;
 805         u32 rx_vlan_mismatch_drops;
 806         u32 rx_dropped_too_small;
 807         u32 rx_dropped_too_short;
 808         u32 rx_dropped_header_too_small;
 809         u32 rx_dropped_invalid_tcp_length;
 810         u32 rx_dropped_runt;
 811         u32 rx_ip_checksum_errors;
 812         u32 rx_tcp_checksum_errors;
 813         u32 rx_udp_checksum_errors;
 814         u32 rx_non_rss_packets;
 815         u32 rsvd_111;
 816         u32 rx_ipv4_packets_lo;
 817         u32 rx_ipv4_packets_hi;
 818         u32 rx_ipv6_packets_lo;
 819         u32 rx_ipv6_packets_hi;
 820         u32 rx_ipv4_bytes_lo;
 821         u32 rx_ipv4_bytes_hi;
 822         u32 rx_ipv6_bytes_lo;
 823         u32 rx_ipv6_bytes_hi;
 824         u32 rx_nic_packets_lo;
 825         u32 rx_nic_packets_hi;
 826         u32 rx_tcp_packets_lo;
 827         u32 rx_tcp_packets_hi;
 828         u32 rx_iscsi_packets_lo;
 829         u32 rx_iscsi_packets_hi;
 830         u32 rx_management_packets_lo;
 831         u32 rx_management_packets_hi;
 832         u32 rx_switched_unicast_packets_lo;
 833         u32 rx_switched_unicast_packets_hi;
 834         u32 rx_switched_multicast_packets_lo;
 835         u32 rx_switched_multicast_packets_hi;
 836         u32 rx_switched_broadcast_packets_lo;
 837         u32 rx_switched_broadcast_packets_hi;
 838         u32 num_forwards_lo;
 839         u32 num_forwards_hi;
 840         u32 rx_fifo_overflow;
 841         u32 rx_input_fifo_overflow;
 842         u32 rx_drops_too_many_frags_lo;
 843         u32 rx_drops_too_many_frags_hi;
 844         u32 rx_drops_invalid_queue;
 845         u32 rsvd_141;
 846         u32 rx_drops_mtu_lo;
 847         u32 rx_drops_mtu_hi;
 848         u32 rx_packets_64_bytes_lo;
 849         u32 rx_packets_64_bytes_hi;
 850         u32 rx_packets_65_to_127_bytes_lo;
 851         u32 rx_packets_65_to_127_bytes_hi;
 852         u32 rx_packets_128_to_255_bytes_lo;
 853         u32 rx_packets_128_to_255_bytes_hi;
 854         u32 rx_packets_256_to_511_bytes_lo;
 855         u32 rx_packets_256_to_511_bytes_hi;
 856         u32 rx_packets_512_to_1023_bytes_lo;
 857         u32 rx_packets_512_to_1023_bytes_hi;
 858         u32 rx_packets_1024_to_1518_bytes_lo;
 859         u32 rx_packets_1024_to_1518_bytes_hi;
 860         u32 rx_packets_1519_to_2047_bytes_lo;
 861         u32 rx_packets_1519_to_2047_bytes_hi;
 862         u32 rx_packets_2048_to_4095_bytes_lo;
 863         u32 rx_packets_2048_to_4095_bytes_hi;
 864         u32 rx_packets_4096_to_8191_bytes_lo;
 865         u32 rx_packets_4096_to_8191_bytes_hi;
 866         u32 rx_packets_8192_to_9216_bytes_lo;
 867         u32 rx_packets_8192_to_9216_bytes_hi;
 868 };
 869
 870 struct pport_stats_params {
 871         u16 pport_num;
 872         u8 rsvd;
 873         u8 reset_stats;
 874 };
 875
 876 struct lancer_cmd_req_pport_stats {
 877         struct be_cmd_req_hdr hdr;
 878         union {
 879                 struct pport_stats_params params;
 880                 u8 rsvd[sizeof(struct lancer_pport_stats)];
 881         } cmd_params;
 882 };
 883
 884 struct lancer_cmd_resp_pport_stats {
 885         struct be_cmd_resp_hdr hdr;
 886         struct lancer_pport_stats pport_stats;
 887 };
 888
 889 static inline struct lancer_pport_stats*
 890         pport_stats_from_cmd(struct be_adapter *adapter)
 891 {
 892         struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va;
 893         return &cmd->pport_stats;
 894 }
 895
 896 struct be_cmd_req_get_cntl_addnl_attribs {
 897         struct be_cmd_req_hdr hdr;
 898         u8 rsvd[8];
 899 };
 900
 901 struct be_cmd_resp_get_cntl_addnl_attribs {
 902         struct be_cmd_resp_hdr hdr;
 903         u16 ipl_file_number;
 904         u8 ipl_file_version;
 905         u8 rsvd0;
 906         u8 on_die_temperature; /* in degrees centigrade*/
 907         u8 rsvd1[3];
 908 };
 909
 910 struct be_cmd_req_vlan_config {
 911         struct be_cmd_req_hdr hdr;
 912         u8 interface_id;
 913         u8 promiscuous;
 914         u8 untagged;
 915         u8 num_vlan;
 916         u16 normal_vlan[64];
 917 } __packed;
 918
 919 /******************* RX FILTER ******************************/
 920 #define BE_MAX_MC               64 /* set mcast promisc if > 64 */
 921 struct macaddr {
 922         u8 byte[ETH_ALEN];
 923 };
 924
 925 struct be_cmd_req_rx_filter {
 926         struct be_cmd_req_hdr hdr;
 927         u32 global_flags_mask;
 928         u32 global_flags;
 929         u32 if_flags_mask;
 930         u32 if_flags;
 931         u32 if_id;
 932         u32 mcast_num;
 933         struct macaddr mcast_mac[BE_MAX_MC];
 934 };
 935
 936 /******************** Link Status Query *******************/
 937 struct be_cmd_req_link_status {
 938         struct be_cmd_req_hdr hdr;
 939         u32 rsvd;
 940 };
 941
 942 enum {
 943         PHY_LINK_DUPLEX_NONE = 0x0,
 944         PHY_LINK_DUPLEX_HALF = 0x1,
 945         PHY_LINK_DUPLEX_FULL = 0x2
 946 };
 947
 948 enum {
 949         PHY_LINK_SPEED_ZERO = 0x0,      /* => No link */
 950         PHY_LINK_SPEED_10MBPS = 0x1,
 951         PHY_LINK_SPEED_100MBPS = 0x2,
 952         PHY_LINK_SPEED_1GBPS = 0x3,
 953         PHY_LINK_SPEED_10GBPS = 0x4
 954 };
 955
 956 struct be_cmd_resp_link_status {
 957         struct be_cmd_resp_hdr hdr;
 958         u8 physical_port;
 959         u8 mac_duplex;
 960         u8 mac_speed;
 961         u8 mac_fault;
 962         u8 mgmt_mac_duplex;
 963         u8 mgmt_mac_speed;
 964         u16 link_speed;
 965         u8 logical_link_status;
 966         u8 rsvd1[3];
 967 } __packed;
 968
 969 /******************** Port Identification ***************************/
 970 /*    Identifies the type of port attached to NIC     */
 971 struct be_cmd_req_port_type {
 972         struct be_cmd_req_hdr hdr;
 973         u32 page_num;
 974         u32 port;
 975 };
 976
 977 enum {
 978         TR_PAGE_A0 = 0xa0,
 979         TR_PAGE_A2 = 0xa2
 980 };
 981
 982 struct be_cmd_resp_port_type {
 983         struct be_cmd_resp_hdr hdr;
 984         u32 page_num;
 985         u32 port;
 986         struct data {
 987                 u8 identifier;
 988                 u8 identifier_ext;
 989                 u8 connector;
 990                 u8 transceiver[8];
 991                 u8 rsvd0[3];
 992                 u8 length_km;
 993                 u8 length_hm;
 994                 u8 length_om1;
 995                 u8 length_om2;
 996                 u8 length_cu;
 997                 u8 length_cu_m;
 998                 u8 vendor_name[16];
 999                 u8 rsvd;
1000                 u8 vendor_oui[3];
1001                 u8 vendor_pn[16];
1002                 u8 vendor_rev[4];
1003         } data;
1004 };
1005
1006 /******************** Get FW Version *******************/
1007 struct be_cmd_req_get_fw_version {
1008         struct be_cmd_req_hdr hdr;
1009         u8 rsvd0[FW_VER_LEN];
1010         u8 rsvd1[FW_VER_LEN];
1011 } __packed;
1012
1013 struct be_cmd_resp_get_fw_version {
1014         struct be_cmd_resp_hdr hdr;
1015         u8 firmware_version_string[FW_VER_LEN];
1016         u8 fw_on_flash_version_string[FW_VER_LEN];
1017 } __packed;
1018
1019 /******************** Set Flow Contrl *******************/
1020 struct be_cmd_req_set_flow_control {
1021         struct be_cmd_req_hdr hdr;
1022         u16 tx_flow_control;
1023         u16 rx_flow_control;
1024 } __packed;
1025
1026 /******************** Get Flow Contrl *******************/
1027 struct be_cmd_req_get_flow_control {
1028         struct be_cmd_req_hdr hdr;
1029         u32 rsvd;
1030 };
1031
1032 struct be_cmd_resp_get_flow_control {
1033         struct be_cmd_resp_hdr hdr;
1034         u16 tx_flow_control;
1035         u16 rx_flow_control;
1036 } __packed;
1037
1038 /******************** Modify EQ Delay *******************/
1039 struct be_cmd_req_modify_eq_delay {
1040         struct be_cmd_req_hdr hdr;
1041         u32 num_eq;
1042         struct {
1043                 u32 eq_id;
1044                 u32 phase;
1045                 u32 delay_multiplier;
1046         } delay[8];
1047 } __packed;
1048
1049 struct be_cmd_resp_modify_eq_delay {
1050         struct be_cmd_resp_hdr hdr;
1051         u32 rsvd0;
1052 } __packed;
1053
1054 /******************** Get FW Config *******************/
1055 #define BE_FUNCTION_CAPS_RSS                    0x2
1056 /* The HW can come up in either of the following multi-channel modes
1057  * based on the skew/IPL.
1058  */
1059 #define FLEX10_MODE                             0x400
1060 #define VNIC_MODE                               0x20000
1061 #define UMC_ENABLED                             0x1000000
1062 struct be_cmd_req_query_fw_cfg {
1063         struct be_cmd_req_hdr hdr;
1064         u32 rsvd[31];
1065 };
1066
1067 struct be_cmd_resp_query_fw_cfg {
1068         struct be_cmd_resp_hdr hdr;
1069         u32 be_config_number;
1070         u32 asic_revision;
1071         u32 phys_port;
1072         u32 function_mode;
1073         u32 rsvd[26];
1074         u32 function_caps;
1075 };
1076
1077 /******************** RSS Config *******************/
1078 /* RSS types */
1079 #define RSS_ENABLE_NONE                         0x0
1080 #define RSS_ENABLE_IPV4                         0x1
1081 #define RSS_ENABLE_TCP_IPV4                     0x2
1082 #define RSS_ENABLE_IPV6                         0x4
1083 #define RSS_ENABLE_TCP_IPV6                     0x8
1084
1085 struct be_cmd_req_rss_config {
1086         struct be_cmd_req_hdr hdr;
1087         u32 if_id;
1088         u16 enable_rss;
1089         u16 cpu_table_size_log2;
1090         u32 hash[10];
1091         u8 cpu_table[128];
1092         u8 flush;
1093         u8 rsvd0[3];
1094 };
1095
1096 /******************** Port Beacon ***************************/
1097
1098 #define BEACON_STATE_ENABLED            0x1
1099 #define BEACON_STATE_DISABLED           0x0
1100
1101 struct be_cmd_req_enable_disable_beacon {
1102         struct be_cmd_req_hdr hdr;
1103         u8  port_num;
1104         u8  beacon_state;
1105         u8  beacon_duration;
1106         u8  status_duration;
1107 } __packed;
1108
1109 struct be_cmd_resp_enable_disable_beacon {
1110         struct be_cmd_resp_hdr resp_hdr;
1111         u32 rsvd0;
1112 } __packed;
1113
1114 struct be_cmd_req_get_beacon_state {
1115         struct be_cmd_req_hdr hdr;
1116         u8  port_num;
1117         u8  rsvd0;
1118         u16 rsvd1;
1119 } __packed;
1120
1121 struct be_cmd_resp_get_beacon_state {
1122         struct be_cmd_resp_hdr resp_hdr;
1123         u8 beacon_state;
1124         u8 rsvd0[3];
1125 } __packed;
1126
1127 /****************** Firmware Flash ******************/
1128 struct flashrom_params {
1129         u32 op_code;
1130         u32 op_type;
1131         u32 data_buf_size;
1132         u32 offset;
1133         u8 data_buf[4];
1134 };
1135
1136 struct be_cmd_write_flashrom {
1137         struct be_cmd_req_hdr hdr;
1138         struct flashrom_params params;
1139 };
1140
1141 /**************** Lancer Firmware Flash ************/
1142 struct amap_lancer_write_obj_context {
1143         u8 write_length[24];
1144         u8 reserved1[7];
1145         u8 eof;
1146 } __packed;
1147
1148 struct lancer_cmd_req_write_object {
1149         struct be_cmd_req_hdr hdr;
1150         u8 context[sizeof(struct amap_lancer_write_obj_context) / 8];
1151         u32 write_offset;
1152         u8 object_name[104];
1153         u32 descriptor_count;
1154         u32 buf_len;
1155         u32 addr_low;
1156         u32 addr_high;
1157 };
1158
1159 struct lancer_cmd_resp_write_object {
1160         u8 opcode;
1161         u8 subsystem;
1162         u8 rsvd1[2];
1163         u8 status;
1164         u8 additional_status;
1165         u8 rsvd2[2];
1166         u32 resp_len;
1167         u32 actual_resp_len;
1168         u32 actual_write_len;
1169 };
1170
1171 /************************ Lancer Read FW info **************/
1172 #define LANCER_READ_FILE_CHUNK                  (32*1024)
1173 #define LANCER_READ_FILE_EOF_MASK               0x80000000
1174
1175 #define LANCER_FW_DUMP_FILE                     "/dbg/dump.bin"
1176 #define LANCER_VPD_PF_FILE                      "/vpd/ntr_pf.vpd"
1177 #define LANCER_VPD_VF_FILE                      "/vpd/ntr_vf.vpd"
1178
1179 struct lancer_cmd_req_read_object {
1180         struct be_cmd_req_hdr hdr;
1181         u32 desired_read_len;
1182         u32 read_offset;
1183         u8 object_name[104];
1184         u32 descriptor_count;
1185         u32 buf_len;
1186         u32 addr_low;
1187         u32 addr_high;
1188 };
1189
1190 struct lancer_cmd_resp_read_object {
1191         u8 opcode;
1192         u8 subsystem;
1193         u8 rsvd1[2];
1194         u8 status;
1195         u8 additional_status;
1196         u8 rsvd2[2];
1197         u32 resp_len;
1198         u32 actual_resp_len;
1199         u32 actual_read_len;
1200         u32 eof;
1201 };
1202
1203 /************************ WOL *******************************/
1204 struct be_cmd_req_acpi_wol_magic_config{
1205         struct be_cmd_req_hdr hdr;
1206         u32 rsvd0[145];
1207         u8 magic_mac[6];
1208         u8 rsvd2[2];
1209 } __packed;
1210
1211 struct be_cmd_req_acpi_wol_magic_config_v1 {
1212         struct be_cmd_req_hdr hdr;
1213         u8 rsvd0[2];
1214         u8 query_options;
1215         u8 rsvd1[5];
1216         u32 rsvd2[288];
1217         u8 magic_mac[6];
1218         u8 rsvd3[22];
1219 } __packed;
1220
1221 struct be_cmd_resp_acpi_wol_magic_config_v1 {
1222         struct be_cmd_resp_hdr hdr;
1223         u8 rsvd0[2];
1224         u8 wol_settings;
1225         u8 rsvd1[5];
1226         u32 rsvd2[295];
1227 } __packed;
1228
1229 #define BE_GET_WOL_CAP                  2
1230
1231 #define BE_WOL_CAP                      0x1
1232 #define BE_PME_D0_CAP                   0x8
1233 #define BE_PME_D1_CAP                   0x10
1234 #define BE_PME_D2_CAP                   0x20
1235 #define BE_PME_D3HOT_CAP                0x40
1236 #define BE_PME_D3COLD_CAP               0x80
1237
1238 /********************** LoopBack test *********************/
1239 struct be_cmd_req_loopback_test {
1240         struct be_cmd_req_hdr hdr;
1241         u32 loopback_type;
1242         u32 num_pkts;
1243         u64 pattern;
1244         u32 src_port;
1245         u32 dest_port;
1246         u32 pkt_size;
1247 };
1248
1249 struct be_cmd_resp_loopback_test {
1250         struct be_cmd_resp_hdr resp_hdr;
1251         u32    status;
1252         u32    num_txfer;
1253         u32    num_rx;
1254         u32    miscomp_off;
1255         u32    ticks_compl;
1256 };
1257
1258 struct be_cmd_req_set_lmode {
1259         struct be_cmd_req_hdr hdr;
1260         u8 src_port;
1261         u8 dest_port;
1262         u8 loopback_type;
1263         u8 loopback_state;
1264 };
1265
1266 struct be_cmd_resp_set_lmode {
1267         struct be_cmd_resp_hdr resp_hdr;
1268         u8 rsvd0[4];
1269 };
1270
1271 /********************** DDR DMA test *********************/
1272 struct be_cmd_req_ddrdma_test {
1273         struct be_cmd_req_hdr hdr;
1274         u64 pattern;
1275         u32 byte_count;
1276         u32 rsvd0;
1277         u8  snd_buff[4096];
1278         u8  rsvd1[4096];
1279 };
1280
1281 struct be_cmd_resp_ddrdma_test {
1282         struct be_cmd_resp_hdr hdr;
1283         u64 pattern;
1284         u32 byte_cnt;
1285         u32 snd_err;
1286         u8  rsvd0[4096];
1287         u8  rcv_buff[4096];
1288 };
1289
1290 /*********************** SEEPROM Read ***********************/
1291
1292 #define BE_READ_SEEPROM_LEN 1024
1293 struct be_cmd_req_seeprom_read {
1294         struct be_cmd_req_hdr hdr;
1295         u8 rsvd0[BE_READ_SEEPROM_LEN];
1296 };
1297
1298 struct be_cmd_resp_seeprom_read {
1299         struct be_cmd_req_hdr hdr;
1300         u8 seeprom_data[BE_READ_SEEPROM_LEN];
1301 };
1302
1303 enum {
1304         PHY_TYPE_CX4_10GB = 0,
1305         PHY_TYPE_XFP_10GB,
1306         PHY_TYPE_SFP_1GB,
1307         PHY_TYPE_SFP_PLUS_10GB,
1308         PHY_TYPE_KR_10GB,
1309         PHY_TYPE_KX4_10GB,
1310         PHY_TYPE_BASET_10GB,
1311         PHY_TYPE_BASET_1GB,
1312         PHY_TYPE_DISABLED = 255
1313 };
1314
1315 struct be_cmd_req_get_phy_info {
1316         struct be_cmd_req_hdr hdr;
1317         u8 rsvd0[24];
1318 };
1319
1320 struct be_phy_info {
1321         u16 phy_type;
1322         u16 interface_type;
1323         u32 misc_params;
1324         u32 future_use[4];
1325 };
1326
1327 struct be_cmd_resp_get_phy_info {
1328         struct be_cmd_req_hdr hdr;
1329         struct be_phy_info phy_info;
1330 };
1331
1332 /*********************** Set QOS ***********************/
1333
1334 #define BE_QOS_BITS_NIC                         1
1335
1336 struct be_cmd_req_set_qos {
1337         struct be_cmd_req_hdr hdr;
1338         u32 valid_bits;
1339         u32 max_bps_nic;
1340         u32 rsvd[7];
1341 };
1342
1343 struct be_cmd_resp_set_qos {
1344         struct be_cmd_resp_hdr hdr;
1345         u32 rsvd;
1346 };
1347
1348 /*********************** Controller Attributes ***********************/
1349 struct be_cmd_req_cntl_attribs {
1350         struct be_cmd_req_hdr hdr;
1351 };
1352
1353 struct be_cmd_resp_cntl_attribs {
1354         struct be_cmd_resp_hdr hdr;
1355         struct mgmt_controller_attrib attribs;
1356 };
1357
1358 /*********************** Set driver function ***********************/
1359 #define CAPABILITY_SW_TIMESTAMPS        2
1360 #define CAPABILITY_BE3_NATIVE_ERX_API   4
1361
1362 struct be_cmd_req_set_func_cap {
1363         struct be_cmd_req_hdr hdr;
1364         u32 valid_cap_flags;
1365         u32 cap_flags;
1366         u8 rsvd[212];
1367 };
1368
1369 struct be_cmd_resp_set_func_cap {
1370         struct be_cmd_resp_hdr hdr;
1371         u32 valid_cap_flags;
1372         u32 cap_flags;
1373         u8 rsvd[212];
1374 };
1375
1376 /******************** GET/SET_MACLIST  **************************/
1377 #define BE_MAX_MAC                      64
1378 struct be_cmd_req_get_mac_list {
1379         struct be_cmd_req_hdr hdr;
1380         u8 mac_type;
1381         u8 perm_override;
1382         u16 iface_id;
1383         u32 mac_id;
1384         u32 rsvd[3];
1385 } __packed;
1386
1387 struct get_list_macaddr {
1388         u16 mac_addr_size;
1389         union {
1390                 u8 macaddr[6];
1391                 struct {
1392                         u8 rsvd[2];
1393                         u32 mac_id;
1394                 } __packed s_mac_id;
1395         } __packed mac_addr_id;
1396 } __packed;
1397
1398 struct be_cmd_resp_get_mac_list {
1399         struct be_cmd_resp_hdr hdr;
1400         struct get_list_macaddr fd_macaddr; /* Factory default mac */
1401         struct get_list_macaddr macid_macaddr; /* soft mac */
1402         u8 true_mac_count;
1403         u8 pseudo_mac_count;
1404         u8 mac_list_size;
1405         u8 rsvd;
1406         /* perm override mac */
1407         struct get_list_macaddr macaddr_list[BE_MAX_MAC];
1408 } __packed;
1409
1410 struct be_cmd_req_set_mac_list {
1411         struct be_cmd_req_hdr hdr;
1412         u8 mac_count;
1413         u8 rsvd1;
1414         u16 rsvd2;
1415         struct macaddr mac[BE_MAX_MAC];
1416 } __packed;
1417
1418 /*********************** HSW Config ***********************/
1419 struct amap_set_hsw_context {
1420         u8 interface_id[16];
1421         u8 rsvd0[14];
1422         u8 pvid_valid;
1423         u8 rsvd1;
1424         u8 rsvd2[16];
1425         u8 pvid[16];
1426         u8 rsvd3[32];
1427         u8 rsvd4[32];
1428         u8 rsvd5[32];
1429 } __packed;
1430
1431 struct be_cmd_req_set_hsw_config {
1432         struct be_cmd_req_hdr hdr;
1433         u8 context[sizeof(struct amap_set_hsw_context) / 8];
1434 } __packed;
1435
1436 struct be_cmd_resp_set_hsw_config {
1437         struct be_cmd_resp_hdr hdr;
1438         u32 rsvd;
1439 };
1440
1441 struct amap_get_hsw_req_context {
1442         u8 interface_id[16];
1443         u8 rsvd0[14];
1444         u8 pvid_valid;
1445         u8 pport;
1446 } __packed;
1447
1448 struct amap_get_hsw_resp_context {
1449         u8 rsvd1[16];
1450         u8 pvid[16];
1451         u8 rsvd2[32];
1452         u8 rsvd3[32];
1453         u8 rsvd4[32];
1454 } __packed;
1455
1456 struct be_cmd_req_get_hsw_config {
1457         struct be_cmd_req_hdr hdr;
1458         u8 context[sizeof(struct amap_get_hsw_req_context) / 8];
1459 } __packed;
1460
1461 struct be_cmd_resp_get_hsw_config {
1462         struct be_cmd_resp_hdr hdr;
1463         u8 context[sizeof(struct amap_get_hsw_resp_context) / 8];
1464         u32 rsvd;
1465 };
1466
1467 /*************** HW Stats Get v1 **********************************/
1468 #define BE_TXP_SW_SZ                    48
1469 struct be_port_rxf_stats_v1 {
1470         u32 rsvd0[12];
1471         u32 rx_crc_errors;
1472         u32 rx_alignment_symbol_errors;
1473         u32 rx_pause_frames;
1474         u32 rx_priority_pause_frames;
1475         u32 rx_control_frames;
1476         u32 rx_in_range_errors;
1477         u32 rx_out_range_errors;
1478         u32 rx_frame_too_long;
1479         u32 rx_address_mismatch_drops;
1480         u32 rx_dropped_too_small;
1481         u32 rx_dropped_too_short;
1482         u32 rx_dropped_header_too_small;
1483         u32 rx_dropped_tcp_length;
1484         u32 rx_dropped_runt;
1485         u32 rsvd1[10];
1486         u32 rx_ip_checksum_errs;
1487         u32 rx_tcp_checksum_errs;
1488         u32 rx_udp_checksum_errs;
1489         u32 rsvd2[7];
1490         u32 rx_switched_unicast_packets;
1491         u32 rx_switched_multicast_packets;
1492         u32 rx_switched_broadcast_packets;
1493         u32 rsvd3[3];
1494         u32 tx_pauseframes;
1495         u32 tx_priority_pauseframes;
1496         u32 tx_controlframes;
1497         u32 rsvd4[10];
1498         u32 rxpp_fifo_overflow_drop;
1499         u32 rx_input_fifo_overflow_drop;
1500         u32 pmem_fifo_overflow_drop;
1501         u32 jabber_events;
1502         u32 rsvd5[3];
1503 };
1504
1505
1506 struct be_rxf_stats_v1 {
1507         struct be_port_rxf_stats_v1 port[4];
1508         u32 rsvd0[2];
1509         u32 rx_drops_no_pbuf;
1510         u32 rx_drops_no_txpb;
1511         u32 rx_drops_no_erx_descr;
1512         u32 rx_drops_no_tpre_descr;
1513         u32 rsvd1[6];
1514         u32 rx_drops_too_many_frags;
1515         u32 rx_drops_invalid_ring;
1516         u32 forwarded_packets;
1517         u32 rx_drops_mtu;
1518         u32 rsvd2[14];
1519 };
1520
1521 struct be_erx_stats_v1 {
1522         u32 rx_drops_no_fragments[68];     /* dwordS 0 to 67*/
1523         u32 rsvd[4];
1524 };
1525
1526 struct be_hw_stats_v1 {
1527         struct be_rxf_stats_v1 rxf;
1528         u32 rsvd0[BE_TXP_SW_SZ];
1529         struct be_erx_stats_v1 erx;
1530         struct be_pmem_stats pmem;
1531         u32 rsvd1[3];
1532 };
1533
1534 struct be_cmd_req_get_stats_v1 {
1535         struct be_cmd_req_hdr hdr;
1536         u8 rsvd[sizeof(struct be_hw_stats_v1)];
1537 };
1538
1539 struct be_cmd_resp_get_stats_v1 {
1540         struct be_cmd_resp_hdr hdr;
1541         struct be_hw_stats_v1 hw_stats;
1542 };
1543
1544 static inline void *hw_stats_from_cmd(struct be_adapter *adapter)
1545 {
1546         if (adapter->generation == BE_GEN3) {
1547                 struct be_cmd_resp_get_stats_v1 *cmd = adapter->stats_cmd.va;
1548
1549                 return &cmd->hw_stats;
1550         } else {
1551                 struct be_cmd_resp_get_stats_v0 *cmd = adapter->stats_cmd.va;
1552
1553                 return &cmd->hw_stats;
1554         }
1555 }
1556
1557 static inline void *be_erx_stats_from_cmd(struct be_adapter *adapter)
1558 {
1559         if (adapter->generation == BE_GEN3) {
1560                 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter);
1561
1562                 return &hw_stats->erx;
1563         } else {
1564                 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter);
1565
1566                 return &hw_stats->erx;
1567         }
1568 }
1569
1570 extern int be_pci_fnum_get(struct be_adapter *adapter);
1571 extern int be_cmd_POST(struct be_adapter *adapter);
1572 extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1573                         u8 type, bool permanent, u32 if_handle, u32 pmac_id);
1574 extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1575                         u32 if_id, u32 *pmac_id, u32 domain);
1576 extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id,
1577                         int pmac_id, u32 domain);
1578 extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
1579                         u32 en_flags, u8 *mac, u32 *if_handle, u32 *pmac_id,
1580                         u32 domain);
1581 extern int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle,
1582                         u32 domain);
1583 extern int be_cmd_eq_create(struct be_adapter *adapter,
1584                         struct be_queue_info *eq, int eq_delay);
1585 extern int be_cmd_cq_create(struct be_adapter *adapter,
1586                         struct be_queue_info *cq, struct be_queue_info *eq,
1587                         bool no_delay, int num_cqe_dma_coalesce);
1588 extern int be_cmd_mccq_create(struct be_adapter *adapter,
1589                         struct be_queue_info *mccq,
1590                         struct be_queue_info *cq);
1591 extern int be_cmd_txq_create(struct be_adapter *adapter,
1592                         struct be_queue_info *txq,
1593                         struct be_queue_info *cq);
1594 extern int be_cmd_rxq_create(struct be_adapter *adapter,
1595                         struct be_queue_info *rxq, u16 cq_id,
1596                         u16 frag_size, u32 if_id, u32 rss, u8 *rss_id);
1597 extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1598                         int type);
1599 extern int be_cmd_rxq_destroy(struct be_adapter *adapter,
1600                         struct be_queue_info *q);
1601 extern int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed,
1602                                     u16 *link_speed, u8 *link_status, u32 dom);
1603 extern int be_cmd_reset(struct be_adapter *adapter);
1604 extern int be_cmd_get_stats(struct be_adapter *adapter,
1605                         struct be_dma_mem *nonemb_cmd);
1606 extern int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1607                         struct be_dma_mem *nonemb_cmd);
1608 extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1609                 char *fw_on_flash);
1610
1611 extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
1612 extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
1613                         u16 *vtag_array, u32 num, bool untagged,
1614                         bool promiscuous);
1615 extern int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status);
1616 extern int be_cmd_set_flow_control(struct be_adapter *adapter,
1617                         u32 tx_fc, u32 rx_fc);
1618 extern int be_cmd_get_flow_control(struct be_adapter *adapter,
1619                         u32 *tx_fc, u32 *rx_fc);
1620 extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
1621                         u32 *port_num, u32 *function_mode, u32 *function_caps);
1622 extern int be_cmd_reset_function(struct be_adapter *adapter);
1623 extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1624                         u16 table_size);
1625 extern int be_process_mcc(struct be_adapter *adapter);
1626 extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
1627                         u8 port_num, u8 beacon, u8 status, u8 state);
1628 extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
1629                         u8 port_num, u32 *state);
1630 extern int be_cmd_write_flashrom(struct be_adapter *adapter,
1631                         struct be_dma_mem *cmd, u32 flash_oper,
1632                         u32 flash_opcode, u32 buf_size);
1633 extern int lancer_cmd_write_object(struct be_adapter *adapter,
1634                                 struct be_dma_mem *cmd,
1635                                 u32 data_size, u32 data_offset,
1636                                 const char *obj_name,
1637                                 u32 *data_written, u8 *addn_status);
1638 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1639                 u32 data_size, u32 data_offset, const char *obj_name,
1640                 u32 *data_read, u32 *eof, u8 *addn_status);
1641 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1642                                 int offset);
1643 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1644                                 struct be_dma_mem *nonemb_cmd);
1645 extern int be_cmd_fw_init(struct be_adapter *adapter);
1646 extern int be_cmd_fw_clean(struct be_adapter *adapter);
1647 extern void be_async_mcc_enable(struct be_adapter *adapter);
1648 extern void be_async_mcc_disable(struct be_adapter *adapter);
1649 extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1650                                 u32 loopback_type, u32 pkt_size,
1651                                 u32 num_pkts, u64 pattern);
1652 extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1653                         u32 byte_cnt, struct be_dma_mem *cmd);
1654 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1655                                 struct be_dma_mem *nonemb_cmd);
1656 extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1657                                 u8 loopback_type, u8 enable);
1658 extern int be_cmd_get_phy_info(struct be_adapter *adapter,
1659                                 struct be_phy_info *phy_info);
1660 extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
1661 extern void be_detect_dump_ue(struct be_adapter *adapter);
1662 extern int be_cmd_get_die_temperature(struct be_adapter *adapter);
1663 extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
1664 extern int be_cmd_req_native_mode(struct be_adapter *adapter);
1665 extern int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size);
1666 extern void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf);
1667 extern int be_cmd_get_mac_from_list(struct be_adapter *adapter, u32 domain,
1668                                 bool *pmac_id_active, u32 *pmac_id, u8 *mac);
1669 extern int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
1670                                                 u8 mac_count, u32 domain);
1671 extern int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
1672                         u32 domain, u16 intf_id);
1673 extern int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
1674                         u32 domain, u16 intf_id);
1675 extern int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter);
1676