drivers/net/ethernet/emulex/benet/be_hw.h

   1 /*
   2  * Copyright (C) 2005 - 2013 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 /********* Mailbox door bell *************/
  19 /* Used for driver communication with the FW.
  20  * The software must write this register twice to post any command. First,
  21  * it writes the register with hi=1 and the upper bits of the physical address
  22  * for the MAILBOX structure. Software must poll the ready bit until this
  23  * is acknowledged. Then, sotware writes the register with hi=0 with the lower
  24  * bits in the address. It must poll the ready bit until the command is
  25  * complete. Upon completion, the MAILBOX will contain a valid completion
  26  * queue entry.
  27  */
  28 #define MPU_MAILBOX_DB_OFFSET   0x160
  29 #define MPU_MAILBOX_DB_RDY_MASK 0x1     /* bit 0 */
  30 #define MPU_MAILBOX_DB_HI_MASK  0x2     /* bit 1 */
  31
  32 #define MPU_EP_CONTROL          0
  33
  34 /********** MPU semphore: used for SH & BE  *************/
  35 #define SLIPORT_SEMAPHORE_OFFSET_BEx            0xac  /* CSR BAR offset */
  36 #define SLIPORT_SEMAPHORE_OFFSET_SH             0x94  /* PCI-CFG offset */
  37 #define POST_STAGE_MASK                         0x0000FFFF
  38 #define POST_ERR_MASK                           0x1
  39 #define POST_ERR_SHIFT                          31
  40
  41 /* MPU semphore POST stage values */
  42 #define POST_STAGE_AWAITING_HOST_RDY    0x1 /* FW awaiting goahead from host */
  43 #define POST_STAGE_HOST_RDY             0x2 /* Host has given go-ahed to FW */
  44 #define POST_STAGE_BE_RESET             0x3 /* Host wants to reset chip */
  45 #define POST_STAGE_ARMFW_RDY            0xc000  /* FW is done with POST */
  46
  47
  48 /* Lancer SLIPORT registers */
  49 #define SLIPORT_STATUS_OFFSET           0x404
  50 #define SLIPORT_CONTROL_OFFSET          0x408
  51 #define SLIPORT_ERROR1_OFFSET           0x40C
  52 #define SLIPORT_ERROR2_OFFSET           0x410
  53 #define PHYSDEV_CONTROL_OFFSET          0x414
  54
  55 #define SLIPORT_STATUS_ERR_MASK         0x80000000
  56 #define SLIPORT_STATUS_DIP_MASK         0x02000000
  57 #define SLIPORT_STATUS_RN_MASK          0x01000000
  58 #define SLIPORT_STATUS_RDY_MASK         0x00800000
  59 #define SLI_PORT_CONTROL_IP_MASK        0x08000000
  60 #define PHYSDEV_CONTROL_FW_RESET_MASK   0x00000002
  61 #define PHYSDEV_CONTROL_DD_MASK         0x00000004
  62 #define PHYSDEV_CONTROL_INP_MASK        0x40000000
  63
  64 #define SLIPORT_ERROR_NO_RESOURCE1      0x2
  65 #define SLIPORT_ERROR_NO_RESOURCE2      0x9
  66
  67 /********* Memory BAR register ************/
  68 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET      0xfc
  69 /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
  70  * Disable" may still globally block interrupts in addition to individual
  71  * interrupt masks; a mechanism for the device driver to block all interrupts
  72  * atomically without having to arbitrate for the PCI Interrupt Disable bit
  73  * with the OS.
  74  */
  75 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK      (1 << 29) /* bit 29 */
  76
  77 /********* PCI Function Capability *********/
  78 #define BE_FUNCTION_CAPS_RSS                    0x2
  79 #define BE_FUNCTION_CAPS_SUPER_NIC              0x40
  80
  81 /********* Power management (WOL) **********/
  82 #define PCICFG_PM_CONTROL_OFFSET                0x44
  83 #define PCICFG_PM_CONTROL_MASK                  0x108   /* bits 3 & 8 */
  84
  85 /********* Online Control Registers *******/
  86 #define PCICFG_ONLINE0                          0xB0
  87 #define PCICFG_ONLINE1                          0xB4
  88
  89 /********* UE Status and Mask Registers ***/
  90 #define PCICFG_UE_STATUS_LOW                    0xA0
  91 #define PCICFG_UE_STATUS_HIGH                   0xA4
  92 #define PCICFG_UE_STATUS_LOW_MASK               0xA8
  93 #define PCICFG_UE_STATUS_HI_MASK                0xAC
  94
  95 /******** SLI_INTF ***********************/
  96 #define SLI_INTF_REG_OFFSET                     0x58
  97 #define SLI_INTF_VALID_MASK                     0xE0000000
  98 #define SLI_INTF_VALID                          0xC0000000
  99 #define SLI_INTF_HINT2_MASK                     0x1F000000
 100 #define SLI_INTF_HINT2_SHIFT                    24
 101 #define SLI_INTF_HINT1_MASK                     0x00FF0000
 102 #define SLI_INTF_HINT1_SHIFT                    16
 103 #define SLI_INTF_FAMILY_MASK                    0x00000F00
 104 #define SLI_INTF_FAMILY_SHIFT                   8
 105 #define SLI_INTF_IF_TYPE_MASK                   0x0000F000
 106 #define SLI_INTF_IF_TYPE_SHIFT                  12
 107 #define SLI_INTF_REV_MASK                       0x000000F0
 108 #define SLI_INTF_REV_SHIFT                      4
 109 #define SLI_INTF_FT_MASK                        0x00000001
 110
 111 #define SLI_INTF_TYPE_2         2
 112 #define SLI_INTF_TYPE_3         3
 113
 114 /********* ISR0 Register offset **********/
 115 #define CEV_ISR0_OFFSET                         0xC18
 116 #define CEV_ISR_SIZE                            4
 117
 118 /********* Event Q door bell *************/
 119 #define DB_EQ_OFFSET                    DB_CQ_OFFSET
 120 #define DB_EQ_RING_ID_MASK              0x1FF   /* bits 0 - 8 */
 121 #define DB_EQ_RING_ID_EXT_MASK          0x3e00  /* bits 9-13 */
 122 #define DB_EQ_RING_ID_EXT_MASK_SHIFT    (2) /* qid bits 9-13 placing at 11-15 */
 123
 124 /* Clear the interrupt for this eq */
 125 #define DB_EQ_CLR_SHIFT                 (9)     /* bit 9 */
 126 /* Must be 1 */
 127 #define DB_EQ_EVNT_SHIFT                (10)    /* bit 10 */
 128 /* Number of event entries processed */
 129 #define DB_EQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 130 /* Rearm bit */
 131 #define DB_EQ_REARM_SHIFT               (29)    /* bit 29 */
 132
 133 /********* Compl Q door bell *************/
 134 #define DB_CQ_OFFSET                    0x120
 135 #define DB_CQ_RING_ID_MASK              0x3FF   /* bits 0 - 9 */
 136 #define DB_CQ_RING_ID_EXT_MASK          0x7C00  /* bits 10-14 */
 137 #define DB_CQ_RING_ID_EXT_MASK_SHIFT    (1)     /* qid bits 10-14
 138                                                  placing at 11-15 */
 139
 140 /* Number of event entries processed */
 141 #define DB_CQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 142 /* Rearm bit */
 143 #define DB_CQ_REARM_SHIFT               (29)    /* bit 29 */
 144
 145 /********** TX ULP door bell *************/
 146 #define DB_TXULP1_OFFSET                0x60
 147 #define DB_TXULP_RING_ID_MASK           0x7FF   /* bits 0 - 10 */
 148 /* Number of tx entries posted */
 149 #define DB_TXULP_NUM_POSTED_SHIFT       (16)    /* bits 16 - 29 */
 150 #define DB_TXULP_NUM_POSTED_MASK        0x3FFF  /* bits 16 - 29 */
 151
 152 /********** RQ(erx) door bell ************/
 153 #define DB_RQ_OFFSET                    0x100
 154 #define DB_RQ_RING_ID_MASK              0x3FF   /* bits 0 - 9 */
 155 /* Number of rx frags posted */
 156 #define DB_RQ_NUM_POSTED_SHIFT          (24)    /* bits 24 - 31 */
 157
 158 /********** MCC door bell ************/
 159 #define DB_MCCQ_OFFSET                  0x140
 160 #define DB_MCCQ_RING_ID_MASK            0x7FF   /* bits 0 - 10 */
 161 /* Number of entries posted */
 162 #define DB_MCCQ_NUM_POSTED_SHIFT        (16)    /* bits 16 - 29 */
 163
 164 /********** SRIOV VF PCICFG OFFSET ********/
 165 #define SRIOV_VF_PCICFG_OFFSET          (4096)
 166
 167 /********** FAT TABLE  ********/
 168 #define RETRIEVE_FAT    0
 169 #define QUERY_FAT       1
 170
 171 /* Flashrom related descriptors */
 172 #define MAX_FLASH_COMP                  32
 173 #define IMAGE_TYPE_FIRMWARE             160
 174 #define IMAGE_TYPE_BOOTCODE             224
 175 #define IMAGE_TYPE_OPTIONROM            32
 176
 177 #define NUM_FLASHDIR_ENTRIES            32
 178
 179 #define OPTYPE_ISCSI_ACTIVE             0
 180 #define OPTYPE_REDBOOT                  1
 181 #define OPTYPE_BIOS                     2
 182 #define OPTYPE_PXE_BIOS                 3
 183 #define OPTYPE_FCOE_BIOS                8
 184 #define OPTYPE_ISCSI_BACKUP             9
 185 #define OPTYPE_FCOE_FW_ACTIVE           10
 186 #define OPTYPE_FCOE_FW_BACKUP           11
 187 #define OPTYPE_NCSI_FW                  13
 188 #define OPTYPE_PHY_FW                   99
 189 #define TN_8022                         13
 190
 191 #define ILLEGAL_IOCTL_REQ               2
 192 #define FLASHROM_OPER_PHY_FLASH         9
 193 #define FLASHROM_OPER_PHY_SAVE          10
 194 #define FLASHROM_OPER_FLASH             1
 195 #define FLASHROM_OPER_SAVE              2
 196 #define FLASHROM_OPER_REPORT            4
 197
 198 #define FLASH_IMAGE_MAX_SIZE_g2         (1310720) /* Max firmware image size */
 199 #define FLASH_BIOS_IMAGE_MAX_SIZE_g2    (262144)  /* Max OPTION ROM image sz */
 200 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2 (262144)  /* Max Redboot image sz    */
 201 #define FLASH_IMAGE_MAX_SIZE_g3         (2097152) /* Max firmware image size */
 202 #define FLASH_BIOS_IMAGE_MAX_SIZE_g3    (524288)  /* Max OPTION ROM image sz */
 203 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 (1048576)  /* Max Redboot image sz    */
 204 #define FLASH_NCSI_IMAGE_MAX_SIZE_g3    (262144)
 205 #define FLASH_PHY_FW_IMAGE_MAX_SIZE_g3  262144
 206
 207 #define FLASH_NCSI_MAGIC                (0x16032009)
 208 #define FLASH_NCSI_DISABLED             (0)
 209 #define FLASH_NCSI_ENABLED              (1)
 210
 211 #define FLASH_NCSI_BITFILE_HDR_OFFSET   (0x600000)
 212
 213 /* Offsets for components on Flash. */
 214 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 (1048576)
 215 #define FLASH_iSCSI_BACKUP_IMAGE_START_g2  (2359296)
 216 #define FLASH_FCoE_PRIMARY_IMAGE_START_g2  (3670016)
 217 #define FLASH_FCoE_BACKUP_IMAGE_START_g2   (4980736)
 218 #define FLASH_iSCSI_BIOS_START_g2          (7340032)
 219 #define FLASH_PXE_BIOS_START_g2            (7864320)
 220 #define FLASH_FCoE_BIOS_START_g2           (524288)
 221 #define FLASH_REDBOOT_START_g2            (0)
 222
 223 #define FLASH_NCSI_START_g3                (15990784)
 224 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 (2097152)
 225 #define FLASH_iSCSI_BACKUP_IMAGE_START_g3  (4194304)
 226 #define FLASH_FCoE_PRIMARY_IMAGE_START_g3  (6291456)
 227 #define FLASH_FCoE_BACKUP_IMAGE_START_g3   (8388608)
 228 #define FLASH_iSCSI_BIOS_START_g3          (12582912)
 229 #define FLASH_PXE_BIOS_START_g3            (13107200)
 230 #define FLASH_FCoE_BIOS_START_g3           (13631488)
 231 #define FLASH_REDBOOT_START_g3             (262144)
 232 #define FLASH_PHY_FW_START_g3              1310720
 233
 234 #define IMAGE_NCSI                      16
 235 #define IMAGE_OPTION_ROM_PXE            32
 236 #define IMAGE_OPTION_ROM_FCoE           33
 237 #define IMAGE_OPTION_ROM_ISCSI          34
 238 #define IMAGE_FLASHISM_JUMPVECTOR       48
 239 #define IMAGE_FLASH_ISM                 49
 240 #define IMAGE_JUMP_VECTOR               50
 241 #define IMAGE_FIRMWARE_iSCSI            160
 242 #define IMAGE_FIRMWARE_COMP_iSCSI       161
 243 #define IMAGE_FIRMWARE_FCoE             162
 244 #define IMAGE_FIRMWARE_COMP_FCoE        163
 245 #define IMAGE_FIRMWARE_BACKUP_iSCSI     176
 246 #define IMAGE_FIRMWARE_BACKUP_COMP_iSCSI 177
 247 #define IMAGE_FIRMWARE_BACKUP_FCoE      178
 248 #define IMAGE_FIRMWARE_BACKUP_COMP_FCoE 179
 249 #define IMAGE_FIRMWARE_PHY              192
 250 #define IMAGE_BOOT_CODE                 224
 251
 252 /************* Rx Packet Type Encoding **************/
 253 #define BE_UNICAST_PACKET               0
 254 #define BE_MULTICAST_PACKET             1
 255 #define BE_BROADCAST_PACKET             2
 256 #define BE_RSVD_PACKET                  3
 257
 258 /*
 259  * BE descriptors: host memory data structures whose formats
 260  * are hardwired in BE silicon.
 261  */
 262 /* Event Queue Descriptor */
 263 #define EQ_ENTRY_VALID_MASK             0x1     /* bit 0 */
 264 #define EQ_ENTRY_RES_ID_MASK            0xFFFF  /* bits 16 - 31 */
 265 #define EQ_ENTRY_RES_ID_SHIFT           16
 266
 267 struct be_eq_entry {
 268         u32 evt;
 269 };
 270
 271 /* TX Queue Descriptor */
 272 #define ETH_WRB_FRAG_LEN_MASK           0xFFFF
 273 struct be_eth_wrb {
 274         u32 frag_pa_hi;         /* dword 0 */
 275         u32 frag_pa_lo;         /* dword 1 */
 276         u32 rsvd0;              /* dword 2 */
 277         u32 frag_len;           /* dword 3: bits 0 - 15 */
 278 } __packed;
 279
 280 /* Pseudo amap definition for eth_hdr_wrb in which each bit of the
 281  * actual structure is defined as a byte : used to calculate
 282  * offset/shift/mask of each field */
 283 struct amap_eth_hdr_wrb {
 284         u8 rsvd0[32];           /* dword 0 */
 285         u8 rsvd1[32];           /* dword 1 */
 286         u8 complete;            /* dword 2 */
 287         u8 event;
 288         u8 crc;
 289         u8 forward;
 290         u8 lso6;
 291         u8 mgmt;
 292         u8 ipcs;
 293         u8 udpcs;
 294         u8 tcpcs;
 295         u8 lso;
 296         u8 vlan;
 297         u8 gso[2];
 298         u8 num_wrb[5];
 299         u8 lso_mss[14];
 300         u8 len[16];             /* dword 3 */
 301         u8 vlan_tag[16];
 302 } __packed;
 303
 304 struct be_eth_hdr_wrb {
 305         u32 dw[4];
 306 };
 307
 308 /* TX Compl Queue Descriptor */
 309
 310 /* Pseudo amap definition for eth_tx_compl in which each bit of the
 311  * actual structure is defined as a byte: used to calculate
 312  * offset/shift/mask of each field */
 313 struct amap_eth_tx_compl {
 314         u8 wrb_index[16];       /* dword 0 */
 315         u8 ct[2];               /* dword 0 */
 316         u8 port[2];             /* dword 0 */
 317         u8 rsvd0[8];            /* dword 0 */
 318         u8 status[4];           /* dword 0 */
 319         u8 user_bytes[16];      /* dword 1 */
 320         u8 nwh_bytes[8];        /* dword 1 */
 321         u8 lso;                 /* dword 1 */
 322         u8 cast_enc[2];         /* dword 1 */
 323         u8 rsvd1[5];            /* dword 1 */
 324         u8 rsvd2[32];           /* dword 2 */
 325         u8 pkts[16];            /* dword 3 */
 326         u8 ringid[11];          /* dword 3 */
 327         u8 hash_val[4];         /* dword 3 */
 328         u8 valid;               /* dword 3 */
 329 } __packed;
 330
 331 struct be_eth_tx_compl {
 332         u32 dw[4];
 333 };
 334
 335 /* RX Queue Descriptor */
 336 struct be_eth_rx_d {
 337         u32 fragpa_hi;
 338         u32 fragpa_lo;
 339 };
 340
 341 /* RX Compl Queue Descriptor */
 342
 343 /* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which
 344  * each bit of the actual structure is defined as a byte: used to calculate
 345  * offset/shift/mask of each field */
 346 struct amap_eth_rx_compl_v0 {
 347         u8 vlan_tag[16];        /* dword 0 */
 348         u8 pktsize[14];         /* dword 0 */
 349         u8 port;                /* dword 0 */
 350         u8 ip_opt;              /* dword 0 */
 351         u8 err;                 /* dword 1 */
 352         u8 rsshp;               /* dword 1 */
 353         u8 ipf;                 /* dword 1 */
 354         u8 tcpf;                /* dword 1 */
 355         u8 udpf;                /* dword 1 */
 356         u8 ipcksm;              /* dword 1 */
 357         u8 l4_cksm;             /* dword 1 */
 358         u8 ip_version;          /* dword 1 */
 359         u8 macdst[6];           /* dword 1 */
 360         u8 vtp;                 /* dword 1 */
 361         u8 rsvd0;               /* dword 1 */
 362         u8 fragndx[10];         /* dword 1 */
 363         u8 ct[2];               /* dword 1 */
 364         u8 sw;                  /* dword 1 */
 365         u8 numfrags[3];         /* dword 1 */
 366         u8 rss_flush;           /* dword 2 */
 367         u8 cast_enc[2];         /* dword 2 */
 368         u8 vtm;                 /* dword 2 */
 369         u8 rss_bank;            /* dword 2 */
 370         u8 rsvd1[23];           /* dword 2 */
 371         u8 lro_pkt;             /* dword 2 */
 372         u8 rsvd2[2];            /* dword 2 */
 373         u8 valid;               /* dword 2 */
 374         u8 rsshash[32];         /* dword 3 */
 375 } __packed;
 376
 377 /* Pseudo amap definition for BE3 native mode eth_rx_compl in which
 378  * each bit of the actual structure is defined as a byte: used to calculate
 379  * offset/shift/mask of each field */
 380 struct amap_eth_rx_compl_v1 {
 381         u8 vlan_tag[16];        /* dword 0 */
 382         u8 pktsize[14];         /* dword 0 */
 383         u8 vtp;                 /* dword 0 */
 384         u8 ip_opt;              /* dword 0 */
 385         u8 err;                 /* dword 1 */
 386         u8 rsshp;               /* dword 1 */
 387         u8 ipf;                 /* dword 1 */
 388         u8 tcpf;                /* dword 1 */
 389         u8 udpf;                /* dword 1 */
 390         u8 ipcksm;              /* dword 1 */
 391         u8 l4_cksm;             /* dword 1 */
 392         u8 ip_version;          /* dword 1 */
 393         u8 macdst[7];           /* dword 1 */
 394         u8 rsvd0;               /* dword 1 */
 395         u8 fragndx[10];         /* dword 1 */
 396         u8 ct[2];               /* dword 1 */
 397         u8 sw;                  /* dword 1 */
 398         u8 numfrags[3];         /* dword 1 */
 399         u8 rss_flush;           /* dword 2 */
 400         u8 cast_enc[2];         /* dword 2 */
 401         u8 vtm;                 /* dword 2 */
 402         u8 rss_bank;            /* dword 2 */
 403         u8 port[2];             /* dword 2 */
 404         u8 vntagp;              /* dword 2 */
 405         u8 header_len[8];       /* dword 2 */
 406         u8 header_split[2];     /* dword 2 */
 407         u8 rsvd1[13];           /* dword 2 */
 408         u8 valid;               /* dword 2 */
 409         u8 rsshash[32];         /* dword 3 */
 410 } __packed;
 411
 412 struct be_eth_rx_compl {
 413         u32 dw[4];
 414 };
 415
 416 struct mgmt_hba_attribs {
 417         u8 flashrom_version_string[32];
 418         u8 manufacturer_name[32];
 419         u32 supported_modes;
 420         u32 rsvd0[3];
 421         u8 ncsi_ver_string[12];
 422         u32 default_extended_timeout;
 423         u8 controller_model_number[32];
 424         u8 controller_description[64];
 425         u8 controller_serial_number[32];
 426         u8 ip_version_string[32];
 427         u8 firmware_version_string[32];
 428         u8 bios_version_string[32];
 429         u8 redboot_version_string[32];
 430         u8 driver_version_string[32];
 431         u8 fw_on_flash_version_string[32];
 432         u32 functionalities_supported;
 433         u16 max_cdblength;
 434         u8 asic_revision;
 435         u8 generational_guid[16];
 436         u8 hba_port_count;
 437         u16 default_link_down_timeout;
 438         u8 iscsi_ver_min_max;
 439         u8 multifunction_device;
 440         u8 cache_valid;
 441         u8 hba_status;
 442         u8 max_domains_supported;
 443         u8 phy_port;
 444         u32 firmware_post_status;
 445         u32 hba_mtu[8];
 446         u32 rsvd1[4];
 447 };
 448
 449 struct mgmt_controller_attrib {
 450         struct mgmt_hba_attribs hba_attribs;
 451         u16 pci_vendor_id;
 452         u16 pci_device_id;
 453         u16 pci_sub_vendor_id;
 454         u16 pci_sub_system_id;
 455         u8 pci_bus_number;
 456         u8 pci_device_number;
 457         u8 pci_function_number;
 458         u8 interface_type;
 459         u64 unique_identifier;
 460         u32 rsvd0[5];
 461 };
 462
 463 struct controller_id {
 464         u32 vendor;
 465         u32 device;
 466         u32 subvendor;
 467         u32 subdevice;
 468 };
 469
 470 struct flash_comp {
 471         unsigned long offset;
 472         int optype;
 473         int size;
 474         int img_type;
 475 };
 476
 477 struct image_hdr {
 478         u32 imageid;
 479         u32 imageoffset;
 480         u32 imagelength;
 481         u32 image_checksum;
 482         u8 image_version[32];
 483 };
 484 struct flash_file_hdr_g2 {
 485         u8 sign[32];
 486         u32 cksum;
 487         u32 antidote;
 488         struct controller_id cont_id;
 489         u32 file_len;
 490         u32 chunk_num;
 491         u32 total_chunks;
 492         u32 num_imgs;
 493         u8 build[24];
 494 };
 495
 496 struct flash_file_hdr_g3 {
 497         u8 sign[52];
 498         u8 ufi_version[4];
 499         u32 file_len;
 500         u32 cksum;
 501         u32 antidote;
 502         u32 num_imgs;
 503         u8 build[24];
 504         u8 asic_type_rev;
 505         u8 rsvd[31];
 506 };
 507
 508 struct flash_section_hdr {
 509         u32 format_rev;
 510         u32 cksum;
 511         u32 antidote;
 512         u32 num_images;
 513         u8 id_string[128];
 514         u32 rsvd[4];
 515 } __packed;
 516
 517 struct flash_section_hdr_g2 {
 518         u32 format_rev;
 519         u32 cksum;
 520         u32 antidote;
 521         u32 build_num;
 522         u8 id_string[128];
 523         u32 rsvd[8];
 524 } __packed;
 525
 526 struct flash_section_entry {
 527         u32 type;
 528         u32 offset;
 529         u32 pad_size;
 530         u32 image_size;
 531         u32 cksum;
 532         u32 entry_point;
 533         u32 rsvd0;
 534         u32 rsvd1;
 535         u8 ver_data[32];
 536 } __packed;
 537
 538 struct flash_section_info {
 539         u8 cookie[32];
 540         struct flash_section_hdr fsec_hdr;
 541         struct flash_section_entry fsec_entry[32];
 542 } __packed;
 543
 544 struct flash_section_info_g2 {
 545         u8 cookie[32];
 546         struct flash_section_hdr_g2 fsec_hdr;
 547         struct flash_section_entry fsec_entry[32];
 548 } __packed;