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[deliverable/linux.git] / drivers / net / ethernet / freescale / fec.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/spinlock.h>
38 #include <linux/workqueue.h>
39 #include <linux/bitops.h>
40 #include <linux/io.h>
41 #include <linux/irq.h>
42 #include <linux/clk.h>
43 #include <linux/platform_device.h>
44 #include <linux/phy.h>
45 #include <linux/fec.h>
46 #include <linux/of.h>
47 #include <linux/of_device.h>
48 #include <linux/of_gpio.h>
49 #include <linux/of_net.h>
50 #include <linux/pinctrl/consumer.h>
51 #include <linux/regulator/consumer.h>
52
53 #include <asm/cacheflush.h>
54
55 #ifndef CONFIG_ARM
56 #include <asm/coldfire.h>
57 #include <asm/mcfsim.h>
58 #endif
59
60 #include "fec.h"
61
62 #if defined(CONFIG_ARM)
63 #define FEC_ALIGNMENT 0xf
64 #else
65 #define FEC_ALIGNMENT 0x3
66 #endif
67
68 #define DRIVER_NAME "fec"
69 #define FEC_NAPI_WEIGHT 64
70
71 /* Pause frame feild and FIFO threshold */
72 #define FEC_ENET_FCE (1 << 5)
73 #define FEC_ENET_RSEM_V 0x84
74 #define FEC_ENET_RSFL_V 16
75 #define FEC_ENET_RAEM_V 0x8
76 #define FEC_ENET_RAFL_V 0x8
77 #define FEC_ENET_OPD_V 0xFFF0
78
79 /* Controller is ENET-MAC */
80 #define FEC_QUIRK_ENET_MAC (1 << 0)
81 /* Controller needs driver to swap frame */
82 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
83 /* Controller uses gasket */
84 #define FEC_QUIRK_USE_GASKET (1 << 2)
85 /* Controller has GBIT support */
86 #define FEC_QUIRK_HAS_GBIT (1 << 3)
87 /* Controller has extend desc buffer */
88 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
89
90 static struct platform_device_id fec_devtype[] = {
91 {
92 /* keep it for coldfire */
93 .name = DRIVER_NAME,
94 .driver_data = 0,
95 }, {
96 .name = "imx25-fec",
97 .driver_data = FEC_QUIRK_USE_GASKET,
98 }, {
99 .name = "imx27-fec",
100 .driver_data = 0,
101 }, {
102 .name = "imx28-fec",
103 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
104 }, {
105 .name = "imx6q-fec",
106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
107 FEC_QUIRK_HAS_BUFDESC_EX,
108 }, {
109 /* sentinel */
110 }
111 };
112 MODULE_DEVICE_TABLE(platform, fec_devtype);
113
114 enum imx_fec_type {
115 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
116 IMX27_FEC, /* runs on i.mx27/35/51 */
117 IMX28_FEC,
118 IMX6Q_FEC,
119 };
120
121 static const struct of_device_id fec_dt_ids[] = {
122 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
123 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
124 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
125 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
126 { /* sentinel */ }
127 };
128 MODULE_DEVICE_TABLE(of, fec_dt_ids);
129
130 static unsigned char macaddr[ETH_ALEN];
131 module_param_array(macaddr, byte, NULL, 0);
132 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
133
134 #if defined(CONFIG_M5272)
135 /*
136 * Some hardware gets it MAC address out of local flash memory.
137 * if this is non-zero then assume it is the address to get MAC from.
138 */
139 #if defined(CONFIG_NETtel)
140 #define FEC_FLASHMAC 0xf0006006
141 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
142 #define FEC_FLASHMAC 0xf0006000
143 #elif defined(CONFIG_CANCam)
144 #define FEC_FLASHMAC 0xf0020000
145 #elif defined (CONFIG_M5272C3)
146 #define FEC_FLASHMAC (0xffe04000 + 4)
147 #elif defined(CONFIG_MOD5272)
148 #define FEC_FLASHMAC 0xffc0406b
149 #else
150 #define FEC_FLASHMAC 0
151 #endif
152 #endif /* CONFIG_M5272 */
153
154 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
155 #error "FEC: descriptor ring size constants too large"
156 #endif
157
158 /* Interrupt events/masks. */
159 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
160 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
161 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
162 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
163 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
164 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
165 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
166 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
167 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
168 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
169
170 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
171 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
172
173 /* The FEC stores dest/src/type, data, and checksum for receive packets.
174 */
175 #define PKT_MAXBUF_SIZE 1518
176 #define PKT_MINBUF_SIZE 64
177 #define PKT_MAXBLR_SIZE 1520
178
179 /*
180 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
181 * size bits. Other FEC hardware does not, so we need to take that into
182 * account when setting it.
183 */
184 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
185 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
186 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
187 #else
188 #define OPT_FRAME_SIZE 0
189 #endif
190
191 /* FEC MII MMFR bits definition */
192 #define FEC_MMFR_ST (1 << 30)
193 #define FEC_MMFR_OP_READ (2 << 28)
194 #define FEC_MMFR_OP_WRITE (1 << 28)
195 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
196 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
197 #define FEC_MMFR_TA (2 << 16)
198 #define FEC_MMFR_DATA(v) (v & 0xffff)
199
200 #define FEC_MII_TIMEOUT 30000 /* us */
201
202 /* Transmitter timeout */
203 #define TX_TIMEOUT (2 * HZ)
204
205 #define FEC_PAUSE_FLAG_AUTONEG 0x1
206 #define FEC_PAUSE_FLAG_ENABLE 0x2
207
208 static int mii_cnt;
209
210 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
211 {
212 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
213 if (is_ex)
214 return (struct bufdesc *)(ex + 1);
215 else
216 return bdp + 1;
217 }
218
219 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex)
220 {
221 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
222 if (is_ex)
223 return (struct bufdesc *)(ex - 1);
224 else
225 return bdp - 1;
226 }
227
228 static void *swap_buffer(void *bufaddr, int len)
229 {
230 int i;
231 unsigned int *buf = bufaddr;
232
233 for (i = 0; i < (len + 3) / 4; i++, buf++)
234 *buf = cpu_to_be32(*buf);
235
236 return bufaddr;
237 }
238
239 static netdev_tx_t
240 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
241 {
242 struct fec_enet_private *fep = netdev_priv(ndev);
243 const struct platform_device_id *id_entry =
244 platform_get_device_id(fep->pdev);
245 struct bufdesc *bdp;
246 void *bufaddr;
247 unsigned short status;
248 unsigned int index;
249
250 if (!fep->link) {
251 /* Link is down or autonegotiation is in progress. */
252 return NETDEV_TX_BUSY;
253 }
254
255 /* Fill in a Tx ring entry */
256 bdp = fep->cur_tx;
257
258 status = bdp->cbd_sc;
259
260 if (status & BD_ENET_TX_READY) {
261 /* Ooops. All transmit buffers are full. Bail out.
262 * This should not happen, since ndev->tbusy should be set.
263 */
264 printk("%s: tx queue full!.\n", ndev->name);
265 return NETDEV_TX_BUSY;
266 }
267
268 /* Clear all of the status flags */
269 status &= ~BD_ENET_TX_STATS;
270
271 /* Set buffer length and buffer pointer */
272 bufaddr = skb->data;
273 bdp->cbd_datlen = skb->len;
274
275 /*
276 * On some FEC implementations data must be aligned on
277 * 4-byte boundaries. Use bounce buffers to copy data
278 * and get it aligned. Ugh.
279 */
280 if (fep->bufdesc_ex)
281 index = (struct bufdesc_ex *)bdp -
282 (struct bufdesc_ex *)fep->tx_bd_base;
283 else
284 index = bdp - fep->tx_bd_base;
285
286 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
287 memcpy(fep->tx_bounce[index], skb->data, skb->len);
288 bufaddr = fep->tx_bounce[index];
289 }
290
291 /*
292 * Some design made an incorrect assumption on endian mode of
293 * the system that it's running on. As the result, driver has to
294 * swap every frame going to and coming from the controller.
295 */
296 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
297 swap_buffer(bufaddr, skb->len);
298
299 /* Save skb pointer */
300 fep->tx_skbuff[index] = skb;
301
302 /* Push the data cache so the CPM does not get stale memory
303 * data.
304 */
305 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
306 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
307
308 /* Send it on its way. Tell FEC it's ready, interrupt when done,
309 * it's the last BD of the frame, and to put the CRC on the end.
310 */
311 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
312 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
313 bdp->cbd_sc = status;
314
315 if (fep->bufdesc_ex) {
316
317 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
318 ebdp->cbd_bdu = 0;
319 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
320 fep->hwts_tx_en)) {
321 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
322 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
323 } else {
324
325 ebdp->cbd_esc = BD_ENET_TX_INT;
326 }
327 }
328 /* If this was the last BD in the ring, start at the beginning again. */
329 if (status & BD_ENET_TX_WRAP)
330 bdp = fep->tx_bd_base;
331 else
332 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
333
334 fep->cur_tx = bdp;
335
336 if (fep->cur_tx == fep->dirty_tx)
337 netif_stop_queue(ndev);
338
339 /* Trigger transmission start */
340 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
341
342 skb_tx_timestamp(skb);
343
344 return NETDEV_TX_OK;
345 }
346
347 /* This function is called to start or restart the FEC during a link
348 * change. This only happens when switching between half and full
349 * duplex.
350 */
351 static void
352 fec_restart(struct net_device *ndev, int duplex)
353 {
354 struct fec_enet_private *fep = netdev_priv(ndev);
355 const struct platform_device_id *id_entry =
356 platform_get_device_id(fep->pdev);
357 int i;
358 u32 temp_mac[2];
359 u32 rcntl = OPT_FRAME_SIZE | 0x04;
360 u32 ecntl = 0x2; /* ETHEREN */
361
362 /* Whack a reset. We should wait for this. */
363 writel(1, fep->hwp + FEC_ECNTRL);
364 udelay(10);
365
366 /*
367 * enet-mac reset will reset mac address registers too,
368 * so need to reconfigure it.
369 */
370 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
371 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
372 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
373 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
374 }
375
376 /* Clear any outstanding interrupt. */
377 writel(0xffc00000, fep->hwp + FEC_IEVENT);
378
379 /* Reset all multicast. */
380 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
381 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
382 #ifndef CONFIG_M5272
383 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
384 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
385 #endif
386
387 /* Set maximum receive buffer size. */
388 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
389
390 /* Set receive and transmit descriptor base. */
391 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
392 if (fep->bufdesc_ex)
393 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
394 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
395 else
396 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
397 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
398
399 fep->cur_rx = fep->rx_bd_base;
400
401 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
402 if (fep->tx_skbuff[i]) {
403 dev_kfree_skb_any(fep->tx_skbuff[i]);
404 fep->tx_skbuff[i] = NULL;
405 }
406 }
407
408 /* Enable MII mode */
409 if (duplex) {
410 /* FD enable */
411 writel(0x04, fep->hwp + FEC_X_CNTRL);
412 } else {
413 /* No Rcv on Xmit */
414 rcntl |= 0x02;
415 writel(0x0, fep->hwp + FEC_X_CNTRL);
416 }
417
418 fep->full_duplex = duplex;
419
420 /* Set MII speed */
421 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
422
423 /*
424 * The phy interface and speed need to get configured
425 * differently on enet-mac.
426 */
427 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
428 /* Enable flow control and length check */
429 rcntl |= 0x40000000 | 0x00000020;
430
431 /* RGMII, RMII or MII */
432 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
433 rcntl |= (1 << 6);
434 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
435 rcntl |= (1 << 8);
436 else
437 rcntl &= ~(1 << 8);
438
439 /* 1G, 100M or 10M */
440 if (fep->phy_dev) {
441 if (fep->phy_dev->speed == SPEED_1000)
442 ecntl |= (1 << 5);
443 else if (fep->phy_dev->speed == SPEED_100)
444 rcntl &= ~(1 << 9);
445 else
446 rcntl |= (1 << 9);
447 }
448 } else {
449 #ifdef FEC_MIIGSK_ENR
450 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
451 u32 cfgr;
452 /* disable the gasket and wait */
453 writel(0, fep->hwp + FEC_MIIGSK_ENR);
454 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
455 udelay(1);
456
457 /*
458 * configure the gasket:
459 * RMII, 50 MHz, no loopback, no echo
460 * MII, 25 MHz, no loopback, no echo
461 */
462 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
463 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
464 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
465 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
466 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
467
468 /* re-enable the gasket */
469 writel(2, fep->hwp + FEC_MIIGSK_ENR);
470 }
471 #endif
472 }
473
474 /* enable pause frame*/
475 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
476 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
477 fep->phy_dev && fep->phy_dev->pause)) {
478 rcntl |= FEC_ENET_FCE;
479
480 /* set FIFO thresh hold parameter to reduce overrun */
481 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
482 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
483 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
484 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
485
486 /* OPD */
487 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
488 } else {
489 rcntl &= ~FEC_ENET_FCE;
490 }
491
492 writel(rcntl, fep->hwp + FEC_R_CNTRL);
493
494 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
495 /* enable ENET endian swap */
496 ecntl |= (1 << 8);
497 /* enable ENET store and forward mode */
498 writel(1 << 8, fep->hwp + FEC_X_WMRK);
499 }
500
501 if (fep->bufdesc_ex)
502 ecntl |= (1 << 4);
503
504 /* And last, enable the transmit and receive processing */
505 writel(ecntl, fep->hwp + FEC_ECNTRL);
506 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
507
508 if (fep->bufdesc_ex)
509 fec_ptp_start_cyclecounter(ndev);
510
511 /* Enable interrupts we wish to service */
512 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
513 }
514
515 static void
516 fec_stop(struct net_device *ndev)
517 {
518 struct fec_enet_private *fep = netdev_priv(ndev);
519 const struct platform_device_id *id_entry =
520 platform_get_device_id(fep->pdev);
521 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
522
523 /* We cannot expect a graceful transmit stop without link !!! */
524 if (fep->link) {
525 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
526 udelay(10);
527 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
528 printk("fec_stop : Graceful transmit stop did not complete !\n");
529 }
530
531 /* Whack a reset. We should wait for this. */
532 writel(1, fep->hwp + FEC_ECNTRL);
533 udelay(10);
534 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
535 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
536
537 /* We have to keep ENET enabled to have MII interrupt stay working */
538 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
539 writel(2, fep->hwp + FEC_ECNTRL);
540 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
541 }
542 }
543
544
545 static void
546 fec_timeout(struct net_device *ndev)
547 {
548 struct fec_enet_private *fep = netdev_priv(ndev);
549
550 ndev->stats.tx_errors++;
551
552 fec_restart(ndev, fep->full_duplex);
553 netif_wake_queue(ndev);
554 }
555
556 static void
557 fec_enet_tx(struct net_device *ndev)
558 {
559 struct fec_enet_private *fep;
560 struct bufdesc *bdp;
561 unsigned short status;
562 struct sk_buff *skb;
563 int index = 0;
564
565 fep = netdev_priv(ndev);
566 bdp = fep->dirty_tx;
567
568 /* get next bdp of dirty_tx */
569 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
570 bdp = fep->tx_bd_base;
571 else
572 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
573
574 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
575
576 /* current queue is empty */
577 if (bdp == fep->cur_tx)
578 break;
579
580 if (fep->bufdesc_ex)
581 index = (struct bufdesc_ex *)bdp -
582 (struct bufdesc_ex *)fep->tx_bd_base;
583 else
584 index = bdp - fep->tx_bd_base;
585
586 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
587 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
588 bdp->cbd_bufaddr = 0;
589
590 skb = fep->tx_skbuff[index];
591
592 /* Check for errors. */
593 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
594 BD_ENET_TX_RL | BD_ENET_TX_UN |
595 BD_ENET_TX_CSL)) {
596 ndev->stats.tx_errors++;
597 if (status & BD_ENET_TX_HB) /* No heartbeat */
598 ndev->stats.tx_heartbeat_errors++;
599 if (status & BD_ENET_TX_LC) /* Late collision */
600 ndev->stats.tx_window_errors++;
601 if (status & BD_ENET_TX_RL) /* Retrans limit */
602 ndev->stats.tx_aborted_errors++;
603 if (status & BD_ENET_TX_UN) /* Underrun */
604 ndev->stats.tx_fifo_errors++;
605 if (status & BD_ENET_TX_CSL) /* Carrier lost */
606 ndev->stats.tx_carrier_errors++;
607 } else {
608 ndev->stats.tx_packets++;
609 }
610
611 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
612 fep->bufdesc_ex) {
613 struct skb_shared_hwtstamps shhwtstamps;
614 unsigned long flags;
615 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
616
617 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
618 spin_lock_irqsave(&fep->tmreg_lock, flags);
619 shhwtstamps.hwtstamp = ns_to_ktime(
620 timecounter_cyc2time(&fep->tc, ebdp->ts));
621 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
622 skb_tstamp_tx(skb, &shhwtstamps);
623 }
624
625 if (status & BD_ENET_TX_READY)
626 printk("HEY! Enet xmit interrupt and TX_READY.\n");
627
628 /* Deferred means some collisions occurred during transmit,
629 * but we eventually sent the packet OK.
630 */
631 if (status & BD_ENET_TX_DEF)
632 ndev->stats.collisions++;
633
634 /* Free the sk buffer associated with this last transmit */
635 dev_kfree_skb_any(skb);
636 fep->tx_skbuff[index] = NULL;
637
638 fep->dirty_tx = bdp;
639
640 /* Update pointer to next buffer descriptor to be transmitted */
641 if (status & BD_ENET_TX_WRAP)
642 bdp = fep->tx_bd_base;
643 else
644 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
645
646 /* Since we have freed up a buffer, the ring is no longer full
647 */
648 if (fep->dirty_tx != fep->cur_tx) {
649 if (netif_queue_stopped(ndev))
650 netif_wake_queue(ndev);
651 }
652 }
653 return;
654 }
655
656
657 /* During a receive, the cur_rx points to the current incoming buffer.
658 * When we update through the ring, if the next incoming buffer has
659 * not been given to the system, we just set the empty indicator,
660 * effectively tossing the packet.
661 */
662 static int
663 fec_enet_rx(struct net_device *ndev, int budget)
664 {
665 struct fec_enet_private *fep = netdev_priv(ndev);
666 const struct platform_device_id *id_entry =
667 platform_get_device_id(fep->pdev);
668 struct bufdesc *bdp;
669 unsigned short status;
670 struct sk_buff *skb;
671 ushort pkt_len;
672 __u8 *data;
673 int pkt_received = 0;
674
675 #ifdef CONFIG_M532x
676 flush_cache_all();
677 #endif
678
679 /* First, grab all of the stats for the incoming packet.
680 * These get messed up if we get called due to a busy condition.
681 */
682 bdp = fep->cur_rx;
683
684 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
685
686 if (pkt_received >= budget)
687 break;
688 pkt_received++;
689
690 /* Since we have allocated space to hold a complete frame,
691 * the last indicator should be set.
692 */
693 if ((status & BD_ENET_RX_LAST) == 0)
694 printk("FEC ENET: rcv is not +last\n");
695
696 if (!fep->opened)
697 goto rx_processing_done;
698
699 /* Check for errors. */
700 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
701 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
702 ndev->stats.rx_errors++;
703 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
704 /* Frame too long or too short. */
705 ndev->stats.rx_length_errors++;
706 }
707 if (status & BD_ENET_RX_NO) /* Frame alignment */
708 ndev->stats.rx_frame_errors++;
709 if (status & BD_ENET_RX_CR) /* CRC Error */
710 ndev->stats.rx_crc_errors++;
711 if (status & BD_ENET_RX_OV) /* FIFO overrun */
712 ndev->stats.rx_fifo_errors++;
713 }
714
715 /* Report late collisions as a frame error.
716 * On this error, the BD is closed, but we don't know what we
717 * have in the buffer. So, just drop this frame on the floor.
718 */
719 if (status & BD_ENET_RX_CL) {
720 ndev->stats.rx_errors++;
721 ndev->stats.rx_frame_errors++;
722 goto rx_processing_done;
723 }
724
725 /* Process the incoming frame. */
726 ndev->stats.rx_packets++;
727 pkt_len = bdp->cbd_datlen;
728 ndev->stats.rx_bytes += pkt_len;
729 data = (__u8*)__va(bdp->cbd_bufaddr);
730
731 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
732 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
733
734 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
735 swap_buffer(data, pkt_len);
736
737 /* This does 16 byte alignment, exactly what we need.
738 * The packet length includes FCS, but we don't want to
739 * include that when passing upstream as it messes up
740 * bridging applications.
741 */
742 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
743
744 if (unlikely(!skb)) {
745 ndev->stats.rx_dropped++;
746 } else {
747 skb_reserve(skb, NET_IP_ALIGN);
748 skb_put(skb, pkt_len - 4); /* Make room */
749 skb_copy_to_linear_data(skb, data, pkt_len - 4);
750 skb->protocol = eth_type_trans(skb, ndev);
751
752 /* Get receive timestamp from the skb */
753 if (fep->hwts_rx_en && fep->bufdesc_ex) {
754 struct skb_shared_hwtstamps *shhwtstamps =
755 skb_hwtstamps(skb);
756 unsigned long flags;
757 struct bufdesc_ex *ebdp =
758 (struct bufdesc_ex *)bdp;
759
760 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
761
762 spin_lock_irqsave(&fep->tmreg_lock, flags);
763 shhwtstamps->hwtstamp = ns_to_ktime(
764 timecounter_cyc2time(&fep->tc, ebdp->ts));
765 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
766 }
767
768 if (!skb_defer_rx_timestamp(skb))
769 napi_gro_receive(&fep->napi, skb);
770 }
771
772 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
773 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
774 rx_processing_done:
775 /* Clear the status flags for this buffer */
776 status &= ~BD_ENET_RX_STATS;
777
778 /* Mark the buffer empty */
779 status |= BD_ENET_RX_EMPTY;
780 bdp->cbd_sc = status;
781
782 if (fep->bufdesc_ex) {
783 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
784
785 ebdp->cbd_esc = BD_ENET_RX_INT;
786 ebdp->cbd_prot = 0;
787 ebdp->cbd_bdu = 0;
788 }
789
790 /* Update BD pointer to next entry */
791 if (status & BD_ENET_RX_WRAP)
792 bdp = fep->rx_bd_base;
793 else
794 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
795 /* Doing this here will keep the FEC running while we process
796 * incoming frames. On a heavily loaded network, we should be
797 * able to keep up at the expense of system resources.
798 */
799 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
800 }
801 fep->cur_rx = bdp;
802
803 return pkt_received;
804 }
805
806 static irqreturn_t
807 fec_enet_interrupt(int irq, void *dev_id)
808 {
809 struct net_device *ndev = dev_id;
810 struct fec_enet_private *fep = netdev_priv(ndev);
811 uint int_events;
812 irqreturn_t ret = IRQ_NONE;
813
814 do {
815 int_events = readl(fep->hwp + FEC_IEVENT);
816 writel(int_events, fep->hwp + FEC_IEVENT);
817
818 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
819 ret = IRQ_HANDLED;
820
821 /* Disable the RX interrupt */
822 if (napi_schedule_prep(&fep->napi)) {
823 writel(FEC_RX_DISABLED_IMASK,
824 fep->hwp + FEC_IMASK);
825 __napi_schedule(&fep->napi);
826 }
827 }
828
829 if (int_events & FEC_ENET_MII) {
830 ret = IRQ_HANDLED;
831 complete(&fep->mdio_done);
832 }
833 } while (int_events);
834
835 return ret;
836 }
837
838 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
839 {
840 struct net_device *ndev = napi->dev;
841 int pkts = fec_enet_rx(ndev, budget);
842 struct fec_enet_private *fep = netdev_priv(ndev);
843
844 fec_enet_tx(ndev);
845
846 if (pkts < budget) {
847 napi_complete(napi);
848 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
849 }
850 return pkts;
851 }
852
853 /* ------------------------------------------------------------------------- */
854 static void fec_get_mac(struct net_device *ndev)
855 {
856 struct fec_enet_private *fep = netdev_priv(ndev);
857 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
858 unsigned char *iap, tmpaddr[ETH_ALEN];
859
860 /*
861 * try to get mac address in following order:
862 *
863 * 1) module parameter via kernel command line in form
864 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
865 */
866 iap = macaddr;
867
868 #ifdef CONFIG_OF
869 /*
870 * 2) from device tree data
871 */
872 if (!is_valid_ether_addr(iap)) {
873 struct device_node *np = fep->pdev->dev.of_node;
874 if (np) {
875 const char *mac = of_get_mac_address(np);
876 if (mac)
877 iap = (unsigned char *) mac;
878 }
879 }
880 #endif
881
882 /*
883 * 3) from flash or fuse (via platform data)
884 */
885 if (!is_valid_ether_addr(iap)) {
886 #ifdef CONFIG_M5272
887 if (FEC_FLASHMAC)
888 iap = (unsigned char *)FEC_FLASHMAC;
889 #else
890 if (pdata)
891 iap = (unsigned char *)&pdata->mac;
892 #endif
893 }
894
895 /*
896 * 4) FEC mac registers set by bootloader
897 */
898 if (!is_valid_ether_addr(iap)) {
899 *((unsigned long *) &tmpaddr[0]) =
900 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
901 *((unsigned short *) &tmpaddr[4]) =
902 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
903 iap = &tmpaddr[0];
904 }
905
906 memcpy(ndev->dev_addr, iap, ETH_ALEN);
907
908 /* Adjust MAC if using macaddr */
909 if (iap == macaddr)
910 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
911 }
912
913 /* ------------------------------------------------------------------------- */
914
915 /*
916 * Phy section
917 */
918 static void fec_enet_adjust_link(struct net_device *ndev)
919 {
920 struct fec_enet_private *fep = netdev_priv(ndev);
921 struct phy_device *phy_dev = fep->phy_dev;
922 unsigned long flags;
923
924 int status_change = 0;
925
926 spin_lock_irqsave(&fep->hw_lock, flags);
927
928 /* Prevent a state halted on mii error */
929 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
930 phy_dev->state = PHY_RESUMING;
931 goto spin_unlock;
932 }
933
934 /* Duplex link change */
935 if (phy_dev->link) {
936 if (fep->full_duplex != phy_dev->duplex) {
937 fec_restart(ndev, phy_dev->duplex);
938 /* prevent unnecessary second fec_restart() below */
939 fep->link = phy_dev->link;
940 status_change = 1;
941 }
942 }
943
944 /* Link on or off change */
945 if (phy_dev->link != fep->link) {
946 fep->link = phy_dev->link;
947 if (phy_dev->link)
948 fec_restart(ndev, phy_dev->duplex);
949 else
950 fec_stop(ndev);
951 status_change = 1;
952 }
953
954 spin_unlock:
955 spin_unlock_irqrestore(&fep->hw_lock, flags);
956
957 if (status_change)
958 phy_print_status(phy_dev);
959 }
960
961 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
962 {
963 struct fec_enet_private *fep = bus->priv;
964 unsigned long time_left;
965
966 fep->mii_timeout = 0;
967 init_completion(&fep->mdio_done);
968
969 /* start a read op */
970 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
971 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
972 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
973
974 /* wait for end of transfer */
975 time_left = wait_for_completion_timeout(&fep->mdio_done,
976 usecs_to_jiffies(FEC_MII_TIMEOUT));
977 if (time_left == 0) {
978 fep->mii_timeout = 1;
979 printk(KERN_ERR "FEC: MDIO read timeout\n");
980 return -ETIMEDOUT;
981 }
982
983 /* return value */
984 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
985 }
986
987 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
988 u16 value)
989 {
990 struct fec_enet_private *fep = bus->priv;
991 unsigned long time_left;
992
993 fep->mii_timeout = 0;
994 init_completion(&fep->mdio_done);
995
996 /* start a write op */
997 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
998 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
999 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1000 fep->hwp + FEC_MII_DATA);
1001
1002 /* wait for end of transfer */
1003 time_left = wait_for_completion_timeout(&fep->mdio_done,
1004 usecs_to_jiffies(FEC_MII_TIMEOUT));
1005 if (time_left == 0) {
1006 fep->mii_timeout = 1;
1007 printk(KERN_ERR "FEC: MDIO write timeout\n");
1008 return -ETIMEDOUT;
1009 }
1010
1011 return 0;
1012 }
1013
1014 static int fec_enet_mdio_reset(struct mii_bus *bus)
1015 {
1016 return 0;
1017 }
1018
1019 static int fec_enet_mii_probe(struct net_device *ndev)
1020 {
1021 struct fec_enet_private *fep = netdev_priv(ndev);
1022 const struct platform_device_id *id_entry =
1023 platform_get_device_id(fep->pdev);
1024 struct phy_device *phy_dev = NULL;
1025 char mdio_bus_id[MII_BUS_ID_SIZE];
1026 char phy_name[MII_BUS_ID_SIZE + 3];
1027 int phy_id;
1028 int dev_id = fep->dev_id;
1029
1030 fep->phy_dev = NULL;
1031
1032 /* check for attached phy */
1033 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1034 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1035 continue;
1036 if (fep->mii_bus->phy_map[phy_id] == NULL)
1037 continue;
1038 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1039 continue;
1040 if (dev_id--)
1041 continue;
1042 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1043 break;
1044 }
1045
1046 if (phy_id >= PHY_MAX_ADDR) {
1047 printk(KERN_INFO
1048 "%s: no PHY, assuming direct connection to switch\n",
1049 ndev->name);
1050 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1051 phy_id = 0;
1052 }
1053
1054 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1055 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1056 fep->phy_interface);
1057 if (IS_ERR(phy_dev)) {
1058 printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
1059 return PTR_ERR(phy_dev);
1060 }
1061
1062 /* mask with MAC supported features */
1063 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1064 phy_dev->supported &= PHY_GBIT_FEATURES;
1065 phy_dev->supported |= SUPPORTED_Pause;
1066 }
1067 else
1068 phy_dev->supported &= PHY_BASIC_FEATURES;
1069
1070 phy_dev->advertising = phy_dev->supported;
1071
1072 fep->phy_dev = phy_dev;
1073 fep->link = 0;
1074 fep->full_duplex = 0;
1075
1076 printk(KERN_INFO
1077 "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1078 ndev->name,
1079 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1080 fep->phy_dev->irq);
1081
1082 return 0;
1083 }
1084
1085 static int fec_enet_mii_init(struct platform_device *pdev)
1086 {
1087 static struct mii_bus *fec0_mii_bus;
1088 struct net_device *ndev = platform_get_drvdata(pdev);
1089 struct fec_enet_private *fep = netdev_priv(ndev);
1090 const struct platform_device_id *id_entry =
1091 platform_get_device_id(fep->pdev);
1092 int err = -ENXIO, i;
1093
1094 /*
1095 * The dual fec interfaces are not equivalent with enet-mac.
1096 * Here are the differences:
1097 *
1098 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1099 * - fec0 acts as the 1588 time master while fec1 is slave
1100 * - external phys can only be configured by fec0
1101 *
1102 * That is to say fec1 can not work independently. It only works
1103 * when fec0 is working. The reason behind this design is that the
1104 * second interface is added primarily for Switch mode.
1105 *
1106 * Because of the last point above, both phys are attached on fec0
1107 * mdio interface in board design, and need to be configured by
1108 * fec0 mii_bus.
1109 */
1110 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1111 /* fec1 uses fec0 mii_bus */
1112 if (mii_cnt && fec0_mii_bus) {
1113 fep->mii_bus = fec0_mii_bus;
1114 mii_cnt++;
1115 return 0;
1116 }
1117 return -ENOENT;
1118 }
1119
1120 fep->mii_timeout = 0;
1121
1122 /*
1123 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1124 *
1125 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1126 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1127 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1128 * document.
1129 */
1130 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1131 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1132 fep->phy_speed--;
1133 fep->phy_speed <<= 1;
1134 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1135
1136 fep->mii_bus = mdiobus_alloc();
1137 if (fep->mii_bus == NULL) {
1138 err = -ENOMEM;
1139 goto err_out;
1140 }
1141
1142 fep->mii_bus->name = "fec_enet_mii_bus";
1143 fep->mii_bus->read = fec_enet_mdio_read;
1144 fep->mii_bus->write = fec_enet_mdio_write;
1145 fep->mii_bus->reset = fec_enet_mdio_reset;
1146 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1147 pdev->name, fep->dev_id + 1);
1148 fep->mii_bus->priv = fep;
1149 fep->mii_bus->parent = &pdev->dev;
1150
1151 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1152 if (!fep->mii_bus->irq) {
1153 err = -ENOMEM;
1154 goto err_out_free_mdiobus;
1155 }
1156
1157 for (i = 0; i < PHY_MAX_ADDR; i++)
1158 fep->mii_bus->irq[i] = PHY_POLL;
1159
1160 if (mdiobus_register(fep->mii_bus))
1161 goto err_out_free_mdio_irq;
1162
1163 mii_cnt++;
1164
1165 /* save fec0 mii_bus */
1166 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1167 fec0_mii_bus = fep->mii_bus;
1168
1169 return 0;
1170
1171 err_out_free_mdio_irq:
1172 kfree(fep->mii_bus->irq);
1173 err_out_free_mdiobus:
1174 mdiobus_free(fep->mii_bus);
1175 err_out:
1176 return err;
1177 }
1178
1179 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1180 {
1181 if (--mii_cnt == 0) {
1182 mdiobus_unregister(fep->mii_bus);
1183 kfree(fep->mii_bus->irq);
1184 mdiobus_free(fep->mii_bus);
1185 }
1186 }
1187
1188 static int fec_enet_get_settings(struct net_device *ndev,
1189 struct ethtool_cmd *cmd)
1190 {
1191 struct fec_enet_private *fep = netdev_priv(ndev);
1192 struct phy_device *phydev = fep->phy_dev;
1193
1194 if (!phydev)
1195 return -ENODEV;
1196
1197 return phy_ethtool_gset(phydev, cmd);
1198 }
1199
1200 static int fec_enet_set_settings(struct net_device *ndev,
1201 struct ethtool_cmd *cmd)
1202 {
1203 struct fec_enet_private *fep = netdev_priv(ndev);
1204 struct phy_device *phydev = fep->phy_dev;
1205
1206 if (!phydev)
1207 return -ENODEV;
1208
1209 return phy_ethtool_sset(phydev, cmd);
1210 }
1211
1212 static void fec_enet_get_drvinfo(struct net_device *ndev,
1213 struct ethtool_drvinfo *info)
1214 {
1215 struct fec_enet_private *fep = netdev_priv(ndev);
1216
1217 strlcpy(info->driver, fep->pdev->dev.driver->name,
1218 sizeof(info->driver));
1219 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1220 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1221 }
1222
1223 static int fec_enet_get_ts_info(struct net_device *ndev,
1224 struct ethtool_ts_info *info)
1225 {
1226 struct fec_enet_private *fep = netdev_priv(ndev);
1227
1228 if (fep->bufdesc_ex) {
1229
1230 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1231 SOF_TIMESTAMPING_RX_SOFTWARE |
1232 SOF_TIMESTAMPING_SOFTWARE |
1233 SOF_TIMESTAMPING_TX_HARDWARE |
1234 SOF_TIMESTAMPING_RX_HARDWARE |
1235 SOF_TIMESTAMPING_RAW_HARDWARE;
1236 if (fep->ptp_clock)
1237 info->phc_index = ptp_clock_index(fep->ptp_clock);
1238 else
1239 info->phc_index = -1;
1240
1241 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1242 (1 << HWTSTAMP_TX_ON);
1243
1244 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1245 (1 << HWTSTAMP_FILTER_ALL);
1246 return 0;
1247 } else {
1248 return ethtool_op_get_ts_info(ndev, info);
1249 }
1250 }
1251
1252 static void fec_enet_get_pauseparam(struct net_device *ndev,
1253 struct ethtool_pauseparam *pause)
1254 {
1255 struct fec_enet_private *fep = netdev_priv(ndev);
1256
1257 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1258 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1259 pause->rx_pause = pause->tx_pause;
1260 }
1261
1262 static int fec_enet_set_pauseparam(struct net_device *ndev,
1263 struct ethtool_pauseparam *pause)
1264 {
1265 struct fec_enet_private *fep = netdev_priv(ndev);
1266
1267 if (pause->tx_pause != pause->rx_pause) {
1268 netdev_info(ndev,
1269 "hardware only support enable/disable both tx and rx");
1270 return -EINVAL;
1271 }
1272
1273 fep->pause_flag = 0;
1274
1275 /* tx pause must be same as rx pause */
1276 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1277 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1278
1279 if (pause->rx_pause || pause->autoneg) {
1280 fep->phy_dev->supported |= ADVERTISED_Pause;
1281 fep->phy_dev->advertising |= ADVERTISED_Pause;
1282 } else {
1283 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1284 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1285 }
1286
1287 if (pause->autoneg) {
1288 if (netif_running(ndev))
1289 fec_stop(ndev);
1290 phy_start_aneg(fep->phy_dev);
1291 }
1292 if (netif_running(ndev))
1293 fec_restart(ndev, 0);
1294
1295 return 0;
1296 }
1297
1298 static const struct ethtool_ops fec_enet_ethtool_ops = {
1299 .get_pauseparam = fec_enet_get_pauseparam,
1300 .set_pauseparam = fec_enet_set_pauseparam,
1301 .get_settings = fec_enet_get_settings,
1302 .set_settings = fec_enet_set_settings,
1303 .get_drvinfo = fec_enet_get_drvinfo,
1304 .get_link = ethtool_op_get_link,
1305 .get_ts_info = fec_enet_get_ts_info,
1306 };
1307
1308 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1309 {
1310 struct fec_enet_private *fep = netdev_priv(ndev);
1311 struct phy_device *phydev = fep->phy_dev;
1312
1313 if (!netif_running(ndev))
1314 return -EINVAL;
1315
1316 if (!phydev)
1317 return -ENODEV;
1318
1319 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
1320 return fec_ptp_ioctl(ndev, rq, cmd);
1321
1322 return phy_mii_ioctl(phydev, rq, cmd);
1323 }
1324
1325 static void fec_enet_free_buffers(struct net_device *ndev)
1326 {
1327 struct fec_enet_private *fep = netdev_priv(ndev);
1328 int i;
1329 struct sk_buff *skb;
1330 struct bufdesc *bdp;
1331
1332 bdp = fep->rx_bd_base;
1333 for (i = 0; i < RX_RING_SIZE; i++) {
1334 skb = fep->rx_skbuff[i];
1335
1336 if (bdp->cbd_bufaddr)
1337 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1338 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1339 if (skb)
1340 dev_kfree_skb(skb);
1341 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1342 }
1343
1344 bdp = fep->tx_bd_base;
1345 for (i = 0; i < TX_RING_SIZE; i++)
1346 kfree(fep->tx_bounce[i]);
1347 }
1348
1349 static int fec_enet_alloc_buffers(struct net_device *ndev)
1350 {
1351 struct fec_enet_private *fep = netdev_priv(ndev);
1352 int i;
1353 struct sk_buff *skb;
1354 struct bufdesc *bdp;
1355
1356 bdp = fep->rx_bd_base;
1357 for (i = 0; i < RX_RING_SIZE; i++) {
1358 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1359 if (!skb) {
1360 fec_enet_free_buffers(ndev);
1361 return -ENOMEM;
1362 }
1363 fep->rx_skbuff[i] = skb;
1364
1365 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1366 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1367 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1368
1369 if (fep->bufdesc_ex) {
1370 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1371 ebdp->cbd_esc = BD_ENET_RX_INT;
1372 }
1373
1374 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1375 }
1376
1377 /* Set the last buffer to wrap. */
1378 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1379 bdp->cbd_sc |= BD_SC_WRAP;
1380
1381 bdp = fep->tx_bd_base;
1382 for (i = 0; i < TX_RING_SIZE; i++) {
1383 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1384
1385 bdp->cbd_sc = 0;
1386 bdp->cbd_bufaddr = 0;
1387
1388 if (fep->bufdesc_ex) {
1389 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1390 ebdp->cbd_esc = BD_ENET_RX_INT;
1391 }
1392
1393 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1394 }
1395
1396 /* Set the last buffer to wrap. */
1397 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1398 bdp->cbd_sc |= BD_SC_WRAP;
1399
1400 return 0;
1401 }
1402
1403 static int
1404 fec_enet_open(struct net_device *ndev)
1405 {
1406 struct fec_enet_private *fep = netdev_priv(ndev);
1407 int ret;
1408
1409 napi_enable(&fep->napi);
1410
1411 /* I should reset the ring buffers here, but I don't yet know
1412 * a simple way to do that.
1413 */
1414
1415 ret = fec_enet_alloc_buffers(ndev);
1416 if (ret)
1417 return ret;
1418
1419 /* Probe and connect to PHY when open the interface */
1420 ret = fec_enet_mii_probe(ndev);
1421 if (ret) {
1422 fec_enet_free_buffers(ndev);
1423 return ret;
1424 }
1425 phy_start(fep->phy_dev);
1426 netif_start_queue(ndev);
1427 fep->opened = 1;
1428 return 0;
1429 }
1430
1431 static int
1432 fec_enet_close(struct net_device *ndev)
1433 {
1434 struct fec_enet_private *fep = netdev_priv(ndev);
1435
1436 /* Don't know what to do yet. */
1437 fep->opened = 0;
1438 netif_stop_queue(ndev);
1439 fec_stop(ndev);
1440
1441 if (fep->phy_dev) {
1442 phy_stop(fep->phy_dev);
1443 phy_disconnect(fep->phy_dev);
1444 }
1445
1446 fec_enet_free_buffers(ndev);
1447
1448 return 0;
1449 }
1450
1451 /* Set or clear the multicast filter for this adaptor.
1452 * Skeleton taken from sunlance driver.
1453 * The CPM Ethernet implementation allows Multicast as well as individual
1454 * MAC address filtering. Some of the drivers check to make sure it is
1455 * a group multicast address, and discard those that are not. I guess I
1456 * will do the same for now, but just remove the test if you want
1457 * individual filtering as well (do the upper net layers want or support
1458 * this kind of feature?).
1459 */
1460
1461 #define HASH_BITS 6 /* #bits in hash */
1462 #define CRC32_POLY 0xEDB88320
1463
1464 static void set_multicast_list(struct net_device *ndev)
1465 {
1466 struct fec_enet_private *fep = netdev_priv(ndev);
1467 struct netdev_hw_addr *ha;
1468 unsigned int i, bit, data, crc, tmp;
1469 unsigned char hash;
1470
1471 if (ndev->flags & IFF_PROMISC) {
1472 tmp = readl(fep->hwp + FEC_R_CNTRL);
1473 tmp |= 0x8;
1474 writel(tmp, fep->hwp + FEC_R_CNTRL);
1475 return;
1476 }
1477
1478 tmp = readl(fep->hwp + FEC_R_CNTRL);
1479 tmp &= ~0x8;
1480 writel(tmp, fep->hwp + FEC_R_CNTRL);
1481
1482 if (ndev->flags & IFF_ALLMULTI) {
1483 /* Catch all multicast addresses, so set the
1484 * filter to all 1's
1485 */
1486 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1487 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1488
1489 return;
1490 }
1491
1492 /* Clear filter and add the addresses in hash register
1493 */
1494 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1495 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1496
1497 netdev_for_each_mc_addr(ha, ndev) {
1498 /* calculate crc32 value of mac address */
1499 crc = 0xffffffff;
1500
1501 for (i = 0; i < ndev->addr_len; i++) {
1502 data = ha->addr[i];
1503 for (bit = 0; bit < 8; bit++, data >>= 1) {
1504 crc = (crc >> 1) ^
1505 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1506 }
1507 }
1508
1509 /* only upper 6 bits (HASH_BITS) are used
1510 * which point to specific bit in he hash registers
1511 */
1512 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1513
1514 if (hash > 31) {
1515 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1516 tmp |= 1 << (hash - 32);
1517 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1518 } else {
1519 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1520 tmp |= 1 << hash;
1521 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1522 }
1523 }
1524 }
1525
1526 /* Set a MAC change in hardware. */
1527 static int
1528 fec_set_mac_address(struct net_device *ndev, void *p)
1529 {
1530 struct fec_enet_private *fep = netdev_priv(ndev);
1531 struct sockaddr *addr = p;
1532
1533 if (!is_valid_ether_addr(addr->sa_data))
1534 return -EADDRNOTAVAIL;
1535
1536 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1537
1538 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1539 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1540 fep->hwp + FEC_ADDR_LOW);
1541 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1542 fep->hwp + FEC_ADDR_HIGH);
1543 return 0;
1544 }
1545
1546 #ifdef CONFIG_NET_POLL_CONTROLLER
1547 /**
1548 * fec_poll_controller - FEC Poll controller function
1549 * @dev: The FEC network adapter
1550 *
1551 * Polled functionality used by netconsole and others in non interrupt mode
1552 *
1553 */
1554 void fec_poll_controller(struct net_device *dev)
1555 {
1556 int i;
1557 struct fec_enet_private *fep = netdev_priv(dev);
1558
1559 for (i = 0; i < FEC_IRQ_NUM; i++) {
1560 if (fep->irq[i] > 0) {
1561 disable_irq(fep->irq[i]);
1562 fec_enet_interrupt(fep->irq[i], dev);
1563 enable_irq(fep->irq[i]);
1564 }
1565 }
1566 }
1567 #endif
1568
1569 static const struct net_device_ops fec_netdev_ops = {
1570 .ndo_open = fec_enet_open,
1571 .ndo_stop = fec_enet_close,
1572 .ndo_start_xmit = fec_enet_start_xmit,
1573 .ndo_set_rx_mode = set_multicast_list,
1574 .ndo_change_mtu = eth_change_mtu,
1575 .ndo_validate_addr = eth_validate_addr,
1576 .ndo_tx_timeout = fec_timeout,
1577 .ndo_set_mac_address = fec_set_mac_address,
1578 .ndo_do_ioctl = fec_enet_ioctl,
1579 #ifdef CONFIG_NET_POLL_CONTROLLER
1580 .ndo_poll_controller = fec_poll_controller,
1581 #endif
1582 };
1583
1584 /*
1585 * XXX: We need to clean up on failure exits here.
1586 *
1587 */
1588 static int fec_enet_init(struct net_device *ndev)
1589 {
1590 struct fec_enet_private *fep = netdev_priv(ndev);
1591 struct bufdesc *cbd_base;
1592 struct bufdesc *bdp;
1593 int i;
1594
1595 /* Allocate memory for buffer descriptors. */
1596 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1597 GFP_KERNEL);
1598 if (!cbd_base) {
1599 printk("FEC: allocate descriptor memory failed?\n");
1600 return -ENOMEM;
1601 }
1602
1603 spin_lock_init(&fep->hw_lock);
1604
1605 fep->netdev = ndev;
1606
1607 /* Get the Ethernet address */
1608 fec_get_mac(ndev);
1609
1610 /* Set receive and transmit descriptor base. */
1611 fep->rx_bd_base = cbd_base;
1612 if (fep->bufdesc_ex)
1613 fep->tx_bd_base = (struct bufdesc *)
1614 (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE);
1615 else
1616 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1617
1618 /* The FEC Ethernet specific entries in the device structure */
1619 ndev->watchdog_timeo = TX_TIMEOUT;
1620 ndev->netdev_ops = &fec_netdev_ops;
1621 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1622
1623 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
1624 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
1625
1626 /* Initialize the receive buffer descriptors. */
1627 bdp = fep->rx_bd_base;
1628 for (i = 0; i < RX_RING_SIZE; i++) {
1629
1630 /* Initialize the BD for every fragment in the page. */
1631 bdp->cbd_sc = 0;
1632 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1633 }
1634
1635 /* Set the last buffer to wrap */
1636 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1637 bdp->cbd_sc |= BD_SC_WRAP;
1638
1639 /* ...and the same for transmit */
1640 bdp = fep->tx_bd_base;
1641 fep->cur_tx = bdp;
1642 for (i = 0; i < TX_RING_SIZE; i++) {
1643
1644 /* Initialize the BD for every fragment in the page. */
1645 bdp->cbd_sc = 0;
1646 bdp->cbd_bufaddr = 0;
1647 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1648 }
1649
1650 /* Set the last buffer to wrap */
1651 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1652 bdp->cbd_sc |= BD_SC_WRAP;
1653 fep->dirty_tx = bdp;
1654
1655 fec_restart(ndev, 0);
1656
1657 return 0;
1658 }
1659
1660 #ifdef CONFIG_OF
1661 static int fec_get_phy_mode_dt(struct platform_device *pdev)
1662 {
1663 struct device_node *np = pdev->dev.of_node;
1664
1665 if (np)
1666 return of_get_phy_mode(np);
1667
1668 return -ENODEV;
1669 }
1670
1671 static void fec_reset_phy(struct platform_device *pdev)
1672 {
1673 int err, phy_reset;
1674 int msec = 1;
1675 struct device_node *np = pdev->dev.of_node;
1676
1677 if (!np)
1678 return;
1679
1680 of_property_read_u32(np, "phy-reset-duration", &msec);
1681 /* A sane reset duration should not be longer than 1s */
1682 if (msec > 1000)
1683 msec = 1;
1684
1685 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1686 if (!gpio_is_valid(phy_reset))
1687 return;
1688
1689 err = devm_gpio_request_one(&pdev->dev, phy_reset,
1690 GPIOF_OUT_INIT_LOW, "phy-reset");
1691 if (err) {
1692 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
1693 return;
1694 }
1695 msleep(msec);
1696 gpio_set_value(phy_reset, 1);
1697 }
1698 #else /* CONFIG_OF */
1699 static int fec_get_phy_mode_dt(struct platform_device *pdev)
1700 {
1701 return -ENODEV;
1702 }
1703
1704 static void fec_reset_phy(struct platform_device *pdev)
1705 {
1706 /*
1707 * In case of platform probe, the reset has been done
1708 * by machine code.
1709 */
1710 }
1711 #endif /* CONFIG_OF */
1712
1713 static int
1714 fec_probe(struct platform_device *pdev)
1715 {
1716 struct fec_enet_private *fep;
1717 struct fec_platform_data *pdata;
1718 struct net_device *ndev;
1719 int i, irq, ret = 0;
1720 struct resource *r;
1721 const struct of_device_id *of_id;
1722 static int dev_id;
1723 struct pinctrl *pinctrl;
1724 struct regulator *reg_phy;
1725
1726 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1727 if (of_id)
1728 pdev->id_entry = of_id->data;
1729
1730 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1731 if (!r)
1732 return -ENXIO;
1733
1734 r = request_mem_region(r->start, resource_size(r), pdev->name);
1735 if (!r)
1736 return -EBUSY;
1737
1738 /* Init network device */
1739 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1740 if (!ndev) {
1741 ret = -ENOMEM;
1742 goto failed_alloc_etherdev;
1743 }
1744
1745 SET_NETDEV_DEV(ndev, &pdev->dev);
1746
1747 /* setup board info structure */
1748 fep = netdev_priv(ndev);
1749
1750 /* default enable pause frame auto negotiation */
1751 if (pdev->id_entry &&
1752 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
1753 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
1754
1755 fep->hwp = ioremap(r->start, resource_size(r));
1756 fep->pdev = pdev;
1757 fep->dev_id = dev_id++;
1758
1759 fep->bufdesc_ex = 0;
1760
1761 if (!fep->hwp) {
1762 ret = -ENOMEM;
1763 goto failed_ioremap;
1764 }
1765
1766 platform_set_drvdata(pdev, ndev);
1767
1768 ret = fec_get_phy_mode_dt(pdev);
1769 if (ret < 0) {
1770 pdata = pdev->dev.platform_data;
1771 if (pdata)
1772 fep->phy_interface = pdata->phy;
1773 else
1774 fep->phy_interface = PHY_INTERFACE_MODE_MII;
1775 } else {
1776 fep->phy_interface = ret;
1777 }
1778
1779 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1780 if (IS_ERR(pinctrl)) {
1781 ret = PTR_ERR(pinctrl);
1782 goto failed_pin;
1783 }
1784
1785 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1786 if (IS_ERR(fep->clk_ipg)) {
1787 ret = PTR_ERR(fep->clk_ipg);
1788 goto failed_clk;
1789 }
1790
1791 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1792 if (IS_ERR(fep->clk_ahb)) {
1793 ret = PTR_ERR(fep->clk_ahb);
1794 goto failed_clk;
1795 }
1796
1797 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
1798 fep->bufdesc_ex =
1799 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
1800 if (IS_ERR(fep->clk_ptp)) {
1801 ret = PTR_ERR(fep->clk_ptp);
1802 fep->bufdesc_ex = 0;
1803 }
1804
1805 clk_prepare_enable(fep->clk_ahb);
1806 clk_prepare_enable(fep->clk_ipg);
1807 if (!IS_ERR(fep->clk_ptp))
1808 clk_prepare_enable(fep->clk_ptp);
1809
1810 reg_phy = devm_regulator_get(&pdev->dev, "phy");
1811 if (!IS_ERR(reg_phy)) {
1812 ret = regulator_enable(reg_phy);
1813 if (ret) {
1814 dev_err(&pdev->dev,
1815 "Failed to enable phy regulator: %d\n", ret);
1816 goto failed_regulator;
1817 }
1818 }
1819
1820 fec_reset_phy(pdev);
1821
1822 if (fep->bufdesc_ex)
1823 fec_ptp_init(ndev, pdev);
1824
1825 ret = fec_enet_init(ndev);
1826 if (ret)
1827 goto failed_init;
1828
1829 for (i = 0; i < FEC_IRQ_NUM; i++) {
1830 irq = platform_get_irq(pdev, i);
1831 if (irq < 0) {
1832 if (i)
1833 break;
1834 ret = irq;
1835 goto failed_irq;
1836 }
1837 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1838 if (ret) {
1839 while (--i >= 0) {
1840 irq = platform_get_irq(pdev, i);
1841 free_irq(irq, ndev);
1842 }
1843 goto failed_irq;
1844 }
1845 }
1846
1847 ret = fec_enet_mii_init(pdev);
1848 if (ret)
1849 goto failed_mii_init;
1850
1851 /* Carrier starts down, phylib will bring it up */
1852 netif_carrier_off(ndev);
1853
1854 ret = register_netdev(ndev);
1855 if (ret)
1856 goto failed_register;
1857
1858 return 0;
1859
1860 failed_register:
1861 fec_enet_mii_remove(fep);
1862 failed_mii_init:
1863 failed_init:
1864 for (i = 0; i < FEC_IRQ_NUM; i++) {
1865 irq = platform_get_irq(pdev, i);
1866 if (irq > 0)
1867 free_irq(irq, ndev);
1868 }
1869 failed_irq:
1870 failed_regulator:
1871 clk_disable_unprepare(fep->clk_ahb);
1872 clk_disable_unprepare(fep->clk_ipg);
1873 if (!IS_ERR(fep->clk_ptp))
1874 clk_disable_unprepare(fep->clk_ptp);
1875 failed_pin:
1876 failed_clk:
1877 iounmap(fep->hwp);
1878 failed_ioremap:
1879 free_netdev(ndev);
1880 failed_alloc_etherdev:
1881 release_mem_region(r->start, resource_size(r));
1882
1883 return ret;
1884 }
1885
1886 static int
1887 fec_drv_remove(struct platform_device *pdev)
1888 {
1889 struct net_device *ndev = platform_get_drvdata(pdev);
1890 struct fec_enet_private *fep = netdev_priv(ndev);
1891 struct resource *r;
1892 int i;
1893
1894 unregister_netdev(ndev);
1895 fec_enet_mii_remove(fep);
1896 del_timer_sync(&fep->time_keep);
1897 clk_disable_unprepare(fep->clk_ptp);
1898 if (fep->ptp_clock)
1899 ptp_clock_unregister(fep->ptp_clock);
1900 clk_disable_unprepare(fep->clk_ahb);
1901 clk_disable_unprepare(fep->clk_ipg);
1902 for (i = 0; i < FEC_IRQ_NUM; i++) {
1903 int irq = platform_get_irq(pdev, i);
1904 if (irq > 0)
1905 free_irq(irq, ndev);
1906 }
1907 iounmap(fep->hwp);
1908 free_netdev(ndev);
1909
1910 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1911 BUG_ON(!r);
1912 release_mem_region(r->start, resource_size(r));
1913
1914 platform_set_drvdata(pdev, NULL);
1915
1916 return 0;
1917 }
1918
1919 #ifdef CONFIG_PM
1920 static int
1921 fec_suspend(struct device *dev)
1922 {
1923 struct net_device *ndev = dev_get_drvdata(dev);
1924 struct fec_enet_private *fep = netdev_priv(ndev);
1925
1926 if (netif_running(ndev)) {
1927 fec_stop(ndev);
1928 netif_device_detach(ndev);
1929 }
1930 clk_disable_unprepare(fep->clk_ahb);
1931 clk_disable_unprepare(fep->clk_ipg);
1932
1933 return 0;
1934 }
1935
1936 static int
1937 fec_resume(struct device *dev)
1938 {
1939 struct net_device *ndev = dev_get_drvdata(dev);
1940 struct fec_enet_private *fep = netdev_priv(ndev);
1941
1942 clk_prepare_enable(fep->clk_ahb);
1943 clk_prepare_enable(fep->clk_ipg);
1944 if (netif_running(ndev)) {
1945 fec_restart(ndev, fep->full_duplex);
1946 netif_device_attach(ndev);
1947 }
1948
1949 return 0;
1950 }
1951
1952 static const struct dev_pm_ops fec_pm_ops = {
1953 .suspend = fec_suspend,
1954 .resume = fec_resume,
1955 .freeze = fec_suspend,
1956 .thaw = fec_resume,
1957 .poweroff = fec_suspend,
1958 .restore = fec_resume,
1959 };
1960 #endif
1961
1962 static struct platform_driver fec_driver = {
1963 .driver = {
1964 .name = DRIVER_NAME,
1965 .owner = THIS_MODULE,
1966 #ifdef CONFIG_PM
1967 .pm = &fec_pm_ops,
1968 #endif
1969 .of_match_table = fec_dt_ids,
1970 },
1971 .id_table = fec_devtype,
1972 .probe = fec_probe,
1973 .remove = fec_drv_remove,
1974 };
1975
1976 module_platform_driver(fec_driver);
1977
1978 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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