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net: fec: remove inappropriate calls around fec_restart()
[deliverable/linux.git] / drivers / net / ethernet / freescale / fec_main.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/in.h>
37 #include <linux/ip.h>
38 #include <net/ip.h>
39 #include <net/tso.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
46 #include <linux/io.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
52 #include <linux/of.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_net.h>
56 #include <linux/regulator/consumer.h>
57 #include <linux/if_vlan.h>
58 #include <linux/pinctrl/consumer.h>
59
60 #include <asm/cacheflush.h>
61
62 #include "fec.h"
63
64 static void set_multicast_list(struct net_device *ndev);
65
66 #if defined(CONFIG_ARM)
67 #define FEC_ALIGNMENT 0xf
68 #else
69 #define FEC_ALIGNMENT 0x3
70 #endif
71
72 #define DRIVER_NAME "fec"
73
74 /* Pause frame feild and FIFO threshold */
75 #define FEC_ENET_FCE (1 << 5)
76 #define FEC_ENET_RSEM_V 0x84
77 #define FEC_ENET_RSFL_V 16
78 #define FEC_ENET_RAEM_V 0x8
79 #define FEC_ENET_RAFL_V 0x8
80 #define FEC_ENET_OPD_V 0xFFF0
81
82 /* Controller is ENET-MAC */
83 #define FEC_QUIRK_ENET_MAC (1 << 0)
84 /* Controller needs driver to swap frame */
85 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
86 /* Controller uses gasket */
87 #define FEC_QUIRK_USE_GASKET (1 << 2)
88 /* Controller has GBIT support */
89 #define FEC_QUIRK_HAS_GBIT (1 << 3)
90 /* Controller has extend desc buffer */
91 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
92 /* Controller has hardware checksum support */
93 #define FEC_QUIRK_HAS_CSUM (1 << 5)
94 /* Controller has hardware vlan support */
95 #define FEC_QUIRK_HAS_VLAN (1 << 6)
96 /* ENET IP errata ERR006358
97 *
98 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
99 * detected as not set during a prior frame transmission, then the
100 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
101 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
102 * frames not being transmitted until there is a 0-to-1 transition on
103 * ENET_TDAR[TDAR].
104 */
105 #define FEC_QUIRK_ERR006358 (1 << 7)
106
107 static struct platform_device_id fec_devtype[] = {
108 {
109 /* keep it for coldfire */
110 .name = DRIVER_NAME,
111 .driver_data = 0,
112 }, {
113 .name = "imx25-fec",
114 .driver_data = FEC_QUIRK_USE_GASKET,
115 }, {
116 .name = "imx27-fec",
117 .driver_data = 0,
118 }, {
119 .name = "imx28-fec",
120 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
121 }, {
122 .name = "imx6q-fec",
123 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
124 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
125 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
126 }, {
127 .name = "mvf600-fec",
128 .driver_data = FEC_QUIRK_ENET_MAC,
129 }, {
130 /* sentinel */
131 }
132 };
133 MODULE_DEVICE_TABLE(platform, fec_devtype);
134
135 enum imx_fec_type {
136 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
137 IMX27_FEC, /* runs on i.mx27/35/51 */
138 IMX28_FEC,
139 IMX6Q_FEC,
140 MVF600_FEC,
141 };
142
143 static const struct of_device_id fec_dt_ids[] = {
144 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
145 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
146 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
147 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
148 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
149 { /* sentinel */ }
150 };
151 MODULE_DEVICE_TABLE(of, fec_dt_ids);
152
153 static unsigned char macaddr[ETH_ALEN];
154 module_param_array(macaddr, byte, NULL, 0);
155 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
156
157 #if defined(CONFIG_M5272)
158 /*
159 * Some hardware gets it MAC address out of local flash memory.
160 * if this is non-zero then assume it is the address to get MAC from.
161 */
162 #if defined(CONFIG_NETtel)
163 #define FEC_FLASHMAC 0xf0006006
164 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
165 #define FEC_FLASHMAC 0xf0006000
166 #elif defined(CONFIG_CANCam)
167 #define FEC_FLASHMAC 0xf0020000
168 #elif defined (CONFIG_M5272C3)
169 #define FEC_FLASHMAC (0xffe04000 + 4)
170 #elif defined(CONFIG_MOD5272)
171 #define FEC_FLASHMAC 0xffc0406b
172 #else
173 #define FEC_FLASHMAC 0
174 #endif
175 #endif /* CONFIG_M5272 */
176
177 /* Interrupt events/masks. */
178 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
179 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
180 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
181 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
182 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
183 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
184 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
185 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
186 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
187 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
188
189 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
190 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
191
192 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
193 */
194 #define PKT_MAXBUF_SIZE 1522
195 #define PKT_MINBUF_SIZE 64
196 #define PKT_MAXBLR_SIZE 1536
197
198 /* FEC receive acceleration */
199 #define FEC_RACC_IPDIS (1 << 1)
200 #define FEC_RACC_PRODIS (1 << 2)
201 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
202
203 /*
204 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
205 * size bits. Other FEC hardware does not, so we need to take that into
206 * account when setting it.
207 */
208 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
209 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
210 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
211 #else
212 #define OPT_FRAME_SIZE 0
213 #endif
214
215 /* FEC MII MMFR bits definition */
216 #define FEC_MMFR_ST (1 << 30)
217 #define FEC_MMFR_OP_READ (2 << 28)
218 #define FEC_MMFR_OP_WRITE (1 << 28)
219 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
220 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
221 #define FEC_MMFR_TA (2 << 16)
222 #define FEC_MMFR_DATA(v) (v & 0xffff)
223
224 #define FEC_MII_TIMEOUT 30000 /* us */
225
226 /* Transmitter timeout */
227 #define TX_TIMEOUT (2 * HZ)
228
229 #define FEC_PAUSE_FLAG_AUTONEG 0x1
230 #define FEC_PAUSE_FLAG_ENABLE 0x2
231
232 #define TSO_HEADER_SIZE 128
233 /* Max number of allowed TCP segments for software TSO */
234 #define FEC_MAX_TSO_SEGS 100
235 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
236
237 #define IS_TSO_HEADER(txq, addr) \
238 ((addr >= txq->tso_hdrs_dma) && \
239 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
240
241 static int mii_cnt;
242
243 static inline
244 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
245 {
246 struct bufdesc *new_bd = bdp + 1;
247 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
248 struct bufdesc_ex *ex_base;
249 struct bufdesc *base;
250 int ring_size;
251
252 if (bdp >= fep->tx_bd_base) {
253 base = fep->tx_bd_base;
254 ring_size = fep->tx_ring_size;
255 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
256 } else {
257 base = fep->rx_bd_base;
258 ring_size = fep->rx_ring_size;
259 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
260 }
261
262 if (fep->bufdesc_ex)
263 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
264 ex_base : ex_new_bd);
265 else
266 return (new_bd >= (base + ring_size)) ?
267 base : new_bd;
268 }
269
270 static inline
271 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
272 {
273 struct bufdesc *new_bd = bdp - 1;
274 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
275 struct bufdesc_ex *ex_base;
276 struct bufdesc *base;
277 int ring_size;
278
279 if (bdp >= fep->tx_bd_base) {
280 base = fep->tx_bd_base;
281 ring_size = fep->tx_ring_size;
282 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
283 } else {
284 base = fep->rx_bd_base;
285 ring_size = fep->rx_ring_size;
286 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
287 }
288
289 if (fep->bufdesc_ex)
290 return (struct bufdesc *)((ex_new_bd < ex_base) ?
291 (ex_new_bd + ring_size) : ex_new_bd);
292 else
293 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
294 }
295
296 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
297 struct fec_enet_private *fep)
298 {
299 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
300 }
301
302 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep)
303 {
304 int entries;
305
306 entries = ((const char *)fep->dirty_tx -
307 (const char *)fep->cur_tx) / fep->bufdesc_size - 1;
308
309 return entries > 0 ? entries : entries + fep->tx_ring_size;
310 }
311
312 static void *swap_buffer(void *bufaddr, int len)
313 {
314 int i;
315 unsigned int *buf = bufaddr;
316
317 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
318 *buf = cpu_to_be32(*buf);
319
320 return bufaddr;
321 }
322
323 static inline bool is_ipv4_pkt(struct sk_buff *skb)
324 {
325 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
326 }
327
328 static int
329 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
330 {
331 /* Only run for packets requiring a checksum. */
332 if (skb->ip_summed != CHECKSUM_PARTIAL)
333 return 0;
334
335 if (unlikely(skb_cow_head(skb, 0)))
336 return -1;
337
338 if (is_ipv4_pkt(skb))
339 ip_hdr(skb)->check = 0;
340 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
341
342 return 0;
343 }
344
345 static void
346 fec_enet_submit_work(struct bufdesc *bdp, struct fec_enet_private *fep)
347 {
348 const struct platform_device_id *id_entry =
349 platform_get_device_id(fep->pdev);
350 struct bufdesc *bdp_pre;
351
352 bdp_pre = fec_enet_get_prevdesc(bdp, fep);
353 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) &&
354 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) {
355 fep->delay_work.trig_tx = true;
356 schedule_delayed_work(&(fep->delay_work.delay_work),
357 msecs_to_jiffies(1));
358 }
359 }
360
361 static int
362 fec_enet_txq_submit_frag_skb(struct sk_buff *skb, struct net_device *ndev)
363 {
364 struct fec_enet_private *fep = netdev_priv(ndev);
365 const struct platform_device_id *id_entry =
366 platform_get_device_id(fep->pdev);
367 struct bufdesc *bdp = fep->cur_tx;
368 struct bufdesc_ex *ebdp;
369 int nr_frags = skb_shinfo(skb)->nr_frags;
370 int frag, frag_len;
371 unsigned short status;
372 unsigned int estatus = 0;
373 skb_frag_t *this_frag;
374 unsigned int index;
375 void *bufaddr;
376 dma_addr_t addr;
377 int i;
378
379 for (frag = 0; frag < nr_frags; frag++) {
380 this_frag = &skb_shinfo(skb)->frags[frag];
381 bdp = fec_enet_get_nextdesc(bdp, fep);
382 ebdp = (struct bufdesc_ex *)bdp;
383
384 status = bdp->cbd_sc;
385 status &= ~BD_ENET_TX_STATS;
386 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
387 frag_len = skb_shinfo(skb)->frags[frag].size;
388
389 /* Handle the last BD specially */
390 if (frag == nr_frags - 1) {
391 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
392 if (fep->bufdesc_ex) {
393 estatus |= BD_ENET_TX_INT;
394 if (unlikely(skb_shinfo(skb)->tx_flags &
395 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
396 estatus |= BD_ENET_TX_TS;
397 }
398 }
399
400 if (fep->bufdesc_ex) {
401 if (skb->ip_summed == CHECKSUM_PARTIAL)
402 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
403 ebdp->cbd_bdu = 0;
404 ebdp->cbd_esc = estatus;
405 }
406
407 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
408
409 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
410 if (((unsigned long) bufaddr) & FEC_ALIGNMENT ||
411 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
412 memcpy(fep->tx_bounce[index], bufaddr, frag_len);
413 bufaddr = fep->tx_bounce[index];
414
415 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
416 swap_buffer(bufaddr, frag_len);
417 }
418
419 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
420 DMA_TO_DEVICE);
421 if (dma_mapping_error(&fep->pdev->dev, addr)) {
422 dev_kfree_skb_any(skb);
423 if (net_ratelimit())
424 netdev_err(ndev, "Tx DMA memory map failed\n");
425 goto dma_mapping_error;
426 }
427
428 bdp->cbd_bufaddr = addr;
429 bdp->cbd_datlen = frag_len;
430 bdp->cbd_sc = status;
431 }
432
433 fep->cur_tx = bdp;
434
435 return 0;
436
437 dma_mapping_error:
438 bdp = fep->cur_tx;
439 for (i = 0; i < frag; i++) {
440 bdp = fec_enet_get_nextdesc(bdp, fep);
441 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
442 bdp->cbd_datlen, DMA_TO_DEVICE);
443 }
444 return NETDEV_TX_OK;
445 }
446
447 static int fec_enet_txq_submit_skb(struct sk_buff *skb, struct net_device *ndev)
448 {
449 struct fec_enet_private *fep = netdev_priv(ndev);
450 const struct platform_device_id *id_entry =
451 platform_get_device_id(fep->pdev);
452 int nr_frags = skb_shinfo(skb)->nr_frags;
453 struct bufdesc *bdp, *last_bdp;
454 void *bufaddr;
455 dma_addr_t addr;
456 unsigned short status;
457 unsigned short buflen;
458 unsigned int estatus = 0;
459 unsigned int index;
460 int entries_free;
461 int ret;
462
463 entries_free = fec_enet_get_free_txdesc_num(fep);
464 if (entries_free < MAX_SKB_FRAGS + 1) {
465 dev_kfree_skb_any(skb);
466 if (net_ratelimit())
467 netdev_err(ndev, "NOT enough BD for SG!\n");
468 return NETDEV_TX_OK;
469 }
470
471 /* Protocol checksum off-load for TCP and UDP. */
472 if (fec_enet_clear_csum(skb, ndev)) {
473 dev_kfree_skb_any(skb);
474 return NETDEV_TX_OK;
475 }
476
477 /* Fill in a Tx ring entry */
478 bdp = fep->cur_tx;
479 status = bdp->cbd_sc;
480 status &= ~BD_ENET_TX_STATS;
481
482 /* Set buffer length and buffer pointer */
483 bufaddr = skb->data;
484 buflen = skb_headlen(skb);
485
486 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
487 if (((unsigned long) bufaddr) & FEC_ALIGNMENT ||
488 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
489 memcpy(fep->tx_bounce[index], skb->data, buflen);
490 bufaddr = fep->tx_bounce[index];
491
492 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
493 swap_buffer(bufaddr, buflen);
494 }
495
496 /* Push the data cache so the CPM does not get stale memory data. */
497 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
498 if (dma_mapping_error(&fep->pdev->dev, addr)) {
499 dev_kfree_skb_any(skb);
500 if (net_ratelimit())
501 netdev_err(ndev, "Tx DMA memory map failed\n");
502 return NETDEV_TX_OK;
503 }
504
505 if (nr_frags) {
506 ret = fec_enet_txq_submit_frag_skb(skb, ndev);
507 if (ret)
508 return ret;
509 } else {
510 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
511 if (fep->bufdesc_ex) {
512 estatus = BD_ENET_TX_INT;
513 if (unlikely(skb_shinfo(skb)->tx_flags &
514 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
515 estatus |= BD_ENET_TX_TS;
516 }
517 }
518
519 if (fep->bufdesc_ex) {
520
521 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
522
523 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
524 fep->hwts_tx_en))
525 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
526
527 if (skb->ip_summed == CHECKSUM_PARTIAL)
528 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
529
530 ebdp->cbd_bdu = 0;
531 ebdp->cbd_esc = estatus;
532 }
533
534 last_bdp = fep->cur_tx;
535 index = fec_enet_get_bd_index(fep->tx_bd_base, last_bdp, fep);
536 /* Save skb pointer */
537 fep->tx_skbuff[index] = skb;
538
539 bdp->cbd_datlen = buflen;
540 bdp->cbd_bufaddr = addr;
541
542 /* Send it on its way. Tell FEC it's ready, interrupt when done,
543 * it's the last BD of the frame, and to put the CRC on the end.
544 */
545 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
546 bdp->cbd_sc = status;
547
548 fec_enet_submit_work(bdp, fep);
549
550 /* If this was the last BD in the ring, start at the beginning again. */
551 bdp = fec_enet_get_nextdesc(last_bdp, fep);
552
553 skb_tx_timestamp(skb);
554
555 fep->cur_tx = bdp;
556
557 /* Trigger transmission start */
558 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
559
560 return 0;
561 }
562
563 static int
564 fec_enet_txq_put_data_tso(struct sk_buff *skb, struct net_device *ndev,
565 struct bufdesc *bdp, int index, char *data,
566 int size, bool last_tcp, bool is_last)
567 {
568 struct fec_enet_private *fep = netdev_priv(ndev);
569 const struct platform_device_id *id_entry =
570 platform_get_device_id(fep->pdev);
571 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
572 unsigned short status;
573 unsigned int estatus = 0;
574 dma_addr_t addr;
575
576 status = bdp->cbd_sc;
577 status &= ~BD_ENET_TX_STATS;
578
579 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
580
581 if (((unsigned long) data) & FEC_ALIGNMENT ||
582 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
583 memcpy(fep->tx_bounce[index], data, size);
584 data = fep->tx_bounce[index];
585
586 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
587 swap_buffer(data, size);
588 }
589
590 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
591 if (dma_mapping_error(&fep->pdev->dev, addr)) {
592 dev_kfree_skb_any(skb);
593 if (net_ratelimit())
594 netdev_err(ndev, "Tx DMA memory map failed\n");
595 return NETDEV_TX_BUSY;
596 }
597
598 bdp->cbd_datlen = size;
599 bdp->cbd_bufaddr = addr;
600
601 if (fep->bufdesc_ex) {
602 if (skb->ip_summed == CHECKSUM_PARTIAL)
603 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
604 ebdp->cbd_bdu = 0;
605 ebdp->cbd_esc = estatus;
606 }
607
608 /* Handle the last BD specially */
609 if (last_tcp)
610 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
611 if (is_last) {
612 status |= BD_ENET_TX_INTR;
613 if (fep->bufdesc_ex)
614 ebdp->cbd_esc |= BD_ENET_TX_INT;
615 }
616
617 bdp->cbd_sc = status;
618
619 return 0;
620 }
621
622 static int
623 fec_enet_txq_put_hdr_tso(struct sk_buff *skb, struct net_device *ndev,
624 struct bufdesc *bdp, int index)
625 {
626 struct fec_enet_private *fep = netdev_priv(ndev);
627 const struct platform_device_id *id_entry =
628 platform_get_device_id(fep->pdev);
629 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
630 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
631 void *bufaddr;
632 unsigned long dmabuf;
633 unsigned short status;
634 unsigned int estatus = 0;
635
636 status = bdp->cbd_sc;
637 status &= ~BD_ENET_TX_STATS;
638 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
639
640 bufaddr = fep->tso_hdrs + index * TSO_HEADER_SIZE;
641 dmabuf = fep->tso_hdrs_dma + index * TSO_HEADER_SIZE;
642 if (((unsigned long) bufaddr) & FEC_ALIGNMENT ||
643 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
644 memcpy(fep->tx_bounce[index], skb->data, hdr_len);
645 bufaddr = fep->tx_bounce[index];
646
647 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
648 swap_buffer(bufaddr, hdr_len);
649
650 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
651 hdr_len, DMA_TO_DEVICE);
652 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
653 dev_kfree_skb_any(skb);
654 if (net_ratelimit())
655 netdev_err(ndev, "Tx DMA memory map failed\n");
656 return NETDEV_TX_BUSY;
657 }
658 }
659
660 bdp->cbd_bufaddr = dmabuf;
661 bdp->cbd_datlen = hdr_len;
662
663 if (fep->bufdesc_ex) {
664 if (skb->ip_summed == CHECKSUM_PARTIAL)
665 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
666 ebdp->cbd_bdu = 0;
667 ebdp->cbd_esc = estatus;
668 }
669
670 bdp->cbd_sc = status;
671
672 return 0;
673 }
674
675 static int fec_enet_txq_submit_tso(struct sk_buff *skb, struct net_device *ndev)
676 {
677 struct fec_enet_private *fep = netdev_priv(ndev);
678 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
679 int total_len, data_left;
680 struct bufdesc *bdp = fep->cur_tx;
681 struct tso_t tso;
682 unsigned int index = 0;
683 int ret;
684
685 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep)) {
686 dev_kfree_skb_any(skb);
687 if (net_ratelimit())
688 netdev_err(ndev, "NOT enough BD for TSO!\n");
689 return NETDEV_TX_OK;
690 }
691
692 /* Protocol checksum off-load for TCP and UDP. */
693 if (fec_enet_clear_csum(skb, ndev)) {
694 dev_kfree_skb_any(skb);
695 return NETDEV_TX_OK;
696 }
697
698 /* Initialize the TSO handler, and prepare the first payload */
699 tso_start(skb, &tso);
700
701 total_len = skb->len - hdr_len;
702 while (total_len > 0) {
703 char *hdr;
704
705 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
706 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
707 total_len -= data_left;
708
709 /* prepare packet headers: MAC + IP + TCP */
710 hdr = fep->tso_hdrs + index * TSO_HEADER_SIZE;
711 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
712 ret = fec_enet_txq_put_hdr_tso(skb, ndev, bdp, index);
713 if (ret)
714 goto err_release;
715
716 while (data_left > 0) {
717 int size;
718
719 size = min_t(int, tso.size, data_left);
720 bdp = fec_enet_get_nextdesc(bdp, fep);
721 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
722 ret = fec_enet_txq_put_data_tso(skb, ndev, bdp, index, tso.data,
723 size, size == data_left,
724 total_len == 0);
725 if (ret)
726 goto err_release;
727
728 data_left -= size;
729 tso_build_data(skb, &tso, size);
730 }
731
732 bdp = fec_enet_get_nextdesc(bdp, fep);
733 }
734
735 /* Save skb pointer */
736 fep->tx_skbuff[index] = skb;
737
738 fec_enet_submit_work(bdp, fep);
739
740 skb_tx_timestamp(skb);
741 fep->cur_tx = bdp;
742
743 /* Trigger transmission start */
744 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
745
746 return 0;
747
748 err_release:
749 /* TODO: Release all used data descriptors for TSO */
750 return ret;
751 }
752
753 static netdev_tx_t
754 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
755 {
756 struct fec_enet_private *fep = netdev_priv(ndev);
757 int entries_free;
758 int ret;
759
760 if (skb_is_gso(skb))
761 ret = fec_enet_txq_submit_tso(skb, ndev);
762 else
763 ret = fec_enet_txq_submit_skb(skb, ndev);
764 if (ret)
765 return ret;
766
767 entries_free = fec_enet_get_free_txdesc_num(fep);
768 if (entries_free <= fep->tx_stop_threshold)
769 netif_stop_queue(ndev);
770
771 return NETDEV_TX_OK;
772 }
773
774 /* Init RX & TX buffer descriptors
775 */
776 static void fec_enet_bd_init(struct net_device *dev)
777 {
778 struct fec_enet_private *fep = netdev_priv(dev);
779 struct bufdesc *bdp;
780 unsigned int i;
781
782 /* Initialize the receive buffer descriptors. */
783 bdp = fep->rx_bd_base;
784 for (i = 0; i < fep->rx_ring_size; i++) {
785
786 /* Initialize the BD for every fragment in the page. */
787 if (bdp->cbd_bufaddr)
788 bdp->cbd_sc = BD_ENET_RX_EMPTY;
789 else
790 bdp->cbd_sc = 0;
791 bdp = fec_enet_get_nextdesc(bdp, fep);
792 }
793
794 /* Set the last buffer to wrap */
795 bdp = fec_enet_get_prevdesc(bdp, fep);
796 bdp->cbd_sc |= BD_SC_WRAP;
797
798 fep->cur_rx = fep->rx_bd_base;
799
800 /* ...and the same for transmit */
801 bdp = fep->tx_bd_base;
802 fep->cur_tx = bdp;
803 for (i = 0; i < fep->tx_ring_size; i++) {
804
805 /* Initialize the BD for every fragment in the page. */
806 bdp->cbd_sc = 0;
807 if (fep->tx_skbuff[i]) {
808 dev_kfree_skb_any(fep->tx_skbuff[i]);
809 fep->tx_skbuff[i] = NULL;
810 }
811 bdp->cbd_bufaddr = 0;
812 bdp = fec_enet_get_nextdesc(bdp, fep);
813 }
814
815 /* Set the last buffer to wrap */
816 bdp = fec_enet_get_prevdesc(bdp, fep);
817 bdp->cbd_sc |= BD_SC_WRAP;
818 fep->dirty_tx = bdp;
819 }
820
821 /*
822 * This function is called to start or restart the FEC during a link
823 * change, transmit timeout, or to reconfigure the FEC. The network
824 * packet processing for this device must be stopped before this call.
825 */
826 static void
827 fec_restart(struct net_device *ndev, int duplex)
828 {
829 struct fec_enet_private *fep = netdev_priv(ndev);
830 const struct platform_device_id *id_entry =
831 platform_get_device_id(fep->pdev);
832 int i;
833 u32 val;
834 u32 temp_mac[2];
835 u32 rcntl = OPT_FRAME_SIZE | 0x04;
836 u32 ecntl = 0x2; /* ETHEREN */
837
838 /* Whack a reset. We should wait for this. */
839 writel(1, fep->hwp + FEC_ECNTRL);
840 udelay(10);
841
842 /*
843 * enet-mac reset will reset mac address registers too,
844 * so need to reconfigure it.
845 */
846 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
847 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
848 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
849 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
850 }
851
852 /* Clear any outstanding interrupt. */
853 writel(0xffc00000, fep->hwp + FEC_IEVENT);
854
855 /* Set maximum receive buffer size. */
856 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
857
858 fec_enet_bd_init(ndev);
859
860 /* Set receive and transmit descriptor base. */
861 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
862 if (fep->bufdesc_ex)
863 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
864 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
865 else
866 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
867 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
868
869
870 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
871 if (fep->tx_skbuff[i]) {
872 dev_kfree_skb_any(fep->tx_skbuff[i]);
873 fep->tx_skbuff[i] = NULL;
874 }
875 }
876
877 /* Enable MII mode */
878 if (duplex) {
879 /* FD enable */
880 writel(0x04, fep->hwp + FEC_X_CNTRL);
881 } else {
882 /* No Rcv on Xmit */
883 rcntl |= 0x02;
884 writel(0x0, fep->hwp + FEC_X_CNTRL);
885 }
886
887 fep->full_duplex = duplex;
888
889 /* Set MII speed */
890 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
891
892 #if !defined(CONFIG_M5272)
893 /* set RX checksum */
894 val = readl(fep->hwp + FEC_RACC);
895 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
896 val |= FEC_RACC_OPTIONS;
897 else
898 val &= ~FEC_RACC_OPTIONS;
899 writel(val, fep->hwp + FEC_RACC);
900 #endif
901
902 /*
903 * The phy interface and speed need to get configured
904 * differently on enet-mac.
905 */
906 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
907 /* Enable flow control and length check */
908 rcntl |= 0x40000000 | 0x00000020;
909
910 /* RGMII, RMII or MII */
911 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
912 rcntl |= (1 << 6);
913 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
914 rcntl |= (1 << 8);
915 else
916 rcntl &= ~(1 << 8);
917
918 /* 1G, 100M or 10M */
919 if (fep->phy_dev) {
920 if (fep->phy_dev->speed == SPEED_1000)
921 ecntl |= (1 << 5);
922 else if (fep->phy_dev->speed == SPEED_100)
923 rcntl &= ~(1 << 9);
924 else
925 rcntl |= (1 << 9);
926 }
927 } else {
928 #ifdef FEC_MIIGSK_ENR
929 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
930 u32 cfgr;
931 /* disable the gasket and wait */
932 writel(0, fep->hwp + FEC_MIIGSK_ENR);
933 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
934 udelay(1);
935
936 /*
937 * configure the gasket:
938 * RMII, 50 MHz, no loopback, no echo
939 * MII, 25 MHz, no loopback, no echo
940 */
941 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
942 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
943 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
944 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
945 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
946
947 /* re-enable the gasket */
948 writel(2, fep->hwp + FEC_MIIGSK_ENR);
949 }
950 #endif
951 }
952
953 #if !defined(CONFIG_M5272)
954 /* enable pause frame*/
955 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
956 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
957 fep->phy_dev && fep->phy_dev->pause)) {
958 rcntl |= FEC_ENET_FCE;
959
960 /* set FIFO threshold parameter to reduce overrun */
961 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
962 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
963 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
964 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
965
966 /* OPD */
967 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
968 } else {
969 rcntl &= ~FEC_ENET_FCE;
970 }
971 #endif /* !defined(CONFIG_M5272) */
972
973 writel(rcntl, fep->hwp + FEC_R_CNTRL);
974
975 /* Setup multicast filter. */
976 set_multicast_list(ndev);
977 #ifndef CONFIG_M5272
978 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
979 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
980 #endif
981
982 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
983 /* enable ENET endian swap */
984 ecntl |= (1 << 8);
985 /* enable ENET store and forward mode */
986 writel(1 << 8, fep->hwp + FEC_X_WMRK);
987 }
988
989 if (fep->bufdesc_ex)
990 ecntl |= (1 << 4);
991
992 #ifndef CONFIG_M5272
993 /* Enable the MIB statistic event counters */
994 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
995 #endif
996
997 /* And last, enable the transmit and receive processing */
998 writel(ecntl, fep->hwp + FEC_ECNTRL);
999 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1000
1001 if (fep->bufdesc_ex)
1002 fec_ptp_start_cyclecounter(ndev);
1003
1004 /* Enable interrupts we wish to service */
1005 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1006 }
1007
1008 static void
1009 fec_stop(struct net_device *ndev)
1010 {
1011 struct fec_enet_private *fep = netdev_priv(ndev);
1012 const struct platform_device_id *id_entry =
1013 platform_get_device_id(fep->pdev);
1014 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1015
1016 /* We cannot expect a graceful transmit stop without link !!! */
1017 if (fep->link) {
1018 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1019 udelay(10);
1020 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1021 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1022 }
1023
1024 /* Whack a reset. We should wait for this. */
1025 writel(1, fep->hwp + FEC_ECNTRL);
1026 udelay(10);
1027 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1028 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1029
1030 /* We have to keep ENET enabled to have MII interrupt stay working */
1031 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
1032 writel(2, fep->hwp + FEC_ECNTRL);
1033 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1034 }
1035 }
1036
1037
1038 static void
1039 fec_timeout(struct net_device *ndev)
1040 {
1041 struct fec_enet_private *fep = netdev_priv(ndev);
1042
1043 ndev->stats.tx_errors++;
1044
1045 fep->delay_work.timeout = true;
1046 schedule_delayed_work(&(fep->delay_work.delay_work), 0);
1047 }
1048
1049 static void fec_enet_work(struct work_struct *work)
1050 {
1051 struct fec_enet_private *fep =
1052 container_of(work,
1053 struct fec_enet_private,
1054 delay_work.delay_work.work);
1055 struct net_device *ndev = fep->netdev;
1056
1057 if (fep->delay_work.timeout) {
1058 fep->delay_work.timeout = false;
1059 rtnl_lock();
1060 if (netif_device_present(ndev) || netif_running(ndev)) {
1061 napi_disable(&fep->napi);
1062 netif_tx_lock_bh(ndev);
1063 fec_restart(ndev, fep->full_duplex);
1064 netif_wake_queue(ndev);
1065 netif_tx_unlock_bh(ndev);
1066 napi_enable(&fep->napi);
1067 }
1068 rtnl_unlock();
1069 }
1070
1071 if (fep->delay_work.trig_tx) {
1072 fep->delay_work.trig_tx = false;
1073 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
1074 }
1075 }
1076
1077 static void
1078 fec_enet_tx(struct net_device *ndev)
1079 {
1080 struct fec_enet_private *fep;
1081 struct bufdesc *bdp;
1082 unsigned short status;
1083 struct sk_buff *skb;
1084 int index = 0;
1085 int entries_free;
1086
1087 fep = netdev_priv(ndev);
1088 bdp = fep->dirty_tx;
1089
1090 /* get next bdp of dirty_tx */
1091 bdp = fec_enet_get_nextdesc(bdp, fep);
1092
1093 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
1094
1095 /* current queue is empty */
1096 if (bdp == fep->cur_tx)
1097 break;
1098
1099 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
1100
1101 skb = fep->tx_skbuff[index];
1102 fep->tx_skbuff[index] = NULL;
1103 if (!IS_TSO_HEADER(fep, bdp->cbd_bufaddr))
1104 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1105 bdp->cbd_datlen, DMA_TO_DEVICE);
1106 bdp->cbd_bufaddr = 0;
1107 if (!skb) {
1108 bdp = fec_enet_get_nextdesc(bdp, fep);
1109 continue;
1110 }
1111
1112 /* Check for errors. */
1113 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1114 BD_ENET_TX_RL | BD_ENET_TX_UN |
1115 BD_ENET_TX_CSL)) {
1116 ndev->stats.tx_errors++;
1117 if (status & BD_ENET_TX_HB) /* No heartbeat */
1118 ndev->stats.tx_heartbeat_errors++;
1119 if (status & BD_ENET_TX_LC) /* Late collision */
1120 ndev->stats.tx_window_errors++;
1121 if (status & BD_ENET_TX_RL) /* Retrans limit */
1122 ndev->stats.tx_aborted_errors++;
1123 if (status & BD_ENET_TX_UN) /* Underrun */
1124 ndev->stats.tx_fifo_errors++;
1125 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1126 ndev->stats.tx_carrier_errors++;
1127 } else {
1128 ndev->stats.tx_packets++;
1129 ndev->stats.tx_bytes += skb->len;
1130 }
1131
1132 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1133 fep->bufdesc_ex) {
1134 struct skb_shared_hwtstamps shhwtstamps;
1135 unsigned long flags;
1136 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1137
1138 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
1139 spin_lock_irqsave(&fep->tmreg_lock, flags);
1140 shhwtstamps.hwtstamp = ns_to_ktime(
1141 timecounter_cyc2time(&fep->tc, ebdp->ts));
1142 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1143 skb_tstamp_tx(skb, &shhwtstamps);
1144 }
1145
1146 if (status & BD_ENET_TX_READY)
1147 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
1148
1149 /* Deferred means some collisions occurred during transmit,
1150 * but we eventually sent the packet OK.
1151 */
1152 if (status & BD_ENET_TX_DEF)
1153 ndev->stats.collisions++;
1154
1155 /* Free the sk buffer associated with this last transmit */
1156 dev_kfree_skb_any(skb);
1157
1158 fep->dirty_tx = bdp;
1159
1160 /* Update pointer to next buffer descriptor to be transmitted */
1161 bdp = fec_enet_get_nextdesc(bdp, fep);
1162
1163 /* Since we have freed up a buffer, the ring is no longer full
1164 */
1165 if (netif_queue_stopped(ndev)) {
1166 entries_free = fec_enet_get_free_txdesc_num(fep);
1167 if (entries_free >= fep->tx_wake_threshold)
1168 netif_wake_queue(ndev);
1169 }
1170 }
1171 return;
1172 }
1173
1174 /* During a receive, the cur_rx points to the current incoming buffer.
1175 * When we update through the ring, if the next incoming buffer has
1176 * not been given to the system, we just set the empty indicator,
1177 * effectively tossing the packet.
1178 */
1179 static int
1180 fec_enet_rx(struct net_device *ndev, int budget)
1181 {
1182 struct fec_enet_private *fep = netdev_priv(ndev);
1183 const struct platform_device_id *id_entry =
1184 platform_get_device_id(fep->pdev);
1185 struct bufdesc *bdp;
1186 unsigned short status;
1187 struct sk_buff *skb;
1188 ushort pkt_len;
1189 __u8 *data;
1190 int pkt_received = 0;
1191 struct bufdesc_ex *ebdp = NULL;
1192 bool vlan_packet_rcvd = false;
1193 u16 vlan_tag;
1194 int index = 0;
1195
1196 #ifdef CONFIG_M532x
1197 flush_cache_all();
1198 #endif
1199
1200 /* First, grab all of the stats for the incoming packet.
1201 * These get messed up if we get called due to a busy condition.
1202 */
1203 bdp = fep->cur_rx;
1204
1205 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1206
1207 if (pkt_received >= budget)
1208 break;
1209 pkt_received++;
1210
1211 /* Since we have allocated space to hold a complete frame,
1212 * the last indicator should be set.
1213 */
1214 if ((status & BD_ENET_RX_LAST) == 0)
1215 netdev_err(ndev, "rcv is not +last\n");
1216
1217 /* Check for errors. */
1218 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1219 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
1220 ndev->stats.rx_errors++;
1221 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1222 /* Frame too long or too short. */
1223 ndev->stats.rx_length_errors++;
1224 }
1225 if (status & BD_ENET_RX_NO) /* Frame alignment */
1226 ndev->stats.rx_frame_errors++;
1227 if (status & BD_ENET_RX_CR) /* CRC Error */
1228 ndev->stats.rx_crc_errors++;
1229 if (status & BD_ENET_RX_OV) /* FIFO overrun */
1230 ndev->stats.rx_fifo_errors++;
1231 }
1232
1233 /* Report late collisions as a frame error.
1234 * On this error, the BD is closed, but we don't know what we
1235 * have in the buffer. So, just drop this frame on the floor.
1236 */
1237 if (status & BD_ENET_RX_CL) {
1238 ndev->stats.rx_errors++;
1239 ndev->stats.rx_frame_errors++;
1240 goto rx_processing_done;
1241 }
1242
1243 /* Process the incoming frame. */
1244 ndev->stats.rx_packets++;
1245 pkt_len = bdp->cbd_datlen;
1246 ndev->stats.rx_bytes += pkt_len;
1247
1248 index = fec_enet_get_bd_index(fep->rx_bd_base, bdp, fep);
1249 data = fep->rx_skbuff[index]->data;
1250 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1251 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1252
1253 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
1254 swap_buffer(data, pkt_len);
1255
1256 /* Extract the enhanced buffer descriptor */
1257 ebdp = NULL;
1258 if (fep->bufdesc_ex)
1259 ebdp = (struct bufdesc_ex *)bdp;
1260
1261 /* If this is a VLAN packet remove the VLAN Tag */
1262 vlan_packet_rcvd = false;
1263 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1264 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
1265 /* Push and remove the vlan tag */
1266 struct vlan_hdr *vlan_header =
1267 (struct vlan_hdr *) (data + ETH_HLEN);
1268 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1269 pkt_len -= VLAN_HLEN;
1270
1271 vlan_packet_rcvd = true;
1272 }
1273
1274 /* This does 16 byte alignment, exactly what we need.
1275 * The packet length includes FCS, but we don't want to
1276 * include that when passing upstream as it messes up
1277 * bridging applications.
1278 */
1279 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
1280
1281 if (unlikely(!skb)) {
1282 ndev->stats.rx_dropped++;
1283 } else {
1284 int payload_offset = (2 * ETH_ALEN);
1285 skb_reserve(skb, NET_IP_ALIGN);
1286 skb_put(skb, pkt_len - 4); /* Make room */
1287
1288 /* Extract the frame data without the VLAN header. */
1289 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
1290 if (vlan_packet_rcvd)
1291 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
1292 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
1293 data + payload_offset,
1294 pkt_len - 4 - (2 * ETH_ALEN));
1295
1296 skb->protocol = eth_type_trans(skb, ndev);
1297
1298 /* Get receive timestamp from the skb */
1299 if (fep->hwts_rx_en && fep->bufdesc_ex) {
1300 struct skb_shared_hwtstamps *shhwtstamps =
1301 skb_hwtstamps(skb);
1302 unsigned long flags;
1303
1304 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1305
1306 spin_lock_irqsave(&fep->tmreg_lock, flags);
1307 shhwtstamps->hwtstamp = ns_to_ktime(
1308 timecounter_cyc2time(&fep->tc, ebdp->ts));
1309 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1310 }
1311
1312 if (fep->bufdesc_ex &&
1313 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1314 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1315 /* don't check it */
1316 skb->ip_summed = CHECKSUM_UNNECESSARY;
1317 } else {
1318 skb_checksum_none_assert(skb);
1319 }
1320 }
1321
1322 /* Handle received VLAN packets */
1323 if (vlan_packet_rcvd)
1324 __vlan_hwaccel_put_tag(skb,
1325 htons(ETH_P_8021Q),
1326 vlan_tag);
1327
1328 napi_gro_receive(&fep->napi, skb);
1329 }
1330
1331 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1332 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1333 rx_processing_done:
1334 /* Clear the status flags for this buffer */
1335 status &= ~BD_ENET_RX_STATS;
1336
1337 /* Mark the buffer empty */
1338 status |= BD_ENET_RX_EMPTY;
1339 bdp->cbd_sc = status;
1340
1341 if (fep->bufdesc_ex) {
1342 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1343
1344 ebdp->cbd_esc = BD_ENET_RX_INT;
1345 ebdp->cbd_prot = 0;
1346 ebdp->cbd_bdu = 0;
1347 }
1348
1349 /* Update BD pointer to next entry */
1350 bdp = fec_enet_get_nextdesc(bdp, fep);
1351
1352 /* Doing this here will keep the FEC running while we process
1353 * incoming frames. On a heavily loaded network, we should be
1354 * able to keep up at the expense of system resources.
1355 */
1356 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1357 }
1358 fep->cur_rx = bdp;
1359
1360 return pkt_received;
1361 }
1362
1363 static irqreturn_t
1364 fec_enet_interrupt(int irq, void *dev_id)
1365 {
1366 struct net_device *ndev = dev_id;
1367 struct fec_enet_private *fep = netdev_priv(ndev);
1368 const unsigned napi_mask = FEC_ENET_RXF | FEC_ENET_TXF;
1369 uint int_events;
1370 irqreturn_t ret = IRQ_NONE;
1371
1372 int_events = readl(fep->hwp + FEC_IEVENT);
1373 writel(int_events & ~napi_mask, fep->hwp + FEC_IEVENT);
1374
1375 if (int_events & napi_mask) {
1376 ret = IRQ_HANDLED;
1377
1378 /* Disable the NAPI interrupts */
1379 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1380 napi_schedule(&fep->napi);
1381 }
1382
1383 if (int_events & FEC_ENET_MII) {
1384 ret = IRQ_HANDLED;
1385 complete(&fep->mdio_done);
1386 }
1387
1388 return ret;
1389 }
1390
1391 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1392 {
1393 struct net_device *ndev = napi->dev;
1394 struct fec_enet_private *fep = netdev_priv(ndev);
1395 int pkts;
1396
1397 /*
1398 * Clear any pending transmit or receive interrupts before
1399 * processing the rings to avoid racing with the hardware.
1400 */
1401 writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT);
1402
1403 pkts = fec_enet_rx(ndev, budget);
1404
1405 fec_enet_tx(ndev);
1406
1407 if (pkts < budget) {
1408 napi_complete(napi);
1409 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1410 }
1411 return pkts;
1412 }
1413
1414 /* ------------------------------------------------------------------------- */
1415 static void fec_get_mac(struct net_device *ndev)
1416 {
1417 struct fec_enet_private *fep = netdev_priv(ndev);
1418 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1419 unsigned char *iap, tmpaddr[ETH_ALEN];
1420
1421 /*
1422 * try to get mac address in following order:
1423 *
1424 * 1) module parameter via kernel command line in form
1425 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1426 */
1427 iap = macaddr;
1428
1429 /*
1430 * 2) from device tree data
1431 */
1432 if (!is_valid_ether_addr(iap)) {
1433 struct device_node *np = fep->pdev->dev.of_node;
1434 if (np) {
1435 const char *mac = of_get_mac_address(np);
1436 if (mac)
1437 iap = (unsigned char *) mac;
1438 }
1439 }
1440
1441 /*
1442 * 3) from flash or fuse (via platform data)
1443 */
1444 if (!is_valid_ether_addr(iap)) {
1445 #ifdef CONFIG_M5272
1446 if (FEC_FLASHMAC)
1447 iap = (unsigned char *)FEC_FLASHMAC;
1448 #else
1449 if (pdata)
1450 iap = (unsigned char *)&pdata->mac;
1451 #endif
1452 }
1453
1454 /*
1455 * 4) FEC mac registers set by bootloader
1456 */
1457 if (!is_valid_ether_addr(iap)) {
1458 *((__be32 *) &tmpaddr[0]) =
1459 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1460 *((__be16 *) &tmpaddr[4]) =
1461 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1462 iap = &tmpaddr[0];
1463 }
1464
1465 /*
1466 * 5) random mac address
1467 */
1468 if (!is_valid_ether_addr(iap)) {
1469 /* Report it and use a random ethernet address instead */
1470 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1471 eth_hw_addr_random(ndev);
1472 netdev_info(ndev, "Using random MAC address: %pM\n",
1473 ndev->dev_addr);
1474 return;
1475 }
1476
1477 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1478
1479 /* Adjust MAC if using macaddr */
1480 if (iap == macaddr)
1481 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1482 }
1483
1484 /* ------------------------------------------------------------------------- */
1485
1486 /*
1487 * Phy section
1488 */
1489 static void fec_enet_adjust_link(struct net_device *ndev)
1490 {
1491 struct fec_enet_private *fep = netdev_priv(ndev);
1492 struct phy_device *phy_dev = fep->phy_dev;
1493 int status_change = 0;
1494
1495 /* Prevent a state halted on mii error */
1496 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1497 phy_dev->state = PHY_RESUMING;
1498 return;
1499 }
1500
1501 /*
1502 * If the netdev is down, or is going down, we're not interested
1503 * in link state events, so just mark our idea of the link as down
1504 * and ignore the event.
1505 */
1506 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1507 fep->link = 0;
1508 } else if (phy_dev->link) {
1509 if (!fep->link) {
1510 fep->link = phy_dev->link;
1511 status_change = 1;
1512 }
1513
1514 if (fep->full_duplex != phy_dev->duplex)
1515 status_change = 1;
1516
1517 if (phy_dev->speed != fep->speed) {
1518 fep->speed = phy_dev->speed;
1519 status_change = 1;
1520 }
1521
1522 /* if any of the above changed restart the FEC */
1523 if (status_change) {
1524 napi_disable(&fep->napi);
1525 netif_tx_lock_bh(ndev);
1526 fec_restart(ndev, phy_dev->duplex);
1527 netif_wake_queue(ndev);
1528 netif_tx_unlock_bh(ndev);
1529 napi_enable(&fep->napi);
1530 }
1531 } else {
1532 if (fep->link) {
1533 fec_stop(ndev);
1534 fep->link = phy_dev->link;
1535 status_change = 1;
1536 }
1537 }
1538
1539 if (status_change)
1540 phy_print_status(phy_dev);
1541 }
1542
1543 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1544 {
1545 struct fec_enet_private *fep = bus->priv;
1546 unsigned long time_left;
1547
1548 fep->mii_timeout = 0;
1549 init_completion(&fep->mdio_done);
1550
1551 /* start a read op */
1552 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1553 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1554 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1555
1556 /* wait for end of transfer */
1557 time_left = wait_for_completion_timeout(&fep->mdio_done,
1558 usecs_to_jiffies(FEC_MII_TIMEOUT));
1559 if (time_left == 0) {
1560 fep->mii_timeout = 1;
1561 netdev_err(fep->netdev, "MDIO read timeout\n");
1562 return -ETIMEDOUT;
1563 }
1564
1565 /* return value */
1566 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1567 }
1568
1569 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1570 u16 value)
1571 {
1572 struct fec_enet_private *fep = bus->priv;
1573 unsigned long time_left;
1574
1575 fep->mii_timeout = 0;
1576 init_completion(&fep->mdio_done);
1577
1578 /* start a write op */
1579 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1580 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1581 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1582 fep->hwp + FEC_MII_DATA);
1583
1584 /* wait for end of transfer */
1585 time_left = wait_for_completion_timeout(&fep->mdio_done,
1586 usecs_to_jiffies(FEC_MII_TIMEOUT));
1587 if (time_left == 0) {
1588 fep->mii_timeout = 1;
1589 netdev_err(fep->netdev, "MDIO write timeout\n");
1590 return -ETIMEDOUT;
1591 }
1592
1593 return 0;
1594 }
1595
1596 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1597 {
1598 struct fec_enet_private *fep = netdev_priv(ndev);
1599 int ret;
1600
1601 if (enable) {
1602 ret = clk_prepare_enable(fep->clk_ahb);
1603 if (ret)
1604 return ret;
1605 ret = clk_prepare_enable(fep->clk_ipg);
1606 if (ret)
1607 goto failed_clk_ipg;
1608 if (fep->clk_enet_out) {
1609 ret = clk_prepare_enable(fep->clk_enet_out);
1610 if (ret)
1611 goto failed_clk_enet_out;
1612 }
1613 if (fep->clk_ptp) {
1614 ret = clk_prepare_enable(fep->clk_ptp);
1615 if (ret)
1616 goto failed_clk_ptp;
1617 }
1618 } else {
1619 clk_disable_unprepare(fep->clk_ahb);
1620 clk_disable_unprepare(fep->clk_ipg);
1621 if (fep->clk_enet_out)
1622 clk_disable_unprepare(fep->clk_enet_out);
1623 if (fep->clk_ptp)
1624 clk_disable_unprepare(fep->clk_ptp);
1625 }
1626
1627 return 0;
1628 failed_clk_ptp:
1629 if (fep->clk_enet_out)
1630 clk_disable_unprepare(fep->clk_enet_out);
1631 failed_clk_enet_out:
1632 clk_disable_unprepare(fep->clk_ipg);
1633 failed_clk_ipg:
1634 clk_disable_unprepare(fep->clk_ahb);
1635
1636 return ret;
1637 }
1638
1639 static int fec_enet_mii_probe(struct net_device *ndev)
1640 {
1641 struct fec_enet_private *fep = netdev_priv(ndev);
1642 const struct platform_device_id *id_entry =
1643 platform_get_device_id(fep->pdev);
1644 struct phy_device *phy_dev = NULL;
1645 char mdio_bus_id[MII_BUS_ID_SIZE];
1646 char phy_name[MII_BUS_ID_SIZE + 3];
1647 int phy_id;
1648 int dev_id = fep->dev_id;
1649
1650 fep->phy_dev = NULL;
1651
1652 /* check for attached phy */
1653 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1654 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1655 continue;
1656 if (fep->mii_bus->phy_map[phy_id] == NULL)
1657 continue;
1658 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1659 continue;
1660 if (dev_id--)
1661 continue;
1662 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1663 break;
1664 }
1665
1666 if (phy_id >= PHY_MAX_ADDR) {
1667 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1668 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1669 phy_id = 0;
1670 }
1671
1672 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1673 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1674 fep->phy_interface);
1675 if (IS_ERR(phy_dev)) {
1676 netdev_err(ndev, "could not attach to PHY\n");
1677 return PTR_ERR(phy_dev);
1678 }
1679
1680 /* mask with MAC supported features */
1681 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1682 phy_dev->supported &= PHY_GBIT_FEATURES;
1683 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1684 #if !defined(CONFIG_M5272)
1685 phy_dev->supported |= SUPPORTED_Pause;
1686 #endif
1687 }
1688 else
1689 phy_dev->supported &= PHY_BASIC_FEATURES;
1690
1691 phy_dev->advertising = phy_dev->supported;
1692
1693 fep->phy_dev = phy_dev;
1694 fep->link = 0;
1695 fep->full_duplex = 0;
1696
1697 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1698 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1699 fep->phy_dev->irq);
1700
1701 return 0;
1702 }
1703
1704 static int fec_enet_mii_init(struct platform_device *pdev)
1705 {
1706 static struct mii_bus *fec0_mii_bus;
1707 struct net_device *ndev = platform_get_drvdata(pdev);
1708 struct fec_enet_private *fep = netdev_priv(ndev);
1709 const struct platform_device_id *id_entry =
1710 platform_get_device_id(fep->pdev);
1711 int err = -ENXIO, i;
1712
1713 /*
1714 * The dual fec interfaces are not equivalent with enet-mac.
1715 * Here are the differences:
1716 *
1717 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1718 * - fec0 acts as the 1588 time master while fec1 is slave
1719 * - external phys can only be configured by fec0
1720 *
1721 * That is to say fec1 can not work independently. It only works
1722 * when fec0 is working. The reason behind this design is that the
1723 * second interface is added primarily for Switch mode.
1724 *
1725 * Because of the last point above, both phys are attached on fec0
1726 * mdio interface in board design, and need to be configured by
1727 * fec0 mii_bus.
1728 */
1729 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1730 /* fec1 uses fec0 mii_bus */
1731 if (mii_cnt && fec0_mii_bus) {
1732 fep->mii_bus = fec0_mii_bus;
1733 mii_cnt++;
1734 return 0;
1735 }
1736 return -ENOENT;
1737 }
1738
1739 fep->mii_timeout = 0;
1740
1741 /*
1742 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1743 *
1744 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1745 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1746 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1747 * document.
1748 */
1749 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
1750 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1751 fep->phy_speed--;
1752 fep->phy_speed <<= 1;
1753 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1754
1755 fep->mii_bus = mdiobus_alloc();
1756 if (fep->mii_bus == NULL) {
1757 err = -ENOMEM;
1758 goto err_out;
1759 }
1760
1761 fep->mii_bus->name = "fec_enet_mii_bus";
1762 fep->mii_bus->read = fec_enet_mdio_read;
1763 fep->mii_bus->write = fec_enet_mdio_write;
1764 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1765 pdev->name, fep->dev_id + 1);
1766 fep->mii_bus->priv = fep;
1767 fep->mii_bus->parent = &pdev->dev;
1768
1769 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1770 if (!fep->mii_bus->irq) {
1771 err = -ENOMEM;
1772 goto err_out_free_mdiobus;
1773 }
1774
1775 for (i = 0; i < PHY_MAX_ADDR; i++)
1776 fep->mii_bus->irq[i] = PHY_POLL;
1777
1778 if (mdiobus_register(fep->mii_bus))
1779 goto err_out_free_mdio_irq;
1780
1781 mii_cnt++;
1782
1783 /* save fec0 mii_bus */
1784 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1785 fec0_mii_bus = fep->mii_bus;
1786
1787 return 0;
1788
1789 err_out_free_mdio_irq:
1790 kfree(fep->mii_bus->irq);
1791 err_out_free_mdiobus:
1792 mdiobus_free(fep->mii_bus);
1793 err_out:
1794 return err;
1795 }
1796
1797 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1798 {
1799 if (--mii_cnt == 0) {
1800 mdiobus_unregister(fep->mii_bus);
1801 kfree(fep->mii_bus->irq);
1802 mdiobus_free(fep->mii_bus);
1803 }
1804 }
1805
1806 static int fec_enet_get_settings(struct net_device *ndev,
1807 struct ethtool_cmd *cmd)
1808 {
1809 struct fec_enet_private *fep = netdev_priv(ndev);
1810 struct phy_device *phydev = fep->phy_dev;
1811
1812 if (!phydev)
1813 return -ENODEV;
1814
1815 return phy_ethtool_gset(phydev, cmd);
1816 }
1817
1818 static int fec_enet_set_settings(struct net_device *ndev,
1819 struct ethtool_cmd *cmd)
1820 {
1821 struct fec_enet_private *fep = netdev_priv(ndev);
1822 struct phy_device *phydev = fep->phy_dev;
1823
1824 if (!phydev)
1825 return -ENODEV;
1826
1827 return phy_ethtool_sset(phydev, cmd);
1828 }
1829
1830 static void fec_enet_get_drvinfo(struct net_device *ndev,
1831 struct ethtool_drvinfo *info)
1832 {
1833 struct fec_enet_private *fep = netdev_priv(ndev);
1834
1835 strlcpy(info->driver, fep->pdev->dev.driver->name,
1836 sizeof(info->driver));
1837 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1838 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1839 }
1840
1841 static int fec_enet_get_ts_info(struct net_device *ndev,
1842 struct ethtool_ts_info *info)
1843 {
1844 struct fec_enet_private *fep = netdev_priv(ndev);
1845
1846 if (fep->bufdesc_ex) {
1847
1848 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1849 SOF_TIMESTAMPING_RX_SOFTWARE |
1850 SOF_TIMESTAMPING_SOFTWARE |
1851 SOF_TIMESTAMPING_TX_HARDWARE |
1852 SOF_TIMESTAMPING_RX_HARDWARE |
1853 SOF_TIMESTAMPING_RAW_HARDWARE;
1854 if (fep->ptp_clock)
1855 info->phc_index = ptp_clock_index(fep->ptp_clock);
1856 else
1857 info->phc_index = -1;
1858
1859 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1860 (1 << HWTSTAMP_TX_ON);
1861
1862 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1863 (1 << HWTSTAMP_FILTER_ALL);
1864 return 0;
1865 } else {
1866 return ethtool_op_get_ts_info(ndev, info);
1867 }
1868 }
1869
1870 #if !defined(CONFIG_M5272)
1871
1872 static void fec_enet_get_pauseparam(struct net_device *ndev,
1873 struct ethtool_pauseparam *pause)
1874 {
1875 struct fec_enet_private *fep = netdev_priv(ndev);
1876
1877 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1878 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1879 pause->rx_pause = pause->tx_pause;
1880 }
1881
1882 static int fec_enet_set_pauseparam(struct net_device *ndev,
1883 struct ethtool_pauseparam *pause)
1884 {
1885 struct fec_enet_private *fep = netdev_priv(ndev);
1886
1887 if (!fep->phy_dev)
1888 return -ENODEV;
1889
1890 if (pause->tx_pause != pause->rx_pause) {
1891 netdev_info(ndev,
1892 "hardware only support enable/disable both tx and rx");
1893 return -EINVAL;
1894 }
1895
1896 fep->pause_flag = 0;
1897
1898 /* tx pause must be same as rx pause */
1899 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1900 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1901
1902 if (pause->rx_pause || pause->autoneg) {
1903 fep->phy_dev->supported |= ADVERTISED_Pause;
1904 fep->phy_dev->advertising |= ADVERTISED_Pause;
1905 } else {
1906 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1907 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1908 }
1909
1910 if (pause->autoneg) {
1911 if (netif_running(ndev))
1912 fec_stop(ndev);
1913 phy_start_aneg(fep->phy_dev);
1914 }
1915 if (netif_running(ndev)) {
1916 napi_disable(&fep->napi);
1917 netif_tx_lock_bh(ndev);
1918 fec_restart(ndev, fep->full_duplex);
1919 netif_wake_queue(ndev);
1920 netif_tx_unlock_bh(ndev);
1921 napi_enable(&fep->napi);
1922 }
1923
1924 return 0;
1925 }
1926
1927 static const struct fec_stat {
1928 char name[ETH_GSTRING_LEN];
1929 u16 offset;
1930 } fec_stats[] = {
1931 /* RMON TX */
1932 { "tx_dropped", RMON_T_DROP },
1933 { "tx_packets", RMON_T_PACKETS },
1934 { "tx_broadcast", RMON_T_BC_PKT },
1935 { "tx_multicast", RMON_T_MC_PKT },
1936 { "tx_crc_errors", RMON_T_CRC_ALIGN },
1937 { "tx_undersize", RMON_T_UNDERSIZE },
1938 { "tx_oversize", RMON_T_OVERSIZE },
1939 { "tx_fragment", RMON_T_FRAG },
1940 { "tx_jabber", RMON_T_JAB },
1941 { "tx_collision", RMON_T_COL },
1942 { "tx_64byte", RMON_T_P64 },
1943 { "tx_65to127byte", RMON_T_P65TO127 },
1944 { "tx_128to255byte", RMON_T_P128TO255 },
1945 { "tx_256to511byte", RMON_T_P256TO511 },
1946 { "tx_512to1023byte", RMON_T_P512TO1023 },
1947 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
1948 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
1949 { "tx_octets", RMON_T_OCTETS },
1950
1951 /* IEEE TX */
1952 { "IEEE_tx_drop", IEEE_T_DROP },
1953 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
1954 { "IEEE_tx_1col", IEEE_T_1COL },
1955 { "IEEE_tx_mcol", IEEE_T_MCOL },
1956 { "IEEE_tx_def", IEEE_T_DEF },
1957 { "IEEE_tx_lcol", IEEE_T_LCOL },
1958 { "IEEE_tx_excol", IEEE_T_EXCOL },
1959 { "IEEE_tx_macerr", IEEE_T_MACERR },
1960 { "IEEE_tx_cserr", IEEE_T_CSERR },
1961 { "IEEE_tx_sqe", IEEE_T_SQE },
1962 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
1963 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
1964
1965 /* RMON RX */
1966 { "rx_packets", RMON_R_PACKETS },
1967 { "rx_broadcast", RMON_R_BC_PKT },
1968 { "rx_multicast", RMON_R_MC_PKT },
1969 { "rx_crc_errors", RMON_R_CRC_ALIGN },
1970 { "rx_undersize", RMON_R_UNDERSIZE },
1971 { "rx_oversize", RMON_R_OVERSIZE },
1972 { "rx_fragment", RMON_R_FRAG },
1973 { "rx_jabber", RMON_R_JAB },
1974 { "rx_64byte", RMON_R_P64 },
1975 { "rx_65to127byte", RMON_R_P65TO127 },
1976 { "rx_128to255byte", RMON_R_P128TO255 },
1977 { "rx_256to511byte", RMON_R_P256TO511 },
1978 { "rx_512to1023byte", RMON_R_P512TO1023 },
1979 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
1980 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
1981 { "rx_octets", RMON_R_OCTETS },
1982
1983 /* IEEE RX */
1984 { "IEEE_rx_drop", IEEE_R_DROP },
1985 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
1986 { "IEEE_rx_crc", IEEE_R_CRC },
1987 { "IEEE_rx_align", IEEE_R_ALIGN },
1988 { "IEEE_rx_macerr", IEEE_R_MACERR },
1989 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
1990 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
1991 };
1992
1993 static void fec_enet_get_ethtool_stats(struct net_device *dev,
1994 struct ethtool_stats *stats, u64 *data)
1995 {
1996 struct fec_enet_private *fep = netdev_priv(dev);
1997 int i;
1998
1999 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2000 data[i] = readl(fep->hwp + fec_stats[i].offset);
2001 }
2002
2003 static void fec_enet_get_strings(struct net_device *netdev,
2004 u32 stringset, u8 *data)
2005 {
2006 int i;
2007 switch (stringset) {
2008 case ETH_SS_STATS:
2009 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2010 memcpy(data + i * ETH_GSTRING_LEN,
2011 fec_stats[i].name, ETH_GSTRING_LEN);
2012 break;
2013 }
2014 }
2015
2016 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2017 {
2018 switch (sset) {
2019 case ETH_SS_STATS:
2020 return ARRAY_SIZE(fec_stats);
2021 default:
2022 return -EOPNOTSUPP;
2023 }
2024 }
2025 #endif /* !defined(CONFIG_M5272) */
2026
2027 static int fec_enet_nway_reset(struct net_device *dev)
2028 {
2029 struct fec_enet_private *fep = netdev_priv(dev);
2030 struct phy_device *phydev = fep->phy_dev;
2031
2032 if (!phydev)
2033 return -ENODEV;
2034
2035 return genphy_restart_aneg(phydev);
2036 }
2037
2038 static const struct ethtool_ops fec_enet_ethtool_ops = {
2039 #if !defined(CONFIG_M5272)
2040 .get_pauseparam = fec_enet_get_pauseparam,
2041 .set_pauseparam = fec_enet_set_pauseparam,
2042 #endif
2043 .get_settings = fec_enet_get_settings,
2044 .set_settings = fec_enet_set_settings,
2045 .get_drvinfo = fec_enet_get_drvinfo,
2046 .get_link = ethtool_op_get_link,
2047 .get_ts_info = fec_enet_get_ts_info,
2048 .nway_reset = fec_enet_nway_reset,
2049 #ifndef CONFIG_M5272
2050 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2051 .get_strings = fec_enet_get_strings,
2052 .get_sset_count = fec_enet_get_sset_count,
2053 #endif
2054 };
2055
2056 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2057 {
2058 struct fec_enet_private *fep = netdev_priv(ndev);
2059 struct phy_device *phydev = fep->phy_dev;
2060
2061 if (!netif_running(ndev))
2062 return -EINVAL;
2063
2064 if (!phydev)
2065 return -ENODEV;
2066
2067 if (fep->bufdesc_ex) {
2068 if (cmd == SIOCSHWTSTAMP)
2069 return fec_ptp_set(ndev, rq);
2070 if (cmd == SIOCGHWTSTAMP)
2071 return fec_ptp_get(ndev, rq);
2072 }
2073
2074 return phy_mii_ioctl(phydev, rq, cmd);
2075 }
2076
2077 static void fec_enet_free_buffers(struct net_device *ndev)
2078 {
2079 struct fec_enet_private *fep = netdev_priv(ndev);
2080 unsigned int i;
2081 struct sk_buff *skb;
2082 struct bufdesc *bdp;
2083
2084 bdp = fep->rx_bd_base;
2085 for (i = 0; i < fep->rx_ring_size; i++) {
2086 skb = fep->rx_skbuff[i];
2087 fep->rx_skbuff[i] = NULL;
2088 if (skb) {
2089 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
2090 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
2091 dev_kfree_skb(skb);
2092 }
2093 bdp = fec_enet_get_nextdesc(bdp, fep);
2094 }
2095
2096 bdp = fep->tx_bd_base;
2097 for (i = 0; i < fep->tx_ring_size; i++) {
2098 kfree(fep->tx_bounce[i]);
2099 fep->tx_bounce[i] = NULL;
2100 skb = fep->tx_skbuff[i];
2101 fep->tx_skbuff[i] = NULL;
2102 dev_kfree_skb(skb);
2103 }
2104 }
2105
2106 static int fec_enet_alloc_buffers(struct net_device *ndev)
2107 {
2108 struct fec_enet_private *fep = netdev_priv(ndev);
2109 unsigned int i;
2110 struct sk_buff *skb;
2111 struct bufdesc *bdp;
2112
2113 bdp = fep->rx_bd_base;
2114 for (i = 0; i < fep->rx_ring_size; i++) {
2115 dma_addr_t addr;
2116
2117 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2118 if (!skb)
2119 goto err_alloc;
2120
2121 addr = dma_map_single(&fep->pdev->dev, skb->data,
2122 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
2123 if (dma_mapping_error(&fep->pdev->dev, addr)) {
2124 dev_kfree_skb(skb);
2125 if (net_ratelimit())
2126 netdev_err(ndev, "Rx DMA memory map failed\n");
2127 goto err_alloc;
2128 }
2129
2130 fep->rx_skbuff[i] = skb;
2131 bdp->cbd_bufaddr = addr;
2132 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2133
2134 if (fep->bufdesc_ex) {
2135 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2136 ebdp->cbd_esc = BD_ENET_RX_INT;
2137 }
2138
2139 bdp = fec_enet_get_nextdesc(bdp, fep);
2140 }
2141
2142 /* Set the last buffer to wrap. */
2143 bdp = fec_enet_get_prevdesc(bdp, fep);
2144 bdp->cbd_sc |= BD_SC_WRAP;
2145
2146 bdp = fep->tx_bd_base;
2147 for (i = 0; i < fep->tx_ring_size; i++) {
2148 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2149 if (!fep->tx_bounce[i])
2150 goto err_alloc;
2151
2152 bdp->cbd_sc = 0;
2153 bdp->cbd_bufaddr = 0;
2154
2155 if (fep->bufdesc_ex) {
2156 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2157 ebdp->cbd_esc = BD_ENET_TX_INT;
2158 }
2159
2160 bdp = fec_enet_get_nextdesc(bdp, fep);
2161 }
2162
2163 /* Set the last buffer to wrap. */
2164 bdp = fec_enet_get_prevdesc(bdp, fep);
2165 bdp->cbd_sc |= BD_SC_WRAP;
2166
2167 return 0;
2168
2169 err_alloc:
2170 fec_enet_free_buffers(ndev);
2171 return -ENOMEM;
2172 }
2173
2174 static int
2175 fec_enet_open(struct net_device *ndev)
2176 {
2177 struct fec_enet_private *fep = netdev_priv(ndev);
2178 int ret;
2179
2180 pinctrl_pm_select_default_state(&fep->pdev->dev);
2181 ret = fec_enet_clk_enable(ndev, true);
2182 if (ret)
2183 return ret;
2184
2185 /* I should reset the ring buffers here, but I don't yet know
2186 * a simple way to do that.
2187 */
2188
2189 ret = fec_enet_alloc_buffers(ndev);
2190 if (ret)
2191 return ret;
2192
2193 /* Probe and connect to PHY when open the interface */
2194 ret = fec_enet_mii_probe(ndev);
2195 if (ret) {
2196 fec_enet_free_buffers(ndev);
2197 return ret;
2198 }
2199
2200 fec_restart(ndev, fep->full_duplex);
2201 napi_enable(&fep->napi);
2202 phy_start(fep->phy_dev);
2203 netif_start_queue(ndev);
2204 return 0;
2205 }
2206
2207 static int
2208 fec_enet_close(struct net_device *ndev)
2209 {
2210 struct fec_enet_private *fep = netdev_priv(ndev);
2211
2212 phy_stop(fep->phy_dev);
2213
2214 napi_disable(&fep->napi);
2215 netif_tx_disable(ndev);
2216 if (netif_device_present(ndev))
2217 fec_stop(ndev);
2218
2219 phy_disconnect(fep->phy_dev);
2220 fep->phy_dev = NULL;
2221
2222 fec_enet_clk_enable(ndev, false);
2223 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2224 fec_enet_free_buffers(ndev);
2225
2226 return 0;
2227 }
2228
2229 /* Set or clear the multicast filter for this adaptor.
2230 * Skeleton taken from sunlance driver.
2231 * The CPM Ethernet implementation allows Multicast as well as individual
2232 * MAC address filtering. Some of the drivers check to make sure it is
2233 * a group multicast address, and discard those that are not. I guess I
2234 * will do the same for now, but just remove the test if you want
2235 * individual filtering as well (do the upper net layers want or support
2236 * this kind of feature?).
2237 */
2238
2239 #define HASH_BITS 6 /* #bits in hash */
2240 #define CRC32_POLY 0xEDB88320
2241
2242 static void set_multicast_list(struct net_device *ndev)
2243 {
2244 struct fec_enet_private *fep = netdev_priv(ndev);
2245 struct netdev_hw_addr *ha;
2246 unsigned int i, bit, data, crc, tmp;
2247 unsigned char hash;
2248
2249 if (ndev->flags & IFF_PROMISC) {
2250 tmp = readl(fep->hwp + FEC_R_CNTRL);
2251 tmp |= 0x8;
2252 writel(tmp, fep->hwp + FEC_R_CNTRL);
2253 return;
2254 }
2255
2256 tmp = readl(fep->hwp + FEC_R_CNTRL);
2257 tmp &= ~0x8;
2258 writel(tmp, fep->hwp + FEC_R_CNTRL);
2259
2260 if (ndev->flags & IFF_ALLMULTI) {
2261 /* Catch all multicast addresses, so set the
2262 * filter to all 1's
2263 */
2264 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2265 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2266
2267 return;
2268 }
2269
2270 /* Clear filter and add the addresses in hash register
2271 */
2272 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2273 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2274
2275 netdev_for_each_mc_addr(ha, ndev) {
2276 /* calculate crc32 value of mac address */
2277 crc = 0xffffffff;
2278
2279 for (i = 0; i < ndev->addr_len; i++) {
2280 data = ha->addr[i];
2281 for (bit = 0; bit < 8; bit++, data >>= 1) {
2282 crc = (crc >> 1) ^
2283 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2284 }
2285 }
2286
2287 /* only upper 6 bits (HASH_BITS) are used
2288 * which point to specific bit in he hash registers
2289 */
2290 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2291
2292 if (hash > 31) {
2293 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2294 tmp |= 1 << (hash - 32);
2295 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2296 } else {
2297 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2298 tmp |= 1 << hash;
2299 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2300 }
2301 }
2302 }
2303
2304 /* Set a MAC change in hardware. */
2305 static int
2306 fec_set_mac_address(struct net_device *ndev, void *p)
2307 {
2308 struct fec_enet_private *fep = netdev_priv(ndev);
2309 struct sockaddr *addr = p;
2310
2311 if (addr) {
2312 if (!is_valid_ether_addr(addr->sa_data))
2313 return -EADDRNOTAVAIL;
2314 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2315 }
2316
2317 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2318 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
2319 fep->hwp + FEC_ADDR_LOW);
2320 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
2321 fep->hwp + FEC_ADDR_HIGH);
2322 return 0;
2323 }
2324
2325 #ifdef CONFIG_NET_POLL_CONTROLLER
2326 /**
2327 * fec_poll_controller - FEC Poll controller function
2328 * @dev: The FEC network adapter
2329 *
2330 * Polled functionality used by netconsole and others in non interrupt mode
2331 *
2332 */
2333 static void fec_poll_controller(struct net_device *dev)
2334 {
2335 int i;
2336 struct fec_enet_private *fep = netdev_priv(dev);
2337
2338 for (i = 0; i < FEC_IRQ_NUM; i++) {
2339 if (fep->irq[i] > 0) {
2340 disable_irq(fep->irq[i]);
2341 fec_enet_interrupt(fep->irq[i], dev);
2342 enable_irq(fep->irq[i]);
2343 }
2344 }
2345 }
2346 #endif
2347
2348 static int fec_set_features(struct net_device *netdev,
2349 netdev_features_t features)
2350 {
2351 struct fec_enet_private *fep = netdev_priv(netdev);
2352 netdev_features_t changed = features ^ netdev->features;
2353
2354 netdev->features = features;
2355
2356 /* Receive checksum has been changed */
2357 if (changed & NETIF_F_RXCSUM) {
2358 if (features & NETIF_F_RXCSUM)
2359 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2360 else
2361 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
2362
2363 if (netif_running(netdev)) {
2364 fec_stop(netdev);
2365 napi_disable(&fep->napi);
2366 netif_tx_lock_bh(netdev);
2367 fec_restart(netdev, fep->phy_dev->duplex);
2368 netif_wake_queue(netdev);
2369 netif_tx_unlock_bh(netdev);
2370 napi_enable(&fep->napi);
2371 }
2372 }
2373
2374 return 0;
2375 }
2376
2377 static const struct net_device_ops fec_netdev_ops = {
2378 .ndo_open = fec_enet_open,
2379 .ndo_stop = fec_enet_close,
2380 .ndo_start_xmit = fec_enet_start_xmit,
2381 .ndo_set_rx_mode = set_multicast_list,
2382 .ndo_change_mtu = eth_change_mtu,
2383 .ndo_validate_addr = eth_validate_addr,
2384 .ndo_tx_timeout = fec_timeout,
2385 .ndo_set_mac_address = fec_set_mac_address,
2386 .ndo_do_ioctl = fec_enet_ioctl,
2387 #ifdef CONFIG_NET_POLL_CONTROLLER
2388 .ndo_poll_controller = fec_poll_controller,
2389 #endif
2390 .ndo_set_features = fec_set_features,
2391 };
2392
2393 /*
2394 * XXX: We need to clean up on failure exits here.
2395 *
2396 */
2397 static int fec_enet_init(struct net_device *ndev)
2398 {
2399 struct fec_enet_private *fep = netdev_priv(ndev);
2400 const struct platform_device_id *id_entry =
2401 platform_get_device_id(fep->pdev);
2402 struct bufdesc *cbd_base;
2403 int bd_size;
2404
2405 /* init the tx & rx ring size */
2406 fep->tx_ring_size = TX_RING_SIZE;
2407 fep->rx_ring_size = RX_RING_SIZE;
2408
2409 fep->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2410 fep->tx_wake_threshold = (fep->tx_ring_size - fep->tx_stop_threshold) / 2;
2411
2412 if (fep->bufdesc_ex)
2413 fep->bufdesc_size = sizeof(struct bufdesc_ex);
2414 else
2415 fep->bufdesc_size = sizeof(struct bufdesc);
2416 bd_size = (fep->tx_ring_size + fep->rx_ring_size) *
2417 fep->bufdesc_size;
2418
2419 /* Allocate memory for buffer descriptors. */
2420 cbd_base = dma_alloc_coherent(NULL, bd_size, &fep->bd_dma,
2421 GFP_KERNEL);
2422 if (!cbd_base)
2423 return -ENOMEM;
2424
2425 fep->tso_hdrs = dma_alloc_coherent(NULL, fep->tx_ring_size * TSO_HEADER_SIZE,
2426 &fep->tso_hdrs_dma, GFP_KERNEL);
2427 if (!fep->tso_hdrs) {
2428 dma_free_coherent(NULL, bd_size, cbd_base, fep->bd_dma);
2429 return -ENOMEM;
2430 }
2431
2432 memset(cbd_base, 0, PAGE_SIZE);
2433
2434 fep->netdev = ndev;
2435
2436 /* Get the Ethernet address */
2437 fec_get_mac(ndev);
2438 /* make sure MAC we just acquired is programmed into the hw */
2439 fec_set_mac_address(ndev, NULL);
2440
2441 /* Set receive and transmit descriptor base. */
2442 fep->rx_bd_base = cbd_base;
2443 if (fep->bufdesc_ex)
2444 fep->tx_bd_base = (struct bufdesc *)
2445 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size);
2446 else
2447 fep->tx_bd_base = cbd_base + fep->rx_ring_size;
2448
2449 /* The FEC Ethernet specific entries in the device structure */
2450 ndev->watchdog_timeo = TX_TIMEOUT;
2451 ndev->netdev_ops = &fec_netdev_ops;
2452 ndev->ethtool_ops = &fec_enet_ethtool_ops;
2453
2454 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
2455 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
2456
2457 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN)
2458 /* enable hw VLAN support */
2459 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2460
2461 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
2462 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
2463
2464 /* enable hw accelerator */
2465 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2466 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
2467 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2468 }
2469
2470 ndev->hw_features = ndev->features;
2471
2472 fec_restart(ndev, 0);
2473
2474 return 0;
2475 }
2476
2477 #ifdef CONFIG_OF
2478 static void fec_reset_phy(struct platform_device *pdev)
2479 {
2480 int err, phy_reset;
2481 int msec = 1;
2482 struct device_node *np = pdev->dev.of_node;
2483
2484 if (!np)
2485 return;
2486
2487 of_property_read_u32(np, "phy-reset-duration", &msec);
2488 /* A sane reset duration should not be longer than 1s */
2489 if (msec > 1000)
2490 msec = 1;
2491
2492 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
2493 if (!gpio_is_valid(phy_reset))
2494 return;
2495
2496 err = devm_gpio_request_one(&pdev->dev, phy_reset,
2497 GPIOF_OUT_INIT_LOW, "phy-reset");
2498 if (err) {
2499 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
2500 return;
2501 }
2502 msleep(msec);
2503 gpio_set_value(phy_reset, 1);
2504 }
2505 #else /* CONFIG_OF */
2506 static void fec_reset_phy(struct platform_device *pdev)
2507 {
2508 /*
2509 * In case of platform probe, the reset has been done
2510 * by machine code.
2511 */
2512 }
2513 #endif /* CONFIG_OF */
2514
2515 static int
2516 fec_probe(struct platform_device *pdev)
2517 {
2518 struct fec_enet_private *fep;
2519 struct fec_platform_data *pdata;
2520 struct net_device *ndev;
2521 int i, irq, ret = 0;
2522 struct resource *r;
2523 const struct of_device_id *of_id;
2524 static int dev_id;
2525
2526 of_id = of_match_device(fec_dt_ids, &pdev->dev);
2527 if (of_id)
2528 pdev->id_entry = of_id->data;
2529
2530 /* Init network device */
2531 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
2532 if (!ndev)
2533 return -ENOMEM;
2534
2535 SET_NETDEV_DEV(ndev, &pdev->dev);
2536
2537 /* setup board info structure */
2538 fep = netdev_priv(ndev);
2539
2540 #if !defined(CONFIG_M5272)
2541 /* default enable pause frame auto negotiation */
2542 if (pdev->id_entry &&
2543 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
2544 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
2545 #endif
2546
2547 /* Select default pin state */
2548 pinctrl_pm_select_default_state(&pdev->dev);
2549
2550 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2551 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
2552 if (IS_ERR(fep->hwp)) {
2553 ret = PTR_ERR(fep->hwp);
2554 goto failed_ioremap;
2555 }
2556
2557 fep->pdev = pdev;
2558 fep->dev_id = dev_id++;
2559
2560 fep->bufdesc_ex = 0;
2561
2562 platform_set_drvdata(pdev, ndev);
2563
2564 ret = of_get_phy_mode(pdev->dev.of_node);
2565 if (ret < 0) {
2566 pdata = dev_get_platdata(&pdev->dev);
2567 if (pdata)
2568 fep->phy_interface = pdata->phy;
2569 else
2570 fep->phy_interface = PHY_INTERFACE_MODE_MII;
2571 } else {
2572 fep->phy_interface = ret;
2573 }
2574
2575 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2576 if (IS_ERR(fep->clk_ipg)) {
2577 ret = PTR_ERR(fep->clk_ipg);
2578 goto failed_clk;
2579 }
2580
2581 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2582 if (IS_ERR(fep->clk_ahb)) {
2583 ret = PTR_ERR(fep->clk_ahb);
2584 goto failed_clk;
2585 }
2586
2587 /* enet_out is optional, depends on board */
2588 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
2589 if (IS_ERR(fep->clk_enet_out))
2590 fep->clk_enet_out = NULL;
2591
2592 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
2593 fep->bufdesc_ex =
2594 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
2595 if (IS_ERR(fep->clk_ptp)) {
2596 fep->clk_ptp = NULL;
2597 fep->bufdesc_ex = 0;
2598 }
2599
2600 ret = fec_enet_clk_enable(ndev, true);
2601 if (ret)
2602 goto failed_clk;
2603
2604 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
2605 if (!IS_ERR(fep->reg_phy)) {
2606 ret = regulator_enable(fep->reg_phy);
2607 if (ret) {
2608 dev_err(&pdev->dev,
2609 "Failed to enable phy regulator: %d\n", ret);
2610 goto failed_regulator;
2611 }
2612 } else {
2613 fep->reg_phy = NULL;
2614 }
2615
2616 fec_reset_phy(pdev);
2617
2618 if (fep->bufdesc_ex)
2619 fec_ptp_init(pdev);
2620
2621 ret = fec_enet_init(ndev);
2622 if (ret)
2623 goto failed_init;
2624
2625 for (i = 0; i < FEC_IRQ_NUM; i++) {
2626 irq = platform_get_irq(pdev, i);
2627 if (irq < 0) {
2628 if (i)
2629 break;
2630 ret = irq;
2631 goto failed_irq;
2632 }
2633 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
2634 0, pdev->name, ndev);
2635 if (ret)
2636 goto failed_irq;
2637 }
2638
2639 ret = fec_enet_mii_init(pdev);
2640 if (ret)
2641 goto failed_mii_init;
2642
2643 /* Carrier starts down, phylib will bring it up */
2644 netif_carrier_off(ndev);
2645 fec_enet_clk_enable(ndev, false);
2646 pinctrl_pm_select_sleep_state(&pdev->dev);
2647
2648 ret = register_netdev(ndev);
2649 if (ret)
2650 goto failed_register;
2651
2652 if (fep->bufdesc_ex && fep->ptp_clock)
2653 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
2654
2655 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
2656 return 0;
2657
2658 failed_register:
2659 fec_enet_mii_remove(fep);
2660 failed_mii_init:
2661 failed_irq:
2662 failed_init:
2663 if (fep->reg_phy)
2664 regulator_disable(fep->reg_phy);
2665 failed_regulator:
2666 fec_enet_clk_enable(ndev, false);
2667 failed_clk:
2668 failed_ioremap:
2669 free_netdev(ndev);
2670
2671 return ret;
2672 }
2673
2674 static int
2675 fec_drv_remove(struct platform_device *pdev)
2676 {
2677 struct net_device *ndev = platform_get_drvdata(pdev);
2678 struct fec_enet_private *fep = netdev_priv(ndev);
2679
2680 cancel_delayed_work_sync(&(fep->delay_work.delay_work));
2681 unregister_netdev(ndev);
2682 fec_enet_mii_remove(fep);
2683 del_timer_sync(&fep->time_keep);
2684 if (fep->reg_phy)
2685 regulator_disable(fep->reg_phy);
2686 if (fep->ptp_clock)
2687 ptp_clock_unregister(fep->ptp_clock);
2688 fec_enet_clk_enable(ndev, false);
2689 free_netdev(ndev);
2690
2691 return 0;
2692 }
2693
2694 #ifdef CONFIG_PM_SLEEP
2695 static int
2696 fec_suspend(struct device *dev)
2697 {
2698 struct net_device *ndev = dev_get_drvdata(dev);
2699 struct fec_enet_private *fep = netdev_priv(ndev);
2700
2701 rtnl_lock();
2702 if (netif_running(ndev)) {
2703 phy_stop(fep->phy_dev);
2704 fec_stop(ndev);
2705 netif_device_detach(ndev);
2706 }
2707 rtnl_unlock();
2708
2709 fec_enet_clk_enable(ndev, false);
2710 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2711
2712 if (fep->reg_phy)
2713 regulator_disable(fep->reg_phy);
2714
2715 return 0;
2716 }
2717
2718 static int
2719 fec_resume(struct device *dev)
2720 {
2721 struct net_device *ndev = dev_get_drvdata(dev);
2722 struct fec_enet_private *fep = netdev_priv(ndev);
2723 int ret;
2724
2725 if (fep->reg_phy) {
2726 ret = regulator_enable(fep->reg_phy);
2727 if (ret)
2728 return ret;
2729 }
2730
2731 pinctrl_pm_select_default_state(&fep->pdev->dev);
2732 ret = fec_enet_clk_enable(ndev, true);
2733 if (ret)
2734 goto failed_clk;
2735
2736 rtnl_lock();
2737 if (netif_running(ndev)) {
2738 napi_disable(&fep->napi);
2739 netif_tx_lock_bh(ndev);
2740 fec_restart(ndev, fep->full_duplex);
2741 netif_device_attach(ndev);
2742 netif_tx_unlock_bh(ndev);
2743 netif_device_attach(ndev);
2744 napi_enable(&fep->napi);
2745 phy_start(fep->phy_dev);
2746 }
2747 rtnl_unlock();
2748
2749 return 0;
2750
2751 failed_clk:
2752 if (fep->reg_phy)
2753 regulator_disable(fep->reg_phy);
2754 return ret;
2755 }
2756 #endif /* CONFIG_PM_SLEEP */
2757
2758 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
2759
2760 static struct platform_driver fec_driver = {
2761 .driver = {
2762 .name = DRIVER_NAME,
2763 .owner = THIS_MODULE,
2764 .pm = &fec_pm_ops,
2765 .of_match_table = fec_dt_ids,
2766 },
2767 .id_table = fec_devtype,
2768 .probe = fec_probe,
2769 .remove = fec_drv_remove,
2770 };
2771
2772 module_platform_driver(fec_driver);
2773
2774 MODULE_ALIAS("platform:"DRIVER_NAME);
2775 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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