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[deliverable/linux.git] / drivers / net / ethernet / freescale / fec_main.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/in.h>
37 #include <linux/ip.h>
38 #include <net/ip.h>
39 #include <net/tso.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
46 #include <linux/io.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
52 #include <linux/of.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_mdio.h>
56 #include <linux/of_net.h>
57 #include <linux/regulator/consumer.h>
58 #include <linux/if_vlan.h>
59 #include <linux/pinctrl/consumer.h>
60
61 #include <asm/cacheflush.h>
62
63 #include "fec.h"
64
65 static void set_multicast_list(struct net_device *ndev);
66 static void fec_enet_itr_coal_init(struct net_device *ndev);
67
68 #define DRIVER_NAME "fec"
69
70 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
71
72 /* Pause frame feild and FIFO threshold */
73 #define FEC_ENET_FCE (1 << 5)
74 #define FEC_ENET_RSEM_V 0x84
75 #define FEC_ENET_RSFL_V 16
76 #define FEC_ENET_RAEM_V 0x8
77 #define FEC_ENET_RAFL_V 0x8
78 #define FEC_ENET_OPD_V 0xFFF0
79
80 /* Controller is ENET-MAC */
81 #define FEC_QUIRK_ENET_MAC (1 << 0)
82 /* Controller needs driver to swap frame */
83 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
84 /* Controller uses gasket */
85 #define FEC_QUIRK_USE_GASKET (1 << 2)
86 /* Controller has GBIT support */
87 #define FEC_QUIRK_HAS_GBIT (1 << 3)
88 /* Controller has extend desc buffer */
89 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
90 /* Controller has hardware checksum support */
91 #define FEC_QUIRK_HAS_CSUM (1 << 5)
92 /* Controller has hardware vlan support */
93 #define FEC_QUIRK_HAS_VLAN (1 << 6)
94 /* ENET IP errata ERR006358
95 *
96 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
97 * detected as not set during a prior frame transmission, then the
98 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
99 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
100 * frames not being transmitted until there is a 0-to-1 transition on
101 * ENET_TDAR[TDAR].
102 */
103 #define FEC_QUIRK_ERR006358 (1 << 7)
104 /* ENET IP hw AVB
105 *
106 * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support.
107 * - Two class indicators on receive with configurable priority
108 * - Two class indicators and line speed timer on transmit allowing
109 * implementation class credit based shapers externally
110 * - Additional DMA registers provisioned to allow managing up to 3
111 * independent rings
112 */
113 #define FEC_QUIRK_HAS_AVB (1 << 8)
114 /* There is a TDAR race condition for mutliQ when the software sets TDAR
115 * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
116 * This will cause the udma_tx and udma_tx_arbiter state machines to hang.
117 * The issue exist at i.MX6SX enet IP.
118 */
119 #define FEC_QUIRK_ERR007885 (1 << 9)
120
121 static struct platform_device_id fec_devtype[] = {
122 {
123 /* keep it for coldfire */
124 .name = DRIVER_NAME,
125 .driver_data = 0,
126 }, {
127 .name = "imx25-fec",
128 .driver_data = FEC_QUIRK_USE_GASKET,
129 }, {
130 .name = "imx27-fec",
131 .driver_data = 0,
132 }, {
133 .name = "imx28-fec",
134 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
135 }, {
136 .name = "imx6q-fec",
137 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
138 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
139 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
140 }, {
141 .name = "mvf600-fec",
142 .driver_data = FEC_QUIRK_ENET_MAC,
143 }, {
144 .name = "imx6sx-fec",
145 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
146 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
147 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
148 FEC_QUIRK_ERR007885,
149 }, {
150 /* sentinel */
151 }
152 };
153 MODULE_DEVICE_TABLE(platform, fec_devtype);
154
155 enum imx_fec_type {
156 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
157 IMX27_FEC, /* runs on i.mx27/35/51 */
158 IMX28_FEC,
159 IMX6Q_FEC,
160 MVF600_FEC,
161 IMX6SX_FEC,
162 };
163
164 static const struct of_device_id fec_dt_ids[] = {
165 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
166 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
167 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
168 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
169 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
170 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
171 { /* sentinel */ }
172 };
173 MODULE_DEVICE_TABLE(of, fec_dt_ids);
174
175 static unsigned char macaddr[ETH_ALEN];
176 module_param_array(macaddr, byte, NULL, 0);
177 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
178
179 #if defined(CONFIG_M5272)
180 /*
181 * Some hardware gets it MAC address out of local flash memory.
182 * if this is non-zero then assume it is the address to get MAC from.
183 */
184 #if defined(CONFIG_NETtel)
185 #define FEC_FLASHMAC 0xf0006006
186 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
187 #define FEC_FLASHMAC 0xf0006000
188 #elif defined(CONFIG_CANCam)
189 #define FEC_FLASHMAC 0xf0020000
190 #elif defined (CONFIG_M5272C3)
191 #define FEC_FLASHMAC (0xffe04000 + 4)
192 #elif defined(CONFIG_MOD5272)
193 #define FEC_FLASHMAC 0xffc0406b
194 #else
195 #define FEC_FLASHMAC 0
196 #endif
197 #endif /* CONFIG_M5272 */
198
199 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
200 */
201 #define PKT_MAXBUF_SIZE 1522
202 #define PKT_MINBUF_SIZE 64
203 #define PKT_MAXBLR_SIZE 1536
204
205 /* FEC receive acceleration */
206 #define FEC_RACC_IPDIS (1 << 1)
207 #define FEC_RACC_PRODIS (1 << 2)
208 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
209
210 /*
211 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
212 * size bits. Other FEC hardware does not, so we need to take that into
213 * account when setting it.
214 */
215 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
216 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
217 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
218 #else
219 #define OPT_FRAME_SIZE 0
220 #endif
221
222 /* FEC MII MMFR bits definition */
223 #define FEC_MMFR_ST (1 << 30)
224 #define FEC_MMFR_OP_READ (2 << 28)
225 #define FEC_MMFR_OP_WRITE (1 << 28)
226 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
227 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
228 #define FEC_MMFR_TA (2 << 16)
229 #define FEC_MMFR_DATA(v) (v & 0xffff)
230
231 #define FEC_MII_TIMEOUT 30000 /* us */
232
233 /* Transmitter timeout */
234 #define TX_TIMEOUT (2 * HZ)
235
236 #define FEC_PAUSE_FLAG_AUTONEG 0x1
237 #define FEC_PAUSE_FLAG_ENABLE 0x2
238
239 #define TSO_HEADER_SIZE 128
240 /* Max number of allowed TCP segments for software TSO */
241 #define FEC_MAX_TSO_SEGS 100
242 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
243
244 #define IS_TSO_HEADER(txq, addr) \
245 ((addr >= txq->tso_hdrs_dma) && \
246 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
247
248 static int mii_cnt;
249
250 static inline
251 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
252 struct fec_enet_private *fep,
253 int queue_id)
254 {
255 struct bufdesc *new_bd = bdp + 1;
256 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
257 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
258 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
259 struct bufdesc_ex *ex_base;
260 struct bufdesc *base;
261 int ring_size;
262
263 if (bdp >= txq->tx_bd_base) {
264 base = txq->tx_bd_base;
265 ring_size = txq->tx_ring_size;
266 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
267 } else {
268 base = rxq->rx_bd_base;
269 ring_size = rxq->rx_ring_size;
270 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
271 }
272
273 if (fep->bufdesc_ex)
274 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
275 ex_base : ex_new_bd);
276 else
277 return (new_bd >= (base + ring_size)) ?
278 base : new_bd;
279 }
280
281 static inline
282 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
283 struct fec_enet_private *fep,
284 int queue_id)
285 {
286 struct bufdesc *new_bd = bdp - 1;
287 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
288 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
289 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
290 struct bufdesc_ex *ex_base;
291 struct bufdesc *base;
292 int ring_size;
293
294 if (bdp >= txq->tx_bd_base) {
295 base = txq->tx_bd_base;
296 ring_size = txq->tx_ring_size;
297 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
298 } else {
299 base = rxq->rx_bd_base;
300 ring_size = rxq->rx_ring_size;
301 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
302 }
303
304 if (fep->bufdesc_ex)
305 return (struct bufdesc *)((ex_new_bd < ex_base) ?
306 (ex_new_bd + ring_size) : ex_new_bd);
307 else
308 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
309 }
310
311 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
312 struct fec_enet_private *fep)
313 {
314 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
315 }
316
317 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
318 struct fec_enet_priv_tx_q *txq)
319 {
320 int entries;
321
322 entries = ((const char *)txq->dirty_tx -
323 (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
324
325 return entries > 0 ? entries : entries + txq->tx_ring_size;
326 }
327
328 static void *swap_buffer(void *bufaddr, int len)
329 {
330 int i;
331 unsigned int *buf = bufaddr;
332
333 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
334 *buf = cpu_to_be32(*buf);
335
336 return bufaddr;
337 }
338
339 static void fec_dump(struct net_device *ndev)
340 {
341 struct fec_enet_private *fep = netdev_priv(ndev);
342 struct bufdesc *bdp;
343 struct fec_enet_priv_tx_q *txq;
344 int index = 0;
345
346 netdev_info(ndev, "TX ring dump\n");
347 pr_info("Nr SC addr len SKB\n");
348
349 txq = fep->tx_queue[0];
350 bdp = txq->tx_bd_base;
351
352 do {
353 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n",
354 index,
355 bdp == txq->cur_tx ? 'S' : ' ',
356 bdp == txq->dirty_tx ? 'H' : ' ',
357 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen,
358 txq->tx_skbuff[index]);
359 bdp = fec_enet_get_nextdesc(bdp, fep, 0);
360 index++;
361 } while (bdp != txq->tx_bd_base);
362 }
363
364 static inline bool is_ipv4_pkt(struct sk_buff *skb)
365 {
366 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
367 }
368
369 static int
370 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
371 {
372 /* Only run for packets requiring a checksum. */
373 if (skb->ip_summed != CHECKSUM_PARTIAL)
374 return 0;
375
376 if (unlikely(skb_cow_head(skb, 0)))
377 return -1;
378
379 if (is_ipv4_pkt(skb))
380 ip_hdr(skb)->check = 0;
381 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
382
383 return 0;
384 }
385
386 static int
387 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
388 struct sk_buff *skb,
389 struct net_device *ndev)
390 {
391 struct fec_enet_private *fep = netdev_priv(ndev);
392 const struct platform_device_id *id_entry =
393 platform_get_device_id(fep->pdev);
394 struct bufdesc *bdp = txq->cur_tx;
395 struct bufdesc_ex *ebdp;
396 int nr_frags = skb_shinfo(skb)->nr_frags;
397 unsigned short queue = skb_get_queue_mapping(skb);
398 int frag, frag_len;
399 unsigned short status;
400 unsigned int estatus = 0;
401 skb_frag_t *this_frag;
402 unsigned int index;
403 void *bufaddr;
404 dma_addr_t addr;
405 int i;
406
407 for (frag = 0; frag < nr_frags; frag++) {
408 this_frag = &skb_shinfo(skb)->frags[frag];
409 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
410 ebdp = (struct bufdesc_ex *)bdp;
411
412 status = bdp->cbd_sc;
413 status &= ~BD_ENET_TX_STATS;
414 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
415 frag_len = skb_shinfo(skb)->frags[frag].size;
416
417 /* Handle the last BD specially */
418 if (frag == nr_frags - 1) {
419 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
420 if (fep->bufdesc_ex) {
421 estatus |= BD_ENET_TX_INT;
422 if (unlikely(skb_shinfo(skb)->tx_flags &
423 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
424 estatus |= BD_ENET_TX_TS;
425 }
426 }
427
428 if (fep->bufdesc_ex) {
429 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB)
430 estatus |= FEC_TX_BD_FTYPE(queue);
431 if (skb->ip_summed == CHECKSUM_PARTIAL)
432 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
433 ebdp->cbd_bdu = 0;
434 ebdp->cbd_esc = estatus;
435 }
436
437 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
438
439 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
440 if (((unsigned long) bufaddr) & fep->tx_align ||
441 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
442 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
443 bufaddr = txq->tx_bounce[index];
444
445 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
446 swap_buffer(bufaddr, frag_len);
447 }
448
449 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
450 DMA_TO_DEVICE);
451 if (dma_mapping_error(&fep->pdev->dev, addr)) {
452 dev_kfree_skb_any(skb);
453 if (net_ratelimit())
454 netdev_err(ndev, "Tx DMA memory map failed\n");
455 goto dma_mapping_error;
456 }
457
458 bdp->cbd_bufaddr = addr;
459 bdp->cbd_datlen = frag_len;
460 bdp->cbd_sc = status;
461 }
462
463 txq->cur_tx = bdp;
464
465 return 0;
466
467 dma_mapping_error:
468 bdp = txq->cur_tx;
469 for (i = 0; i < frag; i++) {
470 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
471 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
472 bdp->cbd_datlen, DMA_TO_DEVICE);
473 }
474 return NETDEV_TX_OK;
475 }
476
477 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
478 struct sk_buff *skb, struct net_device *ndev)
479 {
480 struct fec_enet_private *fep = netdev_priv(ndev);
481 const struct platform_device_id *id_entry =
482 platform_get_device_id(fep->pdev);
483 int nr_frags = skb_shinfo(skb)->nr_frags;
484 struct bufdesc *bdp, *last_bdp;
485 void *bufaddr;
486 dma_addr_t addr;
487 unsigned short status;
488 unsigned short buflen;
489 unsigned short queue;
490 unsigned int estatus = 0;
491 unsigned int index;
492 int entries_free;
493 int ret;
494
495 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
496 if (entries_free < MAX_SKB_FRAGS + 1) {
497 dev_kfree_skb_any(skb);
498 if (net_ratelimit())
499 netdev_err(ndev, "NOT enough BD for SG!\n");
500 return NETDEV_TX_OK;
501 }
502
503 /* Protocol checksum off-load for TCP and UDP. */
504 if (fec_enet_clear_csum(skb, ndev)) {
505 dev_kfree_skb_any(skb);
506 return NETDEV_TX_OK;
507 }
508
509 /* Fill in a Tx ring entry */
510 bdp = txq->cur_tx;
511 status = bdp->cbd_sc;
512 status &= ~BD_ENET_TX_STATS;
513
514 /* Set buffer length and buffer pointer */
515 bufaddr = skb->data;
516 buflen = skb_headlen(skb);
517
518 queue = skb_get_queue_mapping(skb);
519 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
520 if (((unsigned long) bufaddr) & fep->tx_align ||
521 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
522 memcpy(txq->tx_bounce[index], skb->data, buflen);
523 bufaddr = txq->tx_bounce[index];
524
525 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
526 swap_buffer(bufaddr, buflen);
527 }
528
529 /* Push the data cache so the CPM does not get stale memory data. */
530 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
531 if (dma_mapping_error(&fep->pdev->dev, addr)) {
532 dev_kfree_skb_any(skb);
533 if (net_ratelimit())
534 netdev_err(ndev, "Tx DMA memory map failed\n");
535 return NETDEV_TX_OK;
536 }
537
538 if (nr_frags) {
539 ret = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
540 if (ret)
541 return ret;
542 } else {
543 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
544 if (fep->bufdesc_ex) {
545 estatus = BD_ENET_TX_INT;
546 if (unlikely(skb_shinfo(skb)->tx_flags &
547 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
548 estatus |= BD_ENET_TX_TS;
549 }
550 }
551
552 if (fep->bufdesc_ex) {
553
554 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
555
556 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
557 fep->hwts_tx_en))
558 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
559
560 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB)
561 estatus |= FEC_TX_BD_FTYPE(queue);
562
563 if (skb->ip_summed == CHECKSUM_PARTIAL)
564 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
565
566 ebdp->cbd_bdu = 0;
567 ebdp->cbd_esc = estatus;
568 }
569
570 last_bdp = txq->cur_tx;
571 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
572 /* Save skb pointer */
573 txq->tx_skbuff[index] = skb;
574
575 bdp->cbd_datlen = buflen;
576 bdp->cbd_bufaddr = addr;
577
578 /* Send it on its way. Tell FEC it's ready, interrupt when done,
579 * it's the last BD of the frame, and to put the CRC on the end.
580 */
581 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
582 bdp->cbd_sc = status;
583
584 /* If this was the last BD in the ring, start at the beginning again. */
585 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
586
587 skb_tx_timestamp(skb);
588
589 txq->cur_tx = bdp;
590
591 /* Trigger transmission start */
592 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
593
594 return 0;
595 }
596
597 static int
598 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
599 struct net_device *ndev,
600 struct bufdesc *bdp, int index, char *data,
601 int size, bool last_tcp, bool is_last)
602 {
603 struct fec_enet_private *fep = netdev_priv(ndev);
604 const struct platform_device_id *id_entry =
605 platform_get_device_id(fep->pdev);
606 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
607 unsigned short queue = skb_get_queue_mapping(skb);
608 unsigned short status;
609 unsigned int estatus = 0;
610 dma_addr_t addr;
611
612 status = bdp->cbd_sc;
613 status &= ~BD_ENET_TX_STATS;
614
615 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
616
617 if (((unsigned long) data) & fep->tx_align ||
618 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
619 memcpy(txq->tx_bounce[index], data, size);
620 data = txq->tx_bounce[index];
621
622 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
623 swap_buffer(data, size);
624 }
625
626 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
627 if (dma_mapping_error(&fep->pdev->dev, addr)) {
628 dev_kfree_skb_any(skb);
629 if (net_ratelimit())
630 netdev_err(ndev, "Tx DMA memory map failed\n");
631 return NETDEV_TX_BUSY;
632 }
633
634 bdp->cbd_datlen = size;
635 bdp->cbd_bufaddr = addr;
636
637 if (fep->bufdesc_ex) {
638 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB)
639 estatus |= FEC_TX_BD_FTYPE(queue);
640 if (skb->ip_summed == CHECKSUM_PARTIAL)
641 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
642 ebdp->cbd_bdu = 0;
643 ebdp->cbd_esc = estatus;
644 }
645
646 /* Handle the last BD specially */
647 if (last_tcp)
648 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
649 if (is_last) {
650 status |= BD_ENET_TX_INTR;
651 if (fep->bufdesc_ex)
652 ebdp->cbd_esc |= BD_ENET_TX_INT;
653 }
654
655 bdp->cbd_sc = status;
656
657 return 0;
658 }
659
660 static int
661 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
662 struct sk_buff *skb, struct net_device *ndev,
663 struct bufdesc *bdp, int index)
664 {
665 struct fec_enet_private *fep = netdev_priv(ndev);
666 const struct platform_device_id *id_entry =
667 platform_get_device_id(fep->pdev);
668 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
669 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
670 unsigned short queue = skb_get_queue_mapping(skb);
671 void *bufaddr;
672 unsigned long dmabuf;
673 unsigned short status;
674 unsigned int estatus = 0;
675
676 status = bdp->cbd_sc;
677 status &= ~BD_ENET_TX_STATS;
678 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
679
680 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
681 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
682 if (((unsigned long)bufaddr) & fep->tx_align ||
683 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
684 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
685 bufaddr = txq->tx_bounce[index];
686
687 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
688 swap_buffer(bufaddr, hdr_len);
689
690 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
691 hdr_len, DMA_TO_DEVICE);
692 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
693 dev_kfree_skb_any(skb);
694 if (net_ratelimit())
695 netdev_err(ndev, "Tx DMA memory map failed\n");
696 return NETDEV_TX_BUSY;
697 }
698 }
699
700 bdp->cbd_bufaddr = dmabuf;
701 bdp->cbd_datlen = hdr_len;
702
703 if (fep->bufdesc_ex) {
704 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB)
705 estatus |= FEC_TX_BD_FTYPE(queue);
706 if (skb->ip_summed == CHECKSUM_PARTIAL)
707 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
708 ebdp->cbd_bdu = 0;
709 ebdp->cbd_esc = estatus;
710 }
711
712 bdp->cbd_sc = status;
713
714 return 0;
715 }
716
717 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
718 struct sk_buff *skb,
719 struct net_device *ndev)
720 {
721 struct fec_enet_private *fep = netdev_priv(ndev);
722 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
723 int total_len, data_left;
724 struct bufdesc *bdp = txq->cur_tx;
725 unsigned short queue = skb_get_queue_mapping(skb);
726 struct tso_t tso;
727 unsigned int index = 0;
728 int ret;
729 const struct platform_device_id *id_entry =
730 platform_get_device_id(fep->pdev);
731
732 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
733 dev_kfree_skb_any(skb);
734 if (net_ratelimit())
735 netdev_err(ndev, "NOT enough BD for TSO!\n");
736 return NETDEV_TX_OK;
737 }
738
739 /* Protocol checksum off-load for TCP and UDP. */
740 if (fec_enet_clear_csum(skb, ndev)) {
741 dev_kfree_skb_any(skb);
742 return NETDEV_TX_OK;
743 }
744
745 /* Initialize the TSO handler, and prepare the first payload */
746 tso_start(skb, &tso);
747
748 total_len = skb->len - hdr_len;
749 while (total_len > 0) {
750 char *hdr;
751
752 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
753 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
754 total_len -= data_left;
755
756 /* prepare packet headers: MAC + IP + TCP */
757 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
758 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
759 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
760 if (ret)
761 goto err_release;
762
763 while (data_left > 0) {
764 int size;
765
766 size = min_t(int, tso.size, data_left);
767 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
768 index = fec_enet_get_bd_index(txq->tx_bd_base,
769 bdp, fep);
770 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
771 bdp, index,
772 tso.data, size,
773 size == data_left,
774 total_len == 0);
775 if (ret)
776 goto err_release;
777
778 data_left -= size;
779 tso_build_data(skb, &tso, size);
780 }
781
782 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
783 }
784
785 /* Save skb pointer */
786 txq->tx_skbuff[index] = skb;
787
788 skb_tx_timestamp(skb);
789 txq->cur_tx = bdp;
790
791 /* Trigger transmission start */
792 if (!(id_entry->driver_data & FEC_QUIRK_ERR007885) ||
793 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
794 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
795 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
796 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
797 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
798
799 return 0;
800
801 err_release:
802 /* TODO: Release all used data descriptors for TSO */
803 return ret;
804 }
805
806 static netdev_tx_t
807 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
808 {
809 struct fec_enet_private *fep = netdev_priv(ndev);
810 int entries_free;
811 unsigned short queue;
812 struct fec_enet_priv_tx_q *txq;
813 struct netdev_queue *nq;
814 int ret;
815
816 queue = skb_get_queue_mapping(skb);
817 txq = fep->tx_queue[queue];
818 nq = netdev_get_tx_queue(ndev, queue);
819
820 if (skb_is_gso(skb))
821 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
822 else
823 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
824 if (ret)
825 return ret;
826
827 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
828 if (entries_free <= txq->tx_stop_threshold)
829 netif_tx_stop_queue(nq);
830
831 return NETDEV_TX_OK;
832 }
833
834 /* Init RX & TX buffer descriptors
835 */
836 static void fec_enet_bd_init(struct net_device *dev)
837 {
838 struct fec_enet_private *fep = netdev_priv(dev);
839 struct fec_enet_priv_tx_q *txq;
840 struct fec_enet_priv_rx_q *rxq;
841 struct bufdesc *bdp;
842 unsigned int i;
843 unsigned int q;
844
845 for (q = 0; q < fep->num_rx_queues; q++) {
846 /* Initialize the receive buffer descriptors. */
847 rxq = fep->rx_queue[q];
848 bdp = rxq->rx_bd_base;
849
850 for (i = 0; i < rxq->rx_ring_size; i++) {
851
852 /* Initialize the BD for every fragment in the page. */
853 if (bdp->cbd_bufaddr)
854 bdp->cbd_sc = BD_ENET_RX_EMPTY;
855 else
856 bdp->cbd_sc = 0;
857 bdp = fec_enet_get_nextdesc(bdp, fep, q);
858 }
859
860 /* Set the last buffer to wrap */
861 bdp = fec_enet_get_prevdesc(bdp, fep, q);
862 bdp->cbd_sc |= BD_SC_WRAP;
863
864 rxq->cur_rx = rxq->rx_bd_base;
865 }
866
867 for (q = 0; q < fep->num_tx_queues; q++) {
868 /* ...and the same for transmit */
869 txq = fep->tx_queue[q];
870 bdp = txq->tx_bd_base;
871 txq->cur_tx = bdp;
872
873 for (i = 0; i < txq->tx_ring_size; i++) {
874 /* Initialize the BD for every fragment in the page. */
875 bdp->cbd_sc = 0;
876 if (txq->tx_skbuff[i]) {
877 dev_kfree_skb_any(txq->tx_skbuff[i]);
878 txq->tx_skbuff[i] = NULL;
879 }
880 bdp->cbd_bufaddr = 0;
881 bdp = fec_enet_get_nextdesc(bdp, fep, q);
882 }
883
884 /* Set the last buffer to wrap */
885 bdp = fec_enet_get_prevdesc(bdp, fep, q);
886 bdp->cbd_sc |= BD_SC_WRAP;
887 txq->dirty_tx = bdp;
888 }
889 }
890
891 static void fec_enet_active_rxring(struct net_device *ndev)
892 {
893 struct fec_enet_private *fep = netdev_priv(ndev);
894 int i;
895
896 for (i = 0; i < fep->num_rx_queues; i++)
897 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
898 }
899
900 static void fec_enet_enable_ring(struct net_device *ndev)
901 {
902 struct fec_enet_private *fep = netdev_priv(ndev);
903 struct fec_enet_priv_tx_q *txq;
904 struct fec_enet_priv_rx_q *rxq;
905 int i;
906
907 for (i = 0; i < fep->num_rx_queues; i++) {
908 rxq = fep->rx_queue[i];
909 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
910
911 /* enable DMA1/2 */
912 if (i)
913 writel(RCMR_MATCHEN | RCMR_CMP(i),
914 fep->hwp + FEC_RCMR(i));
915 }
916
917 for (i = 0; i < fep->num_tx_queues; i++) {
918 txq = fep->tx_queue[i];
919 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
920
921 /* enable DMA1/2 */
922 if (i)
923 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
924 fep->hwp + FEC_DMA_CFG(i));
925 }
926 }
927
928 static void fec_enet_reset_skb(struct net_device *ndev)
929 {
930 struct fec_enet_private *fep = netdev_priv(ndev);
931 struct fec_enet_priv_tx_q *txq;
932 int i, j;
933
934 for (i = 0; i < fep->num_tx_queues; i++) {
935 txq = fep->tx_queue[i];
936
937 for (j = 0; j < txq->tx_ring_size; j++) {
938 if (txq->tx_skbuff[j]) {
939 dev_kfree_skb_any(txq->tx_skbuff[j]);
940 txq->tx_skbuff[j] = NULL;
941 }
942 }
943 }
944 }
945
946 /*
947 * This function is called to start or restart the FEC during a link
948 * change, transmit timeout, or to reconfigure the FEC. The network
949 * packet processing for this device must be stopped before this call.
950 */
951 static void
952 fec_restart(struct net_device *ndev)
953 {
954 struct fec_enet_private *fep = netdev_priv(ndev);
955 const struct platform_device_id *id_entry =
956 platform_get_device_id(fep->pdev);
957 u32 val;
958 u32 temp_mac[2];
959 u32 rcntl = OPT_FRAME_SIZE | 0x04;
960 u32 ecntl = 0x2; /* ETHEREN */
961
962 /* Whack a reset. We should wait for this.
963 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
964 * instead of reset MAC itself.
965 */
966 if (id_entry && id_entry->driver_data & FEC_QUIRK_HAS_AVB) {
967 writel(0, fep->hwp + FEC_ECNTRL);
968 } else {
969 writel(1, fep->hwp + FEC_ECNTRL);
970 udelay(10);
971 }
972
973 /*
974 * enet-mac reset will reset mac address registers too,
975 * so need to reconfigure it.
976 */
977 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
978 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
979 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
980 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
981 }
982
983 /* Clear any outstanding interrupt. */
984 writel(0xffc00000, fep->hwp + FEC_IEVENT);
985
986 /* Set maximum receive buffer size. */
987 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
988
989 fec_enet_bd_init(ndev);
990
991 fec_enet_enable_ring(ndev);
992
993 /* Reset tx SKB buffers. */
994 fec_enet_reset_skb(ndev);
995
996 /* Enable MII mode */
997 if (fep->full_duplex == DUPLEX_FULL) {
998 /* FD enable */
999 writel(0x04, fep->hwp + FEC_X_CNTRL);
1000 } else {
1001 /* No Rcv on Xmit */
1002 rcntl |= 0x02;
1003 writel(0x0, fep->hwp + FEC_X_CNTRL);
1004 }
1005
1006 /* Set MII speed */
1007 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1008
1009 #if !defined(CONFIG_M5272)
1010 /* set RX checksum */
1011 val = readl(fep->hwp + FEC_RACC);
1012 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
1013 val |= FEC_RACC_OPTIONS;
1014 else
1015 val &= ~FEC_RACC_OPTIONS;
1016 writel(val, fep->hwp + FEC_RACC);
1017 #endif
1018
1019 /*
1020 * The phy interface and speed need to get configured
1021 * differently on enet-mac.
1022 */
1023 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
1024 /* Enable flow control and length check */
1025 rcntl |= 0x40000000 | 0x00000020;
1026
1027 /* RGMII, RMII or MII */
1028 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
1029 rcntl |= (1 << 6);
1030 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1031 rcntl |= (1 << 8);
1032 else
1033 rcntl &= ~(1 << 8);
1034
1035 /* 1G, 100M or 10M */
1036 if (fep->phy_dev) {
1037 if (fep->phy_dev->speed == SPEED_1000)
1038 ecntl |= (1 << 5);
1039 else if (fep->phy_dev->speed == SPEED_100)
1040 rcntl &= ~(1 << 9);
1041 else
1042 rcntl |= (1 << 9);
1043 }
1044 } else {
1045 #ifdef FEC_MIIGSK_ENR
1046 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
1047 u32 cfgr;
1048 /* disable the gasket and wait */
1049 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1050 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1051 udelay(1);
1052
1053 /*
1054 * configure the gasket:
1055 * RMII, 50 MHz, no loopback, no echo
1056 * MII, 25 MHz, no loopback, no echo
1057 */
1058 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1059 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1060 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
1061 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1062 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1063
1064 /* re-enable the gasket */
1065 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1066 }
1067 #endif
1068 }
1069
1070 #if !defined(CONFIG_M5272)
1071 /* enable pause frame*/
1072 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1073 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1074 fep->phy_dev && fep->phy_dev->pause)) {
1075 rcntl |= FEC_ENET_FCE;
1076
1077 /* set FIFO threshold parameter to reduce overrun */
1078 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1079 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1080 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1081 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1082
1083 /* OPD */
1084 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1085 } else {
1086 rcntl &= ~FEC_ENET_FCE;
1087 }
1088 #endif /* !defined(CONFIG_M5272) */
1089
1090 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1091
1092 /* Setup multicast filter. */
1093 set_multicast_list(ndev);
1094 #ifndef CONFIG_M5272
1095 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1096 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1097 #endif
1098
1099 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
1100 /* enable ENET endian swap */
1101 ecntl |= (1 << 8);
1102 /* enable ENET store and forward mode */
1103 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1104 }
1105
1106 if (fep->bufdesc_ex)
1107 ecntl |= (1 << 4);
1108
1109 #ifndef CONFIG_M5272
1110 /* Enable the MIB statistic event counters */
1111 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1112 #endif
1113
1114 /* And last, enable the transmit and receive processing */
1115 writel(ecntl, fep->hwp + FEC_ECNTRL);
1116 fec_enet_active_rxring(ndev);
1117
1118 if (fep->bufdesc_ex)
1119 fec_ptp_start_cyclecounter(ndev);
1120
1121 /* Enable interrupts we wish to service */
1122 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1123
1124 /* Init the interrupt coalescing */
1125 fec_enet_itr_coal_init(ndev);
1126
1127 }
1128
1129 static void
1130 fec_stop(struct net_device *ndev)
1131 {
1132 struct fec_enet_private *fep = netdev_priv(ndev);
1133 const struct platform_device_id *id_entry =
1134 platform_get_device_id(fep->pdev);
1135 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1136
1137 /* We cannot expect a graceful transmit stop without link !!! */
1138 if (fep->link) {
1139 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1140 udelay(10);
1141 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1142 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1143 }
1144
1145 /* Whack a reset. We should wait for this.
1146 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1147 * instead of reset MAC itself.
1148 */
1149 if (id_entry && id_entry->driver_data & FEC_QUIRK_HAS_AVB) {
1150 writel(0, fep->hwp + FEC_ECNTRL);
1151 } else {
1152 writel(1, fep->hwp + FEC_ECNTRL);
1153 udelay(10);
1154 }
1155 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1156 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1157
1158 /* We have to keep ENET enabled to have MII interrupt stay working */
1159 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
1160 writel(2, fep->hwp + FEC_ECNTRL);
1161 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1162 }
1163 }
1164
1165
1166 static void
1167 fec_timeout(struct net_device *ndev)
1168 {
1169 struct fec_enet_private *fep = netdev_priv(ndev);
1170
1171 fec_dump(ndev);
1172
1173 ndev->stats.tx_errors++;
1174
1175 schedule_work(&fep->tx_timeout_work);
1176 }
1177
1178 static void fec_enet_timeout_work(struct work_struct *work)
1179 {
1180 struct fec_enet_private *fep =
1181 container_of(work, struct fec_enet_private, tx_timeout_work);
1182 struct net_device *ndev = fep->netdev;
1183
1184 rtnl_lock();
1185 if (netif_device_present(ndev) || netif_running(ndev)) {
1186 napi_disable(&fep->napi);
1187 netif_tx_lock_bh(ndev);
1188 fec_restart(ndev);
1189 netif_wake_queue(ndev);
1190 netif_tx_unlock_bh(ndev);
1191 napi_enable(&fep->napi);
1192 }
1193 rtnl_unlock();
1194 }
1195
1196 static void
1197 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1198 struct skb_shared_hwtstamps *hwtstamps)
1199 {
1200 unsigned long flags;
1201 u64 ns;
1202
1203 spin_lock_irqsave(&fep->tmreg_lock, flags);
1204 ns = timecounter_cyc2time(&fep->tc, ts);
1205 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1206
1207 memset(hwtstamps, 0, sizeof(*hwtstamps));
1208 hwtstamps->hwtstamp = ns_to_ktime(ns);
1209 }
1210
1211 static void
1212 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1213 {
1214 struct fec_enet_private *fep;
1215 struct bufdesc *bdp;
1216 unsigned short status;
1217 struct sk_buff *skb;
1218 struct fec_enet_priv_tx_q *txq;
1219 struct netdev_queue *nq;
1220 int index = 0;
1221 int entries_free;
1222
1223 fep = netdev_priv(ndev);
1224
1225 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1226
1227 txq = fep->tx_queue[queue_id];
1228 /* get next bdp of dirty_tx */
1229 nq = netdev_get_tx_queue(ndev, queue_id);
1230 bdp = txq->dirty_tx;
1231
1232 /* get next bdp of dirty_tx */
1233 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1234
1235 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
1236
1237 /* current queue is empty */
1238 if (bdp == txq->cur_tx)
1239 break;
1240
1241 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
1242
1243 skb = txq->tx_skbuff[index];
1244 txq->tx_skbuff[index] = NULL;
1245 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr))
1246 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1247 bdp->cbd_datlen, DMA_TO_DEVICE);
1248 bdp->cbd_bufaddr = 0;
1249 if (!skb) {
1250 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1251 continue;
1252 }
1253
1254 /* Check for errors. */
1255 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1256 BD_ENET_TX_RL | BD_ENET_TX_UN |
1257 BD_ENET_TX_CSL)) {
1258 ndev->stats.tx_errors++;
1259 if (status & BD_ENET_TX_HB) /* No heartbeat */
1260 ndev->stats.tx_heartbeat_errors++;
1261 if (status & BD_ENET_TX_LC) /* Late collision */
1262 ndev->stats.tx_window_errors++;
1263 if (status & BD_ENET_TX_RL) /* Retrans limit */
1264 ndev->stats.tx_aborted_errors++;
1265 if (status & BD_ENET_TX_UN) /* Underrun */
1266 ndev->stats.tx_fifo_errors++;
1267 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1268 ndev->stats.tx_carrier_errors++;
1269 } else {
1270 ndev->stats.tx_packets++;
1271 ndev->stats.tx_bytes += skb->len;
1272 }
1273
1274 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1275 fep->bufdesc_ex) {
1276 struct skb_shared_hwtstamps shhwtstamps;
1277 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1278
1279 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps);
1280 skb_tstamp_tx(skb, &shhwtstamps);
1281 }
1282
1283 /* Deferred means some collisions occurred during transmit,
1284 * but we eventually sent the packet OK.
1285 */
1286 if (status & BD_ENET_TX_DEF)
1287 ndev->stats.collisions++;
1288
1289 /* Free the sk buffer associated with this last transmit */
1290 dev_kfree_skb_any(skb);
1291
1292 txq->dirty_tx = bdp;
1293
1294 /* Update pointer to next buffer descriptor to be transmitted */
1295 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1296
1297 /* Since we have freed up a buffer, the ring is no longer full
1298 */
1299 if (netif_queue_stopped(ndev)) {
1300 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
1301 if (entries_free >= txq->tx_wake_threshold)
1302 netif_tx_wake_queue(nq);
1303 }
1304 }
1305
1306 /* ERR006538: Keep the transmitter going */
1307 if (bdp != txq->cur_tx &&
1308 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
1309 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
1310 }
1311
1312 static void
1313 fec_enet_tx(struct net_device *ndev)
1314 {
1315 struct fec_enet_private *fep = netdev_priv(ndev);
1316 u16 queue_id;
1317 /* First process class A queue, then Class B and Best Effort queue */
1318 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1319 clear_bit(queue_id, &fep->work_tx);
1320 fec_enet_tx_queue(ndev, queue_id);
1321 }
1322 return;
1323 }
1324
1325 /* During a receive, the cur_rx points to the current incoming buffer.
1326 * When we update through the ring, if the next incoming buffer has
1327 * not been given to the system, we just set the empty indicator,
1328 * effectively tossing the packet.
1329 */
1330 static int
1331 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1332 {
1333 struct fec_enet_private *fep = netdev_priv(ndev);
1334 const struct platform_device_id *id_entry =
1335 platform_get_device_id(fep->pdev);
1336 struct fec_enet_priv_rx_q *rxq;
1337 struct bufdesc *bdp;
1338 unsigned short status;
1339 struct sk_buff *skb;
1340 ushort pkt_len;
1341 __u8 *data;
1342 int pkt_received = 0;
1343 struct bufdesc_ex *ebdp = NULL;
1344 bool vlan_packet_rcvd = false;
1345 u16 vlan_tag;
1346 int index = 0;
1347
1348 #ifdef CONFIG_M532x
1349 flush_cache_all();
1350 #endif
1351 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1352 rxq = fep->rx_queue[queue_id];
1353
1354 /* First, grab all of the stats for the incoming packet.
1355 * These get messed up if we get called due to a busy condition.
1356 */
1357 bdp = rxq->cur_rx;
1358
1359 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1360
1361 if (pkt_received >= budget)
1362 break;
1363 pkt_received++;
1364
1365 /* Since we have allocated space to hold a complete frame,
1366 * the last indicator should be set.
1367 */
1368 if ((status & BD_ENET_RX_LAST) == 0)
1369 netdev_err(ndev, "rcv is not +last\n");
1370
1371
1372 /* Check for errors. */
1373 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1374 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
1375 ndev->stats.rx_errors++;
1376 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1377 /* Frame too long or too short. */
1378 ndev->stats.rx_length_errors++;
1379 }
1380 if (status & BD_ENET_RX_NO) /* Frame alignment */
1381 ndev->stats.rx_frame_errors++;
1382 if (status & BD_ENET_RX_CR) /* CRC Error */
1383 ndev->stats.rx_crc_errors++;
1384 if (status & BD_ENET_RX_OV) /* FIFO overrun */
1385 ndev->stats.rx_fifo_errors++;
1386 }
1387
1388 /* Report late collisions as a frame error.
1389 * On this error, the BD is closed, but we don't know what we
1390 * have in the buffer. So, just drop this frame on the floor.
1391 */
1392 if (status & BD_ENET_RX_CL) {
1393 ndev->stats.rx_errors++;
1394 ndev->stats.rx_frame_errors++;
1395 goto rx_processing_done;
1396 }
1397
1398 /* Process the incoming frame. */
1399 ndev->stats.rx_packets++;
1400 pkt_len = bdp->cbd_datlen;
1401 ndev->stats.rx_bytes += pkt_len;
1402
1403 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
1404 data = rxq->rx_skbuff[index]->data;
1405 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1406 FEC_ENET_RX_FRSIZE - fep->rx_align,
1407 DMA_FROM_DEVICE);
1408
1409 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
1410 swap_buffer(data, pkt_len);
1411
1412 /* Extract the enhanced buffer descriptor */
1413 ebdp = NULL;
1414 if (fep->bufdesc_ex)
1415 ebdp = (struct bufdesc_ex *)bdp;
1416
1417 /* If this is a VLAN packet remove the VLAN Tag */
1418 vlan_packet_rcvd = false;
1419 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1420 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
1421 /* Push and remove the vlan tag */
1422 struct vlan_hdr *vlan_header =
1423 (struct vlan_hdr *) (data + ETH_HLEN);
1424 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1425 pkt_len -= VLAN_HLEN;
1426
1427 vlan_packet_rcvd = true;
1428 }
1429
1430 /* This does 16 byte alignment, exactly what we need.
1431 * The packet length includes FCS, but we don't want to
1432 * include that when passing upstream as it messes up
1433 * bridging applications.
1434 */
1435 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
1436
1437 if (unlikely(!skb)) {
1438 ndev->stats.rx_dropped++;
1439 } else {
1440 int payload_offset = (2 * ETH_ALEN);
1441 skb_reserve(skb, NET_IP_ALIGN);
1442 skb_put(skb, pkt_len - 4); /* Make room */
1443
1444 /* Extract the frame data without the VLAN header. */
1445 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
1446 if (vlan_packet_rcvd)
1447 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
1448 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
1449 data + payload_offset,
1450 pkt_len - 4 - (2 * ETH_ALEN));
1451
1452 skb->protocol = eth_type_trans(skb, ndev);
1453
1454 /* Get receive timestamp from the skb */
1455 if (fep->hwts_rx_en && fep->bufdesc_ex)
1456 fec_enet_hwtstamp(fep, ebdp->ts,
1457 skb_hwtstamps(skb));
1458
1459 if (fep->bufdesc_ex &&
1460 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1461 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1462 /* don't check it */
1463 skb->ip_summed = CHECKSUM_UNNECESSARY;
1464 } else {
1465 skb_checksum_none_assert(skb);
1466 }
1467 }
1468
1469 /* Handle received VLAN packets */
1470 if (vlan_packet_rcvd)
1471 __vlan_hwaccel_put_tag(skb,
1472 htons(ETH_P_8021Q),
1473 vlan_tag);
1474
1475 napi_gro_receive(&fep->napi, skb);
1476 }
1477
1478 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1479 FEC_ENET_RX_FRSIZE - fep->rx_align,
1480 DMA_FROM_DEVICE);
1481 rx_processing_done:
1482 /* Clear the status flags for this buffer */
1483 status &= ~BD_ENET_RX_STATS;
1484
1485 /* Mark the buffer empty */
1486 status |= BD_ENET_RX_EMPTY;
1487 bdp->cbd_sc = status;
1488
1489 if (fep->bufdesc_ex) {
1490 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1491
1492 ebdp->cbd_esc = BD_ENET_RX_INT;
1493 ebdp->cbd_prot = 0;
1494 ebdp->cbd_bdu = 0;
1495 }
1496
1497 /* Update BD pointer to next entry */
1498 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1499
1500 /* Doing this here will keep the FEC running while we process
1501 * incoming frames. On a heavily loaded network, we should be
1502 * able to keep up at the expense of system resources.
1503 */
1504 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
1505 }
1506 rxq->cur_rx = bdp;
1507 return pkt_received;
1508 }
1509
1510 static int
1511 fec_enet_rx(struct net_device *ndev, int budget)
1512 {
1513 int pkt_received = 0;
1514 u16 queue_id;
1515 struct fec_enet_private *fep = netdev_priv(ndev);
1516
1517 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1518 clear_bit(queue_id, &fep->work_rx);
1519 pkt_received += fec_enet_rx_queue(ndev,
1520 budget - pkt_received, queue_id);
1521 }
1522 return pkt_received;
1523 }
1524
1525 static bool
1526 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1527 {
1528 if (int_events == 0)
1529 return false;
1530
1531 if (int_events & FEC_ENET_RXF)
1532 fep->work_rx |= (1 << 2);
1533 if (int_events & FEC_ENET_RXF_1)
1534 fep->work_rx |= (1 << 0);
1535 if (int_events & FEC_ENET_RXF_2)
1536 fep->work_rx |= (1 << 1);
1537
1538 if (int_events & FEC_ENET_TXF)
1539 fep->work_tx |= (1 << 2);
1540 if (int_events & FEC_ENET_TXF_1)
1541 fep->work_tx |= (1 << 0);
1542 if (int_events & FEC_ENET_TXF_2)
1543 fep->work_tx |= (1 << 1);
1544
1545 return true;
1546 }
1547
1548 static irqreturn_t
1549 fec_enet_interrupt(int irq, void *dev_id)
1550 {
1551 struct net_device *ndev = dev_id;
1552 struct fec_enet_private *fep = netdev_priv(ndev);
1553 const unsigned napi_mask = FEC_ENET_RXF | FEC_ENET_TXF;
1554 uint int_events;
1555 irqreturn_t ret = IRQ_NONE;
1556
1557 int_events = readl(fep->hwp + FEC_IEVENT);
1558 writel(int_events & ~napi_mask, fep->hwp + FEC_IEVENT);
1559 fec_enet_collect_events(fep, int_events);
1560
1561 if (int_events & napi_mask) {
1562 ret = IRQ_HANDLED;
1563
1564 /* Disable the NAPI interrupts */
1565 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1566 napi_schedule(&fep->napi);
1567 }
1568
1569 if (int_events & FEC_ENET_MII) {
1570 ret = IRQ_HANDLED;
1571 complete(&fep->mdio_done);
1572 }
1573
1574 return ret;
1575 }
1576
1577 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1578 {
1579 struct net_device *ndev = napi->dev;
1580 struct fec_enet_private *fep = netdev_priv(ndev);
1581 int pkts;
1582
1583 /*
1584 * Clear any pending transmit or receive interrupts before
1585 * processing the rings to avoid racing with the hardware.
1586 */
1587 writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT);
1588
1589 pkts = fec_enet_rx(ndev, budget);
1590
1591 fec_enet_tx(ndev);
1592
1593 if (pkts < budget) {
1594 napi_complete(napi);
1595 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1596 }
1597 return pkts;
1598 }
1599
1600 /* ------------------------------------------------------------------------- */
1601 static void fec_get_mac(struct net_device *ndev)
1602 {
1603 struct fec_enet_private *fep = netdev_priv(ndev);
1604 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1605 unsigned char *iap, tmpaddr[ETH_ALEN];
1606
1607 /*
1608 * try to get mac address in following order:
1609 *
1610 * 1) module parameter via kernel command line in form
1611 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1612 */
1613 iap = macaddr;
1614
1615 /*
1616 * 2) from device tree data
1617 */
1618 if (!is_valid_ether_addr(iap)) {
1619 struct device_node *np = fep->pdev->dev.of_node;
1620 if (np) {
1621 const char *mac = of_get_mac_address(np);
1622 if (mac)
1623 iap = (unsigned char *) mac;
1624 }
1625 }
1626
1627 /*
1628 * 3) from flash or fuse (via platform data)
1629 */
1630 if (!is_valid_ether_addr(iap)) {
1631 #ifdef CONFIG_M5272
1632 if (FEC_FLASHMAC)
1633 iap = (unsigned char *)FEC_FLASHMAC;
1634 #else
1635 if (pdata)
1636 iap = (unsigned char *)&pdata->mac;
1637 #endif
1638 }
1639
1640 /*
1641 * 4) FEC mac registers set by bootloader
1642 */
1643 if (!is_valid_ether_addr(iap)) {
1644 *((__be32 *) &tmpaddr[0]) =
1645 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1646 *((__be16 *) &tmpaddr[4]) =
1647 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1648 iap = &tmpaddr[0];
1649 }
1650
1651 /*
1652 * 5) random mac address
1653 */
1654 if (!is_valid_ether_addr(iap)) {
1655 /* Report it and use a random ethernet address instead */
1656 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1657 eth_hw_addr_random(ndev);
1658 netdev_info(ndev, "Using random MAC address: %pM\n",
1659 ndev->dev_addr);
1660 return;
1661 }
1662
1663 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1664
1665 /* Adjust MAC if using macaddr */
1666 if (iap == macaddr)
1667 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1668 }
1669
1670 /* ------------------------------------------------------------------------- */
1671
1672 /*
1673 * Phy section
1674 */
1675 static void fec_enet_adjust_link(struct net_device *ndev)
1676 {
1677 struct fec_enet_private *fep = netdev_priv(ndev);
1678 struct phy_device *phy_dev = fep->phy_dev;
1679 int status_change = 0;
1680
1681 /* Prevent a state halted on mii error */
1682 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1683 phy_dev->state = PHY_RESUMING;
1684 return;
1685 }
1686
1687 /*
1688 * If the netdev is down, or is going down, we're not interested
1689 * in link state events, so just mark our idea of the link as down
1690 * and ignore the event.
1691 */
1692 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1693 fep->link = 0;
1694 } else if (phy_dev->link) {
1695 if (!fep->link) {
1696 fep->link = phy_dev->link;
1697 status_change = 1;
1698 }
1699
1700 if (fep->full_duplex != phy_dev->duplex) {
1701 fep->full_duplex = phy_dev->duplex;
1702 status_change = 1;
1703 }
1704
1705 if (phy_dev->speed != fep->speed) {
1706 fep->speed = phy_dev->speed;
1707 status_change = 1;
1708 }
1709
1710 /* if any of the above changed restart the FEC */
1711 if (status_change) {
1712 napi_disable(&fep->napi);
1713 netif_tx_lock_bh(ndev);
1714 fec_restart(ndev);
1715 netif_wake_queue(ndev);
1716 netif_tx_unlock_bh(ndev);
1717 napi_enable(&fep->napi);
1718 }
1719 } else {
1720 if (fep->link) {
1721 napi_disable(&fep->napi);
1722 netif_tx_lock_bh(ndev);
1723 fec_stop(ndev);
1724 netif_tx_unlock_bh(ndev);
1725 napi_enable(&fep->napi);
1726 fep->link = phy_dev->link;
1727 status_change = 1;
1728 }
1729 }
1730
1731 if (status_change)
1732 phy_print_status(phy_dev);
1733 }
1734
1735 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1736 {
1737 struct fec_enet_private *fep = bus->priv;
1738 unsigned long time_left;
1739
1740 fep->mii_timeout = 0;
1741 init_completion(&fep->mdio_done);
1742
1743 /* start a read op */
1744 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1745 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1746 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1747
1748 /* wait for end of transfer */
1749 time_left = wait_for_completion_timeout(&fep->mdio_done,
1750 usecs_to_jiffies(FEC_MII_TIMEOUT));
1751 if (time_left == 0) {
1752 fep->mii_timeout = 1;
1753 netdev_err(fep->netdev, "MDIO read timeout\n");
1754 return -ETIMEDOUT;
1755 }
1756
1757 /* return value */
1758 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1759 }
1760
1761 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1762 u16 value)
1763 {
1764 struct fec_enet_private *fep = bus->priv;
1765 unsigned long time_left;
1766
1767 fep->mii_timeout = 0;
1768 init_completion(&fep->mdio_done);
1769
1770 /* start a write op */
1771 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1772 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1773 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1774 fep->hwp + FEC_MII_DATA);
1775
1776 /* wait for end of transfer */
1777 time_left = wait_for_completion_timeout(&fep->mdio_done,
1778 usecs_to_jiffies(FEC_MII_TIMEOUT));
1779 if (time_left == 0) {
1780 fep->mii_timeout = 1;
1781 netdev_err(fep->netdev, "MDIO write timeout\n");
1782 return -ETIMEDOUT;
1783 }
1784
1785 return 0;
1786 }
1787
1788 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1789 {
1790 struct fec_enet_private *fep = netdev_priv(ndev);
1791 int ret;
1792
1793 if (enable) {
1794 ret = clk_prepare_enable(fep->clk_ahb);
1795 if (ret)
1796 return ret;
1797 ret = clk_prepare_enable(fep->clk_ipg);
1798 if (ret)
1799 goto failed_clk_ipg;
1800 if (fep->clk_enet_out) {
1801 ret = clk_prepare_enable(fep->clk_enet_out);
1802 if (ret)
1803 goto failed_clk_enet_out;
1804 }
1805 if (fep->clk_ptp) {
1806 mutex_lock(&fep->ptp_clk_mutex);
1807 ret = clk_prepare_enable(fep->clk_ptp);
1808 if (ret) {
1809 mutex_unlock(&fep->ptp_clk_mutex);
1810 goto failed_clk_ptp;
1811 } else {
1812 fep->ptp_clk_on = true;
1813 }
1814 mutex_unlock(&fep->ptp_clk_mutex);
1815 }
1816 if (fep->clk_ref) {
1817 ret = clk_prepare_enable(fep->clk_ref);
1818 if (ret)
1819 goto failed_clk_ref;
1820 }
1821 } else {
1822 clk_disable_unprepare(fep->clk_ahb);
1823 clk_disable_unprepare(fep->clk_ipg);
1824 if (fep->clk_enet_out)
1825 clk_disable_unprepare(fep->clk_enet_out);
1826 if (fep->clk_ptp) {
1827 mutex_lock(&fep->ptp_clk_mutex);
1828 clk_disable_unprepare(fep->clk_ptp);
1829 fep->ptp_clk_on = false;
1830 mutex_unlock(&fep->ptp_clk_mutex);
1831 }
1832 if (fep->clk_ref)
1833 clk_disable_unprepare(fep->clk_ref);
1834 }
1835
1836 return 0;
1837
1838 failed_clk_ref:
1839 if (fep->clk_ref)
1840 clk_disable_unprepare(fep->clk_ref);
1841 failed_clk_ptp:
1842 if (fep->clk_enet_out)
1843 clk_disable_unprepare(fep->clk_enet_out);
1844 failed_clk_enet_out:
1845 clk_disable_unprepare(fep->clk_ipg);
1846 failed_clk_ipg:
1847 clk_disable_unprepare(fep->clk_ahb);
1848
1849 return ret;
1850 }
1851
1852 static int fec_enet_mii_probe(struct net_device *ndev)
1853 {
1854 struct fec_enet_private *fep = netdev_priv(ndev);
1855 const struct platform_device_id *id_entry =
1856 platform_get_device_id(fep->pdev);
1857 struct phy_device *phy_dev = NULL;
1858 char mdio_bus_id[MII_BUS_ID_SIZE];
1859 char phy_name[MII_BUS_ID_SIZE + 3];
1860 int phy_id;
1861 int dev_id = fep->dev_id;
1862
1863 fep->phy_dev = NULL;
1864
1865 if (fep->phy_node) {
1866 phy_dev = of_phy_connect(ndev, fep->phy_node,
1867 &fec_enet_adjust_link, 0,
1868 fep->phy_interface);
1869 } else {
1870 /* check for attached phy */
1871 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1872 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1873 continue;
1874 if (fep->mii_bus->phy_map[phy_id] == NULL)
1875 continue;
1876 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1877 continue;
1878 if (dev_id--)
1879 continue;
1880 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1881 break;
1882 }
1883
1884 if (phy_id >= PHY_MAX_ADDR) {
1885 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1886 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1887 phy_id = 0;
1888 }
1889
1890 snprintf(phy_name, sizeof(phy_name),
1891 PHY_ID_FMT, mdio_bus_id, phy_id);
1892 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1893 fep->phy_interface);
1894 }
1895
1896 if (IS_ERR(phy_dev)) {
1897 netdev_err(ndev, "could not attach to PHY\n");
1898 return PTR_ERR(phy_dev);
1899 }
1900
1901 /* mask with MAC supported features */
1902 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1903 phy_dev->supported &= PHY_GBIT_FEATURES;
1904 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1905 #if !defined(CONFIG_M5272)
1906 phy_dev->supported |= SUPPORTED_Pause;
1907 #endif
1908 }
1909 else
1910 phy_dev->supported &= PHY_BASIC_FEATURES;
1911
1912 phy_dev->advertising = phy_dev->supported;
1913
1914 fep->phy_dev = phy_dev;
1915 fep->link = 0;
1916 fep->full_duplex = 0;
1917
1918 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1919 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1920 fep->phy_dev->irq);
1921
1922 return 0;
1923 }
1924
1925 static int fec_enet_mii_init(struct platform_device *pdev)
1926 {
1927 static struct mii_bus *fec0_mii_bus;
1928 struct net_device *ndev = platform_get_drvdata(pdev);
1929 struct fec_enet_private *fep = netdev_priv(ndev);
1930 const struct platform_device_id *id_entry =
1931 platform_get_device_id(fep->pdev);
1932 struct device_node *node;
1933 int err = -ENXIO, i;
1934
1935 /*
1936 * The dual fec interfaces are not equivalent with enet-mac.
1937 * Here are the differences:
1938 *
1939 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1940 * - fec0 acts as the 1588 time master while fec1 is slave
1941 * - external phys can only be configured by fec0
1942 *
1943 * That is to say fec1 can not work independently. It only works
1944 * when fec0 is working. The reason behind this design is that the
1945 * second interface is added primarily for Switch mode.
1946 *
1947 * Because of the last point above, both phys are attached on fec0
1948 * mdio interface in board design, and need to be configured by
1949 * fec0 mii_bus.
1950 */
1951 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1952 /* fec1 uses fec0 mii_bus */
1953 if (mii_cnt && fec0_mii_bus) {
1954 fep->mii_bus = fec0_mii_bus;
1955 mii_cnt++;
1956 return 0;
1957 }
1958 return -ENOENT;
1959 }
1960
1961 fep->mii_timeout = 0;
1962
1963 /*
1964 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1965 *
1966 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1967 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1968 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1969 * document.
1970 */
1971 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
1972 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1973 fep->phy_speed--;
1974 fep->phy_speed <<= 1;
1975 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1976
1977 fep->mii_bus = mdiobus_alloc();
1978 if (fep->mii_bus == NULL) {
1979 err = -ENOMEM;
1980 goto err_out;
1981 }
1982
1983 fep->mii_bus->name = "fec_enet_mii_bus";
1984 fep->mii_bus->read = fec_enet_mdio_read;
1985 fep->mii_bus->write = fec_enet_mdio_write;
1986 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1987 pdev->name, fep->dev_id + 1);
1988 fep->mii_bus->priv = fep;
1989 fep->mii_bus->parent = &pdev->dev;
1990
1991 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1992 if (!fep->mii_bus->irq) {
1993 err = -ENOMEM;
1994 goto err_out_free_mdiobus;
1995 }
1996
1997 for (i = 0; i < PHY_MAX_ADDR; i++)
1998 fep->mii_bus->irq[i] = PHY_POLL;
1999
2000 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2001 if (node) {
2002 err = of_mdiobus_register(fep->mii_bus, node);
2003 of_node_put(node);
2004 } else {
2005 err = mdiobus_register(fep->mii_bus);
2006 }
2007
2008 if (err)
2009 goto err_out_free_mdio_irq;
2010
2011 mii_cnt++;
2012
2013 /* save fec0 mii_bus */
2014 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
2015 fec0_mii_bus = fep->mii_bus;
2016
2017 return 0;
2018
2019 err_out_free_mdio_irq:
2020 kfree(fep->mii_bus->irq);
2021 err_out_free_mdiobus:
2022 mdiobus_free(fep->mii_bus);
2023 err_out:
2024 return err;
2025 }
2026
2027 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2028 {
2029 if (--mii_cnt == 0) {
2030 mdiobus_unregister(fep->mii_bus);
2031 kfree(fep->mii_bus->irq);
2032 mdiobus_free(fep->mii_bus);
2033 }
2034 }
2035
2036 static int fec_enet_get_settings(struct net_device *ndev,
2037 struct ethtool_cmd *cmd)
2038 {
2039 struct fec_enet_private *fep = netdev_priv(ndev);
2040 struct phy_device *phydev = fep->phy_dev;
2041
2042 if (!phydev)
2043 return -ENODEV;
2044
2045 return phy_ethtool_gset(phydev, cmd);
2046 }
2047
2048 static int fec_enet_set_settings(struct net_device *ndev,
2049 struct ethtool_cmd *cmd)
2050 {
2051 struct fec_enet_private *fep = netdev_priv(ndev);
2052 struct phy_device *phydev = fep->phy_dev;
2053
2054 if (!phydev)
2055 return -ENODEV;
2056
2057 return phy_ethtool_sset(phydev, cmd);
2058 }
2059
2060 static void fec_enet_get_drvinfo(struct net_device *ndev,
2061 struct ethtool_drvinfo *info)
2062 {
2063 struct fec_enet_private *fep = netdev_priv(ndev);
2064
2065 strlcpy(info->driver, fep->pdev->dev.driver->name,
2066 sizeof(info->driver));
2067 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2068 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2069 }
2070
2071 static int fec_enet_get_ts_info(struct net_device *ndev,
2072 struct ethtool_ts_info *info)
2073 {
2074 struct fec_enet_private *fep = netdev_priv(ndev);
2075
2076 if (fep->bufdesc_ex) {
2077
2078 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2079 SOF_TIMESTAMPING_RX_SOFTWARE |
2080 SOF_TIMESTAMPING_SOFTWARE |
2081 SOF_TIMESTAMPING_TX_HARDWARE |
2082 SOF_TIMESTAMPING_RX_HARDWARE |
2083 SOF_TIMESTAMPING_RAW_HARDWARE;
2084 if (fep->ptp_clock)
2085 info->phc_index = ptp_clock_index(fep->ptp_clock);
2086 else
2087 info->phc_index = -1;
2088
2089 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2090 (1 << HWTSTAMP_TX_ON);
2091
2092 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2093 (1 << HWTSTAMP_FILTER_ALL);
2094 return 0;
2095 } else {
2096 return ethtool_op_get_ts_info(ndev, info);
2097 }
2098 }
2099
2100 #if !defined(CONFIG_M5272)
2101
2102 static void fec_enet_get_pauseparam(struct net_device *ndev,
2103 struct ethtool_pauseparam *pause)
2104 {
2105 struct fec_enet_private *fep = netdev_priv(ndev);
2106
2107 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2108 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2109 pause->rx_pause = pause->tx_pause;
2110 }
2111
2112 static int fec_enet_set_pauseparam(struct net_device *ndev,
2113 struct ethtool_pauseparam *pause)
2114 {
2115 struct fec_enet_private *fep = netdev_priv(ndev);
2116
2117 if (!fep->phy_dev)
2118 return -ENODEV;
2119
2120 if (pause->tx_pause != pause->rx_pause) {
2121 netdev_info(ndev,
2122 "hardware only support enable/disable both tx and rx");
2123 return -EINVAL;
2124 }
2125
2126 fep->pause_flag = 0;
2127
2128 /* tx pause must be same as rx pause */
2129 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2130 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2131
2132 if (pause->rx_pause || pause->autoneg) {
2133 fep->phy_dev->supported |= ADVERTISED_Pause;
2134 fep->phy_dev->advertising |= ADVERTISED_Pause;
2135 } else {
2136 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2137 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2138 }
2139
2140 if (pause->autoneg) {
2141 if (netif_running(ndev))
2142 fec_stop(ndev);
2143 phy_start_aneg(fep->phy_dev);
2144 }
2145 if (netif_running(ndev)) {
2146 napi_disable(&fep->napi);
2147 netif_tx_lock_bh(ndev);
2148 fec_restart(ndev);
2149 netif_wake_queue(ndev);
2150 netif_tx_unlock_bh(ndev);
2151 napi_enable(&fep->napi);
2152 }
2153
2154 return 0;
2155 }
2156
2157 static const struct fec_stat {
2158 char name[ETH_GSTRING_LEN];
2159 u16 offset;
2160 } fec_stats[] = {
2161 /* RMON TX */
2162 { "tx_dropped", RMON_T_DROP },
2163 { "tx_packets", RMON_T_PACKETS },
2164 { "tx_broadcast", RMON_T_BC_PKT },
2165 { "tx_multicast", RMON_T_MC_PKT },
2166 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2167 { "tx_undersize", RMON_T_UNDERSIZE },
2168 { "tx_oversize", RMON_T_OVERSIZE },
2169 { "tx_fragment", RMON_T_FRAG },
2170 { "tx_jabber", RMON_T_JAB },
2171 { "tx_collision", RMON_T_COL },
2172 { "tx_64byte", RMON_T_P64 },
2173 { "tx_65to127byte", RMON_T_P65TO127 },
2174 { "tx_128to255byte", RMON_T_P128TO255 },
2175 { "tx_256to511byte", RMON_T_P256TO511 },
2176 { "tx_512to1023byte", RMON_T_P512TO1023 },
2177 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2178 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2179 { "tx_octets", RMON_T_OCTETS },
2180
2181 /* IEEE TX */
2182 { "IEEE_tx_drop", IEEE_T_DROP },
2183 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2184 { "IEEE_tx_1col", IEEE_T_1COL },
2185 { "IEEE_tx_mcol", IEEE_T_MCOL },
2186 { "IEEE_tx_def", IEEE_T_DEF },
2187 { "IEEE_tx_lcol", IEEE_T_LCOL },
2188 { "IEEE_tx_excol", IEEE_T_EXCOL },
2189 { "IEEE_tx_macerr", IEEE_T_MACERR },
2190 { "IEEE_tx_cserr", IEEE_T_CSERR },
2191 { "IEEE_tx_sqe", IEEE_T_SQE },
2192 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2193 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2194
2195 /* RMON RX */
2196 { "rx_packets", RMON_R_PACKETS },
2197 { "rx_broadcast", RMON_R_BC_PKT },
2198 { "rx_multicast", RMON_R_MC_PKT },
2199 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2200 { "rx_undersize", RMON_R_UNDERSIZE },
2201 { "rx_oversize", RMON_R_OVERSIZE },
2202 { "rx_fragment", RMON_R_FRAG },
2203 { "rx_jabber", RMON_R_JAB },
2204 { "rx_64byte", RMON_R_P64 },
2205 { "rx_65to127byte", RMON_R_P65TO127 },
2206 { "rx_128to255byte", RMON_R_P128TO255 },
2207 { "rx_256to511byte", RMON_R_P256TO511 },
2208 { "rx_512to1023byte", RMON_R_P512TO1023 },
2209 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2210 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2211 { "rx_octets", RMON_R_OCTETS },
2212
2213 /* IEEE RX */
2214 { "IEEE_rx_drop", IEEE_R_DROP },
2215 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2216 { "IEEE_rx_crc", IEEE_R_CRC },
2217 { "IEEE_rx_align", IEEE_R_ALIGN },
2218 { "IEEE_rx_macerr", IEEE_R_MACERR },
2219 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2220 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2221 };
2222
2223 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2224 struct ethtool_stats *stats, u64 *data)
2225 {
2226 struct fec_enet_private *fep = netdev_priv(dev);
2227 int i;
2228
2229 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2230 data[i] = readl(fep->hwp + fec_stats[i].offset);
2231 }
2232
2233 static void fec_enet_get_strings(struct net_device *netdev,
2234 u32 stringset, u8 *data)
2235 {
2236 int i;
2237 switch (stringset) {
2238 case ETH_SS_STATS:
2239 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2240 memcpy(data + i * ETH_GSTRING_LEN,
2241 fec_stats[i].name, ETH_GSTRING_LEN);
2242 break;
2243 }
2244 }
2245
2246 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2247 {
2248 switch (sset) {
2249 case ETH_SS_STATS:
2250 return ARRAY_SIZE(fec_stats);
2251 default:
2252 return -EOPNOTSUPP;
2253 }
2254 }
2255 #endif /* !defined(CONFIG_M5272) */
2256
2257 static int fec_enet_nway_reset(struct net_device *dev)
2258 {
2259 struct fec_enet_private *fep = netdev_priv(dev);
2260 struct phy_device *phydev = fep->phy_dev;
2261
2262 if (!phydev)
2263 return -ENODEV;
2264
2265 return genphy_restart_aneg(phydev);
2266 }
2267
2268 /* ITR clock source is enet system clock (clk_ahb).
2269 * TCTT unit is cycle_ns * 64 cycle
2270 * So, the ICTT value = X us / (cycle_ns * 64)
2271 */
2272 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2273 {
2274 struct fec_enet_private *fep = netdev_priv(ndev);
2275
2276 return us * (fep->itr_clk_rate / 64000) / 1000;
2277 }
2278
2279 /* Set threshold for interrupt coalescing */
2280 static void fec_enet_itr_coal_set(struct net_device *ndev)
2281 {
2282 struct fec_enet_private *fep = netdev_priv(ndev);
2283 const struct platform_device_id *id_entry =
2284 platform_get_device_id(fep->pdev);
2285 int rx_itr, tx_itr;
2286
2287 if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB))
2288 return;
2289
2290 /* Must be greater than zero to avoid unpredictable behavior */
2291 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2292 !fep->tx_time_itr || !fep->tx_pkts_itr)
2293 return;
2294
2295 /* Select enet system clock as Interrupt Coalescing
2296 * timer Clock Source
2297 */
2298 rx_itr = FEC_ITR_CLK_SEL;
2299 tx_itr = FEC_ITR_CLK_SEL;
2300
2301 /* set ICFT and ICTT */
2302 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2303 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2304 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2305 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2306
2307 rx_itr |= FEC_ITR_EN;
2308 tx_itr |= FEC_ITR_EN;
2309
2310 writel(tx_itr, fep->hwp + FEC_TXIC0);
2311 writel(rx_itr, fep->hwp + FEC_RXIC0);
2312 writel(tx_itr, fep->hwp + FEC_TXIC1);
2313 writel(rx_itr, fep->hwp + FEC_RXIC1);
2314 writel(tx_itr, fep->hwp + FEC_TXIC2);
2315 writel(rx_itr, fep->hwp + FEC_RXIC2);
2316 }
2317
2318 static int
2319 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2320 {
2321 struct fec_enet_private *fep = netdev_priv(ndev);
2322 const struct platform_device_id *id_entry =
2323 platform_get_device_id(fep->pdev);
2324
2325 if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB))
2326 return -EOPNOTSUPP;
2327
2328 ec->rx_coalesce_usecs = fep->rx_time_itr;
2329 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2330
2331 ec->tx_coalesce_usecs = fep->tx_time_itr;
2332 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2333
2334 return 0;
2335 }
2336
2337 static int
2338 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2339 {
2340 struct fec_enet_private *fep = netdev_priv(ndev);
2341 const struct platform_device_id *id_entry =
2342 platform_get_device_id(fep->pdev);
2343
2344 unsigned int cycle;
2345
2346 if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB))
2347 return -EOPNOTSUPP;
2348
2349 if (ec->rx_max_coalesced_frames > 255) {
2350 pr_err("Rx coalesced frames exceed hardware limiation");
2351 return -EINVAL;
2352 }
2353
2354 if (ec->tx_max_coalesced_frames > 255) {
2355 pr_err("Tx coalesced frame exceed hardware limiation");
2356 return -EINVAL;
2357 }
2358
2359 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2360 if (cycle > 0xFFFF) {
2361 pr_err("Rx coalesed usec exceeed hardware limiation");
2362 return -EINVAL;
2363 }
2364
2365 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2366 if (cycle > 0xFFFF) {
2367 pr_err("Rx coalesed usec exceeed hardware limiation");
2368 return -EINVAL;
2369 }
2370
2371 fep->rx_time_itr = ec->rx_coalesce_usecs;
2372 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2373
2374 fep->tx_time_itr = ec->tx_coalesce_usecs;
2375 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2376
2377 fec_enet_itr_coal_set(ndev);
2378
2379 return 0;
2380 }
2381
2382 static void fec_enet_itr_coal_init(struct net_device *ndev)
2383 {
2384 struct ethtool_coalesce ec;
2385
2386 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2387 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2388
2389 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2390 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2391
2392 fec_enet_set_coalesce(ndev, &ec);
2393 }
2394
2395 static const struct ethtool_ops fec_enet_ethtool_ops = {
2396 .get_settings = fec_enet_get_settings,
2397 .set_settings = fec_enet_set_settings,
2398 .get_drvinfo = fec_enet_get_drvinfo,
2399 .nway_reset = fec_enet_nway_reset,
2400 .get_link = ethtool_op_get_link,
2401 .get_coalesce = fec_enet_get_coalesce,
2402 .set_coalesce = fec_enet_set_coalesce,
2403 #ifndef CONFIG_M5272
2404 .get_pauseparam = fec_enet_get_pauseparam,
2405 .set_pauseparam = fec_enet_set_pauseparam,
2406 .get_strings = fec_enet_get_strings,
2407 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2408 .get_sset_count = fec_enet_get_sset_count,
2409 #endif
2410 .get_ts_info = fec_enet_get_ts_info,
2411 };
2412
2413 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2414 {
2415 struct fec_enet_private *fep = netdev_priv(ndev);
2416 struct phy_device *phydev = fep->phy_dev;
2417
2418 if (!netif_running(ndev))
2419 return -EINVAL;
2420
2421 if (!phydev)
2422 return -ENODEV;
2423
2424 if (fep->bufdesc_ex) {
2425 if (cmd == SIOCSHWTSTAMP)
2426 return fec_ptp_set(ndev, rq);
2427 if (cmd == SIOCGHWTSTAMP)
2428 return fec_ptp_get(ndev, rq);
2429 }
2430
2431 return phy_mii_ioctl(phydev, rq, cmd);
2432 }
2433
2434 static void fec_enet_free_buffers(struct net_device *ndev)
2435 {
2436 struct fec_enet_private *fep = netdev_priv(ndev);
2437 unsigned int i;
2438 struct sk_buff *skb;
2439 struct bufdesc *bdp;
2440 struct fec_enet_priv_tx_q *txq;
2441 struct fec_enet_priv_rx_q *rxq;
2442 unsigned int q;
2443
2444 for (q = 0; q < fep->num_rx_queues; q++) {
2445 rxq = fep->rx_queue[q];
2446 bdp = rxq->rx_bd_base;
2447 for (i = 0; i < rxq->rx_ring_size; i++) {
2448 skb = rxq->rx_skbuff[i];
2449 rxq->rx_skbuff[i] = NULL;
2450 if (skb) {
2451 dma_unmap_single(&fep->pdev->dev,
2452 bdp->cbd_bufaddr,
2453 FEC_ENET_RX_FRSIZE - fep->rx_align,
2454 DMA_FROM_DEVICE);
2455 dev_kfree_skb(skb);
2456 }
2457 bdp = fec_enet_get_nextdesc(bdp, fep, q);
2458 }
2459 }
2460
2461 for (q = 0; q < fep->num_tx_queues; q++) {
2462 txq = fep->tx_queue[q];
2463 bdp = txq->tx_bd_base;
2464 for (i = 0; i < txq->tx_ring_size; i++) {
2465 kfree(txq->tx_bounce[i]);
2466 txq->tx_bounce[i] = NULL;
2467 skb = txq->tx_skbuff[i];
2468 txq->tx_skbuff[i] = NULL;
2469 dev_kfree_skb(skb);
2470 }
2471 }
2472 }
2473
2474 static void fec_enet_free_queue(struct net_device *ndev)
2475 {
2476 struct fec_enet_private *fep = netdev_priv(ndev);
2477 int i;
2478 struct fec_enet_priv_tx_q *txq;
2479
2480 for (i = 0; i < fep->num_tx_queues; i++)
2481 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2482 txq = fep->tx_queue[i];
2483 dma_free_coherent(NULL,
2484 txq->tx_ring_size * TSO_HEADER_SIZE,
2485 txq->tso_hdrs,
2486 txq->tso_hdrs_dma);
2487 }
2488
2489 for (i = 0; i < fep->num_rx_queues; i++)
2490 if (fep->rx_queue[i])
2491 kfree(fep->rx_queue[i]);
2492
2493 for (i = 0; i < fep->num_tx_queues; i++)
2494 if (fep->tx_queue[i])
2495 kfree(fep->tx_queue[i]);
2496 }
2497
2498 static int fec_enet_alloc_queue(struct net_device *ndev)
2499 {
2500 struct fec_enet_private *fep = netdev_priv(ndev);
2501 int i;
2502 int ret = 0;
2503 struct fec_enet_priv_tx_q *txq;
2504
2505 for (i = 0; i < fep->num_tx_queues; i++) {
2506 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2507 if (!txq) {
2508 ret = -ENOMEM;
2509 goto alloc_failed;
2510 }
2511
2512 fep->tx_queue[i] = txq;
2513 txq->tx_ring_size = TX_RING_SIZE;
2514 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
2515
2516 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2517 txq->tx_wake_threshold =
2518 (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
2519
2520 txq->tso_hdrs = dma_alloc_coherent(NULL,
2521 txq->tx_ring_size * TSO_HEADER_SIZE,
2522 &txq->tso_hdrs_dma,
2523 GFP_KERNEL);
2524 if (!txq->tso_hdrs) {
2525 ret = -ENOMEM;
2526 goto alloc_failed;
2527 }
2528 }
2529
2530 for (i = 0; i < fep->num_rx_queues; i++) {
2531 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2532 GFP_KERNEL);
2533 if (!fep->rx_queue[i]) {
2534 ret = -ENOMEM;
2535 goto alloc_failed;
2536 }
2537
2538 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
2539 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
2540 }
2541 return ret;
2542
2543 alloc_failed:
2544 fec_enet_free_queue(ndev);
2545 return ret;
2546 }
2547
2548 static int
2549 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2550 {
2551 struct fec_enet_private *fep = netdev_priv(ndev);
2552 unsigned int i;
2553 struct sk_buff *skb;
2554 struct bufdesc *bdp;
2555 struct fec_enet_priv_rx_q *rxq;
2556 unsigned int off;
2557
2558 rxq = fep->rx_queue[queue];
2559 bdp = rxq->rx_bd_base;
2560 for (i = 0; i < rxq->rx_ring_size; i++) {
2561 dma_addr_t addr;
2562
2563 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2564 if (!skb)
2565 goto err_alloc;
2566
2567 off = ((unsigned long)skb->data) & fep->rx_align;
2568 if (off)
2569 skb_reserve(skb, fep->rx_align + 1 - off);
2570
2571 addr = dma_map_single(&fep->pdev->dev, skb->data,
2572 FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE);
2573
2574 if (dma_mapping_error(&fep->pdev->dev, addr)) {
2575 dev_kfree_skb(skb);
2576 if (net_ratelimit())
2577 netdev_err(ndev, "Rx DMA memory map failed\n");
2578 goto err_alloc;
2579 }
2580
2581 rxq->rx_skbuff[i] = skb;
2582 bdp->cbd_bufaddr = addr;
2583 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2584
2585 if (fep->bufdesc_ex) {
2586 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2587 ebdp->cbd_esc = BD_ENET_RX_INT;
2588 }
2589
2590 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2591 }
2592
2593 /* Set the last buffer to wrap. */
2594 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2595 bdp->cbd_sc |= BD_SC_WRAP;
2596 return 0;
2597
2598 err_alloc:
2599 fec_enet_free_buffers(ndev);
2600 return -ENOMEM;
2601 }
2602
2603 static int
2604 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2605 {
2606 struct fec_enet_private *fep = netdev_priv(ndev);
2607 unsigned int i;
2608 struct bufdesc *bdp;
2609 struct fec_enet_priv_tx_q *txq;
2610
2611 txq = fep->tx_queue[queue];
2612 bdp = txq->tx_bd_base;
2613 for (i = 0; i < txq->tx_ring_size; i++) {
2614 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2615 if (!txq->tx_bounce[i])
2616 goto err_alloc;
2617
2618 bdp->cbd_sc = 0;
2619 bdp->cbd_bufaddr = 0;
2620
2621 if (fep->bufdesc_ex) {
2622 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2623 ebdp->cbd_esc = BD_ENET_TX_INT;
2624 }
2625
2626 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2627 }
2628
2629 /* Set the last buffer to wrap. */
2630 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2631 bdp->cbd_sc |= BD_SC_WRAP;
2632
2633 return 0;
2634
2635 err_alloc:
2636 fec_enet_free_buffers(ndev);
2637 return -ENOMEM;
2638 }
2639
2640 static int fec_enet_alloc_buffers(struct net_device *ndev)
2641 {
2642 struct fec_enet_private *fep = netdev_priv(ndev);
2643 unsigned int i;
2644
2645 for (i = 0; i < fep->num_rx_queues; i++)
2646 if (fec_enet_alloc_rxq_buffers(ndev, i))
2647 return -ENOMEM;
2648
2649 for (i = 0; i < fep->num_tx_queues; i++)
2650 if (fec_enet_alloc_txq_buffers(ndev, i))
2651 return -ENOMEM;
2652 return 0;
2653 }
2654
2655 static int
2656 fec_enet_open(struct net_device *ndev)
2657 {
2658 struct fec_enet_private *fep = netdev_priv(ndev);
2659 int ret;
2660
2661 pinctrl_pm_select_default_state(&fep->pdev->dev);
2662 ret = fec_enet_clk_enable(ndev, true);
2663 if (ret)
2664 return ret;
2665
2666 /* I should reset the ring buffers here, but I don't yet know
2667 * a simple way to do that.
2668 */
2669
2670 ret = fec_enet_alloc_buffers(ndev);
2671 if (ret)
2672 return ret;
2673
2674 /* Probe and connect to PHY when open the interface */
2675 ret = fec_enet_mii_probe(ndev);
2676 if (ret) {
2677 fec_enet_free_buffers(ndev);
2678 fec_enet_clk_enable(ndev, false);
2679 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2680 return ret;
2681 }
2682
2683 fec_restart(ndev);
2684 napi_enable(&fep->napi);
2685 phy_start(fep->phy_dev);
2686 netif_tx_start_all_queues(ndev);
2687
2688 return 0;
2689 }
2690
2691 static int
2692 fec_enet_close(struct net_device *ndev)
2693 {
2694 struct fec_enet_private *fep = netdev_priv(ndev);
2695
2696 phy_stop(fep->phy_dev);
2697
2698 if (netif_device_present(ndev)) {
2699 napi_disable(&fep->napi);
2700 netif_tx_disable(ndev);
2701 fec_stop(ndev);
2702 }
2703
2704 phy_disconnect(fep->phy_dev);
2705 fep->phy_dev = NULL;
2706
2707 fec_enet_clk_enable(ndev, false);
2708 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2709 fec_enet_free_buffers(ndev);
2710
2711 return 0;
2712 }
2713
2714 /* Set or clear the multicast filter for this adaptor.
2715 * Skeleton taken from sunlance driver.
2716 * The CPM Ethernet implementation allows Multicast as well as individual
2717 * MAC address filtering. Some of the drivers check to make sure it is
2718 * a group multicast address, and discard those that are not. I guess I
2719 * will do the same for now, but just remove the test if you want
2720 * individual filtering as well (do the upper net layers want or support
2721 * this kind of feature?).
2722 */
2723
2724 #define HASH_BITS 6 /* #bits in hash */
2725 #define CRC32_POLY 0xEDB88320
2726
2727 static void set_multicast_list(struct net_device *ndev)
2728 {
2729 struct fec_enet_private *fep = netdev_priv(ndev);
2730 struct netdev_hw_addr *ha;
2731 unsigned int i, bit, data, crc, tmp;
2732 unsigned char hash;
2733
2734 if (ndev->flags & IFF_PROMISC) {
2735 tmp = readl(fep->hwp + FEC_R_CNTRL);
2736 tmp |= 0x8;
2737 writel(tmp, fep->hwp + FEC_R_CNTRL);
2738 return;
2739 }
2740
2741 tmp = readl(fep->hwp + FEC_R_CNTRL);
2742 tmp &= ~0x8;
2743 writel(tmp, fep->hwp + FEC_R_CNTRL);
2744
2745 if (ndev->flags & IFF_ALLMULTI) {
2746 /* Catch all multicast addresses, so set the
2747 * filter to all 1's
2748 */
2749 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2750 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2751
2752 return;
2753 }
2754
2755 /* Clear filter and add the addresses in hash register
2756 */
2757 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2758 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2759
2760 netdev_for_each_mc_addr(ha, ndev) {
2761 /* calculate crc32 value of mac address */
2762 crc = 0xffffffff;
2763
2764 for (i = 0; i < ndev->addr_len; i++) {
2765 data = ha->addr[i];
2766 for (bit = 0; bit < 8; bit++, data >>= 1) {
2767 crc = (crc >> 1) ^
2768 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2769 }
2770 }
2771
2772 /* only upper 6 bits (HASH_BITS) are used
2773 * which point to specific bit in he hash registers
2774 */
2775 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2776
2777 if (hash > 31) {
2778 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2779 tmp |= 1 << (hash - 32);
2780 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2781 } else {
2782 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2783 tmp |= 1 << hash;
2784 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2785 }
2786 }
2787 }
2788
2789 /* Set a MAC change in hardware. */
2790 static int
2791 fec_set_mac_address(struct net_device *ndev, void *p)
2792 {
2793 struct fec_enet_private *fep = netdev_priv(ndev);
2794 struct sockaddr *addr = p;
2795
2796 if (addr) {
2797 if (!is_valid_ether_addr(addr->sa_data))
2798 return -EADDRNOTAVAIL;
2799 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2800 }
2801
2802 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2803 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
2804 fep->hwp + FEC_ADDR_LOW);
2805 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
2806 fep->hwp + FEC_ADDR_HIGH);
2807 return 0;
2808 }
2809
2810 #ifdef CONFIG_NET_POLL_CONTROLLER
2811 /**
2812 * fec_poll_controller - FEC Poll controller function
2813 * @dev: The FEC network adapter
2814 *
2815 * Polled functionality used by netconsole and others in non interrupt mode
2816 *
2817 */
2818 static void fec_poll_controller(struct net_device *dev)
2819 {
2820 int i;
2821 struct fec_enet_private *fep = netdev_priv(dev);
2822
2823 for (i = 0; i < FEC_IRQ_NUM; i++) {
2824 if (fep->irq[i] > 0) {
2825 disable_irq(fep->irq[i]);
2826 fec_enet_interrupt(fep->irq[i], dev);
2827 enable_irq(fep->irq[i]);
2828 }
2829 }
2830 }
2831 #endif
2832
2833 #define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM
2834
2835 static int fec_set_features(struct net_device *netdev,
2836 netdev_features_t features)
2837 {
2838 struct fec_enet_private *fep = netdev_priv(netdev);
2839 netdev_features_t changed = features ^ netdev->features;
2840
2841 /* Quiesce the device if necessary */
2842 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
2843 napi_disable(&fep->napi);
2844 netif_tx_lock_bh(netdev);
2845 fec_stop(netdev);
2846 }
2847
2848 netdev->features = features;
2849
2850 /* Receive checksum has been changed */
2851 if (changed & NETIF_F_RXCSUM) {
2852 if (features & NETIF_F_RXCSUM)
2853 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2854 else
2855 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
2856 }
2857
2858 /* Resume the device after updates */
2859 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
2860 fec_restart(netdev);
2861 netif_tx_wake_all_queues(netdev);
2862 netif_tx_unlock_bh(netdev);
2863 napi_enable(&fep->napi);
2864 }
2865
2866 return 0;
2867 }
2868
2869 static const struct net_device_ops fec_netdev_ops = {
2870 .ndo_open = fec_enet_open,
2871 .ndo_stop = fec_enet_close,
2872 .ndo_start_xmit = fec_enet_start_xmit,
2873 .ndo_set_rx_mode = set_multicast_list,
2874 .ndo_change_mtu = eth_change_mtu,
2875 .ndo_validate_addr = eth_validate_addr,
2876 .ndo_tx_timeout = fec_timeout,
2877 .ndo_set_mac_address = fec_set_mac_address,
2878 .ndo_do_ioctl = fec_enet_ioctl,
2879 #ifdef CONFIG_NET_POLL_CONTROLLER
2880 .ndo_poll_controller = fec_poll_controller,
2881 #endif
2882 .ndo_set_features = fec_set_features,
2883 };
2884
2885 /*
2886 * XXX: We need to clean up on failure exits here.
2887 *
2888 */
2889 static int fec_enet_init(struct net_device *ndev)
2890 {
2891 struct fec_enet_private *fep = netdev_priv(ndev);
2892 const struct platform_device_id *id_entry =
2893 platform_get_device_id(fep->pdev);
2894 struct fec_enet_priv_tx_q *txq;
2895 struct fec_enet_priv_rx_q *rxq;
2896 struct bufdesc *cbd_base;
2897 dma_addr_t bd_dma;
2898 int bd_size;
2899 unsigned int i;
2900
2901 #if defined(CONFIG_ARM)
2902 fep->rx_align = 0xf;
2903 fep->tx_align = 0xf;
2904 #else
2905 fep->rx_align = 0x3;
2906 fep->tx_align = 0x3;
2907 #endif
2908
2909 fec_enet_alloc_queue(ndev);
2910
2911 if (fep->bufdesc_ex)
2912 fep->bufdesc_size = sizeof(struct bufdesc_ex);
2913 else
2914 fep->bufdesc_size = sizeof(struct bufdesc);
2915 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
2916 fep->bufdesc_size;
2917
2918 /* Allocate memory for buffer descriptors. */
2919 cbd_base = dma_alloc_coherent(NULL, bd_size, &bd_dma,
2920 GFP_KERNEL);
2921 if (!cbd_base) {
2922 return -ENOMEM;
2923 }
2924
2925 memset(cbd_base, 0, bd_size);
2926
2927 /* Get the Ethernet address */
2928 fec_get_mac(ndev);
2929 /* make sure MAC we just acquired is programmed into the hw */
2930 fec_set_mac_address(ndev, NULL);
2931
2932 /* Set receive and transmit descriptor base. */
2933 for (i = 0; i < fep->num_rx_queues; i++) {
2934 rxq = fep->rx_queue[i];
2935 rxq->index = i;
2936 rxq->rx_bd_base = (struct bufdesc *)cbd_base;
2937 rxq->bd_dma = bd_dma;
2938 if (fep->bufdesc_ex) {
2939 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
2940 cbd_base = (struct bufdesc *)
2941 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
2942 } else {
2943 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
2944 cbd_base += rxq->rx_ring_size;
2945 }
2946 }
2947
2948 for (i = 0; i < fep->num_tx_queues; i++) {
2949 txq = fep->tx_queue[i];
2950 txq->index = i;
2951 txq->tx_bd_base = (struct bufdesc *)cbd_base;
2952 txq->bd_dma = bd_dma;
2953 if (fep->bufdesc_ex) {
2954 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
2955 cbd_base = (struct bufdesc *)
2956 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
2957 } else {
2958 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
2959 cbd_base += txq->tx_ring_size;
2960 }
2961 }
2962
2963
2964 /* The FEC Ethernet specific entries in the device structure */
2965 ndev->watchdog_timeo = TX_TIMEOUT;
2966 ndev->netdev_ops = &fec_netdev_ops;
2967 ndev->ethtool_ops = &fec_enet_ethtool_ops;
2968
2969 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
2970 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
2971
2972 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN)
2973 /* enable hw VLAN support */
2974 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2975
2976 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
2977 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
2978
2979 /* enable hw accelerator */
2980 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2981 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
2982 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2983 }
2984
2985 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB) {
2986 fep->tx_align = 0;
2987 fep->rx_align = 0x3f;
2988 }
2989
2990 ndev->hw_features = ndev->features;
2991
2992 fec_restart(ndev);
2993
2994 return 0;
2995 }
2996
2997 #ifdef CONFIG_OF
2998 static void fec_reset_phy(struct platform_device *pdev)
2999 {
3000 int err, phy_reset;
3001 int msec = 1;
3002 struct device_node *np = pdev->dev.of_node;
3003
3004 if (!np)
3005 return;
3006
3007 of_property_read_u32(np, "phy-reset-duration", &msec);
3008 /* A sane reset duration should not be longer than 1s */
3009 if (msec > 1000)
3010 msec = 1;
3011
3012 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3013 if (!gpio_is_valid(phy_reset))
3014 return;
3015
3016 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3017 GPIOF_OUT_INIT_LOW, "phy-reset");
3018 if (err) {
3019 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3020 return;
3021 }
3022 msleep(msec);
3023 gpio_set_value(phy_reset, 1);
3024 }
3025 #else /* CONFIG_OF */
3026 static void fec_reset_phy(struct platform_device *pdev)
3027 {
3028 /*
3029 * In case of platform probe, the reset has been done
3030 * by machine code.
3031 */
3032 }
3033 #endif /* CONFIG_OF */
3034
3035 static void
3036 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3037 {
3038 struct device_node *np = pdev->dev.of_node;
3039 int err;
3040
3041 *num_tx = *num_rx = 1;
3042
3043 if (!np || !of_device_is_available(np))
3044 return;
3045
3046 /* parse the num of tx and rx queues */
3047 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3048 if (err)
3049 *num_tx = 1;
3050
3051 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3052 if (err)
3053 *num_rx = 1;
3054
3055 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3056 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3057 *num_tx);
3058 *num_tx = 1;
3059 return;
3060 }
3061
3062 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3063 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3064 *num_rx);
3065 *num_rx = 1;
3066 return;
3067 }
3068
3069 }
3070
3071 static int
3072 fec_probe(struct platform_device *pdev)
3073 {
3074 struct fec_enet_private *fep;
3075 struct fec_platform_data *pdata;
3076 struct net_device *ndev;
3077 int i, irq, ret = 0;
3078 struct resource *r;
3079 const struct of_device_id *of_id;
3080 static int dev_id;
3081 struct device_node *np = pdev->dev.of_node, *phy_node;
3082 int num_tx_qs;
3083 int num_rx_qs;
3084
3085 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3086 if (of_id)
3087 pdev->id_entry = of_id->data;
3088
3089 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3090
3091 /* Init network device */
3092 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3093 num_tx_qs, num_rx_qs);
3094 if (!ndev)
3095 return -ENOMEM;
3096
3097 SET_NETDEV_DEV(ndev, &pdev->dev);
3098
3099 /* setup board info structure */
3100 fep = netdev_priv(ndev);
3101
3102 fep->num_rx_queues = num_rx_qs;
3103 fep->num_tx_queues = num_tx_qs;
3104
3105 #if !defined(CONFIG_M5272)
3106 /* default enable pause frame auto negotiation */
3107 if (pdev->id_entry &&
3108 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
3109 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3110 #endif
3111
3112 /* Select default pin state */
3113 pinctrl_pm_select_default_state(&pdev->dev);
3114
3115 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3116 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3117 if (IS_ERR(fep->hwp)) {
3118 ret = PTR_ERR(fep->hwp);
3119 goto failed_ioremap;
3120 }
3121
3122 fep->pdev = pdev;
3123 fep->dev_id = dev_id++;
3124
3125 fep->bufdesc_ex = 0;
3126
3127 platform_set_drvdata(pdev, ndev);
3128
3129 phy_node = of_parse_phandle(np, "phy-handle", 0);
3130 if (!phy_node && of_phy_is_fixed_link(np)) {
3131 ret = of_phy_register_fixed_link(np);
3132 if (ret < 0) {
3133 dev_err(&pdev->dev,
3134 "broken fixed-link specification\n");
3135 goto failed_phy;
3136 }
3137 phy_node = of_node_get(np);
3138 }
3139 fep->phy_node = phy_node;
3140
3141 ret = of_get_phy_mode(pdev->dev.of_node);
3142 if (ret < 0) {
3143 pdata = dev_get_platdata(&pdev->dev);
3144 if (pdata)
3145 fep->phy_interface = pdata->phy;
3146 else
3147 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3148 } else {
3149 fep->phy_interface = ret;
3150 }
3151
3152 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3153 if (IS_ERR(fep->clk_ipg)) {
3154 ret = PTR_ERR(fep->clk_ipg);
3155 goto failed_clk;
3156 }
3157
3158 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3159 if (IS_ERR(fep->clk_ahb)) {
3160 ret = PTR_ERR(fep->clk_ahb);
3161 goto failed_clk;
3162 }
3163
3164 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3165
3166 /* enet_out is optional, depends on board */
3167 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3168 if (IS_ERR(fep->clk_enet_out))
3169 fep->clk_enet_out = NULL;
3170
3171 fep->ptp_clk_on = false;
3172 mutex_init(&fep->ptp_clk_mutex);
3173
3174 /* clk_ref is optional, depends on board */
3175 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3176 if (IS_ERR(fep->clk_ref))
3177 fep->clk_ref = NULL;
3178
3179 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3180 fep->bufdesc_ex =
3181 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
3182 if (IS_ERR(fep->clk_ptp)) {
3183 fep->clk_ptp = NULL;
3184 fep->bufdesc_ex = 0;
3185 }
3186
3187 ret = fec_enet_clk_enable(ndev, true);
3188 if (ret)
3189 goto failed_clk;
3190
3191 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3192 if (!IS_ERR(fep->reg_phy)) {
3193 ret = regulator_enable(fep->reg_phy);
3194 if (ret) {
3195 dev_err(&pdev->dev,
3196 "Failed to enable phy regulator: %d\n", ret);
3197 goto failed_regulator;
3198 }
3199 } else {
3200 fep->reg_phy = NULL;
3201 }
3202
3203 fec_reset_phy(pdev);
3204
3205 if (fep->bufdesc_ex)
3206 fec_ptp_init(pdev);
3207
3208 ret = fec_enet_init(ndev);
3209 if (ret)
3210 goto failed_init;
3211
3212 for (i = 0; i < FEC_IRQ_NUM; i++) {
3213 irq = platform_get_irq(pdev, i);
3214 if (irq < 0) {
3215 if (i)
3216 break;
3217 ret = irq;
3218 goto failed_irq;
3219 }
3220 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3221 0, pdev->name, ndev);
3222 if (ret)
3223 goto failed_irq;
3224 }
3225
3226 init_completion(&fep->mdio_done);
3227 ret = fec_enet_mii_init(pdev);
3228 if (ret)
3229 goto failed_mii_init;
3230
3231 /* Carrier starts down, phylib will bring it up */
3232 netif_carrier_off(ndev);
3233 fec_enet_clk_enable(ndev, false);
3234 pinctrl_pm_select_sleep_state(&pdev->dev);
3235
3236 ret = register_netdev(ndev);
3237 if (ret)
3238 goto failed_register;
3239
3240 if (fep->bufdesc_ex && fep->ptp_clock)
3241 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3242
3243 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3244 return 0;
3245
3246 failed_register:
3247 fec_enet_mii_remove(fep);
3248 failed_mii_init:
3249 failed_irq:
3250 failed_init:
3251 if (fep->reg_phy)
3252 regulator_disable(fep->reg_phy);
3253 failed_regulator:
3254 fec_enet_clk_enable(ndev, false);
3255 failed_clk:
3256 failed_phy:
3257 of_node_put(phy_node);
3258 failed_ioremap:
3259 free_netdev(ndev);
3260
3261 return ret;
3262 }
3263
3264 static int
3265 fec_drv_remove(struct platform_device *pdev)
3266 {
3267 struct net_device *ndev = platform_get_drvdata(pdev);
3268 struct fec_enet_private *fep = netdev_priv(ndev);
3269
3270 cancel_delayed_work_sync(&fep->time_keep);
3271 cancel_work_sync(&fep->tx_timeout_work);
3272 unregister_netdev(ndev);
3273 fec_enet_mii_remove(fep);
3274 if (fep->reg_phy)
3275 regulator_disable(fep->reg_phy);
3276 if (fep->ptp_clock)
3277 ptp_clock_unregister(fep->ptp_clock);
3278 fec_enet_clk_enable(ndev, false);
3279 of_node_put(fep->phy_node);
3280 free_netdev(ndev);
3281
3282 return 0;
3283 }
3284
3285 static int __maybe_unused fec_suspend(struct device *dev)
3286 {
3287 struct net_device *ndev = dev_get_drvdata(dev);
3288 struct fec_enet_private *fep = netdev_priv(ndev);
3289
3290 rtnl_lock();
3291 if (netif_running(ndev)) {
3292 phy_stop(fep->phy_dev);
3293 napi_disable(&fep->napi);
3294 netif_tx_lock_bh(ndev);
3295 netif_device_detach(ndev);
3296 netif_tx_unlock_bh(ndev);
3297 fec_stop(ndev);
3298 }
3299 rtnl_unlock();
3300
3301 fec_enet_clk_enable(ndev, false);
3302 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3303
3304 if (fep->reg_phy)
3305 regulator_disable(fep->reg_phy);
3306
3307 return 0;
3308 }
3309
3310 static int __maybe_unused fec_resume(struct device *dev)
3311 {
3312 struct net_device *ndev = dev_get_drvdata(dev);
3313 struct fec_enet_private *fep = netdev_priv(ndev);
3314 int ret;
3315
3316 if (fep->reg_phy) {
3317 ret = regulator_enable(fep->reg_phy);
3318 if (ret)
3319 return ret;
3320 }
3321
3322 pinctrl_pm_select_default_state(&fep->pdev->dev);
3323 ret = fec_enet_clk_enable(ndev, true);
3324 if (ret)
3325 goto failed_clk;
3326
3327 rtnl_lock();
3328 if (netif_running(ndev)) {
3329 fec_restart(ndev);
3330 netif_tx_lock_bh(ndev);
3331 netif_device_attach(ndev);
3332 netif_tx_unlock_bh(ndev);
3333 napi_enable(&fep->napi);
3334 phy_start(fep->phy_dev);
3335 }
3336 rtnl_unlock();
3337
3338 return 0;
3339
3340 failed_clk:
3341 if (fep->reg_phy)
3342 regulator_disable(fep->reg_phy);
3343 return ret;
3344 }
3345
3346 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
3347
3348 static struct platform_driver fec_driver = {
3349 .driver = {
3350 .name = DRIVER_NAME,
3351 .owner = THIS_MODULE,
3352 .pm = &fec_pm_ops,
3353 .of_match_table = fec_dt_ids,
3354 },
3355 .id_table = fec_devtype,
3356 .probe = fec_probe,
3357 .remove = fec_drv_remove,
3358 };
3359
3360 module_platform_driver(fec_driver);
3361
3362 MODULE_ALIAS("platform:"DRIVER_NAME);
3363 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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