2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_net.h>
56 #include <linux/regulator/consumer.h>
57 #include <linux/if_vlan.h>
59 #include <asm/cacheflush.h>
63 static void set_multicast_list(struct net_device
*ndev
);
65 #if defined(CONFIG_ARM)
66 #define FEC_ALIGNMENT 0xf
68 #define FEC_ALIGNMENT 0x3
71 #define DRIVER_NAME "fec"
73 /* Pause frame feild and FIFO threshold */
74 #define FEC_ENET_FCE (1 << 5)
75 #define FEC_ENET_RSEM_V 0x84
76 #define FEC_ENET_RSFL_V 16
77 #define FEC_ENET_RAEM_V 0x8
78 #define FEC_ENET_RAFL_V 0x8
79 #define FEC_ENET_OPD_V 0xFFF0
81 /* Controller is ENET-MAC */
82 #define FEC_QUIRK_ENET_MAC (1 << 0)
83 /* Controller needs driver to swap frame */
84 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
85 /* Controller uses gasket */
86 #define FEC_QUIRK_USE_GASKET (1 << 2)
87 /* Controller has GBIT support */
88 #define FEC_QUIRK_HAS_GBIT (1 << 3)
89 /* Controller has extend desc buffer */
90 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
91 /* Controller has hardware checksum support */
92 #define FEC_QUIRK_HAS_CSUM (1 << 5)
93 /* Controller has hardware vlan support */
94 #define FEC_QUIRK_HAS_VLAN (1 << 6)
95 /* ENET IP errata ERR006358
97 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
98 * detected as not set during a prior frame transmission, then the
99 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
100 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
101 * frames not being transmitted until there is a 0-to-1 transition on
104 #define FEC_QUIRK_ERR006358 (1 << 7)
106 static struct platform_device_id fec_devtype
[] = {
108 /* keep it for coldfire */
113 .driver_data
= FEC_QUIRK_USE_GASKET
,
119 .driver_data
= FEC_QUIRK_ENET_MAC
| FEC_QUIRK_SWAP_FRAME
,
122 .driver_data
= FEC_QUIRK_ENET_MAC
| FEC_QUIRK_HAS_GBIT
|
123 FEC_QUIRK_HAS_BUFDESC_EX
| FEC_QUIRK_HAS_CSUM
|
124 FEC_QUIRK_HAS_VLAN
| FEC_QUIRK_ERR006358
,
126 .name
= "mvf600-fec",
127 .driver_data
= FEC_QUIRK_ENET_MAC
,
132 MODULE_DEVICE_TABLE(platform
, fec_devtype
);
135 IMX25_FEC
= 1, /* runs on i.mx25/50/53 */
136 IMX27_FEC
, /* runs on i.mx27/35/51 */
142 static const struct of_device_id fec_dt_ids
[] = {
143 { .compatible
= "fsl,imx25-fec", .data
= &fec_devtype
[IMX25_FEC
], },
144 { .compatible
= "fsl,imx27-fec", .data
= &fec_devtype
[IMX27_FEC
], },
145 { .compatible
= "fsl,imx28-fec", .data
= &fec_devtype
[IMX28_FEC
], },
146 { .compatible
= "fsl,imx6q-fec", .data
= &fec_devtype
[IMX6Q_FEC
], },
147 { .compatible
= "fsl,mvf600-fec", .data
= &fec_devtype
[MVF600_FEC
], },
150 MODULE_DEVICE_TABLE(of
, fec_dt_ids
);
152 static unsigned char macaddr
[ETH_ALEN
];
153 module_param_array(macaddr
, byte
, NULL
, 0);
154 MODULE_PARM_DESC(macaddr
, "FEC Ethernet MAC address");
156 #if defined(CONFIG_M5272)
158 * Some hardware gets it MAC address out of local flash memory.
159 * if this is non-zero then assume it is the address to get MAC from.
161 #if defined(CONFIG_NETtel)
162 #define FEC_FLASHMAC 0xf0006006
163 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
164 #define FEC_FLASHMAC 0xf0006000
165 #elif defined(CONFIG_CANCam)
166 #define FEC_FLASHMAC 0xf0020000
167 #elif defined (CONFIG_M5272C3)
168 #define FEC_FLASHMAC (0xffe04000 + 4)
169 #elif defined(CONFIG_MOD5272)
170 #define FEC_FLASHMAC 0xffc0406b
172 #define FEC_FLASHMAC 0
174 #endif /* CONFIG_M5272 */
176 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
177 #error "FEC: descriptor ring size constants too large"
180 /* Interrupt events/masks. */
181 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
182 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
183 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
184 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
185 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
186 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
187 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
188 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
189 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
190 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
192 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
193 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
195 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
197 #define PKT_MAXBUF_SIZE 1522
198 #define PKT_MINBUF_SIZE 64
199 #define PKT_MAXBLR_SIZE 1536
201 /* FEC receive acceleration */
202 #define FEC_RACC_IPDIS (1 << 1)
203 #define FEC_RACC_PRODIS (1 << 2)
204 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
207 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
208 * size bits. Other FEC hardware does not, so we need to take that into
209 * account when setting it.
211 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
212 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
213 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
215 #define OPT_FRAME_SIZE 0
218 /* FEC MII MMFR bits definition */
219 #define FEC_MMFR_ST (1 << 30)
220 #define FEC_MMFR_OP_READ (2 << 28)
221 #define FEC_MMFR_OP_WRITE (1 << 28)
222 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
223 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
224 #define FEC_MMFR_TA (2 << 16)
225 #define FEC_MMFR_DATA(v) (v & 0xffff)
227 #define FEC_MII_TIMEOUT 30000 /* us */
229 /* Transmitter timeout */
230 #define TX_TIMEOUT (2 * HZ)
232 #define FEC_PAUSE_FLAG_AUTONEG 0x1
233 #define FEC_PAUSE_FLAG_ENABLE 0x2
238 struct bufdesc
*fec_enet_get_nextdesc(struct bufdesc
*bdp
, struct fec_enet_private
*fep
)
240 struct bufdesc
*new_bd
= bdp
+ 1;
241 struct bufdesc_ex
*ex_new_bd
= (struct bufdesc_ex
*)bdp
+ 1;
242 struct bufdesc_ex
*ex_base
;
243 struct bufdesc
*base
;
246 if (bdp
>= fep
->tx_bd_base
) {
247 base
= fep
->tx_bd_base
;
248 ring_size
= fep
->tx_ring_size
;
249 ex_base
= (struct bufdesc_ex
*)fep
->tx_bd_base
;
251 base
= fep
->rx_bd_base
;
252 ring_size
= fep
->rx_ring_size
;
253 ex_base
= (struct bufdesc_ex
*)fep
->rx_bd_base
;
257 return (struct bufdesc
*)((ex_new_bd
>= (ex_base
+ ring_size
)) ?
258 ex_base
: ex_new_bd
);
260 return (new_bd
>= (base
+ ring_size
)) ?
265 struct bufdesc
*fec_enet_get_prevdesc(struct bufdesc
*bdp
, struct fec_enet_private
*fep
)
267 struct bufdesc
*new_bd
= bdp
- 1;
268 struct bufdesc_ex
*ex_new_bd
= (struct bufdesc_ex
*)bdp
- 1;
269 struct bufdesc_ex
*ex_base
;
270 struct bufdesc
*base
;
273 if (bdp
>= fep
->tx_bd_base
) {
274 base
= fep
->tx_bd_base
;
275 ring_size
= fep
->tx_ring_size
;
276 ex_base
= (struct bufdesc_ex
*)fep
->tx_bd_base
;
278 base
= fep
->rx_bd_base
;
279 ring_size
= fep
->rx_ring_size
;
280 ex_base
= (struct bufdesc_ex
*)fep
->rx_bd_base
;
284 return (struct bufdesc
*)((ex_new_bd
< ex_base
) ?
285 (ex_new_bd
+ ring_size
) : ex_new_bd
);
287 return (new_bd
< base
) ? (new_bd
+ ring_size
) : new_bd
;
290 static void *swap_buffer(void *bufaddr
, int len
)
293 unsigned int *buf
= bufaddr
;
295 for (i
= 0; i
< DIV_ROUND_UP(len
, 4); i
++, buf
++)
296 *buf
= cpu_to_be32(*buf
);
302 fec_enet_clear_csum(struct sk_buff
*skb
, struct net_device
*ndev
)
304 /* Only run for packets requiring a checksum. */
305 if (skb
->ip_summed
!= CHECKSUM_PARTIAL
)
308 if (unlikely(skb_cow_head(skb
, 0)))
311 *(__sum16
*)(skb
->head
+ skb
->csum_start
+ skb
->csum_offset
) = 0;
317 fec_enet_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
319 struct fec_enet_private
*fep
= netdev_priv(ndev
);
320 const struct platform_device_id
*id_entry
=
321 platform_get_device_id(fep
->pdev
);
322 struct bufdesc
*bdp
, *bdp_pre
;
324 unsigned short status
;
327 /* Fill in a Tx ring entry */
330 status
= bdp
->cbd_sc
;
332 if (status
& BD_ENET_TX_READY
) {
333 /* Ooops. All transmit buffers are full. Bail out.
334 * This should not happen, since ndev->tbusy should be set.
336 netdev_err(ndev
, "tx queue full!\n");
337 return NETDEV_TX_BUSY
;
340 /* Protocol checksum off-load for TCP and UDP. */
341 if (fec_enet_clear_csum(skb
, ndev
)) {
346 /* Clear all of the status flags */
347 status
&= ~BD_ENET_TX_STATS
;
349 /* Set buffer length and buffer pointer */
351 bdp
->cbd_datlen
= skb
->len
;
354 * On some FEC implementations data must be aligned on
355 * 4-byte boundaries. Use bounce buffers to copy data
356 * and get it aligned. Ugh.
359 index
= (struct bufdesc_ex
*)bdp
-
360 (struct bufdesc_ex
*)fep
->tx_bd_base
;
362 index
= bdp
- fep
->tx_bd_base
;
364 if (((unsigned long) bufaddr
) & FEC_ALIGNMENT
) {
365 memcpy(fep
->tx_bounce
[index
], skb
->data
, skb
->len
);
366 bufaddr
= fep
->tx_bounce
[index
];
370 * Some design made an incorrect assumption on endian mode of
371 * the system that it's running on. As the result, driver has to
372 * swap every frame going to and coming from the controller.
374 if (id_entry
->driver_data
& FEC_QUIRK_SWAP_FRAME
)
375 swap_buffer(bufaddr
, skb
->len
);
377 /* Save skb pointer */
378 fep
->tx_skbuff
[index
] = skb
;
380 /* Push the data cache so the CPM does not get stale memory
383 bdp
->cbd_bufaddr
= dma_map_single(&fep
->pdev
->dev
, bufaddr
,
384 skb
->len
, DMA_TO_DEVICE
);
385 if (dma_mapping_error(&fep
->pdev
->dev
, bdp
->cbd_bufaddr
)) {
386 bdp
->cbd_bufaddr
= 0;
387 fep
->tx_skbuff
[index
] = NULL
;
388 dev_kfree_skb_any(skb
);
390 netdev_err(ndev
, "Tx DMA memory map failed\n");
393 /* Send it on its way. Tell FEC it's ready, interrupt when done,
394 * it's the last BD of the frame, and to put the CRC on the end.
396 status
|= (BD_ENET_TX_READY
| BD_ENET_TX_INTR
397 | BD_ENET_TX_LAST
| BD_ENET_TX_TC
);
398 bdp
->cbd_sc
= status
;
400 if (fep
->bufdesc_ex
) {
402 struct bufdesc_ex
*ebdp
= (struct bufdesc_ex
*)bdp
;
404 if (unlikely(skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
&&
406 ebdp
->cbd_esc
= (BD_ENET_TX_TS
| BD_ENET_TX_INT
);
407 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
409 ebdp
->cbd_esc
= BD_ENET_TX_INT
;
411 /* Enable protocol checksum flags
412 * We do not bother with the IP Checksum bits as they
413 * are done by the kernel
415 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
416 ebdp
->cbd_esc
|= BD_ENET_TX_PINS
;
420 bdp_pre
= fec_enet_get_prevdesc(bdp
, fep
);
421 if ((id_entry
->driver_data
& FEC_QUIRK_ERR006358
) &&
422 !(bdp_pre
->cbd_sc
& BD_ENET_TX_READY
)) {
423 fep
->delay_work
.trig_tx
= true;
424 schedule_delayed_work(&(fep
->delay_work
.delay_work
),
425 msecs_to_jiffies(1));
428 /* If this was the last BD in the ring, start at the beginning again. */
429 bdp
= fec_enet_get_nextdesc(bdp
, fep
);
431 skb_tx_timestamp(skb
);
435 if (fep
->cur_tx
== fep
->dirty_tx
)
436 netif_stop_queue(ndev
);
438 /* Trigger transmission start */
439 writel(0, fep
->hwp
+ FEC_X_DES_ACTIVE
);
444 /* Init RX & TX buffer descriptors
446 static void fec_enet_bd_init(struct net_device
*dev
)
448 struct fec_enet_private
*fep
= netdev_priv(dev
);
452 /* Initialize the receive buffer descriptors. */
453 bdp
= fep
->rx_bd_base
;
454 for (i
= 0; i
< fep
->rx_ring_size
; i
++) {
456 /* Initialize the BD for every fragment in the page. */
457 if (bdp
->cbd_bufaddr
)
458 bdp
->cbd_sc
= BD_ENET_RX_EMPTY
;
461 bdp
= fec_enet_get_nextdesc(bdp
, fep
);
464 /* Set the last buffer to wrap */
465 bdp
= fec_enet_get_prevdesc(bdp
, fep
);
466 bdp
->cbd_sc
|= BD_SC_WRAP
;
468 fep
->cur_rx
= fep
->rx_bd_base
;
470 /* ...and the same for transmit */
471 bdp
= fep
->tx_bd_base
;
473 for (i
= 0; i
< fep
->tx_ring_size
; i
++) {
475 /* Initialize the BD for every fragment in the page. */
477 if (bdp
->cbd_bufaddr
&& fep
->tx_skbuff
[i
]) {
478 dev_kfree_skb_any(fep
->tx_skbuff
[i
]);
479 fep
->tx_skbuff
[i
] = NULL
;
481 bdp
->cbd_bufaddr
= 0;
482 bdp
= fec_enet_get_nextdesc(bdp
, fep
);
485 /* Set the last buffer to wrap */
486 bdp
= fec_enet_get_prevdesc(bdp
, fep
);
487 bdp
->cbd_sc
|= BD_SC_WRAP
;
491 /* This function is called to start or restart the FEC during a link
492 * change. This only happens when switching between half and full
496 fec_restart(struct net_device
*ndev
, int duplex
)
498 struct fec_enet_private
*fep
= netdev_priv(ndev
);
499 const struct platform_device_id
*id_entry
=
500 platform_get_device_id(fep
->pdev
);
504 u32 rcntl
= OPT_FRAME_SIZE
| 0x04;
505 u32 ecntl
= 0x2; /* ETHEREN */
507 if (netif_running(ndev
)) {
508 netif_device_detach(ndev
);
509 napi_disable(&fep
->napi
);
510 netif_stop_queue(ndev
);
511 netif_tx_lock_bh(ndev
);
514 /* Whack a reset. We should wait for this. */
515 writel(1, fep
->hwp
+ FEC_ECNTRL
);
519 * enet-mac reset will reset mac address registers too,
520 * so need to reconfigure it.
522 if (id_entry
->driver_data
& FEC_QUIRK_ENET_MAC
) {
523 memcpy(&temp_mac
, ndev
->dev_addr
, ETH_ALEN
);
524 writel(cpu_to_be32(temp_mac
[0]), fep
->hwp
+ FEC_ADDR_LOW
);
525 writel(cpu_to_be32(temp_mac
[1]), fep
->hwp
+ FEC_ADDR_HIGH
);
528 /* Clear any outstanding interrupt. */
529 writel(0xffc00000, fep
->hwp
+ FEC_IEVENT
);
531 /* Setup multicast filter. */
532 set_multicast_list(ndev
);
534 writel(0, fep
->hwp
+ FEC_HASH_TABLE_HIGH
);
535 writel(0, fep
->hwp
+ FEC_HASH_TABLE_LOW
);
538 /* Set maximum receive buffer size. */
539 writel(PKT_MAXBLR_SIZE
, fep
->hwp
+ FEC_R_BUFF_SIZE
);
541 fec_enet_bd_init(ndev
);
543 /* Set receive and transmit descriptor base. */
544 writel(fep
->bd_dma
, fep
->hwp
+ FEC_R_DES_START
);
546 writel((unsigned long)fep
->bd_dma
+ sizeof(struct bufdesc_ex
)
547 * fep
->rx_ring_size
, fep
->hwp
+ FEC_X_DES_START
);
549 writel((unsigned long)fep
->bd_dma
+ sizeof(struct bufdesc
)
550 * fep
->rx_ring_size
, fep
->hwp
+ FEC_X_DES_START
);
553 for (i
= 0; i
<= TX_RING_MOD_MASK
; i
++) {
554 if (fep
->tx_skbuff
[i
]) {
555 dev_kfree_skb_any(fep
->tx_skbuff
[i
]);
556 fep
->tx_skbuff
[i
] = NULL
;
560 /* Enable MII mode */
563 writel(0x04, fep
->hwp
+ FEC_X_CNTRL
);
567 writel(0x0, fep
->hwp
+ FEC_X_CNTRL
);
570 fep
->full_duplex
= duplex
;
573 writel(fep
->phy_speed
, fep
->hwp
+ FEC_MII_SPEED
);
575 #if !defined(CONFIG_M5272)
576 /* set RX checksum */
577 val
= readl(fep
->hwp
+ FEC_RACC
);
578 if (fep
->csum_flags
& FLAG_RX_CSUM_ENABLED
)
579 val
|= FEC_RACC_OPTIONS
;
581 val
&= ~FEC_RACC_OPTIONS
;
582 writel(val
, fep
->hwp
+ FEC_RACC
);
586 * The phy interface and speed need to get configured
587 * differently on enet-mac.
589 if (id_entry
->driver_data
& FEC_QUIRK_ENET_MAC
) {
590 /* Enable flow control and length check */
591 rcntl
|= 0x40000000 | 0x00000020;
593 /* RGMII, RMII or MII */
594 if (fep
->phy_interface
== PHY_INTERFACE_MODE_RGMII
)
596 else if (fep
->phy_interface
== PHY_INTERFACE_MODE_RMII
)
601 /* 1G, 100M or 10M */
603 if (fep
->phy_dev
->speed
== SPEED_1000
)
605 else if (fep
->phy_dev
->speed
== SPEED_100
)
611 #ifdef FEC_MIIGSK_ENR
612 if (id_entry
->driver_data
& FEC_QUIRK_USE_GASKET
) {
614 /* disable the gasket and wait */
615 writel(0, fep
->hwp
+ FEC_MIIGSK_ENR
);
616 while (readl(fep
->hwp
+ FEC_MIIGSK_ENR
) & 4)
620 * configure the gasket:
621 * RMII, 50 MHz, no loopback, no echo
622 * MII, 25 MHz, no loopback, no echo
624 cfgr
= (fep
->phy_interface
== PHY_INTERFACE_MODE_RMII
)
625 ? BM_MIIGSK_CFGR_RMII
: BM_MIIGSK_CFGR_MII
;
626 if (fep
->phy_dev
&& fep
->phy_dev
->speed
== SPEED_10
)
627 cfgr
|= BM_MIIGSK_CFGR_FRCONT_10M
;
628 writel(cfgr
, fep
->hwp
+ FEC_MIIGSK_CFGR
);
630 /* re-enable the gasket */
631 writel(2, fep
->hwp
+ FEC_MIIGSK_ENR
);
636 #if !defined(CONFIG_M5272)
637 /* enable pause frame*/
638 if ((fep
->pause_flag
& FEC_PAUSE_FLAG_ENABLE
) ||
639 ((fep
->pause_flag
& FEC_PAUSE_FLAG_AUTONEG
) &&
640 fep
->phy_dev
&& fep
->phy_dev
->pause
)) {
641 rcntl
|= FEC_ENET_FCE
;
643 /* set FIFO threshold parameter to reduce overrun */
644 writel(FEC_ENET_RSEM_V
, fep
->hwp
+ FEC_R_FIFO_RSEM
);
645 writel(FEC_ENET_RSFL_V
, fep
->hwp
+ FEC_R_FIFO_RSFL
);
646 writel(FEC_ENET_RAEM_V
, fep
->hwp
+ FEC_R_FIFO_RAEM
);
647 writel(FEC_ENET_RAFL_V
, fep
->hwp
+ FEC_R_FIFO_RAFL
);
650 writel(FEC_ENET_OPD_V
, fep
->hwp
+ FEC_OPD
);
652 rcntl
&= ~FEC_ENET_FCE
;
654 #endif /* !defined(CONFIG_M5272) */
656 writel(rcntl
, fep
->hwp
+ FEC_R_CNTRL
);
658 if (id_entry
->driver_data
& FEC_QUIRK_ENET_MAC
) {
659 /* enable ENET endian swap */
661 /* enable ENET store and forward mode */
662 writel(1 << 8, fep
->hwp
+ FEC_X_WMRK
);
669 /* Enable the MIB statistic event counters */
670 writel(0 << 31, fep
->hwp
+ FEC_MIB_CTRLSTAT
);
673 /* And last, enable the transmit and receive processing */
674 writel(ecntl
, fep
->hwp
+ FEC_ECNTRL
);
675 writel(0, fep
->hwp
+ FEC_R_DES_ACTIVE
);
678 fec_ptp_start_cyclecounter(ndev
);
680 /* Enable interrupts we wish to service */
681 writel(FEC_DEFAULT_IMASK
, fep
->hwp
+ FEC_IMASK
);
683 if (netif_running(ndev
)) {
684 netif_tx_unlock_bh(ndev
);
685 netif_wake_queue(ndev
);
686 napi_enable(&fep
->napi
);
687 netif_device_attach(ndev
);
692 fec_stop(struct net_device
*ndev
)
694 struct fec_enet_private
*fep
= netdev_priv(ndev
);
695 const struct platform_device_id
*id_entry
=
696 platform_get_device_id(fep
->pdev
);
697 u32 rmii_mode
= readl(fep
->hwp
+ FEC_R_CNTRL
) & (1 << 8);
699 /* We cannot expect a graceful transmit stop without link !!! */
701 writel(1, fep
->hwp
+ FEC_X_CNTRL
); /* Graceful transmit stop */
703 if (!(readl(fep
->hwp
+ FEC_IEVENT
) & FEC_ENET_GRA
))
704 netdev_err(ndev
, "Graceful transmit stop did not complete!\n");
707 /* Whack a reset. We should wait for this. */
708 writel(1, fep
->hwp
+ FEC_ECNTRL
);
710 writel(fep
->phy_speed
, fep
->hwp
+ FEC_MII_SPEED
);
711 writel(FEC_DEFAULT_IMASK
, fep
->hwp
+ FEC_IMASK
);
713 /* We have to keep ENET enabled to have MII interrupt stay working */
714 if (id_entry
->driver_data
& FEC_QUIRK_ENET_MAC
) {
715 writel(2, fep
->hwp
+ FEC_ECNTRL
);
716 writel(rmii_mode
, fep
->hwp
+ FEC_R_CNTRL
);
722 fec_timeout(struct net_device
*ndev
)
724 struct fec_enet_private
*fep
= netdev_priv(ndev
);
726 ndev
->stats
.tx_errors
++;
728 fep
->delay_work
.timeout
= true;
729 schedule_delayed_work(&(fep
->delay_work
.delay_work
), 0);
732 static void fec_enet_work(struct work_struct
*work
)
734 struct fec_enet_private
*fep
=
736 struct fec_enet_private
,
737 delay_work
.delay_work
.work
);
739 if (fep
->delay_work
.timeout
) {
740 fep
->delay_work
.timeout
= false;
741 fec_restart(fep
->netdev
, fep
->full_duplex
);
742 netif_wake_queue(fep
->netdev
);
745 if (fep
->delay_work
.trig_tx
) {
746 fep
->delay_work
.trig_tx
= false;
747 writel(0, fep
->hwp
+ FEC_X_DES_ACTIVE
);
752 fec_enet_tx(struct net_device
*ndev
)
754 struct fec_enet_private
*fep
;
756 unsigned short status
;
760 fep
= netdev_priv(ndev
);
763 /* get next bdp of dirty_tx */
764 bdp
= fec_enet_get_nextdesc(bdp
, fep
);
766 while (((status
= bdp
->cbd_sc
) & BD_ENET_TX_READY
) == 0) {
768 /* current queue is empty */
769 if (bdp
== fep
->cur_tx
)
773 index
= (struct bufdesc_ex
*)bdp
-
774 (struct bufdesc_ex
*)fep
->tx_bd_base
;
776 index
= bdp
- fep
->tx_bd_base
;
778 skb
= fep
->tx_skbuff
[index
];
779 dma_unmap_single(&fep
->pdev
->dev
, bdp
->cbd_bufaddr
, skb
->len
,
781 bdp
->cbd_bufaddr
= 0;
783 /* Check for errors. */
784 if (status
& (BD_ENET_TX_HB
| BD_ENET_TX_LC
|
785 BD_ENET_TX_RL
| BD_ENET_TX_UN
|
787 ndev
->stats
.tx_errors
++;
788 if (status
& BD_ENET_TX_HB
) /* No heartbeat */
789 ndev
->stats
.tx_heartbeat_errors
++;
790 if (status
& BD_ENET_TX_LC
) /* Late collision */
791 ndev
->stats
.tx_window_errors
++;
792 if (status
& BD_ENET_TX_RL
) /* Retrans limit */
793 ndev
->stats
.tx_aborted_errors
++;
794 if (status
& BD_ENET_TX_UN
) /* Underrun */
795 ndev
->stats
.tx_fifo_errors
++;
796 if (status
& BD_ENET_TX_CSL
) /* Carrier lost */
797 ndev
->stats
.tx_carrier_errors
++;
799 ndev
->stats
.tx_packets
++;
800 ndev
->stats
.tx_bytes
+= bdp
->cbd_datlen
;
803 if (unlikely(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
) &&
805 struct skb_shared_hwtstamps shhwtstamps
;
807 struct bufdesc_ex
*ebdp
= (struct bufdesc_ex
*)bdp
;
809 memset(&shhwtstamps
, 0, sizeof(shhwtstamps
));
810 spin_lock_irqsave(&fep
->tmreg_lock
, flags
);
811 shhwtstamps
.hwtstamp
= ns_to_ktime(
812 timecounter_cyc2time(&fep
->tc
, ebdp
->ts
));
813 spin_unlock_irqrestore(&fep
->tmreg_lock
, flags
);
814 skb_tstamp_tx(skb
, &shhwtstamps
);
817 if (status
& BD_ENET_TX_READY
)
818 netdev_err(ndev
, "HEY! Enet xmit interrupt and TX_READY\n");
820 /* Deferred means some collisions occurred during transmit,
821 * but we eventually sent the packet OK.
823 if (status
& BD_ENET_TX_DEF
)
824 ndev
->stats
.collisions
++;
826 /* Free the sk buffer associated with this last transmit */
827 dev_kfree_skb_any(skb
);
828 fep
->tx_skbuff
[index
] = NULL
;
832 /* Update pointer to next buffer descriptor to be transmitted */
833 bdp
= fec_enet_get_nextdesc(bdp
, fep
);
835 /* Since we have freed up a buffer, the ring is no longer full
837 if (fep
->dirty_tx
!= fep
->cur_tx
) {
838 if (netif_queue_stopped(ndev
))
839 netif_wake_queue(ndev
);
846 /* During a receive, the cur_rx points to the current incoming buffer.
847 * When we update through the ring, if the next incoming buffer has
848 * not been given to the system, we just set the empty indicator,
849 * effectively tossing the packet.
852 fec_enet_rx(struct net_device
*ndev
, int budget
)
854 struct fec_enet_private
*fep
= netdev_priv(ndev
);
855 const struct platform_device_id
*id_entry
=
856 platform_get_device_id(fep
->pdev
);
858 unsigned short status
;
862 int pkt_received
= 0;
863 struct bufdesc_ex
*ebdp
= NULL
;
864 bool vlan_packet_rcvd
= false;
872 /* First, grab all of the stats for the incoming packet.
873 * These get messed up if we get called due to a busy condition.
877 while (!((status
= bdp
->cbd_sc
) & BD_ENET_RX_EMPTY
)) {
879 if (pkt_received
>= budget
)
883 /* Since we have allocated space to hold a complete frame,
884 * the last indicator should be set.
886 if ((status
& BD_ENET_RX_LAST
) == 0)
887 netdev_err(ndev
, "rcv is not +last\n");
890 goto rx_processing_done
;
892 /* Check for errors. */
893 if (status
& (BD_ENET_RX_LG
| BD_ENET_RX_SH
| BD_ENET_RX_NO
|
894 BD_ENET_RX_CR
| BD_ENET_RX_OV
)) {
895 ndev
->stats
.rx_errors
++;
896 if (status
& (BD_ENET_RX_LG
| BD_ENET_RX_SH
)) {
897 /* Frame too long or too short. */
898 ndev
->stats
.rx_length_errors
++;
900 if (status
& BD_ENET_RX_NO
) /* Frame alignment */
901 ndev
->stats
.rx_frame_errors
++;
902 if (status
& BD_ENET_RX_CR
) /* CRC Error */
903 ndev
->stats
.rx_crc_errors
++;
904 if (status
& BD_ENET_RX_OV
) /* FIFO overrun */
905 ndev
->stats
.rx_fifo_errors
++;
908 /* Report late collisions as a frame error.
909 * On this error, the BD is closed, but we don't know what we
910 * have in the buffer. So, just drop this frame on the floor.
912 if (status
& BD_ENET_RX_CL
) {
913 ndev
->stats
.rx_errors
++;
914 ndev
->stats
.rx_frame_errors
++;
915 goto rx_processing_done
;
918 /* Process the incoming frame. */
919 ndev
->stats
.rx_packets
++;
920 pkt_len
= bdp
->cbd_datlen
;
921 ndev
->stats
.rx_bytes
+= pkt_len
;
924 index
= (struct bufdesc_ex
*)bdp
-
925 (struct bufdesc_ex
*)fep
->rx_bd_base
;
927 index
= bdp
- fep
->rx_bd_base
;
928 data
= fep
->rx_skbuff
[index
]->data
;
929 dma_sync_single_for_cpu(&fep
->pdev
->dev
, bdp
->cbd_bufaddr
,
930 FEC_ENET_RX_FRSIZE
, DMA_FROM_DEVICE
);
932 if (id_entry
->driver_data
& FEC_QUIRK_SWAP_FRAME
)
933 swap_buffer(data
, pkt_len
);
935 /* Extract the enhanced buffer descriptor */
938 ebdp
= (struct bufdesc_ex
*)bdp
;
940 /* If this is a VLAN packet remove the VLAN Tag */
941 vlan_packet_rcvd
= false;
942 if ((ndev
->features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
943 fep
->bufdesc_ex
&& (ebdp
->cbd_esc
& BD_ENET_RX_VLAN
)) {
944 /* Push and remove the vlan tag */
945 struct vlan_hdr
*vlan_header
=
946 (struct vlan_hdr
*) (data
+ ETH_HLEN
);
947 vlan_tag
= ntohs(vlan_header
->h_vlan_TCI
);
948 pkt_len
-= VLAN_HLEN
;
950 vlan_packet_rcvd
= true;
953 /* This does 16 byte alignment, exactly what we need.
954 * The packet length includes FCS, but we don't want to
955 * include that when passing upstream as it messes up
956 * bridging applications.
958 skb
= netdev_alloc_skb(ndev
, pkt_len
- 4 + NET_IP_ALIGN
);
960 if (unlikely(!skb
)) {
961 ndev
->stats
.rx_dropped
++;
963 int payload_offset
= (2 * ETH_ALEN
);
964 skb_reserve(skb
, NET_IP_ALIGN
);
965 skb_put(skb
, pkt_len
- 4); /* Make room */
967 /* Extract the frame data without the VLAN header. */
968 skb_copy_to_linear_data(skb
, data
, (2 * ETH_ALEN
));
969 if (vlan_packet_rcvd
)
970 payload_offset
= (2 * ETH_ALEN
) + VLAN_HLEN
;
971 skb_copy_to_linear_data_offset(skb
, (2 * ETH_ALEN
),
972 data
+ payload_offset
,
973 pkt_len
- 4 - (2 * ETH_ALEN
));
975 skb
->protocol
= eth_type_trans(skb
, ndev
);
977 /* Get receive timestamp from the skb */
978 if (fep
->hwts_rx_en
&& fep
->bufdesc_ex
) {
979 struct skb_shared_hwtstamps
*shhwtstamps
=
983 memset(shhwtstamps
, 0, sizeof(*shhwtstamps
));
985 spin_lock_irqsave(&fep
->tmreg_lock
, flags
);
986 shhwtstamps
->hwtstamp
= ns_to_ktime(
987 timecounter_cyc2time(&fep
->tc
, ebdp
->ts
));
988 spin_unlock_irqrestore(&fep
->tmreg_lock
, flags
);
991 if (fep
->bufdesc_ex
&&
992 (fep
->csum_flags
& FLAG_RX_CSUM_ENABLED
)) {
993 if (!(ebdp
->cbd_esc
& FLAG_RX_CSUM_ERROR
)) {
995 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
997 skb_checksum_none_assert(skb
);
1001 /* Handle received VLAN packets */
1002 if (vlan_packet_rcvd
)
1003 __vlan_hwaccel_put_tag(skb
,
1007 napi_gro_receive(&fep
->napi
, skb
);
1010 dma_sync_single_for_device(&fep
->pdev
->dev
, bdp
->cbd_bufaddr
,
1011 FEC_ENET_RX_FRSIZE
, DMA_FROM_DEVICE
);
1013 /* Clear the status flags for this buffer */
1014 status
&= ~BD_ENET_RX_STATS
;
1016 /* Mark the buffer empty */
1017 status
|= BD_ENET_RX_EMPTY
;
1018 bdp
->cbd_sc
= status
;
1020 if (fep
->bufdesc_ex
) {
1021 struct bufdesc_ex
*ebdp
= (struct bufdesc_ex
*)bdp
;
1023 ebdp
->cbd_esc
= BD_ENET_RX_INT
;
1028 /* Update BD pointer to next entry */
1029 bdp
= fec_enet_get_nextdesc(bdp
, fep
);
1031 /* Doing this here will keep the FEC running while we process
1032 * incoming frames. On a heavily loaded network, we should be
1033 * able to keep up at the expense of system resources.
1035 writel(0, fep
->hwp
+ FEC_R_DES_ACTIVE
);
1039 return pkt_received
;
1043 fec_enet_interrupt(int irq
, void *dev_id
)
1045 struct net_device
*ndev
= dev_id
;
1046 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1048 irqreturn_t ret
= IRQ_NONE
;
1051 int_events
= readl(fep
->hwp
+ FEC_IEVENT
);
1052 writel(int_events
, fep
->hwp
+ FEC_IEVENT
);
1054 if (int_events
& (FEC_ENET_RXF
| FEC_ENET_TXF
)) {
1057 /* Disable the RX interrupt */
1058 if (napi_schedule_prep(&fep
->napi
)) {
1059 writel(FEC_RX_DISABLED_IMASK
,
1060 fep
->hwp
+ FEC_IMASK
);
1061 __napi_schedule(&fep
->napi
);
1065 if (int_events
& FEC_ENET_MII
) {
1067 complete(&fep
->mdio_done
);
1069 } while (int_events
);
1074 static int fec_enet_rx_napi(struct napi_struct
*napi
, int budget
)
1076 struct net_device
*ndev
= napi
->dev
;
1077 int pkts
= fec_enet_rx(ndev
, budget
);
1078 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1082 if (pkts
< budget
) {
1083 napi_complete(napi
);
1084 writel(FEC_DEFAULT_IMASK
, fep
->hwp
+ FEC_IMASK
);
1089 /* ------------------------------------------------------------------------- */
1090 static void fec_get_mac(struct net_device
*ndev
)
1092 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1093 struct fec_platform_data
*pdata
= dev_get_platdata(&fep
->pdev
->dev
);
1094 unsigned char *iap
, tmpaddr
[ETH_ALEN
];
1097 * try to get mac address in following order:
1099 * 1) module parameter via kernel command line in form
1100 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1105 * 2) from device tree data
1107 if (!is_valid_ether_addr(iap
)) {
1108 struct device_node
*np
= fep
->pdev
->dev
.of_node
;
1110 const char *mac
= of_get_mac_address(np
);
1112 iap
= (unsigned char *) mac
;
1117 * 3) from flash or fuse (via platform data)
1119 if (!is_valid_ether_addr(iap
)) {
1122 iap
= (unsigned char *)FEC_FLASHMAC
;
1125 iap
= (unsigned char *)&pdata
->mac
;
1130 * 4) FEC mac registers set by bootloader
1132 if (!is_valid_ether_addr(iap
)) {
1133 *((__be32
*) &tmpaddr
[0]) =
1134 cpu_to_be32(readl(fep
->hwp
+ FEC_ADDR_LOW
));
1135 *((__be16
*) &tmpaddr
[4]) =
1136 cpu_to_be16(readl(fep
->hwp
+ FEC_ADDR_HIGH
) >> 16);
1141 * 5) random mac address
1143 if (!is_valid_ether_addr(iap
)) {
1144 /* Report it and use a random ethernet address instead */
1145 netdev_err(ndev
, "Invalid MAC address: %pM\n", iap
);
1146 eth_hw_addr_random(ndev
);
1147 netdev_info(ndev
, "Using random MAC address: %pM\n",
1152 memcpy(ndev
->dev_addr
, iap
, ETH_ALEN
);
1154 /* Adjust MAC if using macaddr */
1156 ndev
->dev_addr
[ETH_ALEN
-1] = macaddr
[ETH_ALEN
-1] + fep
->dev_id
;
1159 /* ------------------------------------------------------------------------- */
1164 static void fec_enet_adjust_link(struct net_device
*ndev
)
1166 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1167 struct phy_device
*phy_dev
= fep
->phy_dev
;
1168 int status_change
= 0;
1170 /* Prevent a state halted on mii error */
1171 if (fep
->mii_timeout
&& phy_dev
->state
== PHY_HALTED
) {
1172 phy_dev
->state
= PHY_RESUMING
;
1176 if (phy_dev
->link
) {
1178 fep
->link
= phy_dev
->link
;
1182 if (fep
->full_duplex
!= phy_dev
->duplex
)
1185 if (phy_dev
->speed
!= fep
->speed
) {
1186 fep
->speed
= phy_dev
->speed
;
1190 /* if any of the above changed restart the FEC */
1192 fec_restart(ndev
, phy_dev
->duplex
);
1196 fep
->link
= phy_dev
->link
;
1202 phy_print_status(phy_dev
);
1205 static int fec_enet_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
1207 struct fec_enet_private
*fep
= bus
->priv
;
1208 unsigned long time_left
;
1210 fep
->mii_timeout
= 0;
1211 init_completion(&fep
->mdio_done
);
1213 /* start a read op */
1214 writel(FEC_MMFR_ST
| FEC_MMFR_OP_READ
|
1215 FEC_MMFR_PA(mii_id
) | FEC_MMFR_RA(regnum
) |
1216 FEC_MMFR_TA
, fep
->hwp
+ FEC_MII_DATA
);
1218 /* wait for end of transfer */
1219 time_left
= wait_for_completion_timeout(&fep
->mdio_done
,
1220 usecs_to_jiffies(FEC_MII_TIMEOUT
));
1221 if (time_left
== 0) {
1222 fep
->mii_timeout
= 1;
1223 netdev_err(fep
->netdev
, "MDIO read timeout\n");
1228 return FEC_MMFR_DATA(readl(fep
->hwp
+ FEC_MII_DATA
));
1231 static int fec_enet_mdio_write(struct mii_bus
*bus
, int mii_id
, int regnum
,
1234 struct fec_enet_private
*fep
= bus
->priv
;
1235 unsigned long time_left
;
1237 fep
->mii_timeout
= 0;
1238 init_completion(&fep
->mdio_done
);
1240 /* start a write op */
1241 writel(FEC_MMFR_ST
| FEC_MMFR_OP_WRITE
|
1242 FEC_MMFR_PA(mii_id
) | FEC_MMFR_RA(regnum
) |
1243 FEC_MMFR_TA
| FEC_MMFR_DATA(value
),
1244 fep
->hwp
+ FEC_MII_DATA
);
1246 /* wait for end of transfer */
1247 time_left
= wait_for_completion_timeout(&fep
->mdio_done
,
1248 usecs_to_jiffies(FEC_MII_TIMEOUT
));
1249 if (time_left
== 0) {
1250 fep
->mii_timeout
= 1;
1251 netdev_err(fep
->netdev
, "MDIO write timeout\n");
1258 static int fec_enet_mdio_reset(struct mii_bus
*bus
)
1263 static int fec_enet_mii_probe(struct net_device
*ndev
)
1265 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1266 const struct platform_device_id
*id_entry
=
1267 platform_get_device_id(fep
->pdev
);
1268 struct phy_device
*phy_dev
= NULL
;
1269 char mdio_bus_id
[MII_BUS_ID_SIZE
];
1270 char phy_name
[MII_BUS_ID_SIZE
+ 3];
1272 int dev_id
= fep
->dev_id
;
1274 fep
->phy_dev
= NULL
;
1276 /* check for attached phy */
1277 for (phy_id
= 0; (phy_id
< PHY_MAX_ADDR
); phy_id
++) {
1278 if ((fep
->mii_bus
->phy_mask
& (1 << phy_id
)))
1280 if (fep
->mii_bus
->phy_map
[phy_id
] == NULL
)
1282 if (fep
->mii_bus
->phy_map
[phy_id
]->phy_id
== 0)
1286 strncpy(mdio_bus_id
, fep
->mii_bus
->id
, MII_BUS_ID_SIZE
);
1290 if (phy_id
>= PHY_MAX_ADDR
) {
1291 netdev_info(ndev
, "no PHY, assuming direct connection to switch\n");
1292 strncpy(mdio_bus_id
, "fixed-0", MII_BUS_ID_SIZE
);
1296 snprintf(phy_name
, sizeof(phy_name
), PHY_ID_FMT
, mdio_bus_id
, phy_id
);
1297 phy_dev
= phy_connect(ndev
, phy_name
, &fec_enet_adjust_link
,
1298 fep
->phy_interface
);
1299 if (IS_ERR(phy_dev
)) {
1300 netdev_err(ndev
, "could not attach to PHY\n");
1301 return PTR_ERR(phy_dev
);
1304 /* mask with MAC supported features */
1305 if (id_entry
->driver_data
& FEC_QUIRK_HAS_GBIT
) {
1306 phy_dev
->supported
&= PHY_GBIT_FEATURES
;
1307 #if !defined(CONFIG_M5272)
1308 phy_dev
->supported
|= SUPPORTED_Pause
;
1312 phy_dev
->supported
&= PHY_BASIC_FEATURES
;
1314 phy_dev
->advertising
= phy_dev
->supported
;
1316 fep
->phy_dev
= phy_dev
;
1318 fep
->full_duplex
= 0;
1320 netdev_info(ndev
, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1321 fep
->phy_dev
->drv
->name
, dev_name(&fep
->phy_dev
->dev
),
1327 static int fec_enet_mii_init(struct platform_device
*pdev
)
1329 static struct mii_bus
*fec0_mii_bus
;
1330 struct net_device
*ndev
= platform_get_drvdata(pdev
);
1331 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1332 const struct platform_device_id
*id_entry
=
1333 platform_get_device_id(fep
->pdev
);
1334 int err
= -ENXIO
, i
;
1337 * The dual fec interfaces are not equivalent with enet-mac.
1338 * Here are the differences:
1340 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1341 * - fec0 acts as the 1588 time master while fec1 is slave
1342 * - external phys can only be configured by fec0
1344 * That is to say fec1 can not work independently. It only works
1345 * when fec0 is working. The reason behind this design is that the
1346 * second interface is added primarily for Switch mode.
1348 * Because of the last point above, both phys are attached on fec0
1349 * mdio interface in board design, and need to be configured by
1352 if ((id_entry
->driver_data
& FEC_QUIRK_ENET_MAC
) && fep
->dev_id
> 0) {
1353 /* fec1 uses fec0 mii_bus */
1354 if (mii_cnt
&& fec0_mii_bus
) {
1355 fep
->mii_bus
= fec0_mii_bus
;
1362 fep
->mii_timeout
= 0;
1365 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1367 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1368 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1369 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1372 fep
->phy_speed
= DIV_ROUND_UP(clk_get_rate(fep
->clk_ahb
), 5000000);
1373 if (id_entry
->driver_data
& FEC_QUIRK_ENET_MAC
)
1375 fep
->phy_speed
<<= 1;
1376 writel(fep
->phy_speed
, fep
->hwp
+ FEC_MII_SPEED
);
1378 fep
->mii_bus
= mdiobus_alloc();
1379 if (fep
->mii_bus
== NULL
) {
1384 fep
->mii_bus
->name
= "fec_enet_mii_bus";
1385 fep
->mii_bus
->read
= fec_enet_mdio_read
;
1386 fep
->mii_bus
->write
= fec_enet_mdio_write
;
1387 fep
->mii_bus
->reset
= fec_enet_mdio_reset
;
1388 snprintf(fep
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-%x",
1389 pdev
->name
, fep
->dev_id
+ 1);
1390 fep
->mii_bus
->priv
= fep
;
1391 fep
->mii_bus
->parent
= &pdev
->dev
;
1393 fep
->mii_bus
->irq
= kmalloc(sizeof(int) * PHY_MAX_ADDR
, GFP_KERNEL
);
1394 if (!fep
->mii_bus
->irq
) {
1396 goto err_out_free_mdiobus
;
1399 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1400 fep
->mii_bus
->irq
[i
] = PHY_POLL
;
1402 if (mdiobus_register(fep
->mii_bus
))
1403 goto err_out_free_mdio_irq
;
1407 /* save fec0 mii_bus */
1408 if (id_entry
->driver_data
& FEC_QUIRK_ENET_MAC
)
1409 fec0_mii_bus
= fep
->mii_bus
;
1413 err_out_free_mdio_irq
:
1414 kfree(fep
->mii_bus
->irq
);
1415 err_out_free_mdiobus
:
1416 mdiobus_free(fep
->mii_bus
);
1421 static void fec_enet_mii_remove(struct fec_enet_private
*fep
)
1423 if (--mii_cnt
== 0) {
1424 mdiobus_unregister(fep
->mii_bus
);
1425 kfree(fep
->mii_bus
->irq
);
1426 mdiobus_free(fep
->mii_bus
);
1430 static int fec_enet_get_settings(struct net_device
*ndev
,
1431 struct ethtool_cmd
*cmd
)
1433 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1434 struct phy_device
*phydev
= fep
->phy_dev
;
1439 return phy_ethtool_gset(phydev
, cmd
);
1442 static int fec_enet_set_settings(struct net_device
*ndev
,
1443 struct ethtool_cmd
*cmd
)
1445 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1446 struct phy_device
*phydev
= fep
->phy_dev
;
1451 return phy_ethtool_sset(phydev
, cmd
);
1454 static void fec_enet_get_drvinfo(struct net_device
*ndev
,
1455 struct ethtool_drvinfo
*info
)
1457 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1459 strlcpy(info
->driver
, fep
->pdev
->dev
.driver
->name
,
1460 sizeof(info
->driver
));
1461 strlcpy(info
->version
, "Revision: 1.0", sizeof(info
->version
));
1462 strlcpy(info
->bus_info
, dev_name(&ndev
->dev
), sizeof(info
->bus_info
));
1465 static int fec_enet_get_ts_info(struct net_device
*ndev
,
1466 struct ethtool_ts_info
*info
)
1468 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1470 if (fep
->bufdesc_ex
) {
1472 info
->so_timestamping
= SOF_TIMESTAMPING_TX_SOFTWARE
|
1473 SOF_TIMESTAMPING_RX_SOFTWARE
|
1474 SOF_TIMESTAMPING_SOFTWARE
|
1475 SOF_TIMESTAMPING_TX_HARDWARE
|
1476 SOF_TIMESTAMPING_RX_HARDWARE
|
1477 SOF_TIMESTAMPING_RAW_HARDWARE
;
1479 info
->phc_index
= ptp_clock_index(fep
->ptp_clock
);
1481 info
->phc_index
= -1;
1483 info
->tx_types
= (1 << HWTSTAMP_TX_OFF
) |
1484 (1 << HWTSTAMP_TX_ON
);
1486 info
->rx_filters
= (1 << HWTSTAMP_FILTER_NONE
) |
1487 (1 << HWTSTAMP_FILTER_ALL
);
1490 return ethtool_op_get_ts_info(ndev
, info
);
1494 #if !defined(CONFIG_M5272)
1496 static void fec_enet_get_pauseparam(struct net_device
*ndev
,
1497 struct ethtool_pauseparam
*pause
)
1499 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1501 pause
->autoneg
= (fep
->pause_flag
& FEC_PAUSE_FLAG_AUTONEG
) != 0;
1502 pause
->tx_pause
= (fep
->pause_flag
& FEC_PAUSE_FLAG_ENABLE
) != 0;
1503 pause
->rx_pause
= pause
->tx_pause
;
1506 static int fec_enet_set_pauseparam(struct net_device
*ndev
,
1507 struct ethtool_pauseparam
*pause
)
1509 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1511 if (pause
->tx_pause
!= pause
->rx_pause
) {
1513 "hardware only support enable/disable both tx and rx");
1517 fep
->pause_flag
= 0;
1519 /* tx pause must be same as rx pause */
1520 fep
->pause_flag
|= pause
->rx_pause
? FEC_PAUSE_FLAG_ENABLE
: 0;
1521 fep
->pause_flag
|= pause
->autoneg
? FEC_PAUSE_FLAG_AUTONEG
: 0;
1523 if (pause
->rx_pause
|| pause
->autoneg
) {
1524 fep
->phy_dev
->supported
|= ADVERTISED_Pause
;
1525 fep
->phy_dev
->advertising
|= ADVERTISED_Pause
;
1527 fep
->phy_dev
->supported
&= ~ADVERTISED_Pause
;
1528 fep
->phy_dev
->advertising
&= ~ADVERTISED_Pause
;
1531 if (pause
->autoneg
) {
1532 if (netif_running(ndev
))
1534 phy_start_aneg(fep
->phy_dev
);
1536 if (netif_running(ndev
))
1537 fec_restart(ndev
, 0);
1542 static const struct fec_stat
{
1543 char name
[ETH_GSTRING_LEN
];
1547 { "tx_dropped", RMON_T_DROP
},
1548 { "tx_packets", RMON_T_PACKETS
},
1549 { "tx_broadcast", RMON_T_BC_PKT
},
1550 { "tx_multicast", RMON_T_MC_PKT
},
1551 { "tx_crc_errors", RMON_T_CRC_ALIGN
},
1552 { "tx_undersize", RMON_T_UNDERSIZE
},
1553 { "tx_oversize", RMON_T_OVERSIZE
},
1554 { "tx_fragment", RMON_T_FRAG
},
1555 { "tx_jabber", RMON_T_JAB
},
1556 { "tx_collision", RMON_T_COL
},
1557 { "tx_64byte", RMON_T_P64
},
1558 { "tx_65to127byte", RMON_T_P65TO127
},
1559 { "tx_128to255byte", RMON_T_P128TO255
},
1560 { "tx_256to511byte", RMON_T_P256TO511
},
1561 { "tx_512to1023byte", RMON_T_P512TO1023
},
1562 { "tx_1024to2047byte", RMON_T_P1024TO2047
},
1563 { "tx_GTE2048byte", RMON_T_P_GTE2048
},
1564 { "tx_octets", RMON_T_OCTETS
},
1567 { "IEEE_tx_drop", IEEE_T_DROP
},
1568 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK
},
1569 { "IEEE_tx_1col", IEEE_T_1COL
},
1570 { "IEEE_tx_mcol", IEEE_T_MCOL
},
1571 { "IEEE_tx_def", IEEE_T_DEF
},
1572 { "IEEE_tx_lcol", IEEE_T_LCOL
},
1573 { "IEEE_tx_excol", IEEE_T_EXCOL
},
1574 { "IEEE_tx_macerr", IEEE_T_MACERR
},
1575 { "IEEE_tx_cserr", IEEE_T_CSERR
},
1576 { "IEEE_tx_sqe", IEEE_T_SQE
},
1577 { "IEEE_tx_fdxfc", IEEE_T_FDXFC
},
1578 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK
},
1581 { "rx_packets", RMON_R_PACKETS
},
1582 { "rx_broadcast", RMON_R_BC_PKT
},
1583 { "rx_multicast", RMON_R_MC_PKT
},
1584 { "rx_crc_errors", RMON_R_CRC_ALIGN
},
1585 { "rx_undersize", RMON_R_UNDERSIZE
},
1586 { "rx_oversize", RMON_R_OVERSIZE
},
1587 { "rx_fragment", RMON_R_FRAG
},
1588 { "rx_jabber", RMON_R_JAB
},
1589 { "rx_64byte", RMON_R_P64
},
1590 { "rx_65to127byte", RMON_R_P65TO127
},
1591 { "rx_128to255byte", RMON_R_P128TO255
},
1592 { "rx_256to511byte", RMON_R_P256TO511
},
1593 { "rx_512to1023byte", RMON_R_P512TO1023
},
1594 { "rx_1024to2047byte", RMON_R_P1024TO2047
},
1595 { "rx_GTE2048byte", RMON_R_P_GTE2048
},
1596 { "rx_octets", RMON_R_OCTETS
},
1599 { "IEEE_rx_drop", IEEE_R_DROP
},
1600 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK
},
1601 { "IEEE_rx_crc", IEEE_R_CRC
},
1602 { "IEEE_rx_align", IEEE_R_ALIGN
},
1603 { "IEEE_rx_macerr", IEEE_R_MACERR
},
1604 { "IEEE_rx_fdxfc", IEEE_R_FDXFC
},
1605 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK
},
1608 static void fec_enet_get_ethtool_stats(struct net_device
*dev
,
1609 struct ethtool_stats
*stats
, u64
*data
)
1611 struct fec_enet_private
*fep
= netdev_priv(dev
);
1614 for (i
= 0; i
< ARRAY_SIZE(fec_stats
); i
++)
1615 data
[i
] = readl(fep
->hwp
+ fec_stats
[i
].offset
);
1618 static void fec_enet_get_strings(struct net_device
*netdev
,
1619 u32 stringset
, u8
*data
)
1622 switch (stringset
) {
1624 for (i
= 0; i
< ARRAY_SIZE(fec_stats
); i
++)
1625 memcpy(data
+ i
* ETH_GSTRING_LEN
,
1626 fec_stats
[i
].name
, ETH_GSTRING_LEN
);
1631 static int fec_enet_get_sset_count(struct net_device
*dev
, int sset
)
1635 return ARRAY_SIZE(fec_stats
);
1640 #endif /* !defined(CONFIG_M5272) */
1642 static int fec_enet_nway_reset(struct net_device
*dev
)
1644 struct fec_enet_private
*fep
= netdev_priv(dev
);
1645 struct phy_device
*phydev
= fep
->phy_dev
;
1650 return genphy_restart_aneg(phydev
);
1653 static const struct ethtool_ops fec_enet_ethtool_ops
= {
1654 #if !defined(CONFIG_M5272)
1655 .get_pauseparam
= fec_enet_get_pauseparam
,
1656 .set_pauseparam
= fec_enet_set_pauseparam
,
1658 .get_settings
= fec_enet_get_settings
,
1659 .set_settings
= fec_enet_set_settings
,
1660 .get_drvinfo
= fec_enet_get_drvinfo
,
1661 .get_link
= ethtool_op_get_link
,
1662 .get_ts_info
= fec_enet_get_ts_info
,
1663 .nway_reset
= fec_enet_nway_reset
,
1664 #ifndef CONFIG_M5272
1665 .get_ethtool_stats
= fec_enet_get_ethtool_stats
,
1666 .get_strings
= fec_enet_get_strings
,
1667 .get_sset_count
= fec_enet_get_sset_count
,
1671 static int fec_enet_ioctl(struct net_device
*ndev
, struct ifreq
*rq
, int cmd
)
1673 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1674 struct phy_device
*phydev
= fep
->phy_dev
;
1676 if (!netif_running(ndev
))
1682 if (fep
->bufdesc_ex
) {
1683 if (cmd
== SIOCSHWTSTAMP
)
1684 return fec_ptp_set(ndev
, rq
);
1685 if (cmd
== SIOCGHWTSTAMP
)
1686 return fec_ptp_get(ndev
, rq
);
1689 return phy_mii_ioctl(phydev
, rq
, cmd
);
1692 static void fec_enet_free_buffers(struct net_device
*ndev
)
1694 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1696 struct sk_buff
*skb
;
1697 struct bufdesc
*bdp
;
1699 bdp
= fep
->rx_bd_base
;
1700 for (i
= 0; i
< fep
->rx_ring_size
; i
++) {
1701 skb
= fep
->rx_skbuff
[i
];
1703 if (bdp
->cbd_bufaddr
)
1704 dma_unmap_single(&fep
->pdev
->dev
, bdp
->cbd_bufaddr
,
1705 FEC_ENET_RX_FRSIZE
, DMA_FROM_DEVICE
);
1708 bdp
= fec_enet_get_nextdesc(bdp
, fep
);
1711 bdp
= fep
->tx_bd_base
;
1712 for (i
= 0; i
< fep
->tx_ring_size
; i
++)
1713 kfree(fep
->tx_bounce
[i
]);
1716 static int fec_enet_alloc_buffers(struct net_device
*ndev
)
1718 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1720 struct sk_buff
*skb
;
1721 struct bufdesc
*bdp
;
1723 bdp
= fep
->rx_bd_base
;
1724 for (i
= 0; i
< fep
->rx_ring_size
; i
++) {
1725 skb
= netdev_alloc_skb(ndev
, FEC_ENET_RX_FRSIZE
);
1727 fec_enet_free_buffers(ndev
);
1730 fep
->rx_skbuff
[i
] = skb
;
1732 bdp
->cbd_bufaddr
= dma_map_single(&fep
->pdev
->dev
, skb
->data
,
1733 FEC_ENET_RX_FRSIZE
, DMA_FROM_DEVICE
);
1734 if (dma_mapping_error(&fep
->pdev
->dev
, bdp
->cbd_bufaddr
)) {
1735 fec_enet_free_buffers(ndev
);
1736 if (net_ratelimit())
1737 netdev_err(ndev
, "Rx DMA memory map failed\n");
1740 bdp
->cbd_sc
= BD_ENET_RX_EMPTY
;
1742 if (fep
->bufdesc_ex
) {
1743 struct bufdesc_ex
*ebdp
= (struct bufdesc_ex
*)bdp
;
1744 ebdp
->cbd_esc
= BD_ENET_RX_INT
;
1747 bdp
= fec_enet_get_nextdesc(bdp
, fep
);
1750 /* Set the last buffer to wrap. */
1751 bdp
= fec_enet_get_prevdesc(bdp
, fep
);
1752 bdp
->cbd_sc
|= BD_SC_WRAP
;
1754 bdp
= fep
->tx_bd_base
;
1755 for (i
= 0; i
< fep
->tx_ring_size
; i
++) {
1756 fep
->tx_bounce
[i
] = kmalloc(FEC_ENET_TX_FRSIZE
, GFP_KERNEL
);
1759 bdp
->cbd_bufaddr
= 0;
1761 if (fep
->bufdesc_ex
) {
1762 struct bufdesc_ex
*ebdp
= (struct bufdesc_ex
*)bdp
;
1763 ebdp
->cbd_esc
= BD_ENET_TX_INT
;
1766 bdp
= fec_enet_get_nextdesc(bdp
, fep
);
1769 /* Set the last buffer to wrap. */
1770 bdp
= fec_enet_get_prevdesc(bdp
, fep
);
1771 bdp
->cbd_sc
|= BD_SC_WRAP
;
1777 fec_enet_open(struct net_device
*ndev
)
1779 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1782 napi_enable(&fep
->napi
);
1784 /* I should reset the ring buffers here, but I don't yet know
1785 * a simple way to do that.
1788 ret
= fec_enet_alloc_buffers(ndev
);
1792 /* Probe and connect to PHY when open the interface */
1793 ret
= fec_enet_mii_probe(ndev
);
1795 fec_enet_free_buffers(ndev
);
1798 phy_start(fep
->phy_dev
);
1799 netif_start_queue(ndev
);
1805 fec_enet_close(struct net_device
*ndev
)
1807 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1809 /* Don't know what to do yet. */
1810 napi_disable(&fep
->napi
);
1812 netif_stop_queue(ndev
);
1816 phy_stop(fep
->phy_dev
);
1817 phy_disconnect(fep
->phy_dev
);
1820 fec_enet_free_buffers(ndev
);
1825 /* Set or clear the multicast filter for this adaptor.
1826 * Skeleton taken from sunlance driver.
1827 * The CPM Ethernet implementation allows Multicast as well as individual
1828 * MAC address filtering. Some of the drivers check to make sure it is
1829 * a group multicast address, and discard those that are not. I guess I
1830 * will do the same for now, but just remove the test if you want
1831 * individual filtering as well (do the upper net layers want or support
1832 * this kind of feature?).
1835 #define HASH_BITS 6 /* #bits in hash */
1836 #define CRC32_POLY 0xEDB88320
1838 static void set_multicast_list(struct net_device
*ndev
)
1840 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1841 struct netdev_hw_addr
*ha
;
1842 unsigned int i
, bit
, data
, crc
, tmp
;
1845 if (ndev
->flags
& IFF_PROMISC
) {
1846 tmp
= readl(fep
->hwp
+ FEC_R_CNTRL
);
1848 writel(tmp
, fep
->hwp
+ FEC_R_CNTRL
);
1852 tmp
= readl(fep
->hwp
+ FEC_R_CNTRL
);
1854 writel(tmp
, fep
->hwp
+ FEC_R_CNTRL
);
1856 if (ndev
->flags
& IFF_ALLMULTI
) {
1857 /* Catch all multicast addresses, so set the
1860 writel(0xffffffff, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
1861 writel(0xffffffff, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
1866 /* Clear filter and add the addresses in hash register
1868 writel(0, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
1869 writel(0, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
1871 netdev_for_each_mc_addr(ha
, ndev
) {
1872 /* calculate crc32 value of mac address */
1875 for (i
= 0; i
< ndev
->addr_len
; i
++) {
1877 for (bit
= 0; bit
< 8; bit
++, data
>>= 1) {
1879 (((crc
^ data
) & 1) ? CRC32_POLY
: 0);
1883 /* only upper 6 bits (HASH_BITS) are used
1884 * which point to specific bit in he hash registers
1886 hash
= (crc
>> (32 - HASH_BITS
)) & 0x3f;
1889 tmp
= readl(fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
1890 tmp
|= 1 << (hash
- 32);
1891 writel(tmp
, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
1893 tmp
= readl(fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
1895 writel(tmp
, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
1900 /* Set a MAC change in hardware. */
1902 fec_set_mac_address(struct net_device
*ndev
, void *p
)
1904 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1905 struct sockaddr
*addr
= p
;
1907 if (!is_valid_ether_addr(addr
->sa_data
))
1908 return -EADDRNOTAVAIL
;
1910 memcpy(ndev
->dev_addr
, addr
->sa_data
, ndev
->addr_len
);
1912 writel(ndev
->dev_addr
[3] | (ndev
->dev_addr
[2] << 8) |
1913 (ndev
->dev_addr
[1] << 16) | (ndev
->dev_addr
[0] << 24),
1914 fep
->hwp
+ FEC_ADDR_LOW
);
1915 writel((ndev
->dev_addr
[5] << 16) | (ndev
->dev_addr
[4] << 24),
1916 fep
->hwp
+ FEC_ADDR_HIGH
);
1920 #ifdef CONFIG_NET_POLL_CONTROLLER
1922 * fec_poll_controller - FEC Poll controller function
1923 * @dev: The FEC network adapter
1925 * Polled functionality used by netconsole and others in non interrupt mode
1928 static void fec_poll_controller(struct net_device
*dev
)
1931 struct fec_enet_private
*fep
= netdev_priv(dev
);
1933 for (i
= 0; i
< FEC_IRQ_NUM
; i
++) {
1934 if (fep
->irq
[i
] > 0) {
1935 disable_irq(fep
->irq
[i
]);
1936 fec_enet_interrupt(fep
->irq
[i
], dev
);
1937 enable_irq(fep
->irq
[i
]);
1943 static int fec_set_features(struct net_device
*netdev
,
1944 netdev_features_t features
)
1946 struct fec_enet_private
*fep
= netdev_priv(netdev
);
1947 netdev_features_t changed
= features
^ netdev
->features
;
1949 netdev
->features
= features
;
1951 /* Receive checksum has been changed */
1952 if (changed
& NETIF_F_RXCSUM
) {
1953 if (features
& NETIF_F_RXCSUM
)
1954 fep
->csum_flags
|= FLAG_RX_CSUM_ENABLED
;
1956 fep
->csum_flags
&= ~FLAG_RX_CSUM_ENABLED
;
1958 if (netif_running(netdev
)) {
1960 fec_restart(netdev
, fep
->phy_dev
->duplex
);
1961 netif_wake_queue(netdev
);
1963 fec_restart(netdev
, fep
->phy_dev
->duplex
);
1970 static const struct net_device_ops fec_netdev_ops
= {
1971 .ndo_open
= fec_enet_open
,
1972 .ndo_stop
= fec_enet_close
,
1973 .ndo_start_xmit
= fec_enet_start_xmit
,
1974 .ndo_set_rx_mode
= set_multicast_list
,
1975 .ndo_change_mtu
= eth_change_mtu
,
1976 .ndo_validate_addr
= eth_validate_addr
,
1977 .ndo_tx_timeout
= fec_timeout
,
1978 .ndo_set_mac_address
= fec_set_mac_address
,
1979 .ndo_do_ioctl
= fec_enet_ioctl
,
1980 #ifdef CONFIG_NET_POLL_CONTROLLER
1981 .ndo_poll_controller
= fec_poll_controller
,
1983 .ndo_set_features
= fec_set_features
,
1987 * XXX: We need to clean up on failure exits here.
1990 static int fec_enet_init(struct net_device
*ndev
)
1992 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1993 const struct platform_device_id
*id_entry
=
1994 platform_get_device_id(fep
->pdev
);
1995 struct bufdesc
*cbd_base
;
1997 /* Allocate memory for buffer descriptors. */
1998 cbd_base
= dma_alloc_coherent(NULL
, PAGE_SIZE
, &fep
->bd_dma
,
2003 memset(cbd_base
, 0, PAGE_SIZE
);
2007 /* Get the Ethernet address */
2010 /* init the tx & rx ring size */
2011 fep
->tx_ring_size
= TX_RING_SIZE
;
2012 fep
->rx_ring_size
= RX_RING_SIZE
;
2014 /* Set receive and transmit descriptor base. */
2015 fep
->rx_bd_base
= cbd_base
;
2016 if (fep
->bufdesc_ex
)
2017 fep
->tx_bd_base
= (struct bufdesc
*)
2018 (((struct bufdesc_ex
*)cbd_base
) + fep
->rx_ring_size
);
2020 fep
->tx_bd_base
= cbd_base
+ fep
->rx_ring_size
;
2022 /* The FEC Ethernet specific entries in the device structure */
2023 ndev
->watchdog_timeo
= TX_TIMEOUT
;
2024 ndev
->netdev_ops
= &fec_netdev_ops
;
2025 ndev
->ethtool_ops
= &fec_enet_ethtool_ops
;
2027 writel(FEC_RX_DISABLED_IMASK
, fep
->hwp
+ FEC_IMASK
);
2028 netif_napi_add(ndev
, &fep
->napi
, fec_enet_rx_napi
, NAPI_POLL_WEIGHT
);
2030 if (id_entry
->driver_data
& FEC_QUIRK_HAS_VLAN
) {
2031 /* enable hw VLAN support */
2032 ndev
->features
|= NETIF_F_HW_VLAN_CTAG_RX
;
2033 ndev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
;
2036 if (id_entry
->driver_data
& FEC_QUIRK_HAS_CSUM
) {
2037 /* enable hw accelerator */
2038 ndev
->features
|= (NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
2040 ndev
->hw_features
|= (NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
2042 fep
->csum_flags
|= FLAG_RX_CSUM_ENABLED
;
2045 fec_restart(ndev
, 0);
2051 static void fec_reset_phy(struct platform_device
*pdev
)
2055 struct device_node
*np
= pdev
->dev
.of_node
;
2060 of_property_read_u32(np
, "phy-reset-duration", &msec
);
2061 /* A sane reset duration should not be longer than 1s */
2065 phy_reset
= of_get_named_gpio(np
, "phy-reset-gpios", 0);
2066 if (!gpio_is_valid(phy_reset
))
2069 err
= devm_gpio_request_one(&pdev
->dev
, phy_reset
,
2070 GPIOF_OUT_INIT_LOW
, "phy-reset");
2072 dev_err(&pdev
->dev
, "failed to get phy-reset-gpios: %d\n", err
);
2076 gpio_set_value(phy_reset
, 1);
2078 #else /* CONFIG_OF */
2079 static void fec_reset_phy(struct platform_device
*pdev
)
2082 * In case of platform probe, the reset has been done
2086 #endif /* CONFIG_OF */
2089 fec_probe(struct platform_device
*pdev
)
2091 struct fec_enet_private
*fep
;
2092 struct fec_platform_data
*pdata
;
2093 struct net_device
*ndev
;
2094 int i
, irq
, ret
= 0;
2096 const struct of_device_id
*of_id
;
2099 of_id
= of_match_device(fec_dt_ids
, &pdev
->dev
);
2101 pdev
->id_entry
= of_id
->data
;
2103 /* Init network device */
2104 ndev
= alloc_etherdev(sizeof(struct fec_enet_private
));
2108 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
2110 /* setup board info structure */
2111 fep
= netdev_priv(ndev
);
2113 #if !defined(CONFIG_M5272)
2114 /* default enable pause frame auto negotiation */
2115 if (pdev
->id_entry
&&
2116 (pdev
->id_entry
->driver_data
& FEC_QUIRK_HAS_GBIT
))
2117 fep
->pause_flag
|= FEC_PAUSE_FLAG_AUTONEG
;
2120 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2121 fep
->hwp
= devm_ioremap_resource(&pdev
->dev
, r
);
2122 if (IS_ERR(fep
->hwp
)) {
2123 ret
= PTR_ERR(fep
->hwp
);
2124 goto failed_ioremap
;
2128 fep
->dev_id
= dev_id
++;
2130 fep
->bufdesc_ex
= 0;
2132 platform_set_drvdata(pdev
, ndev
);
2134 ret
= of_get_phy_mode(pdev
->dev
.of_node
);
2136 pdata
= dev_get_platdata(&pdev
->dev
);
2138 fep
->phy_interface
= pdata
->phy
;
2140 fep
->phy_interface
= PHY_INTERFACE_MODE_MII
;
2142 fep
->phy_interface
= ret
;
2145 fep
->clk_ipg
= devm_clk_get(&pdev
->dev
, "ipg");
2146 if (IS_ERR(fep
->clk_ipg
)) {
2147 ret
= PTR_ERR(fep
->clk_ipg
);
2151 fep
->clk_ahb
= devm_clk_get(&pdev
->dev
, "ahb");
2152 if (IS_ERR(fep
->clk_ahb
)) {
2153 ret
= PTR_ERR(fep
->clk_ahb
);
2157 /* enet_out is optional, depends on board */
2158 fep
->clk_enet_out
= devm_clk_get(&pdev
->dev
, "enet_out");
2159 if (IS_ERR(fep
->clk_enet_out
))
2160 fep
->clk_enet_out
= NULL
;
2162 fep
->clk_ptp
= devm_clk_get(&pdev
->dev
, "ptp");
2164 pdev
->id_entry
->driver_data
& FEC_QUIRK_HAS_BUFDESC_EX
;
2165 if (IS_ERR(fep
->clk_ptp
)) {
2166 fep
->clk_ptp
= NULL
;
2167 fep
->bufdesc_ex
= 0;
2170 ret
= clk_prepare_enable(fep
->clk_ahb
);
2174 ret
= clk_prepare_enable(fep
->clk_ipg
);
2176 goto failed_clk_ipg
;
2178 if (fep
->clk_enet_out
) {
2179 ret
= clk_prepare_enable(fep
->clk_enet_out
);
2181 goto failed_clk_enet_out
;
2185 ret
= clk_prepare_enable(fep
->clk_ptp
);
2187 goto failed_clk_ptp
;
2190 fep
->reg_phy
= devm_regulator_get(&pdev
->dev
, "phy");
2191 if (!IS_ERR(fep
->reg_phy
)) {
2192 ret
= regulator_enable(fep
->reg_phy
);
2195 "Failed to enable phy regulator: %d\n", ret
);
2196 goto failed_regulator
;
2199 fep
->reg_phy
= NULL
;
2202 fec_reset_phy(pdev
);
2204 if (fep
->bufdesc_ex
)
2207 ret
= fec_enet_init(ndev
);
2211 for (i
= 0; i
< FEC_IRQ_NUM
; i
++) {
2212 irq
= platform_get_irq(pdev
, i
);
2219 ret
= devm_request_irq(&pdev
->dev
, irq
, fec_enet_interrupt
,
2220 0, pdev
->name
, ndev
);
2225 ret
= fec_enet_mii_init(pdev
);
2227 goto failed_mii_init
;
2229 /* Carrier starts down, phylib will bring it up */
2230 netif_carrier_off(ndev
);
2232 ret
= register_netdev(ndev
);
2234 goto failed_register
;
2236 if (fep
->bufdesc_ex
&& fep
->ptp_clock
)
2237 netdev_info(ndev
, "registered PHC device %d\n", fep
->dev_id
);
2239 INIT_DELAYED_WORK(&(fep
->delay_work
.delay_work
), fec_enet_work
);
2243 fec_enet_mii_remove(fep
);
2248 regulator_disable(fep
->reg_phy
);
2251 clk_disable_unprepare(fep
->clk_ptp
);
2253 if (fep
->clk_enet_out
)
2254 clk_disable_unprepare(fep
->clk_enet_out
);
2255 failed_clk_enet_out
:
2256 clk_disable_unprepare(fep
->clk_ipg
);
2258 clk_disable_unprepare(fep
->clk_ahb
);
2267 fec_drv_remove(struct platform_device
*pdev
)
2269 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2270 struct fec_enet_private
*fep
= netdev_priv(ndev
);
2272 cancel_delayed_work_sync(&(fep
->delay_work
.delay_work
));
2273 unregister_netdev(ndev
);
2274 fec_enet_mii_remove(fep
);
2275 del_timer_sync(&fep
->time_keep
);
2277 regulator_disable(fep
->reg_phy
);
2279 clk_disable_unprepare(fep
->clk_ptp
);
2281 ptp_clock_unregister(fep
->ptp_clock
);
2282 if (fep
->clk_enet_out
)
2283 clk_disable_unprepare(fep
->clk_enet_out
);
2284 clk_disable_unprepare(fep
->clk_ipg
);
2285 clk_disable_unprepare(fep
->clk_ahb
);
2291 #ifdef CONFIG_PM_SLEEP
2293 fec_suspend(struct device
*dev
)
2295 struct net_device
*ndev
= dev_get_drvdata(dev
);
2296 struct fec_enet_private
*fep
= netdev_priv(ndev
);
2298 if (netif_running(ndev
)) {
2300 netif_device_detach(ndev
);
2303 clk_disable_unprepare(fep
->clk_ptp
);
2304 if (fep
->clk_enet_out
)
2305 clk_disable_unprepare(fep
->clk_enet_out
);
2306 clk_disable_unprepare(fep
->clk_ipg
);
2307 clk_disable_unprepare(fep
->clk_ahb
);
2310 regulator_disable(fep
->reg_phy
);
2316 fec_resume(struct device
*dev
)
2318 struct net_device
*ndev
= dev_get_drvdata(dev
);
2319 struct fec_enet_private
*fep
= netdev_priv(ndev
);
2323 ret
= regulator_enable(fep
->reg_phy
);
2328 ret
= clk_prepare_enable(fep
->clk_ahb
);
2330 goto failed_clk_ahb
;
2332 ret
= clk_prepare_enable(fep
->clk_ipg
);
2334 goto failed_clk_ipg
;
2336 if (fep
->clk_enet_out
) {
2337 ret
= clk_prepare_enable(fep
->clk_enet_out
);
2339 goto failed_clk_enet_out
;
2343 ret
= clk_prepare_enable(fep
->clk_ptp
);
2345 goto failed_clk_ptp
;
2348 if (netif_running(ndev
)) {
2349 fec_restart(ndev
, fep
->full_duplex
);
2350 netif_device_attach(ndev
);
2356 if (fep
->clk_enet_out
)
2357 clk_disable_unprepare(fep
->clk_enet_out
);
2358 failed_clk_enet_out
:
2359 clk_disable_unprepare(fep
->clk_ipg
);
2361 clk_disable_unprepare(fep
->clk_ahb
);
2364 regulator_disable(fep
->reg_phy
);
2367 #endif /* CONFIG_PM_SLEEP */
2369 static SIMPLE_DEV_PM_OPS(fec_pm_ops
, fec_suspend
, fec_resume
);
2371 static struct platform_driver fec_driver
= {
2373 .name
= DRIVER_NAME
,
2374 .owner
= THIS_MODULE
,
2376 .of_match_table
= fec_dt_ids
,
2378 .id_table
= fec_devtype
,
2380 .remove
= fec_drv_remove
,
2383 module_platform_driver(fec_driver
);
2385 MODULE_ALIAS("platform:"DRIVER_NAME
);
2386 MODULE_LICENSE("GPL");