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net: fec: fix kernel oops when plug/unplug cable many times
[deliverable/linux.git] / drivers / net / ethernet / freescale / fec_main.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/in.h>
38 #include <linux/ip.h>
39 #include <net/ip.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
46 #include <linux/io.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
52 #include <linux/of.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_net.h>
56 #include <linux/pinctrl/consumer.h>
57 #include <linux/regulator/consumer.h>
58
59 #include <asm/cacheflush.h>
60
61 #include "fec.h"
62
63 #if defined(CONFIG_ARM)
64 #define FEC_ALIGNMENT 0xf
65 #else
66 #define FEC_ALIGNMENT 0x3
67 #endif
68
69 #define DRIVER_NAME "fec"
70 #define FEC_NAPI_WEIGHT 64
71
72 /* Pause frame feild and FIFO threshold */
73 #define FEC_ENET_FCE (1 << 5)
74 #define FEC_ENET_RSEM_V 0x84
75 #define FEC_ENET_RSFL_V 16
76 #define FEC_ENET_RAEM_V 0x8
77 #define FEC_ENET_RAFL_V 0x8
78 #define FEC_ENET_OPD_V 0xFFF0
79
80 /* Controller is ENET-MAC */
81 #define FEC_QUIRK_ENET_MAC (1 << 0)
82 /* Controller needs driver to swap frame */
83 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
84 /* Controller uses gasket */
85 #define FEC_QUIRK_USE_GASKET (1 << 2)
86 /* Controller has GBIT support */
87 #define FEC_QUIRK_HAS_GBIT (1 << 3)
88 /* Controller has extend desc buffer */
89 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
90
91 static struct platform_device_id fec_devtype[] = {
92 {
93 /* keep it for coldfire */
94 .name = DRIVER_NAME,
95 .driver_data = 0,
96 }, {
97 .name = "imx25-fec",
98 .driver_data = FEC_QUIRK_USE_GASKET,
99 }, {
100 .name = "imx27-fec",
101 .driver_data = 0,
102 }, {
103 .name = "imx28-fec",
104 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
105 }, {
106 .name = "imx6q-fec",
107 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
108 FEC_QUIRK_HAS_BUFDESC_EX,
109 }, {
110 .name = "mvf-fec",
111 .driver_data = FEC_QUIRK_ENET_MAC,
112 }, {
113 /* sentinel */
114 }
115 };
116 MODULE_DEVICE_TABLE(platform, fec_devtype);
117
118 enum imx_fec_type {
119 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
120 IMX27_FEC, /* runs on i.mx27/35/51 */
121 IMX28_FEC,
122 IMX6Q_FEC,
123 MVF_FEC,
124 };
125
126 static const struct of_device_id fec_dt_ids[] = {
127 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
128 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
129 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
130 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
131 { .compatible = "fsl,mvf-fec", .data = &fec_devtype[MVF_FEC], },
132 { /* sentinel */ }
133 };
134 MODULE_DEVICE_TABLE(of, fec_dt_ids);
135
136 static unsigned char macaddr[ETH_ALEN];
137 module_param_array(macaddr, byte, NULL, 0);
138 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
139
140 #if defined(CONFIG_M5272)
141 /*
142 * Some hardware gets it MAC address out of local flash memory.
143 * if this is non-zero then assume it is the address to get MAC from.
144 */
145 #if defined(CONFIG_NETtel)
146 #define FEC_FLASHMAC 0xf0006006
147 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
148 #define FEC_FLASHMAC 0xf0006000
149 #elif defined(CONFIG_CANCam)
150 #define FEC_FLASHMAC 0xf0020000
151 #elif defined (CONFIG_M5272C3)
152 #define FEC_FLASHMAC (0xffe04000 + 4)
153 #elif defined(CONFIG_MOD5272)
154 #define FEC_FLASHMAC 0xffc0406b
155 #else
156 #define FEC_FLASHMAC 0
157 #endif
158 #endif /* CONFIG_M5272 */
159
160 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
161 #error "FEC: descriptor ring size constants too large"
162 #endif
163
164 /* Interrupt events/masks. */
165 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
166 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
167 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
168 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
169 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
170 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
171 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
172 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
173 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
174 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
175
176 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
177 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
178
179 /* The FEC stores dest/src/type, data, and checksum for receive packets.
180 */
181 #define PKT_MAXBUF_SIZE 1518
182 #define PKT_MINBUF_SIZE 64
183 #define PKT_MAXBLR_SIZE 1520
184
185 /* FEC receive acceleration */
186 #define FEC_RACC_IPDIS (1 << 1)
187 #define FEC_RACC_PRODIS (1 << 2)
188 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
189
190 /*
191 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
192 * size bits. Other FEC hardware does not, so we need to take that into
193 * account when setting it.
194 */
195 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
196 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
197 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
198 #else
199 #define OPT_FRAME_SIZE 0
200 #endif
201
202 /* FEC MII MMFR bits definition */
203 #define FEC_MMFR_ST (1 << 30)
204 #define FEC_MMFR_OP_READ (2 << 28)
205 #define FEC_MMFR_OP_WRITE (1 << 28)
206 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
207 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
208 #define FEC_MMFR_TA (2 << 16)
209 #define FEC_MMFR_DATA(v) (v & 0xffff)
210
211 #define FEC_MII_TIMEOUT 30000 /* us */
212
213 /* Transmitter timeout */
214 #define TX_TIMEOUT (2 * HZ)
215
216 #define FEC_PAUSE_FLAG_AUTONEG 0x1
217 #define FEC_PAUSE_FLAG_ENABLE 0x2
218
219 static int mii_cnt;
220
221 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
222 {
223 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
224 if (is_ex)
225 return (struct bufdesc *)(ex + 1);
226 else
227 return bdp + 1;
228 }
229
230 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex)
231 {
232 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
233 if (is_ex)
234 return (struct bufdesc *)(ex - 1);
235 else
236 return bdp - 1;
237 }
238
239 static void *swap_buffer(void *bufaddr, int len)
240 {
241 int i;
242 unsigned int *buf = bufaddr;
243
244 for (i = 0; i < (len + 3) / 4; i++, buf++)
245 *buf = cpu_to_be32(*buf);
246
247 return bufaddr;
248 }
249
250 static int
251 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
252 {
253 /* Only run for packets requiring a checksum. */
254 if (skb->ip_summed != CHECKSUM_PARTIAL)
255 return 0;
256
257 if (unlikely(skb_cow_head(skb, 0)))
258 return -1;
259
260 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
261
262 return 0;
263 }
264
265 static netdev_tx_t
266 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
267 {
268 struct fec_enet_private *fep = netdev_priv(ndev);
269 const struct platform_device_id *id_entry =
270 platform_get_device_id(fep->pdev);
271 struct bufdesc *bdp;
272 void *bufaddr;
273 unsigned short status;
274 unsigned int index;
275
276 if (!fep->link) {
277 /* Link is down or auto-negotiation is in progress. */
278 return NETDEV_TX_BUSY;
279 }
280
281 /* Fill in a Tx ring entry */
282 bdp = fep->cur_tx;
283
284 status = bdp->cbd_sc;
285
286 if (status & BD_ENET_TX_READY) {
287 /* Ooops. All transmit buffers are full. Bail out.
288 * This should not happen, since ndev->tbusy should be set.
289 */
290 netdev_err(ndev, "tx queue full!\n");
291 return NETDEV_TX_BUSY;
292 }
293
294 /* Protocol checksum off-load for TCP and UDP. */
295 if (fec_enet_clear_csum(skb, ndev)) {
296 kfree_skb(skb);
297 return NETDEV_TX_OK;
298 }
299
300 /* Clear all of the status flags */
301 status &= ~BD_ENET_TX_STATS;
302
303 /* Set buffer length and buffer pointer */
304 bufaddr = skb->data;
305 bdp->cbd_datlen = skb->len;
306
307 /*
308 * On some FEC implementations data must be aligned on
309 * 4-byte boundaries. Use bounce buffers to copy data
310 * and get it aligned. Ugh.
311 */
312 if (fep->bufdesc_ex)
313 index = (struct bufdesc_ex *)bdp -
314 (struct bufdesc_ex *)fep->tx_bd_base;
315 else
316 index = bdp - fep->tx_bd_base;
317
318 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
319 memcpy(fep->tx_bounce[index], skb->data, skb->len);
320 bufaddr = fep->tx_bounce[index];
321 }
322
323 /*
324 * Some design made an incorrect assumption on endian mode of
325 * the system that it's running on. As the result, driver has to
326 * swap every frame going to and coming from the controller.
327 */
328 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
329 swap_buffer(bufaddr, skb->len);
330
331 /* Save skb pointer */
332 fep->tx_skbuff[index] = skb;
333
334 /* Push the data cache so the CPM does not get stale memory
335 * data.
336 */
337 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
338 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
339
340 /* Send it on its way. Tell FEC it's ready, interrupt when done,
341 * it's the last BD of the frame, and to put the CRC on the end.
342 */
343 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
344 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
345 bdp->cbd_sc = status;
346
347 if (fep->bufdesc_ex) {
348
349 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
350 ebdp->cbd_bdu = 0;
351 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
352 fep->hwts_tx_en)) {
353 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
354 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
355 } else {
356 ebdp->cbd_esc = BD_ENET_TX_INT;
357
358 /* Enable protocol checksum flags
359 * We do not bother with the IP Checksum bits as they
360 * are done by the kernel
361 */
362 if (skb->ip_summed == CHECKSUM_PARTIAL)
363 ebdp->cbd_esc |= BD_ENET_TX_PINS;
364 }
365 }
366 /* If this was the last BD in the ring, start at the beginning again. */
367 if (status & BD_ENET_TX_WRAP)
368 bdp = fep->tx_bd_base;
369 else
370 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
371
372 fep->cur_tx = bdp;
373
374 if (fep->cur_tx == fep->dirty_tx)
375 netif_stop_queue(ndev);
376
377 /* Trigger transmission start */
378 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
379
380 skb_tx_timestamp(skb);
381
382 return NETDEV_TX_OK;
383 }
384
385 /* Init RX & TX buffer descriptors
386 */
387 static void fec_enet_bd_init(struct net_device *dev)
388 {
389 struct fec_enet_private *fep = netdev_priv(dev);
390 struct bufdesc *bdp;
391 unsigned int i;
392
393 /* Initialize the receive buffer descriptors. */
394 bdp = fep->rx_bd_base;
395 for (i = 0; i < RX_RING_SIZE; i++) {
396
397 /* Initialize the BD for every fragment in the page. */
398 if (bdp->cbd_bufaddr)
399 bdp->cbd_sc = BD_ENET_RX_EMPTY;
400 else
401 bdp->cbd_sc = 0;
402 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
403 }
404
405 /* Set the last buffer to wrap */
406 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
407 bdp->cbd_sc |= BD_SC_WRAP;
408
409 fep->cur_rx = fep->rx_bd_base;
410
411 /* ...and the same for transmit */
412 bdp = fep->tx_bd_base;
413 fep->cur_tx = bdp;
414 for (i = 0; i < TX_RING_SIZE; i++) {
415
416 /* Initialize the BD for every fragment in the page. */
417 bdp->cbd_sc = 0;
418 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
419 dev_kfree_skb_any(fep->tx_skbuff[i]);
420 fep->tx_skbuff[i] = NULL;
421 }
422 bdp->cbd_bufaddr = 0;
423 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
424 }
425
426 /* Set the last buffer to wrap */
427 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
428 bdp->cbd_sc |= BD_SC_WRAP;
429 fep->dirty_tx = bdp;
430 }
431
432 /* This function is called to start or restart the FEC during a link
433 * change. This only happens when switching between half and full
434 * duplex.
435 */
436 static void
437 fec_restart(struct net_device *ndev, int duplex)
438 {
439 struct fec_enet_private *fep = netdev_priv(ndev);
440 const struct platform_device_id *id_entry =
441 platform_get_device_id(fep->pdev);
442 int i;
443 u32 val;
444 u32 temp_mac[2];
445 u32 rcntl = OPT_FRAME_SIZE | 0x04;
446 u32 ecntl = 0x2; /* ETHEREN */
447
448 if (netif_running(ndev)) {
449 netif_device_detach(ndev);
450 napi_disable(&fep->napi);
451 netif_stop_queue(ndev);
452 netif_tx_lock(ndev);
453 }
454
455 /* Whack a reset. We should wait for this. */
456 writel(1, fep->hwp + FEC_ECNTRL);
457 udelay(10);
458
459 /*
460 * enet-mac reset will reset mac address registers too,
461 * so need to reconfigure it.
462 */
463 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
464 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
465 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
466 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
467 }
468
469 /* Clear any outstanding interrupt. */
470 writel(0xffc00000, fep->hwp + FEC_IEVENT);
471
472 /* Reset all multicast. */
473 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
474 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
475 #ifndef CONFIG_M5272
476 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
477 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
478 #endif
479
480 /* Set maximum receive buffer size. */
481 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
482
483 fec_enet_bd_init(ndev);
484
485 /* Set receive and transmit descriptor base. */
486 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
487 if (fep->bufdesc_ex)
488 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
489 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
490 else
491 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
492 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
493
494
495 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
496 if (fep->tx_skbuff[i]) {
497 dev_kfree_skb_any(fep->tx_skbuff[i]);
498 fep->tx_skbuff[i] = NULL;
499 }
500 }
501
502 /* Enable MII mode */
503 if (duplex) {
504 /* FD enable */
505 writel(0x04, fep->hwp + FEC_X_CNTRL);
506 } else {
507 /* No Rcv on Xmit */
508 rcntl |= 0x02;
509 writel(0x0, fep->hwp + FEC_X_CNTRL);
510 }
511
512 fep->full_duplex = duplex;
513
514 /* Set MII speed */
515 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
516
517 /* set RX checksum */
518 val = readl(fep->hwp + FEC_RACC);
519 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
520 val |= FEC_RACC_OPTIONS;
521 else
522 val &= ~FEC_RACC_OPTIONS;
523 writel(val, fep->hwp + FEC_RACC);
524
525 /*
526 * The phy interface and speed need to get configured
527 * differently on enet-mac.
528 */
529 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
530 /* Enable flow control and length check */
531 rcntl |= 0x40000000 | 0x00000020;
532
533 /* RGMII, RMII or MII */
534 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
535 rcntl |= (1 << 6);
536 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
537 rcntl |= (1 << 8);
538 else
539 rcntl &= ~(1 << 8);
540
541 /* 1G, 100M or 10M */
542 if (fep->phy_dev) {
543 if (fep->phy_dev->speed == SPEED_1000)
544 ecntl |= (1 << 5);
545 else if (fep->phy_dev->speed == SPEED_100)
546 rcntl &= ~(1 << 9);
547 else
548 rcntl |= (1 << 9);
549 }
550 } else {
551 #ifdef FEC_MIIGSK_ENR
552 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
553 u32 cfgr;
554 /* disable the gasket and wait */
555 writel(0, fep->hwp + FEC_MIIGSK_ENR);
556 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
557 udelay(1);
558
559 /*
560 * configure the gasket:
561 * RMII, 50 MHz, no loopback, no echo
562 * MII, 25 MHz, no loopback, no echo
563 */
564 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
565 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
566 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
567 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
568 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
569
570 /* re-enable the gasket */
571 writel(2, fep->hwp + FEC_MIIGSK_ENR);
572 }
573 #endif
574 }
575
576 /* enable pause frame*/
577 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
578 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
579 fep->phy_dev && fep->phy_dev->pause)) {
580 rcntl |= FEC_ENET_FCE;
581
582 /* set FIFO threshold parameter to reduce overrun */
583 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
584 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
585 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
586 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
587
588 /* OPD */
589 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
590 } else {
591 rcntl &= ~FEC_ENET_FCE;
592 }
593
594 writel(rcntl, fep->hwp + FEC_R_CNTRL);
595
596 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
597 /* enable ENET endian swap */
598 ecntl |= (1 << 8);
599 /* enable ENET store and forward mode */
600 writel(1 << 8, fep->hwp + FEC_X_WMRK);
601 }
602
603 if (fep->bufdesc_ex)
604 ecntl |= (1 << 4);
605
606 /* And last, enable the transmit and receive processing */
607 writel(ecntl, fep->hwp + FEC_ECNTRL);
608 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
609
610 if (fep->bufdesc_ex)
611 fec_ptp_start_cyclecounter(ndev);
612
613 /* Enable interrupts we wish to service */
614 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
615
616 if (netif_running(ndev)) {
617 netif_device_attach(ndev);
618 napi_enable(&fep->napi);
619 netif_wake_queue(ndev);
620 netif_tx_unlock(ndev);
621 }
622 }
623
624 static void
625 fec_stop(struct net_device *ndev)
626 {
627 struct fec_enet_private *fep = netdev_priv(ndev);
628 const struct platform_device_id *id_entry =
629 platform_get_device_id(fep->pdev);
630 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
631
632 /* We cannot expect a graceful transmit stop without link !!! */
633 if (fep->link) {
634 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
635 udelay(10);
636 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
637 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
638 }
639
640 /* Whack a reset. We should wait for this. */
641 writel(1, fep->hwp + FEC_ECNTRL);
642 udelay(10);
643 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
644 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
645
646 /* We have to keep ENET enabled to have MII interrupt stay working */
647 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
648 writel(2, fep->hwp + FEC_ECNTRL);
649 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
650 }
651 }
652
653
654 static void
655 fec_timeout(struct net_device *ndev)
656 {
657 struct fec_enet_private *fep = netdev_priv(ndev);
658
659 ndev->stats.tx_errors++;
660
661 fep->delay_work.timeout = true;
662 schedule_delayed_work(&(fep->delay_work.delay_work), 0);
663 }
664
665 static void fec_enet_work(struct work_struct *work)
666 {
667 struct fec_enet_private *fep =
668 container_of(work,
669 struct fec_enet_private,
670 delay_work.delay_work.work);
671
672 if (fep->delay_work.timeout) {
673 fep->delay_work.timeout = false;
674 fec_restart(fep->netdev, fep->full_duplex);
675 netif_wake_queue(fep->netdev);
676 }
677 }
678
679 static void
680 fec_enet_tx(struct net_device *ndev)
681 {
682 struct fec_enet_private *fep;
683 struct bufdesc *bdp;
684 unsigned short status;
685 struct sk_buff *skb;
686 int index = 0;
687
688 fep = netdev_priv(ndev);
689 bdp = fep->dirty_tx;
690
691 /* get next bdp of dirty_tx */
692 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
693 bdp = fep->tx_bd_base;
694 else
695 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
696
697 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
698
699 /* current queue is empty */
700 if (bdp == fep->cur_tx)
701 break;
702
703 if (fep->bufdesc_ex)
704 index = (struct bufdesc_ex *)bdp -
705 (struct bufdesc_ex *)fep->tx_bd_base;
706 else
707 index = bdp - fep->tx_bd_base;
708
709 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
710 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
711 bdp->cbd_bufaddr = 0;
712
713 skb = fep->tx_skbuff[index];
714
715 /* Check for errors. */
716 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
717 BD_ENET_TX_RL | BD_ENET_TX_UN |
718 BD_ENET_TX_CSL)) {
719 ndev->stats.tx_errors++;
720 if (status & BD_ENET_TX_HB) /* No heartbeat */
721 ndev->stats.tx_heartbeat_errors++;
722 if (status & BD_ENET_TX_LC) /* Late collision */
723 ndev->stats.tx_window_errors++;
724 if (status & BD_ENET_TX_RL) /* Retrans limit */
725 ndev->stats.tx_aborted_errors++;
726 if (status & BD_ENET_TX_UN) /* Underrun */
727 ndev->stats.tx_fifo_errors++;
728 if (status & BD_ENET_TX_CSL) /* Carrier lost */
729 ndev->stats.tx_carrier_errors++;
730 } else {
731 ndev->stats.tx_packets++;
732 }
733
734 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
735 fep->bufdesc_ex) {
736 struct skb_shared_hwtstamps shhwtstamps;
737 unsigned long flags;
738 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
739
740 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
741 spin_lock_irqsave(&fep->tmreg_lock, flags);
742 shhwtstamps.hwtstamp = ns_to_ktime(
743 timecounter_cyc2time(&fep->tc, ebdp->ts));
744 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
745 skb_tstamp_tx(skb, &shhwtstamps);
746 }
747
748 if (status & BD_ENET_TX_READY)
749 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
750
751 /* Deferred means some collisions occurred during transmit,
752 * but we eventually sent the packet OK.
753 */
754 if (status & BD_ENET_TX_DEF)
755 ndev->stats.collisions++;
756
757 /* Free the sk buffer associated with this last transmit */
758 dev_kfree_skb_any(skb);
759 fep->tx_skbuff[index] = NULL;
760
761 fep->dirty_tx = bdp;
762
763 /* Update pointer to next buffer descriptor to be transmitted */
764 if (status & BD_ENET_TX_WRAP)
765 bdp = fep->tx_bd_base;
766 else
767 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
768
769 /* Since we have freed up a buffer, the ring is no longer full
770 */
771 if (fep->dirty_tx != fep->cur_tx) {
772 if (netif_queue_stopped(ndev))
773 netif_wake_queue(ndev);
774 }
775 }
776 return;
777 }
778
779
780 /* During a receive, the cur_rx points to the current incoming buffer.
781 * When we update through the ring, if the next incoming buffer has
782 * not been given to the system, we just set the empty indicator,
783 * effectively tossing the packet.
784 */
785 static int
786 fec_enet_rx(struct net_device *ndev, int budget)
787 {
788 struct fec_enet_private *fep = netdev_priv(ndev);
789 const struct platform_device_id *id_entry =
790 platform_get_device_id(fep->pdev);
791 struct bufdesc *bdp;
792 unsigned short status;
793 struct sk_buff *skb;
794 ushort pkt_len;
795 __u8 *data;
796 int pkt_received = 0;
797
798 #ifdef CONFIG_M532x
799 flush_cache_all();
800 #endif
801
802 /* First, grab all of the stats for the incoming packet.
803 * These get messed up if we get called due to a busy condition.
804 */
805 bdp = fep->cur_rx;
806
807 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
808
809 if (pkt_received >= budget)
810 break;
811 pkt_received++;
812
813 /* Since we have allocated space to hold a complete frame,
814 * the last indicator should be set.
815 */
816 if ((status & BD_ENET_RX_LAST) == 0)
817 netdev_err(ndev, "rcv is not +last\n");
818
819 if (!fep->opened)
820 goto rx_processing_done;
821
822 /* Check for errors. */
823 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
824 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
825 ndev->stats.rx_errors++;
826 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
827 /* Frame too long or too short. */
828 ndev->stats.rx_length_errors++;
829 }
830 if (status & BD_ENET_RX_NO) /* Frame alignment */
831 ndev->stats.rx_frame_errors++;
832 if (status & BD_ENET_RX_CR) /* CRC Error */
833 ndev->stats.rx_crc_errors++;
834 if (status & BD_ENET_RX_OV) /* FIFO overrun */
835 ndev->stats.rx_fifo_errors++;
836 }
837
838 /* Report late collisions as a frame error.
839 * On this error, the BD is closed, but we don't know what we
840 * have in the buffer. So, just drop this frame on the floor.
841 */
842 if (status & BD_ENET_RX_CL) {
843 ndev->stats.rx_errors++;
844 ndev->stats.rx_frame_errors++;
845 goto rx_processing_done;
846 }
847
848 /* Process the incoming frame. */
849 ndev->stats.rx_packets++;
850 pkt_len = bdp->cbd_datlen;
851 ndev->stats.rx_bytes += pkt_len;
852 data = (__u8*)__va(bdp->cbd_bufaddr);
853
854 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
855 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
856
857 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
858 swap_buffer(data, pkt_len);
859
860 /* This does 16 byte alignment, exactly what we need.
861 * The packet length includes FCS, but we don't want to
862 * include that when passing upstream as it messes up
863 * bridging applications.
864 */
865 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
866
867 if (unlikely(!skb)) {
868 ndev->stats.rx_dropped++;
869 } else {
870 skb_reserve(skb, NET_IP_ALIGN);
871 skb_put(skb, pkt_len - 4); /* Make room */
872 skb_copy_to_linear_data(skb, data, pkt_len - 4);
873 skb->protocol = eth_type_trans(skb, ndev);
874
875 /* Get receive timestamp from the skb */
876 if (fep->hwts_rx_en && fep->bufdesc_ex) {
877 struct skb_shared_hwtstamps *shhwtstamps =
878 skb_hwtstamps(skb);
879 unsigned long flags;
880 struct bufdesc_ex *ebdp =
881 (struct bufdesc_ex *)bdp;
882
883 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
884
885 spin_lock_irqsave(&fep->tmreg_lock, flags);
886 shhwtstamps->hwtstamp = ns_to_ktime(
887 timecounter_cyc2time(&fep->tc, ebdp->ts));
888 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
889 }
890
891 if (fep->bufdesc_ex &&
892 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
893 struct bufdesc_ex *ebdp =
894 (struct bufdesc_ex *)bdp;
895 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
896 /* don't check it */
897 skb->ip_summed = CHECKSUM_UNNECESSARY;
898 } else {
899 skb_checksum_none_assert(skb);
900 }
901 }
902
903 if (!skb_defer_rx_timestamp(skb))
904 napi_gro_receive(&fep->napi, skb);
905 }
906
907 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
908 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
909 rx_processing_done:
910 /* Clear the status flags for this buffer */
911 status &= ~BD_ENET_RX_STATS;
912
913 /* Mark the buffer empty */
914 status |= BD_ENET_RX_EMPTY;
915 bdp->cbd_sc = status;
916
917 if (fep->bufdesc_ex) {
918 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
919
920 ebdp->cbd_esc = BD_ENET_RX_INT;
921 ebdp->cbd_prot = 0;
922 ebdp->cbd_bdu = 0;
923 }
924
925 /* Update BD pointer to next entry */
926 if (status & BD_ENET_RX_WRAP)
927 bdp = fep->rx_bd_base;
928 else
929 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
930 /* Doing this here will keep the FEC running while we process
931 * incoming frames. On a heavily loaded network, we should be
932 * able to keep up at the expense of system resources.
933 */
934 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
935 }
936 fep->cur_rx = bdp;
937
938 return pkt_received;
939 }
940
941 static irqreturn_t
942 fec_enet_interrupt(int irq, void *dev_id)
943 {
944 struct net_device *ndev = dev_id;
945 struct fec_enet_private *fep = netdev_priv(ndev);
946 uint int_events;
947 irqreturn_t ret = IRQ_NONE;
948
949 do {
950 int_events = readl(fep->hwp + FEC_IEVENT);
951 writel(int_events, fep->hwp + FEC_IEVENT);
952
953 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
954 ret = IRQ_HANDLED;
955
956 /* Disable the RX interrupt */
957 if (napi_schedule_prep(&fep->napi)) {
958 writel(FEC_RX_DISABLED_IMASK,
959 fep->hwp + FEC_IMASK);
960 __napi_schedule(&fep->napi);
961 }
962 }
963
964 if (int_events & FEC_ENET_MII) {
965 ret = IRQ_HANDLED;
966 complete(&fep->mdio_done);
967 }
968 } while (int_events);
969
970 return ret;
971 }
972
973 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
974 {
975 struct net_device *ndev = napi->dev;
976 int pkts = fec_enet_rx(ndev, budget);
977 struct fec_enet_private *fep = netdev_priv(ndev);
978
979 fec_enet_tx(ndev);
980
981 if (pkts < budget) {
982 napi_complete(napi);
983 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
984 }
985 return pkts;
986 }
987
988 /* ------------------------------------------------------------------------- */
989 static void fec_get_mac(struct net_device *ndev)
990 {
991 struct fec_enet_private *fep = netdev_priv(ndev);
992 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
993 unsigned char *iap, tmpaddr[ETH_ALEN];
994
995 /*
996 * try to get mac address in following order:
997 *
998 * 1) module parameter via kernel command line in form
999 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1000 */
1001 iap = macaddr;
1002
1003 /*
1004 * 2) from device tree data
1005 */
1006 if (!is_valid_ether_addr(iap)) {
1007 struct device_node *np = fep->pdev->dev.of_node;
1008 if (np) {
1009 const char *mac = of_get_mac_address(np);
1010 if (mac)
1011 iap = (unsigned char *) mac;
1012 }
1013 }
1014
1015 /*
1016 * 3) from flash or fuse (via platform data)
1017 */
1018 if (!is_valid_ether_addr(iap)) {
1019 #ifdef CONFIG_M5272
1020 if (FEC_FLASHMAC)
1021 iap = (unsigned char *)FEC_FLASHMAC;
1022 #else
1023 if (pdata)
1024 iap = (unsigned char *)&pdata->mac;
1025 #endif
1026 }
1027
1028 /*
1029 * 4) FEC mac registers set by bootloader
1030 */
1031 if (!is_valid_ether_addr(iap)) {
1032 *((unsigned long *) &tmpaddr[0]) =
1033 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
1034 *((unsigned short *) &tmpaddr[4]) =
1035 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1036 iap = &tmpaddr[0];
1037 }
1038
1039 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1040
1041 /* Adjust MAC if using macaddr */
1042 if (iap == macaddr)
1043 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1044 }
1045
1046 /* ------------------------------------------------------------------------- */
1047
1048 /*
1049 * Phy section
1050 */
1051 static void fec_enet_adjust_link(struct net_device *ndev)
1052 {
1053 struct fec_enet_private *fep = netdev_priv(ndev);
1054 struct phy_device *phy_dev = fep->phy_dev;
1055 int status_change = 0;
1056
1057 /* Prevent a state halted on mii error */
1058 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1059 phy_dev->state = PHY_RESUMING;
1060 return;
1061 }
1062
1063 if (phy_dev->link) {
1064 if (!fep->link) {
1065 fep->link = phy_dev->link;
1066 status_change = 1;
1067 }
1068
1069 if (fep->full_duplex != phy_dev->duplex)
1070 status_change = 1;
1071
1072 if (phy_dev->speed != fep->speed) {
1073 fep->speed = phy_dev->speed;
1074 status_change = 1;
1075 }
1076
1077 /* if any of the above changed restart the FEC */
1078 if (status_change)
1079 fec_restart(ndev, phy_dev->duplex);
1080 } else {
1081 if (fep->link) {
1082 fec_stop(ndev);
1083 fep->link = phy_dev->link;
1084 status_change = 1;
1085 }
1086 }
1087
1088 if (status_change)
1089 phy_print_status(phy_dev);
1090 }
1091
1092 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1093 {
1094 struct fec_enet_private *fep = bus->priv;
1095 unsigned long time_left;
1096
1097 fep->mii_timeout = 0;
1098 init_completion(&fep->mdio_done);
1099
1100 /* start a read op */
1101 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1102 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1103 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1104
1105 /* wait for end of transfer */
1106 time_left = wait_for_completion_timeout(&fep->mdio_done,
1107 usecs_to_jiffies(FEC_MII_TIMEOUT));
1108 if (time_left == 0) {
1109 fep->mii_timeout = 1;
1110 netdev_err(fep->netdev, "MDIO read timeout\n");
1111 return -ETIMEDOUT;
1112 }
1113
1114 /* return value */
1115 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1116 }
1117
1118 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1119 u16 value)
1120 {
1121 struct fec_enet_private *fep = bus->priv;
1122 unsigned long time_left;
1123
1124 fep->mii_timeout = 0;
1125 init_completion(&fep->mdio_done);
1126
1127 /* start a write op */
1128 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1129 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1130 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1131 fep->hwp + FEC_MII_DATA);
1132
1133 /* wait for end of transfer */
1134 time_left = wait_for_completion_timeout(&fep->mdio_done,
1135 usecs_to_jiffies(FEC_MII_TIMEOUT));
1136 if (time_left == 0) {
1137 fep->mii_timeout = 1;
1138 netdev_err(fep->netdev, "MDIO write timeout\n");
1139 return -ETIMEDOUT;
1140 }
1141
1142 return 0;
1143 }
1144
1145 static int fec_enet_mdio_reset(struct mii_bus *bus)
1146 {
1147 return 0;
1148 }
1149
1150 static int fec_enet_mii_probe(struct net_device *ndev)
1151 {
1152 struct fec_enet_private *fep = netdev_priv(ndev);
1153 const struct platform_device_id *id_entry =
1154 platform_get_device_id(fep->pdev);
1155 struct phy_device *phy_dev = NULL;
1156 char mdio_bus_id[MII_BUS_ID_SIZE];
1157 char phy_name[MII_BUS_ID_SIZE + 3];
1158 int phy_id;
1159 int dev_id = fep->dev_id;
1160
1161 fep->phy_dev = NULL;
1162
1163 /* check for attached phy */
1164 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1165 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1166 continue;
1167 if (fep->mii_bus->phy_map[phy_id] == NULL)
1168 continue;
1169 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1170 continue;
1171 if (dev_id--)
1172 continue;
1173 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1174 break;
1175 }
1176
1177 if (phy_id >= PHY_MAX_ADDR) {
1178 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1179 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1180 phy_id = 0;
1181 }
1182
1183 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1184 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1185 fep->phy_interface);
1186 if (IS_ERR(phy_dev)) {
1187 netdev_err(ndev, "could not attach to PHY\n");
1188 return PTR_ERR(phy_dev);
1189 }
1190
1191 /* mask with MAC supported features */
1192 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1193 phy_dev->supported &= PHY_GBIT_FEATURES;
1194 phy_dev->supported |= SUPPORTED_Pause;
1195 }
1196 else
1197 phy_dev->supported &= PHY_BASIC_FEATURES;
1198
1199 phy_dev->advertising = phy_dev->supported;
1200
1201 fep->phy_dev = phy_dev;
1202 fep->link = 0;
1203 fep->full_duplex = 0;
1204
1205 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1206 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1207 fep->phy_dev->irq);
1208
1209 return 0;
1210 }
1211
1212 static int fec_enet_mii_init(struct platform_device *pdev)
1213 {
1214 static struct mii_bus *fec0_mii_bus;
1215 struct net_device *ndev = platform_get_drvdata(pdev);
1216 struct fec_enet_private *fep = netdev_priv(ndev);
1217 const struct platform_device_id *id_entry =
1218 platform_get_device_id(fep->pdev);
1219 int err = -ENXIO, i;
1220
1221 /*
1222 * The dual fec interfaces are not equivalent with enet-mac.
1223 * Here are the differences:
1224 *
1225 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1226 * - fec0 acts as the 1588 time master while fec1 is slave
1227 * - external phys can only be configured by fec0
1228 *
1229 * That is to say fec1 can not work independently. It only works
1230 * when fec0 is working. The reason behind this design is that the
1231 * second interface is added primarily for Switch mode.
1232 *
1233 * Because of the last point above, both phys are attached on fec0
1234 * mdio interface in board design, and need to be configured by
1235 * fec0 mii_bus.
1236 */
1237 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1238 /* fec1 uses fec0 mii_bus */
1239 if (mii_cnt && fec0_mii_bus) {
1240 fep->mii_bus = fec0_mii_bus;
1241 mii_cnt++;
1242 return 0;
1243 }
1244 return -ENOENT;
1245 }
1246
1247 fep->mii_timeout = 0;
1248
1249 /*
1250 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1251 *
1252 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1253 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1254 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1255 * document.
1256 */
1257 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1258 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1259 fep->phy_speed--;
1260 fep->phy_speed <<= 1;
1261 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1262
1263 fep->mii_bus = mdiobus_alloc();
1264 if (fep->mii_bus == NULL) {
1265 err = -ENOMEM;
1266 goto err_out;
1267 }
1268
1269 fep->mii_bus->name = "fec_enet_mii_bus";
1270 fep->mii_bus->read = fec_enet_mdio_read;
1271 fep->mii_bus->write = fec_enet_mdio_write;
1272 fep->mii_bus->reset = fec_enet_mdio_reset;
1273 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1274 pdev->name, fep->dev_id + 1);
1275 fep->mii_bus->priv = fep;
1276 fep->mii_bus->parent = &pdev->dev;
1277
1278 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1279 if (!fep->mii_bus->irq) {
1280 err = -ENOMEM;
1281 goto err_out_free_mdiobus;
1282 }
1283
1284 for (i = 0; i < PHY_MAX_ADDR; i++)
1285 fep->mii_bus->irq[i] = PHY_POLL;
1286
1287 if (mdiobus_register(fep->mii_bus))
1288 goto err_out_free_mdio_irq;
1289
1290 mii_cnt++;
1291
1292 /* save fec0 mii_bus */
1293 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1294 fec0_mii_bus = fep->mii_bus;
1295
1296 return 0;
1297
1298 err_out_free_mdio_irq:
1299 kfree(fep->mii_bus->irq);
1300 err_out_free_mdiobus:
1301 mdiobus_free(fep->mii_bus);
1302 err_out:
1303 return err;
1304 }
1305
1306 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1307 {
1308 if (--mii_cnt == 0) {
1309 mdiobus_unregister(fep->mii_bus);
1310 kfree(fep->mii_bus->irq);
1311 mdiobus_free(fep->mii_bus);
1312 }
1313 }
1314
1315 static int fec_enet_get_settings(struct net_device *ndev,
1316 struct ethtool_cmd *cmd)
1317 {
1318 struct fec_enet_private *fep = netdev_priv(ndev);
1319 struct phy_device *phydev = fep->phy_dev;
1320
1321 if (!phydev)
1322 return -ENODEV;
1323
1324 return phy_ethtool_gset(phydev, cmd);
1325 }
1326
1327 static int fec_enet_set_settings(struct net_device *ndev,
1328 struct ethtool_cmd *cmd)
1329 {
1330 struct fec_enet_private *fep = netdev_priv(ndev);
1331 struct phy_device *phydev = fep->phy_dev;
1332
1333 if (!phydev)
1334 return -ENODEV;
1335
1336 return phy_ethtool_sset(phydev, cmd);
1337 }
1338
1339 static void fec_enet_get_drvinfo(struct net_device *ndev,
1340 struct ethtool_drvinfo *info)
1341 {
1342 struct fec_enet_private *fep = netdev_priv(ndev);
1343
1344 strlcpy(info->driver, fep->pdev->dev.driver->name,
1345 sizeof(info->driver));
1346 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1347 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1348 }
1349
1350 static int fec_enet_get_ts_info(struct net_device *ndev,
1351 struct ethtool_ts_info *info)
1352 {
1353 struct fec_enet_private *fep = netdev_priv(ndev);
1354
1355 if (fep->bufdesc_ex) {
1356
1357 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1358 SOF_TIMESTAMPING_RX_SOFTWARE |
1359 SOF_TIMESTAMPING_SOFTWARE |
1360 SOF_TIMESTAMPING_TX_HARDWARE |
1361 SOF_TIMESTAMPING_RX_HARDWARE |
1362 SOF_TIMESTAMPING_RAW_HARDWARE;
1363 if (fep->ptp_clock)
1364 info->phc_index = ptp_clock_index(fep->ptp_clock);
1365 else
1366 info->phc_index = -1;
1367
1368 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1369 (1 << HWTSTAMP_TX_ON);
1370
1371 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1372 (1 << HWTSTAMP_FILTER_ALL);
1373 return 0;
1374 } else {
1375 return ethtool_op_get_ts_info(ndev, info);
1376 }
1377 }
1378
1379 static void fec_enet_get_pauseparam(struct net_device *ndev,
1380 struct ethtool_pauseparam *pause)
1381 {
1382 struct fec_enet_private *fep = netdev_priv(ndev);
1383
1384 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1385 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1386 pause->rx_pause = pause->tx_pause;
1387 }
1388
1389 static int fec_enet_set_pauseparam(struct net_device *ndev,
1390 struct ethtool_pauseparam *pause)
1391 {
1392 struct fec_enet_private *fep = netdev_priv(ndev);
1393
1394 if (pause->tx_pause != pause->rx_pause) {
1395 netdev_info(ndev,
1396 "hardware only support enable/disable both tx and rx");
1397 return -EINVAL;
1398 }
1399
1400 fep->pause_flag = 0;
1401
1402 /* tx pause must be same as rx pause */
1403 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1404 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1405
1406 if (pause->rx_pause || pause->autoneg) {
1407 fep->phy_dev->supported |= ADVERTISED_Pause;
1408 fep->phy_dev->advertising |= ADVERTISED_Pause;
1409 } else {
1410 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1411 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1412 }
1413
1414 if (pause->autoneg) {
1415 if (netif_running(ndev))
1416 fec_stop(ndev);
1417 phy_start_aneg(fep->phy_dev);
1418 }
1419 if (netif_running(ndev))
1420 fec_restart(ndev, 0);
1421
1422 return 0;
1423 }
1424
1425 static const struct ethtool_ops fec_enet_ethtool_ops = {
1426 .get_pauseparam = fec_enet_get_pauseparam,
1427 .set_pauseparam = fec_enet_set_pauseparam,
1428 .get_settings = fec_enet_get_settings,
1429 .set_settings = fec_enet_set_settings,
1430 .get_drvinfo = fec_enet_get_drvinfo,
1431 .get_link = ethtool_op_get_link,
1432 .get_ts_info = fec_enet_get_ts_info,
1433 };
1434
1435 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1436 {
1437 struct fec_enet_private *fep = netdev_priv(ndev);
1438 struct phy_device *phydev = fep->phy_dev;
1439
1440 if (!netif_running(ndev))
1441 return -EINVAL;
1442
1443 if (!phydev)
1444 return -ENODEV;
1445
1446 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
1447 return fec_ptp_ioctl(ndev, rq, cmd);
1448
1449 return phy_mii_ioctl(phydev, rq, cmd);
1450 }
1451
1452 static void fec_enet_free_buffers(struct net_device *ndev)
1453 {
1454 struct fec_enet_private *fep = netdev_priv(ndev);
1455 unsigned int i;
1456 struct sk_buff *skb;
1457 struct bufdesc *bdp;
1458
1459 bdp = fep->rx_bd_base;
1460 for (i = 0; i < RX_RING_SIZE; i++) {
1461 skb = fep->rx_skbuff[i];
1462
1463 if (bdp->cbd_bufaddr)
1464 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1465 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1466 if (skb)
1467 dev_kfree_skb(skb);
1468 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1469 }
1470
1471 bdp = fep->tx_bd_base;
1472 for (i = 0; i < TX_RING_SIZE; i++)
1473 kfree(fep->tx_bounce[i]);
1474 }
1475
1476 static int fec_enet_alloc_buffers(struct net_device *ndev)
1477 {
1478 struct fec_enet_private *fep = netdev_priv(ndev);
1479 unsigned int i;
1480 struct sk_buff *skb;
1481 struct bufdesc *bdp;
1482
1483 bdp = fep->rx_bd_base;
1484 for (i = 0; i < RX_RING_SIZE; i++) {
1485 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1486 if (!skb) {
1487 fec_enet_free_buffers(ndev);
1488 return -ENOMEM;
1489 }
1490 fep->rx_skbuff[i] = skb;
1491
1492 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1493 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1494 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1495
1496 if (fep->bufdesc_ex) {
1497 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1498 ebdp->cbd_esc = BD_ENET_RX_INT;
1499 }
1500
1501 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1502 }
1503
1504 /* Set the last buffer to wrap. */
1505 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1506 bdp->cbd_sc |= BD_SC_WRAP;
1507
1508 bdp = fep->tx_bd_base;
1509 for (i = 0; i < TX_RING_SIZE; i++) {
1510 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1511
1512 bdp->cbd_sc = 0;
1513 bdp->cbd_bufaddr = 0;
1514
1515 if (fep->bufdesc_ex) {
1516 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1517 ebdp->cbd_esc = BD_ENET_TX_INT;
1518 }
1519
1520 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1521 }
1522
1523 /* Set the last buffer to wrap. */
1524 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1525 bdp->cbd_sc |= BD_SC_WRAP;
1526
1527 return 0;
1528 }
1529
1530 static int
1531 fec_enet_open(struct net_device *ndev)
1532 {
1533 struct fec_enet_private *fep = netdev_priv(ndev);
1534 int ret;
1535
1536 napi_enable(&fep->napi);
1537
1538 /* I should reset the ring buffers here, but I don't yet know
1539 * a simple way to do that.
1540 */
1541
1542 ret = fec_enet_alloc_buffers(ndev);
1543 if (ret)
1544 return ret;
1545
1546 /* Probe and connect to PHY when open the interface */
1547 ret = fec_enet_mii_probe(ndev);
1548 if (ret) {
1549 fec_enet_free_buffers(ndev);
1550 return ret;
1551 }
1552 phy_start(fep->phy_dev);
1553 netif_start_queue(ndev);
1554 fep->opened = 1;
1555 return 0;
1556 }
1557
1558 static int
1559 fec_enet_close(struct net_device *ndev)
1560 {
1561 struct fec_enet_private *fep = netdev_priv(ndev);
1562
1563 /* Don't know what to do yet. */
1564 napi_disable(&fep->napi);
1565 fep->opened = 0;
1566 netif_stop_queue(ndev);
1567 fec_stop(ndev);
1568
1569 if (fep->phy_dev) {
1570 phy_stop(fep->phy_dev);
1571 phy_disconnect(fep->phy_dev);
1572 }
1573
1574 fec_enet_free_buffers(ndev);
1575
1576 return 0;
1577 }
1578
1579 /* Set or clear the multicast filter for this adaptor.
1580 * Skeleton taken from sunlance driver.
1581 * The CPM Ethernet implementation allows Multicast as well as individual
1582 * MAC address filtering. Some of the drivers check to make sure it is
1583 * a group multicast address, and discard those that are not. I guess I
1584 * will do the same for now, but just remove the test if you want
1585 * individual filtering as well (do the upper net layers want or support
1586 * this kind of feature?).
1587 */
1588
1589 #define HASH_BITS 6 /* #bits in hash */
1590 #define CRC32_POLY 0xEDB88320
1591
1592 static void set_multicast_list(struct net_device *ndev)
1593 {
1594 struct fec_enet_private *fep = netdev_priv(ndev);
1595 struct netdev_hw_addr *ha;
1596 unsigned int i, bit, data, crc, tmp;
1597 unsigned char hash;
1598
1599 if (ndev->flags & IFF_PROMISC) {
1600 tmp = readl(fep->hwp + FEC_R_CNTRL);
1601 tmp |= 0x8;
1602 writel(tmp, fep->hwp + FEC_R_CNTRL);
1603 return;
1604 }
1605
1606 tmp = readl(fep->hwp + FEC_R_CNTRL);
1607 tmp &= ~0x8;
1608 writel(tmp, fep->hwp + FEC_R_CNTRL);
1609
1610 if (ndev->flags & IFF_ALLMULTI) {
1611 /* Catch all multicast addresses, so set the
1612 * filter to all 1's
1613 */
1614 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1615 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1616
1617 return;
1618 }
1619
1620 /* Clear filter and add the addresses in hash register
1621 */
1622 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1623 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1624
1625 netdev_for_each_mc_addr(ha, ndev) {
1626 /* calculate crc32 value of mac address */
1627 crc = 0xffffffff;
1628
1629 for (i = 0; i < ndev->addr_len; i++) {
1630 data = ha->addr[i];
1631 for (bit = 0; bit < 8; bit++, data >>= 1) {
1632 crc = (crc >> 1) ^
1633 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1634 }
1635 }
1636
1637 /* only upper 6 bits (HASH_BITS) are used
1638 * which point to specific bit in he hash registers
1639 */
1640 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1641
1642 if (hash > 31) {
1643 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1644 tmp |= 1 << (hash - 32);
1645 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1646 } else {
1647 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1648 tmp |= 1 << hash;
1649 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1650 }
1651 }
1652 }
1653
1654 /* Set a MAC change in hardware. */
1655 static int
1656 fec_set_mac_address(struct net_device *ndev, void *p)
1657 {
1658 struct fec_enet_private *fep = netdev_priv(ndev);
1659 struct sockaddr *addr = p;
1660
1661 if (!is_valid_ether_addr(addr->sa_data))
1662 return -EADDRNOTAVAIL;
1663
1664 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1665
1666 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1667 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1668 fep->hwp + FEC_ADDR_LOW);
1669 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1670 fep->hwp + FEC_ADDR_HIGH);
1671 return 0;
1672 }
1673
1674 #ifdef CONFIG_NET_POLL_CONTROLLER
1675 /**
1676 * fec_poll_controller - FEC Poll controller function
1677 * @dev: The FEC network adapter
1678 *
1679 * Polled functionality used by netconsole and others in non interrupt mode
1680 *
1681 */
1682 static void fec_poll_controller(struct net_device *dev)
1683 {
1684 int i;
1685 struct fec_enet_private *fep = netdev_priv(dev);
1686
1687 for (i = 0; i < FEC_IRQ_NUM; i++) {
1688 if (fep->irq[i] > 0) {
1689 disable_irq(fep->irq[i]);
1690 fec_enet_interrupt(fep->irq[i], dev);
1691 enable_irq(fep->irq[i]);
1692 }
1693 }
1694 }
1695 #endif
1696
1697 static int fec_set_features(struct net_device *netdev,
1698 netdev_features_t features)
1699 {
1700 struct fec_enet_private *fep = netdev_priv(netdev);
1701 netdev_features_t changed = features ^ netdev->features;
1702
1703 netdev->features = features;
1704
1705 /* Receive checksum has been changed */
1706 if (changed & NETIF_F_RXCSUM) {
1707 if (features & NETIF_F_RXCSUM)
1708 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
1709 else
1710 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
1711
1712 if (netif_running(netdev)) {
1713 fec_stop(netdev);
1714 fec_restart(netdev, fep->phy_dev->duplex);
1715 netif_wake_queue(netdev);
1716 } else {
1717 fec_restart(netdev, fep->phy_dev->duplex);
1718 }
1719 }
1720
1721 return 0;
1722 }
1723
1724 static const struct net_device_ops fec_netdev_ops = {
1725 .ndo_open = fec_enet_open,
1726 .ndo_stop = fec_enet_close,
1727 .ndo_start_xmit = fec_enet_start_xmit,
1728 .ndo_set_rx_mode = set_multicast_list,
1729 .ndo_change_mtu = eth_change_mtu,
1730 .ndo_validate_addr = eth_validate_addr,
1731 .ndo_tx_timeout = fec_timeout,
1732 .ndo_set_mac_address = fec_set_mac_address,
1733 .ndo_do_ioctl = fec_enet_ioctl,
1734 #ifdef CONFIG_NET_POLL_CONTROLLER
1735 .ndo_poll_controller = fec_poll_controller,
1736 #endif
1737 .ndo_set_features = fec_set_features,
1738 };
1739
1740 /*
1741 * XXX: We need to clean up on failure exits here.
1742 *
1743 */
1744 static int fec_enet_init(struct net_device *ndev)
1745 {
1746 struct fec_enet_private *fep = netdev_priv(ndev);
1747 struct bufdesc *cbd_base;
1748
1749 /* Allocate memory for buffer descriptors. */
1750 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1751 GFP_KERNEL);
1752 if (!cbd_base)
1753 return -ENOMEM;
1754
1755 memset(cbd_base, 0, PAGE_SIZE);
1756
1757 fep->netdev = ndev;
1758
1759 /* Get the Ethernet address */
1760 fec_get_mac(ndev);
1761
1762 /* Set receive and transmit descriptor base. */
1763 fep->rx_bd_base = cbd_base;
1764 if (fep->bufdesc_ex)
1765 fep->tx_bd_base = (struct bufdesc *)
1766 (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE);
1767 else
1768 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1769
1770 /* The FEC Ethernet specific entries in the device structure */
1771 ndev->watchdog_timeo = TX_TIMEOUT;
1772 ndev->netdev_ops = &fec_netdev_ops;
1773 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1774
1775 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
1776 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
1777
1778 /* enable hw accelerator */
1779 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
1780 | NETIF_F_RXCSUM);
1781 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
1782 | NETIF_F_RXCSUM);
1783 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
1784
1785 fec_restart(ndev, 0);
1786
1787 return 0;
1788 }
1789
1790 #ifdef CONFIG_OF
1791 static void fec_reset_phy(struct platform_device *pdev)
1792 {
1793 int err, phy_reset;
1794 int msec = 1;
1795 struct device_node *np = pdev->dev.of_node;
1796
1797 if (!np)
1798 return;
1799
1800 of_property_read_u32(np, "phy-reset-duration", &msec);
1801 /* A sane reset duration should not be longer than 1s */
1802 if (msec > 1000)
1803 msec = 1;
1804
1805 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1806 if (!gpio_is_valid(phy_reset))
1807 return;
1808
1809 err = devm_gpio_request_one(&pdev->dev, phy_reset,
1810 GPIOF_OUT_INIT_LOW, "phy-reset");
1811 if (err) {
1812 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
1813 return;
1814 }
1815 msleep(msec);
1816 gpio_set_value(phy_reset, 1);
1817 }
1818 #else /* CONFIG_OF */
1819 static void fec_reset_phy(struct platform_device *pdev)
1820 {
1821 /*
1822 * In case of platform probe, the reset has been done
1823 * by machine code.
1824 */
1825 }
1826 #endif /* CONFIG_OF */
1827
1828 static int
1829 fec_probe(struct platform_device *pdev)
1830 {
1831 struct fec_enet_private *fep;
1832 struct fec_platform_data *pdata;
1833 struct net_device *ndev;
1834 int i, irq, ret = 0;
1835 struct resource *r;
1836 const struct of_device_id *of_id;
1837 static int dev_id;
1838 struct pinctrl *pinctrl;
1839 struct regulator *reg_phy;
1840
1841 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1842 if (of_id)
1843 pdev->id_entry = of_id->data;
1844
1845 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1846 if (!r)
1847 return -ENXIO;
1848
1849 /* Init network device */
1850 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1851 if (!ndev)
1852 return -ENOMEM;
1853
1854 SET_NETDEV_DEV(ndev, &pdev->dev);
1855
1856 /* setup board info structure */
1857 fep = netdev_priv(ndev);
1858
1859 /* default enable pause frame auto negotiation */
1860 if (pdev->id_entry &&
1861 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
1862 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
1863
1864 fep->hwp = devm_request_and_ioremap(&pdev->dev, r);
1865 fep->pdev = pdev;
1866 fep->dev_id = dev_id++;
1867
1868 fep->bufdesc_ex = 0;
1869
1870 if (!fep->hwp) {
1871 ret = -ENOMEM;
1872 goto failed_ioremap;
1873 }
1874
1875 platform_set_drvdata(pdev, ndev);
1876
1877 ret = of_get_phy_mode(pdev->dev.of_node);
1878 if (ret < 0) {
1879 pdata = pdev->dev.platform_data;
1880 if (pdata)
1881 fep->phy_interface = pdata->phy;
1882 else
1883 fep->phy_interface = PHY_INTERFACE_MODE_MII;
1884 } else {
1885 fep->phy_interface = ret;
1886 }
1887
1888 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1889 if (IS_ERR(pinctrl)) {
1890 ret = PTR_ERR(pinctrl);
1891 goto failed_pin;
1892 }
1893
1894 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1895 if (IS_ERR(fep->clk_ipg)) {
1896 ret = PTR_ERR(fep->clk_ipg);
1897 goto failed_clk;
1898 }
1899
1900 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1901 if (IS_ERR(fep->clk_ahb)) {
1902 ret = PTR_ERR(fep->clk_ahb);
1903 goto failed_clk;
1904 }
1905
1906 /* enet_out is optional, depends on board */
1907 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
1908 if (IS_ERR(fep->clk_enet_out))
1909 fep->clk_enet_out = NULL;
1910
1911 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
1912 fep->bufdesc_ex =
1913 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
1914 if (IS_ERR(fep->clk_ptp)) {
1915 fep->clk_ptp = NULL;
1916 fep->bufdesc_ex = 0;
1917 }
1918
1919 clk_prepare_enable(fep->clk_ahb);
1920 clk_prepare_enable(fep->clk_ipg);
1921 clk_prepare_enable(fep->clk_enet_out);
1922 clk_prepare_enable(fep->clk_ptp);
1923
1924 reg_phy = devm_regulator_get(&pdev->dev, "phy");
1925 if (!IS_ERR(reg_phy)) {
1926 ret = regulator_enable(reg_phy);
1927 if (ret) {
1928 dev_err(&pdev->dev,
1929 "Failed to enable phy regulator: %d\n", ret);
1930 goto failed_regulator;
1931 }
1932 }
1933
1934 fec_reset_phy(pdev);
1935
1936 if (fep->bufdesc_ex)
1937 fec_ptp_init(ndev, pdev);
1938
1939 ret = fec_enet_init(ndev);
1940 if (ret)
1941 goto failed_init;
1942
1943 for (i = 0; i < FEC_IRQ_NUM; i++) {
1944 irq = platform_get_irq(pdev, i);
1945 if (irq < 0) {
1946 if (i)
1947 break;
1948 ret = irq;
1949 goto failed_irq;
1950 }
1951 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1952 if (ret) {
1953 while (--i >= 0) {
1954 irq = platform_get_irq(pdev, i);
1955 free_irq(irq, ndev);
1956 }
1957 goto failed_irq;
1958 }
1959 }
1960
1961 ret = fec_enet_mii_init(pdev);
1962 if (ret)
1963 goto failed_mii_init;
1964
1965 /* Carrier starts down, phylib will bring it up */
1966 netif_carrier_off(ndev);
1967
1968 ret = register_netdev(ndev);
1969 if (ret)
1970 goto failed_register;
1971
1972 if (fep->bufdesc_ex && fep->ptp_clock)
1973 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
1974
1975 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
1976 return 0;
1977
1978 failed_register:
1979 fec_enet_mii_remove(fep);
1980 failed_mii_init:
1981 failed_init:
1982 for (i = 0; i < FEC_IRQ_NUM; i++) {
1983 irq = platform_get_irq(pdev, i);
1984 if (irq > 0)
1985 free_irq(irq, ndev);
1986 }
1987 failed_irq:
1988 failed_regulator:
1989 clk_disable_unprepare(fep->clk_ahb);
1990 clk_disable_unprepare(fep->clk_ipg);
1991 clk_disable_unprepare(fep->clk_enet_out);
1992 clk_disable_unprepare(fep->clk_ptp);
1993 failed_pin:
1994 failed_clk:
1995 failed_ioremap:
1996 free_netdev(ndev);
1997
1998 return ret;
1999 }
2000
2001 static int
2002 fec_drv_remove(struct platform_device *pdev)
2003 {
2004 struct net_device *ndev = platform_get_drvdata(pdev);
2005 struct fec_enet_private *fep = netdev_priv(ndev);
2006 int i;
2007
2008 cancel_delayed_work_sync(&(fep->delay_work.delay_work));
2009 unregister_netdev(ndev);
2010 fec_enet_mii_remove(fep);
2011 del_timer_sync(&fep->time_keep);
2012 clk_disable_unprepare(fep->clk_ptp);
2013 if (fep->ptp_clock)
2014 ptp_clock_unregister(fep->ptp_clock);
2015 clk_disable_unprepare(fep->clk_enet_out);
2016 clk_disable_unprepare(fep->clk_ahb);
2017 clk_disable_unprepare(fep->clk_ipg);
2018 for (i = 0; i < FEC_IRQ_NUM; i++) {
2019 int irq = platform_get_irq(pdev, i);
2020 if (irq > 0)
2021 free_irq(irq, ndev);
2022 }
2023 free_netdev(ndev);
2024
2025 platform_set_drvdata(pdev, NULL);
2026
2027 return 0;
2028 }
2029
2030 #ifdef CONFIG_PM_SLEEP
2031 static int
2032 fec_suspend(struct device *dev)
2033 {
2034 struct net_device *ndev = dev_get_drvdata(dev);
2035 struct fec_enet_private *fep = netdev_priv(ndev);
2036
2037 if (netif_running(ndev)) {
2038 fec_stop(ndev);
2039 netif_device_detach(ndev);
2040 }
2041 clk_disable_unprepare(fep->clk_enet_out);
2042 clk_disable_unprepare(fep->clk_ahb);
2043 clk_disable_unprepare(fep->clk_ipg);
2044
2045 return 0;
2046 }
2047
2048 static int
2049 fec_resume(struct device *dev)
2050 {
2051 struct net_device *ndev = dev_get_drvdata(dev);
2052 struct fec_enet_private *fep = netdev_priv(ndev);
2053
2054 clk_prepare_enable(fep->clk_enet_out);
2055 clk_prepare_enable(fep->clk_ahb);
2056 clk_prepare_enable(fep->clk_ipg);
2057 if (netif_running(ndev)) {
2058 fec_restart(ndev, fep->full_duplex);
2059 netif_device_attach(ndev);
2060 }
2061
2062 return 0;
2063 }
2064 #endif /* CONFIG_PM_SLEEP */
2065
2066 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
2067
2068 static struct platform_driver fec_driver = {
2069 .driver = {
2070 .name = DRIVER_NAME,
2071 .owner = THIS_MODULE,
2072 .pm = &fec_pm_ops,
2073 .of_match_table = fec_dt_ids,
2074 },
2075 .id_table = fec_devtype,
2076 .probe = fec_probe,
2077 .remove = fec_drv_remove,
2078 };
2079
2080 module_platform_driver(fec_driver);
2081
2082 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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