projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelv...
[deliverable/linux.git] / drivers / net / ethernet / freescale / fec_main.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/ptrace.h>
29 #include <linux/errno.h>
30 #include <linux/ioport.h>
31 #include <linux/slab.h>
32 #include <linux/interrupt.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/in.h>
38 #include <linux/ip.h>
39 #include <net/ip.h>
40 #include <net/tso.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/icmp.h>
44 #include <linux/spinlock.h>
45 #include <linux/workqueue.h>
46 #include <linux/bitops.h>
47 #include <linux/io.h>
48 #include <linux/irq.h>
49 #include <linux/clk.h>
50 #include <linux/platform_device.h>
51 #include <linux/mdio.h>
52 #include <linux/phy.h>
53 #include <linux/fec.h>
54 #include <linux/of.h>
55 #include <linux/of_device.h>
56 #include <linux/of_gpio.h>
57 #include <linux/of_mdio.h>
58 #include <linux/of_net.h>
59 #include <linux/regulator/consumer.h>
60 #include <linux/if_vlan.h>
61 #include <linux/pinctrl/consumer.h>
62 #include <linux/prefetch.h>
63
64 #include <asm/cacheflush.h>
65
66 #include "fec.h"
67
68 static void set_multicast_list(struct net_device *ndev);
69 static void fec_enet_itr_coal_init(struct net_device *ndev);
70
71 #define DRIVER_NAME "fec"
72
73 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
74
75 /* Pause frame feild and FIFO threshold */
76 #define FEC_ENET_FCE (1 << 5)
77 #define FEC_ENET_RSEM_V 0x84
78 #define FEC_ENET_RSFL_V 16
79 #define FEC_ENET_RAEM_V 0x8
80 #define FEC_ENET_RAFL_V 0x8
81 #define FEC_ENET_OPD_V 0xFFF0
82 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */
83
84 static struct platform_device_id fec_devtype[] = {
85 {
86 /* keep it for coldfire */
87 .name = DRIVER_NAME,
88 .driver_data = 0,
89 }, {
90 .name = "imx25-fec",
91 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_HAS_RACC,
92 }, {
93 .name = "imx27-fec",
94 .driver_data = FEC_QUIRK_HAS_RACC,
95 }, {
96 .name = "imx28-fec",
97 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
98 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC,
99 }, {
100 .name = "imx6q-fec",
101 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
102 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
103 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
104 FEC_QUIRK_HAS_RACC,
105 }, {
106 .name = "mvf600-fec",
107 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
108 }, {
109 .name = "imx6sx-fec",
110 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
111 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
112 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
113 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
114 FEC_QUIRK_HAS_RACC,
115 }, {
116 /* sentinel */
117 }
118 };
119 MODULE_DEVICE_TABLE(platform, fec_devtype);
120
121 enum imx_fec_type {
122 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
123 IMX27_FEC, /* runs on i.mx27/35/51 */
124 IMX28_FEC,
125 IMX6Q_FEC,
126 MVF600_FEC,
127 IMX6SX_FEC,
128 };
129
130 static const struct of_device_id fec_dt_ids[] = {
131 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
132 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
133 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
134 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
135 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
136 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
137 { /* sentinel */ }
138 };
139 MODULE_DEVICE_TABLE(of, fec_dt_ids);
140
141 static unsigned char macaddr[ETH_ALEN];
142 module_param_array(macaddr, byte, NULL, 0);
143 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
144
145 #if defined(CONFIG_M5272)
146 /*
147 * Some hardware gets it MAC address out of local flash memory.
148 * if this is non-zero then assume it is the address to get MAC from.
149 */
150 #if defined(CONFIG_NETtel)
151 #define FEC_FLASHMAC 0xf0006006
152 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
153 #define FEC_FLASHMAC 0xf0006000
154 #elif defined(CONFIG_CANCam)
155 #define FEC_FLASHMAC 0xf0020000
156 #elif defined (CONFIG_M5272C3)
157 #define FEC_FLASHMAC (0xffe04000 + 4)
158 #elif defined(CONFIG_MOD5272)
159 #define FEC_FLASHMAC 0xffc0406b
160 #else
161 #define FEC_FLASHMAC 0
162 #endif
163 #endif /* CONFIG_M5272 */
164
165 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
166 */
167 #define PKT_MAXBUF_SIZE 1522
168 #define PKT_MINBUF_SIZE 64
169 #define PKT_MAXBLR_SIZE 1536
170
171 /* FEC receive acceleration */
172 #define FEC_RACC_IPDIS (1 << 1)
173 #define FEC_RACC_PRODIS (1 << 2)
174 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
175
176 /*
177 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
178 * size bits. Other FEC hardware does not, so we need to take that into
179 * account when setting it.
180 */
181 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
182 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
183 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
184 #else
185 #define OPT_FRAME_SIZE 0
186 #endif
187
188 /* FEC MII MMFR bits definition */
189 #define FEC_MMFR_ST (1 << 30)
190 #define FEC_MMFR_OP_READ (2 << 28)
191 #define FEC_MMFR_OP_WRITE (1 << 28)
192 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
193 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
194 #define FEC_MMFR_TA (2 << 16)
195 #define FEC_MMFR_DATA(v) (v & 0xffff)
196 /* FEC ECR bits definition */
197 #define FEC_ECR_MAGICEN (1 << 2)
198 #define FEC_ECR_SLEEP (1 << 3)
199
200 #define FEC_MII_TIMEOUT 30000 /* us */
201
202 /* Transmitter timeout */
203 #define TX_TIMEOUT (2 * HZ)
204
205 #define FEC_PAUSE_FLAG_AUTONEG 0x1
206 #define FEC_PAUSE_FLAG_ENABLE 0x2
207 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
208 #define FEC_WOL_FLAG_ENABLE (0x1 << 1)
209 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
210
211 #define COPYBREAK_DEFAULT 256
212
213 #define TSO_HEADER_SIZE 128
214 /* Max number of allowed TCP segments for software TSO */
215 #define FEC_MAX_TSO_SEGS 100
216 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
217
218 #define IS_TSO_HEADER(txq, addr) \
219 ((addr >= txq->tso_hdrs_dma) && \
220 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
221
222 static int mii_cnt;
223
224 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
225 struct bufdesc_prop *bd)
226 {
227 return (bdp >= bd->last) ? bd->base
228 : (struct bufdesc *)(((unsigned)bdp) + bd->dsize);
229 }
230
231 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
232 struct bufdesc_prop *bd)
233 {
234 return (bdp <= bd->base) ? bd->last
235 : (struct bufdesc *)(((unsigned)bdp) - bd->dsize);
236 }
237
238 static int fec_enet_get_bd_index(struct bufdesc *bdp,
239 struct bufdesc_prop *bd)
240 {
241 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
242 }
243
244 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
245 {
246 int entries;
247
248 entries = (((const char *)txq->dirty_tx -
249 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
250
251 return entries >= 0 ? entries : entries + txq->bd.ring_size;
252 }
253
254 static void swap_buffer(void *bufaddr, int len)
255 {
256 int i;
257 unsigned int *buf = bufaddr;
258
259 for (i = 0; i < len; i += 4, buf++)
260 swab32s(buf);
261 }
262
263 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
264 {
265 int i;
266 unsigned int *src = src_buf;
267 unsigned int *dst = dst_buf;
268
269 for (i = 0; i < len; i += 4, src++, dst++)
270 *dst = swab32p(src);
271 }
272
273 static void fec_dump(struct net_device *ndev)
274 {
275 struct fec_enet_private *fep = netdev_priv(ndev);
276 struct bufdesc *bdp;
277 struct fec_enet_priv_tx_q *txq;
278 int index = 0;
279
280 netdev_info(ndev, "TX ring dump\n");
281 pr_info("Nr SC addr len SKB\n");
282
283 txq = fep->tx_queue[0];
284 bdp = txq->bd.base;
285
286 do {
287 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
288 index,
289 bdp == txq->bd.cur ? 'S' : ' ',
290 bdp == txq->dirty_tx ? 'H' : ' ',
291 fec16_to_cpu(bdp->cbd_sc),
292 fec32_to_cpu(bdp->cbd_bufaddr),
293 fec16_to_cpu(bdp->cbd_datlen),
294 txq->tx_skbuff[index]);
295 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
296 index++;
297 } while (bdp != txq->bd.base);
298 }
299
300 static inline bool is_ipv4_pkt(struct sk_buff *skb)
301 {
302 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
303 }
304
305 static int
306 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
307 {
308 /* Only run for packets requiring a checksum. */
309 if (skb->ip_summed != CHECKSUM_PARTIAL)
310 return 0;
311
312 if (unlikely(skb_cow_head(skb, 0)))
313 return -1;
314
315 if (is_ipv4_pkt(skb))
316 ip_hdr(skb)->check = 0;
317 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
318
319 return 0;
320 }
321
322 static struct bufdesc *
323 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
324 struct sk_buff *skb,
325 struct net_device *ndev)
326 {
327 struct fec_enet_private *fep = netdev_priv(ndev);
328 struct bufdesc *bdp = txq->bd.cur;
329 struct bufdesc_ex *ebdp;
330 int nr_frags = skb_shinfo(skb)->nr_frags;
331 int frag, frag_len;
332 unsigned short status;
333 unsigned int estatus = 0;
334 skb_frag_t *this_frag;
335 unsigned int index;
336 void *bufaddr;
337 dma_addr_t addr;
338 int i;
339
340 for (frag = 0; frag < nr_frags; frag++) {
341 this_frag = &skb_shinfo(skb)->frags[frag];
342 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
343 ebdp = (struct bufdesc_ex *)bdp;
344
345 status = fec16_to_cpu(bdp->cbd_sc);
346 status &= ~BD_ENET_TX_STATS;
347 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
348 frag_len = skb_shinfo(skb)->frags[frag].size;
349
350 /* Handle the last BD specially */
351 if (frag == nr_frags - 1) {
352 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
353 if (fep->bufdesc_ex) {
354 estatus |= BD_ENET_TX_INT;
355 if (unlikely(skb_shinfo(skb)->tx_flags &
356 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
357 estatus |= BD_ENET_TX_TS;
358 }
359 }
360
361 if (fep->bufdesc_ex) {
362 if (fep->quirks & FEC_QUIRK_HAS_AVB)
363 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
364 if (skb->ip_summed == CHECKSUM_PARTIAL)
365 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
366 ebdp->cbd_bdu = 0;
367 ebdp->cbd_esc = cpu_to_fec32(estatus);
368 }
369
370 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
371
372 index = fec_enet_get_bd_index(bdp, &txq->bd);
373 if (((unsigned long) bufaddr) & fep->tx_align ||
374 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
375 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
376 bufaddr = txq->tx_bounce[index];
377
378 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
379 swap_buffer(bufaddr, frag_len);
380 }
381
382 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
383 DMA_TO_DEVICE);
384 if (dma_mapping_error(&fep->pdev->dev, addr)) {
385 if (net_ratelimit())
386 netdev_err(ndev, "Tx DMA memory map failed\n");
387 goto dma_mapping_error;
388 }
389
390 bdp->cbd_bufaddr = cpu_to_fec32(addr);
391 bdp->cbd_datlen = cpu_to_fec16(frag_len);
392 /* Make sure the updates to rest of the descriptor are
393 * performed before transferring ownership.
394 */
395 wmb();
396 bdp->cbd_sc = cpu_to_fec16(status);
397 }
398
399 return bdp;
400 dma_mapping_error:
401 bdp = txq->bd.cur;
402 for (i = 0; i < frag; i++) {
403 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
404 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
405 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
406 }
407 return ERR_PTR(-ENOMEM);
408 }
409
410 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
411 struct sk_buff *skb, struct net_device *ndev)
412 {
413 struct fec_enet_private *fep = netdev_priv(ndev);
414 int nr_frags = skb_shinfo(skb)->nr_frags;
415 struct bufdesc *bdp, *last_bdp;
416 void *bufaddr;
417 dma_addr_t addr;
418 unsigned short status;
419 unsigned short buflen;
420 unsigned int estatus = 0;
421 unsigned int index;
422 int entries_free;
423
424 entries_free = fec_enet_get_free_txdesc_num(txq);
425 if (entries_free < MAX_SKB_FRAGS + 1) {
426 dev_kfree_skb_any(skb);
427 if (net_ratelimit())
428 netdev_err(ndev, "NOT enough BD for SG!\n");
429 return NETDEV_TX_OK;
430 }
431
432 /* Protocol checksum off-load for TCP and UDP. */
433 if (fec_enet_clear_csum(skb, ndev)) {
434 dev_kfree_skb_any(skb);
435 return NETDEV_TX_OK;
436 }
437
438 /* Fill in a Tx ring entry */
439 bdp = txq->bd.cur;
440 last_bdp = bdp;
441 status = fec16_to_cpu(bdp->cbd_sc);
442 status &= ~BD_ENET_TX_STATS;
443
444 /* Set buffer length and buffer pointer */
445 bufaddr = skb->data;
446 buflen = skb_headlen(skb);
447
448 index = fec_enet_get_bd_index(bdp, &txq->bd);
449 if (((unsigned long) bufaddr) & fep->tx_align ||
450 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
451 memcpy(txq->tx_bounce[index], skb->data, buflen);
452 bufaddr = txq->tx_bounce[index];
453
454 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
455 swap_buffer(bufaddr, buflen);
456 }
457
458 /* Push the data cache so the CPM does not get stale memory data. */
459 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
460 if (dma_mapping_error(&fep->pdev->dev, addr)) {
461 dev_kfree_skb_any(skb);
462 if (net_ratelimit())
463 netdev_err(ndev, "Tx DMA memory map failed\n");
464 return NETDEV_TX_OK;
465 }
466
467 if (nr_frags) {
468 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
469 if (IS_ERR(last_bdp)) {
470 dma_unmap_single(&fep->pdev->dev, addr,
471 buflen, DMA_TO_DEVICE);
472 dev_kfree_skb_any(skb);
473 return NETDEV_TX_OK;
474 }
475 } else {
476 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
477 if (fep->bufdesc_ex) {
478 estatus = BD_ENET_TX_INT;
479 if (unlikely(skb_shinfo(skb)->tx_flags &
480 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
481 estatus |= BD_ENET_TX_TS;
482 }
483 }
484 bdp->cbd_bufaddr = cpu_to_fec32(addr);
485 bdp->cbd_datlen = cpu_to_fec16(buflen);
486
487 if (fep->bufdesc_ex) {
488
489 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
490
491 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
492 fep->hwts_tx_en))
493 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
494
495 if (fep->quirks & FEC_QUIRK_HAS_AVB)
496 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
497
498 if (skb->ip_summed == CHECKSUM_PARTIAL)
499 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
500
501 ebdp->cbd_bdu = 0;
502 ebdp->cbd_esc = cpu_to_fec32(estatus);
503 }
504
505 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
506 /* Save skb pointer */
507 txq->tx_skbuff[index] = skb;
508
509 /* Make sure the updates to rest of the descriptor are performed before
510 * transferring ownership.
511 */
512 wmb();
513
514 /* Send it on its way. Tell FEC it's ready, interrupt when done,
515 * it's the last BD of the frame, and to put the CRC on the end.
516 */
517 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
518 bdp->cbd_sc = cpu_to_fec16(status);
519
520 /* If this was the last BD in the ring, start at the beginning again. */
521 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
522
523 skb_tx_timestamp(skb);
524
525 /* Make sure the update to bdp and tx_skbuff are performed before
526 * txq->bd.cur.
527 */
528 wmb();
529 txq->bd.cur = bdp;
530
531 /* Trigger transmission start */
532 writel(0, txq->bd.reg_desc_active);
533
534 return 0;
535 }
536
537 static int
538 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
539 struct net_device *ndev,
540 struct bufdesc *bdp, int index, char *data,
541 int size, bool last_tcp, bool is_last)
542 {
543 struct fec_enet_private *fep = netdev_priv(ndev);
544 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
545 unsigned short status;
546 unsigned int estatus = 0;
547 dma_addr_t addr;
548
549 status = fec16_to_cpu(bdp->cbd_sc);
550 status &= ~BD_ENET_TX_STATS;
551
552 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
553
554 if (((unsigned long) data) & fep->tx_align ||
555 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
556 memcpy(txq->tx_bounce[index], data, size);
557 data = txq->tx_bounce[index];
558
559 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
560 swap_buffer(data, size);
561 }
562
563 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
564 if (dma_mapping_error(&fep->pdev->dev, addr)) {
565 dev_kfree_skb_any(skb);
566 if (net_ratelimit())
567 netdev_err(ndev, "Tx DMA memory map failed\n");
568 return NETDEV_TX_BUSY;
569 }
570
571 bdp->cbd_datlen = cpu_to_fec16(size);
572 bdp->cbd_bufaddr = cpu_to_fec32(addr);
573
574 if (fep->bufdesc_ex) {
575 if (fep->quirks & FEC_QUIRK_HAS_AVB)
576 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
577 if (skb->ip_summed == CHECKSUM_PARTIAL)
578 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
579 ebdp->cbd_bdu = 0;
580 ebdp->cbd_esc = cpu_to_fec32(estatus);
581 }
582
583 /* Handle the last BD specially */
584 if (last_tcp)
585 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
586 if (is_last) {
587 status |= BD_ENET_TX_INTR;
588 if (fep->bufdesc_ex)
589 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
590 }
591
592 bdp->cbd_sc = cpu_to_fec16(status);
593
594 return 0;
595 }
596
597 static int
598 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
599 struct sk_buff *skb, struct net_device *ndev,
600 struct bufdesc *bdp, int index)
601 {
602 struct fec_enet_private *fep = netdev_priv(ndev);
603 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
604 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
605 void *bufaddr;
606 unsigned long dmabuf;
607 unsigned short status;
608 unsigned int estatus = 0;
609
610 status = fec16_to_cpu(bdp->cbd_sc);
611 status &= ~BD_ENET_TX_STATS;
612 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
613
614 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
615 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
616 if (((unsigned long)bufaddr) & fep->tx_align ||
617 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
618 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
619 bufaddr = txq->tx_bounce[index];
620
621 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
622 swap_buffer(bufaddr, hdr_len);
623
624 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
625 hdr_len, DMA_TO_DEVICE);
626 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
627 dev_kfree_skb_any(skb);
628 if (net_ratelimit())
629 netdev_err(ndev, "Tx DMA memory map failed\n");
630 return NETDEV_TX_BUSY;
631 }
632 }
633
634 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
635 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
636
637 if (fep->bufdesc_ex) {
638 if (fep->quirks & FEC_QUIRK_HAS_AVB)
639 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
640 if (skb->ip_summed == CHECKSUM_PARTIAL)
641 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
642 ebdp->cbd_bdu = 0;
643 ebdp->cbd_esc = cpu_to_fec32(estatus);
644 }
645
646 bdp->cbd_sc = cpu_to_fec16(status);
647
648 return 0;
649 }
650
651 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
652 struct sk_buff *skb,
653 struct net_device *ndev)
654 {
655 struct fec_enet_private *fep = netdev_priv(ndev);
656 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
657 int total_len, data_left;
658 struct bufdesc *bdp = txq->bd.cur;
659 struct tso_t tso;
660 unsigned int index = 0;
661 int ret;
662
663 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
664 dev_kfree_skb_any(skb);
665 if (net_ratelimit())
666 netdev_err(ndev, "NOT enough BD for TSO!\n");
667 return NETDEV_TX_OK;
668 }
669
670 /* Protocol checksum off-load for TCP and UDP. */
671 if (fec_enet_clear_csum(skb, ndev)) {
672 dev_kfree_skb_any(skb);
673 return NETDEV_TX_OK;
674 }
675
676 /* Initialize the TSO handler, and prepare the first payload */
677 tso_start(skb, &tso);
678
679 total_len = skb->len - hdr_len;
680 while (total_len > 0) {
681 char *hdr;
682
683 index = fec_enet_get_bd_index(bdp, &txq->bd);
684 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
685 total_len -= data_left;
686
687 /* prepare packet headers: MAC + IP + TCP */
688 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
689 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
690 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
691 if (ret)
692 goto err_release;
693
694 while (data_left > 0) {
695 int size;
696
697 size = min_t(int, tso.size, data_left);
698 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
699 index = fec_enet_get_bd_index(bdp, &txq->bd);
700 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
701 bdp, index,
702 tso.data, size,
703 size == data_left,
704 total_len == 0);
705 if (ret)
706 goto err_release;
707
708 data_left -= size;
709 tso_build_data(skb, &tso, size);
710 }
711
712 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
713 }
714
715 /* Save skb pointer */
716 txq->tx_skbuff[index] = skb;
717
718 skb_tx_timestamp(skb);
719 txq->bd.cur = bdp;
720
721 /* Trigger transmission start */
722 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
723 !readl(txq->bd.reg_desc_active) ||
724 !readl(txq->bd.reg_desc_active) ||
725 !readl(txq->bd.reg_desc_active) ||
726 !readl(txq->bd.reg_desc_active))
727 writel(0, txq->bd.reg_desc_active);
728
729 return 0;
730
731 err_release:
732 /* TODO: Release all used data descriptors for TSO */
733 return ret;
734 }
735
736 static netdev_tx_t
737 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
738 {
739 struct fec_enet_private *fep = netdev_priv(ndev);
740 int entries_free;
741 unsigned short queue;
742 struct fec_enet_priv_tx_q *txq;
743 struct netdev_queue *nq;
744 int ret;
745
746 queue = skb_get_queue_mapping(skb);
747 txq = fep->tx_queue[queue];
748 nq = netdev_get_tx_queue(ndev, queue);
749
750 if (skb_is_gso(skb))
751 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
752 else
753 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
754 if (ret)
755 return ret;
756
757 entries_free = fec_enet_get_free_txdesc_num(txq);
758 if (entries_free <= txq->tx_stop_threshold)
759 netif_tx_stop_queue(nq);
760
761 return NETDEV_TX_OK;
762 }
763
764 /* Init RX & TX buffer descriptors
765 */
766 static void fec_enet_bd_init(struct net_device *dev)
767 {
768 struct fec_enet_private *fep = netdev_priv(dev);
769 struct fec_enet_priv_tx_q *txq;
770 struct fec_enet_priv_rx_q *rxq;
771 struct bufdesc *bdp;
772 unsigned int i;
773 unsigned int q;
774
775 for (q = 0; q < fep->num_rx_queues; q++) {
776 /* Initialize the receive buffer descriptors. */
777 rxq = fep->rx_queue[q];
778 bdp = rxq->bd.base;
779
780 for (i = 0; i < rxq->bd.ring_size; i++) {
781
782 /* Initialize the BD for every fragment in the page. */
783 if (bdp->cbd_bufaddr)
784 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
785 else
786 bdp->cbd_sc = cpu_to_fec16(0);
787 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
788 }
789
790 /* Set the last buffer to wrap */
791 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
792 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
793
794 rxq->bd.cur = rxq->bd.base;
795 }
796
797 for (q = 0; q < fep->num_tx_queues; q++) {
798 /* ...and the same for transmit */
799 txq = fep->tx_queue[q];
800 bdp = txq->bd.base;
801 txq->bd.cur = bdp;
802
803 for (i = 0; i < txq->bd.ring_size; i++) {
804 /* Initialize the BD for every fragment in the page. */
805 bdp->cbd_sc = cpu_to_fec16(0);
806 if (txq->tx_skbuff[i]) {
807 dev_kfree_skb_any(txq->tx_skbuff[i]);
808 txq->tx_skbuff[i] = NULL;
809 }
810 bdp->cbd_bufaddr = cpu_to_fec32(0);
811 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
812 }
813
814 /* Set the last buffer to wrap */
815 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
816 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
817 txq->dirty_tx = bdp;
818 }
819 }
820
821 static void fec_enet_active_rxring(struct net_device *ndev)
822 {
823 struct fec_enet_private *fep = netdev_priv(ndev);
824 int i;
825
826 for (i = 0; i < fep->num_rx_queues; i++)
827 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
828 }
829
830 static void fec_enet_enable_ring(struct net_device *ndev)
831 {
832 struct fec_enet_private *fep = netdev_priv(ndev);
833 struct fec_enet_priv_tx_q *txq;
834 struct fec_enet_priv_rx_q *rxq;
835 int i;
836
837 for (i = 0; i < fep->num_rx_queues; i++) {
838 rxq = fep->rx_queue[i];
839 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
840 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
841
842 /* enable DMA1/2 */
843 if (i)
844 writel(RCMR_MATCHEN | RCMR_CMP(i),
845 fep->hwp + FEC_RCMR(i));
846 }
847
848 for (i = 0; i < fep->num_tx_queues; i++) {
849 txq = fep->tx_queue[i];
850 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
851
852 /* enable DMA1/2 */
853 if (i)
854 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
855 fep->hwp + FEC_DMA_CFG(i));
856 }
857 }
858
859 static void fec_enet_reset_skb(struct net_device *ndev)
860 {
861 struct fec_enet_private *fep = netdev_priv(ndev);
862 struct fec_enet_priv_tx_q *txq;
863 int i, j;
864
865 for (i = 0; i < fep->num_tx_queues; i++) {
866 txq = fep->tx_queue[i];
867
868 for (j = 0; j < txq->bd.ring_size; j++) {
869 if (txq->tx_skbuff[j]) {
870 dev_kfree_skb_any(txq->tx_skbuff[j]);
871 txq->tx_skbuff[j] = NULL;
872 }
873 }
874 }
875 }
876
877 /*
878 * This function is called to start or restart the FEC during a link
879 * change, transmit timeout, or to reconfigure the FEC. The network
880 * packet processing for this device must be stopped before this call.
881 */
882 static void
883 fec_restart(struct net_device *ndev)
884 {
885 struct fec_enet_private *fep = netdev_priv(ndev);
886 u32 val;
887 u32 temp_mac[2];
888 u32 rcntl = OPT_FRAME_SIZE | 0x04;
889 u32 ecntl = 0x2; /* ETHEREN */
890
891 /* Whack a reset. We should wait for this.
892 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
893 * instead of reset MAC itself.
894 */
895 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
896 writel(0, fep->hwp + FEC_ECNTRL);
897 } else {
898 writel(1, fep->hwp + FEC_ECNTRL);
899 udelay(10);
900 }
901
902 /*
903 * enet-mac reset will reset mac address registers too,
904 * so need to reconfigure it.
905 */
906 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
907 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
908 writel((__force u32)cpu_to_be32(temp_mac[0]),
909 fep->hwp + FEC_ADDR_LOW);
910 writel((__force u32)cpu_to_be32(temp_mac[1]),
911 fep->hwp + FEC_ADDR_HIGH);
912 }
913
914 /* Clear any outstanding interrupt. */
915 writel(0xffffffff, fep->hwp + FEC_IEVENT);
916
917 fec_enet_bd_init(ndev);
918
919 fec_enet_enable_ring(ndev);
920
921 /* Reset tx SKB buffers. */
922 fec_enet_reset_skb(ndev);
923
924 /* Enable MII mode */
925 if (fep->full_duplex == DUPLEX_FULL) {
926 /* FD enable */
927 writel(0x04, fep->hwp + FEC_X_CNTRL);
928 } else {
929 /* No Rcv on Xmit */
930 rcntl |= 0x02;
931 writel(0x0, fep->hwp + FEC_X_CNTRL);
932 }
933
934 /* Set MII speed */
935 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
936
937 #if !defined(CONFIG_M5272)
938 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
939 /* set RX checksum */
940 val = readl(fep->hwp + FEC_RACC);
941 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
942 val |= FEC_RACC_OPTIONS;
943 else
944 val &= ~FEC_RACC_OPTIONS;
945 writel(val, fep->hwp + FEC_RACC);
946 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
947 }
948 #endif
949
950 /*
951 * The phy interface and speed need to get configured
952 * differently on enet-mac.
953 */
954 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
955 /* Enable flow control and length check */
956 rcntl |= 0x40000000 | 0x00000020;
957
958 /* RGMII, RMII or MII */
959 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
960 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
961 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
962 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
963 rcntl |= (1 << 6);
964 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
965 rcntl |= (1 << 8);
966 else
967 rcntl &= ~(1 << 8);
968
969 /* 1G, 100M or 10M */
970 if (ndev->phydev) {
971 if (ndev->phydev->speed == SPEED_1000)
972 ecntl |= (1 << 5);
973 else if (ndev->phydev->speed == SPEED_100)
974 rcntl &= ~(1 << 9);
975 else
976 rcntl |= (1 << 9);
977 }
978 } else {
979 #ifdef FEC_MIIGSK_ENR
980 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
981 u32 cfgr;
982 /* disable the gasket and wait */
983 writel(0, fep->hwp + FEC_MIIGSK_ENR);
984 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
985 udelay(1);
986
987 /*
988 * configure the gasket:
989 * RMII, 50 MHz, no loopback, no echo
990 * MII, 25 MHz, no loopback, no echo
991 */
992 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
993 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
994 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
995 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
996 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
997
998 /* re-enable the gasket */
999 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1000 }
1001 #endif
1002 }
1003
1004 #if !defined(CONFIG_M5272)
1005 /* enable pause frame*/
1006 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1007 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1008 ndev->phydev && ndev->phydev->pause)) {
1009 rcntl |= FEC_ENET_FCE;
1010
1011 /* set FIFO threshold parameter to reduce overrun */
1012 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1013 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1014 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1015 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1016
1017 /* OPD */
1018 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1019 } else {
1020 rcntl &= ~FEC_ENET_FCE;
1021 }
1022 #endif /* !defined(CONFIG_M5272) */
1023
1024 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1025
1026 /* Setup multicast filter. */
1027 set_multicast_list(ndev);
1028 #ifndef CONFIG_M5272
1029 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1030 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1031 #endif
1032
1033 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1034 /* enable ENET endian swap */
1035 ecntl |= (1 << 8);
1036 /* enable ENET store and forward mode */
1037 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1038 }
1039
1040 if (fep->bufdesc_ex)
1041 ecntl |= (1 << 4);
1042
1043 #ifndef CONFIG_M5272
1044 /* Enable the MIB statistic event counters */
1045 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1046 #endif
1047
1048 /* And last, enable the transmit and receive processing */
1049 writel(ecntl, fep->hwp + FEC_ECNTRL);
1050 fec_enet_active_rxring(ndev);
1051
1052 if (fep->bufdesc_ex)
1053 fec_ptp_start_cyclecounter(ndev);
1054
1055 /* Enable interrupts we wish to service */
1056 if (fep->link)
1057 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1058 else
1059 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1060
1061 /* Init the interrupt coalescing */
1062 fec_enet_itr_coal_init(ndev);
1063
1064 }
1065
1066 static void
1067 fec_stop(struct net_device *ndev)
1068 {
1069 struct fec_enet_private *fep = netdev_priv(ndev);
1070 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1071 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1072 u32 val;
1073
1074 /* We cannot expect a graceful transmit stop without link !!! */
1075 if (fep->link) {
1076 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1077 udelay(10);
1078 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1079 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1080 }
1081
1082 /* Whack a reset. We should wait for this.
1083 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1084 * instead of reset MAC itself.
1085 */
1086 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1087 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1088 writel(0, fep->hwp + FEC_ECNTRL);
1089 } else {
1090 writel(1, fep->hwp + FEC_ECNTRL);
1091 udelay(10);
1092 }
1093 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1094 } else {
1095 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1096 val = readl(fep->hwp + FEC_ECNTRL);
1097 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1098 writel(val, fep->hwp + FEC_ECNTRL);
1099
1100 if (pdata && pdata->sleep_mode_enable)
1101 pdata->sleep_mode_enable(true);
1102 }
1103 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1104
1105 /* We have to keep ENET enabled to have MII interrupt stay working */
1106 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1107 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1108 writel(2, fep->hwp + FEC_ECNTRL);
1109 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1110 }
1111 }
1112
1113
1114 static void
1115 fec_timeout(struct net_device *ndev)
1116 {
1117 struct fec_enet_private *fep = netdev_priv(ndev);
1118
1119 fec_dump(ndev);
1120
1121 ndev->stats.tx_errors++;
1122
1123 schedule_work(&fep->tx_timeout_work);
1124 }
1125
1126 static void fec_enet_timeout_work(struct work_struct *work)
1127 {
1128 struct fec_enet_private *fep =
1129 container_of(work, struct fec_enet_private, tx_timeout_work);
1130 struct net_device *ndev = fep->netdev;
1131
1132 rtnl_lock();
1133 if (netif_device_present(ndev) || netif_running(ndev)) {
1134 napi_disable(&fep->napi);
1135 netif_tx_lock_bh(ndev);
1136 fec_restart(ndev);
1137 netif_wake_queue(ndev);
1138 netif_tx_unlock_bh(ndev);
1139 napi_enable(&fep->napi);
1140 }
1141 rtnl_unlock();
1142 }
1143
1144 static void
1145 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1146 struct skb_shared_hwtstamps *hwtstamps)
1147 {
1148 unsigned long flags;
1149 u64 ns;
1150
1151 spin_lock_irqsave(&fep->tmreg_lock, flags);
1152 ns = timecounter_cyc2time(&fep->tc, ts);
1153 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1154
1155 memset(hwtstamps, 0, sizeof(*hwtstamps));
1156 hwtstamps->hwtstamp = ns_to_ktime(ns);
1157 }
1158
1159 static void
1160 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1161 {
1162 struct fec_enet_private *fep;
1163 struct bufdesc *bdp;
1164 unsigned short status;
1165 struct sk_buff *skb;
1166 struct fec_enet_priv_tx_q *txq;
1167 struct netdev_queue *nq;
1168 int index = 0;
1169 int entries_free;
1170
1171 fep = netdev_priv(ndev);
1172
1173 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1174
1175 txq = fep->tx_queue[queue_id];
1176 /* get next bdp of dirty_tx */
1177 nq = netdev_get_tx_queue(ndev, queue_id);
1178 bdp = txq->dirty_tx;
1179
1180 /* get next bdp of dirty_tx */
1181 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1182
1183 while (bdp != READ_ONCE(txq->bd.cur)) {
1184 /* Order the load of bd.cur and cbd_sc */
1185 rmb();
1186 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1187 if (status & BD_ENET_TX_READY)
1188 break;
1189
1190 index = fec_enet_get_bd_index(bdp, &txq->bd);
1191
1192 skb = txq->tx_skbuff[index];
1193 txq->tx_skbuff[index] = NULL;
1194 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1195 dma_unmap_single(&fep->pdev->dev,
1196 fec32_to_cpu(bdp->cbd_bufaddr),
1197 fec16_to_cpu(bdp->cbd_datlen),
1198 DMA_TO_DEVICE);
1199 bdp->cbd_bufaddr = cpu_to_fec32(0);
1200 if (!skb) {
1201 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1202 continue;
1203 }
1204
1205 /* Check for errors. */
1206 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1207 BD_ENET_TX_RL | BD_ENET_TX_UN |
1208 BD_ENET_TX_CSL)) {
1209 ndev->stats.tx_errors++;
1210 if (status & BD_ENET_TX_HB) /* No heartbeat */
1211 ndev->stats.tx_heartbeat_errors++;
1212 if (status & BD_ENET_TX_LC) /* Late collision */
1213 ndev->stats.tx_window_errors++;
1214 if (status & BD_ENET_TX_RL) /* Retrans limit */
1215 ndev->stats.tx_aborted_errors++;
1216 if (status & BD_ENET_TX_UN) /* Underrun */
1217 ndev->stats.tx_fifo_errors++;
1218 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1219 ndev->stats.tx_carrier_errors++;
1220 } else {
1221 ndev->stats.tx_packets++;
1222 ndev->stats.tx_bytes += skb->len;
1223 }
1224
1225 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1226 fep->bufdesc_ex) {
1227 struct skb_shared_hwtstamps shhwtstamps;
1228 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1229
1230 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1231 skb_tstamp_tx(skb, &shhwtstamps);
1232 }
1233
1234 /* Deferred means some collisions occurred during transmit,
1235 * but we eventually sent the packet OK.
1236 */
1237 if (status & BD_ENET_TX_DEF)
1238 ndev->stats.collisions++;
1239
1240 /* Free the sk buffer associated with this last transmit */
1241 dev_kfree_skb_any(skb);
1242
1243 /* Make sure the update to bdp and tx_skbuff are performed
1244 * before dirty_tx
1245 */
1246 wmb();
1247 txq->dirty_tx = bdp;
1248
1249 /* Update pointer to next buffer descriptor to be transmitted */
1250 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1251
1252 /* Since we have freed up a buffer, the ring is no longer full
1253 */
1254 if (netif_queue_stopped(ndev)) {
1255 entries_free = fec_enet_get_free_txdesc_num(txq);
1256 if (entries_free >= txq->tx_wake_threshold)
1257 netif_tx_wake_queue(nq);
1258 }
1259 }
1260
1261 /* ERR006538: Keep the transmitter going */
1262 if (bdp != txq->bd.cur &&
1263 readl(txq->bd.reg_desc_active) == 0)
1264 writel(0, txq->bd.reg_desc_active);
1265 }
1266
1267 static void
1268 fec_enet_tx(struct net_device *ndev)
1269 {
1270 struct fec_enet_private *fep = netdev_priv(ndev);
1271 u16 queue_id;
1272 /* First process class A queue, then Class B and Best Effort queue */
1273 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1274 clear_bit(queue_id, &fep->work_tx);
1275 fec_enet_tx_queue(ndev, queue_id);
1276 }
1277 return;
1278 }
1279
1280 static int
1281 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1282 {
1283 struct fec_enet_private *fep = netdev_priv(ndev);
1284 int off;
1285
1286 off = ((unsigned long)skb->data) & fep->rx_align;
1287 if (off)
1288 skb_reserve(skb, fep->rx_align + 1 - off);
1289
1290 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1291 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1292 if (net_ratelimit())
1293 netdev_err(ndev, "Rx DMA memory map failed\n");
1294 return -ENOMEM;
1295 }
1296
1297 return 0;
1298 }
1299
1300 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1301 struct bufdesc *bdp, u32 length, bool swap)
1302 {
1303 struct fec_enet_private *fep = netdev_priv(ndev);
1304 struct sk_buff *new_skb;
1305
1306 if (length > fep->rx_copybreak)
1307 return false;
1308
1309 new_skb = netdev_alloc_skb(ndev, length);
1310 if (!new_skb)
1311 return false;
1312
1313 dma_sync_single_for_cpu(&fep->pdev->dev,
1314 fec32_to_cpu(bdp->cbd_bufaddr),
1315 FEC_ENET_RX_FRSIZE - fep->rx_align,
1316 DMA_FROM_DEVICE);
1317 if (!swap)
1318 memcpy(new_skb->data, (*skb)->data, length);
1319 else
1320 swap_buffer2(new_skb->data, (*skb)->data, length);
1321 *skb = new_skb;
1322
1323 return true;
1324 }
1325
1326 /* During a receive, the bd_rx.cur points to the current incoming buffer.
1327 * When we update through the ring, if the next incoming buffer has
1328 * not been given to the system, we just set the empty indicator,
1329 * effectively tossing the packet.
1330 */
1331 static int
1332 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1333 {
1334 struct fec_enet_private *fep = netdev_priv(ndev);
1335 struct fec_enet_priv_rx_q *rxq;
1336 struct bufdesc *bdp;
1337 unsigned short status;
1338 struct sk_buff *skb_new = NULL;
1339 struct sk_buff *skb;
1340 ushort pkt_len;
1341 __u8 *data;
1342 int pkt_received = 0;
1343 struct bufdesc_ex *ebdp = NULL;
1344 bool vlan_packet_rcvd = false;
1345 u16 vlan_tag;
1346 int index = 0;
1347 bool is_copybreak;
1348 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1349
1350 #ifdef CONFIG_M532x
1351 flush_cache_all();
1352 #endif
1353 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1354 rxq = fep->rx_queue[queue_id];
1355
1356 /* First, grab all of the stats for the incoming packet.
1357 * These get messed up if we get called due to a busy condition.
1358 */
1359 bdp = rxq->bd.cur;
1360
1361 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1362
1363 if (pkt_received >= budget)
1364 break;
1365 pkt_received++;
1366
1367 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1368
1369 /* Check for errors. */
1370 status ^= BD_ENET_RX_LAST;
1371 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1372 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1373 BD_ENET_RX_CL)) {
1374 ndev->stats.rx_errors++;
1375 if (status & BD_ENET_RX_OV) {
1376 /* FIFO overrun */
1377 ndev->stats.rx_fifo_errors++;
1378 goto rx_processing_done;
1379 }
1380 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1381 | BD_ENET_RX_LAST)) {
1382 /* Frame too long or too short. */
1383 ndev->stats.rx_length_errors++;
1384 if (status & BD_ENET_RX_LAST)
1385 netdev_err(ndev, "rcv is not +last\n");
1386 }
1387 if (status & BD_ENET_RX_CR) /* CRC Error */
1388 ndev->stats.rx_crc_errors++;
1389 /* Report late collisions as a frame error. */
1390 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1391 ndev->stats.rx_frame_errors++;
1392 goto rx_processing_done;
1393 }
1394
1395 /* Process the incoming frame. */
1396 ndev->stats.rx_packets++;
1397 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1398 ndev->stats.rx_bytes += pkt_len;
1399
1400 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1401 skb = rxq->rx_skbuff[index];
1402
1403 /* The packet length includes FCS, but we don't want to
1404 * include that when passing upstream as it messes up
1405 * bridging applications.
1406 */
1407 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1408 need_swap);
1409 if (!is_copybreak) {
1410 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1411 if (unlikely(!skb_new)) {
1412 ndev->stats.rx_dropped++;
1413 goto rx_processing_done;
1414 }
1415 dma_unmap_single(&fep->pdev->dev,
1416 fec32_to_cpu(bdp->cbd_bufaddr),
1417 FEC_ENET_RX_FRSIZE - fep->rx_align,
1418 DMA_FROM_DEVICE);
1419 }
1420
1421 prefetch(skb->data - NET_IP_ALIGN);
1422 skb_put(skb, pkt_len - 4);
1423 data = skb->data;
1424 if (!is_copybreak && need_swap)
1425 swap_buffer(data, pkt_len);
1426
1427 /* Extract the enhanced buffer descriptor */
1428 ebdp = NULL;
1429 if (fep->bufdesc_ex)
1430 ebdp = (struct bufdesc_ex *)bdp;
1431
1432 /* If this is a VLAN packet remove the VLAN Tag */
1433 vlan_packet_rcvd = false;
1434 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1435 fep->bufdesc_ex &&
1436 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1437 /* Push and remove the vlan tag */
1438 struct vlan_hdr *vlan_header =
1439 (struct vlan_hdr *) (data + ETH_HLEN);
1440 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1441
1442 vlan_packet_rcvd = true;
1443
1444 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1445 skb_pull(skb, VLAN_HLEN);
1446 }
1447
1448 skb->protocol = eth_type_trans(skb, ndev);
1449
1450 /* Get receive timestamp from the skb */
1451 if (fep->hwts_rx_en && fep->bufdesc_ex)
1452 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1453 skb_hwtstamps(skb));
1454
1455 if (fep->bufdesc_ex &&
1456 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1457 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1458 /* don't check it */
1459 skb->ip_summed = CHECKSUM_UNNECESSARY;
1460 } else {
1461 skb_checksum_none_assert(skb);
1462 }
1463 }
1464
1465 /* Handle received VLAN packets */
1466 if (vlan_packet_rcvd)
1467 __vlan_hwaccel_put_tag(skb,
1468 htons(ETH_P_8021Q),
1469 vlan_tag);
1470
1471 napi_gro_receive(&fep->napi, skb);
1472
1473 if (is_copybreak) {
1474 dma_sync_single_for_device(&fep->pdev->dev,
1475 fec32_to_cpu(bdp->cbd_bufaddr),
1476 FEC_ENET_RX_FRSIZE - fep->rx_align,
1477 DMA_FROM_DEVICE);
1478 } else {
1479 rxq->rx_skbuff[index] = skb_new;
1480 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1481 }
1482
1483 rx_processing_done:
1484 /* Clear the status flags for this buffer */
1485 status &= ~BD_ENET_RX_STATS;
1486
1487 /* Mark the buffer empty */
1488 status |= BD_ENET_RX_EMPTY;
1489
1490 if (fep->bufdesc_ex) {
1491 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1492
1493 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1494 ebdp->cbd_prot = 0;
1495 ebdp->cbd_bdu = 0;
1496 }
1497 /* Make sure the updates to rest of the descriptor are
1498 * performed before transferring ownership.
1499 */
1500 wmb();
1501 bdp->cbd_sc = cpu_to_fec16(status);
1502
1503 /* Update BD pointer to next entry */
1504 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1505
1506 /* Doing this here will keep the FEC running while we process
1507 * incoming frames. On a heavily loaded network, we should be
1508 * able to keep up at the expense of system resources.
1509 */
1510 writel(0, rxq->bd.reg_desc_active);
1511 }
1512 rxq->bd.cur = bdp;
1513 return pkt_received;
1514 }
1515
1516 static int
1517 fec_enet_rx(struct net_device *ndev, int budget)
1518 {
1519 int pkt_received = 0;
1520 u16 queue_id;
1521 struct fec_enet_private *fep = netdev_priv(ndev);
1522
1523 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1524 int ret;
1525
1526 ret = fec_enet_rx_queue(ndev,
1527 budget - pkt_received, queue_id);
1528
1529 if (ret < budget - pkt_received)
1530 clear_bit(queue_id, &fep->work_rx);
1531
1532 pkt_received += ret;
1533 }
1534 return pkt_received;
1535 }
1536
1537 static bool
1538 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1539 {
1540 if (int_events == 0)
1541 return false;
1542
1543 if (int_events & FEC_ENET_RXF)
1544 fep->work_rx |= (1 << 2);
1545 if (int_events & FEC_ENET_RXF_1)
1546 fep->work_rx |= (1 << 0);
1547 if (int_events & FEC_ENET_RXF_2)
1548 fep->work_rx |= (1 << 1);
1549
1550 if (int_events & FEC_ENET_TXF)
1551 fep->work_tx |= (1 << 2);
1552 if (int_events & FEC_ENET_TXF_1)
1553 fep->work_tx |= (1 << 0);
1554 if (int_events & FEC_ENET_TXF_2)
1555 fep->work_tx |= (1 << 1);
1556
1557 return true;
1558 }
1559
1560 static irqreturn_t
1561 fec_enet_interrupt(int irq, void *dev_id)
1562 {
1563 struct net_device *ndev = dev_id;
1564 struct fec_enet_private *fep = netdev_priv(ndev);
1565 uint int_events;
1566 irqreturn_t ret = IRQ_NONE;
1567
1568 int_events = readl(fep->hwp + FEC_IEVENT);
1569 writel(int_events, fep->hwp + FEC_IEVENT);
1570 fec_enet_collect_events(fep, int_events);
1571
1572 if ((fep->work_tx || fep->work_rx) && fep->link) {
1573 ret = IRQ_HANDLED;
1574
1575 if (napi_schedule_prep(&fep->napi)) {
1576 /* Disable the NAPI interrupts */
1577 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK);
1578 __napi_schedule(&fep->napi);
1579 }
1580 }
1581
1582 if (int_events & FEC_ENET_MII) {
1583 ret = IRQ_HANDLED;
1584 complete(&fep->mdio_done);
1585 }
1586
1587 if (fep->ptp_clock)
1588 fec_ptp_check_pps_event(fep);
1589
1590 return ret;
1591 }
1592
1593 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1594 {
1595 struct net_device *ndev = napi->dev;
1596 struct fec_enet_private *fep = netdev_priv(ndev);
1597 int pkts;
1598
1599 pkts = fec_enet_rx(ndev, budget);
1600
1601 fec_enet_tx(ndev);
1602
1603 if (pkts < budget) {
1604 napi_complete(napi);
1605 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1606 }
1607 return pkts;
1608 }
1609
1610 /* ------------------------------------------------------------------------- */
1611 static void fec_get_mac(struct net_device *ndev)
1612 {
1613 struct fec_enet_private *fep = netdev_priv(ndev);
1614 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1615 unsigned char *iap, tmpaddr[ETH_ALEN];
1616
1617 /*
1618 * try to get mac address in following order:
1619 *
1620 * 1) module parameter via kernel command line in form
1621 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1622 */
1623 iap = macaddr;
1624
1625 /*
1626 * 2) from device tree data
1627 */
1628 if (!is_valid_ether_addr(iap)) {
1629 struct device_node *np = fep->pdev->dev.of_node;
1630 if (np) {
1631 const char *mac = of_get_mac_address(np);
1632 if (mac)
1633 iap = (unsigned char *) mac;
1634 }
1635 }
1636
1637 /*
1638 * 3) from flash or fuse (via platform data)
1639 */
1640 if (!is_valid_ether_addr(iap)) {
1641 #ifdef CONFIG_M5272
1642 if (FEC_FLASHMAC)
1643 iap = (unsigned char *)FEC_FLASHMAC;
1644 #else
1645 if (pdata)
1646 iap = (unsigned char *)&pdata->mac;
1647 #endif
1648 }
1649
1650 /*
1651 * 4) FEC mac registers set by bootloader
1652 */
1653 if (!is_valid_ether_addr(iap)) {
1654 *((__be32 *) &tmpaddr[0]) =
1655 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1656 *((__be16 *) &tmpaddr[4]) =
1657 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1658 iap = &tmpaddr[0];
1659 }
1660
1661 /*
1662 * 5) random mac address
1663 */
1664 if (!is_valid_ether_addr(iap)) {
1665 /* Report it and use a random ethernet address instead */
1666 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1667 eth_hw_addr_random(ndev);
1668 netdev_info(ndev, "Using random MAC address: %pM\n",
1669 ndev->dev_addr);
1670 return;
1671 }
1672
1673 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1674
1675 /* Adjust MAC if using macaddr */
1676 if (iap == macaddr)
1677 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1678 }
1679
1680 /* ------------------------------------------------------------------------- */
1681
1682 /*
1683 * Phy section
1684 */
1685 static void fec_enet_adjust_link(struct net_device *ndev)
1686 {
1687 struct fec_enet_private *fep = netdev_priv(ndev);
1688 struct phy_device *phy_dev = ndev->phydev;
1689 int status_change = 0;
1690
1691 /* Prevent a state halted on mii error */
1692 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1693 phy_dev->state = PHY_RESUMING;
1694 return;
1695 }
1696
1697 /*
1698 * If the netdev is down, or is going down, we're not interested
1699 * in link state events, so just mark our idea of the link as down
1700 * and ignore the event.
1701 */
1702 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1703 fep->link = 0;
1704 } else if (phy_dev->link) {
1705 if (!fep->link) {
1706 fep->link = phy_dev->link;
1707 status_change = 1;
1708 }
1709
1710 if (fep->full_duplex != phy_dev->duplex) {
1711 fep->full_duplex = phy_dev->duplex;
1712 status_change = 1;
1713 }
1714
1715 if (phy_dev->speed != fep->speed) {
1716 fep->speed = phy_dev->speed;
1717 status_change = 1;
1718 }
1719
1720 /* if any of the above changed restart the FEC */
1721 if (status_change) {
1722 napi_disable(&fep->napi);
1723 netif_tx_lock_bh(ndev);
1724 fec_restart(ndev);
1725 netif_wake_queue(ndev);
1726 netif_tx_unlock_bh(ndev);
1727 napi_enable(&fep->napi);
1728 }
1729 } else {
1730 if (fep->link) {
1731 napi_disable(&fep->napi);
1732 netif_tx_lock_bh(ndev);
1733 fec_stop(ndev);
1734 netif_tx_unlock_bh(ndev);
1735 napi_enable(&fep->napi);
1736 fep->link = phy_dev->link;
1737 status_change = 1;
1738 }
1739 }
1740
1741 if (status_change)
1742 phy_print_status(phy_dev);
1743 }
1744
1745 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1746 {
1747 struct fec_enet_private *fep = bus->priv;
1748 struct device *dev = &fep->pdev->dev;
1749 unsigned long time_left;
1750 int ret = 0;
1751
1752 ret = pm_runtime_get_sync(dev);
1753 if (ret < 0)
1754 return ret;
1755
1756 fep->mii_timeout = 0;
1757 reinit_completion(&fep->mdio_done);
1758
1759 /* start a read op */
1760 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1761 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1762 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1763
1764 /* wait for end of transfer */
1765 time_left = wait_for_completion_timeout(&fep->mdio_done,
1766 usecs_to_jiffies(FEC_MII_TIMEOUT));
1767 if (time_left == 0) {
1768 fep->mii_timeout = 1;
1769 netdev_err(fep->netdev, "MDIO read timeout\n");
1770 ret = -ETIMEDOUT;
1771 goto out;
1772 }
1773
1774 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1775
1776 out:
1777 pm_runtime_mark_last_busy(dev);
1778 pm_runtime_put_autosuspend(dev);
1779
1780 return ret;
1781 }
1782
1783 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1784 u16 value)
1785 {
1786 struct fec_enet_private *fep = bus->priv;
1787 struct device *dev = &fep->pdev->dev;
1788 unsigned long time_left;
1789 int ret;
1790
1791 ret = pm_runtime_get_sync(dev);
1792 if (ret < 0)
1793 return ret;
1794 else
1795 ret = 0;
1796
1797 fep->mii_timeout = 0;
1798 reinit_completion(&fep->mdio_done);
1799
1800 /* start a write op */
1801 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1802 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1803 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1804 fep->hwp + FEC_MII_DATA);
1805
1806 /* wait for end of transfer */
1807 time_left = wait_for_completion_timeout(&fep->mdio_done,
1808 usecs_to_jiffies(FEC_MII_TIMEOUT));
1809 if (time_left == 0) {
1810 fep->mii_timeout = 1;
1811 netdev_err(fep->netdev, "MDIO write timeout\n");
1812 ret = -ETIMEDOUT;
1813 }
1814
1815 pm_runtime_mark_last_busy(dev);
1816 pm_runtime_put_autosuspend(dev);
1817
1818 return ret;
1819 }
1820
1821 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1822 {
1823 struct fec_enet_private *fep = netdev_priv(ndev);
1824 int ret;
1825
1826 if (enable) {
1827 ret = clk_prepare_enable(fep->clk_ahb);
1828 if (ret)
1829 return ret;
1830 if (fep->clk_enet_out) {
1831 ret = clk_prepare_enable(fep->clk_enet_out);
1832 if (ret)
1833 goto failed_clk_enet_out;
1834 }
1835 if (fep->clk_ptp) {
1836 mutex_lock(&fep->ptp_clk_mutex);
1837 ret = clk_prepare_enable(fep->clk_ptp);
1838 if (ret) {
1839 mutex_unlock(&fep->ptp_clk_mutex);
1840 goto failed_clk_ptp;
1841 } else {
1842 fep->ptp_clk_on = true;
1843 }
1844 mutex_unlock(&fep->ptp_clk_mutex);
1845 }
1846 if (fep->clk_ref) {
1847 ret = clk_prepare_enable(fep->clk_ref);
1848 if (ret)
1849 goto failed_clk_ref;
1850 }
1851 } else {
1852 clk_disable_unprepare(fep->clk_ahb);
1853 if (fep->clk_enet_out)
1854 clk_disable_unprepare(fep->clk_enet_out);
1855 if (fep->clk_ptp) {
1856 mutex_lock(&fep->ptp_clk_mutex);
1857 clk_disable_unprepare(fep->clk_ptp);
1858 fep->ptp_clk_on = false;
1859 mutex_unlock(&fep->ptp_clk_mutex);
1860 }
1861 if (fep->clk_ref)
1862 clk_disable_unprepare(fep->clk_ref);
1863 }
1864
1865 return 0;
1866
1867 failed_clk_ref:
1868 if (fep->clk_ref)
1869 clk_disable_unprepare(fep->clk_ref);
1870 failed_clk_ptp:
1871 if (fep->clk_enet_out)
1872 clk_disable_unprepare(fep->clk_enet_out);
1873 failed_clk_enet_out:
1874 clk_disable_unprepare(fep->clk_ahb);
1875
1876 return ret;
1877 }
1878
1879 static int fec_enet_mii_probe(struct net_device *ndev)
1880 {
1881 struct fec_enet_private *fep = netdev_priv(ndev);
1882 struct phy_device *phy_dev = NULL;
1883 char mdio_bus_id[MII_BUS_ID_SIZE];
1884 char phy_name[MII_BUS_ID_SIZE + 3];
1885 int phy_id;
1886 int dev_id = fep->dev_id;
1887
1888 if (fep->phy_node) {
1889 phy_dev = of_phy_connect(ndev, fep->phy_node,
1890 &fec_enet_adjust_link, 0,
1891 fep->phy_interface);
1892 if (!phy_dev)
1893 return -ENODEV;
1894 } else {
1895 /* check for attached phy */
1896 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1897 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
1898 continue;
1899 if (dev_id--)
1900 continue;
1901 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1902 break;
1903 }
1904
1905 if (phy_id >= PHY_MAX_ADDR) {
1906 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1907 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1908 phy_id = 0;
1909 }
1910
1911 snprintf(phy_name, sizeof(phy_name),
1912 PHY_ID_FMT, mdio_bus_id, phy_id);
1913 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1914 fep->phy_interface);
1915 }
1916
1917 if (IS_ERR(phy_dev)) {
1918 netdev_err(ndev, "could not attach to PHY\n");
1919 return PTR_ERR(phy_dev);
1920 }
1921
1922 /* mask with MAC supported features */
1923 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1924 phy_dev->supported &= PHY_GBIT_FEATURES;
1925 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1926 #if !defined(CONFIG_M5272)
1927 phy_dev->supported |= SUPPORTED_Pause;
1928 #endif
1929 }
1930 else
1931 phy_dev->supported &= PHY_BASIC_FEATURES;
1932
1933 phy_dev->advertising = phy_dev->supported;
1934
1935 fep->link = 0;
1936 fep->full_duplex = 0;
1937
1938 phy_attached_info(phy_dev);
1939
1940 return 0;
1941 }
1942
1943 static int fec_enet_mii_init(struct platform_device *pdev)
1944 {
1945 static struct mii_bus *fec0_mii_bus;
1946 struct net_device *ndev = platform_get_drvdata(pdev);
1947 struct fec_enet_private *fep = netdev_priv(ndev);
1948 struct device_node *node;
1949 int err = -ENXIO;
1950 u32 mii_speed, holdtime;
1951
1952 /*
1953 * The i.MX28 dual fec interfaces are not equal.
1954 * Here are the differences:
1955 *
1956 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1957 * - fec0 acts as the 1588 time master while fec1 is slave
1958 * - external phys can only be configured by fec0
1959 *
1960 * That is to say fec1 can not work independently. It only works
1961 * when fec0 is working. The reason behind this design is that the
1962 * second interface is added primarily for Switch mode.
1963 *
1964 * Because of the last point above, both phys are attached on fec0
1965 * mdio interface in board design, and need to be configured by
1966 * fec0 mii_bus.
1967 */
1968 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
1969 /* fec1 uses fec0 mii_bus */
1970 if (mii_cnt && fec0_mii_bus) {
1971 fep->mii_bus = fec0_mii_bus;
1972 mii_cnt++;
1973 return 0;
1974 }
1975 return -ENOENT;
1976 }
1977
1978 fep->mii_timeout = 0;
1979
1980 /*
1981 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1982 *
1983 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1984 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1985 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1986 * document.
1987 */
1988 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
1989 if (fep->quirks & FEC_QUIRK_ENET_MAC)
1990 mii_speed--;
1991 if (mii_speed > 63) {
1992 dev_err(&pdev->dev,
1993 "fec clock (%lu) to fast to get right mii speed\n",
1994 clk_get_rate(fep->clk_ipg));
1995 err = -EINVAL;
1996 goto err_out;
1997 }
1998
1999 /*
2000 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2001 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2002 * versions are RAZ there, so just ignore the difference and write the
2003 * register always.
2004 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2005 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2006 * output.
2007 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2008 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2009 * holdtime cannot result in a value greater than 3.
2010 */
2011 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2012
2013 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2014
2015 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2016
2017 fep->mii_bus = mdiobus_alloc();
2018 if (fep->mii_bus == NULL) {
2019 err = -ENOMEM;
2020 goto err_out;
2021 }
2022
2023 fep->mii_bus->name = "fec_enet_mii_bus";
2024 fep->mii_bus->read = fec_enet_mdio_read;
2025 fep->mii_bus->write = fec_enet_mdio_write;
2026 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2027 pdev->name, fep->dev_id + 1);
2028 fep->mii_bus->priv = fep;
2029 fep->mii_bus->parent = &pdev->dev;
2030
2031 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2032 if (node) {
2033 err = of_mdiobus_register(fep->mii_bus, node);
2034 of_node_put(node);
2035 } else {
2036 err = mdiobus_register(fep->mii_bus);
2037 }
2038
2039 if (err)
2040 goto err_out_free_mdiobus;
2041
2042 mii_cnt++;
2043
2044 /* save fec0 mii_bus */
2045 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2046 fec0_mii_bus = fep->mii_bus;
2047
2048 return 0;
2049
2050 err_out_free_mdiobus:
2051 mdiobus_free(fep->mii_bus);
2052 err_out:
2053 return err;
2054 }
2055
2056 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2057 {
2058 if (--mii_cnt == 0) {
2059 mdiobus_unregister(fep->mii_bus);
2060 mdiobus_free(fep->mii_bus);
2061 }
2062 }
2063
2064 static void fec_enet_get_drvinfo(struct net_device *ndev,
2065 struct ethtool_drvinfo *info)
2066 {
2067 struct fec_enet_private *fep = netdev_priv(ndev);
2068
2069 strlcpy(info->driver, fep->pdev->dev.driver->name,
2070 sizeof(info->driver));
2071 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2072 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2073 }
2074
2075 static int fec_enet_get_regs_len(struct net_device *ndev)
2076 {
2077 struct fec_enet_private *fep = netdev_priv(ndev);
2078 struct resource *r;
2079 int s = 0;
2080
2081 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2082 if (r)
2083 s = resource_size(r);
2084
2085 return s;
2086 }
2087
2088 /* List of registers that can be safety be read to dump them with ethtool */
2089 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2090 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
2091 static u32 fec_enet_register_offset[] = {
2092 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2093 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2094 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2095 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2096 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2097 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2098 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2099 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2100 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2101 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2102 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2103 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2104 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2105 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2106 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2107 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2108 RMON_T_P_GTE2048, RMON_T_OCTETS,
2109 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2110 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2111 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2112 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2113 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2114 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2115 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2116 RMON_R_P_GTE2048, RMON_R_OCTETS,
2117 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2118 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2119 };
2120 #else
2121 static u32 fec_enet_register_offset[] = {
2122 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2123 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2124 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2125 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2126 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2127 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2128 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2129 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2130 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2131 };
2132 #endif
2133
2134 static void fec_enet_get_regs(struct net_device *ndev,
2135 struct ethtool_regs *regs, void *regbuf)
2136 {
2137 struct fec_enet_private *fep = netdev_priv(ndev);
2138 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2139 u32 *buf = (u32 *)regbuf;
2140 u32 i, off;
2141
2142 memset(buf, 0, regs->len);
2143
2144 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2145 off = fec_enet_register_offset[i] / 4;
2146 buf[off] = readl(&theregs[off]);
2147 }
2148 }
2149
2150 static int fec_enet_get_ts_info(struct net_device *ndev,
2151 struct ethtool_ts_info *info)
2152 {
2153 struct fec_enet_private *fep = netdev_priv(ndev);
2154
2155 if (fep->bufdesc_ex) {
2156
2157 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2158 SOF_TIMESTAMPING_RX_SOFTWARE |
2159 SOF_TIMESTAMPING_SOFTWARE |
2160 SOF_TIMESTAMPING_TX_HARDWARE |
2161 SOF_TIMESTAMPING_RX_HARDWARE |
2162 SOF_TIMESTAMPING_RAW_HARDWARE;
2163 if (fep->ptp_clock)
2164 info->phc_index = ptp_clock_index(fep->ptp_clock);
2165 else
2166 info->phc_index = -1;
2167
2168 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2169 (1 << HWTSTAMP_TX_ON);
2170
2171 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2172 (1 << HWTSTAMP_FILTER_ALL);
2173 return 0;
2174 } else {
2175 return ethtool_op_get_ts_info(ndev, info);
2176 }
2177 }
2178
2179 #if !defined(CONFIG_M5272)
2180
2181 static void fec_enet_get_pauseparam(struct net_device *ndev,
2182 struct ethtool_pauseparam *pause)
2183 {
2184 struct fec_enet_private *fep = netdev_priv(ndev);
2185
2186 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2187 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2188 pause->rx_pause = pause->tx_pause;
2189 }
2190
2191 static int fec_enet_set_pauseparam(struct net_device *ndev,
2192 struct ethtool_pauseparam *pause)
2193 {
2194 struct fec_enet_private *fep = netdev_priv(ndev);
2195
2196 if (!ndev->phydev)
2197 return -ENODEV;
2198
2199 if (pause->tx_pause != pause->rx_pause) {
2200 netdev_info(ndev,
2201 "hardware only support enable/disable both tx and rx");
2202 return -EINVAL;
2203 }
2204
2205 fep->pause_flag = 0;
2206
2207 /* tx pause must be same as rx pause */
2208 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2209 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2210
2211 if (pause->rx_pause || pause->autoneg) {
2212 ndev->phydev->supported |= ADVERTISED_Pause;
2213 ndev->phydev->advertising |= ADVERTISED_Pause;
2214 } else {
2215 ndev->phydev->supported &= ~ADVERTISED_Pause;
2216 ndev->phydev->advertising &= ~ADVERTISED_Pause;
2217 }
2218
2219 if (pause->autoneg) {
2220 if (netif_running(ndev))
2221 fec_stop(ndev);
2222 phy_start_aneg(ndev->phydev);
2223 }
2224 if (netif_running(ndev)) {
2225 napi_disable(&fep->napi);
2226 netif_tx_lock_bh(ndev);
2227 fec_restart(ndev);
2228 netif_wake_queue(ndev);
2229 netif_tx_unlock_bh(ndev);
2230 napi_enable(&fep->napi);
2231 }
2232
2233 return 0;
2234 }
2235
2236 static const struct fec_stat {
2237 char name[ETH_GSTRING_LEN];
2238 u16 offset;
2239 } fec_stats[] = {
2240 /* RMON TX */
2241 { "tx_dropped", RMON_T_DROP },
2242 { "tx_packets", RMON_T_PACKETS },
2243 { "tx_broadcast", RMON_T_BC_PKT },
2244 { "tx_multicast", RMON_T_MC_PKT },
2245 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2246 { "tx_undersize", RMON_T_UNDERSIZE },
2247 { "tx_oversize", RMON_T_OVERSIZE },
2248 { "tx_fragment", RMON_T_FRAG },
2249 { "tx_jabber", RMON_T_JAB },
2250 { "tx_collision", RMON_T_COL },
2251 { "tx_64byte", RMON_T_P64 },
2252 { "tx_65to127byte", RMON_T_P65TO127 },
2253 { "tx_128to255byte", RMON_T_P128TO255 },
2254 { "tx_256to511byte", RMON_T_P256TO511 },
2255 { "tx_512to1023byte", RMON_T_P512TO1023 },
2256 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2257 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2258 { "tx_octets", RMON_T_OCTETS },
2259
2260 /* IEEE TX */
2261 { "IEEE_tx_drop", IEEE_T_DROP },
2262 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2263 { "IEEE_tx_1col", IEEE_T_1COL },
2264 { "IEEE_tx_mcol", IEEE_T_MCOL },
2265 { "IEEE_tx_def", IEEE_T_DEF },
2266 { "IEEE_tx_lcol", IEEE_T_LCOL },
2267 { "IEEE_tx_excol", IEEE_T_EXCOL },
2268 { "IEEE_tx_macerr", IEEE_T_MACERR },
2269 { "IEEE_tx_cserr", IEEE_T_CSERR },
2270 { "IEEE_tx_sqe", IEEE_T_SQE },
2271 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2272 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2273
2274 /* RMON RX */
2275 { "rx_packets", RMON_R_PACKETS },
2276 { "rx_broadcast", RMON_R_BC_PKT },
2277 { "rx_multicast", RMON_R_MC_PKT },
2278 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2279 { "rx_undersize", RMON_R_UNDERSIZE },
2280 { "rx_oversize", RMON_R_OVERSIZE },
2281 { "rx_fragment", RMON_R_FRAG },
2282 { "rx_jabber", RMON_R_JAB },
2283 { "rx_64byte", RMON_R_P64 },
2284 { "rx_65to127byte", RMON_R_P65TO127 },
2285 { "rx_128to255byte", RMON_R_P128TO255 },
2286 { "rx_256to511byte", RMON_R_P256TO511 },
2287 { "rx_512to1023byte", RMON_R_P512TO1023 },
2288 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2289 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2290 { "rx_octets", RMON_R_OCTETS },
2291
2292 /* IEEE RX */
2293 { "IEEE_rx_drop", IEEE_R_DROP },
2294 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2295 { "IEEE_rx_crc", IEEE_R_CRC },
2296 { "IEEE_rx_align", IEEE_R_ALIGN },
2297 { "IEEE_rx_macerr", IEEE_R_MACERR },
2298 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2299 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2300 };
2301
2302 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2303 struct ethtool_stats *stats, u64 *data)
2304 {
2305 struct fec_enet_private *fep = netdev_priv(dev);
2306 int i;
2307
2308 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2309 data[i] = readl(fep->hwp + fec_stats[i].offset);
2310 }
2311
2312 static void fec_enet_get_strings(struct net_device *netdev,
2313 u32 stringset, u8 *data)
2314 {
2315 int i;
2316 switch (stringset) {
2317 case ETH_SS_STATS:
2318 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2319 memcpy(data + i * ETH_GSTRING_LEN,
2320 fec_stats[i].name, ETH_GSTRING_LEN);
2321 break;
2322 }
2323 }
2324
2325 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2326 {
2327 switch (sset) {
2328 case ETH_SS_STATS:
2329 return ARRAY_SIZE(fec_stats);
2330 default:
2331 return -EOPNOTSUPP;
2332 }
2333 }
2334 #endif /* !defined(CONFIG_M5272) */
2335
2336 static int fec_enet_nway_reset(struct net_device *dev)
2337 {
2338 struct phy_device *phydev = dev->phydev;
2339
2340 if (!phydev)
2341 return -ENODEV;
2342
2343 return genphy_restart_aneg(phydev);
2344 }
2345
2346 /* ITR clock source is enet system clock (clk_ahb).
2347 * TCTT unit is cycle_ns * 64 cycle
2348 * So, the ICTT value = X us / (cycle_ns * 64)
2349 */
2350 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2351 {
2352 struct fec_enet_private *fep = netdev_priv(ndev);
2353
2354 return us * (fep->itr_clk_rate / 64000) / 1000;
2355 }
2356
2357 /* Set threshold for interrupt coalescing */
2358 static void fec_enet_itr_coal_set(struct net_device *ndev)
2359 {
2360 struct fec_enet_private *fep = netdev_priv(ndev);
2361 int rx_itr, tx_itr;
2362
2363 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2364 return;
2365
2366 /* Must be greater than zero to avoid unpredictable behavior */
2367 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2368 !fep->tx_time_itr || !fep->tx_pkts_itr)
2369 return;
2370
2371 /* Select enet system clock as Interrupt Coalescing
2372 * timer Clock Source
2373 */
2374 rx_itr = FEC_ITR_CLK_SEL;
2375 tx_itr = FEC_ITR_CLK_SEL;
2376
2377 /* set ICFT and ICTT */
2378 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2379 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2380 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2381 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2382
2383 rx_itr |= FEC_ITR_EN;
2384 tx_itr |= FEC_ITR_EN;
2385
2386 writel(tx_itr, fep->hwp + FEC_TXIC0);
2387 writel(rx_itr, fep->hwp + FEC_RXIC0);
2388 writel(tx_itr, fep->hwp + FEC_TXIC1);
2389 writel(rx_itr, fep->hwp + FEC_RXIC1);
2390 writel(tx_itr, fep->hwp + FEC_TXIC2);
2391 writel(rx_itr, fep->hwp + FEC_RXIC2);
2392 }
2393
2394 static int
2395 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2396 {
2397 struct fec_enet_private *fep = netdev_priv(ndev);
2398
2399 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2400 return -EOPNOTSUPP;
2401
2402 ec->rx_coalesce_usecs = fep->rx_time_itr;
2403 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2404
2405 ec->tx_coalesce_usecs = fep->tx_time_itr;
2406 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2407
2408 return 0;
2409 }
2410
2411 static int
2412 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2413 {
2414 struct fec_enet_private *fep = netdev_priv(ndev);
2415 unsigned int cycle;
2416
2417 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2418 return -EOPNOTSUPP;
2419
2420 if (ec->rx_max_coalesced_frames > 255) {
2421 pr_err("Rx coalesced frames exceed hardware limiation");
2422 return -EINVAL;
2423 }
2424
2425 if (ec->tx_max_coalesced_frames > 255) {
2426 pr_err("Tx coalesced frame exceed hardware limiation");
2427 return -EINVAL;
2428 }
2429
2430 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2431 if (cycle > 0xFFFF) {
2432 pr_err("Rx coalesed usec exceeed hardware limiation");
2433 return -EINVAL;
2434 }
2435
2436 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2437 if (cycle > 0xFFFF) {
2438 pr_err("Rx coalesed usec exceeed hardware limiation");
2439 return -EINVAL;
2440 }
2441
2442 fep->rx_time_itr = ec->rx_coalesce_usecs;
2443 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2444
2445 fep->tx_time_itr = ec->tx_coalesce_usecs;
2446 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2447
2448 fec_enet_itr_coal_set(ndev);
2449
2450 return 0;
2451 }
2452
2453 static void fec_enet_itr_coal_init(struct net_device *ndev)
2454 {
2455 struct ethtool_coalesce ec;
2456
2457 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2458 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2459
2460 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2461 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2462
2463 fec_enet_set_coalesce(ndev, &ec);
2464 }
2465
2466 static int fec_enet_get_tunable(struct net_device *netdev,
2467 const struct ethtool_tunable *tuna,
2468 void *data)
2469 {
2470 struct fec_enet_private *fep = netdev_priv(netdev);
2471 int ret = 0;
2472
2473 switch (tuna->id) {
2474 case ETHTOOL_RX_COPYBREAK:
2475 *(u32 *)data = fep->rx_copybreak;
2476 break;
2477 default:
2478 ret = -EINVAL;
2479 break;
2480 }
2481
2482 return ret;
2483 }
2484
2485 static int fec_enet_set_tunable(struct net_device *netdev,
2486 const struct ethtool_tunable *tuna,
2487 const void *data)
2488 {
2489 struct fec_enet_private *fep = netdev_priv(netdev);
2490 int ret = 0;
2491
2492 switch (tuna->id) {
2493 case ETHTOOL_RX_COPYBREAK:
2494 fep->rx_copybreak = *(u32 *)data;
2495 break;
2496 default:
2497 ret = -EINVAL;
2498 break;
2499 }
2500
2501 return ret;
2502 }
2503
2504 static void
2505 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2506 {
2507 struct fec_enet_private *fep = netdev_priv(ndev);
2508
2509 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2510 wol->supported = WAKE_MAGIC;
2511 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2512 } else {
2513 wol->supported = wol->wolopts = 0;
2514 }
2515 }
2516
2517 static int
2518 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2519 {
2520 struct fec_enet_private *fep = netdev_priv(ndev);
2521
2522 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2523 return -EINVAL;
2524
2525 if (wol->wolopts & ~WAKE_MAGIC)
2526 return -EINVAL;
2527
2528 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2529 if (device_may_wakeup(&ndev->dev)) {
2530 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2531 if (fep->irq[0] > 0)
2532 enable_irq_wake(fep->irq[0]);
2533 } else {
2534 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2535 if (fep->irq[0] > 0)
2536 disable_irq_wake(fep->irq[0]);
2537 }
2538
2539 return 0;
2540 }
2541
2542 static const struct ethtool_ops fec_enet_ethtool_ops = {
2543 .get_drvinfo = fec_enet_get_drvinfo,
2544 .get_regs_len = fec_enet_get_regs_len,
2545 .get_regs = fec_enet_get_regs,
2546 .nway_reset = fec_enet_nway_reset,
2547 .get_link = ethtool_op_get_link,
2548 .get_coalesce = fec_enet_get_coalesce,
2549 .set_coalesce = fec_enet_set_coalesce,
2550 #ifndef CONFIG_M5272
2551 .get_pauseparam = fec_enet_get_pauseparam,
2552 .set_pauseparam = fec_enet_set_pauseparam,
2553 .get_strings = fec_enet_get_strings,
2554 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2555 .get_sset_count = fec_enet_get_sset_count,
2556 #endif
2557 .get_ts_info = fec_enet_get_ts_info,
2558 .get_tunable = fec_enet_get_tunable,
2559 .set_tunable = fec_enet_set_tunable,
2560 .get_wol = fec_enet_get_wol,
2561 .set_wol = fec_enet_set_wol,
2562 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2563 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2564 };
2565
2566 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2567 {
2568 struct fec_enet_private *fep = netdev_priv(ndev);
2569 struct phy_device *phydev = ndev->phydev;
2570
2571 if (!netif_running(ndev))
2572 return -EINVAL;
2573
2574 if (!phydev)
2575 return -ENODEV;
2576
2577 if (fep->bufdesc_ex) {
2578 if (cmd == SIOCSHWTSTAMP)
2579 return fec_ptp_set(ndev, rq);
2580 if (cmd == SIOCGHWTSTAMP)
2581 return fec_ptp_get(ndev, rq);
2582 }
2583
2584 return phy_mii_ioctl(phydev, rq, cmd);
2585 }
2586
2587 static void fec_enet_free_buffers(struct net_device *ndev)
2588 {
2589 struct fec_enet_private *fep = netdev_priv(ndev);
2590 unsigned int i;
2591 struct sk_buff *skb;
2592 struct bufdesc *bdp;
2593 struct fec_enet_priv_tx_q *txq;
2594 struct fec_enet_priv_rx_q *rxq;
2595 unsigned int q;
2596
2597 for (q = 0; q < fep->num_rx_queues; q++) {
2598 rxq = fep->rx_queue[q];
2599 bdp = rxq->bd.base;
2600 for (i = 0; i < rxq->bd.ring_size; i++) {
2601 skb = rxq->rx_skbuff[i];
2602 rxq->rx_skbuff[i] = NULL;
2603 if (skb) {
2604 dma_unmap_single(&fep->pdev->dev,
2605 fec32_to_cpu(bdp->cbd_bufaddr),
2606 FEC_ENET_RX_FRSIZE - fep->rx_align,
2607 DMA_FROM_DEVICE);
2608 dev_kfree_skb(skb);
2609 }
2610 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2611 }
2612 }
2613
2614 for (q = 0; q < fep->num_tx_queues; q++) {
2615 txq = fep->tx_queue[q];
2616 bdp = txq->bd.base;
2617 for (i = 0; i < txq->bd.ring_size; i++) {
2618 kfree(txq->tx_bounce[i]);
2619 txq->tx_bounce[i] = NULL;
2620 skb = txq->tx_skbuff[i];
2621 txq->tx_skbuff[i] = NULL;
2622 dev_kfree_skb(skb);
2623 }
2624 }
2625 }
2626
2627 static void fec_enet_free_queue(struct net_device *ndev)
2628 {
2629 struct fec_enet_private *fep = netdev_priv(ndev);
2630 int i;
2631 struct fec_enet_priv_tx_q *txq;
2632
2633 for (i = 0; i < fep->num_tx_queues; i++)
2634 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2635 txq = fep->tx_queue[i];
2636 dma_free_coherent(NULL,
2637 txq->bd.ring_size * TSO_HEADER_SIZE,
2638 txq->tso_hdrs,
2639 txq->tso_hdrs_dma);
2640 }
2641
2642 for (i = 0; i < fep->num_rx_queues; i++)
2643 kfree(fep->rx_queue[i]);
2644 for (i = 0; i < fep->num_tx_queues; i++)
2645 kfree(fep->tx_queue[i]);
2646 }
2647
2648 static int fec_enet_alloc_queue(struct net_device *ndev)
2649 {
2650 struct fec_enet_private *fep = netdev_priv(ndev);
2651 int i;
2652 int ret = 0;
2653 struct fec_enet_priv_tx_q *txq;
2654
2655 for (i = 0; i < fep->num_tx_queues; i++) {
2656 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2657 if (!txq) {
2658 ret = -ENOMEM;
2659 goto alloc_failed;
2660 }
2661
2662 fep->tx_queue[i] = txq;
2663 txq->bd.ring_size = TX_RING_SIZE;
2664 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
2665
2666 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2667 txq->tx_wake_threshold =
2668 (txq->bd.ring_size - txq->tx_stop_threshold) / 2;
2669
2670 txq->tso_hdrs = dma_alloc_coherent(NULL,
2671 txq->bd.ring_size * TSO_HEADER_SIZE,
2672 &txq->tso_hdrs_dma,
2673 GFP_KERNEL);
2674 if (!txq->tso_hdrs) {
2675 ret = -ENOMEM;
2676 goto alloc_failed;
2677 }
2678 }
2679
2680 for (i = 0; i < fep->num_rx_queues; i++) {
2681 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2682 GFP_KERNEL);
2683 if (!fep->rx_queue[i]) {
2684 ret = -ENOMEM;
2685 goto alloc_failed;
2686 }
2687
2688 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2689 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
2690 }
2691 return ret;
2692
2693 alloc_failed:
2694 fec_enet_free_queue(ndev);
2695 return ret;
2696 }
2697
2698 static int
2699 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2700 {
2701 struct fec_enet_private *fep = netdev_priv(ndev);
2702 unsigned int i;
2703 struct sk_buff *skb;
2704 struct bufdesc *bdp;
2705 struct fec_enet_priv_rx_q *rxq;
2706
2707 rxq = fep->rx_queue[queue];
2708 bdp = rxq->bd.base;
2709 for (i = 0; i < rxq->bd.ring_size; i++) {
2710 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2711 if (!skb)
2712 goto err_alloc;
2713
2714 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2715 dev_kfree_skb(skb);
2716 goto err_alloc;
2717 }
2718
2719 rxq->rx_skbuff[i] = skb;
2720 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
2721
2722 if (fep->bufdesc_ex) {
2723 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2724 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
2725 }
2726
2727 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2728 }
2729
2730 /* Set the last buffer to wrap. */
2731 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
2732 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2733 return 0;
2734
2735 err_alloc:
2736 fec_enet_free_buffers(ndev);
2737 return -ENOMEM;
2738 }
2739
2740 static int
2741 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2742 {
2743 struct fec_enet_private *fep = netdev_priv(ndev);
2744 unsigned int i;
2745 struct bufdesc *bdp;
2746 struct fec_enet_priv_tx_q *txq;
2747
2748 txq = fep->tx_queue[queue];
2749 bdp = txq->bd.base;
2750 for (i = 0; i < txq->bd.ring_size; i++) {
2751 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2752 if (!txq->tx_bounce[i])
2753 goto err_alloc;
2754
2755 bdp->cbd_sc = cpu_to_fec16(0);
2756 bdp->cbd_bufaddr = cpu_to_fec32(0);
2757
2758 if (fep->bufdesc_ex) {
2759 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2760 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
2761 }
2762
2763 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
2764 }
2765
2766 /* Set the last buffer to wrap. */
2767 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
2768 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2769
2770 return 0;
2771
2772 err_alloc:
2773 fec_enet_free_buffers(ndev);
2774 return -ENOMEM;
2775 }
2776
2777 static int fec_enet_alloc_buffers(struct net_device *ndev)
2778 {
2779 struct fec_enet_private *fep = netdev_priv(ndev);
2780 unsigned int i;
2781
2782 for (i = 0; i < fep->num_rx_queues; i++)
2783 if (fec_enet_alloc_rxq_buffers(ndev, i))
2784 return -ENOMEM;
2785
2786 for (i = 0; i < fep->num_tx_queues; i++)
2787 if (fec_enet_alloc_txq_buffers(ndev, i))
2788 return -ENOMEM;
2789 return 0;
2790 }
2791
2792 static int
2793 fec_enet_open(struct net_device *ndev)
2794 {
2795 struct fec_enet_private *fep = netdev_priv(ndev);
2796 int ret;
2797
2798 ret = pm_runtime_get_sync(&fep->pdev->dev);
2799 if (ret < 0)
2800 return ret;
2801
2802 pinctrl_pm_select_default_state(&fep->pdev->dev);
2803 ret = fec_enet_clk_enable(ndev, true);
2804 if (ret)
2805 goto clk_enable;
2806
2807 /* I should reset the ring buffers here, but I don't yet know
2808 * a simple way to do that.
2809 */
2810
2811 ret = fec_enet_alloc_buffers(ndev);
2812 if (ret)
2813 goto err_enet_alloc;
2814
2815 /* Init MAC prior to mii bus probe */
2816 fec_restart(ndev);
2817
2818 /* Probe and connect to PHY when open the interface */
2819 ret = fec_enet_mii_probe(ndev);
2820 if (ret)
2821 goto err_enet_mii_probe;
2822
2823 napi_enable(&fep->napi);
2824 phy_start(ndev->phydev);
2825 netif_tx_start_all_queues(ndev);
2826
2827 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2828 FEC_WOL_FLAG_ENABLE);
2829
2830 return 0;
2831
2832 err_enet_mii_probe:
2833 fec_enet_free_buffers(ndev);
2834 err_enet_alloc:
2835 fec_enet_clk_enable(ndev, false);
2836 clk_enable:
2837 pm_runtime_mark_last_busy(&fep->pdev->dev);
2838 pm_runtime_put_autosuspend(&fep->pdev->dev);
2839 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2840 return ret;
2841 }
2842
2843 static int
2844 fec_enet_close(struct net_device *ndev)
2845 {
2846 struct fec_enet_private *fep = netdev_priv(ndev);
2847
2848 phy_stop(ndev->phydev);
2849
2850 if (netif_device_present(ndev)) {
2851 napi_disable(&fep->napi);
2852 netif_tx_disable(ndev);
2853 fec_stop(ndev);
2854 }
2855
2856 phy_disconnect(ndev->phydev);
2857
2858 fec_enet_clk_enable(ndev, false);
2859 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2860 pm_runtime_mark_last_busy(&fep->pdev->dev);
2861 pm_runtime_put_autosuspend(&fep->pdev->dev);
2862
2863 fec_enet_free_buffers(ndev);
2864
2865 return 0;
2866 }
2867
2868 /* Set or clear the multicast filter for this adaptor.
2869 * Skeleton taken from sunlance driver.
2870 * The CPM Ethernet implementation allows Multicast as well as individual
2871 * MAC address filtering. Some of the drivers check to make sure it is
2872 * a group multicast address, and discard those that are not. I guess I
2873 * will do the same for now, but just remove the test if you want
2874 * individual filtering as well (do the upper net layers want or support
2875 * this kind of feature?).
2876 */
2877
2878 #define HASH_BITS 6 /* #bits in hash */
2879 #define CRC32_POLY 0xEDB88320
2880
2881 static void set_multicast_list(struct net_device *ndev)
2882 {
2883 struct fec_enet_private *fep = netdev_priv(ndev);
2884 struct netdev_hw_addr *ha;
2885 unsigned int i, bit, data, crc, tmp;
2886 unsigned char hash;
2887
2888 if (ndev->flags & IFF_PROMISC) {
2889 tmp = readl(fep->hwp + FEC_R_CNTRL);
2890 tmp |= 0x8;
2891 writel(tmp, fep->hwp + FEC_R_CNTRL);
2892 return;
2893 }
2894
2895 tmp = readl(fep->hwp + FEC_R_CNTRL);
2896 tmp &= ~0x8;
2897 writel(tmp, fep->hwp + FEC_R_CNTRL);
2898
2899 if (ndev->flags & IFF_ALLMULTI) {
2900 /* Catch all multicast addresses, so set the
2901 * filter to all 1's
2902 */
2903 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2904 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2905
2906 return;
2907 }
2908
2909 /* Clear filter and add the addresses in hash register
2910 */
2911 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2912 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2913
2914 netdev_for_each_mc_addr(ha, ndev) {
2915 /* calculate crc32 value of mac address */
2916 crc = 0xffffffff;
2917
2918 for (i = 0; i < ndev->addr_len; i++) {
2919 data = ha->addr[i];
2920 for (bit = 0; bit < 8; bit++, data >>= 1) {
2921 crc = (crc >> 1) ^
2922 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2923 }
2924 }
2925
2926 /* only upper 6 bits (HASH_BITS) are used
2927 * which point to specific bit in he hash registers
2928 */
2929 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2930
2931 if (hash > 31) {
2932 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2933 tmp |= 1 << (hash - 32);
2934 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2935 } else {
2936 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2937 tmp |= 1 << hash;
2938 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2939 }
2940 }
2941 }
2942
2943 /* Set a MAC change in hardware. */
2944 static int
2945 fec_set_mac_address(struct net_device *ndev, void *p)
2946 {
2947 struct fec_enet_private *fep = netdev_priv(ndev);
2948 struct sockaddr *addr = p;
2949
2950 if (addr) {
2951 if (!is_valid_ether_addr(addr->sa_data))
2952 return -EADDRNOTAVAIL;
2953 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2954 }
2955
2956 /* Add netif status check here to avoid system hang in below case:
2957 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
2958 * After ethx down, fec all clocks are gated off and then register
2959 * access causes system hang.
2960 */
2961 if (!netif_running(ndev))
2962 return 0;
2963
2964 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2965 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
2966 fep->hwp + FEC_ADDR_LOW);
2967 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
2968 fep->hwp + FEC_ADDR_HIGH);
2969 return 0;
2970 }
2971
2972 #ifdef CONFIG_NET_POLL_CONTROLLER
2973 /**
2974 * fec_poll_controller - FEC Poll controller function
2975 * @dev: The FEC network adapter
2976 *
2977 * Polled functionality used by netconsole and others in non interrupt mode
2978 *
2979 */
2980 static void fec_poll_controller(struct net_device *dev)
2981 {
2982 int i;
2983 struct fec_enet_private *fep = netdev_priv(dev);
2984
2985 for (i = 0; i < FEC_IRQ_NUM; i++) {
2986 if (fep->irq[i] > 0) {
2987 disable_irq(fep->irq[i]);
2988 fec_enet_interrupt(fep->irq[i], dev);
2989 enable_irq(fep->irq[i]);
2990 }
2991 }
2992 }
2993 #endif
2994
2995 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
2996 netdev_features_t features)
2997 {
2998 struct fec_enet_private *fep = netdev_priv(netdev);
2999 netdev_features_t changed = features ^ netdev->features;
3000
3001 netdev->features = features;
3002
3003 /* Receive checksum has been changed */
3004 if (changed & NETIF_F_RXCSUM) {
3005 if (features & NETIF_F_RXCSUM)
3006 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3007 else
3008 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3009 }
3010 }
3011
3012 static int fec_set_features(struct net_device *netdev,
3013 netdev_features_t features)
3014 {
3015 struct fec_enet_private *fep = netdev_priv(netdev);
3016 netdev_features_t changed = features ^ netdev->features;
3017
3018 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3019 napi_disable(&fep->napi);
3020 netif_tx_lock_bh(netdev);
3021 fec_stop(netdev);
3022 fec_enet_set_netdev_features(netdev, features);
3023 fec_restart(netdev);
3024 netif_tx_wake_all_queues(netdev);
3025 netif_tx_unlock_bh(netdev);
3026 napi_enable(&fep->napi);
3027 } else {
3028 fec_enet_set_netdev_features(netdev, features);
3029 }
3030
3031 return 0;
3032 }
3033
3034 static const struct net_device_ops fec_netdev_ops = {
3035 .ndo_open = fec_enet_open,
3036 .ndo_stop = fec_enet_close,
3037 .ndo_start_xmit = fec_enet_start_xmit,
3038 .ndo_set_rx_mode = set_multicast_list,
3039 .ndo_change_mtu = eth_change_mtu,
3040 .ndo_validate_addr = eth_validate_addr,
3041 .ndo_tx_timeout = fec_timeout,
3042 .ndo_set_mac_address = fec_set_mac_address,
3043 .ndo_do_ioctl = fec_enet_ioctl,
3044 #ifdef CONFIG_NET_POLL_CONTROLLER
3045 .ndo_poll_controller = fec_poll_controller,
3046 #endif
3047 .ndo_set_features = fec_set_features,
3048 };
3049
3050 static const unsigned short offset_des_active_rxq[] = {
3051 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3052 };
3053
3054 static const unsigned short offset_des_active_txq[] = {
3055 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3056 };
3057
3058 /*
3059 * XXX: We need to clean up on failure exits here.
3060 *
3061 */
3062 static int fec_enet_init(struct net_device *ndev)
3063 {
3064 struct fec_enet_private *fep = netdev_priv(ndev);
3065 struct bufdesc *cbd_base;
3066 dma_addr_t bd_dma;
3067 int bd_size;
3068 unsigned int i;
3069 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3070 sizeof(struct bufdesc);
3071 unsigned dsize_log2 = __fls(dsize);
3072
3073 WARN_ON(dsize != (1 << dsize_log2));
3074 #if defined(CONFIG_ARM)
3075 fep->rx_align = 0xf;
3076 fep->tx_align = 0xf;
3077 #else
3078 fep->rx_align = 0x3;
3079 fep->tx_align = 0x3;
3080 #endif
3081
3082 fec_enet_alloc_queue(ndev);
3083
3084 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
3085
3086 /* Allocate memory for buffer descriptors. */
3087 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3088 GFP_KERNEL);
3089 if (!cbd_base) {
3090 return -ENOMEM;
3091 }
3092
3093 memset(cbd_base, 0, bd_size);
3094
3095 /* Get the Ethernet address */
3096 fec_get_mac(ndev);
3097 /* make sure MAC we just acquired is programmed into the hw */
3098 fec_set_mac_address(ndev, NULL);
3099
3100 /* Set receive and transmit descriptor base. */
3101 for (i = 0; i < fep->num_rx_queues; i++) {
3102 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3103 unsigned size = dsize * rxq->bd.ring_size;
3104
3105 rxq->bd.qid = i;
3106 rxq->bd.base = cbd_base;
3107 rxq->bd.cur = cbd_base;
3108 rxq->bd.dma = bd_dma;
3109 rxq->bd.dsize = dsize;
3110 rxq->bd.dsize_log2 = dsize_log2;
3111 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
3112 bd_dma += size;
3113 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3114 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3115 }
3116
3117 for (i = 0; i < fep->num_tx_queues; i++) {
3118 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3119 unsigned size = dsize * txq->bd.ring_size;
3120
3121 txq->bd.qid = i;
3122 txq->bd.base = cbd_base;
3123 txq->bd.cur = cbd_base;
3124 txq->bd.dma = bd_dma;
3125 txq->bd.dsize = dsize;
3126 txq->bd.dsize_log2 = dsize_log2;
3127 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
3128 bd_dma += size;
3129 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3130 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3131 }
3132
3133
3134 /* The FEC Ethernet specific entries in the device structure */
3135 ndev->watchdog_timeo = TX_TIMEOUT;
3136 ndev->netdev_ops = &fec_netdev_ops;
3137 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3138
3139 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3140 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3141
3142 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3143 /* enable hw VLAN support */
3144 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3145
3146 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3147 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3148
3149 /* enable hw accelerator */
3150 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3151 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3152 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3153 }
3154
3155 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3156 fep->tx_align = 0;
3157 fep->rx_align = 0x3f;
3158 }
3159
3160 ndev->hw_features = ndev->features;
3161
3162 fec_restart(ndev);
3163
3164 return 0;
3165 }
3166
3167 #ifdef CONFIG_OF
3168 static void fec_reset_phy(struct platform_device *pdev)
3169 {
3170 int err, phy_reset;
3171 bool active_high = false;
3172 int msec = 1;
3173 struct device_node *np = pdev->dev.of_node;
3174
3175 if (!np)
3176 return;
3177
3178 of_property_read_u32(np, "phy-reset-duration", &msec);
3179 /* A sane reset duration should not be longer than 1s */
3180 if (msec > 1000)
3181 msec = 1;
3182
3183 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3184 if (!gpio_is_valid(phy_reset))
3185 return;
3186
3187 active_high = of_property_read_bool(np, "phy-reset-active-high");
3188
3189 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3190 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
3191 "phy-reset");
3192 if (err) {
3193 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3194 return;
3195 }
3196 msleep(msec);
3197 gpio_set_value_cansleep(phy_reset, !active_high);
3198 }
3199 #else /* CONFIG_OF */
3200 static void fec_reset_phy(struct platform_device *pdev)
3201 {
3202 /*
3203 * In case of platform probe, the reset has been done
3204 * by machine code.
3205 */
3206 }
3207 #endif /* CONFIG_OF */
3208
3209 static void
3210 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3211 {
3212 struct device_node *np = pdev->dev.of_node;
3213
3214 *num_tx = *num_rx = 1;
3215
3216 if (!np || !of_device_is_available(np))
3217 return;
3218
3219 /* parse the num of tx and rx queues */
3220 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3221
3222 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3223
3224 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3225 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3226 *num_tx);
3227 *num_tx = 1;
3228 return;
3229 }
3230
3231 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3232 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3233 *num_rx);
3234 *num_rx = 1;
3235 return;
3236 }
3237
3238 }
3239
3240 static int
3241 fec_probe(struct platform_device *pdev)
3242 {
3243 struct fec_enet_private *fep;
3244 struct fec_platform_data *pdata;
3245 struct net_device *ndev;
3246 int i, irq, ret = 0;
3247 struct resource *r;
3248 const struct of_device_id *of_id;
3249 static int dev_id;
3250 struct device_node *np = pdev->dev.of_node, *phy_node;
3251 int num_tx_qs;
3252 int num_rx_qs;
3253
3254 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3255
3256 /* Init network device */
3257 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3258 num_tx_qs, num_rx_qs);
3259 if (!ndev)
3260 return -ENOMEM;
3261
3262 SET_NETDEV_DEV(ndev, &pdev->dev);
3263
3264 /* setup board info structure */
3265 fep = netdev_priv(ndev);
3266
3267 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3268 if (of_id)
3269 pdev->id_entry = of_id->data;
3270 fep->quirks = pdev->id_entry->driver_data;
3271
3272 fep->netdev = ndev;
3273 fep->num_rx_queues = num_rx_qs;
3274 fep->num_tx_queues = num_tx_qs;
3275
3276 #if !defined(CONFIG_M5272)
3277 /* default enable pause frame auto negotiation */
3278 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3279 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3280 #endif
3281
3282 /* Select default pin state */
3283 pinctrl_pm_select_default_state(&pdev->dev);
3284
3285 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3286 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3287 if (IS_ERR(fep->hwp)) {
3288 ret = PTR_ERR(fep->hwp);
3289 goto failed_ioremap;
3290 }
3291
3292 fep->pdev = pdev;
3293 fep->dev_id = dev_id++;
3294
3295 platform_set_drvdata(pdev, ndev);
3296
3297 if (of_get_property(np, "fsl,magic-packet", NULL))
3298 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3299
3300 phy_node = of_parse_phandle(np, "phy-handle", 0);
3301 if (!phy_node && of_phy_is_fixed_link(np)) {
3302 ret = of_phy_register_fixed_link(np);
3303 if (ret < 0) {
3304 dev_err(&pdev->dev,
3305 "broken fixed-link specification\n");
3306 goto failed_phy;
3307 }
3308 phy_node = of_node_get(np);
3309 }
3310 fep->phy_node = phy_node;
3311
3312 ret = of_get_phy_mode(pdev->dev.of_node);
3313 if (ret < 0) {
3314 pdata = dev_get_platdata(&pdev->dev);
3315 if (pdata)
3316 fep->phy_interface = pdata->phy;
3317 else
3318 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3319 } else {
3320 fep->phy_interface = ret;
3321 }
3322
3323 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3324 if (IS_ERR(fep->clk_ipg)) {
3325 ret = PTR_ERR(fep->clk_ipg);
3326 goto failed_clk;
3327 }
3328
3329 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3330 if (IS_ERR(fep->clk_ahb)) {
3331 ret = PTR_ERR(fep->clk_ahb);
3332 goto failed_clk;
3333 }
3334
3335 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3336
3337 /* enet_out is optional, depends on board */
3338 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3339 if (IS_ERR(fep->clk_enet_out))
3340 fep->clk_enet_out = NULL;
3341
3342 fep->ptp_clk_on = false;
3343 mutex_init(&fep->ptp_clk_mutex);
3344
3345 /* clk_ref is optional, depends on board */
3346 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3347 if (IS_ERR(fep->clk_ref))
3348 fep->clk_ref = NULL;
3349
3350 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3351 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3352 if (IS_ERR(fep->clk_ptp)) {
3353 fep->clk_ptp = NULL;
3354 fep->bufdesc_ex = false;
3355 }
3356
3357 ret = fec_enet_clk_enable(ndev, true);
3358 if (ret)
3359 goto failed_clk;
3360
3361 ret = clk_prepare_enable(fep->clk_ipg);
3362 if (ret)
3363 goto failed_clk_ipg;
3364
3365 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3366 if (!IS_ERR(fep->reg_phy)) {
3367 ret = regulator_enable(fep->reg_phy);
3368 if (ret) {
3369 dev_err(&pdev->dev,
3370 "Failed to enable phy regulator: %d\n", ret);
3371 goto failed_regulator;
3372 }
3373 } else {
3374 fep->reg_phy = NULL;
3375 }
3376
3377 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3378 pm_runtime_use_autosuspend(&pdev->dev);
3379 pm_runtime_get_noresume(&pdev->dev);
3380 pm_runtime_set_active(&pdev->dev);
3381 pm_runtime_enable(&pdev->dev);
3382
3383 fec_reset_phy(pdev);
3384
3385 if (fep->bufdesc_ex)
3386 fec_ptp_init(pdev);
3387
3388 ret = fec_enet_init(ndev);
3389 if (ret)
3390 goto failed_init;
3391
3392 for (i = 0; i < FEC_IRQ_NUM; i++) {
3393 irq = platform_get_irq(pdev, i);
3394 if (irq < 0) {
3395 if (i)
3396 break;
3397 ret = irq;
3398 goto failed_irq;
3399 }
3400 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3401 0, pdev->name, ndev);
3402 if (ret)
3403 goto failed_irq;
3404
3405 fep->irq[i] = irq;
3406 }
3407
3408 init_completion(&fep->mdio_done);
3409 ret = fec_enet_mii_init(pdev);
3410 if (ret)
3411 goto failed_mii_init;
3412
3413 /* Carrier starts down, phylib will bring it up */
3414 netif_carrier_off(ndev);
3415 fec_enet_clk_enable(ndev, false);
3416 pinctrl_pm_select_sleep_state(&pdev->dev);
3417
3418 ret = register_netdev(ndev);
3419 if (ret)
3420 goto failed_register;
3421
3422 device_init_wakeup(&ndev->dev, fep->wol_flag &
3423 FEC_WOL_HAS_MAGIC_PACKET);
3424
3425 if (fep->bufdesc_ex && fep->ptp_clock)
3426 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3427
3428 fep->rx_copybreak = COPYBREAK_DEFAULT;
3429 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3430
3431 pm_runtime_mark_last_busy(&pdev->dev);
3432 pm_runtime_put_autosuspend(&pdev->dev);
3433
3434 return 0;
3435
3436 failed_register:
3437 fec_enet_mii_remove(fep);
3438 failed_mii_init:
3439 failed_irq:
3440 failed_init:
3441 fec_ptp_stop(pdev);
3442 if (fep->reg_phy)
3443 regulator_disable(fep->reg_phy);
3444 failed_regulator:
3445 clk_disable_unprepare(fep->clk_ipg);
3446 failed_clk_ipg:
3447 fec_enet_clk_enable(ndev, false);
3448 failed_clk:
3449 failed_phy:
3450 of_node_put(phy_node);
3451 failed_ioremap:
3452 free_netdev(ndev);
3453
3454 return ret;
3455 }
3456
3457 static int
3458 fec_drv_remove(struct platform_device *pdev)
3459 {
3460 struct net_device *ndev = platform_get_drvdata(pdev);
3461 struct fec_enet_private *fep = netdev_priv(ndev);
3462
3463 cancel_work_sync(&fep->tx_timeout_work);
3464 fec_ptp_stop(pdev);
3465 unregister_netdev(ndev);
3466 fec_enet_mii_remove(fep);
3467 if (fep->reg_phy)
3468 regulator_disable(fep->reg_phy);
3469 of_node_put(fep->phy_node);
3470 free_netdev(ndev);
3471
3472 return 0;
3473 }
3474
3475 static int __maybe_unused fec_suspend(struct device *dev)
3476 {
3477 struct net_device *ndev = dev_get_drvdata(dev);
3478 struct fec_enet_private *fep = netdev_priv(ndev);
3479
3480 rtnl_lock();
3481 if (netif_running(ndev)) {
3482 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3483 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3484 phy_stop(ndev->phydev);
3485 napi_disable(&fep->napi);
3486 netif_tx_lock_bh(ndev);
3487 netif_device_detach(ndev);
3488 netif_tx_unlock_bh(ndev);
3489 fec_stop(ndev);
3490 fec_enet_clk_enable(ndev, false);
3491 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3492 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3493 }
3494 rtnl_unlock();
3495
3496 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3497 regulator_disable(fep->reg_phy);
3498
3499 /* SOC supply clock to phy, when clock is disabled, phy link down
3500 * SOC control phy regulator, when regulator is disabled, phy link down
3501 */
3502 if (fep->clk_enet_out || fep->reg_phy)
3503 fep->link = 0;
3504
3505 return 0;
3506 }
3507
3508 static int __maybe_unused fec_resume(struct device *dev)
3509 {
3510 struct net_device *ndev = dev_get_drvdata(dev);
3511 struct fec_enet_private *fep = netdev_priv(ndev);
3512 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3513 int ret;
3514 int val;
3515
3516 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3517 ret = regulator_enable(fep->reg_phy);
3518 if (ret)
3519 return ret;
3520 }
3521
3522 rtnl_lock();
3523 if (netif_running(ndev)) {
3524 ret = fec_enet_clk_enable(ndev, true);
3525 if (ret) {
3526 rtnl_unlock();
3527 goto failed_clk;
3528 }
3529 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3530 if (pdata && pdata->sleep_mode_enable)
3531 pdata->sleep_mode_enable(false);
3532 val = readl(fep->hwp + FEC_ECNTRL);
3533 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3534 writel(val, fep->hwp + FEC_ECNTRL);
3535 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3536 } else {
3537 pinctrl_pm_select_default_state(&fep->pdev->dev);
3538 }
3539 fec_restart(ndev);
3540 netif_tx_lock_bh(ndev);
3541 netif_device_attach(ndev);
3542 netif_tx_unlock_bh(ndev);
3543 napi_enable(&fep->napi);
3544 phy_start(ndev->phydev);
3545 }
3546 rtnl_unlock();
3547
3548 return 0;
3549
3550 failed_clk:
3551 if (fep->reg_phy)
3552 regulator_disable(fep->reg_phy);
3553 return ret;
3554 }
3555
3556 static int __maybe_unused fec_runtime_suspend(struct device *dev)
3557 {
3558 struct net_device *ndev = dev_get_drvdata(dev);
3559 struct fec_enet_private *fep = netdev_priv(ndev);
3560
3561 clk_disable_unprepare(fep->clk_ipg);
3562
3563 return 0;
3564 }
3565
3566 static int __maybe_unused fec_runtime_resume(struct device *dev)
3567 {
3568 struct net_device *ndev = dev_get_drvdata(dev);
3569 struct fec_enet_private *fep = netdev_priv(ndev);
3570
3571 return clk_prepare_enable(fep->clk_ipg);
3572 }
3573
3574 static const struct dev_pm_ops fec_pm_ops = {
3575 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3576 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3577 };
3578
3579 static struct platform_driver fec_driver = {
3580 .driver = {
3581 .name = DRIVER_NAME,
3582 .pm = &fec_pm_ops,
3583 .of_match_table = fec_dt_ids,
3584 },
3585 .id_table = fec_devtype,
3586 .probe = fec_probe,
3587 .remove = fec_drv_remove,
3588 };
3589
3590 module_platform_driver(fec_driver);
3591
3592 MODULE_ALIAS("platform:"DRIVER_NAME);
3593 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.203684 seconds and 5 git commands to generate.