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Merge branch 'pci/resource' into next
[deliverable/linux.git] / drivers / net / ethernet / freescale / fec_main.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/in.h>
37 #include <linux/ip.h>
38 #include <net/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/udp.h>
41 #include <linux/icmp.h>
42 #include <linux/spinlock.h>
43 #include <linux/workqueue.h>
44 #include <linux/bitops.h>
45 #include <linux/io.h>
46 #include <linux/irq.h>
47 #include <linux/clk.h>
48 #include <linux/platform_device.h>
49 #include <linux/phy.h>
50 #include <linux/fec.h>
51 #include <linux/of.h>
52 #include <linux/of_device.h>
53 #include <linux/of_gpio.h>
54 #include <linux/of_net.h>
55 #include <linux/regulator/consumer.h>
56 #include <linux/if_vlan.h>
57
58 #include <asm/cacheflush.h>
59
60 #include "fec.h"
61
62 static void set_multicast_list(struct net_device *ndev);
63
64 #if defined(CONFIG_ARM)
65 #define FEC_ALIGNMENT 0xf
66 #else
67 #define FEC_ALIGNMENT 0x3
68 #endif
69
70 #define DRIVER_NAME "fec"
71
72 /* Pause frame feild and FIFO threshold */
73 #define FEC_ENET_FCE (1 << 5)
74 #define FEC_ENET_RSEM_V 0x84
75 #define FEC_ENET_RSFL_V 16
76 #define FEC_ENET_RAEM_V 0x8
77 #define FEC_ENET_RAFL_V 0x8
78 #define FEC_ENET_OPD_V 0xFFF0
79
80 /* Controller is ENET-MAC */
81 #define FEC_QUIRK_ENET_MAC (1 << 0)
82 /* Controller needs driver to swap frame */
83 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
84 /* Controller uses gasket */
85 #define FEC_QUIRK_USE_GASKET (1 << 2)
86 /* Controller has GBIT support */
87 #define FEC_QUIRK_HAS_GBIT (1 << 3)
88 /* Controller has extend desc buffer */
89 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
90 /* Controller has hardware checksum support */
91 #define FEC_QUIRK_HAS_CSUM (1 << 5)
92 /* Controller has hardware vlan support */
93 #define FEC_QUIRK_HAS_VLAN (1 << 6)
94 /* ENET IP errata ERR006358
95 *
96 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
97 * detected as not set during a prior frame transmission, then the
98 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
99 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
100 * frames not being transmitted until there is a 0-to-1 transition on
101 * ENET_TDAR[TDAR].
102 */
103 #define FEC_QUIRK_ERR006358 (1 << 7)
104
105 static struct platform_device_id fec_devtype[] = {
106 {
107 /* keep it for coldfire */
108 .name = DRIVER_NAME,
109 .driver_data = 0,
110 }, {
111 .name = "imx25-fec",
112 .driver_data = FEC_QUIRK_USE_GASKET,
113 }, {
114 .name = "imx27-fec",
115 .driver_data = 0,
116 }, {
117 .name = "imx28-fec",
118 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
119 }, {
120 .name = "imx6q-fec",
121 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
122 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
123 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
124 }, {
125 .name = "mvf600-fec",
126 .driver_data = FEC_QUIRK_ENET_MAC,
127 }, {
128 /* sentinel */
129 }
130 };
131 MODULE_DEVICE_TABLE(platform, fec_devtype);
132
133 enum imx_fec_type {
134 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
135 IMX27_FEC, /* runs on i.mx27/35/51 */
136 IMX28_FEC,
137 IMX6Q_FEC,
138 MVF600_FEC,
139 };
140
141 static const struct of_device_id fec_dt_ids[] = {
142 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
143 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
144 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
145 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
146 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
147 { /* sentinel */ }
148 };
149 MODULE_DEVICE_TABLE(of, fec_dt_ids);
150
151 static unsigned char macaddr[ETH_ALEN];
152 module_param_array(macaddr, byte, NULL, 0);
153 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
154
155 #if defined(CONFIG_M5272)
156 /*
157 * Some hardware gets it MAC address out of local flash memory.
158 * if this is non-zero then assume it is the address to get MAC from.
159 */
160 #if defined(CONFIG_NETtel)
161 #define FEC_FLASHMAC 0xf0006006
162 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
163 #define FEC_FLASHMAC 0xf0006000
164 #elif defined(CONFIG_CANCam)
165 #define FEC_FLASHMAC 0xf0020000
166 #elif defined (CONFIG_M5272C3)
167 #define FEC_FLASHMAC (0xffe04000 + 4)
168 #elif defined(CONFIG_MOD5272)
169 #define FEC_FLASHMAC 0xffc0406b
170 #else
171 #define FEC_FLASHMAC 0
172 #endif
173 #endif /* CONFIG_M5272 */
174
175 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
176 #error "FEC: descriptor ring size constants too large"
177 #endif
178
179 /* Interrupt events/masks. */
180 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
181 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
182 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
183 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
184 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
185 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
186 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
187 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
188 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
189 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
190
191 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
192 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
193
194 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
195 */
196 #define PKT_MAXBUF_SIZE 1522
197 #define PKT_MINBUF_SIZE 64
198 #define PKT_MAXBLR_SIZE 1536
199
200 /* FEC receive acceleration */
201 #define FEC_RACC_IPDIS (1 << 1)
202 #define FEC_RACC_PRODIS (1 << 2)
203 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
204
205 /*
206 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
207 * size bits. Other FEC hardware does not, so we need to take that into
208 * account when setting it.
209 */
210 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
211 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
212 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
213 #else
214 #define OPT_FRAME_SIZE 0
215 #endif
216
217 /* FEC MII MMFR bits definition */
218 #define FEC_MMFR_ST (1 << 30)
219 #define FEC_MMFR_OP_READ (2 << 28)
220 #define FEC_MMFR_OP_WRITE (1 << 28)
221 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
222 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
223 #define FEC_MMFR_TA (2 << 16)
224 #define FEC_MMFR_DATA(v) (v & 0xffff)
225
226 #define FEC_MII_TIMEOUT 30000 /* us */
227
228 /* Transmitter timeout */
229 #define TX_TIMEOUT (2 * HZ)
230
231 #define FEC_PAUSE_FLAG_AUTONEG 0x1
232 #define FEC_PAUSE_FLAG_ENABLE 0x2
233
234 static int mii_cnt;
235
236 static inline
237 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
238 {
239 struct bufdesc *new_bd = bdp + 1;
240 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
241 struct bufdesc_ex *ex_base;
242 struct bufdesc *base;
243 int ring_size;
244
245 if (bdp >= fep->tx_bd_base) {
246 base = fep->tx_bd_base;
247 ring_size = fep->tx_ring_size;
248 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
249 } else {
250 base = fep->rx_bd_base;
251 ring_size = fep->rx_ring_size;
252 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
253 }
254
255 if (fep->bufdesc_ex)
256 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
257 ex_base : ex_new_bd);
258 else
259 return (new_bd >= (base + ring_size)) ?
260 base : new_bd;
261 }
262
263 static inline
264 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
265 {
266 struct bufdesc *new_bd = bdp - 1;
267 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
268 struct bufdesc_ex *ex_base;
269 struct bufdesc *base;
270 int ring_size;
271
272 if (bdp >= fep->tx_bd_base) {
273 base = fep->tx_bd_base;
274 ring_size = fep->tx_ring_size;
275 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
276 } else {
277 base = fep->rx_bd_base;
278 ring_size = fep->rx_ring_size;
279 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
280 }
281
282 if (fep->bufdesc_ex)
283 return (struct bufdesc *)((ex_new_bd < ex_base) ?
284 (ex_new_bd + ring_size) : ex_new_bd);
285 else
286 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
287 }
288
289 static void *swap_buffer(void *bufaddr, int len)
290 {
291 int i;
292 unsigned int *buf = bufaddr;
293
294 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
295 *buf = cpu_to_be32(*buf);
296
297 return bufaddr;
298 }
299
300 static int
301 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
302 {
303 /* Only run for packets requiring a checksum. */
304 if (skb->ip_summed != CHECKSUM_PARTIAL)
305 return 0;
306
307 if (unlikely(skb_cow_head(skb, 0)))
308 return -1;
309
310 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
311
312 return 0;
313 }
314
315 static netdev_tx_t
316 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
317 {
318 struct fec_enet_private *fep = netdev_priv(ndev);
319 const struct platform_device_id *id_entry =
320 platform_get_device_id(fep->pdev);
321 struct bufdesc *bdp, *bdp_pre;
322 void *bufaddr;
323 unsigned short status;
324 unsigned int index;
325
326 /* Fill in a Tx ring entry */
327 bdp = fep->cur_tx;
328
329 status = bdp->cbd_sc;
330
331 if (status & BD_ENET_TX_READY) {
332 /* Ooops. All transmit buffers are full. Bail out.
333 * This should not happen, since ndev->tbusy should be set.
334 */
335 netdev_err(ndev, "tx queue full!\n");
336 return NETDEV_TX_BUSY;
337 }
338
339 /* Protocol checksum off-load for TCP and UDP. */
340 if (fec_enet_clear_csum(skb, ndev)) {
341 kfree_skb(skb);
342 return NETDEV_TX_OK;
343 }
344
345 /* Clear all of the status flags */
346 status &= ~BD_ENET_TX_STATS;
347
348 /* Set buffer length and buffer pointer */
349 bufaddr = skb->data;
350 bdp->cbd_datlen = skb->len;
351
352 /*
353 * On some FEC implementations data must be aligned on
354 * 4-byte boundaries. Use bounce buffers to copy data
355 * and get it aligned. Ugh.
356 */
357 if (fep->bufdesc_ex)
358 index = (struct bufdesc_ex *)bdp -
359 (struct bufdesc_ex *)fep->tx_bd_base;
360 else
361 index = bdp - fep->tx_bd_base;
362
363 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
364 memcpy(fep->tx_bounce[index], skb->data, skb->len);
365 bufaddr = fep->tx_bounce[index];
366 }
367
368 /*
369 * Some design made an incorrect assumption on endian mode of
370 * the system that it's running on. As the result, driver has to
371 * swap every frame going to and coming from the controller.
372 */
373 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
374 swap_buffer(bufaddr, skb->len);
375
376 /* Save skb pointer */
377 fep->tx_skbuff[index] = skb;
378
379 /* Push the data cache so the CPM does not get stale memory
380 * data.
381 */
382 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
383 skb->len, DMA_TO_DEVICE);
384 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
385 bdp->cbd_bufaddr = 0;
386 fep->tx_skbuff[index] = NULL;
387 dev_kfree_skb_any(skb);
388 if (net_ratelimit())
389 netdev_err(ndev, "Tx DMA memory map failed\n");
390 return NETDEV_TX_OK;
391 }
392 /* Send it on its way. Tell FEC it's ready, interrupt when done,
393 * it's the last BD of the frame, and to put the CRC on the end.
394 */
395 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
396 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
397 bdp->cbd_sc = status;
398
399 if (fep->bufdesc_ex) {
400
401 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
402 ebdp->cbd_bdu = 0;
403 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
404 fep->hwts_tx_en)) {
405 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
406 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
407 } else {
408 ebdp->cbd_esc = BD_ENET_TX_INT;
409
410 /* Enable protocol checksum flags
411 * We do not bother with the IP Checksum bits as they
412 * are done by the kernel
413 */
414 if (skb->ip_summed == CHECKSUM_PARTIAL)
415 ebdp->cbd_esc |= BD_ENET_TX_PINS;
416 }
417 }
418
419 bdp_pre = fec_enet_get_prevdesc(bdp, fep);
420 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) &&
421 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) {
422 fep->delay_work.trig_tx = true;
423 schedule_delayed_work(&(fep->delay_work.delay_work),
424 msecs_to_jiffies(1));
425 }
426
427 /* If this was the last BD in the ring, start at the beginning again. */
428 bdp = fec_enet_get_nextdesc(bdp, fep);
429
430 skb_tx_timestamp(skb);
431
432 fep->cur_tx = bdp;
433
434 if (fep->cur_tx == fep->dirty_tx)
435 netif_stop_queue(ndev);
436
437 /* Trigger transmission start */
438 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
439
440 return NETDEV_TX_OK;
441 }
442
443 /* Init RX & TX buffer descriptors
444 */
445 static void fec_enet_bd_init(struct net_device *dev)
446 {
447 struct fec_enet_private *fep = netdev_priv(dev);
448 struct bufdesc *bdp;
449 unsigned int i;
450
451 /* Initialize the receive buffer descriptors. */
452 bdp = fep->rx_bd_base;
453 for (i = 0; i < fep->rx_ring_size; i++) {
454
455 /* Initialize the BD for every fragment in the page. */
456 if (bdp->cbd_bufaddr)
457 bdp->cbd_sc = BD_ENET_RX_EMPTY;
458 else
459 bdp->cbd_sc = 0;
460 bdp = fec_enet_get_nextdesc(bdp, fep);
461 }
462
463 /* Set the last buffer to wrap */
464 bdp = fec_enet_get_prevdesc(bdp, fep);
465 bdp->cbd_sc |= BD_SC_WRAP;
466
467 fep->cur_rx = fep->rx_bd_base;
468
469 /* ...and the same for transmit */
470 bdp = fep->tx_bd_base;
471 fep->cur_tx = bdp;
472 for (i = 0; i < fep->tx_ring_size; i++) {
473
474 /* Initialize the BD for every fragment in the page. */
475 bdp->cbd_sc = 0;
476 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
477 dev_kfree_skb_any(fep->tx_skbuff[i]);
478 fep->tx_skbuff[i] = NULL;
479 }
480 bdp->cbd_bufaddr = 0;
481 bdp = fec_enet_get_nextdesc(bdp, fep);
482 }
483
484 /* Set the last buffer to wrap */
485 bdp = fec_enet_get_prevdesc(bdp, fep);
486 bdp->cbd_sc |= BD_SC_WRAP;
487 fep->dirty_tx = bdp;
488 }
489
490 /* This function is called to start or restart the FEC during a link
491 * change. This only happens when switching between half and full
492 * duplex.
493 */
494 static void
495 fec_restart(struct net_device *ndev, int duplex)
496 {
497 struct fec_enet_private *fep = netdev_priv(ndev);
498 const struct platform_device_id *id_entry =
499 platform_get_device_id(fep->pdev);
500 int i;
501 u32 val;
502 u32 temp_mac[2];
503 u32 rcntl = OPT_FRAME_SIZE | 0x04;
504 u32 ecntl = 0x2; /* ETHEREN */
505
506 if (netif_running(ndev)) {
507 netif_device_detach(ndev);
508 napi_disable(&fep->napi);
509 netif_stop_queue(ndev);
510 netif_tx_lock_bh(ndev);
511 }
512
513 /* Whack a reset. We should wait for this. */
514 writel(1, fep->hwp + FEC_ECNTRL);
515 udelay(10);
516
517 /*
518 * enet-mac reset will reset mac address registers too,
519 * so need to reconfigure it.
520 */
521 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
522 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
523 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
524 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
525 }
526
527 /* Clear any outstanding interrupt. */
528 writel(0xffc00000, fep->hwp + FEC_IEVENT);
529
530 /* Setup multicast filter. */
531 set_multicast_list(ndev);
532 #ifndef CONFIG_M5272
533 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
534 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
535 #endif
536
537 /* Set maximum receive buffer size. */
538 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
539
540 fec_enet_bd_init(ndev);
541
542 /* Set receive and transmit descriptor base. */
543 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
544 if (fep->bufdesc_ex)
545 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
546 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
547 else
548 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
549 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
550
551
552 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
553 if (fep->tx_skbuff[i]) {
554 dev_kfree_skb_any(fep->tx_skbuff[i]);
555 fep->tx_skbuff[i] = NULL;
556 }
557 }
558
559 /* Enable MII mode */
560 if (duplex) {
561 /* FD enable */
562 writel(0x04, fep->hwp + FEC_X_CNTRL);
563 } else {
564 /* No Rcv on Xmit */
565 rcntl |= 0x02;
566 writel(0x0, fep->hwp + FEC_X_CNTRL);
567 }
568
569 fep->full_duplex = duplex;
570
571 /* Set MII speed */
572 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
573
574 #if !defined(CONFIG_M5272)
575 /* set RX checksum */
576 val = readl(fep->hwp + FEC_RACC);
577 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
578 val |= FEC_RACC_OPTIONS;
579 else
580 val &= ~FEC_RACC_OPTIONS;
581 writel(val, fep->hwp + FEC_RACC);
582 #endif
583
584 /*
585 * The phy interface and speed need to get configured
586 * differently on enet-mac.
587 */
588 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
589 /* Enable flow control and length check */
590 rcntl |= 0x40000000 | 0x00000020;
591
592 /* RGMII, RMII or MII */
593 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
594 rcntl |= (1 << 6);
595 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
596 rcntl |= (1 << 8);
597 else
598 rcntl &= ~(1 << 8);
599
600 /* 1G, 100M or 10M */
601 if (fep->phy_dev) {
602 if (fep->phy_dev->speed == SPEED_1000)
603 ecntl |= (1 << 5);
604 else if (fep->phy_dev->speed == SPEED_100)
605 rcntl &= ~(1 << 9);
606 else
607 rcntl |= (1 << 9);
608 }
609 } else {
610 #ifdef FEC_MIIGSK_ENR
611 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
612 u32 cfgr;
613 /* disable the gasket and wait */
614 writel(0, fep->hwp + FEC_MIIGSK_ENR);
615 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
616 udelay(1);
617
618 /*
619 * configure the gasket:
620 * RMII, 50 MHz, no loopback, no echo
621 * MII, 25 MHz, no loopback, no echo
622 */
623 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
624 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
625 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
626 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
627 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
628
629 /* re-enable the gasket */
630 writel(2, fep->hwp + FEC_MIIGSK_ENR);
631 }
632 #endif
633 }
634
635 #if !defined(CONFIG_M5272)
636 /* enable pause frame*/
637 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
638 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
639 fep->phy_dev && fep->phy_dev->pause)) {
640 rcntl |= FEC_ENET_FCE;
641
642 /* set FIFO threshold parameter to reduce overrun */
643 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
644 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
645 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
646 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
647
648 /* OPD */
649 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
650 } else {
651 rcntl &= ~FEC_ENET_FCE;
652 }
653 #endif /* !defined(CONFIG_M5272) */
654
655 writel(rcntl, fep->hwp + FEC_R_CNTRL);
656
657 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
658 /* enable ENET endian swap */
659 ecntl |= (1 << 8);
660 /* enable ENET store and forward mode */
661 writel(1 << 8, fep->hwp + FEC_X_WMRK);
662 }
663
664 if (fep->bufdesc_ex)
665 ecntl |= (1 << 4);
666
667 #ifndef CONFIG_M5272
668 /* Enable the MIB statistic event counters */
669 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
670 #endif
671
672 /* And last, enable the transmit and receive processing */
673 writel(ecntl, fep->hwp + FEC_ECNTRL);
674 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
675
676 if (fep->bufdesc_ex)
677 fec_ptp_start_cyclecounter(ndev);
678
679 /* Enable interrupts we wish to service */
680 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
681
682 if (netif_running(ndev)) {
683 netif_tx_unlock_bh(ndev);
684 netif_wake_queue(ndev);
685 napi_enable(&fep->napi);
686 netif_device_attach(ndev);
687 }
688 }
689
690 static void
691 fec_stop(struct net_device *ndev)
692 {
693 struct fec_enet_private *fep = netdev_priv(ndev);
694 const struct platform_device_id *id_entry =
695 platform_get_device_id(fep->pdev);
696 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
697
698 /* We cannot expect a graceful transmit stop without link !!! */
699 if (fep->link) {
700 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
701 udelay(10);
702 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
703 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
704 }
705
706 /* Whack a reset. We should wait for this. */
707 writel(1, fep->hwp + FEC_ECNTRL);
708 udelay(10);
709 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
710 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
711
712 /* We have to keep ENET enabled to have MII interrupt stay working */
713 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
714 writel(2, fep->hwp + FEC_ECNTRL);
715 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
716 }
717 }
718
719
720 static void
721 fec_timeout(struct net_device *ndev)
722 {
723 struct fec_enet_private *fep = netdev_priv(ndev);
724
725 ndev->stats.tx_errors++;
726
727 fep->delay_work.timeout = true;
728 schedule_delayed_work(&(fep->delay_work.delay_work), 0);
729 }
730
731 static void fec_enet_work(struct work_struct *work)
732 {
733 struct fec_enet_private *fep =
734 container_of(work,
735 struct fec_enet_private,
736 delay_work.delay_work.work);
737
738 if (fep->delay_work.timeout) {
739 fep->delay_work.timeout = false;
740 fec_restart(fep->netdev, fep->full_duplex);
741 netif_wake_queue(fep->netdev);
742 }
743
744 if (fep->delay_work.trig_tx) {
745 fep->delay_work.trig_tx = false;
746 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
747 }
748 }
749
750 static void
751 fec_enet_tx(struct net_device *ndev)
752 {
753 struct fec_enet_private *fep;
754 struct bufdesc *bdp;
755 unsigned short status;
756 struct sk_buff *skb;
757 int index = 0;
758
759 fep = netdev_priv(ndev);
760 bdp = fep->dirty_tx;
761
762 /* get next bdp of dirty_tx */
763 bdp = fec_enet_get_nextdesc(bdp, fep);
764
765 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
766
767 /* current queue is empty */
768 if (bdp == fep->cur_tx)
769 break;
770
771 if (fep->bufdesc_ex)
772 index = (struct bufdesc_ex *)bdp -
773 (struct bufdesc_ex *)fep->tx_bd_base;
774 else
775 index = bdp - fep->tx_bd_base;
776
777 skb = fep->tx_skbuff[index];
778 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, skb->len,
779 DMA_TO_DEVICE);
780 bdp->cbd_bufaddr = 0;
781
782 /* Check for errors. */
783 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
784 BD_ENET_TX_RL | BD_ENET_TX_UN |
785 BD_ENET_TX_CSL)) {
786 ndev->stats.tx_errors++;
787 if (status & BD_ENET_TX_HB) /* No heartbeat */
788 ndev->stats.tx_heartbeat_errors++;
789 if (status & BD_ENET_TX_LC) /* Late collision */
790 ndev->stats.tx_window_errors++;
791 if (status & BD_ENET_TX_RL) /* Retrans limit */
792 ndev->stats.tx_aborted_errors++;
793 if (status & BD_ENET_TX_UN) /* Underrun */
794 ndev->stats.tx_fifo_errors++;
795 if (status & BD_ENET_TX_CSL) /* Carrier lost */
796 ndev->stats.tx_carrier_errors++;
797 } else {
798 ndev->stats.tx_packets++;
799 ndev->stats.tx_bytes += bdp->cbd_datlen;
800 }
801
802 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
803 fep->bufdesc_ex) {
804 struct skb_shared_hwtstamps shhwtstamps;
805 unsigned long flags;
806 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
807
808 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
809 spin_lock_irqsave(&fep->tmreg_lock, flags);
810 shhwtstamps.hwtstamp = ns_to_ktime(
811 timecounter_cyc2time(&fep->tc, ebdp->ts));
812 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
813 skb_tstamp_tx(skb, &shhwtstamps);
814 }
815
816 if (status & BD_ENET_TX_READY)
817 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
818
819 /* Deferred means some collisions occurred during transmit,
820 * but we eventually sent the packet OK.
821 */
822 if (status & BD_ENET_TX_DEF)
823 ndev->stats.collisions++;
824
825 /* Free the sk buffer associated with this last transmit */
826 dev_kfree_skb_any(skb);
827 fep->tx_skbuff[index] = NULL;
828
829 fep->dirty_tx = bdp;
830
831 /* Update pointer to next buffer descriptor to be transmitted */
832 bdp = fec_enet_get_nextdesc(bdp, fep);
833
834 /* Since we have freed up a buffer, the ring is no longer full
835 */
836 if (fep->dirty_tx != fep->cur_tx) {
837 if (netif_queue_stopped(ndev))
838 netif_wake_queue(ndev);
839 }
840 }
841 return;
842 }
843
844
845 /* During a receive, the cur_rx points to the current incoming buffer.
846 * When we update through the ring, if the next incoming buffer has
847 * not been given to the system, we just set the empty indicator,
848 * effectively tossing the packet.
849 */
850 static int
851 fec_enet_rx(struct net_device *ndev, int budget)
852 {
853 struct fec_enet_private *fep = netdev_priv(ndev);
854 const struct platform_device_id *id_entry =
855 platform_get_device_id(fep->pdev);
856 struct bufdesc *bdp;
857 unsigned short status;
858 struct sk_buff *skb;
859 ushort pkt_len;
860 __u8 *data;
861 int pkt_received = 0;
862 struct bufdesc_ex *ebdp = NULL;
863 bool vlan_packet_rcvd = false;
864 u16 vlan_tag;
865 int index = 0;
866
867 #ifdef CONFIG_M532x
868 flush_cache_all();
869 #endif
870
871 /* First, grab all of the stats for the incoming packet.
872 * These get messed up if we get called due to a busy condition.
873 */
874 bdp = fep->cur_rx;
875
876 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
877
878 if (pkt_received >= budget)
879 break;
880 pkt_received++;
881
882 /* Since we have allocated space to hold a complete frame,
883 * the last indicator should be set.
884 */
885 if ((status & BD_ENET_RX_LAST) == 0)
886 netdev_err(ndev, "rcv is not +last\n");
887
888 if (!fep->opened)
889 goto rx_processing_done;
890
891 /* Check for errors. */
892 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
893 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
894 ndev->stats.rx_errors++;
895 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
896 /* Frame too long or too short. */
897 ndev->stats.rx_length_errors++;
898 }
899 if (status & BD_ENET_RX_NO) /* Frame alignment */
900 ndev->stats.rx_frame_errors++;
901 if (status & BD_ENET_RX_CR) /* CRC Error */
902 ndev->stats.rx_crc_errors++;
903 if (status & BD_ENET_RX_OV) /* FIFO overrun */
904 ndev->stats.rx_fifo_errors++;
905 }
906
907 /* Report late collisions as a frame error.
908 * On this error, the BD is closed, but we don't know what we
909 * have in the buffer. So, just drop this frame on the floor.
910 */
911 if (status & BD_ENET_RX_CL) {
912 ndev->stats.rx_errors++;
913 ndev->stats.rx_frame_errors++;
914 goto rx_processing_done;
915 }
916
917 /* Process the incoming frame. */
918 ndev->stats.rx_packets++;
919 pkt_len = bdp->cbd_datlen;
920 ndev->stats.rx_bytes += pkt_len;
921
922 if (fep->bufdesc_ex)
923 index = (struct bufdesc_ex *)bdp -
924 (struct bufdesc_ex *)fep->rx_bd_base;
925 else
926 index = bdp - fep->rx_bd_base;
927 data = fep->rx_skbuff[index]->data;
928 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
929 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
930
931 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
932 swap_buffer(data, pkt_len);
933
934 /* Extract the enhanced buffer descriptor */
935 ebdp = NULL;
936 if (fep->bufdesc_ex)
937 ebdp = (struct bufdesc_ex *)bdp;
938
939 /* If this is a VLAN packet remove the VLAN Tag */
940 vlan_packet_rcvd = false;
941 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
942 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
943 /* Push and remove the vlan tag */
944 struct vlan_hdr *vlan_header =
945 (struct vlan_hdr *) (data + ETH_HLEN);
946 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
947 pkt_len -= VLAN_HLEN;
948
949 vlan_packet_rcvd = true;
950 }
951
952 /* This does 16 byte alignment, exactly what we need.
953 * The packet length includes FCS, but we don't want to
954 * include that when passing upstream as it messes up
955 * bridging applications.
956 */
957 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
958
959 if (unlikely(!skb)) {
960 ndev->stats.rx_dropped++;
961 } else {
962 int payload_offset = (2 * ETH_ALEN);
963 skb_reserve(skb, NET_IP_ALIGN);
964 skb_put(skb, pkt_len - 4); /* Make room */
965
966 /* Extract the frame data without the VLAN header. */
967 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
968 if (vlan_packet_rcvd)
969 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
970 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
971 data + payload_offset,
972 pkt_len - 4 - (2 * ETH_ALEN));
973
974 skb->protocol = eth_type_trans(skb, ndev);
975
976 /* Get receive timestamp from the skb */
977 if (fep->hwts_rx_en && fep->bufdesc_ex) {
978 struct skb_shared_hwtstamps *shhwtstamps =
979 skb_hwtstamps(skb);
980 unsigned long flags;
981
982 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
983
984 spin_lock_irqsave(&fep->tmreg_lock, flags);
985 shhwtstamps->hwtstamp = ns_to_ktime(
986 timecounter_cyc2time(&fep->tc, ebdp->ts));
987 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
988 }
989
990 if (fep->bufdesc_ex &&
991 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
992 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
993 /* don't check it */
994 skb->ip_summed = CHECKSUM_UNNECESSARY;
995 } else {
996 skb_checksum_none_assert(skb);
997 }
998 }
999
1000 /* Handle received VLAN packets */
1001 if (vlan_packet_rcvd)
1002 __vlan_hwaccel_put_tag(skb,
1003 htons(ETH_P_8021Q),
1004 vlan_tag);
1005
1006 napi_gro_receive(&fep->napi, skb);
1007 }
1008
1009 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1010 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1011 rx_processing_done:
1012 /* Clear the status flags for this buffer */
1013 status &= ~BD_ENET_RX_STATS;
1014
1015 /* Mark the buffer empty */
1016 status |= BD_ENET_RX_EMPTY;
1017 bdp->cbd_sc = status;
1018
1019 if (fep->bufdesc_ex) {
1020 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1021
1022 ebdp->cbd_esc = BD_ENET_RX_INT;
1023 ebdp->cbd_prot = 0;
1024 ebdp->cbd_bdu = 0;
1025 }
1026
1027 /* Update BD pointer to next entry */
1028 bdp = fec_enet_get_nextdesc(bdp, fep);
1029
1030 /* Doing this here will keep the FEC running while we process
1031 * incoming frames. On a heavily loaded network, we should be
1032 * able to keep up at the expense of system resources.
1033 */
1034 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1035 }
1036 fep->cur_rx = bdp;
1037
1038 return pkt_received;
1039 }
1040
1041 static irqreturn_t
1042 fec_enet_interrupt(int irq, void *dev_id)
1043 {
1044 struct net_device *ndev = dev_id;
1045 struct fec_enet_private *fep = netdev_priv(ndev);
1046 uint int_events;
1047 irqreturn_t ret = IRQ_NONE;
1048
1049 do {
1050 int_events = readl(fep->hwp + FEC_IEVENT);
1051 writel(int_events, fep->hwp + FEC_IEVENT);
1052
1053 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
1054 ret = IRQ_HANDLED;
1055
1056 /* Disable the RX interrupt */
1057 if (napi_schedule_prep(&fep->napi)) {
1058 writel(FEC_RX_DISABLED_IMASK,
1059 fep->hwp + FEC_IMASK);
1060 __napi_schedule(&fep->napi);
1061 }
1062 }
1063
1064 if (int_events & FEC_ENET_MII) {
1065 ret = IRQ_HANDLED;
1066 complete(&fep->mdio_done);
1067 }
1068 } while (int_events);
1069
1070 return ret;
1071 }
1072
1073 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1074 {
1075 struct net_device *ndev = napi->dev;
1076 int pkts = fec_enet_rx(ndev, budget);
1077 struct fec_enet_private *fep = netdev_priv(ndev);
1078
1079 fec_enet_tx(ndev);
1080
1081 if (pkts < budget) {
1082 napi_complete(napi);
1083 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1084 }
1085 return pkts;
1086 }
1087
1088 /* ------------------------------------------------------------------------- */
1089 static void fec_get_mac(struct net_device *ndev)
1090 {
1091 struct fec_enet_private *fep = netdev_priv(ndev);
1092 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1093 unsigned char *iap, tmpaddr[ETH_ALEN];
1094
1095 /*
1096 * try to get mac address in following order:
1097 *
1098 * 1) module parameter via kernel command line in form
1099 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1100 */
1101 iap = macaddr;
1102
1103 /*
1104 * 2) from device tree data
1105 */
1106 if (!is_valid_ether_addr(iap)) {
1107 struct device_node *np = fep->pdev->dev.of_node;
1108 if (np) {
1109 const char *mac = of_get_mac_address(np);
1110 if (mac)
1111 iap = (unsigned char *) mac;
1112 }
1113 }
1114
1115 /*
1116 * 3) from flash or fuse (via platform data)
1117 */
1118 if (!is_valid_ether_addr(iap)) {
1119 #ifdef CONFIG_M5272
1120 if (FEC_FLASHMAC)
1121 iap = (unsigned char *)FEC_FLASHMAC;
1122 #else
1123 if (pdata)
1124 iap = (unsigned char *)&pdata->mac;
1125 #endif
1126 }
1127
1128 /*
1129 * 4) FEC mac registers set by bootloader
1130 */
1131 if (!is_valid_ether_addr(iap)) {
1132 *((__be32 *) &tmpaddr[0]) =
1133 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1134 *((__be16 *) &tmpaddr[4]) =
1135 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1136 iap = &tmpaddr[0];
1137 }
1138
1139 /*
1140 * 5) random mac address
1141 */
1142 if (!is_valid_ether_addr(iap)) {
1143 /* Report it and use a random ethernet address instead */
1144 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1145 eth_hw_addr_random(ndev);
1146 netdev_info(ndev, "Using random MAC address: %pM\n",
1147 ndev->dev_addr);
1148 return;
1149 }
1150
1151 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1152
1153 /* Adjust MAC if using macaddr */
1154 if (iap == macaddr)
1155 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1156 }
1157
1158 /* ------------------------------------------------------------------------- */
1159
1160 /*
1161 * Phy section
1162 */
1163 static void fec_enet_adjust_link(struct net_device *ndev)
1164 {
1165 struct fec_enet_private *fep = netdev_priv(ndev);
1166 struct phy_device *phy_dev = fep->phy_dev;
1167 int status_change = 0;
1168
1169 /* Prevent a state halted on mii error */
1170 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1171 phy_dev->state = PHY_RESUMING;
1172 return;
1173 }
1174
1175 if (phy_dev->link) {
1176 if (!fep->link) {
1177 fep->link = phy_dev->link;
1178 status_change = 1;
1179 }
1180
1181 if (fep->full_duplex != phy_dev->duplex)
1182 status_change = 1;
1183
1184 if (phy_dev->speed != fep->speed) {
1185 fep->speed = phy_dev->speed;
1186 status_change = 1;
1187 }
1188
1189 /* if any of the above changed restart the FEC */
1190 if (status_change)
1191 fec_restart(ndev, phy_dev->duplex);
1192 } else {
1193 if (fep->link) {
1194 fec_stop(ndev);
1195 fep->link = phy_dev->link;
1196 status_change = 1;
1197 }
1198 }
1199
1200 if (status_change)
1201 phy_print_status(phy_dev);
1202 }
1203
1204 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1205 {
1206 struct fec_enet_private *fep = bus->priv;
1207 unsigned long time_left;
1208
1209 fep->mii_timeout = 0;
1210 init_completion(&fep->mdio_done);
1211
1212 /* start a read op */
1213 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1214 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1215 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1216
1217 /* wait for end of transfer */
1218 time_left = wait_for_completion_timeout(&fep->mdio_done,
1219 usecs_to_jiffies(FEC_MII_TIMEOUT));
1220 if (time_left == 0) {
1221 fep->mii_timeout = 1;
1222 netdev_err(fep->netdev, "MDIO read timeout\n");
1223 return -ETIMEDOUT;
1224 }
1225
1226 /* return value */
1227 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1228 }
1229
1230 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1231 u16 value)
1232 {
1233 struct fec_enet_private *fep = bus->priv;
1234 unsigned long time_left;
1235
1236 fep->mii_timeout = 0;
1237 init_completion(&fep->mdio_done);
1238
1239 /* start a write op */
1240 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1241 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1242 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1243 fep->hwp + FEC_MII_DATA);
1244
1245 /* wait for end of transfer */
1246 time_left = wait_for_completion_timeout(&fep->mdio_done,
1247 usecs_to_jiffies(FEC_MII_TIMEOUT));
1248 if (time_left == 0) {
1249 fep->mii_timeout = 1;
1250 netdev_err(fep->netdev, "MDIO write timeout\n");
1251 return -ETIMEDOUT;
1252 }
1253
1254 return 0;
1255 }
1256
1257 static int fec_enet_mdio_reset(struct mii_bus *bus)
1258 {
1259 return 0;
1260 }
1261
1262 static int fec_enet_mii_probe(struct net_device *ndev)
1263 {
1264 struct fec_enet_private *fep = netdev_priv(ndev);
1265 const struct platform_device_id *id_entry =
1266 platform_get_device_id(fep->pdev);
1267 struct phy_device *phy_dev = NULL;
1268 char mdio_bus_id[MII_BUS_ID_SIZE];
1269 char phy_name[MII_BUS_ID_SIZE + 3];
1270 int phy_id;
1271 int dev_id = fep->dev_id;
1272
1273 fep->phy_dev = NULL;
1274
1275 /* check for attached phy */
1276 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1277 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1278 continue;
1279 if (fep->mii_bus->phy_map[phy_id] == NULL)
1280 continue;
1281 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1282 continue;
1283 if (dev_id--)
1284 continue;
1285 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1286 break;
1287 }
1288
1289 if (phy_id >= PHY_MAX_ADDR) {
1290 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1291 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1292 phy_id = 0;
1293 }
1294
1295 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1296 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1297 fep->phy_interface);
1298 if (IS_ERR(phy_dev)) {
1299 netdev_err(ndev, "could not attach to PHY\n");
1300 return PTR_ERR(phy_dev);
1301 }
1302
1303 /* mask with MAC supported features */
1304 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1305 phy_dev->supported &= PHY_GBIT_FEATURES;
1306 #if !defined(CONFIG_M5272)
1307 phy_dev->supported |= SUPPORTED_Pause;
1308 #endif
1309 }
1310 else
1311 phy_dev->supported &= PHY_BASIC_FEATURES;
1312
1313 phy_dev->advertising = phy_dev->supported;
1314
1315 fep->phy_dev = phy_dev;
1316 fep->link = 0;
1317 fep->full_duplex = 0;
1318
1319 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1320 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1321 fep->phy_dev->irq);
1322
1323 return 0;
1324 }
1325
1326 static int fec_enet_mii_init(struct platform_device *pdev)
1327 {
1328 static struct mii_bus *fec0_mii_bus;
1329 struct net_device *ndev = platform_get_drvdata(pdev);
1330 struct fec_enet_private *fep = netdev_priv(ndev);
1331 const struct platform_device_id *id_entry =
1332 platform_get_device_id(fep->pdev);
1333 int err = -ENXIO, i;
1334
1335 /*
1336 * The dual fec interfaces are not equivalent with enet-mac.
1337 * Here are the differences:
1338 *
1339 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1340 * - fec0 acts as the 1588 time master while fec1 is slave
1341 * - external phys can only be configured by fec0
1342 *
1343 * That is to say fec1 can not work independently. It only works
1344 * when fec0 is working. The reason behind this design is that the
1345 * second interface is added primarily for Switch mode.
1346 *
1347 * Because of the last point above, both phys are attached on fec0
1348 * mdio interface in board design, and need to be configured by
1349 * fec0 mii_bus.
1350 */
1351 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1352 /* fec1 uses fec0 mii_bus */
1353 if (mii_cnt && fec0_mii_bus) {
1354 fep->mii_bus = fec0_mii_bus;
1355 mii_cnt++;
1356 return 0;
1357 }
1358 return -ENOENT;
1359 }
1360
1361 fep->mii_timeout = 0;
1362
1363 /*
1364 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1365 *
1366 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1367 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1368 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1369 * document.
1370 */
1371 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1372 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1373 fep->phy_speed--;
1374 fep->phy_speed <<= 1;
1375 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1376
1377 fep->mii_bus = mdiobus_alloc();
1378 if (fep->mii_bus == NULL) {
1379 err = -ENOMEM;
1380 goto err_out;
1381 }
1382
1383 fep->mii_bus->name = "fec_enet_mii_bus";
1384 fep->mii_bus->read = fec_enet_mdio_read;
1385 fep->mii_bus->write = fec_enet_mdio_write;
1386 fep->mii_bus->reset = fec_enet_mdio_reset;
1387 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1388 pdev->name, fep->dev_id + 1);
1389 fep->mii_bus->priv = fep;
1390 fep->mii_bus->parent = &pdev->dev;
1391
1392 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1393 if (!fep->mii_bus->irq) {
1394 err = -ENOMEM;
1395 goto err_out_free_mdiobus;
1396 }
1397
1398 for (i = 0; i < PHY_MAX_ADDR; i++)
1399 fep->mii_bus->irq[i] = PHY_POLL;
1400
1401 if (mdiobus_register(fep->mii_bus))
1402 goto err_out_free_mdio_irq;
1403
1404 mii_cnt++;
1405
1406 /* save fec0 mii_bus */
1407 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1408 fec0_mii_bus = fep->mii_bus;
1409
1410 return 0;
1411
1412 err_out_free_mdio_irq:
1413 kfree(fep->mii_bus->irq);
1414 err_out_free_mdiobus:
1415 mdiobus_free(fep->mii_bus);
1416 err_out:
1417 return err;
1418 }
1419
1420 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1421 {
1422 if (--mii_cnt == 0) {
1423 mdiobus_unregister(fep->mii_bus);
1424 kfree(fep->mii_bus->irq);
1425 mdiobus_free(fep->mii_bus);
1426 }
1427 }
1428
1429 static int fec_enet_get_settings(struct net_device *ndev,
1430 struct ethtool_cmd *cmd)
1431 {
1432 struct fec_enet_private *fep = netdev_priv(ndev);
1433 struct phy_device *phydev = fep->phy_dev;
1434
1435 if (!phydev)
1436 return -ENODEV;
1437
1438 return phy_ethtool_gset(phydev, cmd);
1439 }
1440
1441 static int fec_enet_set_settings(struct net_device *ndev,
1442 struct ethtool_cmd *cmd)
1443 {
1444 struct fec_enet_private *fep = netdev_priv(ndev);
1445 struct phy_device *phydev = fep->phy_dev;
1446
1447 if (!phydev)
1448 return -ENODEV;
1449
1450 return phy_ethtool_sset(phydev, cmd);
1451 }
1452
1453 static void fec_enet_get_drvinfo(struct net_device *ndev,
1454 struct ethtool_drvinfo *info)
1455 {
1456 struct fec_enet_private *fep = netdev_priv(ndev);
1457
1458 strlcpy(info->driver, fep->pdev->dev.driver->name,
1459 sizeof(info->driver));
1460 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1461 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1462 }
1463
1464 static int fec_enet_get_ts_info(struct net_device *ndev,
1465 struct ethtool_ts_info *info)
1466 {
1467 struct fec_enet_private *fep = netdev_priv(ndev);
1468
1469 if (fep->bufdesc_ex) {
1470
1471 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1472 SOF_TIMESTAMPING_RX_SOFTWARE |
1473 SOF_TIMESTAMPING_SOFTWARE |
1474 SOF_TIMESTAMPING_TX_HARDWARE |
1475 SOF_TIMESTAMPING_RX_HARDWARE |
1476 SOF_TIMESTAMPING_RAW_HARDWARE;
1477 if (fep->ptp_clock)
1478 info->phc_index = ptp_clock_index(fep->ptp_clock);
1479 else
1480 info->phc_index = -1;
1481
1482 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1483 (1 << HWTSTAMP_TX_ON);
1484
1485 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1486 (1 << HWTSTAMP_FILTER_ALL);
1487 return 0;
1488 } else {
1489 return ethtool_op_get_ts_info(ndev, info);
1490 }
1491 }
1492
1493 #if !defined(CONFIG_M5272)
1494
1495 static void fec_enet_get_pauseparam(struct net_device *ndev,
1496 struct ethtool_pauseparam *pause)
1497 {
1498 struct fec_enet_private *fep = netdev_priv(ndev);
1499
1500 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1501 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1502 pause->rx_pause = pause->tx_pause;
1503 }
1504
1505 static int fec_enet_set_pauseparam(struct net_device *ndev,
1506 struct ethtool_pauseparam *pause)
1507 {
1508 struct fec_enet_private *fep = netdev_priv(ndev);
1509
1510 if (pause->tx_pause != pause->rx_pause) {
1511 netdev_info(ndev,
1512 "hardware only support enable/disable both tx and rx");
1513 return -EINVAL;
1514 }
1515
1516 fep->pause_flag = 0;
1517
1518 /* tx pause must be same as rx pause */
1519 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1520 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1521
1522 if (pause->rx_pause || pause->autoneg) {
1523 fep->phy_dev->supported |= ADVERTISED_Pause;
1524 fep->phy_dev->advertising |= ADVERTISED_Pause;
1525 } else {
1526 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1527 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1528 }
1529
1530 if (pause->autoneg) {
1531 if (netif_running(ndev))
1532 fec_stop(ndev);
1533 phy_start_aneg(fep->phy_dev);
1534 }
1535 if (netif_running(ndev))
1536 fec_restart(ndev, 0);
1537
1538 return 0;
1539 }
1540
1541 static const struct fec_stat {
1542 char name[ETH_GSTRING_LEN];
1543 u16 offset;
1544 } fec_stats[] = {
1545 /* RMON TX */
1546 { "tx_dropped", RMON_T_DROP },
1547 { "tx_packets", RMON_T_PACKETS },
1548 { "tx_broadcast", RMON_T_BC_PKT },
1549 { "tx_multicast", RMON_T_MC_PKT },
1550 { "tx_crc_errors", RMON_T_CRC_ALIGN },
1551 { "tx_undersize", RMON_T_UNDERSIZE },
1552 { "tx_oversize", RMON_T_OVERSIZE },
1553 { "tx_fragment", RMON_T_FRAG },
1554 { "tx_jabber", RMON_T_JAB },
1555 { "tx_collision", RMON_T_COL },
1556 { "tx_64byte", RMON_T_P64 },
1557 { "tx_65to127byte", RMON_T_P65TO127 },
1558 { "tx_128to255byte", RMON_T_P128TO255 },
1559 { "tx_256to511byte", RMON_T_P256TO511 },
1560 { "tx_512to1023byte", RMON_T_P512TO1023 },
1561 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
1562 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
1563 { "tx_octets", RMON_T_OCTETS },
1564
1565 /* IEEE TX */
1566 { "IEEE_tx_drop", IEEE_T_DROP },
1567 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
1568 { "IEEE_tx_1col", IEEE_T_1COL },
1569 { "IEEE_tx_mcol", IEEE_T_MCOL },
1570 { "IEEE_tx_def", IEEE_T_DEF },
1571 { "IEEE_tx_lcol", IEEE_T_LCOL },
1572 { "IEEE_tx_excol", IEEE_T_EXCOL },
1573 { "IEEE_tx_macerr", IEEE_T_MACERR },
1574 { "IEEE_tx_cserr", IEEE_T_CSERR },
1575 { "IEEE_tx_sqe", IEEE_T_SQE },
1576 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
1577 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
1578
1579 /* RMON RX */
1580 { "rx_packets", RMON_R_PACKETS },
1581 { "rx_broadcast", RMON_R_BC_PKT },
1582 { "rx_multicast", RMON_R_MC_PKT },
1583 { "rx_crc_errors", RMON_R_CRC_ALIGN },
1584 { "rx_undersize", RMON_R_UNDERSIZE },
1585 { "rx_oversize", RMON_R_OVERSIZE },
1586 { "rx_fragment", RMON_R_FRAG },
1587 { "rx_jabber", RMON_R_JAB },
1588 { "rx_64byte", RMON_R_P64 },
1589 { "rx_65to127byte", RMON_R_P65TO127 },
1590 { "rx_128to255byte", RMON_R_P128TO255 },
1591 { "rx_256to511byte", RMON_R_P256TO511 },
1592 { "rx_512to1023byte", RMON_R_P512TO1023 },
1593 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
1594 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
1595 { "rx_octets", RMON_R_OCTETS },
1596
1597 /* IEEE RX */
1598 { "IEEE_rx_drop", IEEE_R_DROP },
1599 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
1600 { "IEEE_rx_crc", IEEE_R_CRC },
1601 { "IEEE_rx_align", IEEE_R_ALIGN },
1602 { "IEEE_rx_macerr", IEEE_R_MACERR },
1603 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
1604 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
1605 };
1606
1607 static void fec_enet_get_ethtool_stats(struct net_device *dev,
1608 struct ethtool_stats *stats, u64 *data)
1609 {
1610 struct fec_enet_private *fep = netdev_priv(dev);
1611 int i;
1612
1613 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1614 data[i] = readl(fep->hwp + fec_stats[i].offset);
1615 }
1616
1617 static void fec_enet_get_strings(struct net_device *netdev,
1618 u32 stringset, u8 *data)
1619 {
1620 int i;
1621 switch (stringset) {
1622 case ETH_SS_STATS:
1623 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1624 memcpy(data + i * ETH_GSTRING_LEN,
1625 fec_stats[i].name, ETH_GSTRING_LEN);
1626 break;
1627 }
1628 }
1629
1630 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
1631 {
1632 switch (sset) {
1633 case ETH_SS_STATS:
1634 return ARRAY_SIZE(fec_stats);
1635 default:
1636 return -EOPNOTSUPP;
1637 }
1638 }
1639 #endif /* !defined(CONFIG_M5272) */
1640
1641 static int fec_enet_nway_reset(struct net_device *dev)
1642 {
1643 struct fec_enet_private *fep = netdev_priv(dev);
1644 struct phy_device *phydev = fep->phy_dev;
1645
1646 if (!phydev)
1647 return -ENODEV;
1648
1649 return genphy_restart_aneg(phydev);
1650 }
1651
1652 static const struct ethtool_ops fec_enet_ethtool_ops = {
1653 #if !defined(CONFIG_M5272)
1654 .get_pauseparam = fec_enet_get_pauseparam,
1655 .set_pauseparam = fec_enet_set_pauseparam,
1656 #endif
1657 .get_settings = fec_enet_get_settings,
1658 .set_settings = fec_enet_set_settings,
1659 .get_drvinfo = fec_enet_get_drvinfo,
1660 .get_link = ethtool_op_get_link,
1661 .get_ts_info = fec_enet_get_ts_info,
1662 .nway_reset = fec_enet_nway_reset,
1663 #ifndef CONFIG_M5272
1664 .get_ethtool_stats = fec_enet_get_ethtool_stats,
1665 .get_strings = fec_enet_get_strings,
1666 .get_sset_count = fec_enet_get_sset_count,
1667 #endif
1668 };
1669
1670 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1671 {
1672 struct fec_enet_private *fep = netdev_priv(ndev);
1673 struct phy_device *phydev = fep->phy_dev;
1674
1675 if (!netif_running(ndev))
1676 return -EINVAL;
1677
1678 if (!phydev)
1679 return -ENODEV;
1680
1681 if (fep->bufdesc_ex) {
1682 if (cmd == SIOCSHWTSTAMP)
1683 return fec_ptp_set(ndev, rq);
1684 if (cmd == SIOCGHWTSTAMP)
1685 return fec_ptp_get(ndev, rq);
1686 }
1687
1688 return phy_mii_ioctl(phydev, rq, cmd);
1689 }
1690
1691 static void fec_enet_free_buffers(struct net_device *ndev)
1692 {
1693 struct fec_enet_private *fep = netdev_priv(ndev);
1694 unsigned int i;
1695 struct sk_buff *skb;
1696 struct bufdesc *bdp;
1697
1698 bdp = fep->rx_bd_base;
1699 for (i = 0; i < fep->rx_ring_size; i++) {
1700 skb = fep->rx_skbuff[i];
1701
1702 if (bdp->cbd_bufaddr)
1703 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1704 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1705 if (skb)
1706 dev_kfree_skb(skb);
1707 bdp = fec_enet_get_nextdesc(bdp, fep);
1708 }
1709
1710 bdp = fep->tx_bd_base;
1711 for (i = 0; i < fep->tx_ring_size; i++)
1712 kfree(fep->tx_bounce[i]);
1713 }
1714
1715 static int fec_enet_alloc_buffers(struct net_device *ndev)
1716 {
1717 struct fec_enet_private *fep = netdev_priv(ndev);
1718 unsigned int i;
1719 struct sk_buff *skb;
1720 struct bufdesc *bdp;
1721
1722 bdp = fep->rx_bd_base;
1723 for (i = 0; i < fep->rx_ring_size; i++) {
1724 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1725 if (!skb) {
1726 fec_enet_free_buffers(ndev);
1727 return -ENOMEM;
1728 }
1729 fep->rx_skbuff[i] = skb;
1730
1731 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1732 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1733 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1734 fec_enet_free_buffers(ndev);
1735 if (net_ratelimit())
1736 netdev_err(ndev, "Rx DMA memory map failed\n");
1737 return -ENOMEM;
1738 }
1739 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1740
1741 if (fep->bufdesc_ex) {
1742 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1743 ebdp->cbd_esc = BD_ENET_RX_INT;
1744 }
1745
1746 bdp = fec_enet_get_nextdesc(bdp, fep);
1747 }
1748
1749 /* Set the last buffer to wrap. */
1750 bdp = fec_enet_get_prevdesc(bdp, fep);
1751 bdp->cbd_sc |= BD_SC_WRAP;
1752
1753 bdp = fep->tx_bd_base;
1754 for (i = 0; i < fep->tx_ring_size; i++) {
1755 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1756
1757 bdp->cbd_sc = 0;
1758 bdp->cbd_bufaddr = 0;
1759
1760 if (fep->bufdesc_ex) {
1761 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1762 ebdp->cbd_esc = BD_ENET_TX_INT;
1763 }
1764
1765 bdp = fec_enet_get_nextdesc(bdp, fep);
1766 }
1767
1768 /* Set the last buffer to wrap. */
1769 bdp = fec_enet_get_prevdesc(bdp, fep);
1770 bdp->cbd_sc |= BD_SC_WRAP;
1771
1772 return 0;
1773 }
1774
1775 static int
1776 fec_enet_open(struct net_device *ndev)
1777 {
1778 struct fec_enet_private *fep = netdev_priv(ndev);
1779 int ret;
1780
1781 napi_enable(&fep->napi);
1782
1783 /* I should reset the ring buffers here, but I don't yet know
1784 * a simple way to do that.
1785 */
1786
1787 ret = fec_enet_alloc_buffers(ndev);
1788 if (ret)
1789 return ret;
1790
1791 /* Probe and connect to PHY when open the interface */
1792 ret = fec_enet_mii_probe(ndev);
1793 if (ret) {
1794 fec_enet_free_buffers(ndev);
1795 return ret;
1796 }
1797 phy_start(fep->phy_dev);
1798 netif_start_queue(ndev);
1799 fep->opened = 1;
1800 return 0;
1801 }
1802
1803 static int
1804 fec_enet_close(struct net_device *ndev)
1805 {
1806 struct fec_enet_private *fep = netdev_priv(ndev);
1807
1808 /* Don't know what to do yet. */
1809 napi_disable(&fep->napi);
1810 fep->opened = 0;
1811 netif_stop_queue(ndev);
1812 fec_stop(ndev);
1813
1814 if (fep->phy_dev) {
1815 phy_stop(fep->phy_dev);
1816 phy_disconnect(fep->phy_dev);
1817 }
1818
1819 fec_enet_free_buffers(ndev);
1820
1821 return 0;
1822 }
1823
1824 /* Set or clear the multicast filter for this adaptor.
1825 * Skeleton taken from sunlance driver.
1826 * The CPM Ethernet implementation allows Multicast as well as individual
1827 * MAC address filtering. Some of the drivers check to make sure it is
1828 * a group multicast address, and discard those that are not. I guess I
1829 * will do the same for now, but just remove the test if you want
1830 * individual filtering as well (do the upper net layers want or support
1831 * this kind of feature?).
1832 */
1833
1834 #define HASH_BITS 6 /* #bits in hash */
1835 #define CRC32_POLY 0xEDB88320
1836
1837 static void set_multicast_list(struct net_device *ndev)
1838 {
1839 struct fec_enet_private *fep = netdev_priv(ndev);
1840 struct netdev_hw_addr *ha;
1841 unsigned int i, bit, data, crc, tmp;
1842 unsigned char hash;
1843
1844 if (ndev->flags & IFF_PROMISC) {
1845 tmp = readl(fep->hwp + FEC_R_CNTRL);
1846 tmp |= 0x8;
1847 writel(tmp, fep->hwp + FEC_R_CNTRL);
1848 return;
1849 }
1850
1851 tmp = readl(fep->hwp + FEC_R_CNTRL);
1852 tmp &= ~0x8;
1853 writel(tmp, fep->hwp + FEC_R_CNTRL);
1854
1855 if (ndev->flags & IFF_ALLMULTI) {
1856 /* Catch all multicast addresses, so set the
1857 * filter to all 1's
1858 */
1859 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1860 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1861
1862 return;
1863 }
1864
1865 /* Clear filter and add the addresses in hash register
1866 */
1867 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1868 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1869
1870 netdev_for_each_mc_addr(ha, ndev) {
1871 /* calculate crc32 value of mac address */
1872 crc = 0xffffffff;
1873
1874 for (i = 0; i < ndev->addr_len; i++) {
1875 data = ha->addr[i];
1876 for (bit = 0; bit < 8; bit++, data >>= 1) {
1877 crc = (crc >> 1) ^
1878 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1879 }
1880 }
1881
1882 /* only upper 6 bits (HASH_BITS) are used
1883 * which point to specific bit in he hash registers
1884 */
1885 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1886
1887 if (hash > 31) {
1888 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1889 tmp |= 1 << (hash - 32);
1890 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1891 } else {
1892 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1893 tmp |= 1 << hash;
1894 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1895 }
1896 }
1897 }
1898
1899 /* Set a MAC change in hardware. */
1900 static int
1901 fec_set_mac_address(struct net_device *ndev, void *p)
1902 {
1903 struct fec_enet_private *fep = netdev_priv(ndev);
1904 struct sockaddr *addr = p;
1905
1906 if (!is_valid_ether_addr(addr->sa_data))
1907 return -EADDRNOTAVAIL;
1908
1909 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1910
1911 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1912 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1913 fep->hwp + FEC_ADDR_LOW);
1914 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1915 fep->hwp + FEC_ADDR_HIGH);
1916 return 0;
1917 }
1918
1919 #ifdef CONFIG_NET_POLL_CONTROLLER
1920 /**
1921 * fec_poll_controller - FEC Poll controller function
1922 * @dev: The FEC network adapter
1923 *
1924 * Polled functionality used by netconsole and others in non interrupt mode
1925 *
1926 */
1927 static void fec_poll_controller(struct net_device *dev)
1928 {
1929 int i;
1930 struct fec_enet_private *fep = netdev_priv(dev);
1931
1932 for (i = 0; i < FEC_IRQ_NUM; i++) {
1933 if (fep->irq[i] > 0) {
1934 disable_irq(fep->irq[i]);
1935 fec_enet_interrupt(fep->irq[i], dev);
1936 enable_irq(fep->irq[i]);
1937 }
1938 }
1939 }
1940 #endif
1941
1942 static int fec_set_features(struct net_device *netdev,
1943 netdev_features_t features)
1944 {
1945 struct fec_enet_private *fep = netdev_priv(netdev);
1946 netdev_features_t changed = features ^ netdev->features;
1947
1948 netdev->features = features;
1949
1950 /* Receive checksum has been changed */
1951 if (changed & NETIF_F_RXCSUM) {
1952 if (features & NETIF_F_RXCSUM)
1953 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
1954 else
1955 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
1956
1957 if (netif_running(netdev)) {
1958 fec_stop(netdev);
1959 fec_restart(netdev, fep->phy_dev->duplex);
1960 netif_wake_queue(netdev);
1961 } else {
1962 fec_restart(netdev, fep->phy_dev->duplex);
1963 }
1964 }
1965
1966 return 0;
1967 }
1968
1969 static const struct net_device_ops fec_netdev_ops = {
1970 .ndo_open = fec_enet_open,
1971 .ndo_stop = fec_enet_close,
1972 .ndo_start_xmit = fec_enet_start_xmit,
1973 .ndo_set_rx_mode = set_multicast_list,
1974 .ndo_change_mtu = eth_change_mtu,
1975 .ndo_validate_addr = eth_validate_addr,
1976 .ndo_tx_timeout = fec_timeout,
1977 .ndo_set_mac_address = fec_set_mac_address,
1978 .ndo_do_ioctl = fec_enet_ioctl,
1979 #ifdef CONFIG_NET_POLL_CONTROLLER
1980 .ndo_poll_controller = fec_poll_controller,
1981 #endif
1982 .ndo_set_features = fec_set_features,
1983 };
1984
1985 /*
1986 * XXX: We need to clean up on failure exits here.
1987 *
1988 */
1989 static int fec_enet_init(struct net_device *ndev)
1990 {
1991 struct fec_enet_private *fep = netdev_priv(ndev);
1992 const struct platform_device_id *id_entry =
1993 platform_get_device_id(fep->pdev);
1994 struct bufdesc *cbd_base;
1995
1996 /* Allocate memory for buffer descriptors. */
1997 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1998 GFP_KERNEL);
1999 if (!cbd_base)
2000 return -ENOMEM;
2001
2002 memset(cbd_base, 0, PAGE_SIZE);
2003
2004 fep->netdev = ndev;
2005
2006 /* Get the Ethernet address */
2007 fec_get_mac(ndev);
2008
2009 /* init the tx & rx ring size */
2010 fep->tx_ring_size = TX_RING_SIZE;
2011 fep->rx_ring_size = RX_RING_SIZE;
2012
2013 /* Set receive and transmit descriptor base. */
2014 fep->rx_bd_base = cbd_base;
2015 if (fep->bufdesc_ex)
2016 fep->tx_bd_base = (struct bufdesc *)
2017 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size);
2018 else
2019 fep->tx_bd_base = cbd_base + fep->rx_ring_size;
2020
2021 /* The FEC Ethernet specific entries in the device structure */
2022 ndev->watchdog_timeo = TX_TIMEOUT;
2023 ndev->netdev_ops = &fec_netdev_ops;
2024 ndev->ethtool_ops = &fec_enet_ethtool_ops;
2025
2026 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
2027 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
2028
2029 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) {
2030 /* enable hw VLAN support */
2031 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2032 ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2033 }
2034
2035 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
2036 /* enable hw accelerator */
2037 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2038 | NETIF_F_RXCSUM);
2039 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2040 | NETIF_F_RXCSUM);
2041 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2042 }
2043
2044 fec_restart(ndev, 0);
2045
2046 return 0;
2047 }
2048
2049 #ifdef CONFIG_OF
2050 static void fec_reset_phy(struct platform_device *pdev)
2051 {
2052 int err, phy_reset;
2053 int msec = 1;
2054 struct device_node *np = pdev->dev.of_node;
2055
2056 if (!np)
2057 return;
2058
2059 of_property_read_u32(np, "phy-reset-duration", &msec);
2060 /* A sane reset duration should not be longer than 1s */
2061 if (msec > 1000)
2062 msec = 1;
2063
2064 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
2065 if (!gpio_is_valid(phy_reset))
2066 return;
2067
2068 err = devm_gpio_request_one(&pdev->dev, phy_reset,
2069 GPIOF_OUT_INIT_LOW, "phy-reset");
2070 if (err) {
2071 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
2072 return;
2073 }
2074 msleep(msec);
2075 gpio_set_value(phy_reset, 1);
2076 }
2077 #else /* CONFIG_OF */
2078 static void fec_reset_phy(struct platform_device *pdev)
2079 {
2080 /*
2081 * In case of platform probe, the reset has been done
2082 * by machine code.
2083 */
2084 }
2085 #endif /* CONFIG_OF */
2086
2087 static int
2088 fec_probe(struct platform_device *pdev)
2089 {
2090 struct fec_enet_private *fep;
2091 struct fec_platform_data *pdata;
2092 struct net_device *ndev;
2093 int i, irq, ret = 0;
2094 struct resource *r;
2095 const struct of_device_id *of_id;
2096 static int dev_id;
2097
2098 of_id = of_match_device(fec_dt_ids, &pdev->dev);
2099 if (of_id)
2100 pdev->id_entry = of_id->data;
2101
2102 /* Init network device */
2103 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
2104 if (!ndev)
2105 return -ENOMEM;
2106
2107 SET_NETDEV_DEV(ndev, &pdev->dev);
2108
2109 /* setup board info structure */
2110 fep = netdev_priv(ndev);
2111
2112 #if !defined(CONFIG_M5272)
2113 /* default enable pause frame auto negotiation */
2114 if (pdev->id_entry &&
2115 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
2116 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
2117 #endif
2118
2119 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2120 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
2121 if (IS_ERR(fep->hwp)) {
2122 ret = PTR_ERR(fep->hwp);
2123 goto failed_ioremap;
2124 }
2125
2126 fep->pdev = pdev;
2127 fep->dev_id = dev_id++;
2128
2129 fep->bufdesc_ex = 0;
2130
2131 platform_set_drvdata(pdev, ndev);
2132
2133 ret = of_get_phy_mode(pdev->dev.of_node);
2134 if (ret < 0) {
2135 pdata = dev_get_platdata(&pdev->dev);
2136 if (pdata)
2137 fep->phy_interface = pdata->phy;
2138 else
2139 fep->phy_interface = PHY_INTERFACE_MODE_MII;
2140 } else {
2141 fep->phy_interface = ret;
2142 }
2143
2144 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2145 if (IS_ERR(fep->clk_ipg)) {
2146 ret = PTR_ERR(fep->clk_ipg);
2147 goto failed_clk;
2148 }
2149
2150 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2151 if (IS_ERR(fep->clk_ahb)) {
2152 ret = PTR_ERR(fep->clk_ahb);
2153 goto failed_clk;
2154 }
2155
2156 /* enet_out is optional, depends on board */
2157 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
2158 if (IS_ERR(fep->clk_enet_out))
2159 fep->clk_enet_out = NULL;
2160
2161 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
2162 fep->bufdesc_ex =
2163 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
2164 if (IS_ERR(fep->clk_ptp)) {
2165 fep->clk_ptp = NULL;
2166 fep->bufdesc_ex = 0;
2167 }
2168
2169 ret = clk_prepare_enable(fep->clk_ahb);
2170 if (ret)
2171 goto failed_clk;
2172
2173 ret = clk_prepare_enable(fep->clk_ipg);
2174 if (ret)
2175 goto failed_clk_ipg;
2176
2177 if (fep->clk_enet_out) {
2178 ret = clk_prepare_enable(fep->clk_enet_out);
2179 if (ret)
2180 goto failed_clk_enet_out;
2181 }
2182
2183 if (fep->clk_ptp) {
2184 ret = clk_prepare_enable(fep->clk_ptp);
2185 if (ret)
2186 goto failed_clk_ptp;
2187 }
2188
2189 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
2190 if (!IS_ERR(fep->reg_phy)) {
2191 ret = regulator_enable(fep->reg_phy);
2192 if (ret) {
2193 dev_err(&pdev->dev,
2194 "Failed to enable phy regulator: %d\n", ret);
2195 goto failed_regulator;
2196 }
2197 } else {
2198 fep->reg_phy = NULL;
2199 }
2200
2201 fec_reset_phy(pdev);
2202
2203 if (fep->bufdesc_ex)
2204 fec_ptp_init(pdev);
2205
2206 ret = fec_enet_init(ndev);
2207 if (ret)
2208 goto failed_init;
2209
2210 for (i = 0; i < FEC_IRQ_NUM; i++) {
2211 irq = platform_get_irq(pdev, i);
2212 if (irq < 0) {
2213 if (i)
2214 break;
2215 ret = irq;
2216 goto failed_irq;
2217 }
2218 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
2219 0, pdev->name, ndev);
2220 if (ret)
2221 goto failed_irq;
2222 }
2223
2224 ret = fec_enet_mii_init(pdev);
2225 if (ret)
2226 goto failed_mii_init;
2227
2228 /* Carrier starts down, phylib will bring it up */
2229 netif_carrier_off(ndev);
2230
2231 ret = register_netdev(ndev);
2232 if (ret)
2233 goto failed_register;
2234
2235 if (fep->bufdesc_ex && fep->ptp_clock)
2236 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
2237
2238 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
2239 return 0;
2240
2241 failed_register:
2242 fec_enet_mii_remove(fep);
2243 failed_mii_init:
2244 failed_irq:
2245 failed_init:
2246 if (fep->reg_phy)
2247 regulator_disable(fep->reg_phy);
2248 failed_regulator:
2249 if (fep->clk_ptp)
2250 clk_disable_unprepare(fep->clk_ptp);
2251 failed_clk_ptp:
2252 if (fep->clk_enet_out)
2253 clk_disable_unprepare(fep->clk_enet_out);
2254 failed_clk_enet_out:
2255 clk_disable_unprepare(fep->clk_ipg);
2256 failed_clk_ipg:
2257 clk_disable_unprepare(fep->clk_ahb);
2258 failed_clk:
2259 failed_ioremap:
2260 free_netdev(ndev);
2261
2262 return ret;
2263 }
2264
2265 static int
2266 fec_drv_remove(struct platform_device *pdev)
2267 {
2268 struct net_device *ndev = platform_get_drvdata(pdev);
2269 struct fec_enet_private *fep = netdev_priv(ndev);
2270
2271 cancel_delayed_work_sync(&(fep->delay_work.delay_work));
2272 unregister_netdev(ndev);
2273 fec_enet_mii_remove(fep);
2274 del_timer_sync(&fep->time_keep);
2275 if (fep->reg_phy)
2276 regulator_disable(fep->reg_phy);
2277 if (fep->clk_ptp)
2278 clk_disable_unprepare(fep->clk_ptp);
2279 if (fep->ptp_clock)
2280 ptp_clock_unregister(fep->ptp_clock);
2281 if (fep->clk_enet_out)
2282 clk_disable_unprepare(fep->clk_enet_out);
2283 clk_disable_unprepare(fep->clk_ipg);
2284 clk_disable_unprepare(fep->clk_ahb);
2285 free_netdev(ndev);
2286
2287 return 0;
2288 }
2289
2290 #ifdef CONFIG_PM_SLEEP
2291 static int
2292 fec_suspend(struct device *dev)
2293 {
2294 struct net_device *ndev = dev_get_drvdata(dev);
2295 struct fec_enet_private *fep = netdev_priv(ndev);
2296
2297 if (netif_running(ndev)) {
2298 fec_stop(ndev);
2299 netif_device_detach(ndev);
2300 }
2301 if (fep->clk_ptp)
2302 clk_disable_unprepare(fep->clk_ptp);
2303 if (fep->clk_enet_out)
2304 clk_disable_unprepare(fep->clk_enet_out);
2305 clk_disable_unprepare(fep->clk_ipg);
2306 clk_disable_unprepare(fep->clk_ahb);
2307
2308 if (fep->reg_phy)
2309 regulator_disable(fep->reg_phy);
2310
2311 return 0;
2312 }
2313
2314 static int
2315 fec_resume(struct device *dev)
2316 {
2317 struct net_device *ndev = dev_get_drvdata(dev);
2318 struct fec_enet_private *fep = netdev_priv(ndev);
2319 int ret;
2320
2321 if (fep->reg_phy) {
2322 ret = regulator_enable(fep->reg_phy);
2323 if (ret)
2324 return ret;
2325 }
2326
2327 ret = clk_prepare_enable(fep->clk_ahb);
2328 if (ret)
2329 goto failed_clk_ahb;
2330
2331 ret = clk_prepare_enable(fep->clk_ipg);
2332 if (ret)
2333 goto failed_clk_ipg;
2334
2335 if (fep->clk_enet_out) {
2336 ret = clk_prepare_enable(fep->clk_enet_out);
2337 if (ret)
2338 goto failed_clk_enet_out;
2339 }
2340
2341 if (fep->clk_ptp) {
2342 ret = clk_prepare_enable(fep->clk_ptp);
2343 if (ret)
2344 goto failed_clk_ptp;
2345 }
2346
2347 if (netif_running(ndev)) {
2348 fec_restart(ndev, fep->full_duplex);
2349 netif_device_attach(ndev);
2350 }
2351
2352 return 0;
2353
2354 failed_clk_ptp:
2355 if (fep->clk_enet_out)
2356 clk_disable_unprepare(fep->clk_enet_out);
2357 failed_clk_enet_out:
2358 clk_disable_unprepare(fep->clk_ipg);
2359 failed_clk_ipg:
2360 clk_disable_unprepare(fep->clk_ahb);
2361 failed_clk_ahb:
2362 if (fep->reg_phy)
2363 regulator_disable(fep->reg_phy);
2364 return ret;
2365 }
2366 #endif /* CONFIG_PM_SLEEP */
2367
2368 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
2369
2370 static struct platform_driver fec_driver = {
2371 .driver = {
2372 .name = DRIVER_NAME,
2373 .owner = THIS_MODULE,
2374 .pm = &fec_pm_ops,
2375 .of_match_table = fec_dt_ids,
2376 },
2377 .id_table = fec_devtype,
2378 .probe = fec_probe,
2379 .remove = fec_drv_remove,
2380 };
2381
2382 module_platform_driver(fec_driver);
2383
2384 MODULE_ALIAS("platform:"DRIVER_NAME);
2385 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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