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fec: Convert printks to netdev_<level>
[deliverable/linux.git] / drivers / net / ethernet / freescale / fec_main.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/spinlock.h>
38 #include <linux/workqueue.h>
39 #include <linux/bitops.h>
40 #include <linux/io.h>
41 #include <linux/irq.h>
42 #include <linux/clk.h>
43 #include <linux/platform_device.h>
44 #include <linux/phy.h>
45 #include <linux/fec.h>
46 #include <linux/of.h>
47 #include <linux/of_device.h>
48 #include <linux/of_gpio.h>
49 #include <linux/of_net.h>
50 #include <linux/pinctrl/consumer.h>
51 #include <linux/regulator/consumer.h>
52
53 #include <asm/cacheflush.h>
54
55 #ifndef CONFIG_ARM
56 #include <asm/coldfire.h>
57 #include <asm/mcfsim.h>
58 #endif
59
60 #include "fec.h"
61
62 #if defined(CONFIG_ARM)
63 #define FEC_ALIGNMENT 0xf
64 #else
65 #define FEC_ALIGNMENT 0x3
66 #endif
67
68 #define DRIVER_NAME "fec"
69 #define FEC_NAPI_WEIGHT 64
70
71 /* Pause frame feild and FIFO threshold */
72 #define FEC_ENET_FCE (1 << 5)
73 #define FEC_ENET_RSEM_V 0x84
74 #define FEC_ENET_RSFL_V 16
75 #define FEC_ENET_RAEM_V 0x8
76 #define FEC_ENET_RAFL_V 0x8
77 #define FEC_ENET_OPD_V 0xFFF0
78
79 /* Controller is ENET-MAC */
80 #define FEC_QUIRK_ENET_MAC (1 << 0)
81 /* Controller needs driver to swap frame */
82 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
83 /* Controller uses gasket */
84 #define FEC_QUIRK_USE_GASKET (1 << 2)
85 /* Controller has GBIT support */
86 #define FEC_QUIRK_HAS_GBIT (1 << 3)
87 /* Controller has extend desc buffer */
88 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
89
90 static struct platform_device_id fec_devtype[] = {
91 {
92 /* keep it for coldfire */
93 .name = DRIVER_NAME,
94 .driver_data = 0,
95 }, {
96 .name = "imx25-fec",
97 .driver_data = FEC_QUIRK_USE_GASKET,
98 }, {
99 .name = "imx27-fec",
100 .driver_data = 0,
101 }, {
102 .name = "imx28-fec",
103 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
104 }, {
105 .name = "imx6q-fec",
106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
107 FEC_QUIRK_HAS_BUFDESC_EX,
108 }, {
109 .name = "mvf-fec",
110 .driver_data = FEC_QUIRK_ENET_MAC,
111 }, {
112 /* sentinel */
113 }
114 };
115 MODULE_DEVICE_TABLE(platform, fec_devtype);
116
117 enum imx_fec_type {
118 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
119 IMX27_FEC, /* runs on i.mx27/35/51 */
120 IMX28_FEC,
121 IMX6Q_FEC,
122 MVF_FEC,
123 };
124
125 static const struct of_device_id fec_dt_ids[] = {
126 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
127 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
128 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
129 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
130 { .compatible = "fsl,mvf-fec", .data = &fec_devtype[MVF_FEC], },
131 { /* sentinel */ }
132 };
133 MODULE_DEVICE_TABLE(of, fec_dt_ids);
134
135 static unsigned char macaddr[ETH_ALEN];
136 module_param_array(macaddr, byte, NULL, 0);
137 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
138
139 #if defined(CONFIG_M5272)
140 /*
141 * Some hardware gets it MAC address out of local flash memory.
142 * if this is non-zero then assume it is the address to get MAC from.
143 */
144 #if defined(CONFIG_NETtel)
145 #define FEC_FLASHMAC 0xf0006006
146 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
147 #define FEC_FLASHMAC 0xf0006000
148 #elif defined(CONFIG_CANCam)
149 #define FEC_FLASHMAC 0xf0020000
150 #elif defined (CONFIG_M5272C3)
151 #define FEC_FLASHMAC (0xffe04000 + 4)
152 #elif defined(CONFIG_MOD5272)
153 #define FEC_FLASHMAC 0xffc0406b
154 #else
155 #define FEC_FLASHMAC 0
156 #endif
157 #endif /* CONFIG_M5272 */
158
159 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
160 #error "FEC: descriptor ring size constants too large"
161 #endif
162
163 /* Interrupt events/masks. */
164 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
165 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
166 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
167 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
168 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
169 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
170 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
171 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
172 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
173 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
174
175 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
176 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
177
178 /* The FEC stores dest/src/type, data, and checksum for receive packets.
179 */
180 #define PKT_MAXBUF_SIZE 1518
181 #define PKT_MINBUF_SIZE 64
182 #define PKT_MAXBLR_SIZE 1520
183
184 /*
185 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
186 * size bits. Other FEC hardware does not, so we need to take that into
187 * account when setting it.
188 */
189 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
190 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
191 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
192 #else
193 #define OPT_FRAME_SIZE 0
194 #endif
195
196 /* FEC MII MMFR bits definition */
197 #define FEC_MMFR_ST (1 << 30)
198 #define FEC_MMFR_OP_READ (2 << 28)
199 #define FEC_MMFR_OP_WRITE (1 << 28)
200 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
201 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
202 #define FEC_MMFR_TA (2 << 16)
203 #define FEC_MMFR_DATA(v) (v & 0xffff)
204
205 #define FEC_MII_TIMEOUT 30000 /* us */
206
207 /* Transmitter timeout */
208 #define TX_TIMEOUT (2 * HZ)
209
210 #define FEC_PAUSE_FLAG_AUTONEG 0x1
211 #define FEC_PAUSE_FLAG_ENABLE 0x2
212
213 static int mii_cnt;
214
215 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
216 {
217 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
218 if (is_ex)
219 return (struct bufdesc *)(ex + 1);
220 else
221 return bdp + 1;
222 }
223
224 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex)
225 {
226 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
227 if (is_ex)
228 return (struct bufdesc *)(ex - 1);
229 else
230 return bdp - 1;
231 }
232
233 static void *swap_buffer(void *bufaddr, int len)
234 {
235 int i;
236 unsigned int *buf = bufaddr;
237
238 for (i = 0; i < (len + 3) / 4; i++, buf++)
239 *buf = cpu_to_be32(*buf);
240
241 return bufaddr;
242 }
243
244 static netdev_tx_t
245 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
246 {
247 struct fec_enet_private *fep = netdev_priv(ndev);
248 const struct platform_device_id *id_entry =
249 platform_get_device_id(fep->pdev);
250 struct bufdesc *bdp;
251 void *bufaddr;
252 unsigned short status;
253 unsigned int index;
254
255 if (!fep->link) {
256 /* Link is down or autonegotiation is in progress. */
257 return NETDEV_TX_BUSY;
258 }
259
260 /* Fill in a Tx ring entry */
261 bdp = fep->cur_tx;
262
263 status = bdp->cbd_sc;
264
265 if (status & BD_ENET_TX_READY) {
266 /* Ooops. All transmit buffers are full. Bail out.
267 * This should not happen, since ndev->tbusy should be set.
268 */
269 netdev_err(ndev, "tx queue full!\n");
270 return NETDEV_TX_BUSY;
271 }
272
273 /* Clear all of the status flags */
274 status &= ~BD_ENET_TX_STATS;
275
276 /* Set buffer length and buffer pointer */
277 bufaddr = skb->data;
278 bdp->cbd_datlen = skb->len;
279
280 /*
281 * On some FEC implementations data must be aligned on
282 * 4-byte boundaries. Use bounce buffers to copy data
283 * and get it aligned. Ugh.
284 */
285 if (fep->bufdesc_ex)
286 index = (struct bufdesc_ex *)bdp -
287 (struct bufdesc_ex *)fep->tx_bd_base;
288 else
289 index = bdp - fep->tx_bd_base;
290
291 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
292 memcpy(fep->tx_bounce[index], skb->data, skb->len);
293 bufaddr = fep->tx_bounce[index];
294 }
295
296 /*
297 * Some design made an incorrect assumption on endian mode of
298 * the system that it's running on. As the result, driver has to
299 * swap every frame going to and coming from the controller.
300 */
301 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
302 swap_buffer(bufaddr, skb->len);
303
304 /* Save skb pointer */
305 fep->tx_skbuff[index] = skb;
306
307 /* Push the data cache so the CPM does not get stale memory
308 * data.
309 */
310 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
311 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
312
313 /* Send it on its way. Tell FEC it's ready, interrupt when done,
314 * it's the last BD of the frame, and to put the CRC on the end.
315 */
316 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
317 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
318 bdp->cbd_sc = status;
319
320 if (fep->bufdesc_ex) {
321
322 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
323 ebdp->cbd_bdu = 0;
324 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
325 fep->hwts_tx_en)) {
326 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
327 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
328 } else {
329
330 ebdp->cbd_esc = BD_ENET_TX_INT;
331 }
332 }
333 /* If this was the last BD in the ring, start at the beginning again. */
334 if (status & BD_ENET_TX_WRAP)
335 bdp = fep->tx_bd_base;
336 else
337 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
338
339 fep->cur_tx = bdp;
340
341 if (fep->cur_tx == fep->dirty_tx)
342 netif_stop_queue(ndev);
343
344 /* Trigger transmission start */
345 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
346
347 skb_tx_timestamp(skb);
348
349 return NETDEV_TX_OK;
350 }
351
352 /* Init RX & TX buffer descriptors
353 */
354 static void fec_enet_bd_init(struct net_device *dev)
355 {
356 struct fec_enet_private *fep = netdev_priv(dev);
357 struct bufdesc *bdp;
358 unsigned int i;
359
360 /* Initialize the receive buffer descriptors. */
361 bdp = fep->rx_bd_base;
362 for (i = 0; i < RX_RING_SIZE; i++) {
363
364 /* Initialize the BD for every fragment in the page. */
365 if (bdp->cbd_bufaddr)
366 bdp->cbd_sc = BD_ENET_RX_EMPTY;
367 else
368 bdp->cbd_sc = 0;
369 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
370 }
371
372 /* Set the last buffer to wrap */
373 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
374 bdp->cbd_sc |= BD_SC_WRAP;
375
376 fep->cur_rx = fep->rx_bd_base;
377
378 /* ...and the same for transmit */
379 bdp = fep->tx_bd_base;
380 fep->cur_tx = bdp;
381 for (i = 0; i < TX_RING_SIZE; i++) {
382
383 /* Initialize the BD for every fragment in the page. */
384 bdp->cbd_sc = 0;
385 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
386 dev_kfree_skb_any(fep->tx_skbuff[i]);
387 fep->tx_skbuff[i] = NULL;
388 }
389 bdp->cbd_bufaddr = 0;
390 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
391 }
392
393 /* Set the last buffer to wrap */
394 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
395 bdp->cbd_sc |= BD_SC_WRAP;
396 fep->dirty_tx = bdp;
397 }
398
399 /* This function is called to start or restart the FEC during a link
400 * change. This only happens when switching between half and full
401 * duplex.
402 */
403 static void
404 fec_restart(struct net_device *ndev, int duplex)
405 {
406 struct fec_enet_private *fep = netdev_priv(ndev);
407 const struct platform_device_id *id_entry =
408 platform_get_device_id(fep->pdev);
409 int i;
410 u32 temp_mac[2];
411 u32 rcntl = OPT_FRAME_SIZE | 0x04;
412 u32 ecntl = 0x2; /* ETHEREN */
413
414 /* Whack a reset. We should wait for this. */
415 writel(1, fep->hwp + FEC_ECNTRL);
416 udelay(10);
417
418 /*
419 * enet-mac reset will reset mac address registers too,
420 * so need to reconfigure it.
421 */
422 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
423 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
424 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
425 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
426 }
427
428 /* Clear any outstanding interrupt. */
429 writel(0xffc00000, fep->hwp + FEC_IEVENT);
430
431 /* Reset all multicast. */
432 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
433 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
434 #ifndef CONFIG_M5272
435 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
436 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
437 #endif
438
439 /* Set maximum receive buffer size. */
440 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
441
442 fec_enet_bd_init(ndev);
443
444 /* Set receive and transmit descriptor base. */
445 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
446 if (fep->bufdesc_ex)
447 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
448 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
449 else
450 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
451 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
452
453
454 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
455 if (fep->tx_skbuff[i]) {
456 dev_kfree_skb_any(fep->tx_skbuff[i]);
457 fep->tx_skbuff[i] = NULL;
458 }
459 }
460
461 /* Enable MII mode */
462 if (duplex) {
463 /* FD enable */
464 writel(0x04, fep->hwp + FEC_X_CNTRL);
465 } else {
466 /* No Rcv on Xmit */
467 rcntl |= 0x02;
468 writel(0x0, fep->hwp + FEC_X_CNTRL);
469 }
470
471 fep->full_duplex = duplex;
472
473 /* Set MII speed */
474 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
475
476 /*
477 * The phy interface and speed need to get configured
478 * differently on enet-mac.
479 */
480 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
481 /* Enable flow control and length check */
482 rcntl |= 0x40000000 | 0x00000020;
483
484 /* RGMII, RMII or MII */
485 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
486 rcntl |= (1 << 6);
487 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
488 rcntl |= (1 << 8);
489 else
490 rcntl &= ~(1 << 8);
491
492 /* 1G, 100M or 10M */
493 if (fep->phy_dev) {
494 if (fep->phy_dev->speed == SPEED_1000)
495 ecntl |= (1 << 5);
496 else if (fep->phy_dev->speed == SPEED_100)
497 rcntl &= ~(1 << 9);
498 else
499 rcntl |= (1 << 9);
500 }
501 } else {
502 #ifdef FEC_MIIGSK_ENR
503 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
504 u32 cfgr;
505 /* disable the gasket and wait */
506 writel(0, fep->hwp + FEC_MIIGSK_ENR);
507 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
508 udelay(1);
509
510 /*
511 * configure the gasket:
512 * RMII, 50 MHz, no loopback, no echo
513 * MII, 25 MHz, no loopback, no echo
514 */
515 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
516 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
517 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
518 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
519 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
520
521 /* re-enable the gasket */
522 writel(2, fep->hwp + FEC_MIIGSK_ENR);
523 }
524 #endif
525 }
526
527 /* enable pause frame*/
528 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
529 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
530 fep->phy_dev && fep->phy_dev->pause)) {
531 rcntl |= FEC_ENET_FCE;
532
533 /* set FIFO thresh hold parameter to reduce overrun */
534 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
535 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
536 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
537 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
538
539 /* OPD */
540 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
541 } else {
542 rcntl &= ~FEC_ENET_FCE;
543 }
544
545 writel(rcntl, fep->hwp + FEC_R_CNTRL);
546
547 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
548 /* enable ENET endian swap */
549 ecntl |= (1 << 8);
550 /* enable ENET store and forward mode */
551 writel(1 << 8, fep->hwp + FEC_X_WMRK);
552 }
553
554 if (fep->bufdesc_ex)
555 ecntl |= (1 << 4);
556
557 /* And last, enable the transmit and receive processing */
558 writel(ecntl, fep->hwp + FEC_ECNTRL);
559 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
560
561 if (fep->bufdesc_ex)
562 fec_ptp_start_cyclecounter(ndev);
563
564 /* Enable interrupts we wish to service */
565 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
566 }
567
568 static void
569 fec_stop(struct net_device *ndev)
570 {
571 struct fec_enet_private *fep = netdev_priv(ndev);
572 const struct platform_device_id *id_entry =
573 platform_get_device_id(fep->pdev);
574 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
575
576 /* We cannot expect a graceful transmit stop without link !!! */
577 if (fep->link) {
578 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
579 udelay(10);
580 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
581 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
582 }
583
584 /* Whack a reset. We should wait for this. */
585 writel(1, fep->hwp + FEC_ECNTRL);
586 udelay(10);
587 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
588 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
589
590 /* We have to keep ENET enabled to have MII interrupt stay working */
591 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
592 writel(2, fep->hwp + FEC_ECNTRL);
593 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
594 }
595 }
596
597
598 static void
599 fec_timeout(struct net_device *ndev)
600 {
601 struct fec_enet_private *fep = netdev_priv(ndev);
602
603 ndev->stats.tx_errors++;
604
605 fec_restart(ndev, fep->full_duplex);
606 netif_wake_queue(ndev);
607 }
608
609 static void
610 fec_enet_tx(struct net_device *ndev)
611 {
612 struct fec_enet_private *fep;
613 struct bufdesc *bdp;
614 unsigned short status;
615 struct sk_buff *skb;
616 int index = 0;
617
618 fep = netdev_priv(ndev);
619 bdp = fep->dirty_tx;
620
621 /* get next bdp of dirty_tx */
622 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
623 bdp = fep->tx_bd_base;
624 else
625 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
626
627 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
628
629 /* current queue is empty */
630 if (bdp == fep->cur_tx)
631 break;
632
633 if (fep->bufdesc_ex)
634 index = (struct bufdesc_ex *)bdp -
635 (struct bufdesc_ex *)fep->tx_bd_base;
636 else
637 index = bdp - fep->tx_bd_base;
638
639 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
640 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
641 bdp->cbd_bufaddr = 0;
642
643 skb = fep->tx_skbuff[index];
644
645 /* Check for errors. */
646 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
647 BD_ENET_TX_RL | BD_ENET_TX_UN |
648 BD_ENET_TX_CSL)) {
649 ndev->stats.tx_errors++;
650 if (status & BD_ENET_TX_HB) /* No heartbeat */
651 ndev->stats.tx_heartbeat_errors++;
652 if (status & BD_ENET_TX_LC) /* Late collision */
653 ndev->stats.tx_window_errors++;
654 if (status & BD_ENET_TX_RL) /* Retrans limit */
655 ndev->stats.tx_aborted_errors++;
656 if (status & BD_ENET_TX_UN) /* Underrun */
657 ndev->stats.tx_fifo_errors++;
658 if (status & BD_ENET_TX_CSL) /* Carrier lost */
659 ndev->stats.tx_carrier_errors++;
660 } else {
661 ndev->stats.tx_packets++;
662 }
663
664 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
665 fep->bufdesc_ex) {
666 struct skb_shared_hwtstamps shhwtstamps;
667 unsigned long flags;
668 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
669
670 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
671 spin_lock_irqsave(&fep->tmreg_lock, flags);
672 shhwtstamps.hwtstamp = ns_to_ktime(
673 timecounter_cyc2time(&fep->tc, ebdp->ts));
674 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
675 skb_tstamp_tx(skb, &shhwtstamps);
676 }
677
678 if (status & BD_ENET_TX_READY)
679 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
680
681 /* Deferred means some collisions occurred during transmit,
682 * but we eventually sent the packet OK.
683 */
684 if (status & BD_ENET_TX_DEF)
685 ndev->stats.collisions++;
686
687 /* Free the sk buffer associated with this last transmit */
688 dev_kfree_skb_any(skb);
689 fep->tx_skbuff[index] = NULL;
690
691 fep->dirty_tx = bdp;
692
693 /* Update pointer to next buffer descriptor to be transmitted */
694 if (status & BD_ENET_TX_WRAP)
695 bdp = fep->tx_bd_base;
696 else
697 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
698
699 /* Since we have freed up a buffer, the ring is no longer full
700 */
701 if (fep->dirty_tx != fep->cur_tx) {
702 if (netif_queue_stopped(ndev))
703 netif_wake_queue(ndev);
704 }
705 }
706 return;
707 }
708
709
710 /* During a receive, the cur_rx points to the current incoming buffer.
711 * When we update through the ring, if the next incoming buffer has
712 * not been given to the system, we just set the empty indicator,
713 * effectively tossing the packet.
714 */
715 static int
716 fec_enet_rx(struct net_device *ndev, int budget)
717 {
718 struct fec_enet_private *fep = netdev_priv(ndev);
719 const struct platform_device_id *id_entry =
720 platform_get_device_id(fep->pdev);
721 struct bufdesc *bdp;
722 unsigned short status;
723 struct sk_buff *skb;
724 ushort pkt_len;
725 __u8 *data;
726 int pkt_received = 0;
727
728 #ifdef CONFIG_M532x
729 flush_cache_all();
730 #endif
731
732 /* First, grab all of the stats for the incoming packet.
733 * These get messed up if we get called due to a busy condition.
734 */
735 bdp = fep->cur_rx;
736
737 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
738
739 if (pkt_received >= budget)
740 break;
741 pkt_received++;
742
743 /* Since we have allocated space to hold a complete frame,
744 * the last indicator should be set.
745 */
746 if ((status & BD_ENET_RX_LAST) == 0)
747 netdev_err(ndev, "rcv is not +last\n");
748
749 if (!fep->opened)
750 goto rx_processing_done;
751
752 /* Check for errors. */
753 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
754 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
755 ndev->stats.rx_errors++;
756 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
757 /* Frame too long or too short. */
758 ndev->stats.rx_length_errors++;
759 }
760 if (status & BD_ENET_RX_NO) /* Frame alignment */
761 ndev->stats.rx_frame_errors++;
762 if (status & BD_ENET_RX_CR) /* CRC Error */
763 ndev->stats.rx_crc_errors++;
764 if (status & BD_ENET_RX_OV) /* FIFO overrun */
765 ndev->stats.rx_fifo_errors++;
766 }
767
768 /* Report late collisions as a frame error.
769 * On this error, the BD is closed, but we don't know what we
770 * have in the buffer. So, just drop this frame on the floor.
771 */
772 if (status & BD_ENET_RX_CL) {
773 ndev->stats.rx_errors++;
774 ndev->stats.rx_frame_errors++;
775 goto rx_processing_done;
776 }
777
778 /* Process the incoming frame. */
779 ndev->stats.rx_packets++;
780 pkt_len = bdp->cbd_datlen;
781 ndev->stats.rx_bytes += pkt_len;
782 data = (__u8*)__va(bdp->cbd_bufaddr);
783
784 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
785 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
786
787 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
788 swap_buffer(data, pkt_len);
789
790 /* This does 16 byte alignment, exactly what we need.
791 * The packet length includes FCS, but we don't want to
792 * include that when passing upstream as it messes up
793 * bridging applications.
794 */
795 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
796
797 if (unlikely(!skb)) {
798 ndev->stats.rx_dropped++;
799 } else {
800 skb_reserve(skb, NET_IP_ALIGN);
801 skb_put(skb, pkt_len - 4); /* Make room */
802 skb_copy_to_linear_data(skb, data, pkt_len - 4);
803 skb->protocol = eth_type_trans(skb, ndev);
804
805 /* Get receive timestamp from the skb */
806 if (fep->hwts_rx_en && fep->bufdesc_ex) {
807 struct skb_shared_hwtstamps *shhwtstamps =
808 skb_hwtstamps(skb);
809 unsigned long flags;
810 struct bufdesc_ex *ebdp =
811 (struct bufdesc_ex *)bdp;
812
813 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
814
815 spin_lock_irqsave(&fep->tmreg_lock, flags);
816 shhwtstamps->hwtstamp = ns_to_ktime(
817 timecounter_cyc2time(&fep->tc, ebdp->ts));
818 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
819 }
820
821 if (!skb_defer_rx_timestamp(skb))
822 napi_gro_receive(&fep->napi, skb);
823 }
824
825 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
826 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
827 rx_processing_done:
828 /* Clear the status flags for this buffer */
829 status &= ~BD_ENET_RX_STATS;
830
831 /* Mark the buffer empty */
832 status |= BD_ENET_RX_EMPTY;
833 bdp->cbd_sc = status;
834
835 if (fep->bufdesc_ex) {
836 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
837
838 ebdp->cbd_esc = BD_ENET_RX_INT;
839 ebdp->cbd_prot = 0;
840 ebdp->cbd_bdu = 0;
841 }
842
843 /* Update BD pointer to next entry */
844 if (status & BD_ENET_RX_WRAP)
845 bdp = fep->rx_bd_base;
846 else
847 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
848 /* Doing this here will keep the FEC running while we process
849 * incoming frames. On a heavily loaded network, we should be
850 * able to keep up at the expense of system resources.
851 */
852 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
853 }
854 fep->cur_rx = bdp;
855
856 return pkt_received;
857 }
858
859 static irqreturn_t
860 fec_enet_interrupt(int irq, void *dev_id)
861 {
862 struct net_device *ndev = dev_id;
863 struct fec_enet_private *fep = netdev_priv(ndev);
864 uint int_events;
865 irqreturn_t ret = IRQ_NONE;
866
867 do {
868 int_events = readl(fep->hwp + FEC_IEVENT);
869 writel(int_events, fep->hwp + FEC_IEVENT);
870
871 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
872 ret = IRQ_HANDLED;
873
874 /* Disable the RX interrupt */
875 if (napi_schedule_prep(&fep->napi)) {
876 writel(FEC_RX_DISABLED_IMASK,
877 fep->hwp + FEC_IMASK);
878 __napi_schedule(&fep->napi);
879 }
880 }
881
882 if (int_events & FEC_ENET_MII) {
883 ret = IRQ_HANDLED;
884 complete(&fep->mdio_done);
885 }
886 } while (int_events);
887
888 return ret;
889 }
890
891 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
892 {
893 struct net_device *ndev = napi->dev;
894 int pkts = fec_enet_rx(ndev, budget);
895 struct fec_enet_private *fep = netdev_priv(ndev);
896
897 fec_enet_tx(ndev);
898
899 if (pkts < budget) {
900 napi_complete(napi);
901 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
902 }
903 return pkts;
904 }
905
906 /* ------------------------------------------------------------------------- */
907 static void fec_get_mac(struct net_device *ndev)
908 {
909 struct fec_enet_private *fep = netdev_priv(ndev);
910 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
911 unsigned char *iap, tmpaddr[ETH_ALEN];
912
913 /*
914 * try to get mac address in following order:
915 *
916 * 1) module parameter via kernel command line in form
917 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
918 */
919 iap = macaddr;
920
921 /*
922 * 2) from device tree data
923 */
924 if (!is_valid_ether_addr(iap)) {
925 struct device_node *np = fep->pdev->dev.of_node;
926 if (np) {
927 const char *mac = of_get_mac_address(np);
928 if (mac)
929 iap = (unsigned char *) mac;
930 }
931 }
932
933 /*
934 * 3) from flash or fuse (via platform data)
935 */
936 if (!is_valid_ether_addr(iap)) {
937 #ifdef CONFIG_M5272
938 if (FEC_FLASHMAC)
939 iap = (unsigned char *)FEC_FLASHMAC;
940 #else
941 if (pdata)
942 iap = (unsigned char *)&pdata->mac;
943 #endif
944 }
945
946 /*
947 * 4) FEC mac registers set by bootloader
948 */
949 if (!is_valid_ether_addr(iap)) {
950 *((unsigned long *) &tmpaddr[0]) =
951 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
952 *((unsigned short *) &tmpaddr[4]) =
953 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
954 iap = &tmpaddr[0];
955 }
956
957 memcpy(ndev->dev_addr, iap, ETH_ALEN);
958
959 /* Adjust MAC if using macaddr */
960 if (iap == macaddr)
961 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
962 }
963
964 /* ------------------------------------------------------------------------- */
965
966 /*
967 * Phy section
968 */
969 static void fec_enet_adjust_link(struct net_device *ndev)
970 {
971 struct fec_enet_private *fep = netdev_priv(ndev);
972 struct phy_device *phy_dev = fep->phy_dev;
973 unsigned long flags;
974
975 int status_change = 0;
976
977 spin_lock_irqsave(&fep->hw_lock, flags);
978
979 /* Prevent a state halted on mii error */
980 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
981 phy_dev->state = PHY_RESUMING;
982 goto spin_unlock;
983 }
984
985 if (phy_dev->link) {
986 if (!fep->link) {
987 fep->link = phy_dev->link;
988 status_change = 1;
989 }
990
991 if (fep->full_duplex != phy_dev->duplex)
992 status_change = 1;
993
994 if (phy_dev->speed != fep->speed) {
995 fep->speed = phy_dev->speed;
996 status_change = 1;
997 }
998
999 /* if any of the above changed restart the FEC */
1000 if (status_change)
1001 fec_restart(ndev, phy_dev->duplex);
1002 } else {
1003 if (fep->link) {
1004 fec_stop(ndev);
1005 status_change = 1;
1006 }
1007 }
1008
1009 spin_unlock:
1010 spin_unlock_irqrestore(&fep->hw_lock, flags);
1011
1012 if (status_change)
1013 phy_print_status(phy_dev);
1014 }
1015
1016 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1017 {
1018 struct fec_enet_private *fep = bus->priv;
1019 unsigned long time_left;
1020
1021 fep->mii_timeout = 0;
1022 init_completion(&fep->mdio_done);
1023
1024 /* start a read op */
1025 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1026 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1027 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1028
1029 /* wait for end of transfer */
1030 time_left = wait_for_completion_timeout(&fep->mdio_done,
1031 usecs_to_jiffies(FEC_MII_TIMEOUT));
1032 if (time_left == 0) {
1033 fep->mii_timeout = 1;
1034 netdev_err(fep->netdev, "MDIO read timeout\n");
1035 return -ETIMEDOUT;
1036 }
1037
1038 /* return value */
1039 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1040 }
1041
1042 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1043 u16 value)
1044 {
1045 struct fec_enet_private *fep = bus->priv;
1046 unsigned long time_left;
1047
1048 fep->mii_timeout = 0;
1049 init_completion(&fep->mdio_done);
1050
1051 /* start a write op */
1052 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1053 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1054 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1055 fep->hwp + FEC_MII_DATA);
1056
1057 /* wait for end of transfer */
1058 time_left = wait_for_completion_timeout(&fep->mdio_done,
1059 usecs_to_jiffies(FEC_MII_TIMEOUT));
1060 if (time_left == 0) {
1061 fep->mii_timeout = 1;
1062 netdev_err(fep->netdev, "MDIO write timeout\n");
1063 return -ETIMEDOUT;
1064 }
1065
1066 return 0;
1067 }
1068
1069 static int fec_enet_mdio_reset(struct mii_bus *bus)
1070 {
1071 return 0;
1072 }
1073
1074 static int fec_enet_mii_probe(struct net_device *ndev)
1075 {
1076 struct fec_enet_private *fep = netdev_priv(ndev);
1077 const struct platform_device_id *id_entry =
1078 platform_get_device_id(fep->pdev);
1079 struct phy_device *phy_dev = NULL;
1080 char mdio_bus_id[MII_BUS_ID_SIZE];
1081 char phy_name[MII_BUS_ID_SIZE + 3];
1082 int phy_id;
1083 int dev_id = fep->dev_id;
1084
1085 fep->phy_dev = NULL;
1086
1087 /* check for attached phy */
1088 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1089 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1090 continue;
1091 if (fep->mii_bus->phy_map[phy_id] == NULL)
1092 continue;
1093 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1094 continue;
1095 if (dev_id--)
1096 continue;
1097 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1098 break;
1099 }
1100
1101 if (phy_id >= PHY_MAX_ADDR) {
1102 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1103 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1104 phy_id = 0;
1105 }
1106
1107 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1108 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1109 fep->phy_interface);
1110 if (IS_ERR(phy_dev)) {
1111 netdev_err(ndev, "could not attach to PHY\n");
1112 return PTR_ERR(phy_dev);
1113 }
1114
1115 /* mask with MAC supported features */
1116 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1117 phy_dev->supported &= PHY_GBIT_FEATURES;
1118 phy_dev->supported |= SUPPORTED_Pause;
1119 }
1120 else
1121 phy_dev->supported &= PHY_BASIC_FEATURES;
1122
1123 phy_dev->advertising = phy_dev->supported;
1124
1125 fep->phy_dev = phy_dev;
1126 fep->link = 0;
1127 fep->full_duplex = 0;
1128
1129 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1130 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1131 fep->phy_dev->irq);
1132
1133 return 0;
1134 }
1135
1136 static int fec_enet_mii_init(struct platform_device *pdev)
1137 {
1138 static struct mii_bus *fec0_mii_bus;
1139 struct net_device *ndev = platform_get_drvdata(pdev);
1140 struct fec_enet_private *fep = netdev_priv(ndev);
1141 const struct platform_device_id *id_entry =
1142 platform_get_device_id(fep->pdev);
1143 int err = -ENXIO, i;
1144
1145 /*
1146 * The dual fec interfaces are not equivalent with enet-mac.
1147 * Here are the differences:
1148 *
1149 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1150 * - fec0 acts as the 1588 time master while fec1 is slave
1151 * - external phys can only be configured by fec0
1152 *
1153 * That is to say fec1 can not work independently. It only works
1154 * when fec0 is working. The reason behind this design is that the
1155 * second interface is added primarily for Switch mode.
1156 *
1157 * Because of the last point above, both phys are attached on fec0
1158 * mdio interface in board design, and need to be configured by
1159 * fec0 mii_bus.
1160 */
1161 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1162 /* fec1 uses fec0 mii_bus */
1163 if (mii_cnt && fec0_mii_bus) {
1164 fep->mii_bus = fec0_mii_bus;
1165 mii_cnt++;
1166 return 0;
1167 }
1168 return -ENOENT;
1169 }
1170
1171 fep->mii_timeout = 0;
1172
1173 /*
1174 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1175 *
1176 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1177 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1178 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1179 * document.
1180 */
1181 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1182 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1183 fep->phy_speed--;
1184 fep->phy_speed <<= 1;
1185 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1186
1187 fep->mii_bus = mdiobus_alloc();
1188 if (fep->mii_bus == NULL) {
1189 err = -ENOMEM;
1190 goto err_out;
1191 }
1192
1193 fep->mii_bus->name = "fec_enet_mii_bus";
1194 fep->mii_bus->read = fec_enet_mdio_read;
1195 fep->mii_bus->write = fec_enet_mdio_write;
1196 fep->mii_bus->reset = fec_enet_mdio_reset;
1197 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1198 pdev->name, fep->dev_id + 1);
1199 fep->mii_bus->priv = fep;
1200 fep->mii_bus->parent = &pdev->dev;
1201
1202 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1203 if (!fep->mii_bus->irq) {
1204 err = -ENOMEM;
1205 goto err_out_free_mdiobus;
1206 }
1207
1208 for (i = 0; i < PHY_MAX_ADDR; i++)
1209 fep->mii_bus->irq[i] = PHY_POLL;
1210
1211 if (mdiobus_register(fep->mii_bus))
1212 goto err_out_free_mdio_irq;
1213
1214 mii_cnt++;
1215
1216 /* save fec0 mii_bus */
1217 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1218 fec0_mii_bus = fep->mii_bus;
1219
1220 return 0;
1221
1222 err_out_free_mdio_irq:
1223 kfree(fep->mii_bus->irq);
1224 err_out_free_mdiobus:
1225 mdiobus_free(fep->mii_bus);
1226 err_out:
1227 return err;
1228 }
1229
1230 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1231 {
1232 if (--mii_cnt == 0) {
1233 mdiobus_unregister(fep->mii_bus);
1234 kfree(fep->mii_bus->irq);
1235 mdiobus_free(fep->mii_bus);
1236 }
1237 }
1238
1239 static int fec_enet_get_settings(struct net_device *ndev,
1240 struct ethtool_cmd *cmd)
1241 {
1242 struct fec_enet_private *fep = netdev_priv(ndev);
1243 struct phy_device *phydev = fep->phy_dev;
1244
1245 if (!phydev)
1246 return -ENODEV;
1247
1248 return phy_ethtool_gset(phydev, cmd);
1249 }
1250
1251 static int fec_enet_set_settings(struct net_device *ndev,
1252 struct ethtool_cmd *cmd)
1253 {
1254 struct fec_enet_private *fep = netdev_priv(ndev);
1255 struct phy_device *phydev = fep->phy_dev;
1256
1257 if (!phydev)
1258 return -ENODEV;
1259
1260 return phy_ethtool_sset(phydev, cmd);
1261 }
1262
1263 static void fec_enet_get_drvinfo(struct net_device *ndev,
1264 struct ethtool_drvinfo *info)
1265 {
1266 struct fec_enet_private *fep = netdev_priv(ndev);
1267
1268 strlcpy(info->driver, fep->pdev->dev.driver->name,
1269 sizeof(info->driver));
1270 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1271 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1272 }
1273
1274 static int fec_enet_get_ts_info(struct net_device *ndev,
1275 struct ethtool_ts_info *info)
1276 {
1277 struct fec_enet_private *fep = netdev_priv(ndev);
1278
1279 if (fep->bufdesc_ex) {
1280
1281 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1282 SOF_TIMESTAMPING_RX_SOFTWARE |
1283 SOF_TIMESTAMPING_SOFTWARE |
1284 SOF_TIMESTAMPING_TX_HARDWARE |
1285 SOF_TIMESTAMPING_RX_HARDWARE |
1286 SOF_TIMESTAMPING_RAW_HARDWARE;
1287 if (fep->ptp_clock)
1288 info->phc_index = ptp_clock_index(fep->ptp_clock);
1289 else
1290 info->phc_index = -1;
1291
1292 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1293 (1 << HWTSTAMP_TX_ON);
1294
1295 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1296 (1 << HWTSTAMP_FILTER_ALL);
1297 return 0;
1298 } else {
1299 return ethtool_op_get_ts_info(ndev, info);
1300 }
1301 }
1302
1303 static void fec_enet_get_pauseparam(struct net_device *ndev,
1304 struct ethtool_pauseparam *pause)
1305 {
1306 struct fec_enet_private *fep = netdev_priv(ndev);
1307
1308 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1309 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1310 pause->rx_pause = pause->tx_pause;
1311 }
1312
1313 static int fec_enet_set_pauseparam(struct net_device *ndev,
1314 struct ethtool_pauseparam *pause)
1315 {
1316 struct fec_enet_private *fep = netdev_priv(ndev);
1317
1318 if (pause->tx_pause != pause->rx_pause) {
1319 netdev_info(ndev,
1320 "hardware only support enable/disable both tx and rx");
1321 return -EINVAL;
1322 }
1323
1324 fep->pause_flag = 0;
1325
1326 /* tx pause must be same as rx pause */
1327 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1328 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1329
1330 if (pause->rx_pause || pause->autoneg) {
1331 fep->phy_dev->supported |= ADVERTISED_Pause;
1332 fep->phy_dev->advertising |= ADVERTISED_Pause;
1333 } else {
1334 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1335 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1336 }
1337
1338 if (pause->autoneg) {
1339 if (netif_running(ndev))
1340 fec_stop(ndev);
1341 phy_start_aneg(fep->phy_dev);
1342 }
1343 if (netif_running(ndev))
1344 fec_restart(ndev, 0);
1345
1346 return 0;
1347 }
1348
1349 static const struct ethtool_ops fec_enet_ethtool_ops = {
1350 .get_pauseparam = fec_enet_get_pauseparam,
1351 .set_pauseparam = fec_enet_set_pauseparam,
1352 .get_settings = fec_enet_get_settings,
1353 .set_settings = fec_enet_set_settings,
1354 .get_drvinfo = fec_enet_get_drvinfo,
1355 .get_link = ethtool_op_get_link,
1356 .get_ts_info = fec_enet_get_ts_info,
1357 };
1358
1359 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1360 {
1361 struct fec_enet_private *fep = netdev_priv(ndev);
1362 struct phy_device *phydev = fep->phy_dev;
1363
1364 if (!netif_running(ndev))
1365 return -EINVAL;
1366
1367 if (!phydev)
1368 return -ENODEV;
1369
1370 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
1371 return fec_ptp_ioctl(ndev, rq, cmd);
1372
1373 return phy_mii_ioctl(phydev, rq, cmd);
1374 }
1375
1376 static void fec_enet_free_buffers(struct net_device *ndev)
1377 {
1378 struct fec_enet_private *fep = netdev_priv(ndev);
1379 unsigned int i;
1380 struct sk_buff *skb;
1381 struct bufdesc *bdp;
1382
1383 bdp = fep->rx_bd_base;
1384 for (i = 0; i < RX_RING_SIZE; i++) {
1385 skb = fep->rx_skbuff[i];
1386
1387 if (bdp->cbd_bufaddr)
1388 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1389 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1390 if (skb)
1391 dev_kfree_skb(skb);
1392 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1393 }
1394
1395 bdp = fep->tx_bd_base;
1396 for (i = 0; i < TX_RING_SIZE; i++)
1397 kfree(fep->tx_bounce[i]);
1398 }
1399
1400 static int fec_enet_alloc_buffers(struct net_device *ndev)
1401 {
1402 struct fec_enet_private *fep = netdev_priv(ndev);
1403 unsigned int i;
1404 struct sk_buff *skb;
1405 struct bufdesc *bdp;
1406
1407 bdp = fep->rx_bd_base;
1408 for (i = 0; i < RX_RING_SIZE; i++) {
1409 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1410 if (!skb) {
1411 fec_enet_free_buffers(ndev);
1412 return -ENOMEM;
1413 }
1414 fep->rx_skbuff[i] = skb;
1415
1416 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1417 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1418 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1419
1420 if (fep->bufdesc_ex) {
1421 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1422 ebdp->cbd_esc = BD_ENET_RX_INT;
1423 }
1424
1425 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1426 }
1427
1428 /* Set the last buffer to wrap. */
1429 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1430 bdp->cbd_sc |= BD_SC_WRAP;
1431
1432 bdp = fep->tx_bd_base;
1433 for (i = 0; i < TX_RING_SIZE; i++) {
1434 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1435
1436 bdp->cbd_sc = 0;
1437 bdp->cbd_bufaddr = 0;
1438
1439 if (fep->bufdesc_ex) {
1440 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1441 ebdp->cbd_esc = BD_ENET_TX_INT;
1442 }
1443
1444 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1445 }
1446
1447 /* Set the last buffer to wrap. */
1448 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1449 bdp->cbd_sc |= BD_SC_WRAP;
1450
1451 return 0;
1452 }
1453
1454 static int
1455 fec_enet_open(struct net_device *ndev)
1456 {
1457 struct fec_enet_private *fep = netdev_priv(ndev);
1458 int ret;
1459
1460 napi_enable(&fep->napi);
1461
1462 /* I should reset the ring buffers here, but I don't yet know
1463 * a simple way to do that.
1464 */
1465
1466 ret = fec_enet_alloc_buffers(ndev);
1467 if (ret)
1468 return ret;
1469
1470 /* Probe and connect to PHY when open the interface */
1471 ret = fec_enet_mii_probe(ndev);
1472 if (ret) {
1473 fec_enet_free_buffers(ndev);
1474 return ret;
1475 }
1476 phy_start(fep->phy_dev);
1477 netif_start_queue(ndev);
1478 fep->opened = 1;
1479 return 0;
1480 }
1481
1482 static int
1483 fec_enet_close(struct net_device *ndev)
1484 {
1485 struct fec_enet_private *fep = netdev_priv(ndev);
1486
1487 /* Don't know what to do yet. */
1488 napi_disable(&fep->napi);
1489 fep->opened = 0;
1490 netif_stop_queue(ndev);
1491 fec_stop(ndev);
1492
1493 if (fep->phy_dev) {
1494 phy_stop(fep->phy_dev);
1495 phy_disconnect(fep->phy_dev);
1496 }
1497
1498 fec_enet_free_buffers(ndev);
1499
1500 return 0;
1501 }
1502
1503 /* Set or clear the multicast filter for this adaptor.
1504 * Skeleton taken from sunlance driver.
1505 * The CPM Ethernet implementation allows Multicast as well as individual
1506 * MAC address filtering. Some of the drivers check to make sure it is
1507 * a group multicast address, and discard those that are not. I guess I
1508 * will do the same for now, but just remove the test if you want
1509 * individual filtering as well (do the upper net layers want or support
1510 * this kind of feature?).
1511 */
1512
1513 #define HASH_BITS 6 /* #bits in hash */
1514 #define CRC32_POLY 0xEDB88320
1515
1516 static void set_multicast_list(struct net_device *ndev)
1517 {
1518 struct fec_enet_private *fep = netdev_priv(ndev);
1519 struct netdev_hw_addr *ha;
1520 unsigned int i, bit, data, crc, tmp;
1521 unsigned char hash;
1522
1523 if (ndev->flags & IFF_PROMISC) {
1524 tmp = readl(fep->hwp + FEC_R_CNTRL);
1525 tmp |= 0x8;
1526 writel(tmp, fep->hwp + FEC_R_CNTRL);
1527 return;
1528 }
1529
1530 tmp = readl(fep->hwp + FEC_R_CNTRL);
1531 tmp &= ~0x8;
1532 writel(tmp, fep->hwp + FEC_R_CNTRL);
1533
1534 if (ndev->flags & IFF_ALLMULTI) {
1535 /* Catch all multicast addresses, so set the
1536 * filter to all 1's
1537 */
1538 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1539 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1540
1541 return;
1542 }
1543
1544 /* Clear filter and add the addresses in hash register
1545 */
1546 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1547 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1548
1549 netdev_for_each_mc_addr(ha, ndev) {
1550 /* calculate crc32 value of mac address */
1551 crc = 0xffffffff;
1552
1553 for (i = 0; i < ndev->addr_len; i++) {
1554 data = ha->addr[i];
1555 for (bit = 0; bit < 8; bit++, data >>= 1) {
1556 crc = (crc >> 1) ^
1557 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1558 }
1559 }
1560
1561 /* only upper 6 bits (HASH_BITS) are used
1562 * which point to specific bit in he hash registers
1563 */
1564 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1565
1566 if (hash > 31) {
1567 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1568 tmp |= 1 << (hash - 32);
1569 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1570 } else {
1571 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1572 tmp |= 1 << hash;
1573 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1574 }
1575 }
1576 }
1577
1578 /* Set a MAC change in hardware. */
1579 static int
1580 fec_set_mac_address(struct net_device *ndev, void *p)
1581 {
1582 struct fec_enet_private *fep = netdev_priv(ndev);
1583 struct sockaddr *addr = p;
1584
1585 if (!is_valid_ether_addr(addr->sa_data))
1586 return -EADDRNOTAVAIL;
1587
1588 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1589
1590 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1591 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1592 fep->hwp + FEC_ADDR_LOW);
1593 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1594 fep->hwp + FEC_ADDR_HIGH);
1595 return 0;
1596 }
1597
1598 #ifdef CONFIG_NET_POLL_CONTROLLER
1599 /**
1600 * fec_poll_controller - FEC Poll controller function
1601 * @dev: The FEC network adapter
1602 *
1603 * Polled functionality used by netconsole and others in non interrupt mode
1604 *
1605 */
1606 static void fec_poll_controller(struct net_device *dev)
1607 {
1608 int i;
1609 struct fec_enet_private *fep = netdev_priv(dev);
1610
1611 for (i = 0; i < FEC_IRQ_NUM; i++) {
1612 if (fep->irq[i] > 0) {
1613 disable_irq(fep->irq[i]);
1614 fec_enet_interrupt(fep->irq[i], dev);
1615 enable_irq(fep->irq[i]);
1616 }
1617 }
1618 }
1619 #endif
1620
1621 static const struct net_device_ops fec_netdev_ops = {
1622 .ndo_open = fec_enet_open,
1623 .ndo_stop = fec_enet_close,
1624 .ndo_start_xmit = fec_enet_start_xmit,
1625 .ndo_set_rx_mode = set_multicast_list,
1626 .ndo_change_mtu = eth_change_mtu,
1627 .ndo_validate_addr = eth_validate_addr,
1628 .ndo_tx_timeout = fec_timeout,
1629 .ndo_set_mac_address = fec_set_mac_address,
1630 .ndo_do_ioctl = fec_enet_ioctl,
1631 #ifdef CONFIG_NET_POLL_CONTROLLER
1632 .ndo_poll_controller = fec_poll_controller,
1633 #endif
1634 };
1635
1636 /*
1637 * XXX: We need to clean up on failure exits here.
1638 *
1639 */
1640 static int fec_enet_init(struct net_device *ndev)
1641 {
1642 struct fec_enet_private *fep = netdev_priv(ndev);
1643 struct bufdesc *cbd_base;
1644
1645 /* Allocate memory for buffer descriptors. */
1646 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1647 GFP_KERNEL);
1648 if (!cbd_base)
1649 return -ENOMEM;
1650
1651 memset(cbd_base, 0, PAGE_SIZE);
1652 spin_lock_init(&fep->hw_lock);
1653
1654 fep->netdev = ndev;
1655
1656 /* Get the Ethernet address */
1657 fec_get_mac(ndev);
1658
1659 /* Set receive and transmit descriptor base. */
1660 fep->rx_bd_base = cbd_base;
1661 if (fep->bufdesc_ex)
1662 fep->tx_bd_base = (struct bufdesc *)
1663 (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE);
1664 else
1665 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1666
1667 /* The FEC Ethernet specific entries in the device structure */
1668 ndev->watchdog_timeo = TX_TIMEOUT;
1669 ndev->netdev_ops = &fec_netdev_ops;
1670 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1671
1672 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
1673 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
1674
1675 fec_restart(ndev, 0);
1676
1677 return 0;
1678 }
1679
1680 #ifdef CONFIG_OF
1681 static void fec_reset_phy(struct platform_device *pdev)
1682 {
1683 int err, phy_reset;
1684 int msec = 1;
1685 struct device_node *np = pdev->dev.of_node;
1686
1687 if (!np)
1688 return;
1689
1690 of_property_read_u32(np, "phy-reset-duration", &msec);
1691 /* A sane reset duration should not be longer than 1s */
1692 if (msec > 1000)
1693 msec = 1;
1694
1695 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1696 if (!gpio_is_valid(phy_reset))
1697 return;
1698
1699 err = devm_gpio_request_one(&pdev->dev, phy_reset,
1700 GPIOF_OUT_INIT_LOW, "phy-reset");
1701 if (err) {
1702 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
1703 return;
1704 }
1705 msleep(msec);
1706 gpio_set_value(phy_reset, 1);
1707 }
1708 #else /* CONFIG_OF */
1709 static void fec_reset_phy(struct platform_device *pdev)
1710 {
1711 /*
1712 * In case of platform probe, the reset has been done
1713 * by machine code.
1714 */
1715 }
1716 #endif /* CONFIG_OF */
1717
1718 static int
1719 fec_probe(struct platform_device *pdev)
1720 {
1721 struct fec_enet_private *fep;
1722 struct fec_platform_data *pdata;
1723 struct net_device *ndev;
1724 int i, irq, ret = 0;
1725 struct resource *r;
1726 const struct of_device_id *of_id;
1727 static int dev_id;
1728 struct pinctrl *pinctrl;
1729 struct regulator *reg_phy;
1730
1731 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1732 if (of_id)
1733 pdev->id_entry = of_id->data;
1734
1735 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1736 if (!r)
1737 return -ENXIO;
1738
1739 /* Init network device */
1740 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1741 if (!ndev)
1742 return -ENOMEM;
1743
1744 SET_NETDEV_DEV(ndev, &pdev->dev);
1745
1746 /* setup board info structure */
1747 fep = netdev_priv(ndev);
1748
1749 /* default enable pause frame auto negotiation */
1750 if (pdev->id_entry &&
1751 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
1752 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
1753
1754 fep->hwp = devm_request_and_ioremap(&pdev->dev, r);
1755 fep->pdev = pdev;
1756 fep->dev_id = dev_id++;
1757
1758 fep->bufdesc_ex = 0;
1759
1760 if (!fep->hwp) {
1761 ret = -ENOMEM;
1762 goto failed_ioremap;
1763 }
1764
1765 platform_set_drvdata(pdev, ndev);
1766
1767 ret = of_get_phy_mode(pdev->dev.of_node);
1768 if (ret < 0) {
1769 pdata = pdev->dev.platform_data;
1770 if (pdata)
1771 fep->phy_interface = pdata->phy;
1772 else
1773 fep->phy_interface = PHY_INTERFACE_MODE_MII;
1774 } else {
1775 fep->phy_interface = ret;
1776 }
1777
1778 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1779 if (IS_ERR(pinctrl)) {
1780 ret = PTR_ERR(pinctrl);
1781 goto failed_pin;
1782 }
1783
1784 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1785 if (IS_ERR(fep->clk_ipg)) {
1786 ret = PTR_ERR(fep->clk_ipg);
1787 goto failed_clk;
1788 }
1789
1790 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1791 if (IS_ERR(fep->clk_ahb)) {
1792 ret = PTR_ERR(fep->clk_ahb);
1793 goto failed_clk;
1794 }
1795
1796 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
1797 fep->bufdesc_ex =
1798 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
1799 if (IS_ERR(fep->clk_ptp)) {
1800 ret = PTR_ERR(fep->clk_ptp);
1801 fep->bufdesc_ex = 0;
1802 }
1803
1804 clk_prepare_enable(fep->clk_ahb);
1805 clk_prepare_enable(fep->clk_ipg);
1806 if (!IS_ERR(fep->clk_ptp))
1807 clk_prepare_enable(fep->clk_ptp);
1808
1809 reg_phy = devm_regulator_get(&pdev->dev, "phy");
1810 if (!IS_ERR(reg_phy)) {
1811 ret = regulator_enable(reg_phy);
1812 if (ret) {
1813 dev_err(&pdev->dev,
1814 "Failed to enable phy regulator: %d\n", ret);
1815 goto failed_regulator;
1816 }
1817 }
1818
1819 fec_reset_phy(pdev);
1820
1821 if (fep->bufdesc_ex)
1822 fec_ptp_init(ndev, pdev);
1823
1824 ret = fec_enet_init(ndev);
1825 if (ret)
1826 goto failed_init;
1827
1828 for (i = 0; i < FEC_IRQ_NUM; i++) {
1829 irq = platform_get_irq(pdev, i);
1830 if (irq < 0) {
1831 if (i)
1832 break;
1833 ret = irq;
1834 goto failed_irq;
1835 }
1836 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1837 if (ret) {
1838 while (--i >= 0) {
1839 irq = platform_get_irq(pdev, i);
1840 free_irq(irq, ndev);
1841 }
1842 goto failed_irq;
1843 }
1844 }
1845
1846 ret = fec_enet_mii_init(pdev);
1847 if (ret)
1848 goto failed_mii_init;
1849
1850 /* Carrier starts down, phylib will bring it up */
1851 netif_carrier_off(ndev);
1852
1853 ret = register_netdev(ndev);
1854 if (ret)
1855 goto failed_register;
1856
1857 if (fep->bufdesc_ex && fep->ptp_clock)
1858 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
1859
1860 return 0;
1861
1862 failed_register:
1863 fec_enet_mii_remove(fep);
1864 failed_mii_init:
1865 failed_init:
1866 for (i = 0; i < FEC_IRQ_NUM; i++) {
1867 irq = platform_get_irq(pdev, i);
1868 if (irq > 0)
1869 free_irq(irq, ndev);
1870 }
1871 failed_irq:
1872 failed_regulator:
1873 clk_disable_unprepare(fep->clk_ahb);
1874 clk_disable_unprepare(fep->clk_ipg);
1875 if (!IS_ERR(fep->clk_ptp))
1876 clk_disable_unprepare(fep->clk_ptp);
1877 failed_pin:
1878 failed_clk:
1879 failed_ioremap:
1880 free_netdev(ndev);
1881
1882 return ret;
1883 }
1884
1885 static int
1886 fec_drv_remove(struct platform_device *pdev)
1887 {
1888 struct net_device *ndev = platform_get_drvdata(pdev);
1889 struct fec_enet_private *fep = netdev_priv(ndev);
1890 int i;
1891
1892 unregister_netdev(ndev);
1893 fec_enet_mii_remove(fep);
1894 del_timer_sync(&fep->time_keep);
1895 clk_disable_unprepare(fep->clk_ptp);
1896 if (fep->ptp_clock)
1897 ptp_clock_unregister(fep->ptp_clock);
1898 clk_disable_unprepare(fep->clk_ahb);
1899 clk_disable_unprepare(fep->clk_ipg);
1900 for (i = 0; i < FEC_IRQ_NUM; i++) {
1901 int irq = platform_get_irq(pdev, i);
1902 if (irq > 0)
1903 free_irq(irq, ndev);
1904 }
1905 free_netdev(ndev);
1906
1907 platform_set_drvdata(pdev, NULL);
1908
1909 return 0;
1910 }
1911
1912 #ifdef CONFIG_PM
1913 static int
1914 fec_suspend(struct device *dev)
1915 {
1916 struct net_device *ndev = dev_get_drvdata(dev);
1917 struct fec_enet_private *fep = netdev_priv(ndev);
1918
1919 if (netif_running(ndev)) {
1920 fec_stop(ndev);
1921 netif_device_detach(ndev);
1922 }
1923 clk_disable_unprepare(fep->clk_ahb);
1924 clk_disable_unprepare(fep->clk_ipg);
1925
1926 return 0;
1927 }
1928
1929 static int
1930 fec_resume(struct device *dev)
1931 {
1932 struct net_device *ndev = dev_get_drvdata(dev);
1933 struct fec_enet_private *fep = netdev_priv(ndev);
1934
1935 clk_prepare_enable(fep->clk_ahb);
1936 clk_prepare_enable(fep->clk_ipg);
1937 if (netif_running(ndev)) {
1938 fec_restart(ndev, fep->full_duplex);
1939 netif_device_attach(ndev);
1940 }
1941
1942 return 0;
1943 }
1944
1945 static const struct dev_pm_ops fec_pm_ops = {
1946 .suspend = fec_suspend,
1947 .resume = fec_resume,
1948 .freeze = fec_suspend,
1949 .thaw = fec_resume,
1950 .poweroff = fec_suspend,
1951 .restore = fec_resume,
1952 };
1953 #endif
1954
1955 static struct platform_driver fec_driver = {
1956 .driver = {
1957 .name = DRIVER_NAME,
1958 .owner = THIS_MODULE,
1959 #ifdef CONFIG_PM
1960 .pm = &fec_pm_ops,
1961 #endif
1962 .of_match_table = fec_dt_ids,
1963 },
1964 .id_table = fec_devtype,
1965 .probe = fec_probe,
1966 .remove = fec_drv_remove,
1967 };
1968
1969 module_platform_driver(fec_driver);
1970
1971 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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