drivers/net/ethernet/freescale/fs_enet/mac-fcc.c

   1 /*
   2  * FCC driver for Motorola MPC82xx (PQ2).
   3  *
   4  * Copyright (c) 2003 Intracom S.A.
   5  *  by Pantelis Antoniou <panto@intracom.gr>
   6  *
   7  * 2005 (c) MontaVista Software, Inc.
   8  * Vitaly Bordug <vbordug@ru.mvista.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public License
  11  * version 2. This program is licensed "as is" without any warranty of any
  12  * kind, whether express or implied.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/types.h>
  18 #include <linux/string.h>
  19 #include <linux/ptrace.h>
  20 #include <linux/errno.h>
  21 #include <linux/ioport.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/init.h>
  24 #include <linux/delay.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/mii.h>
  30 #include <linux/ethtool.h>
  31 #include <linux/bitops.h>
  32 #include <linux/fs.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/phy.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_device.h>
  37 #include <linux/of_irq.h>
  38 #include <linux/gfp.h>
  39
  40 #include <asm/immap_cpm2.h>
  41 #include <asm/mpc8260.h>
  42 #include <asm/cpm2.h>
  43
  44 #include <asm/pgtable.h>
  45 #include <asm/irq.h>
  46 #include <asm/uaccess.h>
  47
  48 #include "fs_enet.h"
  49
  50 /*************************************************/
  51
  52 /* FCC access macros */
  53
  54 /* write, read, set bits, clear bits */
  55 #define W32(_p, _m, _v) out_be32(&(_p)->_m, (_v))
  56 #define R32(_p, _m)     in_be32(&(_p)->_m)
  57 #define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) | (_v))
  58 #define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v))
  59
  60 #define W16(_p, _m, _v) out_be16(&(_p)->_m, (_v))
  61 #define R16(_p, _m)     in_be16(&(_p)->_m)
  62 #define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) | (_v))
  63 #define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v))
  64
  65 #define W8(_p, _m, _v)  out_8(&(_p)->_m, (_v))
  66 #define R8(_p, _m)      in_8(&(_p)->_m)
  67 #define S8(_p, _m, _v)  W8(_p, _m, R8(_p, _m) | (_v))
  68 #define C8(_p, _m, _v)  W8(_p, _m, R8(_p, _m) & ~(_v))
  69
  70 /*************************************************/
  71
  72 #define FCC_MAX_MULTICAST_ADDRS 64
  73
  74 #define mk_mii_read(REG)        (0x60020000 | ((REG & 0x1f) << 18))
  75 #define mk_mii_write(REG, VAL)  (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
  76 #define mk_mii_end              0
  77
  78 #define MAX_CR_CMD_LOOPS        10000
  79
  80 static inline int fcc_cr_cmd(struct fs_enet_private *fep, u32 op)
  81 {
  82         const struct fs_platform_info *fpi = fep->fpi;
  83
  84         return cpm_command(fpi->cp_command, op);
  85 }
  86
  87 static int do_pd_setup(struct fs_enet_private *fep)
  88 {
  89         struct platform_device *ofdev = to_platform_device(fep->dev);
  90         struct fs_platform_info *fpi = fep->fpi;
  91         int ret = -EINVAL;
  92
  93         fep->interrupt = of_irq_to_resource(ofdev->dev.of_node, 0, NULL);
  94         if (fep->interrupt == NO_IRQ)
  95                 goto out;
  96
  97         fep->fcc.fccp = of_iomap(ofdev->dev.of_node, 0);
  98         if (!fep->fcc.fccp)
  99                 goto out;
 100
 101         fep->fcc.ep = of_iomap(ofdev->dev.of_node, 1);
 102         if (!fep->fcc.ep)
 103                 goto out_fccp;
 104
 105         fep->fcc.fcccp = of_iomap(ofdev->dev.of_node, 2);
 106         if (!fep->fcc.fcccp)
 107                 goto out_ep;
 108
 109         fep->fcc.mem = (void __iomem *)cpm2_immr;
 110         fpi->dpram_offset = cpm_dpalloc(128, 32);
 111         if (IS_ERR_VALUE(fpi->dpram_offset)) {
 112                 ret = fpi->dpram_offset;
 113                 goto out_fcccp;
 114         }
 115
 116         return 0;
 117
 118 out_fcccp:
 119         iounmap(fep->fcc.fcccp);
 120 out_ep:
 121         iounmap(fep->fcc.ep);
 122 out_fccp:
 123         iounmap(fep->fcc.fccp);
 124 out:
 125         return ret;
 126 }
 127
 128 #define FCC_NAPI_RX_EVENT_MSK   (FCC_ENET_RXF | FCC_ENET_RXB)
 129 #define FCC_RX_EVENT            (FCC_ENET_RXF)
 130 #define FCC_TX_EVENT            (FCC_ENET_TXB)
 131 #define FCC_ERR_EVENT_MSK       (FCC_ENET_TXE)
 132
 133 static int setup_data(struct net_device *dev)
 134 {
 135         struct fs_enet_private *fep = netdev_priv(dev);
 136
 137         if (do_pd_setup(fep) != 0)
 138                 return -EINVAL;
 139
 140         fep->ev_napi_rx = FCC_NAPI_RX_EVENT_MSK;
 141         fep->ev_rx = FCC_RX_EVENT;
 142         fep->ev_tx = FCC_TX_EVENT;
 143         fep->ev_err = FCC_ERR_EVENT_MSK;
 144
 145         return 0;
 146 }
 147
 148 static int allocate_bd(struct net_device *dev)
 149 {
 150         struct fs_enet_private *fep = netdev_priv(dev);
 151         const struct fs_platform_info *fpi = fep->fpi;
 152
 153         fep->ring_base = (void __iomem __force *)dma_alloc_coherent(fep->dev,
 154                                             (fpi->tx_ring + fpi->rx_ring) *
 155                                             sizeof(cbd_t), &fep->ring_mem_addr,
 156                                             GFP_KERNEL);
 157         if (fep->ring_base == NULL)
 158                 return -ENOMEM;
 159
 160         return 0;
 161 }
 162
 163 static void free_bd(struct net_device *dev)
 164 {
 165         struct fs_enet_private *fep = netdev_priv(dev);
 166         const struct fs_platform_info *fpi = fep->fpi;
 167
 168         if (fep->ring_base)
 169                 dma_free_coherent(fep->dev,
 170                         (fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t),
 171                         (void __force *)fep->ring_base, fep->ring_mem_addr);
 172 }
 173
 174 static void cleanup_data(struct net_device *dev)
 175 {
 176         /* nothing */
 177 }
 178
 179 static void set_promiscuous_mode(struct net_device *dev)
 180 {
 181         struct fs_enet_private *fep = netdev_priv(dev);
 182         fcc_t __iomem *fccp = fep->fcc.fccp;
 183
 184         S32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
 185 }
 186
 187 static void set_multicast_start(struct net_device *dev)
 188 {
 189         struct fs_enet_private *fep = netdev_priv(dev);
 190         fcc_enet_t __iomem *ep = fep->fcc.ep;
 191
 192         W32(ep, fen_gaddrh, 0);
 193         W32(ep, fen_gaddrl, 0);
 194 }
 195
 196 static void set_multicast_one(struct net_device *dev, const u8 *mac)
 197 {
 198         struct fs_enet_private *fep = netdev_priv(dev);
 199         fcc_enet_t __iomem *ep = fep->fcc.ep;
 200         u16 taddrh, taddrm, taddrl;
 201
 202         taddrh = ((u16)mac[5] << 8) | mac[4];
 203         taddrm = ((u16)mac[3] << 8) | mac[2];
 204         taddrl = ((u16)mac[1] << 8) | mac[0];
 205
 206         W16(ep, fen_taddrh, taddrh);
 207         W16(ep, fen_taddrm, taddrm);
 208         W16(ep, fen_taddrl, taddrl);
 209         fcc_cr_cmd(fep, CPM_CR_SET_GADDR);
 210 }
 211
 212 static void set_multicast_finish(struct net_device *dev)
 213 {
 214         struct fs_enet_private *fep = netdev_priv(dev);
 215         fcc_t __iomem *fccp = fep->fcc.fccp;
 216         fcc_enet_t __iomem *ep = fep->fcc.ep;
 217
 218         /* clear promiscuous always */
 219         C32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
 220
 221         /* if all multi or too many multicasts; just enable all */
 222         if ((dev->flags & IFF_ALLMULTI) != 0 ||
 223             netdev_mc_count(dev) > FCC_MAX_MULTICAST_ADDRS) {
 224
 225                 W32(ep, fen_gaddrh, 0xffffffff);
 226                 W32(ep, fen_gaddrl, 0xffffffff);
 227         }
 228
 229         /* read back */
 230         fep->fcc.gaddrh = R32(ep, fen_gaddrh);
 231         fep->fcc.gaddrl = R32(ep, fen_gaddrl);
 232 }
 233
 234 static void set_multicast_list(struct net_device *dev)
 235 {
 236         struct netdev_hw_addr *ha;
 237
 238         if ((dev->flags & IFF_PROMISC) == 0) {
 239                 set_multicast_start(dev);
 240                 netdev_for_each_mc_addr(ha, dev)
 241                         set_multicast_one(dev, ha->addr);
 242                 set_multicast_finish(dev);
 243         } else
 244                 set_promiscuous_mode(dev);
 245 }
 246
 247 static void restart(struct net_device *dev)
 248 {
 249         struct fs_enet_private *fep = netdev_priv(dev);
 250         const struct fs_platform_info *fpi = fep->fpi;
 251         fcc_t __iomem *fccp = fep->fcc.fccp;
 252         fcc_c_t __iomem *fcccp = fep->fcc.fcccp;
 253         fcc_enet_t __iomem *ep = fep->fcc.ep;
 254         dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
 255         u16 paddrh, paddrm, paddrl;
 256         const unsigned char *mac;
 257         int i;
 258
 259         C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
 260
 261         /* clear everything (slow & steady does it) */
 262         for (i = 0; i < sizeof(*ep); i++)
 263                 out_8((u8 __iomem *)ep + i, 0);
 264
 265         /* get physical address */
 266         rx_bd_base_phys = fep->ring_mem_addr;
 267         tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
 268
 269         /* point to bds */
 270         W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys);
 271         W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys);
 272
 273         /* Set maximum bytes per receive buffer.
 274          * It must be a multiple of 32.
 275          */
 276         W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE);
 277
 278         W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
 279         W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
 280
 281         /* Allocate space in the reserved FCC area of DPRAM for the
 282          * internal buffers.  No one uses this space (yet), so we
 283          * can do this.  Later, we will add resource management for
 284          * this area.
 285          */
 286
 287         W16(ep, fen_genfcc.fcc_riptr, fpi->dpram_offset);
 288         W16(ep, fen_genfcc.fcc_tiptr, fpi->dpram_offset + 32);
 289
 290         W16(ep, fen_padptr, fpi->dpram_offset + 64);
 291
 292         /* fill with special symbol...  */
 293         memset_io(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32);
 294
 295         W32(ep, fen_genfcc.fcc_rbptr, 0);
 296         W32(ep, fen_genfcc.fcc_tbptr, 0);
 297         W32(ep, fen_genfcc.fcc_rcrc, 0);
 298         W32(ep, fen_genfcc.fcc_tcrc, 0);
 299         W16(ep, fen_genfcc.fcc_res1, 0);
 300         W32(ep, fen_genfcc.fcc_res2, 0);
 301
 302         /* no CAM */
 303         W32(ep, fen_camptr, 0);
 304
 305         /* Set CRC preset and mask */
 306         W32(ep, fen_cmask, 0xdebb20e3);
 307         W32(ep, fen_cpres, 0xffffffff);
 308
 309         W32(ep, fen_crcec, 0);          /* CRC Error counter       */
 310         W32(ep, fen_alec, 0);           /* alignment error counter */
 311         W32(ep, fen_disfc, 0);          /* discard frame counter   */
 312         W16(ep, fen_retlim, 15);        /* Retry limit threshold   */
 313         W16(ep, fen_pper, 0);           /* Normal persistence      */
 314
 315         /* set group address */
 316         W32(ep, fen_gaddrh, fep->fcc.gaddrh);
 317         W32(ep, fen_gaddrl, fep->fcc.gaddrh);
 318
 319         /* Clear hash filter tables */
 320         W32(ep, fen_iaddrh, 0);
 321         W32(ep, fen_iaddrl, 0);
 322
 323         /* Clear the Out-of-sequence TxBD  */
 324         W16(ep, fen_tfcstat, 0);
 325         W16(ep, fen_tfclen, 0);
 326         W32(ep, fen_tfcptr, 0);
 327
 328         W16(ep, fen_mflr, PKT_MAXBUF_SIZE);     /* maximum frame length register */
 329         W16(ep, fen_minflr, PKT_MINBUF_SIZE);   /* minimum frame length register */
 330
 331         /* set address */
 332         mac = dev->dev_addr;
 333         paddrh = ((u16)mac[5] << 8) | mac[4];
 334         paddrm = ((u16)mac[3] << 8) | mac[2];
 335         paddrl = ((u16)mac[1] << 8) | mac[0];
 336
 337         W16(ep, fen_paddrh, paddrh);
 338         W16(ep, fen_paddrm, paddrm);
 339         W16(ep, fen_paddrl, paddrl);
 340
 341         W16(ep, fen_taddrh, 0);
 342         W16(ep, fen_taddrm, 0);
 343         W16(ep, fen_taddrl, 0);
 344
 345         W16(ep, fen_maxd1, 1520);       /* maximum DMA1 length */
 346         W16(ep, fen_maxd2, 1520);       /* maximum DMA2 length */
 347
 348         /* Clear stat counters, in case we ever enable RMON */
 349         W32(ep, fen_octc, 0);
 350         W32(ep, fen_colc, 0);
 351         W32(ep, fen_broc, 0);
 352         W32(ep, fen_mulc, 0);
 353         W32(ep, fen_uspc, 0);
 354         W32(ep, fen_frgc, 0);
 355         W32(ep, fen_ospc, 0);
 356         W32(ep, fen_jbrc, 0);
 357         W32(ep, fen_p64c, 0);
 358         W32(ep, fen_p65c, 0);
 359         W32(ep, fen_p128c, 0);
 360         W32(ep, fen_p256c, 0);
 361         W32(ep, fen_p512c, 0);
 362         W32(ep, fen_p1024c, 0);
 363
 364         W16(ep, fen_rfthr, 0);  /* Suggested by manual */
 365         W16(ep, fen_rfcnt, 0);
 366         W16(ep, fen_cftype, 0);
 367
 368         fs_init_bds(dev);
 369
 370         /* adjust to speed (for RMII mode) */
 371         if (fpi->use_rmii) {
 372                 if (fep->phydev->speed == 100)
 373                         C8(fcccp, fcc_gfemr, 0x20);
 374                 else
 375                         S8(fcccp, fcc_gfemr, 0x20);
 376         }
 377
 378         fcc_cr_cmd(fep, CPM_CR_INIT_TRX);
 379
 380         /* clear events */
 381         W16(fccp, fcc_fcce, 0xffff);
 382
 383         /* Enable interrupts we wish to service */
 384         W16(fccp, fcc_fccm, FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB);
 385
 386         /* Set GFMR to enable Ethernet operating mode */
 387         W32(fccp, fcc_gfmr, FCC_GFMR_TCI | FCC_GFMR_MODE_ENET);
 388
 389         /* set sync/delimiters */
 390         W16(fccp, fcc_fdsr, 0xd555);
 391
 392         W32(fccp, fcc_fpsmr, FCC_PSMR_ENCRC);
 393
 394         if (fpi->use_rmii)
 395                 S32(fccp, fcc_fpsmr, FCC_PSMR_RMII);
 396
 397         /* adjust to duplex mode */
 398         if (fep->phydev->duplex)
 399                 S32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
 400         else
 401                 C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
 402
 403         /* Restore multicast and promiscuous settings */
 404         set_multicast_list(dev);
 405
 406         S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
 407 }
 408
 409 static void stop(struct net_device *dev)
 410 {
 411         struct fs_enet_private *fep = netdev_priv(dev);
 412         fcc_t __iomem *fccp = fep->fcc.fccp;
 413
 414         /* stop ethernet */
 415         C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
 416
 417         /* clear events */
 418         W16(fccp, fcc_fcce, 0xffff);
 419
 420         /* clear interrupt mask */
 421         W16(fccp, fcc_fccm, 0);
 422
 423         fs_cleanup_bds(dev);
 424 }
 425
 426 static void napi_clear_rx_event(struct net_device *dev)
 427 {
 428         struct fs_enet_private *fep = netdev_priv(dev);
 429         fcc_t __iomem *fccp = fep->fcc.fccp;
 430
 431         W16(fccp, fcc_fcce, FCC_NAPI_RX_EVENT_MSK);
 432 }
 433
 434 static void napi_enable_rx(struct net_device *dev)
 435 {
 436         struct fs_enet_private *fep = netdev_priv(dev);
 437         fcc_t __iomem *fccp = fep->fcc.fccp;
 438
 439         S16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK);
 440 }
 441
 442 static void napi_disable_rx(struct net_device *dev)
 443 {
 444         struct fs_enet_private *fep = netdev_priv(dev);
 445         fcc_t __iomem *fccp = fep->fcc.fccp;
 446
 447         C16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK);
 448 }
 449
 450 static void rx_bd_done(struct net_device *dev)
 451 {
 452         /* nothing */
 453 }
 454
 455 static void tx_kickstart(struct net_device *dev)
 456 {
 457         struct fs_enet_private *fep = netdev_priv(dev);
 458         fcc_t __iomem *fccp = fep->fcc.fccp;
 459
 460         S16(fccp, fcc_ftodr, 0x8000);
 461 }
 462
 463 static u32 get_int_events(struct net_device *dev)
 464 {
 465         struct fs_enet_private *fep = netdev_priv(dev);
 466         fcc_t __iomem *fccp = fep->fcc.fccp;
 467
 468         return (u32)R16(fccp, fcc_fcce);
 469 }
 470
 471 static void clear_int_events(struct net_device *dev, u32 int_events)
 472 {
 473         struct fs_enet_private *fep = netdev_priv(dev);
 474         fcc_t __iomem *fccp = fep->fcc.fccp;
 475
 476         W16(fccp, fcc_fcce, int_events & 0xffff);
 477 }
 478
 479 static void ev_error(struct net_device *dev, u32 int_events)
 480 {
 481         struct fs_enet_private *fep = netdev_priv(dev);
 482
 483         dev_warn(fep->dev, "FS_ENET ERROR(s) 0x%x\n", int_events);
 484 }
 485
 486 static int get_regs(struct net_device *dev, void *p, int *sizep)
 487 {
 488         struct fs_enet_private *fep = netdev_priv(dev);
 489
 490         if (*sizep < sizeof(fcc_t) + sizeof(fcc_enet_t) + 1)
 491                 return -EINVAL;
 492
 493         memcpy_fromio(p, fep->fcc.fccp, sizeof(fcc_t));
 494         p = (char *)p + sizeof(fcc_t);
 495
 496         memcpy_fromio(p, fep->fcc.ep, sizeof(fcc_enet_t));
 497         p = (char *)p + sizeof(fcc_enet_t);
 498
 499         memcpy_fromio(p, fep->fcc.fcccp, 1);
 500         return 0;
 501 }
 502
 503 static int get_regs_len(struct net_device *dev)
 504 {
 505         return sizeof(fcc_t) + sizeof(fcc_enet_t) + 1;
 506 }
 507
 508 /* Some transmit errors cause the transmitter to shut
 509  * down.  We now issue a restart transmit.
 510  * Also, to workaround 8260 device erratum CPM37, we must
 511  * disable and then re-enable the transmitterfollowing a
 512  * Late Collision, Underrun, or Retry Limit error.
 513  * In addition, tbptr may point beyond BDs beyond still marked
 514  * as ready due to internal pipelining, so we need to look back
 515  * through the BDs and adjust tbptr to point to the last BD
 516  * marked as ready.  This may result in some buffers being
 517  * retransmitted.
 518  */
 519 static void tx_restart(struct net_device *dev)
 520 {
 521         struct fs_enet_private *fep = netdev_priv(dev);
 522         fcc_t __iomem *fccp = fep->fcc.fccp;
 523         const struct fs_platform_info *fpi = fep->fpi;
 524         fcc_enet_t __iomem *ep = fep->fcc.ep;
 525         cbd_t __iomem *curr_tbptr;
 526         cbd_t __iomem *recheck_bd;
 527         cbd_t __iomem *prev_bd;
 528         cbd_t __iomem *last_tx_bd;
 529
 530         last_tx_bd = fep->tx_bd_base + (fpi->tx_ring * sizeof(cbd_t));
 531
 532         /* get the current bd held in TBPTR  and scan back from this point */
 533         recheck_bd = curr_tbptr = (cbd_t __iomem *)
 534                 ((R32(ep, fen_genfcc.fcc_tbptr) - fep->ring_mem_addr) +
 535                 fep->ring_base);
 536
 537         prev_bd = (recheck_bd == fep->tx_bd_base) ? last_tx_bd : recheck_bd - 1;
 538
 539         /* Move through the bds in reverse, look for the earliest buffer
 540          * that is not ready.  Adjust TBPTR to the following buffer */
 541         while ((CBDR_SC(prev_bd) & BD_ENET_TX_READY) != 0) {
 542                 /* Go back one buffer */
 543                 recheck_bd = prev_bd;
 544
 545                 /* update the previous buffer */
 546                 prev_bd = (prev_bd == fep->tx_bd_base) ? last_tx_bd : prev_bd - 1;
 547
 548                 /* We should never see all bds marked as ready, check anyway */
 549                 if (recheck_bd == curr_tbptr)
 550                         break;
 551         }
 552         /* Now update the TBPTR and dirty flag to the current buffer */
 553         W32(ep, fen_genfcc.fcc_tbptr,
 554                 (uint) (((void *)recheck_bd - fep->ring_base) +
 555                 fep->ring_mem_addr));
 556         fep->dirty_tx = recheck_bd;
 557
 558         C32(fccp, fcc_gfmr, FCC_GFMR_ENT);
 559         udelay(10);
 560         S32(fccp, fcc_gfmr, FCC_GFMR_ENT);
 561
 562         fcc_cr_cmd(fep, CPM_CR_RESTART_TX);
 563 }
 564
 565 /*************************************************************************/
 566
 567 const struct fs_ops fs_fcc_ops = {
 568         .setup_data             = setup_data,
 569         .cleanup_data           = cleanup_data,
 570         .set_multicast_list     = set_multicast_list,
 571         .restart                = restart,
 572         .stop                   = stop,
 573         .napi_clear_rx_event    = napi_clear_rx_event,
 574         .napi_enable_rx         = napi_enable_rx,
 575         .napi_disable_rx        = napi_disable_rx,
 576         .rx_bd_done             = rx_bd_done,
 577         .tx_kickstart           = tx_kickstart,
 578         .get_int_events         = get_int_events,
 579         .clear_int_events       = clear_int_events,
 580         .ev_error               = ev_error,
 581         .get_regs               = get_regs,
 582         .get_regs_len           = get_regs_len,
 583         .tx_restart             = tx_restart,
 584         .allocate_bd            = allocate_bd,
 585         .free_bd                = free_bd,
 586 };