drivers/net/ethernet/freescale/fsl_pq_mdio.c

   1 /*
   2  * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
   3  * Provides Bus interface for MIIM regs
   4  *
   5  * Author: Andy Fleming <afleming@freescale.com>
   6  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
   7  *
   8  * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
   9  *
  10  * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  *
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/string.h>
  21 #include <linux/errno.h>
  22 #include <linux/slab.h>
  23 #include <linux/init.h>
  24 #include <linux/delay.h>
  25 #include <linux/module.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/mii.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_mdio.h>
  30 #include <linux/of_platform.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/ucc.h>    /* for ucc_set_qe_mux_mii_mng() */
  34
  35 #include "gianfar.h"
  36
  37 #define MIIMIND_BUSY            0x00000001
  38 #define MIIMIND_NOTVALID        0x00000004
  39 #define MIIMCFG_INIT_VALUE      0x00000007
  40 #define MIIMCFG_RESET           0x80000000
  41
  42 #define MII_READ_COMMAND        0x00000001
  43
  44 struct fsl_pq_mdio {
  45         u8 res1[16];
  46         u32 ieventm;    /* MDIO Interrupt event register (for etsec2)*/
  47         u32 imaskm;     /* MDIO Interrupt mask register (for etsec2)*/
  48         u8 res2[4];
  49         u32 emapm;      /* MDIO Event mapping register (for etsec2)*/
  50         u8 res3[1280];
  51         u32 miimcfg;    /* MII management configuration reg */
  52         u32 miimcom;    /* MII management command reg */
  53         u32 miimadd;    /* MII management address reg */
  54         u32 miimcon;    /* MII management control reg */
  55         u32 miimstat;   /* MII management status reg */
  56         u32 miimind;    /* MII management indication reg */
  57         u8 res4[28];
  58         u32 utbipar;    /* TBI phy address reg (only on UCC) */
  59         u8 res5[2728];
  60 } __packed;
  61
  62 /* Number of microseconds to wait for an MII register to respond */
  63 #define MII_TIMEOUT     1000
  64
  65 struct fsl_pq_mdio_priv {
  66         void __iomem *map;
  67         struct fsl_pq_mdio __iomem *regs;
  68 };
  69
  70 /*
  71  * Write value to the PHY at mii_id at register regnum, on the bus attached
  72  * to the local interface, which may be different from the generic mdio bus
  73  * (tied to a single interface), waiting until the write is done before
  74  * returning. This is helpful in programming interfaces like the TBI which
  75  * control interfaces like onchip SERDES and are always tied to the local
  76  * mdio pins, which may not be the same as system mdio bus, used for
  77  * controlling the external PHYs, for example.
  78  */
  79 static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
  80                 u16 value)
  81 {
  82         struct fsl_pq_mdio_priv *priv = bus->priv;
  83         struct fsl_pq_mdio __iomem *regs = priv->regs;
  84         u32 status;
  85
  86         /* Set the PHY address and the register address we want to write */
  87         out_be32(&regs->miimadd, (mii_id << 8) | regnum);
  88
  89         /* Write out the value we want */
  90         out_be32(&regs->miimcon, value);
  91
  92         /* Wait for the transaction to finish */
  93         status = spin_event_timeout(!(in_be32(&regs->miimind) & MIIMIND_BUSY),
  94                                     MII_TIMEOUT, 0);
  95
  96         return status ? 0 : -ETIMEDOUT;
  97 }
  98
  99 /*
 100  * Read the bus for PHY at addr mii_id, register regnum, and return the value.
 101  * Clears miimcom first.
 102  *
 103  * All PHY operation done on the bus attached to the local interface, which
 104  * may be different from the generic mdio bus.  This is helpful in programming
 105  * interfaces like the TBI which, in turn, control interfaces like on-chip
 106  * SERDES and are always tied to the local mdio pins, which may not be the
 107  * same as system mdio bus, used for controlling the external PHYs, for eg.
 108  */
 109 static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
 110 {
 111         struct fsl_pq_mdio_priv *priv = bus->priv;
 112         struct fsl_pq_mdio __iomem *regs = priv->regs;
 113         u32 status;
 114         u16 value;
 115
 116         /* Set the PHY address and the register address we want to read */
 117         out_be32(&regs->miimadd, (mii_id << 8) | regnum);
 118
 119         /* Clear miimcom, and then initiate a read */
 120         out_be32(&regs->miimcom, 0);
 121         out_be32(&regs->miimcom, MII_READ_COMMAND);
 122
 123         /* Wait for the transaction to finish, normally less than 100us */
 124         status = spin_event_timeout(!(in_be32(&regs->miimind) &
 125                                     (MIIMIND_NOTVALID | MIIMIND_BUSY)),
 126                                     MII_TIMEOUT, 0);
 127         if (!status)
 128                 return -ETIMEDOUT;
 129
 130         /* Grab the value of the register from miimstat */
 131         value = in_be32(&regs->miimstat);
 132
 133         return value;
 134 }
 135
 136 /* Reset the MIIM registers, and wait for the bus to free */
 137 static int fsl_pq_mdio_reset(struct mii_bus *bus)
 138 {
 139         struct fsl_pq_mdio_priv *priv = bus->priv;
 140         struct fsl_pq_mdio __iomem *regs = priv->regs;
 141         u32 status;
 142
 143         mutex_lock(&bus->mdio_lock);
 144
 145         /* Reset the management interface */
 146         out_be32(&regs->miimcfg, MIIMCFG_RESET);
 147
 148         /* Setup the MII Mgmt clock speed */
 149         out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);
 150
 151         /* Wait until the bus is free */
 152         status = spin_event_timeout(!(in_be32(&regs->miimind) & MIIMIND_BUSY),
 153                                     MII_TIMEOUT, 0);
 154
 155         mutex_unlock(&bus->mdio_lock);
 156
 157         if (!status) {
 158                 dev_err(&bus->dev, "timeout waiting for MII bus\n");
 159                 return -EBUSY;
 160         }
 161
 162         return 0;
 163 }
 164
 165 static u32 __iomem *get_gfar_tbipa(struct fsl_pq_mdio __iomem *regs, struct device_node *np)
 166 {
 167 #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
 168         struct gfar __iomem *enet_regs;
 169
 170         /*
 171          * This is mildly evil, but so is our hardware for doing this.
 172          * Also, we have to cast back to struct gfar because of
 173          * definition weirdness done in gianfar.h.
 174          */
 175         if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
 176                 of_device_is_compatible(np, "fsl,gianfar-tbi") ||
 177                 of_device_is_compatible(np, "gianfar")) {
 178                 enet_regs = (struct gfar __iomem *)regs;
 179                 return &enet_regs->tbipa;
 180         } else if (of_device_is_compatible(np, "fsl,etsec2-mdio") ||
 181                         of_device_is_compatible(np, "fsl,etsec2-tbi")) {
 182                 return of_iomap(np, 1);
 183         }
 184 #endif
 185         return NULL;
 186 }
 187
 188
 189 static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
 190 {
 191 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
 192         struct device_node *np = NULL;
 193         int err = 0;
 194
 195         for_each_compatible_node(np, NULL, "ucc_geth") {
 196                 struct resource tempres;
 197
 198                 err = of_address_to_resource(np, 0, &tempres);
 199                 if (err)
 200                         continue;
 201
 202                 /* if our mdio regs fall within this UCC regs range */
 203                 if ((start >= tempres.start) && (end <= tempres.end)) {
 204                         /* Find the id of the UCC */
 205                         const u32 *id;
 206
 207                         id = of_get_property(np, "cell-index", NULL);
 208                         if (!id) {
 209                                 id = of_get_property(np, "device-id", NULL);
 210                                 if (!id)
 211                                         continue;
 212                         }
 213
 214                         *ucc_id = *id;
 215
 216                         return 0;
 217                 }
 218         }
 219
 220         if (err)
 221                 return err;
 222         else
 223                 return -EINVAL;
 224 #else
 225         return -ENODEV;
 226 #endif
 227 }
 228
 229 static int fsl_pq_mdio_probe(struct platform_device *pdev)
 230 {
 231         struct device_node *np = pdev->dev.of_node;
 232         struct device_node *tbi;
 233         struct fsl_pq_mdio_priv *priv;
 234         struct fsl_pq_mdio __iomem *regs = NULL;
 235         void __iomem *map;
 236         u32 __iomem *tbipa;
 237         struct mii_bus *new_bus;
 238         int tbiaddr = -1;
 239         const u32 *addrp;
 240         u64 addr = 0, size = 0;
 241         int err;
 242
 243         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 244         if (!priv)
 245                 return -ENOMEM;
 246
 247         new_bus = mdiobus_alloc();
 248         if (!new_bus) {
 249                 err = -ENOMEM;
 250                 goto err_free_priv;
 251         }
 252
 253         new_bus->name = "Freescale PowerQUICC MII Bus",
 254         new_bus->read = &fsl_pq_mdio_read;
 255         new_bus->write = &fsl_pq_mdio_write;
 256         new_bus->reset = &fsl_pq_mdio_reset;
 257         new_bus->priv = priv;
 258
 259         addrp = of_get_address(np, 0, &size, NULL);
 260         if (!addrp) {
 261                 err = -EINVAL;
 262                 goto err_free_bus;
 263         }
 264
 265         /* Set the PHY base address */
 266         addr = of_translate_address(np, addrp);
 267         if (addr == OF_BAD_ADDR) {
 268                 err = -EINVAL;
 269                 goto err_free_bus;
 270         }
 271
 272         snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s@%llx", np->name,
 273                 (unsigned long long)addr);
 274
 275         map = ioremap(addr, size);
 276         if (!map) {
 277                 err = -ENOMEM;
 278                 goto err_free_bus;
 279         }
 280         priv->map = map;
 281
 282         if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
 283                         of_device_is_compatible(np, "fsl,gianfar-tbi") ||
 284                         of_device_is_compatible(np, "fsl,ucc-mdio") ||
 285                         of_device_is_compatible(np, "ucc_geth_phy"))
 286                 map -= offsetof(struct fsl_pq_mdio, miimcfg);
 287         regs = map;
 288         priv->regs = regs;
 289
 290         new_bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
 291
 292         if (NULL == new_bus->irq) {
 293                 err = -ENOMEM;
 294                 goto err_unmap_regs;
 295         }
 296
 297         new_bus->parent = &pdev->dev;
 298         dev_set_drvdata(&pdev->dev, new_bus);
 299
 300         if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
 301                         of_device_is_compatible(np, "fsl,gianfar-tbi") ||
 302                         of_device_is_compatible(np, "fsl,etsec2-mdio") ||
 303                         of_device_is_compatible(np, "fsl,etsec2-tbi") ||
 304                         of_device_is_compatible(np, "gianfar")) {
 305                 tbipa = get_gfar_tbipa(regs, np);
 306                 if (!tbipa) {
 307                         err = -EINVAL;
 308                         goto err_free_irqs;
 309                 }
 310         } else if (of_device_is_compatible(np, "fsl,ucc-mdio") ||
 311                         of_device_is_compatible(np, "ucc_geth_phy")) {
 312                 u32 id;
 313                 static u32 mii_mng_master;
 314
 315                 tbipa = &regs->utbipar;
 316
 317                 if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
 318                         goto err_free_irqs;
 319
 320                 if (!mii_mng_master) {
 321                         mii_mng_master = id;
 322                         ucc_set_qe_mux_mii_mng(id - 1);
 323                 }
 324         } else {
 325                 err = -ENODEV;
 326                 goto err_free_irqs;
 327         }
 328
 329         for_each_child_of_node(np, tbi) {
 330                 if (!strncmp(tbi->type, "tbi-phy", 8))
 331                         break;
 332         }
 333
 334         if (tbi) {
 335                 const u32 *prop = of_get_property(tbi, "reg", NULL);
 336
 337                 if (prop)
 338                         tbiaddr = *prop;
 339
 340                 if (tbiaddr == -1) {
 341                         err = -EBUSY;
 342                         goto err_free_irqs;
 343                 } else {
 344                         out_be32(tbipa, tbiaddr);
 345                 }
 346         }
 347
 348         err = of_mdiobus_register(new_bus, np);
 349         if (err) {
 350                 dev_err(&pdev->dev, "cannot register %s as MDIO bus\n",
 351                         new_bus->name);
 352                 goto err_free_irqs;
 353         }
 354
 355         return 0;
 356
 357 err_free_irqs:
 358         kfree(new_bus->irq);
 359 err_unmap_regs:
 360         iounmap(priv->map);
 361 err_free_bus:
 362         kfree(new_bus);
 363 err_free_priv:
 364         kfree(priv);
 365         return err;
 366 }
 367
 368
 369 static int fsl_pq_mdio_remove(struct platform_device *pdev)
 370 {
 371         struct device *device = &pdev->dev;
 372         struct mii_bus *bus = dev_get_drvdata(device);
 373         struct fsl_pq_mdio_priv *priv = bus->priv;
 374
 375         mdiobus_unregister(bus);
 376
 377         dev_set_drvdata(device, NULL);
 378
 379         iounmap(priv->map);
 380         bus->priv = NULL;
 381         mdiobus_free(bus);
 382         kfree(priv);
 383
 384         return 0;
 385 }
 386
 387 static struct of_device_id fsl_pq_mdio_match[] = {
 388         {
 389                 .type = "mdio",
 390                 .compatible = "ucc_geth_phy",
 391         },
 392         {
 393                 .type = "mdio",
 394                 .compatible = "gianfar",
 395         },
 396         {
 397                 .compatible = "fsl,ucc-mdio",
 398         },
 399         {
 400                 .compatible = "fsl,gianfar-tbi",
 401         },
 402         {
 403                 .compatible = "fsl,gianfar-mdio",
 404         },
 405         {
 406                 .compatible = "fsl,etsec2-tbi",
 407         },
 408         {
 409                 .compatible = "fsl,etsec2-mdio",
 410         },
 411         {},
 412 };
 413 MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
 414
 415 static struct platform_driver fsl_pq_mdio_driver = {
 416         .driver = {
 417                 .name = "fsl-pq_mdio",
 418                 .owner = THIS_MODULE,
 419                 .of_match_table = fsl_pq_mdio_match,
 420         },
 421         .probe = fsl_pq_mdio_probe,
 422         .remove = fsl_pq_mdio_remove,
 423 };
 424
 425 module_platform_driver(fsl_pq_mdio_driver);
 426
 427 MODULE_LICENSE("GPL");