drivers/net/ethernet/freescale/fsl_pq_mdio.c

   1 /*
   2  * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
   3  * Provides Bus interface for MIIM regs
   4  *
   5  * Author: Andy Fleming <afleming@freescale.com>
   6  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
   7  *
   8  * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
   9  *
  10  * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  *
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/string.h>
  21 #include <linux/errno.h>
  22 #include <linux/unistd.h>
  23 #include <linux/slab.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/skbuff.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/mm.h>
  32 #include <linux/module.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/crc32.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/of.h>
  38 #include <linux/of_address.h>
  39 #include <linux/of_mdio.h>
  40 #include <linux/of_platform.h>
  41
  42 #include <asm/io.h>
  43 #include <asm/irq.h>
  44 #include <asm/uaccess.h>
  45 #include <asm/ucc.h>
  46
  47 #include "gianfar.h"
  48
  49 #define MIIMIND_BUSY            0x00000001
  50 #define MIIMIND_NOTVALID        0x00000004
  51 #define MIIMCFG_INIT_VALUE      0x00000007
  52 #define MIIMCFG_RESET           0x80000000
  53
  54 #define MII_READ_COMMAND        0x00000001
  55
  56 struct fsl_pq_mdio {
  57         u8 res1[16];
  58         u32 ieventm;    /* MDIO Interrupt event register (for etsec2)*/
  59         u32 imaskm;     /* MDIO Interrupt mask register (for etsec2)*/
  60         u8 res2[4];
  61         u32 emapm;      /* MDIO Event mapping register (for etsec2)*/
  62         u8 res3[1280];
  63         u32 miimcfg;    /* MII management configuration reg */
  64         u32 miimcom;    /* MII management command reg */
  65         u32 miimadd;    /* MII management address reg */
  66         u32 miimcon;    /* MII management control reg */
  67         u32 miimstat;   /* MII management status reg */
  68         u32 miimind;    /* MII management indication reg */
  69         u8 res4[28];
  70         u32 utbipar;    /* TBI phy address reg (only on UCC) */
  71         u8 res5[2728];
  72 } __packed;
  73
  74 /* Number of microseconds to wait for an MII register to respond */
  75 #define MII_TIMEOUT     1000
  76
  77 struct fsl_pq_mdio_priv {
  78         void __iomem *map;
  79         struct fsl_pq_mdio __iomem *regs;
  80 };
  81
  82 /*
  83  * Write value to the PHY at mii_id at register regnum,
  84  * on the bus attached to the local interface, which may be different from the
  85  * generic mdio bus (tied to a single interface), waiting until the write is
  86  * done before returning. This is helpful in programming interfaces like
  87  * the TBI which control interfaces like onchip SERDES and are always tied to
  88  * the local mdio pins, which may not be the same as system mdio bus, used for
  89  * controlling the external PHYs, for example.
  90  */
  91 static int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
  92                 int regnum, u16 value)
  93 {
  94         u32 status;
  95
  96         /* Set the PHY address and the register address we want to write */
  97         out_be32(&regs->miimadd, (mii_id << 8) | regnum);
  98
  99         /* Write out the value we want */
 100         out_be32(&regs->miimcon, value);
 101
 102         /* Wait for the transaction to finish */
 103         status = spin_event_timeout(!(in_be32(&regs->miimind) & MIIMIND_BUSY),
 104                                     MII_TIMEOUT, 0);
 105
 106         return status ? 0 : -ETIMEDOUT;
 107 }
 108
 109 /*
 110  * Read the bus for PHY at addr mii_id, register regnum, and
 111  * return the value.  Clears miimcom first.  All PHY operation
 112  * done on the bus attached to the local interface,
 113  * which may be different from the generic mdio bus
 114  * This is helpful in programming interfaces like
 115  * the TBI which, in turn, control interfaces like onchip SERDES
 116  * and are always tied to the local mdio pins, which may not be the
 117  * same as system mdio bus, used for controlling the external PHYs, for eg.
 118  */
 119 static int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs,
 120                 int mii_id, int regnum)
 121 {
 122         u16 value;
 123         u32 status;
 124
 125         /* Set the PHY address and the register address we want to read */
 126         out_be32(&regs->miimadd, (mii_id << 8) | regnum);
 127
 128         /* Clear miimcom, and then initiate a read */
 129         out_be32(&regs->miimcom, 0);
 130         out_be32(&regs->miimcom, MII_READ_COMMAND);
 131
 132         /* Wait for the transaction to finish, normally less than 100us */
 133         status = spin_event_timeout(!(in_be32(&regs->miimind) &
 134                                     (MIIMIND_NOTVALID | MIIMIND_BUSY)),
 135                                     MII_TIMEOUT, 0);
 136         if (!status)
 137                 return -ETIMEDOUT;
 138
 139         /* Grab the value of the register from miimstat */
 140         value = in_be32(&regs->miimstat);
 141
 142         return value;
 143 }
 144
 145 static struct fsl_pq_mdio __iomem *fsl_pq_mdio_get_regs(struct mii_bus *bus)
 146 {
 147         struct fsl_pq_mdio_priv *priv = bus->priv;
 148
 149         return priv->regs;
 150 }
 151
 152 /*
 153  * Write value to the PHY at mii_id at register regnum,
 154  * on the bus, waiting until the write is done before returning.
 155  */
 156 static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
 157                 u16 value)
 158 {
 159         struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
 160
 161         /* Write to the local MII regs */
 162         return fsl_pq_local_mdio_write(regs, mii_id, regnum, value);
 163 }
 164
 165 /*
 166  * Read the bus for PHY at addr mii_id, register regnum, and
 167  * return the value.  Clears miimcom first.
 168  */
 169 static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
 170 {
 171         struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
 172
 173         /* Read the local MII regs */
 174         return fsl_pq_local_mdio_read(regs, mii_id, regnum);
 175 }
 176
 177 /* Reset the MIIM registers, and wait for the bus to free */
 178 static int fsl_pq_mdio_reset(struct mii_bus *bus)
 179 {
 180         struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
 181         u32 status;
 182
 183         mutex_lock(&bus->mdio_lock);
 184
 185         /* Reset the management interface */
 186         out_be32(&regs->miimcfg, MIIMCFG_RESET);
 187
 188         /* Setup the MII Mgmt clock speed */
 189         out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);
 190
 191         /* Wait until the bus is free */
 192         status = spin_event_timeout(!(in_be32(&regs->miimind) & MIIMIND_BUSY),
 193                                     MII_TIMEOUT, 0);
 194
 195         mutex_unlock(&bus->mdio_lock);
 196
 197         if (!status) {
 198                 printk(KERN_ERR "%s: The MII Bus is stuck!\n",
 199                                 bus->name);
 200                 return -EBUSY;
 201         }
 202
 203         return 0;
 204 }
 205
 206 static void fsl_pq_mdio_bus_name(char *name, struct device_node *np)
 207 {
 208         const u32 *addr;
 209         u64 taddr = OF_BAD_ADDR;
 210
 211         addr = of_get_address(np, 0, NULL, NULL);
 212         if (addr)
 213                 taddr = of_translate_address(np, addr);
 214
 215         snprintf(name, MII_BUS_ID_SIZE, "%s@%llx", np->name,
 216                 (unsigned long long)taddr);
 217 }
 218
 219
 220 static u32 __iomem *get_gfar_tbipa(struct fsl_pq_mdio __iomem *regs, struct device_node *np)
 221 {
 222 #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
 223         struct gfar __iomem *enet_regs;
 224
 225         /*
 226          * This is mildly evil, but so is our hardware for doing this.
 227          * Also, we have to cast back to struct gfar because of
 228          * definition weirdness done in gianfar.h.
 229          */
 230         if(of_device_is_compatible(np, "fsl,gianfar-mdio") ||
 231                 of_device_is_compatible(np, "fsl,gianfar-tbi") ||
 232                 of_device_is_compatible(np, "gianfar")) {
 233                 enet_regs = (struct gfar __iomem *)regs;
 234                 return &enet_regs->tbipa;
 235         } else if (of_device_is_compatible(np, "fsl,etsec2-mdio") ||
 236                         of_device_is_compatible(np, "fsl,etsec2-tbi")) {
 237                 return of_iomap(np, 1);
 238         }
 239 #endif
 240         return NULL;
 241 }
 242
 243
 244 static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
 245 {
 246 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
 247         struct device_node *np = NULL;
 248         int err = 0;
 249
 250         for_each_compatible_node(np, NULL, "ucc_geth") {
 251                 struct resource tempres;
 252
 253                 err = of_address_to_resource(np, 0, &tempres);
 254                 if (err)
 255                         continue;
 256
 257                 /* if our mdio regs fall within this UCC regs range */
 258                 if ((start >= tempres.start) && (end <= tempres.end)) {
 259                         /* Find the id of the UCC */
 260                         const u32 *id;
 261
 262                         id = of_get_property(np, "cell-index", NULL);
 263                         if (!id) {
 264                                 id = of_get_property(np, "device-id", NULL);
 265                                 if (!id)
 266                                         continue;
 267                         }
 268
 269                         *ucc_id = *id;
 270
 271                         return 0;
 272                 }
 273         }
 274
 275         if (err)
 276                 return err;
 277         else
 278                 return -EINVAL;
 279 #else
 280         return -ENODEV;
 281 #endif
 282 }
 283
 284 static int fsl_pq_mdio_probe(struct platform_device *ofdev)
 285 {
 286         struct device_node *np = ofdev->dev.of_node;
 287         struct device_node *tbi;
 288         struct fsl_pq_mdio_priv *priv;
 289         struct fsl_pq_mdio __iomem *regs = NULL;
 290         void __iomem *map;
 291         u32 __iomem *tbipa;
 292         struct mii_bus *new_bus;
 293         int tbiaddr = -1;
 294         const u32 *addrp;
 295         u64 addr = 0, size = 0;
 296         int err;
 297
 298         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 299         if (!priv)
 300                 return -ENOMEM;
 301
 302         new_bus = mdiobus_alloc();
 303         if (!new_bus) {
 304                 err = -ENOMEM;
 305                 goto err_free_priv;
 306         }
 307
 308         new_bus->name = "Freescale PowerQUICC MII Bus",
 309         new_bus->read = &fsl_pq_mdio_read,
 310         new_bus->write = &fsl_pq_mdio_write,
 311         new_bus->reset = &fsl_pq_mdio_reset,
 312         new_bus->priv = priv;
 313         fsl_pq_mdio_bus_name(new_bus->id, np);
 314
 315         addrp = of_get_address(np, 0, &size, NULL);
 316         if (!addrp) {
 317                 err = -EINVAL;
 318                 goto err_free_bus;
 319         }
 320
 321         /* Set the PHY base address */
 322         addr = of_translate_address(np, addrp);
 323         if (addr == OF_BAD_ADDR) {
 324                 err = -EINVAL;
 325                 goto err_free_bus;
 326         }
 327
 328         map = ioremap(addr, size);
 329         if (!map) {
 330                 err = -ENOMEM;
 331                 goto err_free_bus;
 332         }
 333         priv->map = map;
 334
 335         if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
 336                         of_device_is_compatible(np, "fsl,gianfar-tbi") ||
 337                         of_device_is_compatible(np, "fsl,ucc-mdio") ||
 338                         of_device_is_compatible(np, "ucc_geth_phy"))
 339                 map -= offsetof(struct fsl_pq_mdio, miimcfg);
 340         regs = map;
 341         priv->regs = regs;
 342
 343         new_bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
 344
 345         if (NULL == new_bus->irq) {
 346                 err = -ENOMEM;
 347                 goto err_unmap_regs;
 348         }
 349
 350         new_bus->parent = &ofdev->dev;
 351         dev_set_drvdata(&ofdev->dev, new_bus);
 352
 353         if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
 354                         of_device_is_compatible(np, "fsl,gianfar-tbi") ||
 355                         of_device_is_compatible(np, "fsl,etsec2-mdio") ||
 356                         of_device_is_compatible(np, "fsl,etsec2-tbi") ||
 357                         of_device_is_compatible(np, "gianfar")) {
 358                 tbipa = get_gfar_tbipa(regs, np);
 359                 if (!tbipa) {
 360                         err = -EINVAL;
 361                         goto err_free_irqs;
 362                 }
 363         } else if (of_device_is_compatible(np, "fsl,ucc-mdio") ||
 364                         of_device_is_compatible(np, "ucc_geth_phy")) {
 365                 u32 id;
 366                 static u32 mii_mng_master;
 367
 368                 tbipa = &regs->utbipar;
 369
 370                 if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
 371                         goto err_free_irqs;
 372
 373                 if (!mii_mng_master) {
 374                         mii_mng_master = id;
 375                         ucc_set_qe_mux_mii_mng(id - 1);
 376                 }
 377         } else {
 378                 err = -ENODEV;
 379                 goto err_free_irqs;
 380         }
 381
 382         for_each_child_of_node(np, tbi) {
 383                 if (!strncmp(tbi->type, "tbi-phy", 8))
 384                         break;
 385         }
 386
 387         if (tbi) {
 388                 const u32 *prop = of_get_property(tbi, "reg", NULL);
 389
 390                 if (prop)
 391                         tbiaddr = *prop;
 392
 393                 if (tbiaddr == -1) {
 394                         err = -EBUSY;
 395                         goto err_free_irqs;
 396                 } else {
 397                         out_be32(tbipa, tbiaddr);
 398                 }
 399         }
 400
 401         err = of_mdiobus_register(new_bus, np);
 402         if (err) {
 403                 printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
 404                                 new_bus->name);
 405                 goto err_free_irqs;
 406         }
 407
 408         return 0;
 409
 410 err_free_irqs:
 411         kfree(new_bus->irq);
 412 err_unmap_regs:
 413         iounmap(priv->map);
 414 err_free_bus:
 415         kfree(new_bus);
 416 err_free_priv:
 417         kfree(priv);
 418         return err;
 419 }
 420
 421
 422 static int fsl_pq_mdio_remove(struct platform_device *ofdev)
 423 {
 424         struct device *device = &ofdev->dev;
 425         struct mii_bus *bus = dev_get_drvdata(device);
 426         struct fsl_pq_mdio_priv *priv = bus->priv;
 427
 428         mdiobus_unregister(bus);
 429
 430         dev_set_drvdata(device, NULL);
 431
 432         iounmap(priv->map);
 433         bus->priv = NULL;
 434         mdiobus_free(bus);
 435         kfree(priv);
 436
 437         return 0;
 438 }
 439
 440 static struct of_device_id fsl_pq_mdio_match[] = {
 441         {
 442                 .type = "mdio",
 443                 .compatible = "ucc_geth_phy",
 444         },
 445         {
 446                 .type = "mdio",
 447                 .compatible = "gianfar",
 448         },
 449         {
 450                 .compatible = "fsl,ucc-mdio",
 451         },
 452         {
 453                 .compatible = "fsl,gianfar-tbi",
 454         },
 455         {
 456                 .compatible = "fsl,gianfar-mdio",
 457         },
 458         {
 459                 .compatible = "fsl,etsec2-tbi",
 460         },
 461         {
 462                 .compatible = "fsl,etsec2-mdio",
 463         },
 464         {},
 465 };
 466 MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
 467
 468 static struct platform_driver fsl_pq_mdio_driver = {
 469         .driver = {
 470                 .name = "fsl-pq_mdio",
 471                 .owner = THIS_MODULE,
 472                 .of_match_table = fsl_pq_mdio_match,
 473         },
 474         .probe = fsl_pq_mdio_probe,
 475         .remove = fsl_pq_mdio_remove,
 476 };
 477
 478 module_platform_driver(fsl_pq_mdio_driver);
 479
 480 MODULE_LICENSE("GPL");