drivers/net/ethernet/freescale/fsl_pq_mdio.c

   1 /*
   2  * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
   3  * Provides Bus interface for MIIM regs
   4  *
   5  * Author: Andy Fleming <afleming@freescale.com>
   6  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
   7  *
   8  * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
   9  *
  10  * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  *
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/string.h>
  21 #include <linux/errno.h>
  22 #include <linux/slab.h>
  23 #include <linux/init.h>
  24 #include <linux/delay.h>
  25 #include <linux/module.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/mii.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_mdio.h>
  30 #include <linux/of_platform.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/ucc.h>    /* for ucc_set_qe_mux_mii_mng() */
  34
  35 #include "gianfar.h"
  36
  37 #define MIIMIND_BUSY            0x00000001
  38 #define MIIMIND_NOTVALID        0x00000004
  39 #define MIIMCFG_INIT_VALUE      0x00000007
  40 #define MIIMCFG_RESET           0x80000000
  41
  42 #define MII_READ_COMMAND        0x00000001
  43
  44 struct fsl_pq_mdio {
  45         u8 res1[16];
  46         u32 ieventm;    /* MDIO Interrupt event register (for etsec2)*/
  47         u32 imaskm;     /* MDIO Interrupt mask register (for etsec2)*/
  48         u8 res2[4];
  49         u32 emapm;      /* MDIO Event mapping register (for etsec2)*/
  50         u8 res3[1280];
  51         u32 miimcfg;    /* MII management configuration reg */
  52         u32 miimcom;    /* MII management command reg */
  53         u32 miimadd;    /* MII management address reg */
  54         u32 miimcon;    /* MII management control reg */
  55         u32 miimstat;   /* MII management status reg */
  56         u32 miimind;    /* MII management indication reg */
  57         u8 res4[28];
  58         u32 utbipar;    /* TBI phy address reg (only on UCC) */
  59         u8 res5[2728];
  60 } __packed;
  61
  62 /* Number of microseconds to wait for an MII register to respond */
  63 #define MII_TIMEOUT     1000
  64
  65 struct fsl_pq_mdio_priv {
  66         void __iomem *map;
  67         struct fsl_pq_mdio __iomem *regs;
  68 };
  69
  70 /*
  71  * Write value to the PHY at mii_id at register regnum, on the bus attached
  72  * to the local interface, which may be different from the generic mdio bus
  73  * (tied to a single interface), waiting until the write is done before
  74  * returning. This is helpful in programming interfaces like the TBI which
  75  * control interfaces like onchip SERDES and are always tied to the local
  76  * mdio pins, which may not be the same as system mdio bus, used for
  77  * controlling the external PHYs, for example.
  78  */
  79 static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
  80                 u16 value)
  81 {
  82         struct fsl_pq_mdio_priv *priv = bus->priv;
  83         struct fsl_pq_mdio __iomem *regs = priv->regs;
  84         u32 status;
  85
  86         /* Set the PHY address and the register address we want to write */
  87         out_be32(&regs->miimadd, (mii_id << 8) | regnum);
  88
  89         /* Write out the value we want */
  90         out_be32(&regs->miimcon, value);
  91
  92         /* Wait for the transaction to finish */
  93         status = spin_event_timeout(!(in_be32(&regs->miimind) & MIIMIND_BUSY),
  94                                     MII_TIMEOUT, 0);
  95
  96         return status ? 0 : -ETIMEDOUT;
  97 }
  98
  99 /*
 100  * Read the bus for PHY at addr mii_id, register regnum, and return the value.
 101  * Clears miimcom first.
 102  *
 103  * All PHY operation done on the bus attached to the local interface, which
 104  * may be different from the generic mdio bus.  This is helpful in programming
 105  * interfaces like the TBI which, in turn, control interfaces like on-chip
 106  * SERDES and are always tied to the local mdio pins, which may not be the
 107  * same as system mdio bus, used for controlling the external PHYs, for eg.
 108  */
 109 static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
 110 {
 111         struct fsl_pq_mdio_priv *priv = bus->priv;
 112         struct fsl_pq_mdio __iomem *regs = priv->regs;
 113         u32 status;
 114         u16 value;
 115
 116         /* Set the PHY address and the register address we want to read */
 117         out_be32(&regs->miimadd, (mii_id << 8) | regnum);
 118
 119         /* Clear miimcom, and then initiate a read */
 120         out_be32(&regs->miimcom, 0);
 121         out_be32(&regs->miimcom, MII_READ_COMMAND);
 122
 123         /* Wait for the transaction to finish, normally less than 100us */
 124         status = spin_event_timeout(!(in_be32(&regs->miimind) &
 125                                     (MIIMIND_NOTVALID | MIIMIND_BUSY)),
 126                                     MII_TIMEOUT, 0);
 127         if (!status)
 128                 return -ETIMEDOUT;
 129
 130         /* Grab the value of the register from miimstat */
 131         value = in_be32(&regs->miimstat);
 132
 133         return value;
 134 }
 135
 136 /* Reset the MIIM registers, and wait for the bus to free */
 137 static int fsl_pq_mdio_reset(struct mii_bus *bus)
 138 {
 139         struct fsl_pq_mdio_priv *priv = bus->priv;
 140         struct fsl_pq_mdio __iomem *regs = priv->regs;
 141         u32 status;
 142
 143         mutex_lock(&bus->mdio_lock);
 144
 145         /* Reset the management interface */
 146         out_be32(&regs->miimcfg, MIIMCFG_RESET);
 147
 148         /* Setup the MII Mgmt clock speed */
 149         out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);
 150
 151         /* Wait until the bus is free */
 152         status = spin_event_timeout(!(in_be32(&regs->miimind) & MIIMIND_BUSY),
 153                                     MII_TIMEOUT, 0);
 154
 155         mutex_unlock(&bus->mdio_lock);
 156
 157         if (!status) {
 158                 printk(KERN_ERR "%s: The MII Bus is stuck!\n",
 159                                 bus->name);
 160                 return -EBUSY;
 161         }
 162
 163         return 0;
 164 }
 165
 166 static u32 __iomem *get_gfar_tbipa(struct fsl_pq_mdio __iomem *regs, struct device_node *np)
 167 {
 168 #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
 169         struct gfar __iomem *enet_regs;
 170
 171         /*
 172          * This is mildly evil, but so is our hardware for doing this.
 173          * Also, we have to cast back to struct gfar because of
 174          * definition weirdness done in gianfar.h.
 175          */
 176         if(of_device_is_compatible(np, "fsl,gianfar-mdio") ||
 177                 of_device_is_compatible(np, "fsl,gianfar-tbi") ||
 178                 of_device_is_compatible(np, "gianfar")) {
 179                 enet_regs = (struct gfar __iomem *)regs;
 180                 return &enet_regs->tbipa;
 181         } else if (of_device_is_compatible(np, "fsl,etsec2-mdio") ||
 182                         of_device_is_compatible(np, "fsl,etsec2-tbi")) {
 183                 return of_iomap(np, 1);
 184         }
 185 #endif
 186         return NULL;
 187 }
 188
 189
 190 static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
 191 {
 192 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
 193         struct device_node *np = NULL;
 194         int err = 0;
 195
 196         for_each_compatible_node(np, NULL, "ucc_geth") {
 197                 struct resource tempres;
 198
 199                 err = of_address_to_resource(np, 0, &tempres);
 200                 if (err)
 201                         continue;
 202
 203                 /* if our mdio regs fall within this UCC regs range */
 204                 if ((start >= tempres.start) && (end <= tempres.end)) {
 205                         /* Find the id of the UCC */
 206                         const u32 *id;
 207
 208                         id = of_get_property(np, "cell-index", NULL);
 209                         if (!id) {
 210                                 id = of_get_property(np, "device-id", NULL);
 211                                 if (!id)
 212                                         continue;
 213                         }
 214
 215                         *ucc_id = *id;
 216
 217                         return 0;
 218                 }
 219         }
 220
 221         if (err)
 222                 return err;
 223         else
 224                 return -EINVAL;
 225 #else
 226         return -ENODEV;
 227 #endif
 228 }
 229
 230 static int fsl_pq_mdio_probe(struct platform_device *ofdev)
 231 {
 232         struct device_node *np = ofdev->dev.of_node;
 233         struct device_node *tbi;
 234         struct fsl_pq_mdio_priv *priv;
 235         struct fsl_pq_mdio __iomem *regs = NULL;
 236         void __iomem *map;
 237         u32 __iomem *tbipa;
 238         struct mii_bus *new_bus;
 239         int tbiaddr = -1;
 240         const u32 *addrp;
 241         u64 addr = 0, size = 0;
 242         int err;
 243
 244         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 245         if (!priv)
 246                 return -ENOMEM;
 247
 248         new_bus = mdiobus_alloc();
 249         if (!new_bus) {
 250                 err = -ENOMEM;
 251                 goto err_free_priv;
 252         }
 253
 254         new_bus->name = "Freescale PowerQUICC MII Bus",
 255         new_bus->read = &fsl_pq_mdio_read,
 256         new_bus->write = &fsl_pq_mdio_write,
 257         new_bus->reset = &fsl_pq_mdio_reset,
 258         new_bus->priv = priv;
 259
 260         addrp = of_get_address(np, 0, &size, NULL);
 261         if (!addrp) {
 262                 err = -EINVAL;
 263                 goto err_free_bus;
 264         }
 265
 266         /* Set the PHY base address */
 267         addr = of_translate_address(np, addrp);
 268         if (addr == OF_BAD_ADDR) {
 269                 err = -EINVAL;
 270                 goto err_free_bus;
 271         }
 272
 273         snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s@%llx", np->name,
 274                 (unsigned long long)addr);
 275
 276         map = ioremap(addr, size);
 277         if (!map) {
 278                 err = -ENOMEM;
 279                 goto err_free_bus;
 280         }
 281         priv->map = map;
 282
 283         if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
 284                         of_device_is_compatible(np, "fsl,gianfar-tbi") ||
 285                         of_device_is_compatible(np, "fsl,ucc-mdio") ||
 286                         of_device_is_compatible(np, "ucc_geth_phy"))
 287                 map -= offsetof(struct fsl_pq_mdio, miimcfg);
 288         regs = map;
 289         priv->regs = regs;
 290
 291         new_bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
 292
 293         if (NULL == new_bus->irq) {
 294                 err = -ENOMEM;
 295                 goto err_unmap_regs;
 296         }
 297
 298         new_bus->parent = &ofdev->dev;
 299         dev_set_drvdata(&ofdev->dev, new_bus);
 300
 301         if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
 302                         of_device_is_compatible(np, "fsl,gianfar-tbi") ||
 303                         of_device_is_compatible(np, "fsl,etsec2-mdio") ||
 304                         of_device_is_compatible(np, "fsl,etsec2-tbi") ||
 305                         of_device_is_compatible(np, "gianfar")) {
 306                 tbipa = get_gfar_tbipa(regs, np);
 307                 if (!tbipa) {
 308                         err = -EINVAL;
 309                         goto err_free_irqs;
 310                 }
 311         } else if (of_device_is_compatible(np, "fsl,ucc-mdio") ||
 312                         of_device_is_compatible(np, "ucc_geth_phy")) {
 313                 u32 id;
 314                 static u32 mii_mng_master;
 315
 316                 tbipa = &regs->utbipar;
 317
 318                 if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
 319                         goto err_free_irqs;
 320
 321                 if (!mii_mng_master) {
 322                         mii_mng_master = id;
 323                         ucc_set_qe_mux_mii_mng(id - 1);
 324                 }
 325         } else {
 326                 err = -ENODEV;
 327                 goto err_free_irqs;
 328         }
 329
 330         for_each_child_of_node(np, tbi) {
 331                 if (!strncmp(tbi->type, "tbi-phy", 8))
 332                         break;
 333         }
 334
 335         if (tbi) {
 336                 const u32 *prop = of_get_property(tbi, "reg", NULL);
 337
 338                 if (prop)
 339                         tbiaddr = *prop;
 340
 341                 if (tbiaddr == -1) {
 342                         err = -EBUSY;
 343                         goto err_free_irqs;
 344                 } else {
 345                         out_be32(tbipa, tbiaddr);
 346                 }
 347         }
 348
 349         err = of_mdiobus_register(new_bus, np);
 350         if (err) {
 351                 printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
 352                                 new_bus->name);
 353                 goto err_free_irqs;
 354         }
 355
 356         return 0;
 357
 358 err_free_irqs:
 359         kfree(new_bus->irq);
 360 err_unmap_regs:
 361         iounmap(priv->map);
 362 err_free_bus:
 363         kfree(new_bus);
 364 err_free_priv:
 365         kfree(priv);
 366         return err;
 367 }
 368
 369
 370 static int fsl_pq_mdio_remove(struct platform_device *ofdev)
 371 {
 372         struct device *device = &ofdev->dev;
 373         struct mii_bus *bus = dev_get_drvdata(device);
 374         struct fsl_pq_mdio_priv *priv = bus->priv;
 375
 376         mdiobus_unregister(bus);
 377
 378         dev_set_drvdata(device, NULL);
 379
 380         iounmap(priv->map);
 381         bus->priv = NULL;
 382         mdiobus_free(bus);
 383         kfree(priv);
 384
 385         return 0;
 386 }
 387
 388 static struct of_device_id fsl_pq_mdio_match[] = {
 389         {
 390                 .type = "mdio",
 391                 .compatible = "ucc_geth_phy",
 392         },
 393         {
 394                 .type = "mdio",
 395                 .compatible = "gianfar",
 396         },
 397         {
 398                 .compatible = "fsl,ucc-mdio",
 399         },
 400         {
 401                 .compatible = "fsl,gianfar-tbi",
 402         },
 403         {
 404                 .compatible = "fsl,gianfar-mdio",
 405         },
 406         {
 407                 .compatible = "fsl,etsec2-tbi",
 408         },
 409         {
 410                 .compatible = "fsl,etsec2-mdio",
 411         },
 412         {},
 413 };
 414 MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
 415
 416 static struct platform_driver fsl_pq_mdio_driver = {
 417         .driver = {
 418                 .name = "fsl-pq_mdio",
 419                 .owner = THIS_MODULE,
 420                 .of_match_table = fsl_pq_mdio_match,
 421         },
 422         .probe = fsl_pq_mdio_probe,
 423         .remove = fsl_pq_mdio_remove,
 424 };
 425
 426 module_platform_driver(fsl_pq_mdio_driver);
 427
 428 MODULE_LICENSE("GPL");