1 /* drivers/net/ethernet/freescale/gianfar.c
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
81 #include <linux/of_mdio.h>
82 #include <linux/of_platform.h>
84 #include <linux/tcp.h>
85 #include <linux/udp.h>
87 #include <linux/net_tstamp.h>
92 #include <asm/uaccess.h>
93 #include <linux/module.h>
94 #include <linux/dma-mapping.h>
95 #include <linux/crc32.h>
96 #include <linux/mii.h>
97 #include <linux/phy.h>
98 #include <linux/phy_fixed.h>
100 #include <linux/of_net.h>
104 #define TX_TIMEOUT (1*HZ)
106 const char gfar_driver_version
[] = "1.3";
108 static int gfar_enet_open(struct net_device
*dev
);
109 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
110 static void gfar_reset_task(struct work_struct
*work
);
111 static void gfar_timeout(struct net_device
*dev
);
112 static int gfar_close(struct net_device
*dev
);
113 struct sk_buff
*gfar_new_skb(struct net_device
*dev
);
114 static void gfar_new_rxbdp(struct gfar_priv_rx_q
*rx_queue
, struct rxbd8
*bdp
,
115 struct sk_buff
*skb
);
116 static int gfar_set_mac_address(struct net_device
*dev
);
117 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
118 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
119 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
120 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
121 static void adjust_link(struct net_device
*dev
);
122 static void init_registers(struct net_device
*dev
);
123 static int init_phy(struct net_device
*dev
);
124 static int gfar_probe(struct platform_device
*ofdev
);
125 static int gfar_remove(struct platform_device
*ofdev
);
126 static void free_skb_resources(struct gfar_private
*priv
);
127 static void gfar_set_multi(struct net_device
*dev
);
128 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
129 static void gfar_configure_serdes(struct net_device
*dev
);
130 static int gfar_poll(struct napi_struct
*napi
, int budget
);
131 static int gfar_poll_sq(struct napi_struct
*napi
, int budget
);
132 #ifdef CONFIG_NET_POLL_CONTROLLER
133 static void gfar_netpoll(struct net_device
*dev
);
135 int gfar_clean_rx_ring(struct gfar_priv_rx_q
*rx_queue
, int rx_work_limit
);
136 static void gfar_clean_tx_ring(struct gfar_priv_tx_q
*tx_queue
);
137 static void gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
138 int amount_pull
, struct napi_struct
*napi
);
139 void gfar_halt(struct net_device
*dev
);
140 static void gfar_halt_nodisable(struct net_device
*dev
);
141 void gfar_start(struct net_device
*dev
);
142 static void gfar_clear_exact_match(struct net_device
*dev
);
143 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
,
145 static int gfar_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
);
147 MODULE_AUTHOR("Freescale Semiconductor, Inc");
148 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
149 MODULE_LICENSE("GPL");
151 static void gfar_init_rxbdp(struct gfar_priv_rx_q
*rx_queue
, struct rxbd8
*bdp
,
158 lstatus
= BD_LFLAG(RXBD_EMPTY
| RXBD_INTERRUPT
);
159 if (bdp
== rx_queue
->rx_bd_base
+ rx_queue
->rx_ring_size
- 1)
160 lstatus
|= BD_LFLAG(RXBD_WRAP
);
164 bdp
->lstatus
= lstatus
;
167 static int gfar_init_bds(struct net_device
*ndev
)
169 struct gfar_private
*priv
= netdev_priv(ndev
);
170 struct gfar_priv_tx_q
*tx_queue
= NULL
;
171 struct gfar_priv_rx_q
*rx_queue
= NULL
;
176 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
177 tx_queue
= priv
->tx_queue
[i
];
178 /* Initialize some variables in our dev structure */
179 tx_queue
->num_txbdfree
= tx_queue
->tx_ring_size
;
180 tx_queue
->dirty_tx
= tx_queue
->tx_bd_base
;
181 tx_queue
->cur_tx
= tx_queue
->tx_bd_base
;
182 tx_queue
->skb_curtx
= 0;
183 tx_queue
->skb_dirtytx
= 0;
185 /* Initialize Transmit Descriptor Ring */
186 txbdp
= tx_queue
->tx_bd_base
;
187 for (j
= 0; j
< tx_queue
->tx_ring_size
; j
++) {
193 /* Set the last descriptor in the ring to indicate wrap */
195 txbdp
->status
|= TXBD_WRAP
;
198 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
199 rx_queue
= priv
->rx_queue
[i
];
200 rx_queue
->cur_rx
= rx_queue
->rx_bd_base
;
201 rx_queue
->skb_currx
= 0;
202 rxbdp
= rx_queue
->rx_bd_base
;
204 for (j
= 0; j
< rx_queue
->rx_ring_size
; j
++) {
205 struct sk_buff
*skb
= rx_queue
->rx_skbuff
[j
];
208 gfar_init_rxbdp(rx_queue
, rxbdp
,
211 skb
= gfar_new_skb(ndev
);
213 netdev_err(ndev
, "Can't allocate RX buffers\n");
216 rx_queue
->rx_skbuff
[j
] = skb
;
218 gfar_new_rxbdp(rx_queue
, rxbdp
, skb
);
229 static int gfar_alloc_skb_resources(struct net_device
*ndev
)
234 struct gfar_private
*priv
= netdev_priv(ndev
);
235 struct device
*dev
= priv
->dev
;
236 struct gfar_priv_tx_q
*tx_queue
= NULL
;
237 struct gfar_priv_rx_q
*rx_queue
= NULL
;
239 priv
->total_tx_ring_size
= 0;
240 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
241 priv
->total_tx_ring_size
+= priv
->tx_queue
[i
]->tx_ring_size
;
243 priv
->total_rx_ring_size
= 0;
244 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
245 priv
->total_rx_ring_size
+= priv
->rx_queue
[i
]->rx_ring_size
;
247 /* Allocate memory for the buffer descriptors */
248 vaddr
= dma_alloc_coherent(dev
,
249 (priv
->total_tx_ring_size
*
250 sizeof(struct txbd8
)) +
251 (priv
->total_rx_ring_size
*
252 sizeof(struct rxbd8
)),
257 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
258 tx_queue
= priv
->tx_queue
[i
];
259 tx_queue
->tx_bd_base
= vaddr
;
260 tx_queue
->tx_bd_dma_base
= addr
;
261 tx_queue
->dev
= ndev
;
262 /* enet DMA only understands physical addresses */
263 addr
+= sizeof(struct txbd8
) * tx_queue
->tx_ring_size
;
264 vaddr
+= sizeof(struct txbd8
) * tx_queue
->tx_ring_size
;
267 /* Start the rx descriptor ring where the tx ring leaves off */
268 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
269 rx_queue
= priv
->rx_queue
[i
];
270 rx_queue
->rx_bd_base
= vaddr
;
271 rx_queue
->rx_bd_dma_base
= addr
;
272 rx_queue
->dev
= ndev
;
273 addr
+= sizeof(struct rxbd8
) * rx_queue
->rx_ring_size
;
274 vaddr
+= sizeof(struct rxbd8
) * rx_queue
->rx_ring_size
;
277 /* Setup the skbuff rings */
278 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
279 tx_queue
= priv
->tx_queue
[i
];
280 tx_queue
->tx_skbuff
=
281 kmalloc_array(tx_queue
->tx_ring_size
,
282 sizeof(*tx_queue
->tx_skbuff
),
284 if (!tx_queue
->tx_skbuff
)
287 for (k
= 0; k
< tx_queue
->tx_ring_size
; k
++)
288 tx_queue
->tx_skbuff
[k
] = NULL
;
291 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
292 rx_queue
= priv
->rx_queue
[i
];
293 rx_queue
->rx_skbuff
=
294 kmalloc_array(rx_queue
->rx_ring_size
,
295 sizeof(*rx_queue
->rx_skbuff
),
297 if (!rx_queue
->rx_skbuff
)
300 for (j
= 0; j
< rx_queue
->rx_ring_size
; j
++)
301 rx_queue
->rx_skbuff
[j
] = NULL
;
304 if (gfar_init_bds(ndev
))
310 free_skb_resources(priv
);
314 static void gfar_init_tx_rx_base(struct gfar_private
*priv
)
316 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
320 baddr
= ®s
->tbase0
;
321 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
322 gfar_write(baddr
, priv
->tx_queue
[i
]->tx_bd_dma_base
);
326 baddr
= ®s
->rbase0
;
327 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
328 gfar_write(baddr
, priv
->rx_queue
[i
]->rx_bd_dma_base
);
333 static void gfar_init_mac(struct net_device
*ndev
)
335 struct gfar_private
*priv
= netdev_priv(ndev
);
336 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
341 /* write the tx/rx base registers */
342 gfar_init_tx_rx_base(priv
);
344 /* Configure the coalescing support */
345 gfar_configure_coalescing_all(priv
);
347 /* set this when rx hw offload (TOE) functions are being used */
348 priv
->uses_rxfcb
= 0;
350 if (priv
->rx_filer_enable
) {
351 rctrl
|= RCTRL_FILREN
;
352 /* Program the RIR0 reg with the required distribution */
353 gfar_write(®s
->rir0
, DEFAULT_RIR0
);
356 /* Restore PROMISC mode */
357 if (ndev
->flags
& IFF_PROMISC
)
360 if (ndev
->features
& NETIF_F_RXCSUM
) {
361 rctrl
|= RCTRL_CHECKSUMMING
;
362 priv
->uses_rxfcb
= 1;
365 if (priv
->extended_hash
) {
366 rctrl
|= RCTRL_EXTHASH
;
368 gfar_clear_exact_match(ndev
);
373 rctrl
&= ~RCTRL_PAL_MASK
;
374 rctrl
|= RCTRL_PADDING(priv
->padding
);
377 /* Insert receive time stamps into padding alignment bytes */
378 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
) {
379 rctrl
&= ~RCTRL_PAL_MASK
;
380 rctrl
|= RCTRL_PADDING(8);
384 /* Enable HW time stamping if requested from user space */
385 if (priv
->hwts_rx_en
) {
386 rctrl
|= RCTRL_PRSDEP_INIT
| RCTRL_TS_ENABLE
;
387 priv
->uses_rxfcb
= 1;
390 if (ndev
->features
& NETIF_F_HW_VLAN_CTAG_RX
) {
391 rctrl
|= RCTRL_VLEX
| RCTRL_PRSDEP_INIT
;
392 priv
->uses_rxfcb
= 1;
395 /* Init rctrl based on our settings */
396 gfar_write(®s
->rctrl
, rctrl
);
398 if (ndev
->features
& NETIF_F_IP_CSUM
)
399 tctrl
|= TCTRL_INIT_CSUM
;
401 if (priv
->prio_sched_en
)
402 tctrl
|= TCTRL_TXSCHED_PRIO
;
404 tctrl
|= TCTRL_TXSCHED_WRRS
;
405 gfar_write(®s
->tr03wt
, DEFAULT_WRRS_WEIGHT
);
406 gfar_write(®s
->tr47wt
, DEFAULT_WRRS_WEIGHT
);
409 gfar_write(®s
->tctrl
, tctrl
);
411 /* Set the extraction length and index */
412 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
413 ATTRELI_EI(priv
->rx_stash_index
);
415 gfar_write(®s
->attreli
, attrs
);
417 /* Start with defaults, and add stashing or locking
418 * depending on the approprate variables
420 attrs
= ATTR_INIT_SETTINGS
;
422 if (priv
->bd_stash_en
)
423 attrs
|= ATTR_BDSTASH
;
425 if (priv
->rx_stash_size
!= 0)
426 attrs
|= ATTR_BUFSTASH
;
428 gfar_write(®s
->attr
, attrs
);
430 gfar_write(®s
->fifo_tx_thr
, priv
->fifo_threshold
);
431 gfar_write(®s
->fifo_tx_starve
, priv
->fifo_starve
);
432 gfar_write(®s
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
435 static struct net_device_stats
*gfar_get_stats(struct net_device
*dev
)
437 struct gfar_private
*priv
= netdev_priv(dev
);
438 unsigned long rx_packets
= 0, rx_bytes
= 0, rx_dropped
= 0;
439 unsigned long tx_packets
= 0, tx_bytes
= 0;
442 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
443 rx_packets
+= priv
->rx_queue
[i
]->stats
.rx_packets
;
444 rx_bytes
+= priv
->rx_queue
[i
]->stats
.rx_bytes
;
445 rx_dropped
+= priv
->rx_queue
[i
]->stats
.rx_dropped
;
448 dev
->stats
.rx_packets
= rx_packets
;
449 dev
->stats
.rx_bytes
= rx_bytes
;
450 dev
->stats
.rx_dropped
= rx_dropped
;
452 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
453 tx_bytes
+= priv
->tx_queue
[i
]->stats
.tx_bytes
;
454 tx_packets
+= priv
->tx_queue
[i
]->stats
.tx_packets
;
457 dev
->stats
.tx_bytes
= tx_bytes
;
458 dev
->stats
.tx_packets
= tx_packets
;
463 static const struct net_device_ops gfar_netdev_ops
= {
464 .ndo_open
= gfar_enet_open
,
465 .ndo_start_xmit
= gfar_start_xmit
,
466 .ndo_stop
= gfar_close
,
467 .ndo_change_mtu
= gfar_change_mtu
,
468 .ndo_set_features
= gfar_set_features
,
469 .ndo_set_rx_mode
= gfar_set_multi
,
470 .ndo_tx_timeout
= gfar_timeout
,
471 .ndo_do_ioctl
= gfar_ioctl
,
472 .ndo_get_stats
= gfar_get_stats
,
473 .ndo_set_mac_address
= eth_mac_addr
,
474 .ndo_validate_addr
= eth_validate_addr
,
475 #ifdef CONFIG_NET_POLL_CONTROLLER
476 .ndo_poll_controller
= gfar_netpoll
,
480 void lock_rx_qs(struct gfar_private
*priv
)
484 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
485 spin_lock(&priv
->rx_queue
[i
]->rxlock
);
488 void lock_tx_qs(struct gfar_private
*priv
)
492 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
493 spin_lock(&priv
->tx_queue
[i
]->txlock
);
496 void unlock_rx_qs(struct gfar_private
*priv
)
500 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
501 spin_unlock(&priv
->rx_queue
[i
]->rxlock
);
504 void unlock_tx_qs(struct gfar_private
*priv
)
508 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
509 spin_unlock(&priv
->tx_queue
[i
]->txlock
);
512 static void free_tx_pointers(struct gfar_private
*priv
)
516 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
517 kfree(priv
->tx_queue
[i
]);
520 static void free_rx_pointers(struct gfar_private
*priv
)
524 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
525 kfree(priv
->rx_queue
[i
]);
528 static void unmap_group_regs(struct gfar_private
*priv
)
532 for (i
= 0; i
< MAXGROUPS
; i
++)
533 if (priv
->gfargrp
[i
].regs
)
534 iounmap(priv
->gfargrp
[i
].regs
);
537 static void free_gfar_dev(struct gfar_private
*priv
)
541 for (i
= 0; i
< priv
->num_grps
; i
++)
542 for (j
= 0; j
< GFAR_NUM_IRQS
; j
++) {
543 kfree(priv
->gfargrp
[i
].irqinfo
[j
]);
544 priv
->gfargrp
[i
].irqinfo
[j
] = NULL
;
547 free_netdev(priv
->ndev
);
550 static void disable_napi(struct gfar_private
*priv
)
554 for (i
= 0; i
< priv
->num_grps
; i
++)
555 napi_disable(&priv
->gfargrp
[i
].napi
);
558 static void enable_napi(struct gfar_private
*priv
)
562 for (i
= 0; i
< priv
->num_grps
; i
++)
563 napi_enable(&priv
->gfargrp
[i
].napi
);
566 static int gfar_parse_group(struct device_node
*np
,
567 struct gfar_private
*priv
, const char *model
)
569 struct gfar_priv_grp
*grp
= &priv
->gfargrp
[priv
->num_grps
];
573 for (i
= 0; i
< GFAR_NUM_IRQS
; i
++) {
574 grp
->irqinfo
[i
] = kzalloc(sizeof(struct gfar_irqinfo
),
576 if (!grp
->irqinfo
[i
])
580 grp
->regs
= of_iomap(np
, 0);
584 gfar_irq(grp
, TX
)->irq
= irq_of_parse_and_map(np
, 0);
586 /* If we aren't the FEC we have multiple interrupts */
587 if (model
&& strcasecmp(model
, "FEC")) {
588 gfar_irq(grp
, RX
)->irq
= irq_of_parse_and_map(np
, 1);
589 gfar_irq(grp
, ER
)->irq
= irq_of_parse_and_map(np
, 2);
590 if (gfar_irq(grp
, TX
)->irq
== NO_IRQ
||
591 gfar_irq(grp
, RX
)->irq
== NO_IRQ
||
592 gfar_irq(grp
, ER
)->irq
== NO_IRQ
)
597 spin_lock_init(&grp
->grplock
);
598 if (priv
->mode
== MQ_MG_MODE
) {
599 queue_mask
= (u32
*)of_get_property(np
, "fsl,rx-bit-map", NULL
);
600 grp
->rx_bit_map
= queue_mask
?
601 *queue_mask
: (DEFAULT_MAPPING
>> priv
->num_grps
);
602 queue_mask
= (u32
*)of_get_property(np
, "fsl,tx-bit-map", NULL
);
603 grp
->tx_bit_map
= queue_mask
?
604 *queue_mask
: (DEFAULT_MAPPING
>> priv
->num_grps
);
606 grp
->rx_bit_map
= 0xFF;
607 grp
->tx_bit_map
= 0xFF;
614 static int gfar_of_init(struct platform_device
*ofdev
, struct net_device
**pdev
)
618 const void *mac_addr
;
620 struct net_device
*dev
= NULL
;
621 struct gfar_private
*priv
= NULL
;
622 struct device_node
*np
= ofdev
->dev
.of_node
;
623 struct device_node
*child
= NULL
;
625 const u32
*stash_len
;
626 const u32
*stash_idx
;
627 unsigned int num_tx_qs
, num_rx_qs
;
628 u32
*tx_queues
, *rx_queues
;
630 if (!np
|| !of_device_is_available(np
))
633 /* parse the num of tx and rx queues */
634 tx_queues
= (u32
*)of_get_property(np
, "fsl,num_tx_queues", NULL
);
635 num_tx_qs
= tx_queues
? *tx_queues
: 1;
637 if (num_tx_qs
> MAX_TX_QS
) {
638 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
639 num_tx_qs
, MAX_TX_QS
);
640 pr_err("Cannot do alloc_etherdev, aborting\n");
644 rx_queues
= (u32
*)of_get_property(np
, "fsl,num_rx_queues", NULL
);
645 num_rx_qs
= rx_queues
? *rx_queues
: 1;
647 if (num_rx_qs
> MAX_RX_QS
) {
648 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
649 num_rx_qs
, MAX_RX_QS
);
650 pr_err("Cannot do alloc_etherdev, aborting\n");
654 *pdev
= alloc_etherdev_mq(sizeof(*priv
), num_tx_qs
);
659 priv
= netdev_priv(dev
);
662 priv
->num_tx_queues
= num_tx_qs
;
663 netif_set_real_num_rx_queues(dev
, num_rx_qs
);
664 priv
->num_rx_queues
= num_rx_qs
;
665 priv
->num_grps
= 0x0;
667 /* Init Rx queue filer rule set linked list */
668 INIT_LIST_HEAD(&priv
->rx_list
.list
);
669 priv
->rx_list
.count
= 0;
670 mutex_init(&priv
->rx_queue_access
);
672 model
= of_get_property(np
, "model", NULL
);
674 for (i
= 0; i
< MAXGROUPS
; i
++)
675 priv
->gfargrp
[i
].regs
= NULL
;
677 /* Parse and initialize group specific information */
678 if (of_device_is_compatible(np
, "fsl,etsec2")) {
679 priv
->mode
= MQ_MG_MODE
;
680 for_each_child_of_node(np
, child
) {
681 err
= gfar_parse_group(child
, priv
, model
);
686 priv
->mode
= SQ_SG_MODE
;
687 err
= gfar_parse_group(np
, priv
, model
);
692 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
693 priv
->tx_queue
[i
] = NULL
;
694 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
695 priv
->rx_queue
[i
] = NULL
;
697 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
698 priv
->tx_queue
[i
] = kzalloc(sizeof(struct gfar_priv_tx_q
),
700 if (!priv
->tx_queue
[i
]) {
702 goto tx_alloc_failed
;
704 priv
->tx_queue
[i
]->tx_skbuff
= NULL
;
705 priv
->tx_queue
[i
]->qindex
= i
;
706 priv
->tx_queue
[i
]->dev
= dev
;
707 spin_lock_init(&(priv
->tx_queue
[i
]->txlock
));
710 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
711 priv
->rx_queue
[i
] = kzalloc(sizeof(struct gfar_priv_rx_q
),
713 if (!priv
->rx_queue
[i
]) {
715 goto rx_alloc_failed
;
717 priv
->rx_queue
[i
]->rx_skbuff
= NULL
;
718 priv
->rx_queue
[i
]->qindex
= i
;
719 priv
->rx_queue
[i
]->dev
= dev
;
720 spin_lock_init(&(priv
->rx_queue
[i
]->rxlock
));
724 stash
= of_get_property(np
, "bd-stash", NULL
);
727 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_BD_STASHING
;
728 priv
->bd_stash_en
= 1;
731 stash_len
= of_get_property(np
, "rx-stash-len", NULL
);
734 priv
->rx_stash_size
= *stash_len
;
736 stash_idx
= of_get_property(np
, "rx-stash-idx", NULL
);
739 priv
->rx_stash_index
= *stash_idx
;
741 if (stash_len
|| stash_idx
)
742 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_BUF_STASHING
;
744 mac_addr
= of_get_mac_address(np
);
747 memcpy(dev
->dev_addr
, mac_addr
, ETH_ALEN
);
749 if (model
&& !strcasecmp(model
, "TSEC"))
750 priv
->device_flags
= FSL_GIANFAR_DEV_HAS_GIGABIT
|
751 FSL_GIANFAR_DEV_HAS_COALESCE
|
752 FSL_GIANFAR_DEV_HAS_RMON
|
753 FSL_GIANFAR_DEV_HAS_MULTI_INTR
;
755 if (model
&& !strcasecmp(model
, "eTSEC"))
756 priv
->device_flags
= FSL_GIANFAR_DEV_HAS_GIGABIT
|
757 FSL_GIANFAR_DEV_HAS_COALESCE
|
758 FSL_GIANFAR_DEV_HAS_RMON
|
759 FSL_GIANFAR_DEV_HAS_MULTI_INTR
|
760 FSL_GIANFAR_DEV_HAS_PADDING
|
761 FSL_GIANFAR_DEV_HAS_CSUM
|
762 FSL_GIANFAR_DEV_HAS_VLAN
|
763 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
|
764 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
|
765 FSL_GIANFAR_DEV_HAS_TIMER
;
767 ctype
= of_get_property(np
, "phy-connection-type", NULL
);
769 /* We only care about rgmii-id. The rest are autodetected */
770 if (ctype
&& !strcmp(ctype
, "rgmii-id"))
771 priv
->interface
= PHY_INTERFACE_MODE_RGMII_ID
;
773 priv
->interface
= PHY_INTERFACE_MODE_MII
;
775 if (of_get_property(np
, "fsl,magic-packet", NULL
))
776 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
;
778 priv
->phy_node
= of_parse_phandle(np
, "phy-handle", 0);
780 /* Find the TBI PHY. If it's not there, we don't support SGMII */
781 priv
->tbi_node
= of_parse_phandle(np
, "tbi-handle", 0);
786 free_rx_pointers(priv
);
788 free_tx_pointers(priv
);
790 unmap_group_regs(priv
);
795 static int gfar_hwtstamp_ioctl(struct net_device
*netdev
,
796 struct ifreq
*ifr
, int cmd
)
798 struct hwtstamp_config config
;
799 struct gfar_private
*priv
= netdev_priv(netdev
);
801 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
804 /* reserved for future extensions */
808 switch (config
.tx_type
) {
809 case HWTSTAMP_TX_OFF
:
810 priv
->hwts_tx_en
= 0;
813 if (!(priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
))
815 priv
->hwts_tx_en
= 1;
821 switch (config
.rx_filter
) {
822 case HWTSTAMP_FILTER_NONE
:
823 if (priv
->hwts_rx_en
) {
825 priv
->hwts_rx_en
= 0;
826 startup_gfar(netdev
);
830 if (!(priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
))
832 if (!priv
->hwts_rx_en
) {
834 priv
->hwts_rx_en
= 1;
835 startup_gfar(netdev
);
837 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
841 return copy_to_user(ifr
->ifr_data
, &config
, sizeof(config
)) ?
845 /* Ioctl MII Interface */
846 static int gfar_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
848 struct gfar_private
*priv
= netdev_priv(dev
);
850 if (!netif_running(dev
))
853 if (cmd
== SIOCSHWTSTAMP
)
854 return gfar_hwtstamp_ioctl(dev
, rq
, cmd
);
859 return phy_mii_ioctl(priv
->phydev
, rq
, cmd
);
862 static unsigned int reverse_bitmap(unsigned int bit_map
, unsigned int max_qs
)
864 unsigned int new_bit_map
= 0x0;
865 int mask
= 0x1 << (max_qs
- 1), i
;
867 for (i
= 0; i
< max_qs
; i
++) {
869 new_bit_map
= new_bit_map
+ (1 << i
);
875 static u32
cluster_entry_per_class(struct gfar_private
*priv
, u32 rqfar
,
878 u32 rqfpr
= FPR_FILER_MASK
;
882 rqfcr
= RQFCR_CLE
| RQFCR_PID_MASK
| RQFCR_CMP_EXACT
;
883 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
884 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
885 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
888 rqfcr
= RQFCR_CMP_NOMATCH
;
889 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
890 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
891 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
894 rqfcr
= RQFCR_CMP_EXACT
| RQFCR_PID_PARSE
| RQFCR_CLE
| RQFCR_AND
;
896 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
897 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
898 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
901 rqfcr
= RQFCR_CMP_EXACT
| RQFCR_PID_MASK
| RQFCR_AND
;
903 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
904 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
905 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
910 static void gfar_init_filer_table(struct gfar_private
*priv
)
913 u32 rqfar
= MAX_FILER_IDX
;
915 u32 rqfpr
= FPR_FILER_MASK
;
918 rqfcr
= RQFCR_CMP_MATCH
;
919 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
920 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
921 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
923 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV6
);
924 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV6
| RQFPR_UDP
);
925 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV6
| RQFPR_TCP
);
926 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV4
);
927 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV4
| RQFPR_UDP
);
928 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV4
| RQFPR_TCP
);
930 /* cur_filer_idx indicated the first non-masked rule */
931 priv
->cur_filer_idx
= rqfar
;
933 /* Rest are masked rules */
934 rqfcr
= RQFCR_CMP_NOMATCH
;
935 for (i
= 0; i
< rqfar
; i
++) {
936 priv
->ftp_rqfcr
[i
] = rqfcr
;
937 priv
->ftp_rqfpr
[i
] = rqfpr
;
938 gfar_write_filer(priv
, i
, rqfcr
, rqfpr
);
942 static void gfar_detect_errata(struct gfar_private
*priv
)
944 struct device
*dev
= &priv
->ofdev
->dev
;
945 unsigned int pvr
= mfspr(SPRN_PVR
);
946 unsigned int svr
= mfspr(SPRN_SVR
);
947 unsigned int mod
= (svr
>> 16) & 0xfff6; /* w/o E suffix */
948 unsigned int rev
= svr
& 0xffff;
950 /* MPC8313 Rev 2.0 and higher; All MPC837x */
951 if ((pvr
== 0x80850010 && mod
== 0x80b0 && rev
>= 0x0020) ||
952 (pvr
== 0x80861010 && (mod
& 0xfff9) == 0x80c0))
953 priv
->errata
|= GFAR_ERRATA_74
;
955 /* MPC8313 and MPC837x all rev */
956 if ((pvr
== 0x80850010 && mod
== 0x80b0) ||
957 (pvr
== 0x80861010 && (mod
& 0xfff9) == 0x80c0))
958 priv
->errata
|= GFAR_ERRATA_76
;
960 /* MPC8313 and MPC837x all rev */
961 if ((pvr
== 0x80850010 && mod
== 0x80b0) ||
962 (pvr
== 0x80861010 && (mod
& 0xfff9) == 0x80c0))
963 priv
->errata
|= GFAR_ERRATA_A002
;
965 /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
966 if ((pvr
== 0x80850010 && mod
== 0x80b0 && rev
< 0x0020) ||
967 (pvr
== 0x80210020 && mod
== 0x8030 && rev
== 0x0020))
968 priv
->errata
|= GFAR_ERRATA_12
;
971 dev_info(dev
, "enabled errata workarounds, flags: 0x%x\n",
975 /* Set up the ethernet device structure, private data,
976 * and anything else we need before we start
978 static int gfar_probe(struct platform_device
*ofdev
)
981 struct net_device
*dev
= NULL
;
982 struct gfar_private
*priv
= NULL
;
983 struct gfar __iomem
*regs
= NULL
;
984 int err
= 0, i
, grp_idx
= 0;
985 u32 rstat
= 0, tstat
= 0, rqueue
= 0, tqueue
= 0;
989 err
= gfar_of_init(ofdev
, &dev
);
994 priv
= netdev_priv(dev
);
997 priv
->dev
= &ofdev
->dev
;
998 SET_NETDEV_DEV(dev
, &ofdev
->dev
);
1000 spin_lock_init(&priv
->bflock
);
1001 INIT_WORK(&priv
->reset_task
, gfar_reset_task
);
1003 platform_set_drvdata(ofdev
, priv
);
1004 regs
= priv
->gfargrp
[0].regs
;
1006 gfar_detect_errata(priv
);
1008 /* Stop the DMA engine now, in case it was running before
1009 * (The firmware could have used it, and left it running).
1013 /* Reset MAC layer */
1014 gfar_write(®s
->maccfg1
, MACCFG1_SOFT_RESET
);
1016 /* We need to delay at least 3 TX clocks */
1020 if (!priv
->pause_aneg_en
&& priv
->tx_pause_en
)
1021 tempval
|= MACCFG1_TX_FLOW
;
1022 if (!priv
->pause_aneg_en
&& priv
->rx_pause_en
)
1023 tempval
|= MACCFG1_RX_FLOW
;
1024 /* the soft reset bit is not self-resetting, so we need to
1025 * clear it before resuming normal operation
1027 gfar_write(®s
->maccfg1
, tempval
);
1029 /* Initialize MACCFG2. */
1030 tempval
= MACCFG2_INIT_SETTINGS
;
1031 if (gfar_has_errata(priv
, GFAR_ERRATA_74
))
1032 tempval
|= MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
;
1033 gfar_write(®s
->maccfg2
, tempval
);
1035 /* Initialize ECNTRL */
1036 gfar_write(®s
->ecntrl
, ECNTRL_INIT_SETTINGS
);
1038 /* Set the dev->base_addr to the gfar reg region */
1039 dev
->base_addr
= (unsigned long) regs
;
1041 /* Fill in the dev structure */
1042 dev
->watchdog_timeo
= TX_TIMEOUT
;
1044 dev
->netdev_ops
= &gfar_netdev_ops
;
1045 dev
->ethtool_ops
= &gfar_ethtool_ops
;
1047 /* Register for napi ...We are registering NAPI for each grp */
1048 if (priv
->mode
== SQ_SG_MODE
)
1049 netif_napi_add(dev
, &priv
->gfargrp
[0].napi
, gfar_poll_sq
,
1052 for (i
= 0; i
< priv
->num_grps
; i
++)
1053 netif_napi_add(dev
, &priv
->gfargrp
[i
].napi
, gfar_poll
,
1056 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
1057 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_SG
|
1059 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
|
1060 NETIF_F_RXCSUM
| NETIF_F_HIGHDMA
;
1063 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
) {
1064 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_TX
|
1065 NETIF_F_HW_VLAN_CTAG_RX
;
1066 dev
->features
|= NETIF_F_HW_VLAN_CTAG_RX
;
1069 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
1070 priv
->extended_hash
= 1;
1071 priv
->hash_width
= 9;
1073 priv
->hash_regs
[0] = ®s
->igaddr0
;
1074 priv
->hash_regs
[1] = ®s
->igaddr1
;
1075 priv
->hash_regs
[2] = ®s
->igaddr2
;
1076 priv
->hash_regs
[3] = ®s
->igaddr3
;
1077 priv
->hash_regs
[4] = ®s
->igaddr4
;
1078 priv
->hash_regs
[5] = ®s
->igaddr5
;
1079 priv
->hash_regs
[6] = ®s
->igaddr6
;
1080 priv
->hash_regs
[7] = ®s
->igaddr7
;
1081 priv
->hash_regs
[8] = ®s
->gaddr0
;
1082 priv
->hash_regs
[9] = ®s
->gaddr1
;
1083 priv
->hash_regs
[10] = ®s
->gaddr2
;
1084 priv
->hash_regs
[11] = ®s
->gaddr3
;
1085 priv
->hash_regs
[12] = ®s
->gaddr4
;
1086 priv
->hash_regs
[13] = ®s
->gaddr5
;
1087 priv
->hash_regs
[14] = ®s
->gaddr6
;
1088 priv
->hash_regs
[15] = ®s
->gaddr7
;
1091 priv
->extended_hash
= 0;
1092 priv
->hash_width
= 8;
1094 priv
->hash_regs
[0] = ®s
->gaddr0
;
1095 priv
->hash_regs
[1] = ®s
->gaddr1
;
1096 priv
->hash_regs
[2] = ®s
->gaddr2
;
1097 priv
->hash_regs
[3] = ®s
->gaddr3
;
1098 priv
->hash_regs
[4] = ®s
->gaddr4
;
1099 priv
->hash_regs
[5] = ®s
->gaddr5
;
1100 priv
->hash_regs
[6] = ®s
->gaddr6
;
1101 priv
->hash_regs
[7] = ®s
->gaddr7
;
1104 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
1105 priv
->padding
= DEFAULT_PADDING
;
1109 if (dev
->features
& NETIF_F_IP_CSUM
||
1110 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
)
1111 dev
->needed_headroom
= GMAC_FCB_LEN
;
1113 /* Program the isrg regs only if number of grps > 1 */
1114 if (priv
->num_grps
> 1) {
1115 baddr
= ®s
->isrg0
;
1116 for (i
= 0; i
< priv
->num_grps
; i
++) {
1117 isrg
|= (priv
->gfargrp
[i
].rx_bit_map
<< ISRG_SHIFT_RX
);
1118 isrg
|= (priv
->gfargrp
[i
].tx_bit_map
<< ISRG_SHIFT_TX
);
1119 gfar_write(baddr
, isrg
);
1125 /* Need to reverse the bit maps as bit_map's MSB is q0
1126 * but, for_each_set_bit parses from right to left, which
1127 * basically reverses the queue numbers
1129 for (i
= 0; i
< priv
->num_grps
; i
++) {
1130 priv
->gfargrp
[i
].tx_bit_map
=
1131 reverse_bitmap(priv
->gfargrp
[i
].tx_bit_map
, MAX_TX_QS
);
1132 priv
->gfargrp
[i
].rx_bit_map
=
1133 reverse_bitmap(priv
->gfargrp
[i
].rx_bit_map
, MAX_RX_QS
);
1136 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1137 * also assign queues to groups
1139 for (grp_idx
= 0; grp_idx
< priv
->num_grps
; grp_idx
++) {
1140 priv
->gfargrp
[grp_idx
].num_rx_queues
= 0x0;
1142 for_each_set_bit(i
, &priv
->gfargrp
[grp_idx
].rx_bit_map
,
1143 priv
->num_rx_queues
) {
1144 priv
->gfargrp
[grp_idx
].num_rx_queues
++;
1145 priv
->rx_queue
[i
]->grp
= &priv
->gfargrp
[grp_idx
];
1146 rstat
= rstat
| (RSTAT_CLEAR_RHALT
>> i
);
1147 rqueue
= rqueue
| ((RQUEUE_EN0
| RQUEUE_EX0
) >> i
);
1149 priv
->gfargrp
[grp_idx
].num_tx_queues
= 0x0;
1151 for_each_set_bit(i
, &priv
->gfargrp
[grp_idx
].tx_bit_map
,
1152 priv
->num_tx_queues
) {
1153 priv
->gfargrp
[grp_idx
].num_tx_queues
++;
1154 priv
->tx_queue
[i
]->grp
= &priv
->gfargrp
[grp_idx
];
1155 tstat
= tstat
| (TSTAT_CLEAR_THALT
>> i
);
1156 tqueue
= tqueue
| (TQUEUE_EN0
>> i
);
1158 priv
->gfargrp
[grp_idx
].rstat
= rstat
;
1159 priv
->gfargrp
[grp_idx
].tstat
= tstat
;
1163 gfar_write(®s
->rqueue
, rqueue
);
1164 gfar_write(®s
->tqueue
, tqueue
);
1166 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
1168 /* Initializing some of the rx/tx queue level parameters */
1169 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
1170 priv
->tx_queue
[i
]->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
1171 priv
->tx_queue
[i
]->num_txbdfree
= DEFAULT_TX_RING_SIZE
;
1172 priv
->tx_queue
[i
]->txcoalescing
= DEFAULT_TX_COALESCE
;
1173 priv
->tx_queue
[i
]->txic
= DEFAULT_TXIC
;
1176 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
1177 priv
->rx_queue
[i
]->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
1178 priv
->rx_queue
[i
]->rxcoalescing
= DEFAULT_RX_COALESCE
;
1179 priv
->rx_queue
[i
]->rxic
= DEFAULT_RXIC
;
1182 /* always enable rx filer */
1183 priv
->rx_filer_enable
= 1;
1184 /* Enable most messages by default */
1185 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
1186 /* use pritority h/w tx queue scheduling for single queue devices */
1187 if (priv
->num_tx_queues
== 1)
1188 priv
->prio_sched_en
= 1;
1190 /* Carrier starts down, phylib will bring it up */
1191 netif_carrier_off(dev
);
1193 err
= register_netdev(dev
);
1196 pr_err("%s: Cannot register net device, aborting\n", dev
->name
);
1200 device_init_wakeup(&dev
->dev
,
1201 priv
->device_flags
&
1202 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
1204 /* fill out IRQ number and name fields */
1205 for (i
= 0; i
< priv
->num_grps
; i
++) {
1206 struct gfar_priv_grp
*grp
= &priv
->gfargrp
[i
];
1207 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1208 sprintf(gfar_irq(grp
, TX
)->name
, "%s%s%c%s",
1209 dev
->name
, "_g", '0' + i
, "_tx");
1210 sprintf(gfar_irq(grp
, RX
)->name
, "%s%s%c%s",
1211 dev
->name
, "_g", '0' + i
, "_rx");
1212 sprintf(gfar_irq(grp
, ER
)->name
, "%s%s%c%s",
1213 dev
->name
, "_g", '0' + i
, "_er");
1215 strcpy(gfar_irq(grp
, TX
)->name
, dev
->name
);
1218 /* Initialize the filer table */
1219 gfar_init_filer_table(priv
);
1221 /* Create all the sysfs files */
1222 gfar_init_sysfs(dev
);
1224 /* Print out the device info */
1225 netdev_info(dev
, "mac: %pM\n", dev
->dev_addr
);
1227 /* Even more device info helps when determining which kernel
1228 * provided which set of benchmarks.
1230 netdev_info(dev
, "Running with NAPI enabled\n");
1231 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
1232 netdev_info(dev
, "RX BD ring size for Q[%d]: %d\n",
1233 i
, priv
->rx_queue
[i
]->rx_ring_size
);
1234 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
1235 netdev_info(dev
, "TX BD ring size for Q[%d]: %d\n",
1236 i
, priv
->tx_queue
[i
]->tx_ring_size
);
1241 unmap_group_regs(priv
);
1242 free_tx_pointers(priv
);
1243 free_rx_pointers(priv
);
1245 of_node_put(priv
->phy_node
);
1247 of_node_put(priv
->tbi_node
);
1248 free_gfar_dev(priv
);
1252 static int gfar_remove(struct platform_device
*ofdev
)
1254 struct gfar_private
*priv
= platform_get_drvdata(ofdev
);
1257 of_node_put(priv
->phy_node
);
1259 of_node_put(priv
->tbi_node
);
1261 unregister_netdev(priv
->ndev
);
1262 unmap_group_regs(priv
);
1263 free_gfar_dev(priv
);
1270 static int gfar_suspend(struct device
*dev
)
1272 struct gfar_private
*priv
= dev_get_drvdata(dev
);
1273 struct net_device
*ndev
= priv
->ndev
;
1274 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1275 unsigned long flags
;
1278 int magic_packet
= priv
->wol_en
&&
1279 (priv
->device_flags
&
1280 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
1282 netif_device_detach(ndev
);
1284 if (netif_running(ndev
)) {
1286 local_irq_save(flags
);
1290 gfar_halt_nodisable(ndev
);
1292 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1293 tempval
= gfar_read(®s
->maccfg1
);
1295 tempval
&= ~MACCFG1_TX_EN
;
1298 tempval
&= ~MACCFG1_RX_EN
;
1300 gfar_write(®s
->maccfg1
, tempval
);
1304 local_irq_restore(flags
);
1309 /* Enable interrupt on Magic Packet */
1310 gfar_write(®s
->imask
, IMASK_MAG
);
1312 /* Enable Magic Packet mode */
1313 tempval
= gfar_read(®s
->maccfg2
);
1314 tempval
|= MACCFG2_MPEN
;
1315 gfar_write(®s
->maccfg2
, tempval
);
1317 phy_stop(priv
->phydev
);
1324 static int gfar_resume(struct device
*dev
)
1326 struct gfar_private
*priv
= dev_get_drvdata(dev
);
1327 struct net_device
*ndev
= priv
->ndev
;
1328 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1329 unsigned long flags
;
1331 int magic_packet
= priv
->wol_en
&&
1332 (priv
->device_flags
&
1333 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
1335 if (!netif_running(ndev
)) {
1336 netif_device_attach(ndev
);
1340 if (!magic_packet
&& priv
->phydev
)
1341 phy_start(priv
->phydev
);
1343 /* Disable Magic Packet mode, in case something
1346 local_irq_save(flags
);
1350 tempval
= gfar_read(®s
->maccfg2
);
1351 tempval
&= ~MACCFG2_MPEN
;
1352 gfar_write(®s
->maccfg2
, tempval
);
1358 local_irq_restore(flags
);
1360 netif_device_attach(ndev
);
1367 static int gfar_restore(struct device
*dev
)
1369 struct gfar_private
*priv
= dev_get_drvdata(dev
);
1370 struct net_device
*ndev
= priv
->ndev
;
1372 if (!netif_running(ndev
)) {
1373 netif_device_attach(ndev
);
1378 if (gfar_init_bds(ndev
)) {
1379 free_skb_resources(priv
);
1383 init_registers(ndev
);
1384 gfar_set_mac_address(ndev
);
1385 gfar_init_mac(ndev
);
1390 priv
->oldduplex
= -1;
1393 phy_start(priv
->phydev
);
1395 netif_device_attach(ndev
);
1401 static struct dev_pm_ops gfar_pm_ops
= {
1402 .suspend
= gfar_suspend
,
1403 .resume
= gfar_resume
,
1404 .freeze
= gfar_suspend
,
1405 .thaw
= gfar_resume
,
1406 .restore
= gfar_restore
,
1409 #define GFAR_PM_OPS (&gfar_pm_ops)
1413 #define GFAR_PM_OPS NULL
1417 /* Reads the controller's registers to determine what interface
1418 * connects it to the PHY.
1420 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
1422 struct gfar_private
*priv
= netdev_priv(dev
);
1423 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1426 ecntrl
= gfar_read(®s
->ecntrl
);
1428 if (ecntrl
& ECNTRL_SGMII_MODE
)
1429 return PHY_INTERFACE_MODE_SGMII
;
1431 if (ecntrl
& ECNTRL_TBI_MODE
) {
1432 if (ecntrl
& ECNTRL_REDUCED_MODE
)
1433 return PHY_INTERFACE_MODE_RTBI
;
1435 return PHY_INTERFACE_MODE_TBI
;
1438 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
1439 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
) {
1440 return PHY_INTERFACE_MODE_RMII
;
1443 phy_interface_t interface
= priv
->interface
;
1445 /* This isn't autodetected right now, so it must
1446 * be set by the device tree or platform code.
1448 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
1449 return PHY_INTERFACE_MODE_RGMII_ID
;
1451 return PHY_INTERFACE_MODE_RGMII
;
1455 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
1456 return PHY_INTERFACE_MODE_GMII
;
1458 return PHY_INTERFACE_MODE_MII
;
1462 /* Initializes driver's PHY state, and attaches to the PHY.
1463 * Returns 0 on success.
1465 static int init_phy(struct net_device
*dev
)
1467 struct gfar_private
*priv
= netdev_priv(dev
);
1468 uint gigabit_support
=
1469 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
1470 GFAR_SUPPORTED_GBIT
: 0;
1471 phy_interface_t interface
;
1475 priv
->oldduplex
= -1;
1477 interface
= gfar_get_interface(dev
);
1479 priv
->phydev
= of_phy_connect(dev
, priv
->phy_node
, &adjust_link
, 0,
1482 priv
->phydev
= of_phy_connect_fixed_link(dev
, &adjust_link
,
1484 if (!priv
->phydev
) {
1485 dev_err(&dev
->dev
, "could not attach to PHY\n");
1489 if (interface
== PHY_INTERFACE_MODE_SGMII
)
1490 gfar_configure_serdes(dev
);
1492 /* Remove any features not supported by the controller */
1493 priv
->phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
1494 priv
->phydev
->advertising
= priv
->phydev
->supported
;
1499 /* Initialize TBI PHY interface for communicating with the
1500 * SERDES lynx PHY on the chip. We communicate with this PHY
1501 * through the MDIO bus on each controller, treating it as a
1502 * "normal" PHY at the address found in the TBIPA register. We assume
1503 * that the TBIPA register is valid. Either the MDIO bus code will set
1504 * it to a value that doesn't conflict with other PHYs on the bus, or the
1505 * value doesn't matter, as there are no other PHYs on the bus.
1507 static void gfar_configure_serdes(struct net_device
*dev
)
1509 struct gfar_private
*priv
= netdev_priv(dev
);
1510 struct phy_device
*tbiphy
;
1512 if (!priv
->tbi_node
) {
1513 dev_warn(&dev
->dev
, "error: SGMII mode requires that the "
1514 "device tree specify a tbi-handle\n");
1518 tbiphy
= of_phy_find_device(priv
->tbi_node
);
1520 dev_err(&dev
->dev
, "error: Could not get TBI device\n");
1524 /* If the link is already up, we must already be ok, and don't need to
1525 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1526 * everything for us? Resetting it takes the link down and requires
1527 * several seconds for it to come back.
1529 if (phy_read(tbiphy
, MII_BMSR
) & BMSR_LSTATUS
)
1532 /* Single clk mode, mii mode off(for serdes communication) */
1533 phy_write(tbiphy
, MII_TBICON
, TBICON_CLK_SELECT
);
1535 phy_write(tbiphy
, MII_ADVERTISE
,
1536 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
1537 ADVERTISE_1000XPSE_ASYM
);
1539 phy_write(tbiphy
, MII_BMCR
,
1540 BMCR_ANENABLE
| BMCR_ANRESTART
| BMCR_FULLDPLX
|
1544 static void init_registers(struct net_device
*dev
)
1546 struct gfar_private
*priv
= netdev_priv(dev
);
1547 struct gfar __iomem
*regs
= NULL
;
1550 for (i
= 0; i
< priv
->num_grps
; i
++) {
1551 regs
= priv
->gfargrp
[i
].regs
;
1553 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
1555 /* Initialize IMASK */
1556 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
1559 regs
= priv
->gfargrp
[0].regs
;
1560 /* Init hash registers to zero */
1561 gfar_write(®s
->igaddr0
, 0);
1562 gfar_write(®s
->igaddr1
, 0);
1563 gfar_write(®s
->igaddr2
, 0);
1564 gfar_write(®s
->igaddr3
, 0);
1565 gfar_write(®s
->igaddr4
, 0);
1566 gfar_write(®s
->igaddr5
, 0);
1567 gfar_write(®s
->igaddr6
, 0);
1568 gfar_write(®s
->igaddr7
, 0);
1570 gfar_write(®s
->gaddr0
, 0);
1571 gfar_write(®s
->gaddr1
, 0);
1572 gfar_write(®s
->gaddr2
, 0);
1573 gfar_write(®s
->gaddr3
, 0);
1574 gfar_write(®s
->gaddr4
, 0);
1575 gfar_write(®s
->gaddr5
, 0);
1576 gfar_write(®s
->gaddr6
, 0);
1577 gfar_write(®s
->gaddr7
, 0);
1579 /* Zero out the rmon mib registers if it has them */
1580 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
1581 memset_io(&(regs
->rmon
), 0, sizeof (struct rmon_mib
));
1583 /* Mask off the CAM interrupts */
1584 gfar_write(®s
->rmon
.cam1
, 0xffffffff);
1585 gfar_write(®s
->rmon
.cam2
, 0xffffffff);
1588 /* Initialize the max receive buffer length */
1589 gfar_write(®s
->mrblr
, priv
->rx_buffer_size
);
1591 /* Initialize the Minimum Frame Length Register */
1592 gfar_write(®s
->minflr
, MINFLR_INIT_SETTINGS
);
1595 static int __gfar_is_rx_idle(struct gfar_private
*priv
)
1599 /* Normaly TSEC should not hang on GRS commands, so we should
1600 * actually wait for IEVENT_GRSC flag.
1602 if (likely(!gfar_has_errata(priv
, GFAR_ERRATA_A002
)))
1605 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1606 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1607 * and the Rx can be safely reset.
1609 res
= gfar_read((void __iomem
*)priv
->gfargrp
[0].regs
+ 0xd1c);
1611 if ((res
& 0xffff) == (res
>> 16))
1617 /* Halt the receive and transmit queues */
1618 static void gfar_halt_nodisable(struct net_device
*dev
)
1620 struct gfar_private
*priv
= netdev_priv(dev
);
1621 struct gfar __iomem
*regs
= NULL
;
1625 for (i
= 0; i
< priv
->num_grps
; i
++) {
1626 regs
= priv
->gfargrp
[i
].regs
;
1627 /* Mask all interrupts */
1628 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
1630 /* Clear all interrupts */
1631 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
1634 regs
= priv
->gfargrp
[0].regs
;
1635 /* Stop the DMA, and wait for it to stop */
1636 tempval
= gfar_read(®s
->dmactrl
);
1637 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
)) !=
1638 (DMACTRL_GRS
| DMACTRL_GTS
)) {
1641 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
1642 gfar_write(®s
->dmactrl
, tempval
);
1645 ret
= spin_event_timeout(((gfar_read(®s
->ievent
) &
1646 (IEVENT_GRSC
| IEVENT_GTSC
)) ==
1647 (IEVENT_GRSC
| IEVENT_GTSC
)), 1000000, 0);
1648 if (!ret
&& !(gfar_read(®s
->ievent
) & IEVENT_GRSC
))
1649 ret
= __gfar_is_rx_idle(priv
);
1654 /* Halt the receive and transmit queues */
1655 void gfar_halt(struct net_device
*dev
)
1657 struct gfar_private
*priv
= netdev_priv(dev
);
1658 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1661 gfar_halt_nodisable(dev
);
1663 /* Disable Rx and Tx */
1664 tempval
= gfar_read(®s
->maccfg1
);
1665 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
1666 gfar_write(®s
->maccfg1
, tempval
);
1669 static void free_grp_irqs(struct gfar_priv_grp
*grp
)
1671 free_irq(gfar_irq(grp
, TX
)->irq
, grp
);
1672 free_irq(gfar_irq(grp
, RX
)->irq
, grp
);
1673 free_irq(gfar_irq(grp
, ER
)->irq
, grp
);
1676 void stop_gfar(struct net_device
*dev
)
1678 struct gfar_private
*priv
= netdev_priv(dev
);
1679 unsigned long flags
;
1682 phy_stop(priv
->phydev
);
1686 local_irq_save(flags
);
1694 local_irq_restore(flags
);
1697 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1698 for (i
= 0; i
< priv
->num_grps
; i
++)
1699 free_grp_irqs(&priv
->gfargrp
[i
]);
1701 for (i
= 0; i
< priv
->num_grps
; i
++)
1702 free_irq(gfar_irq(&priv
->gfargrp
[i
], TX
)->irq
,
1706 free_skb_resources(priv
);
1709 static void free_skb_tx_queue(struct gfar_priv_tx_q
*tx_queue
)
1711 struct txbd8
*txbdp
;
1712 struct gfar_private
*priv
= netdev_priv(tx_queue
->dev
);
1715 txbdp
= tx_queue
->tx_bd_base
;
1717 for (i
= 0; i
< tx_queue
->tx_ring_size
; i
++) {
1718 if (!tx_queue
->tx_skbuff
[i
])
1721 dma_unmap_single(priv
->dev
, txbdp
->bufPtr
,
1722 txbdp
->length
, DMA_TO_DEVICE
);
1724 for (j
= 0; j
< skb_shinfo(tx_queue
->tx_skbuff
[i
])->nr_frags
;
1727 dma_unmap_page(priv
->dev
, txbdp
->bufPtr
,
1728 txbdp
->length
, DMA_TO_DEVICE
);
1731 dev_kfree_skb_any(tx_queue
->tx_skbuff
[i
]);
1732 tx_queue
->tx_skbuff
[i
] = NULL
;
1734 kfree(tx_queue
->tx_skbuff
);
1735 tx_queue
->tx_skbuff
= NULL
;
1738 static void free_skb_rx_queue(struct gfar_priv_rx_q
*rx_queue
)
1740 struct rxbd8
*rxbdp
;
1741 struct gfar_private
*priv
= netdev_priv(rx_queue
->dev
);
1744 rxbdp
= rx_queue
->rx_bd_base
;
1746 for (i
= 0; i
< rx_queue
->rx_ring_size
; i
++) {
1747 if (rx_queue
->rx_skbuff
[i
]) {
1748 dma_unmap_single(priv
->dev
, rxbdp
->bufPtr
,
1749 priv
->rx_buffer_size
,
1751 dev_kfree_skb_any(rx_queue
->rx_skbuff
[i
]);
1752 rx_queue
->rx_skbuff
[i
] = NULL
;
1758 kfree(rx_queue
->rx_skbuff
);
1759 rx_queue
->rx_skbuff
= NULL
;
1762 /* If there are any tx skbs or rx skbs still around, free them.
1763 * Then free tx_skbuff and rx_skbuff
1765 static void free_skb_resources(struct gfar_private
*priv
)
1767 struct gfar_priv_tx_q
*tx_queue
= NULL
;
1768 struct gfar_priv_rx_q
*rx_queue
= NULL
;
1771 /* Go through all the buffer descriptors and free their data buffers */
1772 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
1773 struct netdev_queue
*txq
;
1775 tx_queue
= priv
->tx_queue
[i
];
1776 txq
= netdev_get_tx_queue(tx_queue
->dev
, tx_queue
->qindex
);
1777 if (tx_queue
->tx_skbuff
)
1778 free_skb_tx_queue(tx_queue
);
1779 netdev_tx_reset_queue(txq
);
1782 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
1783 rx_queue
= priv
->rx_queue
[i
];
1784 if (rx_queue
->rx_skbuff
)
1785 free_skb_rx_queue(rx_queue
);
1788 dma_free_coherent(priv
->dev
,
1789 sizeof(struct txbd8
) * priv
->total_tx_ring_size
+
1790 sizeof(struct rxbd8
) * priv
->total_rx_ring_size
,
1791 priv
->tx_queue
[0]->tx_bd_base
,
1792 priv
->tx_queue
[0]->tx_bd_dma_base
);
1795 void gfar_start(struct net_device
*dev
)
1797 struct gfar_private
*priv
= netdev_priv(dev
);
1798 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1802 /* Enable Rx and Tx in MACCFG1 */
1803 tempval
= gfar_read(®s
->maccfg1
);
1804 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
1805 gfar_write(®s
->maccfg1
, tempval
);
1807 /* Initialize DMACTRL to have WWR and WOP */
1808 tempval
= gfar_read(®s
->dmactrl
);
1809 tempval
|= DMACTRL_INIT_SETTINGS
;
1810 gfar_write(®s
->dmactrl
, tempval
);
1812 /* Make sure we aren't stopped */
1813 tempval
= gfar_read(®s
->dmactrl
);
1814 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
1815 gfar_write(®s
->dmactrl
, tempval
);
1817 for (i
= 0; i
< priv
->num_grps
; i
++) {
1818 regs
= priv
->gfargrp
[i
].regs
;
1819 /* Clear THLT/RHLT, so that the DMA starts polling now */
1820 gfar_write(®s
->tstat
, priv
->gfargrp
[i
].tstat
);
1821 gfar_write(®s
->rstat
, priv
->gfargrp
[i
].rstat
);
1822 /* Unmask the interrupts we look for */
1823 gfar_write(®s
->imask
, IMASK_DEFAULT
);
1826 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1829 static void gfar_configure_coalescing(struct gfar_private
*priv
,
1830 unsigned long tx_mask
, unsigned long rx_mask
)
1832 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1835 if (priv
->mode
== MQ_MG_MODE
) {
1838 baddr
= ®s
->txic0
;
1839 for_each_set_bit(i
, &tx_mask
, priv
->num_tx_queues
) {
1840 gfar_write(baddr
+ i
, 0);
1841 if (likely(priv
->tx_queue
[i
]->txcoalescing
))
1842 gfar_write(baddr
+ i
, priv
->tx_queue
[i
]->txic
);
1845 baddr
= ®s
->rxic0
;
1846 for_each_set_bit(i
, &rx_mask
, priv
->num_rx_queues
) {
1847 gfar_write(baddr
+ i
, 0);
1848 if (likely(priv
->rx_queue
[i
]->rxcoalescing
))
1849 gfar_write(baddr
+ i
, priv
->rx_queue
[i
]->rxic
);
1852 /* Backward compatible case -- even if we enable
1853 * multiple queues, there's only single reg to program
1855 gfar_write(®s
->txic
, 0);
1856 if (likely(priv
->tx_queue
[0]->txcoalescing
))
1857 gfar_write(®s
->txic
, priv
->tx_queue
[0]->txic
);
1859 gfar_write(®s
->rxic
, 0);
1860 if (unlikely(priv
->rx_queue
[0]->rxcoalescing
))
1861 gfar_write(®s
->rxic
, priv
->rx_queue
[0]->rxic
);
1865 void gfar_configure_coalescing_all(struct gfar_private
*priv
)
1867 gfar_configure_coalescing(priv
, 0xFF, 0xFF);
1870 static int register_grp_irqs(struct gfar_priv_grp
*grp
)
1872 struct gfar_private
*priv
= grp
->priv
;
1873 struct net_device
*dev
= priv
->ndev
;
1876 /* If the device has multiple interrupts, register for
1877 * them. Otherwise, only register for the one
1879 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1880 /* Install our interrupt handlers for Error,
1881 * Transmit, and Receive
1883 err
= request_irq(gfar_irq(grp
, ER
)->irq
, gfar_error
, 0,
1884 gfar_irq(grp
, ER
)->name
, grp
);
1886 netif_err(priv
, intr
, dev
, "Can't get IRQ %d\n",
1887 gfar_irq(grp
, ER
)->irq
);
1891 err
= request_irq(gfar_irq(grp
, TX
)->irq
, gfar_transmit
, 0,
1892 gfar_irq(grp
, TX
)->name
, grp
);
1894 netif_err(priv
, intr
, dev
, "Can't get IRQ %d\n",
1895 gfar_irq(grp
, TX
)->irq
);
1898 err
= request_irq(gfar_irq(grp
, RX
)->irq
, gfar_receive
, 0,
1899 gfar_irq(grp
, RX
)->name
, grp
);
1901 netif_err(priv
, intr
, dev
, "Can't get IRQ %d\n",
1902 gfar_irq(grp
, RX
)->irq
);
1906 err
= request_irq(gfar_irq(grp
, TX
)->irq
, gfar_interrupt
, 0,
1907 gfar_irq(grp
, TX
)->name
, grp
);
1909 netif_err(priv
, intr
, dev
, "Can't get IRQ %d\n",
1910 gfar_irq(grp
, TX
)->irq
);
1918 free_irq(gfar_irq(grp
, TX
)->irq
, grp
);
1920 free_irq(gfar_irq(grp
, ER
)->irq
, grp
);
1926 /* Bring the controller up and running */
1927 int startup_gfar(struct net_device
*ndev
)
1929 struct gfar_private
*priv
= netdev_priv(ndev
);
1930 struct gfar __iomem
*regs
= NULL
;
1933 for (i
= 0; i
< priv
->num_grps
; i
++) {
1934 regs
= priv
->gfargrp
[i
].regs
;
1935 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
1938 regs
= priv
->gfargrp
[0].regs
;
1939 err
= gfar_alloc_skb_resources(ndev
);
1943 gfar_init_mac(ndev
);
1945 for (i
= 0; i
< priv
->num_grps
; i
++) {
1946 err
= register_grp_irqs(&priv
->gfargrp
[i
]);
1948 for (j
= 0; j
< i
; j
++)
1949 free_grp_irqs(&priv
->gfargrp
[j
]);
1954 /* Start the controller */
1957 phy_start(priv
->phydev
);
1959 gfar_configure_coalescing_all(priv
);
1964 free_skb_resources(priv
);
1968 /* Called when something needs to use the ethernet device
1969 * Returns 0 for success.
1971 static int gfar_enet_open(struct net_device
*dev
)
1973 struct gfar_private
*priv
= netdev_priv(dev
);
1978 /* Initialize a bunch of registers */
1979 init_registers(dev
);
1981 gfar_set_mac_address(dev
);
1983 err
= init_phy(dev
);
1990 err
= startup_gfar(dev
);
1996 netif_tx_start_all_queues(dev
);
1998 device_set_wakeup_enable(&dev
->dev
, priv
->wol_en
);
2003 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
)
2005 struct txfcb
*fcb
= (struct txfcb
*)skb_push(skb
, GMAC_FCB_LEN
);
2007 memset(fcb
, 0, GMAC_FCB_LEN
);
2012 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
,
2015 /* If we're here, it's a IP packet with a TCP or UDP
2016 * payload. We set it to checksum, using a pseudo-header
2019 u8 flags
= TXFCB_DEFAULT
;
2021 /* Tell the controller what the protocol is
2022 * And provide the already calculated phcs
2024 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
2026 fcb
->phcs
= udp_hdr(skb
)->check
;
2028 fcb
->phcs
= tcp_hdr(skb
)->check
;
2030 /* l3os is the distance between the start of the
2031 * frame (skb->data) and the start of the IP hdr.
2032 * l4os is the distance between the start of the
2033 * l3 hdr and the l4 hdr
2035 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - fcb_length
);
2036 fcb
->l4os
= skb_network_header_len(skb
);
2041 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
2043 fcb
->flags
|= TXFCB_VLN
;
2044 fcb
->vlctl
= vlan_tx_tag_get(skb
);
2047 static inline struct txbd8
*skip_txbd(struct txbd8
*bdp
, int stride
,
2048 struct txbd8
*base
, int ring_size
)
2050 struct txbd8
*new_bd
= bdp
+ stride
;
2052 return (new_bd
>= (base
+ ring_size
)) ? (new_bd
- ring_size
) : new_bd
;
2055 static inline struct txbd8
*next_txbd(struct txbd8
*bdp
, struct txbd8
*base
,
2058 return skip_txbd(bdp
, 1, base
, ring_size
);
2061 /* eTSEC12: csum generation not supported for some fcb offsets */
2062 static inline bool gfar_csum_errata_12(struct gfar_private
*priv
,
2063 unsigned long fcb_addr
)
2065 return (gfar_has_errata(priv
, GFAR_ERRATA_12
) &&
2066 (fcb_addr
% 0x20) > 0x18);
2069 /* eTSEC76: csum generation for frames larger than 2500 may
2070 * cause excess delays before start of transmission
2072 static inline bool gfar_csum_errata_76(struct gfar_private
*priv
,
2075 return (gfar_has_errata(priv
, GFAR_ERRATA_76
) &&
2079 /* This is called by the kernel when a frame is ready for transmission.
2080 * It is pointed to by the dev->hard_start_xmit function pointer
2082 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2084 struct gfar_private
*priv
= netdev_priv(dev
);
2085 struct gfar_priv_tx_q
*tx_queue
= NULL
;
2086 struct netdev_queue
*txq
;
2087 struct gfar __iomem
*regs
= NULL
;
2088 struct txfcb
*fcb
= NULL
;
2089 struct txbd8
*txbdp
, *txbdp_start
, *base
, *txbdp_tstamp
= NULL
;
2092 int do_tstamp
, do_csum
, do_vlan
;
2094 unsigned long flags
;
2095 unsigned int nr_frags
, nr_txbds
, length
, fcb_len
= 0;
2097 rq
= skb
->queue_mapping
;
2098 tx_queue
= priv
->tx_queue
[rq
];
2099 txq
= netdev_get_tx_queue(dev
, rq
);
2100 base
= tx_queue
->tx_bd_base
;
2101 regs
= tx_queue
->grp
->regs
;
2103 do_csum
= (CHECKSUM_PARTIAL
== skb
->ip_summed
);
2104 do_vlan
= vlan_tx_tag_present(skb
);
2105 do_tstamp
= (skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
) &&
2108 if (do_csum
|| do_vlan
)
2109 fcb_len
= GMAC_FCB_LEN
;
2111 /* check if time stamp should be generated */
2112 if (unlikely(do_tstamp
))
2113 fcb_len
= GMAC_FCB_LEN
+ GMAC_TXPAL_LEN
;
2115 /* make space for additional header when fcb is needed */
2116 if (fcb_len
&& unlikely(skb_headroom(skb
) < fcb_len
)) {
2117 struct sk_buff
*skb_new
;
2119 skb_new
= skb_realloc_headroom(skb
, fcb_len
);
2121 dev
->stats
.tx_errors
++;
2123 return NETDEV_TX_OK
;
2127 skb_set_owner_w(skb_new
, skb
->sk
);
2132 /* total number of fragments in the SKB */
2133 nr_frags
= skb_shinfo(skb
)->nr_frags
;
2135 /* calculate the required number of TxBDs for this skb */
2136 if (unlikely(do_tstamp
))
2137 nr_txbds
= nr_frags
+ 2;
2139 nr_txbds
= nr_frags
+ 1;
2141 /* check if there is space to queue this packet */
2142 if (nr_txbds
> tx_queue
->num_txbdfree
) {
2143 /* no space, stop the queue */
2144 netif_tx_stop_queue(txq
);
2145 dev
->stats
.tx_fifo_errors
++;
2146 return NETDEV_TX_BUSY
;
2149 /* Update transmit stats */
2150 tx_queue
->stats
.tx_bytes
+= skb
->len
;
2151 tx_queue
->stats
.tx_packets
++;
2153 txbdp
= txbdp_start
= tx_queue
->cur_tx
;
2154 lstatus
= txbdp
->lstatus
;
2156 /* Time stamp insertion requires one additional TxBD */
2157 if (unlikely(do_tstamp
))
2158 txbdp_tstamp
= txbdp
= next_txbd(txbdp
, base
,
2159 tx_queue
->tx_ring_size
);
2161 if (nr_frags
== 0) {
2162 if (unlikely(do_tstamp
))
2163 txbdp_tstamp
->lstatus
|= BD_LFLAG(TXBD_LAST
|
2166 lstatus
|= BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
2168 /* Place the fragment addresses and lengths into the TxBDs */
2169 for (i
= 0; i
< nr_frags
; i
++) {
2170 /* Point at the next BD, wrapping as needed */
2171 txbdp
= next_txbd(txbdp
, base
, tx_queue
->tx_ring_size
);
2173 length
= skb_shinfo(skb
)->frags
[i
].size
;
2175 lstatus
= txbdp
->lstatus
| length
|
2176 BD_LFLAG(TXBD_READY
);
2178 /* Handle the last BD specially */
2179 if (i
== nr_frags
- 1)
2180 lstatus
|= BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
2182 bufaddr
= skb_frag_dma_map(priv
->dev
,
2183 &skb_shinfo(skb
)->frags
[i
],
2188 /* set the TxBD length and buffer pointer */
2189 txbdp
->bufPtr
= bufaddr
;
2190 txbdp
->lstatus
= lstatus
;
2193 lstatus
= txbdp_start
->lstatus
;
2196 /* Add TxPAL between FCB and frame if required */
2197 if (unlikely(do_tstamp
)) {
2198 skb_push(skb
, GMAC_TXPAL_LEN
);
2199 memset(skb
->data
, 0, GMAC_TXPAL_LEN
);
2202 /* Add TxFCB if required */
2204 fcb
= gfar_add_fcb(skb
);
2205 lstatus
|= BD_LFLAG(TXBD_TOE
);
2208 /* Set up checksumming */
2210 gfar_tx_checksum(skb
, fcb
, fcb_len
);
2212 if (unlikely(gfar_csum_errata_12(priv
, (unsigned long)fcb
)) ||
2213 unlikely(gfar_csum_errata_76(priv
, skb
->len
))) {
2214 __skb_pull(skb
, GMAC_FCB_LEN
);
2215 skb_checksum_help(skb
);
2216 if (do_vlan
|| do_tstamp
) {
2217 /* put back a new fcb for vlan/tstamp TOE */
2218 fcb
= gfar_add_fcb(skb
);
2220 /* Tx TOE not used */
2221 lstatus
&= ~(BD_LFLAG(TXBD_TOE
));
2228 gfar_tx_vlan(skb
, fcb
);
2230 /* Setup tx hardware time stamping if requested */
2231 if (unlikely(do_tstamp
)) {
2232 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
2236 txbdp_start
->bufPtr
= dma_map_single(priv
->dev
, skb
->data
,
2237 skb_headlen(skb
), DMA_TO_DEVICE
);
2239 /* If time stamping is requested one additional TxBD must be set up. The
2240 * first TxBD points to the FCB and must have a data length of
2241 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2242 * the full frame length.
2244 if (unlikely(do_tstamp
)) {
2245 txbdp_tstamp
->bufPtr
= txbdp_start
->bufPtr
+ fcb_len
;
2246 txbdp_tstamp
->lstatus
|= BD_LFLAG(TXBD_READY
) |
2247 (skb_headlen(skb
) - fcb_len
);
2248 lstatus
|= BD_LFLAG(TXBD_CRC
| TXBD_READY
) | GMAC_FCB_LEN
;
2250 lstatus
|= BD_LFLAG(TXBD_CRC
| TXBD_READY
) | skb_headlen(skb
);
2253 netdev_tx_sent_queue(txq
, skb
->len
);
2255 /* We can work in parallel with gfar_clean_tx_ring(), except
2256 * when modifying num_txbdfree. Note that we didn't grab the lock
2257 * when we were reading the num_txbdfree and checking for available
2258 * space, that's because outside of this function it can only grow,
2259 * and once we've got needed space, it cannot suddenly disappear.
2261 * The lock also protects us from gfar_error(), which can modify
2262 * regs->tstat and thus retrigger the transfers, which is why we
2263 * also must grab the lock before setting ready bit for the first
2264 * to be transmitted BD.
2266 spin_lock_irqsave(&tx_queue
->txlock
, flags
);
2268 /* The powerpc-specific eieio() is used, as wmb() has too strong
2269 * semantics (it requires synchronization between cacheable and
2270 * uncacheable mappings, which eieio doesn't provide and which we
2271 * don't need), thus requiring a more expensive sync instruction. At
2272 * some point, the set of architecture-independent barrier functions
2273 * should be expanded to include weaker barriers.
2277 txbdp_start
->lstatus
= lstatus
;
2279 eieio(); /* force lstatus write before tx_skbuff */
2281 tx_queue
->tx_skbuff
[tx_queue
->skb_curtx
] = skb
;
2283 /* Update the current skb pointer to the next entry we will use
2284 * (wrapping if necessary)
2286 tx_queue
->skb_curtx
= (tx_queue
->skb_curtx
+ 1) &
2287 TX_RING_MOD_MASK(tx_queue
->tx_ring_size
);
2289 tx_queue
->cur_tx
= next_txbd(txbdp
, base
, tx_queue
->tx_ring_size
);
2291 /* reduce TxBD free count */
2292 tx_queue
->num_txbdfree
-= (nr_txbds
);
2294 /* If the next BD still needs to be cleaned up, then the bds
2295 * are full. We need to tell the kernel to stop sending us stuff.
2297 if (!tx_queue
->num_txbdfree
) {
2298 netif_tx_stop_queue(txq
);
2300 dev
->stats
.tx_fifo_errors
++;
2303 /* Tell the DMA to go go go */
2304 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
>> tx_queue
->qindex
);
2307 spin_unlock_irqrestore(&tx_queue
->txlock
, flags
);
2309 return NETDEV_TX_OK
;
2312 /* Stops the kernel queue, and halts the controller */
2313 static int gfar_close(struct net_device
*dev
)
2315 struct gfar_private
*priv
= netdev_priv(dev
);
2319 cancel_work_sync(&priv
->reset_task
);
2322 /* Disconnect from the PHY */
2323 phy_disconnect(priv
->phydev
);
2324 priv
->phydev
= NULL
;
2326 netif_tx_stop_all_queues(dev
);
2331 /* Changes the mac address if the controller is not running. */
2332 static int gfar_set_mac_address(struct net_device
*dev
)
2334 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
2339 /* Check if rx parser should be activated */
2340 void gfar_check_rx_parser_mode(struct gfar_private
*priv
)
2342 struct gfar __iomem
*regs
;
2345 regs
= priv
->gfargrp
[0].regs
;
2347 tempval
= gfar_read(®s
->rctrl
);
2348 /* If parse is no longer required, then disable parser */
2349 if (tempval
& RCTRL_REQ_PARSER
) {
2350 tempval
|= RCTRL_PRSDEP_INIT
;
2351 priv
->uses_rxfcb
= 1;
2353 tempval
&= ~RCTRL_PRSDEP_INIT
;
2354 priv
->uses_rxfcb
= 0;
2356 gfar_write(®s
->rctrl
, tempval
);
2359 /* Enables and disables VLAN insertion/extraction */
2360 void gfar_vlan_mode(struct net_device
*dev
, netdev_features_t features
)
2362 struct gfar_private
*priv
= netdev_priv(dev
);
2363 struct gfar __iomem
*regs
= NULL
;
2364 unsigned long flags
;
2367 regs
= priv
->gfargrp
[0].regs
;
2368 local_irq_save(flags
);
2371 if (features
& NETIF_F_HW_VLAN_CTAG_TX
) {
2372 /* Enable VLAN tag insertion */
2373 tempval
= gfar_read(®s
->tctrl
);
2374 tempval
|= TCTRL_VLINS
;
2375 gfar_write(®s
->tctrl
, tempval
);
2377 /* Disable VLAN tag insertion */
2378 tempval
= gfar_read(®s
->tctrl
);
2379 tempval
&= ~TCTRL_VLINS
;
2380 gfar_write(®s
->tctrl
, tempval
);
2383 if (features
& NETIF_F_HW_VLAN_CTAG_RX
) {
2384 /* Enable VLAN tag extraction */
2385 tempval
= gfar_read(®s
->rctrl
);
2386 tempval
|= (RCTRL_VLEX
| RCTRL_PRSDEP_INIT
);
2387 gfar_write(®s
->rctrl
, tempval
);
2388 priv
->uses_rxfcb
= 1;
2390 /* Disable VLAN tag extraction */
2391 tempval
= gfar_read(®s
->rctrl
);
2392 tempval
&= ~RCTRL_VLEX
;
2393 gfar_write(®s
->rctrl
, tempval
);
2395 gfar_check_rx_parser_mode(priv
);
2398 gfar_change_mtu(dev
, dev
->mtu
);
2401 local_irq_restore(flags
);
2404 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
2406 int tempsize
, tempval
;
2407 struct gfar_private
*priv
= netdev_priv(dev
);
2408 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
2409 int oldsize
= priv
->rx_buffer_size
;
2410 int frame_size
= new_mtu
+ ETH_HLEN
;
2412 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
2413 netif_err(priv
, drv
, dev
, "Invalid MTU setting\n");
2417 if (priv
->uses_rxfcb
)
2418 frame_size
+= GMAC_FCB_LEN
;
2420 frame_size
+= priv
->padding
;
2422 tempsize
= (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
2423 INCREMENTAL_BUFFER_SIZE
;
2425 /* Only stop and start the controller if it isn't already
2426 * stopped, and we changed something
2428 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
2431 priv
->rx_buffer_size
= tempsize
;
2435 gfar_write(®s
->mrblr
, priv
->rx_buffer_size
);
2436 gfar_write(®s
->maxfrm
, priv
->rx_buffer_size
);
2438 /* If the mtu is larger than the max size for standard
2439 * ethernet frames (ie, a jumbo frame), then set maccfg2
2440 * to allow huge frames, and to check the length
2442 tempval
= gfar_read(®s
->maccfg2
);
2444 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
||
2445 gfar_has_errata(priv
, GFAR_ERRATA_74
))
2446 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
2448 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
2450 gfar_write(®s
->maccfg2
, tempval
);
2452 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
2458 /* gfar_reset_task gets scheduled when a packet has not been
2459 * transmitted after a set amount of time.
2460 * For now, assume that clearing out all the structures, and
2461 * starting over will fix the problem.
2463 static void gfar_reset_task(struct work_struct
*work
)
2465 struct gfar_private
*priv
= container_of(work
, struct gfar_private
,
2467 struct net_device
*dev
= priv
->ndev
;
2469 if (dev
->flags
& IFF_UP
) {
2470 netif_tx_stop_all_queues(dev
);
2473 netif_tx_start_all_queues(dev
);
2476 netif_tx_schedule_all(dev
);
2479 static void gfar_timeout(struct net_device
*dev
)
2481 struct gfar_private
*priv
= netdev_priv(dev
);
2483 dev
->stats
.tx_errors
++;
2484 schedule_work(&priv
->reset_task
);
2487 static void gfar_align_skb(struct sk_buff
*skb
)
2489 /* We need the data buffer to be aligned properly. We will reserve
2490 * as many bytes as needed to align the data properly
2492 skb_reserve(skb
, RXBUF_ALIGNMENT
-
2493 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1)));
2496 /* Interrupt Handler for Transmit complete */
2497 static void gfar_clean_tx_ring(struct gfar_priv_tx_q
*tx_queue
)
2499 struct net_device
*dev
= tx_queue
->dev
;
2500 struct netdev_queue
*txq
;
2501 struct gfar_private
*priv
= netdev_priv(dev
);
2502 struct txbd8
*bdp
, *next
= NULL
;
2503 struct txbd8
*lbdp
= NULL
;
2504 struct txbd8
*base
= tx_queue
->tx_bd_base
;
2505 struct sk_buff
*skb
;
2507 int tx_ring_size
= tx_queue
->tx_ring_size
;
2508 int frags
= 0, nr_txbds
= 0;
2511 int tqi
= tx_queue
->qindex
;
2512 unsigned int bytes_sent
= 0;
2516 txq
= netdev_get_tx_queue(dev
, tqi
);
2517 bdp
= tx_queue
->dirty_tx
;
2518 skb_dirtytx
= tx_queue
->skb_dirtytx
;
2520 while ((skb
= tx_queue
->tx_skbuff
[skb_dirtytx
])) {
2521 unsigned long flags
;
2523 frags
= skb_shinfo(skb
)->nr_frags
;
2525 /* When time stamping, one additional TxBD must be freed.
2526 * Also, we need to dma_unmap_single() the TxPAL.
2528 if (unlikely(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
))
2529 nr_txbds
= frags
+ 2;
2531 nr_txbds
= frags
+ 1;
2533 lbdp
= skip_txbd(bdp
, nr_txbds
- 1, base
, tx_ring_size
);
2535 lstatus
= lbdp
->lstatus
;
2537 /* Only clean completed frames */
2538 if ((lstatus
& BD_LFLAG(TXBD_READY
)) &&
2539 (lstatus
& BD_LENGTH_MASK
))
2542 if (unlikely(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
)) {
2543 next
= next_txbd(bdp
, base
, tx_ring_size
);
2544 buflen
= next
->length
+ GMAC_FCB_LEN
+ GMAC_TXPAL_LEN
;
2546 buflen
= bdp
->length
;
2548 dma_unmap_single(priv
->dev
, bdp
->bufPtr
,
2549 buflen
, DMA_TO_DEVICE
);
2551 if (unlikely(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
)) {
2552 struct skb_shared_hwtstamps shhwtstamps
;
2553 u64
*ns
= (u64
*) (((u32
)skb
->data
+ 0x10) & ~0x7);
2555 memset(&shhwtstamps
, 0, sizeof(shhwtstamps
));
2556 shhwtstamps
.hwtstamp
= ns_to_ktime(*ns
);
2557 skb_pull(skb
, GMAC_FCB_LEN
+ GMAC_TXPAL_LEN
);
2558 skb_tstamp_tx(skb
, &shhwtstamps
);
2559 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
2563 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
2564 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
2566 for (i
= 0; i
< frags
; i
++) {
2567 dma_unmap_page(priv
->dev
, bdp
->bufPtr
,
2568 bdp
->length
, DMA_TO_DEVICE
);
2569 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
2570 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
2573 bytes_sent
+= skb
->len
;
2575 dev_kfree_skb_any(skb
);
2577 tx_queue
->tx_skbuff
[skb_dirtytx
] = NULL
;
2579 skb_dirtytx
= (skb_dirtytx
+ 1) &
2580 TX_RING_MOD_MASK(tx_ring_size
);
2583 spin_lock_irqsave(&tx_queue
->txlock
, flags
);
2584 tx_queue
->num_txbdfree
+= nr_txbds
;
2585 spin_unlock_irqrestore(&tx_queue
->txlock
, flags
);
2588 /* If we freed a buffer, we can restart transmission, if necessary */
2589 if (netif_tx_queue_stopped(txq
) && tx_queue
->num_txbdfree
)
2590 netif_wake_subqueue(dev
, tqi
);
2592 /* Update dirty indicators */
2593 tx_queue
->skb_dirtytx
= skb_dirtytx
;
2594 tx_queue
->dirty_tx
= bdp
;
2596 netdev_tx_completed_queue(txq
, howmany
, bytes_sent
);
2599 static void gfar_schedule_cleanup(struct gfar_priv_grp
*gfargrp
)
2601 unsigned long flags
;
2603 spin_lock_irqsave(&gfargrp
->grplock
, flags
);
2604 if (napi_schedule_prep(&gfargrp
->napi
)) {
2605 gfar_write(&gfargrp
->regs
->imask
, IMASK_RTX_DISABLED
);
2606 __napi_schedule(&gfargrp
->napi
);
2608 /* Clear IEVENT, so interrupts aren't called again
2609 * because of the packets that have already arrived.
2611 gfar_write(&gfargrp
->regs
->ievent
, IEVENT_RTX_MASK
);
2613 spin_unlock_irqrestore(&gfargrp
->grplock
, flags
);
2617 /* Interrupt Handler for Transmit complete */
2618 static irqreturn_t
gfar_transmit(int irq
, void *grp_id
)
2620 gfar_schedule_cleanup((struct gfar_priv_grp
*)grp_id
);
2624 static void gfar_new_rxbdp(struct gfar_priv_rx_q
*rx_queue
, struct rxbd8
*bdp
,
2625 struct sk_buff
*skb
)
2627 struct net_device
*dev
= rx_queue
->dev
;
2628 struct gfar_private
*priv
= netdev_priv(dev
);
2631 buf
= dma_map_single(priv
->dev
, skb
->data
,
2632 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
2633 gfar_init_rxbdp(rx_queue
, bdp
, buf
);
2636 static struct sk_buff
*gfar_alloc_skb(struct net_device
*dev
)
2638 struct gfar_private
*priv
= netdev_priv(dev
);
2639 struct sk_buff
*skb
;
2641 skb
= netdev_alloc_skb(dev
, priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
2645 gfar_align_skb(skb
);
2650 struct sk_buff
*gfar_new_skb(struct net_device
*dev
)
2652 return gfar_alloc_skb(dev
);
2655 static inline void count_errors(unsigned short status
, struct net_device
*dev
)
2657 struct gfar_private
*priv
= netdev_priv(dev
);
2658 struct net_device_stats
*stats
= &dev
->stats
;
2659 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
2661 /* If the packet was truncated, none of the other errors matter */
2662 if (status
& RXBD_TRUNCATED
) {
2663 stats
->rx_length_errors
++;
2665 atomic64_inc(&estats
->rx_trunc
);
2669 /* Count the errors, if there were any */
2670 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
2671 stats
->rx_length_errors
++;
2673 if (status
& RXBD_LARGE
)
2674 atomic64_inc(&estats
->rx_large
);
2676 atomic64_inc(&estats
->rx_short
);
2678 if (status
& RXBD_NONOCTET
) {
2679 stats
->rx_frame_errors
++;
2680 atomic64_inc(&estats
->rx_nonoctet
);
2682 if (status
& RXBD_CRCERR
) {
2683 atomic64_inc(&estats
->rx_crcerr
);
2684 stats
->rx_crc_errors
++;
2686 if (status
& RXBD_OVERRUN
) {
2687 atomic64_inc(&estats
->rx_overrun
);
2688 stats
->rx_crc_errors
++;
2692 irqreturn_t
gfar_receive(int irq
, void *grp_id
)
2694 gfar_schedule_cleanup((struct gfar_priv_grp
*)grp_id
);
2698 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
2700 /* If valid headers were found, and valid sums
2701 * were verified, then we tell the kernel that no
2702 * checksumming is necessary. Otherwise, it is [FIXME]
2704 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
2705 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2707 skb_checksum_none_assert(skb
);
2711 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2712 static void gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
2713 int amount_pull
, struct napi_struct
*napi
)
2715 struct gfar_private
*priv
= netdev_priv(dev
);
2716 struct rxfcb
*fcb
= NULL
;
2718 /* fcb is at the beginning if exists */
2719 fcb
= (struct rxfcb
*)skb
->data
;
2721 /* Remove the FCB from the skb
2722 * Remove the padded bytes, if there are any
2725 skb_record_rx_queue(skb
, fcb
->rq
);
2726 skb_pull(skb
, amount_pull
);
2729 /* Get receive timestamp from the skb */
2730 if (priv
->hwts_rx_en
) {
2731 struct skb_shared_hwtstamps
*shhwtstamps
= skb_hwtstamps(skb
);
2732 u64
*ns
= (u64
*) skb
->data
;
2734 memset(shhwtstamps
, 0, sizeof(*shhwtstamps
));
2735 shhwtstamps
->hwtstamp
= ns_to_ktime(*ns
);
2739 skb_pull(skb
, priv
->padding
);
2741 if (dev
->features
& NETIF_F_RXCSUM
)
2742 gfar_rx_checksum(skb
, fcb
);
2744 /* Tell the skb what kind of packet this is */
2745 skb
->protocol
= eth_type_trans(skb
, dev
);
2747 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2748 * Even if vlan rx accel is disabled, on some chips
2749 * RXFCB_VLN is pseudo randomly set.
2751 if (dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
&&
2752 fcb
->flags
& RXFCB_VLN
)
2753 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), fcb
->vlctl
);
2755 /* Send the packet up the stack */
2756 napi_gro_receive(napi
, skb
);
2760 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2761 * until the budget/quota has been reached. Returns the number
2764 int gfar_clean_rx_ring(struct gfar_priv_rx_q
*rx_queue
, int rx_work_limit
)
2766 struct net_device
*dev
= rx_queue
->dev
;
2767 struct rxbd8
*bdp
, *base
;
2768 struct sk_buff
*skb
;
2772 struct gfar_private
*priv
= netdev_priv(dev
);
2774 /* Get the first full descriptor */
2775 bdp
= rx_queue
->cur_rx
;
2776 base
= rx_queue
->rx_bd_base
;
2778 amount_pull
= priv
->uses_rxfcb
? GMAC_FCB_LEN
: 0;
2780 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
2781 struct sk_buff
*newskb
;
2785 /* Add another skb for the future */
2786 newskb
= gfar_new_skb(dev
);
2788 skb
= rx_queue
->rx_skbuff
[rx_queue
->skb_currx
];
2790 dma_unmap_single(priv
->dev
, bdp
->bufPtr
,
2791 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
2793 if (unlikely(!(bdp
->status
& RXBD_ERR
) &&
2794 bdp
->length
> priv
->rx_buffer_size
))
2795 bdp
->status
= RXBD_LARGE
;
2797 /* We drop the frame if we failed to allocate a new buffer */
2798 if (unlikely(!newskb
|| !(bdp
->status
& RXBD_LAST
) ||
2799 bdp
->status
& RXBD_ERR
)) {
2800 count_errors(bdp
->status
, dev
);
2802 if (unlikely(!newskb
))
2807 /* Increment the number of packets */
2808 rx_queue
->stats
.rx_packets
++;
2812 pkt_len
= bdp
->length
- ETH_FCS_LEN
;
2813 /* Remove the FCS from the packet length */
2814 skb_put(skb
, pkt_len
);
2815 rx_queue
->stats
.rx_bytes
+= pkt_len
;
2816 skb_record_rx_queue(skb
, rx_queue
->qindex
);
2817 gfar_process_frame(dev
, skb
, amount_pull
,
2818 &rx_queue
->grp
->napi
);
2821 netif_warn(priv
, rx_err
, dev
, "Missing skb!\n");
2822 rx_queue
->stats
.rx_dropped
++;
2823 atomic64_inc(&priv
->extra_stats
.rx_skbmissing
);
2828 rx_queue
->rx_skbuff
[rx_queue
->skb_currx
] = newskb
;
2830 /* Setup the new bdp */
2831 gfar_new_rxbdp(rx_queue
, bdp
, newskb
);
2833 /* Update to the next pointer */
2834 bdp
= next_bd(bdp
, base
, rx_queue
->rx_ring_size
);
2836 /* update to point at the next skb */
2837 rx_queue
->skb_currx
= (rx_queue
->skb_currx
+ 1) &
2838 RX_RING_MOD_MASK(rx_queue
->rx_ring_size
);
2841 /* Update the current rxbd pointer to be the next one */
2842 rx_queue
->cur_rx
= bdp
;
2847 static int gfar_poll_sq(struct napi_struct
*napi
, int budget
)
2849 struct gfar_priv_grp
*gfargrp
=
2850 container_of(napi
, struct gfar_priv_grp
, napi
);
2851 struct gfar __iomem
*regs
= gfargrp
->regs
;
2852 struct gfar_priv_tx_q
*tx_queue
= gfargrp
->priv
->tx_queue
[0];
2853 struct gfar_priv_rx_q
*rx_queue
= gfargrp
->priv
->rx_queue
[0];
2856 /* Clear IEVENT, so interrupts aren't called again
2857 * because of the packets that have already arrived
2859 gfar_write(®s
->ievent
, IEVENT_RTX_MASK
);
2861 /* run Tx cleanup to completion */
2862 if (tx_queue
->tx_skbuff
[tx_queue
->skb_dirtytx
])
2863 gfar_clean_tx_ring(tx_queue
);
2865 work_done
= gfar_clean_rx_ring(rx_queue
, budget
);
2867 if (work_done
< budget
) {
2868 napi_complete(napi
);
2869 /* Clear the halt bit in RSTAT */
2870 gfar_write(®s
->rstat
, gfargrp
->rstat
);
2872 gfar_write(®s
->imask
, IMASK_DEFAULT
);
2874 /* If we are coalescing interrupts, update the timer
2875 * Otherwise, clear it
2877 gfar_write(®s
->txic
, 0);
2878 if (likely(tx_queue
->txcoalescing
))
2879 gfar_write(®s
->txic
, tx_queue
->txic
);
2881 gfar_write(®s
->rxic
, 0);
2882 if (unlikely(rx_queue
->rxcoalescing
))
2883 gfar_write(®s
->rxic
, rx_queue
->rxic
);
2889 static int gfar_poll(struct napi_struct
*napi
, int budget
)
2891 struct gfar_priv_grp
*gfargrp
=
2892 container_of(napi
, struct gfar_priv_grp
, napi
);
2893 struct gfar_private
*priv
= gfargrp
->priv
;
2894 struct gfar __iomem
*regs
= gfargrp
->regs
;
2895 struct gfar_priv_tx_q
*tx_queue
= NULL
;
2896 struct gfar_priv_rx_q
*rx_queue
= NULL
;
2897 int work_done
= 0, work_done_per_q
= 0;
2898 int i
, budget_per_q
= 0;
2900 unsigned long rstat_rxf
;
2903 /* Clear IEVENT, so interrupts aren't called again
2904 * because of the packets that have already arrived
2906 gfar_write(®s
->ievent
, IEVENT_RTX_MASK
);
2908 rstat_rxf
= gfar_read(®s
->rstat
) & RSTAT_RXF_MASK
;
2910 num_act_queues
= bitmap_weight(&rstat_rxf
, MAX_RX_QS
);
2912 budget_per_q
= budget
/num_act_queues
;
2916 for_each_set_bit(i
, &gfargrp
->tx_bit_map
, priv
->num_tx_queues
) {
2917 tx_queue
= priv
->tx_queue
[i
];
2918 /* run Tx cleanup to completion */
2919 if (tx_queue
->tx_skbuff
[tx_queue
->skb_dirtytx
]) {
2920 gfar_clean_tx_ring(tx_queue
);
2925 for_each_set_bit(i
, &gfargrp
->rx_bit_map
, priv
->num_rx_queues
) {
2926 /* skip queue if not active */
2927 if (!(rstat_rxf
& (RSTAT_CLEAR_RXF0
>> i
)))
2930 rx_queue
= priv
->rx_queue
[i
];
2932 gfar_clean_rx_ring(rx_queue
, budget_per_q
);
2933 work_done
+= work_done_per_q
;
2935 /* finished processing this queue */
2936 if (work_done_per_q
< budget_per_q
) {
2937 /* clear active queue hw indication */
2938 gfar_write(®s
->rstat
,
2939 RSTAT_CLEAR_RXF0
>> i
);
2940 rstat_rxf
&= ~(RSTAT_CLEAR_RXF0
>> i
);
2943 if (!num_act_queues
)
2945 /* recompute budget per Rx queue */
2947 (budget
- work_done
) / num_act_queues
;
2951 if (work_done
>= budget
)
2954 if (!num_act_queues
&& !has_tx_work
) {
2956 napi_complete(napi
);
2958 /* Clear the halt bit in RSTAT */
2959 gfar_write(®s
->rstat
, gfargrp
->rstat
);
2961 gfar_write(®s
->imask
, IMASK_DEFAULT
);
2963 /* If we are coalescing interrupts, update the timer
2964 * Otherwise, clear it
2966 gfar_configure_coalescing(priv
, gfargrp
->rx_bit_map
,
2967 gfargrp
->tx_bit_map
);
2975 #ifdef CONFIG_NET_POLL_CONTROLLER
2976 /* Polling 'interrupt' - used by things like netconsole to send skbs
2977 * without having to re-enable interrupts. It's not called while
2978 * the interrupt routine is executing.
2980 static void gfar_netpoll(struct net_device
*dev
)
2982 struct gfar_private
*priv
= netdev_priv(dev
);
2985 /* If the device has multiple interrupts, run tx/rx */
2986 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
2987 for (i
= 0; i
< priv
->num_grps
; i
++) {
2988 struct gfar_priv_grp
*grp
= &priv
->gfargrp
[i
];
2990 disable_irq(gfar_irq(grp
, TX
)->irq
);
2991 disable_irq(gfar_irq(grp
, RX
)->irq
);
2992 disable_irq(gfar_irq(grp
, ER
)->irq
);
2993 gfar_interrupt(gfar_irq(grp
, TX
)->irq
, grp
);
2994 enable_irq(gfar_irq(grp
, ER
)->irq
);
2995 enable_irq(gfar_irq(grp
, RX
)->irq
);
2996 enable_irq(gfar_irq(grp
, TX
)->irq
);
2999 for (i
= 0; i
< priv
->num_grps
; i
++) {
3000 struct gfar_priv_grp
*grp
= &priv
->gfargrp
[i
];
3002 disable_irq(gfar_irq(grp
, TX
)->irq
);
3003 gfar_interrupt(gfar_irq(grp
, TX
)->irq
, grp
);
3004 enable_irq(gfar_irq(grp
, TX
)->irq
);
3010 /* The interrupt handler for devices with one interrupt */
3011 static irqreturn_t
gfar_interrupt(int irq
, void *grp_id
)
3013 struct gfar_priv_grp
*gfargrp
= grp_id
;
3015 /* Save ievent for future reference */
3016 u32 events
= gfar_read(&gfargrp
->regs
->ievent
);
3018 /* Check for reception */
3019 if (events
& IEVENT_RX_MASK
)
3020 gfar_receive(irq
, grp_id
);
3022 /* Check for transmit completion */
3023 if (events
& IEVENT_TX_MASK
)
3024 gfar_transmit(irq
, grp_id
);
3026 /* Check for errors */
3027 if (events
& IEVENT_ERR_MASK
)
3028 gfar_error(irq
, grp_id
);
3033 static u32
gfar_get_flowctrl_cfg(struct gfar_private
*priv
)
3035 struct phy_device
*phydev
= priv
->phydev
;
3038 if (!phydev
->duplex
)
3041 if (!priv
->pause_aneg_en
) {
3042 if (priv
->tx_pause_en
)
3043 val
|= MACCFG1_TX_FLOW
;
3044 if (priv
->rx_pause_en
)
3045 val
|= MACCFG1_RX_FLOW
;
3047 u16 lcl_adv
, rmt_adv
;
3049 /* get link partner capabilities */
3052 rmt_adv
= LPA_PAUSE_CAP
;
3053 if (phydev
->asym_pause
)
3054 rmt_adv
|= LPA_PAUSE_ASYM
;
3056 lcl_adv
= mii_advertise_flowctrl(phydev
->advertising
);
3058 flowctrl
= mii_resolve_flowctrl_fdx(lcl_adv
, rmt_adv
);
3059 if (flowctrl
& FLOW_CTRL_TX
)
3060 val
|= MACCFG1_TX_FLOW
;
3061 if (flowctrl
& FLOW_CTRL_RX
)
3062 val
|= MACCFG1_RX_FLOW
;
3068 /* Called every time the controller might need to be made
3069 * aware of new link state. The PHY code conveys this
3070 * information through variables in the phydev structure, and this
3071 * function converts those variables into the appropriate
3072 * register values, and can bring down the device if needed.
3074 static void adjust_link(struct net_device
*dev
)
3076 struct gfar_private
*priv
= netdev_priv(dev
);
3077 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
3078 unsigned long flags
;
3079 struct phy_device
*phydev
= priv
->phydev
;
3082 local_irq_save(flags
);
3086 u32 tempval1
= gfar_read(®s
->maccfg1
);
3087 u32 tempval
= gfar_read(®s
->maccfg2
);
3088 u32 ecntrl
= gfar_read(®s
->ecntrl
);
3090 /* Now we make sure that we can be in full duplex mode.
3091 * If not, we operate in half-duplex mode.
3093 if (phydev
->duplex
!= priv
->oldduplex
) {
3095 if (!(phydev
->duplex
))
3096 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
3098 tempval
|= MACCFG2_FULL_DUPLEX
;
3100 priv
->oldduplex
= phydev
->duplex
;
3103 if (phydev
->speed
!= priv
->oldspeed
) {
3105 switch (phydev
->speed
) {
3108 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
3110 ecntrl
&= ~(ECNTRL_R100
);
3115 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
3117 /* Reduced mode distinguishes
3118 * between 10 and 100
3120 if (phydev
->speed
== SPEED_100
)
3121 ecntrl
|= ECNTRL_R100
;
3123 ecntrl
&= ~(ECNTRL_R100
);
3126 netif_warn(priv
, link
, dev
,
3127 "Ack! Speed (%d) is not 10/100/1000!\n",
3132 priv
->oldspeed
= phydev
->speed
;
3135 tempval1
&= ~(MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
3136 tempval1
|= gfar_get_flowctrl_cfg(priv
);
3138 gfar_write(®s
->maccfg1
, tempval1
);
3139 gfar_write(®s
->maccfg2
, tempval
);
3140 gfar_write(®s
->ecntrl
, ecntrl
);
3142 if (!priv
->oldlink
) {
3146 } else if (priv
->oldlink
) {
3150 priv
->oldduplex
= -1;
3153 if (new_state
&& netif_msg_link(priv
))
3154 phy_print_status(phydev
);
3156 local_irq_restore(flags
);
3159 /* Update the hash table based on the current list of multicast
3160 * addresses we subscribe to. Also, change the promiscuity of
3161 * the device based on the flags (this function is called
3162 * whenever dev->flags is changed
3164 static void gfar_set_multi(struct net_device
*dev
)
3166 struct netdev_hw_addr
*ha
;
3167 struct gfar_private
*priv
= netdev_priv(dev
);
3168 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
3171 if (dev
->flags
& IFF_PROMISC
) {
3172 /* Set RCTRL to PROM */
3173 tempval
= gfar_read(®s
->rctrl
);
3174 tempval
|= RCTRL_PROM
;
3175 gfar_write(®s
->rctrl
, tempval
);
3177 /* Set RCTRL to not PROM */
3178 tempval
= gfar_read(®s
->rctrl
);
3179 tempval
&= ~(RCTRL_PROM
);
3180 gfar_write(®s
->rctrl
, tempval
);
3183 if (dev
->flags
& IFF_ALLMULTI
) {
3184 /* Set the hash to rx all multicast frames */
3185 gfar_write(®s
->igaddr0
, 0xffffffff);
3186 gfar_write(®s
->igaddr1
, 0xffffffff);
3187 gfar_write(®s
->igaddr2
, 0xffffffff);
3188 gfar_write(®s
->igaddr3
, 0xffffffff);
3189 gfar_write(®s
->igaddr4
, 0xffffffff);
3190 gfar_write(®s
->igaddr5
, 0xffffffff);
3191 gfar_write(®s
->igaddr6
, 0xffffffff);
3192 gfar_write(®s
->igaddr7
, 0xffffffff);
3193 gfar_write(®s
->gaddr0
, 0xffffffff);
3194 gfar_write(®s
->gaddr1
, 0xffffffff);
3195 gfar_write(®s
->gaddr2
, 0xffffffff);
3196 gfar_write(®s
->gaddr3
, 0xffffffff);
3197 gfar_write(®s
->gaddr4
, 0xffffffff);
3198 gfar_write(®s
->gaddr5
, 0xffffffff);
3199 gfar_write(®s
->gaddr6
, 0xffffffff);
3200 gfar_write(®s
->gaddr7
, 0xffffffff);
3205 /* zero out the hash */
3206 gfar_write(®s
->igaddr0
, 0x0);
3207 gfar_write(®s
->igaddr1
, 0x0);
3208 gfar_write(®s
->igaddr2
, 0x0);
3209 gfar_write(®s
->igaddr3
, 0x0);
3210 gfar_write(®s
->igaddr4
, 0x0);
3211 gfar_write(®s
->igaddr5
, 0x0);
3212 gfar_write(®s
->igaddr6
, 0x0);
3213 gfar_write(®s
->igaddr7
, 0x0);
3214 gfar_write(®s
->gaddr0
, 0x0);
3215 gfar_write(®s
->gaddr1
, 0x0);
3216 gfar_write(®s
->gaddr2
, 0x0);
3217 gfar_write(®s
->gaddr3
, 0x0);
3218 gfar_write(®s
->gaddr4
, 0x0);
3219 gfar_write(®s
->gaddr5
, 0x0);
3220 gfar_write(®s
->gaddr6
, 0x0);
3221 gfar_write(®s
->gaddr7
, 0x0);
3223 /* If we have extended hash tables, we need to
3224 * clear the exact match registers to prepare for
3227 if (priv
->extended_hash
) {
3228 em_num
= GFAR_EM_NUM
+ 1;
3229 gfar_clear_exact_match(dev
);
3236 if (netdev_mc_empty(dev
))
3239 /* Parse the list, and set the appropriate bits */
3240 netdev_for_each_mc_addr(ha
, dev
) {
3242 gfar_set_mac_for_addr(dev
, idx
, ha
->addr
);
3245 gfar_set_hash_for_addr(dev
, ha
->addr
);
3251 /* Clears each of the exact match registers to zero, so they
3252 * don't interfere with normal reception
3254 static void gfar_clear_exact_match(struct net_device
*dev
)
3257 static const u8 zero_arr
[ETH_ALEN
] = {0, 0, 0, 0, 0, 0};
3259 for (idx
= 1; idx
< GFAR_EM_NUM
+ 1; idx
++)
3260 gfar_set_mac_for_addr(dev
, idx
, zero_arr
);
3263 /* Set the appropriate hash bit for the given addr */
3264 /* The algorithm works like so:
3265 * 1) Take the Destination Address (ie the multicast address), and
3266 * do a CRC on it (little endian), and reverse the bits of the
3268 * 2) Use the 8 most significant bits as a hash into a 256-entry
3269 * table. The table is controlled through 8 32-bit registers:
3270 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3271 * gaddr7. This means that the 3 most significant bits in the
3272 * hash index which gaddr register to use, and the 5 other bits
3273 * indicate which bit (assuming an IBM numbering scheme, which
3274 * for PowerPC (tm) is usually the case) in the register holds
3277 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
3280 struct gfar_private
*priv
= netdev_priv(dev
);
3281 u32 result
= ether_crc(ETH_ALEN
, addr
);
3282 int width
= priv
->hash_width
;
3283 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
3284 u8 whichreg
= result
>> (32 - width
+ 5);
3285 u32 value
= (1 << (31-whichbit
));
3287 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
3289 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
3293 /* There are multiple MAC Address register pairs on some controllers
3294 * This function sets the numth pair to a given address
3296 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
,
3299 struct gfar_private
*priv
= netdev_priv(dev
);
3300 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
3302 char tmpbuf
[ETH_ALEN
];
3304 u32 __iomem
*macptr
= ®s
->macstnaddr1
;
3308 /* Now copy it into the mac registers backwards, cuz
3309 * little endian is silly
3311 for (idx
= 0; idx
< ETH_ALEN
; idx
++)
3312 tmpbuf
[ETH_ALEN
- 1 - idx
] = addr
[idx
];
3314 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
3316 tempval
= *((u32
*) (tmpbuf
+ 4));
3318 gfar_write(macptr
+1, tempval
);
3321 /* GFAR error interrupt handler */
3322 static irqreturn_t
gfar_error(int irq
, void *grp_id
)
3324 struct gfar_priv_grp
*gfargrp
= grp_id
;
3325 struct gfar __iomem
*regs
= gfargrp
->regs
;
3326 struct gfar_private
*priv
= gfargrp
->priv
;
3327 struct net_device
*dev
= priv
->ndev
;
3329 /* Save ievent for future reference */
3330 u32 events
= gfar_read(®s
->ievent
);
3333 gfar_write(®s
->ievent
, events
& IEVENT_ERR_MASK
);
3335 /* Magic Packet is not an error. */
3336 if ((priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
) &&
3337 (events
& IEVENT_MAG
))
3338 events
&= ~IEVENT_MAG
;
3341 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
3343 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3344 events
, gfar_read(®s
->imask
));
3346 /* Update the error counters */
3347 if (events
& IEVENT_TXE
) {
3348 dev
->stats
.tx_errors
++;
3350 if (events
& IEVENT_LC
)
3351 dev
->stats
.tx_window_errors
++;
3352 if (events
& IEVENT_CRL
)
3353 dev
->stats
.tx_aborted_errors
++;
3354 if (events
& IEVENT_XFUN
) {
3355 unsigned long flags
;
3357 netif_dbg(priv
, tx_err
, dev
,
3358 "TX FIFO underrun, packet dropped\n");
3359 dev
->stats
.tx_dropped
++;
3360 atomic64_inc(&priv
->extra_stats
.tx_underrun
);
3362 local_irq_save(flags
);
3365 /* Reactivate the Tx Queues */
3366 gfar_write(®s
->tstat
, gfargrp
->tstat
);
3369 local_irq_restore(flags
);
3371 netif_dbg(priv
, tx_err
, dev
, "Transmit Error\n");
3373 if (events
& IEVENT_BSY
) {
3374 dev
->stats
.rx_errors
++;
3375 atomic64_inc(&priv
->extra_stats
.rx_bsy
);
3377 gfar_receive(irq
, grp_id
);
3379 netif_dbg(priv
, rx_err
, dev
, "busy error (rstat: %x)\n",
3380 gfar_read(®s
->rstat
));
3382 if (events
& IEVENT_BABR
) {
3383 dev
->stats
.rx_errors
++;
3384 atomic64_inc(&priv
->extra_stats
.rx_babr
);
3386 netif_dbg(priv
, rx_err
, dev
, "babbling RX error\n");
3388 if (events
& IEVENT_EBERR
) {
3389 atomic64_inc(&priv
->extra_stats
.eberr
);
3390 netif_dbg(priv
, rx_err
, dev
, "bus error\n");
3392 if (events
& IEVENT_RXC
)
3393 netif_dbg(priv
, rx_status
, dev
, "control frame\n");
3395 if (events
& IEVENT_BABT
) {
3396 atomic64_inc(&priv
->extra_stats
.tx_babt
);
3397 netif_dbg(priv
, tx_err
, dev
, "babbling TX error\n");
3402 static struct of_device_id gfar_match
[] =
3406 .compatible
= "gianfar",
3409 .compatible
= "fsl,etsec2",
3413 MODULE_DEVICE_TABLE(of
, gfar_match
);
3415 /* Structure for a device driver */
3416 static struct platform_driver gfar_driver
= {
3418 .name
= "fsl-gianfar",
3419 .owner
= THIS_MODULE
,
3421 .of_match_table
= gfar_match
,
3423 .probe
= gfar_probe
,
3424 .remove
= gfar_remove
,
3427 module_platform_driver(gfar_driver
);