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drivers: clean-up prom.h implicit includes
[deliverable/linux.git] / drivers / net / ethernet / freescale / gianfar.c
1 /* drivers/net/ethernet/freescale/gianfar.c
2 *
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
11 *
12 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
27 *
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
30 *
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
36 *
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
52 * skb.
53 *
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
62 */
63
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65 #define DEBUG
66
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
80 #include <linux/mm.h>
81 #include <linux/of_address.h>
82 #include <linux/of_irq.h>
83 #include <linux/of_mdio.h>
84 #include <linux/of_platform.h>
85 #include <linux/ip.h>
86 #include <linux/tcp.h>
87 #include <linux/udp.h>
88 #include <linux/in.h>
89 #include <linux/net_tstamp.h>
90
91 #include <asm/io.h>
92 #include <asm/reg.h>
93 #include <asm/irq.h>
94 #include <asm/uaccess.h>
95 #include <linux/module.h>
96 #include <linux/dma-mapping.h>
97 #include <linux/crc32.h>
98 #include <linux/mii.h>
99 #include <linux/phy.h>
100 #include <linux/phy_fixed.h>
101 #include <linux/of.h>
102 #include <linux/of_net.h>
103
104 #include "gianfar.h"
105
106 #define TX_TIMEOUT (1*HZ)
107
108 const char gfar_driver_version[] = "1.3";
109
110 static int gfar_enet_open(struct net_device *dev);
111 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
112 static void gfar_reset_task(struct work_struct *work);
113 static void gfar_timeout(struct net_device *dev);
114 static int gfar_close(struct net_device *dev);
115 struct sk_buff *gfar_new_skb(struct net_device *dev);
116 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
117 struct sk_buff *skb);
118 static int gfar_set_mac_address(struct net_device *dev);
119 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
120 static irqreturn_t gfar_error(int irq, void *dev_id);
121 static irqreturn_t gfar_transmit(int irq, void *dev_id);
122 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
123 static void adjust_link(struct net_device *dev);
124 static void init_registers(struct net_device *dev);
125 static int init_phy(struct net_device *dev);
126 static int gfar_probe(struct platform_device *ofdev);
127 static int gfar_remove(struct platform_device *ofdev);
128 static void free_skb_resources(struct gfar_private *priv);
129 static void gfar_set_multi(struct net_device *dev);
130 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
131 static void gfar_configure_serdes(struct net_device *dev);
132 static int gfar_poll(struct napi_struct *napi, int budget);
133 static int gfar_poll_sq(struct napi_struct *napi, int budget);
134 #ifdef CONFIG_NET_POLL_CONTROLLER
135 static void gfar_netpoll(struct net_device *dev);
136 #endif
137 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
138 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
139 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
140 int amount_pull, struct napi_struct *napi);
141 void gfar_halt(struct net_device *dev);
142 static void gfar_halt_nodisable(struct net_device *dev);
143 void gfar_start(struct net_device *dev);
144 static void gfar_clear_exact_match(struct net_device *dev);
145 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
146 const u8 *addr);
147 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
148
149 MODULE_AUTHOR("Freescale Semiconductor, Inc");
150 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
151 MODULE_LICENSE("GPL");
152
153 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
154 dma_addr_t buf)
155 {
156 u32 lstatus;
157
158 bdp->bufPtr = buf;
159
160 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
161 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
162 lstatus |= BD_LFLAG(RXBD_WRAP);
163
164 eieio();
165
166 bdp->lstatus = lstatus;
167 }
168
169 static int gfar_init_bds(struct net_device *ndev)
170 {
171 struct gfar_private *priv = netdev_priv(ndev);
172 struct gfar_priv_tx_q *tx_queue = NULL;
173 struct gfar_priv_rx_q *rx_queue = NULL;
174 struct txbd8 *txbdp;
175 struct rxbd8 *rxbdp;
176 int i, j;
177
178 for (i = 0; i < priv->num_tx_queues; i++) {
179 tx_queue = priv->tx_queue[i];
180 /* Initialize some variables in our dev structure */
181 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
182 tx_queue->dirty_tx = tx_queue->tx_bd_base;
183 tx_queue->cur_tx = tx_queue->tx_bd_base;
184 tx_queue->skb_curtx = 0;
185 tx_queue->skb_dirtytx = 0;
186
187 /* Initialize Transmit Descriptor Ring */
188 txbdp = tx_queue->tx_bd_base;
189 for (j = 0; j < tx_queue->tx_ring_size; j++) {
190 txbdp->lstatus = 0;
191 txbdp->bufPtr = 0;
192 txbdp++;
193 }
194
195 /* Set the last descriptor in the ring to indicate wrap */
196 txbdp--;
197 txbdp->status |= TXBD_WRAP;
198 }
199
200 for (i = 0; i < priv->num_rx_queues; i++) {
201 rx_queue = priv->rx_queue[i];
202 rx_queue->cur_rx = rx_queue->rx_bd_base;
203 rx_queue->skb_currx = 0;
204 rxbdp = rx_queue->rx_bd_base;
205
206 for (j = 0; j < rx_queue->rx_ring_size; j++) {
207 struct sk_buff *skb = rx_queue->rx_skbuff[j];
208
209 if (skb) {
210 gfar_init_rxbdp(rx_queue, rxbdp,
211 rxbdp->bufPtr);
212 } else {
213 skb = gfar_new_skb(ndev);
214 if (!skb) {
215 netdev_err(ndev, "Can't allocate RX buffers\n");
216 return -ENOMEM;
217 }
218 rx_queue->rx_skbuff[j] = skb;
219
220 gfar_new_rxbdp(rx_queue, rxbdp, skb);
221 }
222
223 rxbdp++;
224 }
225
226 }
227
228 return 0;
229 }
230
231 static int gfar_alloc_skb_resources(struct net_device *ndev)
232 {
233 void *vaddr;
234 dma_addr_t addr;
235 int i, j, k;
236 struct gfar_private *priv = netdev_priv(ndev);
237 struct device *dev = priv->dev;
238 struct gfar_priv_tx_q *tx_queue = NULL;
239 struct gfar_priv_rx_q *rx_queue = NULL;
240
241 priv->total_tx_ring_size = 0;
242 for (i = 0; i < priv->num_tx_queues; i++)
243 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
244
245 priv->total_rx_ring_size = 0;
246 for (i = 0; i < priv->num_rx_queues; i++)
247 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
248
249 /* Allocate memory for the buffer descriptors */
250 vaddr = dma_alloc_coherent(dev,
251 (priv->total_tx_ring_size *
252 sizeof(struct txbd8)) +
253 (priv->total_rx_ring_size *
254 sizeof(struct rxbd8)),
255 &addr, GFP_KERNEL);
256 if (!vaddr)
257 return -ENOMEM;
258
259 for (i = 0; i < priv->num_tx_queues; i++) {
260 tx_queue = priv->tx_queue[i];
261 tx_queue->tx_bd_base = vaddr;
262 tx_queue->tx_bd_dma_base = addr;
263 tx_queue->dev = ndev;
264 /* enet DMA only understands physical addresses */
265 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
266 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
267 }
268
269 /* Start the rx descriptor ring where the tx ring leaves off */
270 for (i = 0; i < priv->num_rx_queues; i++) {
271 rx_queue = priv->rx_queue[i];
272 rx_queue->rx_bd_base = vaddr;
273 rx_queue->rx_bd_dma_base = addr;
274 rx_queue->dev = ndev;
275 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
276 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
277 }
278
279 /* Setup the skbuff rings */
280 for (i = 0; i < priv->num_tx_queues; i++) {
281 tx_queue = priv->tx_queue[i];
282 tx_queue->tx_skbuff =
283 kmalloc_array(tx_queue->tx_ring_size,
284 sizeof(*tx_queue->tx_skbuff),
285 GFP_KERNEL);
286 if (!tx_queue->tx_skbuff)
287 goto cleanup;
288
289 for (k = 0; k < tx_queue->tx_ring_size; k++)
290 tx_queue->tx_skbuff[k] = NULL;
291 }
292
293 for (i = 0; i < priv->num_rx_queues; i++) {
294 rx_queue = priv->rx_queue[i];
295 rx_queue->rx_skbuff =
296 kmalloc_array(rx_queue->rx_ring_size,
297 sizeof(*rx_queue->rx_skbuff),
298 GFP_KERNEL);
299 if (!rx_queue->rx_skbuff)
300 goto cleanup;
301
302 for (j = 0; j < rx_queue->rx_ring_size; j++)
303 rx_queue->rx_skbuff[j] = NULL;
304 }
305
306 if (gfar_init_bds(ndev))
307 goto cleanup;
308
309 return 0;
310
311 cleanup:
312 free_skb_resources(priv);
313 return -ENOMEM;
314 }
315
316 static void gfar_init_tx_rx_base(struct gfar_private *priv)
317 {
318 struct gfar __iomem *regs = priv->gfargrp[0].regs;
319 u32 __iomem *baddr;
320 int i;
321
322 baddr = &regs->tbase0;
323 for (i = 0; i < priv->num_tx_queues; i++) {
324 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
325 baddr += 2;
326 }
327
328 baddr = &regs->rbase0;
329 for (i = 0; i < priv->num_rx_queues; i++) {
330 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
331 baddr += 2;
332 }
333 }
334
335 static void gfar_init_mac(struct net_device *ndev)
336 {
337 struct gfar_private *priv = netdev_priv(ndev);
338 struct gfar __iomem *regs = priv->gfargrp[0].regs;
339 u32 rctrl = 0;
340 u32 tctrl = 0;
341 u32 attrs = 0;
342
343 /* write the tx/rx base registers */
344 gfar_init_tx_rx_base(priv);
345
346 /* Configure the coalescing support */
347 gfar_configure_coalescing_all(priv);
348
349 /* set this when rx hw offload (TOE) functions are being used */
350 priv->uses_rxfcb = 0;
351
352 if (priv->rx_filer_enable) {
353 rctrl |= RCTRL_FILREN;
354 /* Program the RIR0 reg with the required distribution */
355 gfar_write(&regs->rir0, DEFAULT_RIR0);
356 }
357
358 /* Restore PROMISC mode */
359 if (ndev->flags & IFF_PROMISC)
360 rctrl |= RCTRL_PROM;
361
362 if (ndev->features & NETIF_F_RXCSUM) {
363 rctrl |= RCTRL_CHECKSUMMING;
364 priv->uses_rxfcb = 1;
365 }
366
367 if (priv->extended_hash) {
368 rctrl |= RCTRL_EXTHASH;
369
370 gfar_clear_exact_match(ndev);
371 rctrl |= RCTRL_EMEN;
372 }
373
374 if (priv->padding) {
375 rctrl &= ~RCTRL_PAL_MASK;
376 rctrl |= RCTRL_PADDING(priv->padding);
377 }
378
379 /* Insert receive time stamps into padding alignment bytes */
380 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
381 rctrl &= ~RCTRL_PAL_MASK;
382 rctrl |= RCTRL_PADDING(8);
383 priv->padding = 8;
384 }
385
386 /* Enable HW time stamping if requested from user space */
387 if (priv->hwts_rx_en) {
388 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
389 priv->uses_rxfcb = 1;
390 }
391
392 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) {
393 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
394 priv->uses_rxfcb = 1;
395 }
396
397 /* Init rctrl based on our settings */
398 gfar_write(&regs->rctrl, rctrl);
399
400 if (ndev->features & NETIF_F_IP_CSUM)
401 tctrl |= TCTRL_INIT_CSUM;
402
403 if (priv->prio_sched_en)
404 tctrl |= TCTRL_TXSCHED_PRIO;
405 else {
406 tctrl |= TCTRL_TXSCHED_WRRS;
407 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
408 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
409 }
410
411 gfar_write(&regs->tctrl, tctrl);
412
413 /* Set the extraction length and index */
414 attrs = ATTRELI_EL(priv->rx_stash_size) |
415 ATTRELI_EI(priv->rx_stash_index);
416
417 gfar_write(&regs->attreli, attrs);
418
419 /* Start with defaults, and add stashing or locking
420 * depending on the approprate variables
421 */
422 attrs = ATTR_INIT_SETTINGS;
423
424 if (priv->bd_stash_en)
425 attrs |= ATTR_BDSTASH;
426
427 if (priv->rx_stash_size != 0)
428 attrs |= ATTR_BUFSTASH;
429
430 gfar_write(&regs->attr, attrs);
431
432 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
433 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
434 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
435 }
436
437 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
438 {
439 struct gfar_private *priv = netdev_priv(dev);
440 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
441 unsigned long tx_packets = 0, tx_bytes = 0;
442 int i;
443
444 for (i = 0; i < priv->num_rx_queues; i++) {
445 rx_packets += priv->rx_queue[i]->stats.rx_packets;
446 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
447 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
448 }
449
450 dev->stats.rx_packets = rx_packets;
451 dev->stats.rx_bytes = rx_bytes;
452 dev->stats.rx_dropped = rx_dropped;
453
454 for (i = 0; i < priv->num_tx_queues; i++) {
455 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
456 tx_packets += priv->tx_queue[i]->stats.tx_packets;
457 }
458
459 dev->stats.tx_bytes = tx_bytes;
460 dev->stats.tx_packets = tx_packets;
461
462 return &dev->stats;
463 }
464
465 static const struct net_device_ops gfar_netdev_ops = {
466 .ndo_open = gfar_enet_open,
467 .ndo_start_xmit = gfar_start_xmit,
468 .ndo_stop = gfar_close,
469 .ndo_change_mtu = gfar_change_mtu,
470 .ndo_set_features = gfar_set_features,
471 .ndo_set_rx_mode = gfar_set_multi,
472 .ndo_tx_timeout = gfar_timeout,
473 .ndo_do_ioctl = gfar_ioctl,
474 .ndo_get_stats = gfar_get_stats,
475 .ndo_set_mac_address = eth_mac_addr,
476 .ndo_validate_addr = eth_validate_addr,
477 #ifdef CONFIG_NET_POLL_CONTROLLER
478 .ndo_poll_controller = gfar_netpoll,
479 #endif
480 };
481
482 void lock_rx_qs(struct gfar_private *priv)
483 {
484 int i;
485
486 for (i = 0; i < priv->num_rx_queues; i++)
487 spin_lock(&priv->rx_queue[i]->rxlock);
488 }
489
490 void lock_tx_qs(struct gfar_private *priv)
491 {
492 int i;
493
494 for (i = 0; i < priv->num_tx_queues; i++)
495 spin_lock(&priv->tx_queue[i]->txlock);
496 }
497
498 void unlock_rx_qs(struct gfar_private *priv)
499 {
500 int i;
501
502 for (i = 0; i < priv->num_rx_queues; i++)
503 spin_unlock(&priv->rx_queue[i]->rxlock);
504 }
505
506 void unlock_tx_qs(struct gfar_private *priv)
507 {
508 int i;
509
510 for (i = 0; i < priv->num_tx_queues; i++)
511 spin_unlock(&priv->tx_queue[i]->txlock);
512 }
513
514 static void free_tx_pointers(struct gfar_private *priv)
515 {
516 int i;
517
518 for (i = 0; i < priv->num_tx_queues; i++)
519 kfree(priv->tx_queue[i]);
520 }
521
522 static void free_rx_pointers(struct gfar_private *priv)
523 {
524 int i;
525
526 for (i = 0; i < priv->num_rx_queues; i++)
527 kfree(priv->rx_queue[i]);
528 }
529
530 static void unmap_group_regs(struct gfar_private *priv)
531 {
532 int i;
533
534 for (i = 0; i < MAXGROUPS; i++)
535 if (priv->gfargrp[i].regs)
536 iounmap(priv->gfargrp[i].regs);
537 }
538
539 static void free_gfar_dev(struct gfar_private *priv)
540 {
541 int i, j;
542
543 for (i = 0; i < priv->num_grps; i++)
544 for (j = 0; j < GFAR_NUM_IRQS; j++) {
545 kfree(priv->gfargrp[i].irqinfo[j]);
546 priv->gfargrp[i].irqinfo[j] = NULL;
547 }
548
549 free_netdev(priv->ndev);
550 }
551
552 static void disable_napi(struct gfar_private *priv)
553 {
554 int i;
555
556 for (i = 0; i < priv->num_grps; i++)
557 napi_disable(&priv->gfargrp[i].napi);
558 }
559
560 static void enable_napi(struct gfar_private *priv)
561 {
562 int i;
563
564 for (i = 0; i < priv->num_grps; i++)
565 napi_enable(&priv->gfargrp[i].napi);
566 }
567
568 static int gfar_parse_group(struct device_node *np,
569 struct gfar_private *priv, const char *model)
570 {
571 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
572 u32 *queue_mask;
573 int i;
574
575 for (i = 0; i < GFAR_NUM_IRQS; i++) {
576 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
577 GFP_KERNEL);
578 if (!grp->irqinfo[i])
579 return -ENOMEM;
580 }
581
582 grp->regs = of_iomap(np, 0);
583 if (!grp->regs)
584 return -ENOMEM;
585
586 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
587
588 /* If we aren't the FEC we have multiple interrupts */
589 if (model && strcasecmp(model, "FEC")) {
590 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
591 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
592 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
593 gfar_irq(grp, RX)->irq == NO_IRQ ||
594 gfar_irq(grp, ER)->irq == NO_IRQ)
595 return -EINVAL;
596 }
597
598 grp->priv = priv;
599 spin_lock_init(&grp->grplock);
600 if (priv->mode == MQ_MG_MODE) {
601 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
602 grp->rx_bit_map = queue_mask ?
603 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
604 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
605 grp->tx_bit_map = queue_mask ?
606 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
607 } else {
608 grp->rx_bit_map = 0xFF;
609 grp->tx_bit_map = 0xFF;
610 }
611 priv->num_grps++;
612
613 return 0;
614 }
615
616 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
617 {
618 const char *model;
619 const char *ctype;
620 const void *mac_addr;
621 int err = 0, i;
622 struct net_device *dev = NULL;
623 struct gfar_private *priv = NULL;
624 struct device_node *np = ofdev->dev.of_node;
625 struct device_node *child = NULL;
626 const u32 *stash;
627 const u32 *stash_len;
628 const u32 *stash_idx;
629 unsigned int num_tx_qs, num_rx_qs;
630 u32 *tx_queues, *rx_queues;
631
632 if (!np || !of_device_is_available(np))
633 return -ENODEV;
634
635 /* parse the num of tx and rx queues */
636 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
637 num_tx_qs = tx_queues ? *tx_queues : 1;
638
639 if (num_tx_qs > MAX_TX_QS) {
640 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
641 num_tx_qs, MAX_TX_QS);
642 pr_err("Cannot do alloc_etherdev, aborting\n");
643 return -EINVAL;
644 }
645
646 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
647 num_rx_qs = rx_queues ? *rx_queues : 1;
648
649 if (num_rx_qs > MAX_RX_QS) {
650 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
651 num_rx_qs, MAX_RX_QS);
652 pr_err("Cannot do alloc_etherdev, aborting\n");
653 return -EINVAL;
654 }
655
656 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
657 dev = *pdev;
658 if (NULL == dev)
659 return -ENOMEM;
660
661 priv = netdev_priv(dev);
662 priv->ndev = dev;
663
664 priv->num_tx_queues = num_tx_qs;
665 netif_set_real_num_rx_queues(dev, num_rx_qs);
666 priv->num_rx_queues = num_rx_qs;
667 priv->num_grps = 0x0;
668
669 /* Init Rx queue filer rule set linked list */
670 INIT_LIST_HEAD(&priv->rx_list.list);
671 priv->rx_list.count = 0;
672 mutex_init(&priv->rx_queue_access);
673
674 model = of_get_property(np, "model", NULL);
675
676 for (i = 0; i < MAXGROUPS; i++)
677 priv->gfargrp[i].regs = NULL;
678
679 /* Parse and initialize group specific information */
680 if (of_device_is_compatible(np, "fsl,etsec2")) {
681 priv->mode = MQ_MG_MODE;
682 for_each_child_of_node(np, child) {
683 err = gfar_parse_group(child, priv, model);
684 if (err)
685 goto err_grp_init;
686 }
687 } else {
688 priv->mode = SQ_SG_MODE;
689 err = gfar_parse_group(np, priv, model);
690 if (err)
691 goto err_grp_init;
692 }
693
694 for (i = 0; i < priv->num_tx_queues; i++)
695 priv->tx_queue[i] = NULL;
696 for (i = 0; i < priv->num_rx_queues; i++)
697 priv->rx_queue[i] = NULL;
698
699 for (i = 0; i < priv->num_tx_queues; i++) {
700 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
701 GFP_KERNEL);
702 if (!priv->tx_queue[i]) {
703 err = -ENOMEM;
704 goto tx_alloc_failed;
705 }
706 priv->tx_queue[i]->tx_skbuff = NULL;
707 priv->tx_queue[i]->qindex = i;
708 priv->tx_queue[i]->dev = dev;
709 spin_lock_init(&(priv->tx_queue[i]->txlock));
710 }
711
712 for (i = 0; i < priv->num_rx_queues; i++) {
713 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
714 GFP_KERNEL);
715 if (!priv->rx_queue[i]) {
716 err = -ENOMEM;
717 goto rx_alloc_failed;
718 }
719 priv->rx_queue[i]->rx_skbuff = NULL;
720 priv->rx_queue[i]->qindex = i;
721 priv->rx_queue[i]->dev = dev;
722 spin_lock_init(&(priv->rx_queue[i]->rxlock));
723 }
724
725
726 stash = of_get_property(np, "bd-stash", NULL);
727
728 if (stash) {
729 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
730 priv->bd_stash_en = 1;
731 }
732
733 stash_len = of_get_property(np, "rx-stash-len", NULL);
734
735 if (stash_len)
736 priv->rx_stash_size = *stash_len;
737
738 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
739
740 if (stash_idx)
741 priv->rx_stash_index = *stash_idx;
742
743 if (stash_len || stash_idx)
744 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
745
746 mac_addr = of_get_mac_address(np);
747
748 if (mac_addr)
749 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
750
751 if (model && !strcasecmp(model, "TSEC"))
752 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
753 FSL_GIANFAR_DEV_HAS_COALESCE |
754 FSL_GIANFAR_DEV_HAS_RMON |
755 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
756
757 if (model && !strcasecmp(model, "eTSEC"))
758 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
759 FSL_GIANFAR_DEV_HAS_COALESCE |
760 FSL_GIANFAR_DEV_HAS_RMON |
761 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
762 FSL_GIANFAR_DEV_HAS_PADDING |
763 FSL_GIANFAR_DEV_HAS_CSUM |
764 FSL_GIANFAR_DEV_HAS_VLAN |
765 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
766 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
767 FSL_GIANFAR_DEV_HAS_TIMER;
768
769 ctype = of_get_property(np, "phy-connection-type", NULL);
770
771 /* We only care about rgmii-id. The rest are autodetected */
772 if (ctype && !strcmp(ctype, "rgmii-id"))
773 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
774 else
775 priv->interface = PHY_INTERFACE_MODE_MII;
776
777 if (of_get_property(np, "fsl,magic-packet", NULL))
778 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
779
780 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
781
782 /* Find the TBI PHY. If it's not there, we don't support SGMII */
783 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
784
785 return 0;
786
787 rx_alloc_failed:
788 free_rx_pointers(priv);
789 tx_alloc_failed:
790 free_tx_pointers(priv);
791 err_grp_init:
792 unmap_group_regs(priv);
793 free_gfar_dev(priv);
794 return err;
795 }
796
797 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
798 struct ifreq *ifr, int cmd)
799 {
800 struct hwtstamp_config config;
801 struct gfar_private *priv = netdev_priv(netdev);
802
803 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
804 return -EFAULT;
805
806 /* reserved for future extensions */
807 if (config.flags)
808 return -EINVAL;
809
810 switch (config.tx_type) {
811 case HWTSTAMP_TX_OFF:
812 priv->hwts_tx_en = 0;
813 break;
814 case HWTSTAMP_TX_ON:
815 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
816 return -ERANGE;
817 priv->hwts_tx_en = 1;
818 break;
819 default:
820 return -ERANGE;
821 }
822
823 switch (config.rx_filter) {
824 case HWTSTAMP_FILTER_NONE:
825 if (priv->hwts_rx_en) {
826 stop_gfar(netdev);
827 priv->hwts_rx_en = 0;
828 startup_gfar(netdev);
829 }
830 break;
831 default:
832 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
833 return -ERANGE;
834 if (!priv->hwts_rx_en) {
835 stop_gfar(netdev);
836 priv->hwts_rx_en = 1;
837 startup_gfar(netdev);
838 }
839 config.rx_filter = HWTSTAMP_FILTER_ALL;
840 break;
841 }
842
843 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
844 -EFAULT : 0;
845 }
846
847 /* Ioctl MII Interface */
848 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
849 {
850 struct gfar_private *priv = netdev_priv(dev);
851
852 if (!netif_running(dev))
853 return -EINVAL;
854
855 if (cmd == SIOCSHWTSTAMP)
856 return gfar_hwtstamp_ioctl(dev, rq, cmd);
857
858 if (!priv->phydev)
859 return -ENODEV;
860
861 return phy_mii_ioctl(priv->phydev, rq, cmd);
862 }
863
864 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
865 {
866 unsigned int new_bit_map = 0x0;
867 int mask = 0x1 << (max_qs - 1), i;
868
869 for (i = 0; i < max_qs; i++) {
870 if (bit_map & mask)
871 new_bit_map = new_bit_map + (1 << i);
872 mask = mask >> 0x1;
873 }
874 return new_bit_map;
875 }
876
877 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
878 u32 class)
879 {
880 u32 rqfpr = FPR_FILER_MASK;
881 u32 rqfcr = 0x0;
882
883 rqfar--;
884 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
885 priv->ftp_rqfpr[rqfar] = rqfpr;
886 priv->ftp_rqfcr[rqfar] = rqfcr;
887 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
888
889 rqfar--;
890 rqfcr = RQFCR_CMP_NOMATCH;
891 priv->ftp_rqfpr[rqfar] = rqfpr;
892 priv->ftp_rqfcr[rqfar] = rqfcr;
893 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
894
895 rqfar--;
896 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
897 rqfpr = class;
898 priv->ftp_rqfcr[rqfar] = rqfcr;
899 priv->ftp_rqfpr[rqfar] = rqfpr;
900 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
901
902 rqfar--;
903 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
904 rqfpr = class;
905 priv->ftp_rqfcr[rqfar] = rqfcr;
906 priv->ftp_rqfpr[rqfar] = rqfpr;
907 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
908
909 return rqfar;
910 }
911
912 static void gfar_init_filer_table(struct gfar_private *priv)
913 {
914 int i = 0x0;
915 u32 rqfar = MAX_FILER_IDX;
916 u32 rqfcr = 0x0;
917 u32 rqfpr = FPR_FILER_MASK;
918
919 /* Default rule */
920 rqfcr = RQFCR_CMP_MATCH;
921 priv->ftp_rqfcr[rqfar] = rqfcr;
922 priv->ftp_rqfpr[rqfar] = rqfpr;
923 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
924
925 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
926 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
927 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
928 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
929 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
930 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
931
932 /* cur_filer_idx indicated the first non-masked rule */
933 priv->cur_filer_idx = rqfar;
934
935 /* Rest are masked rules */
936 rqfcr = RQFCR_CMP_NOMATCH;
937 for (i = 0; i < rqfar; i++) {
938 priv->ftp_rqfcr[i] = rqfcr;
939 priv->ftp_rqfpr[i] = rqfpr;
940 gfar_write_filer(priv, i, rqfcr, rqfpr);
941 }
942 }
943
944 static void gfar_detect_errata(struct gfar_private *priv)
945 {
946 struct device *dev = &priv->ofdev->dev;
947 unsigned int pvr = mfspr(SPRN_PVR);
948 unsigned int svr = mfspr(SPRN_SVR);
949 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
950 unsigned int rev = svr & 0xffff;
951
952 /* MPC8313 Rev 2.0 and higher; All MPC837x */
953 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
954 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
955 priv->errata |= GFAR_ERRATA_74;
956
957 /* MPC8313 and MPC837x all rev */
958 if ((pvr == 0x80850010 && mod == 0x80b0) ||
959 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
960 priv->errata |= GFAR_ERRATA_76;
961
962 /* MPC8313 and MPC837x all rev */
963 if ((pvr == 0x80850010 && mod == 0x80b0) ||
964 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
965 priv->errata |= GFAR_ERRATA_A002;
966
967 /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
968 if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
969 (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
970 priv->errata |= GFAR_ERRATA_12;
971
972 if (priv->errata)
973 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
974 priv->errata);
975 }
976
977 /* Set up the ethernet device structure, private data,
978 * and anything else we need before we start
979 */
980 static int gfar_probe(struct platform_device *ofdev)
981 {
982 u32 tempval;
983 struct net_device *dev = NULL;
984 struct gfar_private *priv = NULL;
985 struct gfar __iomem *regs = NULL;
986 int err = 0, i, grp_idx = 0;
987 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
988 u32 isrg = 0;
989 u32 __iomem *baddr;
990
991 err = gfar_of_init(ofdev, &dev);
992
993 if (err)
994 return err;
995
996 priv = netdev_priv(dev);
997 priv->ndev = dev;
998 priv->ofdev = ofdev;
999 priv->dev = &ofdev->dev;
1000 SET_NETDEV_DEV(dev, &ofdev->dev);
1001
1002 spin_lock_init(&priv->bflock);
1003 INIT_WORK(&priv->reset_task, gfar_reset_task);
1004
1005 platform_set_drvdata(ofdev, priv);
1006 regs = priv->gfargrp[0].regs;
1007
1008 gfar_detect_errata(priv);
1009
1010 /* Stop the DMA engine now, in case it was running before
1011 * (The firmware could have used it, and left it running).
1012 */
1013 gfar_halt(dev);
1014
1015 /* Reset MAC layer */
1016 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1017
1018 /* We need to delay at least 3 TX clocks */
1019 udelay(2);
1020
1021 tempval = 0;
1022 if (!priv->pause_aneg_en && priv->tx_pause_en)
1023 tempval |= MACCFG1_TX_FLOW;
1024 if (!priv->pause_aneg_en && priv->rx_pause_en)
1025 tempval |= MACCFG1_RX_FLOW;
1026 /* the soft reset bit is not self-resetting, so we need to
1027 * clear it before resuming normal operation
1028 */
1029 gfar_write(&regs->maccfg1, tempval);
1030
1031 /* Initialize MACCFG2. */
1032 tempval = MACCFG2_INIT_SETTINGS;
1033 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1034 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1035 gfar_write(&regs->maccfg2, tempval);
1036
1037 /* Initialize ECNTRL */
1038 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1039
1040 /* Set the dev->base_addr to the gfar reg region */
1041 dev->base_addr = (unsigned long) regs;
1042
1043 /* Fill in the dev structure */
1044 dev->watchdog_timeo = TX_TIMEOUT;
1045 dev->mtu = 1500;
1046 dev->netdev_ops = &gfar_netdev_ops;
1047 dev->ethtool_ops = &gfar_ethtool_ops;
1048
1049 /* Register for napi ...We are registering NAPI for each grp */
1050 if (priv->mode == SQ_SG_MODE)
1051 netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq,
1052 GFAR_DEV_WEIGHT);
1053 else
1054 for (i = 0; i < priv->num_grps; i++)
1055 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1056 GFAR_DEV_WEIGHT);
1057
1058 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1059 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1060 NETIF_F_RXCSUM;
1061 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1062 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1063 }
1064
1065 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1066 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1067 NETIF_F_HW_VLAN_CTAG_RX;
1068 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1069 }
1070
1071 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1072 priv->extended_hash = 1;
1073 priv->hash_width = 9;
1074
1075 priv->hash_regs[0] = &regs->igaddr0;
1076 priv->hash_regs[1] = &regs->igaddr1;
1077 priv->hash_regs[2] = &regs->igaddr2;
1078 priv->hash_regs[3] = &regs->igaddr3;
1079 priv->hash_regs[4] = &regs->igaddr4;
1080 priv->hash_regs[5] = &regs->igaddr5;
1081 priv->hash_regs[6] = &regs->igaddr6;
1082 priv->hash_regs[7] = &regs->igaddr7;
1083 priv->hash_regs[8] = &regs->gaddr0;
1084 priv->hash_regs[9] = &regs->gaddr1;
1085 priv->hash_regs[10] = &regs->gaddr2;
1086 priv->hash_regs[11] = &regs->gaddr3;
1087 priv->hash_regs[12] = &regs->gaddr4;
1088 priv->hash_regs[13] = &regs->gaddr5;
1089 priv->hash_regs[14] = &regs->gaddr6;
1090 priv->hash_regs[15] = &regs->gaddr7;
1091
1092 } else {
1093 priv->extended_hash = 0;
1094 priv->hash_width = 8;
1095
1096 priv->hash_regs[0] = &regs->gaddr0;
1097 priv->hash_regs[1] = &regs->gaddr1;
1098 priv->hash_regs[2] = &regs->gaddr2;
1099 priv->hash_regs[3] = &regs->gaddr3;
1100 priv->hash_regs[4] = &regs->gaddr4;
1101 priv->hash_regs[5] = &regs->gaddr5;
1102 priv->hash_regs[6] = &regs->gaddr6;
1103 priv->hash_regs[7] = &regs->gaddr7;
1104 }
1105
1106 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1107 priv->padding = DEFAULT_PADDING;
1108 else
1109 priv->padding = 0;
1110
1111 if (dev->features & NETIF_F_IP_CSUM ||
1112 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1113 dev->needed_headroom = GMAC_FCB_LEN;
1114
1115 /* Program the isrg regs only if number of grps > 1 */
1116 if (priv->num_grps > 1) {
1117 baddr = &regs->isrg0;
1118 for (i = 0; i < priv->num_grps; i++) {
1119 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1120 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1121 gfar_write(baddr, isrg);
1122 baddr++;
1123 isrg = 0x0;
1124 }
1125 }
1126
1127 /* Need to reverse the bit maps as bit_map's MSB is q0
1128 * but, for_each_set_bit parses from right to left, which
1129 * basically reverses the queue numbers
1130 */
1131 for (i = 0; i< priv->num_grps; i++) {
1132 priv->gfargrp[i].tx_bit_map =
1133 reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1134 priv->gfargrp[i].rx_bit_map =
1135 reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1136 }
1137
1138 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1139 * also assign queues to groups
1140 */
1141 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1142 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1143
1144 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1145 priv->num_rx_queues) {
1146 priv->gfargrp[grp_idx].num_rx_queues++;
1147 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1148 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1149 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1150 }
1151 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1152
1153 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1154 priv->num_tx_queues) {
1155 priv->gfargrp[grp_idx].num_tx_queues++;
1156 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1157 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1158 tqueue = tqueue | (TQUEUE_EN0 >> i);
1159 }
1160 priv->gfargrp[grp_idx].rstat = rstat;
1161 priv->gfargrp[grp_idx].tstat = tstat;
1162 rstat = tstat =0;
1163 }
1164
1165 gfar_write(&regs->rqueue, rqueue);
1166 gfar_write(&regs->tqueue, tqueue);
1167
1168 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1169
1170 /* Initializing some of the rx/tx queue level parameters */
1171 for (i = 0; i < priv->num_tx_queues; i++) {
1172 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1173 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1174 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1175 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1176 }
1177
1178 for (i = 0; i < priv->num_rx_queues; i++) {
1179 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1180 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1181 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1182 }
1183
1184 /* always enable rx filer */
1185 priv->rx_filer_enable = 1;
1186 /* Enable most messages by default */
1187 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1188 /* use pritority h/w tx queue scheduling for single queue devices */
1189 if (priv->num_tx_queues == 1)
1190 priv->prio_sched_en = 1;
1191
1192 /* Carrier starts down, phylib will bring it up */
1193 netif_carrier_off(dev);
1194
1195 err = register_netdev(dev);
1196
1197 if (err) {
1198 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1199 goto register_fail;
1200 }
1201
1202 device_init_wakeup(&dev->dev,
1203 priv->device_flags &
1204 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1205
1206 /* fill out IRQ number and name fields */
1207 for (i = 0; i < priv->num_grps; i++) {
1208 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1209 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1210 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1211 dev->name, "_g", '0' + i, "_tx");
1212 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1213 dev->name, "_g", '0' + i, "_rx");
1214 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1215 dev->name, "_g", '0' + i, "_er");
1216 } else
1217 strcpy(gfar_irq(grp, TX)->name, dev->name);
1218 }
1219
1220 /* Initialize the filer table */
1221 gfar_init_filer_table(priv);
1222
1223 /* Create all the sysfs files */
1224 gfar_init_sysfs(dev);
1225
1226 /* Print out the device info */
1227 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1228
1229 /* Even more device info helps when determining which kernel
1230 * provided which set of benchmarks.
1231 */
1232 netdev_info(dev, "Running with NAPI enabled\n");
1233 for (i = 0; i < priv->num_rx_queues; i++)
1234 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1235 i, priv->rx_queue[i]->rx_ring_size);
1236 for (i = 0; i < priv->num_tx_queues; i++)
1237 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1238 i, priv->tx_queue[i]->tx_ring_size);
1239
1240 return 0;
1241
1242 register_fail:
1243 unmap_group_regs(priv);
1244 free_tx_pointers(priv);
1245 free_rx_pointers(priv);
1246 if (priv->phy_node)
1247 of_node_put(priv->phy_node);
1248 if (priv->tbi_node)
1249 of_node_put(priv->tbi_node);
1250 free_gfar_dev(priv);
1251 return err;
1252 }
1253
1254 static int gfar_remove(struct platform_device *ofdev)
1255 {
1256 struct gfar_private *priv = platform_get_drvdata(ofdev);
1257
1258 if (priv->phy_node)
1259 of_node_put(priv->phy_node);
1260 if (priv->tbi_node)
1261 of_node_put(priv->tbi_node);
1262
1263 unregister_netdev(priv->ndev);
1264 unmap_group_regs(priv);
1265 free_gfar_dev(priv);
1266
1267 return 0;
1268 }
1269
1270 #ifdef CONFIG_PM
1271
1272 static int gfar_suspend(struct device *dev)
1273 {
1274 struct gfar_private *priv = dev_get_drvdata(dev);
1275 struct net_device *ndev = priv->ndev;
1276 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1277 unsigned long flags;
1278 u32 tempval;
1279
1280 int magic_packet = priv->wol_en &&
1281 (priv->device_flags &
1282 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1283
1284 netif_device_detach(ndev);
1285
1286 if (netif_running(ndev)) {
1287
1288 local_irq_save(flags);
1289 lock_tx_qs(priv);
1290 lock_rx_qs(priv);
1291
1292 gfar_halt_nodisable(ndev);
1293
1294 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1295 tempval = gfar_read(&regs->maccfg1);
1296
1297 tempval &= ~MACCFG1_TX_EN;
1298
1299 if (!magic_packet)
1300 tempval &= ~MACCFG1_RX_EN;
1301
1302 gfar_write(&regs->maccfg1, tempval);
1303
1304 unlock_rx_qs(priv);
1305 unlock_tx_qs(priv);
1306 local_irq_restore(flags);
1307
1308 disable_napi(priv);
1309
1310 if (magic_packet) {
1311 /* Enable interrupt on Magic Packet */
1312 gfar_write(&regs->imask, IMASK_MAG);
1313
1314 /* Enable Magic Packet mode */
1315 tempval = gfar_read(&regs->maccfg2);
1316 tempval |= MACCFG2_MPEN;
1317 gfar_write(&regs->maccfg2, tempval);
1318 } else {
1319 phy_stop(priv->phydev);
1320 }
1321 }
1322
1323 return 0;
1324 }
1325
1326 static int gfar_resume(struct device *dev)
1327 {
1328 struct gfar_private *priv = dev_get_drvdata(dev);
1329 struct net_device *ndev = priv->ndev;
1330 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1331 unsigned long flags;
1332 u32 tempval;
1333 int magic_packet = priv->wol_en &&
1334 (priv->device_flags &
1335 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1336
1337 if (!netif_running(ndev)) {
1338 netif_device_attach(ndev);
1339 return 0;
1340 }
1341
1342 if (!magic_packet && priv->phydev)
1343 phy_start(priv->phydev);
1344
1345 /* Disable Magic Packet mode, in case something
1346 * else woke us up.
1347 */
1348 local_irq_save(flags);
1349 lock_tx_qs(priv);
1350 lock_rx_qs(priv);
1351
1352 tempval = gfar_read(&regs->maccfg2);
1353 tempval &= ~MACCFG2_MPEN;
1354 gfar_write(&regs->maccfg2, tempval);
1355
1356 gfar_start(ndev);
1357
1358 unlock_rx_qs(priv);
1359 unlock_tx_qs(priv);
1360 local_irq_restore(flags);
1361
1362 netif_device_attach(ndev);
1363
1364 enable_napi(priv);
1365
1366 return 0;
1367 }
1368
1369 static int gfar_restore(struct device *dev)
1370 {
1371 struct gfar_private *priv = dev_get_drvdata(dev);
1372 struct net_device *ndev = priv->ndev;
1373
1374 if (!netif_running(ndev)) {
1375 netif_device_attach(ndev);
1376
1377 return 0;
1378 }
1379
1380 if (gfar_init_bds(ndev)) {
1381 free_skb_resources(priv);
1382 return -ENOMEM;
1383 }
1384
1385 init_registers(ndev);
1386 gfar_set_mac_address(ndev);
1387 gfar_init_mac(ndev);
1388 gfar_start(ndev);
1389
1390 priv->oldlink = 0;
1391 priv->oldspeed = 0;
1392 priv->oldduplex = -1;
1393
1394 if (priv->phydev)
1395 phy_start(priv->phydev);
1396
1397 netif_device_attach(ndev);
1398 enable_napi(priv);
1399
1400 return 0;
1401 }
1402
1403 static struct dev_pm_ops gfar_pm_ops = {
1404 .suspend = gfar_suspend,
1405 .resume = gfar_resume,
1406 .freeze = gfar_suspend,
1407 .thaw = gfar_resume,
1408 .restore = gfar_restore,
1409 };
1410
1411 #define GFAR_PM_OPS (&gfar_pm_ops)
1412
1413 #else
1414
1415 #define GFAR_PM_OPS NULL
1416
1417 #endif
1418
1419 /* Reads the controller's registers to determine what interface
1420 * connects it to the PHY.
1421 */
1422 static phy_interface_t gfar_get_interface(struct net_device *dev)
1423 {
1424 struct gfar_private *priv = netdev_priv(dev);
1425 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1426 u32 ecntrl;
1427
1428 ecntrl = gfar_read(&regs->ecntrl);
1429
1430 if (ecntrl & ECNTRL_SGMII_MODE)
1431 return PHY_INTERFACE_MODE_SGMII;
1432
1433 if (ecntrl & ECNTRL_TBI_MODE) {
1434 if (ecntrl & ECNTRL_REDUCED_MODE)
1435 return PHY_INTERFACE_MODE_RTBI;
1436 else
1437 return PHY_INTERFACE_MODE_TBI;
1438 }
1439
1440 if (ecntrl & ECNTRL_REDUCED_MODE) {
1441 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1442 return PHY_INTERFACE_MODE_RMII;
1443 }
1444 else {
1445 phy_interface_t interface = priv->interface;
1446
1447 /* This isn't autodetected right now, so it must
1448 * be set by the device tree or platform code.
1449 */
1450 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1451 return PHY_INTERFACE_MODE_RGMII_ID;
1452
1453 return PHY_INTERFACE_MODE_RGMII;
1454 }
1455 }
1456
1457 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1458 return PHY_INTERFACE_MODE_GMII;
1459
1460 return PHY_INTERFACE_MODE_MII;
1461 }
1462
1463
1464 /* Initializes driver's PHY state, and attaches to the PHY.
1465 * Returns 0 on success.
1466 */
1467 static int init_phy(struct net_device *dev)
1468 {
1469 struct gfar_private *priv = netdev_priv(dev);
1470 uint gigabit_support =
1471 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1472 GFAR_SUPPORTED_GBIT : 0;
1473 phy_interface_t interface;
1474
1475 priv->oldlink = 0;
1476 priv->oldspeed = 0;
1477 priv->oldduplex = -1;
1478
1479 interface = gfar_get_interface(dev);
1480
1481 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1482 interface);
1483 if (!priv->phydev)
1484 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1485 interface);
1486 if (!priv->phydev) {
1487 dev_err(&dev->dev, "could not attach to PHY\n");
1488 return -ENODEV;
1489 }
1490
1491 if (interface == PHY_INTERFACE_MODE_SGMII)
1492 gfar_configure_serdes(dev);
1493
1494 /* Remove any features not supported by the controller */
1495 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1496 priv->phydev->advertising = priv->phydev->supported;
1497
1498 return 0;
1499 }
1500
1501 /* Initialize TBI PHY interface for communicating with the
1502 * SERDES lynx PHY on the chip. We communicate with this PHY
1503 * through the MDIO bus on each controller, treating it as a
1504 * "normal" PHY at the address found in the TBIPA register. We assume
1505 * that the TBIPA register is valid. Either the MDIO bus code will set
1506 * it to a value that doesn't conflict with other PHYs on the bus, or the
1507 * value doesn't matter, as there are no other PHYs on the bus.
1508 */
1509 static void gfar_configure_serdes(struct net_device *dev)
1510 {
1511 struct gfar_private *priv = netdev_priv(dev);
1512 struct phy_device *tbiphy;
1513
1514 if (!priv->tbi_node) {
1515 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1516 "device tree specify a tbi-handle\n");
1517 return;
1518 }
1519
1520 tbiphy = of_phy_find_device(priv->tbi_node);
1521 if (!tbiphy) {
1522 dev_err(&dev->dev, "error: Could not get TBI device\n");
1523 return;
1524 }
1525
1526 /* If the link is already up, we must already be ok, and don't need to
1527 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1528 * everything for us? Resetting it takes the link down and requires
1529 * several seconds for it to come back.
1530 */
1531 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1532 return;
1533
1534 /* Single clk mode, mii mode off(for serdes communication) */
1535 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1536
1537 phy_write(tbiphy, MII_ADVERTISE,
1538 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1539 ADVERTISE_1000XPSE_ASYM);
1540
1541 phy_write(tbiphy, MII_BMCR,
1542 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1543 BMCR_SPEED1000);
1544 }
1545
1546 static void init_registers(struct net_device *dev)
1547 {
1548 struct gfar_private *priv = netdev_priv(dev);
1549 struct gfar __iomem *regs = NULL;
1550 int i;
1551
1552 for (i = 0; i < priv->num_grps; i++) {
1553 regs = priv->gfargrp[i].regs;
1554 /* Clear IEVENT */
1555 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1556
1557 /* Initialize IMASK */
1558 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1559 }
1560
1561 regs = priv->gfargrp[0].regs;
1562 /* Init hash registers to zero */
1563 gfar_write(&regs->igaddr0, 0);
1564 gfar_write(&regs->igaddr1, 0);
1565 gfar_write(&regs->igaddr2, 0);
1566 gfar_write(&regs->igaddr3, 0);
1567 gfar_write(&regs->igaddr4, 0);
1568 gfar_write(&regs->igaddr5, 0);
1569 gfar_write(&regs->igaddr6, 0);
1570 gfar_write(&regs->igaddr7, 0);
1571
1572 gfar_write(&regs->gaddr0, 0);
1573 gfar_write(&regs->gaddr1, 0);
1574 gfar_write(&regs->gaddr2, 0);
1575 gfar_write(&regs->gaddr3, 0);
1576 gfar_write(&regs->gaddr4, 0);
1577 gfar_write(&regs->gaddr5, 0);
1578 gfar_write(&regs->gaddr6, 0);
1579 gfar_write(&regs->gaddr7, 0);
1580
1581 /* Zero out the rmon mib registers if it has them */
1582 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1583 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1584
1585 /* Mask off the CAM interrupts */
1586 gfar_write(&regs->rmon.cam1, 0xffffffff);
1587 gfar_write(&regs->rmon.cam2, 0xffffffff);
1588 }
1589
1590 /* Initialize the max receive buffer length */
1591 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1592
1593 /* Initialize the Minimum Frame Length Register */
1594 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1595 }
1596
1597 static int __gfar_is_rx_idle(struct gfar_private *priv)
1598 {
1599 u32 res;
1600
1601 /* Normaly TSEC should not hang on GRS commands, so we should
1602 * actually wait for IEVENT_GRSC flag.
1603 */
1604 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1605 return 0;
1606
1607 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1608 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1609 * and the Rx can be safely reset.
1610 */
1611 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1612 res &= 0x7f807f80;
1613 if ((res & 0xffff) == (res >> 16))
1614 return 1;
1615
1616 return 0;
1617 }
1618
1619 /* Halt the receive and transmit queues */
1620 static void gfar_halt_nodisable(struct net_device *dev)
1621 {
1622 struct gfar_private *priv = netdev_priv(dev);
1623 struct gfar __iomem *regs = NULL;
1624 u32 tempval;
1625 int i;
1626
1627 for (i = 0; i < priv->num_grps; i++) {
1628 regs = priv->gfargrp[i].regs;
1629 /* Mask all interrupts */
1630 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1631
1632 /* Clear all interrupts */
1633 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1634 }
1635
1636 regs = priv->gfargrp[0].regs;
1637 /* Stop the DMA, and wait for it to stop */
1638 tempval = gfar_read(&regs->dmactrl);
1639 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1640 (DMACTRL_GRS | DMACTRL_GTS)) {
1641 int ret;
1642
1643 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1644 gfar_write(&regs->dmactrl, tempval);
1645
1646 do {
1647 ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1648 (IEVENT_GRSC | IEVENT_GTSC)) ==
1649 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1650 if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1651 ret = __gfar_is_rx_idle(priv);
1652 } while (!ret);
1653 }
1654 }
1655
1656 /* Halt the receive and transmit queues */
1657 void gfar_halt(struct net_device *dev)
1658 {
1659 struct gfar_private *priv = netdev_priv(dev);
1660 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1661 u32 tempval;
1662
1663 gfar_halt_nodisable(dev);
1664
1665 /* Disable Rx and Tx */
1666 tempval = gfar_read(&regs->maccfg1);
1667 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1668 gfar_write(&regs->maccfg1, tempval);
1669 }
1670
1671 static void free_grp_irqs(struct gfar_priv_grp *grp)
1672 {
1673 free_irq(gfar_irq(grp, TX)->irq, grp);
1674 free_irq(gfar_irq(grp, RX)->irq, grp);
1675 free_irq(gfar_irq(grp, ER)->irq, grp);
1676 }
1677
1678 void stop_gfar(struct net_device *dev)
1679 {
1680 struct gfar_private *priv = netdev_priv(dev);
1681 unsigned long flags;
1682 int i;
1683
1684 phy_stop(priv->phydev);
1685
1686
1687 /* Lock it down */
1688 local_irq_save(flags);
1689 lock_tx_qs(priv);
1690 lock_rx_qs(priv);
1691
1692 gfar_halt(dev);
1693
1694 unlock_rx_qs(priv);
1695 unlock_tx_qs(priv);
1696 local_irq_restore(flags);
1697
1698 /* Free the IRQs */
1699 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1700 for (i = 0; i < priv->num_grps; i++)
1701 free_grp_irqs(&priv->gfargrp[i]);
1702 } else {
1703 for (i = 0; i < priv->num_grps; i++)
1704 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
1705 &priv->gfargrp[i]);
1706 }
1707
1708 free_skb_resources(priv);
1709 }
1710
1711 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1712 {
1713 struct txbd8 *txbdp;
1714 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1715 int i, j;
1716
1717 txbdp = tx_queue->tx_bd_base;
1718
1719 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1720 if (!tx_queue->tx_skbuff[i])
1721 continue;
1722
1723 dma_unmap_single(priv->dev, txbdp->bufPtr,
1724 txbdp->length, DMA_TO_DEVICE);
1725 txbdp->lstatus = 0;
1726 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1727 j++) {
1728 txbdp++;
1729 dma_unmap_page(priv->dev, txbdp->bufPtr,
1730 txbdp->length, DMA_TO_DEVICE);
1731 }
1732 txbdp++;
1733 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1734 tx_queue->tx_skbuff[i] = NULL;
1735 }
1736 kfree(tx_queue->tx_skbuff);
1737 tx_queue->tx_skbuff = NULL;
1738 }
1739
1740 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1741 {
1742 struct rxbd8 *rxbdp;
1743 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1744 int i;
1745
1746 rxbdp = rx_queue->rx_bd_base;
1747
1748 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1749 if (rx_queue->rx_skbuff[i]) {
1750 dma_unmap_single(priv->dev, rxbdp->bufPtr,
1751 priv->rx_buffer_size,
1752 DMA_FROM_DEVICE);
1753 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1754 rx_queue->rx_skbuff[i] = NULL;
1755 }
1756 rxbdp->lstatus = 0;
1757 rxbdp->bufPtr = 0;
1758 rxbdp++;
1759 }
1760 kfree(rx_queue->rx_skbuff);
1761 rx_queue->rx_skbuff = NULL;
1762 }
1763
1764 /* If there are any tx skbs or rx skbs still around, free them.
1765 * Then free tx_skbuff and rx_skbuff
1766 */
1767 static void free_skb_resources(struct gfar_private *priv)
1768 {
1769 struct gfar_priv_tx_q *tx_queue = NULL;
1770 struct gfar_priv_rx_q *rx_queue = NULL;
1771 int i;
1772
1773 /* Go through all the buffer descriptors and free their data buffers */
1774 for (i = 0; i < priv->num_tx_queues; i++) {
1775 struct netdev_queue *txq;
1776
1777 tx_queue = priv->tx_queue[i];
1778 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1779 if (tx_queue->tx_skbuff)
1780 free_skb_tx_queue(tx_queue);
1781 netdev_tx_reset_queue(txq);
1782 }
1783
1784 for (i = 0; i < priv->num_rx_queues; i++) {
1785 rx_queue = priv->rx_queue[i];
1786 if (rx_queue->rx_skbuff)
1787 free_skb_rx_queue(rx_queue);
1788 }
1789
1790 dma_free_coherent(priv->dev,
1791 sizeof(struct txbd8) * priv->total_tx_ring_size +
1792 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1793 priv->tx_queue[0]->tx_bd_base,
1794 priv->tx_queue[0]->tx_bd_dma_base);
1795 }
1796
1797 void gfar_start(struct net_device *dev)
1798 {
1799 struct gfar_private *priv = netdev_priv(dev);
1800 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1801 u32 tempval;
1802 int i = 0;
1803
1804 /* Enable Rx and Tx in MACCFG1 */
1805 tempval = gfar_read(&regs->maccfg1);
1806 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1807 gfar_write(&regs->maccfg1, tempval);
1808
1809 /* Initialize DMACTRL to have WWR and WOP */
1810 tempval = gfar_read(&regs->dmactrl);
1811 tempval |= DMACTRL_INIT_SETTINGS;
1812 gfar_write(&regs->dmactrl, tempval);
1813
1814 /* Make sure we aren't stopped */
1815 tempval = gfar_read(&regs->dmactrl);
1816 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1817 gfar_write(&regs->dmactrl, tempval);
1818
1819 for (i = 0; i < priv->num_grps; i++) {
1820 regs = priv->gfargrp[i].regs;
1821 /* Clear THLT/RHLT, so that the DMA starts polling now */
1822 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1823 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1824 /* Unmask the interrupts we look for */
1825 gfar_write(&regs->imask, IMASK_DEFAULT);
1826 }
1827
1828 dev->trans_start = jiffies; /* prevent tx timeout */
1829 }
1830
1831 static void gfar_configure_coalescing(struct gfar_private *priv,
1832 unsigned long tx_mask, unsigned long rx_mask)
1833 {
1834 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1835 u32 __iomem *baddr;
1836
1837 if (priv->mode == MQ_MG_MODE) {
1838 int i = 0;
1839
1840 baddr = &regs->txic0;
1841 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1842 gfar_write(baddr + i, 0);
1843 if (likely(priv->tx_queue[i]->txcoalescing))
1844 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1845 }
1846
1847 baddr = &regs->rxic0;
1848 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1849 gfar_write(baddr + i, 0);
1850 if (likely(priv->rx_queue[i]->rxcoalescing))
1851 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1852 }
1853 } else {
1854 /* Backward compatible case -- even if we enable
1855 * multiple queues, there's only single reg to program
1856 */
1857 gfar_write(&regs->txic, 0);
1858 if (likely(priv->tx_queue[0]->txcoalescing))
1859 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1860
1861 gfar_write(&regs->rxic, 0);
1862 if (unlikely(priv->rx_queue[0]->rxcoalescing))
1863 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1864 }
1865 }
1866
1867 void gfar_configure_coalescing_all(struct gfar_private *priv)
1868 {
1869 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1870 }
1871
1872 static int register_grp_irqs(struct gfar_priv_grp *grp)
1873 {
1874 struct gfar_private *priv = grp->priv;
1875 struct net_device *dev = priv->ndev;
1876 int err;
1877
1878 /* If the device has multiple interrupts, register for
1879 * them. Otherwise, only register for the one
1880 */
1881 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1882 /* Install our interrupt handlers for Error,
1883 * Transmit, and Receive
1884 */
1885 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1886 gfar_irq(grp, ER)->name, grp);
1887 if (err < 0) {
1888 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1889 gfar_irq(grp, ER)->irq);
1890
1891 goto err_irq_fail;
1892 }
1893 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1894 gfar_irq(grp, TX)->name, grp);
1895 if (err < 0) {
1896 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1897 gfar_irq(grp, TX)->irq);
1898 goto tx_irq_fail;
1899 }
1900 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1901 gfar_irq(grp, RX)->name, grp);
1902 if (err < 0) {
1903 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1904 gfar_irq(grp, RX)->irq);
1905 goto rx_irq_fail;
1906 }
1907 } else {
1908 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1909 gfar_irq(grp, TX)->name, grp);
1910 if (err < 0) {
1911 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1912 gfar_irq(grp, TX)->irq);
1913 goto err_irq_fail;
1914 }
1915 }
1916
1917 return 0;
1918
1919 rx_irq_fail:
1920 free_irq(gfar_irq(grp, TX)->irq, grp);
1921 tx_irq_fail:
1922 free_irq(gfar_irq(grp, ER)->irq, grp);
1923 err_irq_fail:
1924 return err;
1925
1926 }
1927
1928 /* Bring the controller up and running */
1929 int startup_gfar(struct net_device *ndev)
1930 {
1931 struct gfar_private *priv = netdev_priv(ndev);
1932 struct gfar __iomem *regs = NULL;
1933 int err, i, j;
1934
1935 for (i = 0; i < priv->num_grps; i++) {
1936 regs= priv->gfargrp[i].regs;
1937 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1938 }
1939
1940 regs= priv->gfargrp[0].regs;
1941 err = gfar_alloc_skb_resources(ndev);
1942 if (err)
1943 return err;
1944
1945 gfar_init_mac(ndev);
1946
1947 for (i = 0; i < priv->num_grps; i++) {
1948 err = register_grp_irqs(&priv->gfargrp[i]);
1949 if (err) {
1950 for (j = 0; j < i; j++)
1951 free_grp_irqs(&priv->gfargrp[j]);
1952 goto irq_fail;
1953 }
1954 }
1955
1956 /* Start the controller */
1957 gfar_start(ndev);
1958
1959 phy_start(priv->phydev);
1960
1961 gfar_configure_coalescing_all(priv);
1962
1963 return 0;
1964
1965 irq_fail:
1966 free_skb_resources(priv);
1967 return err;
1968 }
1969
1970 /* Called when something needs to use the ethernet device
1971 * Returns 0 for success.
1972 */
1973 static int gfar_enet_open(struct net_device *dev)
1974 {
1975 struct gfar_private *priv = netdev_priv(dev);
1976 int err;
1977
1978 enable_napi(priv);
1979
1980 /* Initialize a bunch of registers */
1981 init_registers(dev);
1982
1983 gfar_set_mac_address(dev);
1984
1985 err = init_phy(dev);
1986
1987 if (err) {
1988 disable_napi(priv);
1989 return err;
1990 }
1991
1992 err = startup_gfar(dev);
1993 if (err) {
1994 disable_napi(priv);
1995 return err;
1996 }
1997
1998 netif_tx_start_all_queues(dev);
1999
2000 device_set_wakeup_enable(&dev->dev, priv->wol_en);
2001
2002 return err;
2003 }
2004
2005 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2006 {
2007 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2008
2009 memset(fcb, 0, GMAC_FCB_LEN);
2010
2011 return fcb;
2012 }
2013
2014 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2015 int fcb_length)
2016 {
2017 /* If we're here, it's a IP packet with a TCP or UDP
2018 * payload. We set it to checksum, using a pseudo-header
2019 * we provide
2020 */
2021 u8 flags = TXFCB_DEFAULT;
2022
2023 /* Tell the controller what the protocol is
2024 * And provide the already calculated phcs
2025 */
2026 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2027 flags |= TXFCB_UDP;
2028 fcb->phcs = udp_hdr(skb)->check;
2029 } else
2030 fcb->phcs = tcp_hdr(skb)->check;
2031
2032 /* l3os is the distance between the start of the
2033 * frame (skb->data) and the start of the IP hdr.
2034 * l4os is the distance between the start of the
2035 * l3 hdr and the l4 hdr
2036 */
2037 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2038 fcb->l4os = skb_network_header_len(skb);
2039
2040 fcb->flags = flags;
2041 }
2042
2043 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2044 {
2045 fcb->flags |= TXFCB_VLN;
2046 fcb->vlctl = vlan_tx_tag_get(skb);
2047 }
2048
2049 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2050 struct txbd8 *base, int ring_size)
2051 {
2052 struct txbd8 *new_bd = bdp + stride;
2053
2054 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2055 }
2056
2057 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2058 int ring_size)
2059 {
2060 return skip_txbd(bdp, 1, base, ring_size);
2061 }
2062
2063 /* eTSEC12: csum generation not supported for some fcb offsets */
2064 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2065 unsigned long fcb_addr)
2066 {
2067 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2068 (fcb_addr % 0x20) > 0x18);
2069 }
2070
2071 /* eTSEC76: csum generation for frames larger than 2500 may
2072 * cause excess delays before start of transmission
2073 */
2074 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2075 unsigned int len)
2076 {
2077 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2078 (len > 2500));
2079 }
2080
2081 /* This is called by the kernel when a frame is ready for transmission.
2082 * It is pointed to by the dev->hard_start_xmit function pointer
2083 */
2084 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2085 {
2086 struct gfar_private *priv = netdev_priv(dev);
2087 struct gfar_priv_tx_q *tx_queue = NULL;
2088 struct netdev_queue *txq;
2089 struct gfar __iomem *regs = NULL;
2090 struct txfcb *fcb = NULL;
2091 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2092 u32 lstatus;
2093 int i, rq = 0;
2094 int do_tstamp, do_csum, do_vlan;
2095 u32 bufaddr;
2096 unsigned long flags;
2097 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2098
2099 rq = skb->queue_mapping;
2100 tx_queue = priv->tx_queue[rq];
2101 txq = netdev_get_tx_queue(dev, rq);
2102 base = tx_queue->tx_bd_base;
2103 regs = tx_queue->grp->regs;
2104
2105 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2106 do_vlan = vlan_tx_tag_present(skb);
2107 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2108 priv->hwts_tx_en;
2109
2110 if (do_csum || do_vlan)
2111 fcb_len = GMAC_FCB_LEN;
2112
2113 /* check if time stamp should be generated */
2114 if (unlikely(do_tstamp))
2115 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2116
2117 /* make space for additional header when fcb is needed */
2118 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2119 struct sk_buff *skb_new;
2120
2121 skb_new = skb_realloc_headroom(skb, fcb_len);
2122 if (!skb_new) {
2123 dev->stats.tx_errors++;
2124 kfree_skb(skb);
2125 return NETDEV_TX_OK;
2126 }
2127
2128 if (skb->sk)
2129 skb_set_owner_w(skb_new, skb->sk);
2130 consume_skb(skb);
2131 skb = skb_new;
2132 }
2133
2134 /* total number of fragments in the SKB */
2135 nr_frags = skb_shinfo(skb)->nr_frags;
2136
2137 /* calculate the required number of TxBDs for this skb */
2138 if (unlikely(do_tstamp))
2139 nr_txbds = nr_frags + 2;
2140 else
2141 nr_txbds = nr_frags + 1;
2142
2143 /* check if there is space to queue this packet */
2144 if (nr_txbds > tx_queue->num_txbdfree) {
2145 /* no space, stop the queue */
2146 netif_tx_stop_queue(txq);
2147 dev->stats.tx_fifo_errors++;
2148 return NETDEV_TX_BUSY;
2149 }
2150
2151 /* Update transmit stats */
2152 bytes_sent = skb->len;
2153 tx_queue->stats.tx_bytes += bytes_sent;
2154 /* keep Tx bytes on wire for BQL accounting */
2155 GFAR_CB(skb)->bytes_sent = bytes_sent;
2156 tx_queue->stats.tx_packets++;
2157
2158 txbdp = txbdp_start = tx_queue->cur_tx;
2159 lstatus = txbdp->lstatus;
2160
2161 /* Time stamp insertion requires one additional TxBD */
2162 if (unlikely(do_tstamp))
2163 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2164 tx_queue->tx_ring_size);
2165
2166 if (nr_frags == 0) {
2167 if (unlikely(do_tstamp))
2168 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2169 TXBD_INTERRUPT);
2170 else
2171 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2172 } else {
2173 /* Place the fragment addresses and lengths into the TxBDs */
2174 for (i = 0; i < nr_frags; i++) {
2175 unsigned int frag_len;
2176 /* Point at the next BD, wrapping as needed */
2177 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2178
2179 frag_len = skb_shinfo(skb)->frags[i].size;
2180
2181 lstatus = txbdp->lstatus | frag_len |
2182 BD_LFLAG(TXBD_READY);
2183
2184 /* Handle the last BD specially */
2185 if (i == nr_frags - 1)
2186 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2187
2188 bufaddr = skb_frag_dma_map(priv->dev,
2189 &skb_shinfo(skb)->frags[i],
2190 0,
2191 frag_len,
2192 DMA_TO_DEVICE);
2193
2194 /* set the TxBD length and buffer pointer */
2195 txbdp->bufPtr = bufaddr;
2196 txbdp->lstatus = lstatus;
2197 }
2198
2199 lstatus = txbdp_start->lstatus;
2200 }
2201
2202 /* Add TxPAL between FCB and frame if required */
2203 if (unlikely(do_tstamp)) {
2204 skb_push(skb, GMAC_TXPAL_LEN);
2205 memset(skb->data, 0, GMAC_TXPAL_LEN);
2206 }
2207
2208 /* Add TxFCB if required */
2209 if (fcb_len) {
2210 fcb = gfar_add_fcb(skb);
2211 lstatus |= BD_LFLAG(TXBD_TOE);
2212 }
2213
2214 /* Set up checksumming */
2215 if (do_csum) {
2216 gfar_tx_checksum(skb, fcb, fcb_len);
2217
2218 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2219 unlikely(gfar_csum_errata_76(priv, skb->len))) {
2220 __skb_pull(skb, GMAC_FCB_LEN);
2221 skb_checksum_help(skb);
2222 if (do_vlan || do_tstamp) {
2223 /* put back a new fcb for vlan/tstamp TOE */
2224 fcb = gfar_add_fcb(skb);
2225 } else {
2226 /* Tx TOE not used */
2227 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2228 fcb = NULL;
2229 }
2230 }
2231 }
2232
2233 if (do_vlan)
2234 gfar_tx_vlan(skb, fcb);
2235
2236 /* Setup tx hardware time stamping if requested */
2237 if (unlikely(do_tstamp)) {
2238 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2239 fcb->ptp = 1;
2240 }
2241
2242 txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data,
2243 skb_headlen(skb), DMA_TO_DEVICE);
2244
2245 /* If time stamping is requested one additional TxBD must be set up. The
2246 * first TxBD points to the FCB and must have a data length of
2247 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2248 * the full frame length.
2249 */
2250 if (unlikely(do_tstamp)) {
2251 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len;
2252 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2253 (skb_headlen(skb) - fcb_len);
2254 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2255 } else {
2256 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2257 }
2258
2259 netdev_tx_sent_queue(txq, bytes_sent);
2260
2261 /* We can work in parallel with gfar_clean_tx_ring(), except
2262 * when modifying num_txbdfree. Note that we didn't grab the lock
2263 * when we were reading the num_txbdfree and checking for available
2264 * space, that's because outside of this function it can only grow,
2265 * and once we've got needed space, it cannot suddenly disappear.
2266 *
2267 * The lock also protects us from gfar_error(), which can modify
2268 * regs->tstat and thus retrigger the transfers, which is why we
2269 * also must grab the lock before setting ready bit for the first
2270 * to be transmitted BD.
2271 */
2272 spin_lock_irqsave(&tx_queue->txlock, flags);
2273
2274 /* The powerpc-specific eieio() is used, as wmb() has too strong
2275 * semantics (it requires synchronization between cacheable and
2276 * uncacheable mappings, which eieio doesn't provide and which we
2277 * don't need), thus requiring a more expensive sync instruction. At
2278 * some point, the set of architecture-independent barrier functions
2279 * should be expanded to include weaker barriers.
2280 */
2281 eieio();
2282
2283 txbdp_start->lstatus = lstatus;
2284
2285 eieio(); /* force lstatus write before tx_skbuff */
2286
2287 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2288
2289 /* Update the current skb pointer to the next entry we will use
2290 * (wrapping if necessary)
2291 */
2292 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2293 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2294
2295 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2296
2297 /* reduce TxBD free count */
2298 tx_queue->num_txbdfree -= (nr_txbds);
2299
2300 /* If the next BD still needs to be cleaned up, then the bds
2301 * are full. We need to tell the kernel to stop sending us stuff.
2302 */
2303 if (!tx_queue->num_txbdfree) {
2304 netif_tx_stop_queue(txq);
2305
2306 dev->stats.tx_fifo_errors++;
2307 }
2308
2309 /* Tell the DMA to go go go */
2310 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2311
2312 /* Unlock priv */
2313 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2314
2315 return NETDEV_TX_OK;
2316 }
2317
2318 /* Stops the kernel queue, and halts the controller */
2319 static int gfar_close(struct net_device *dev)
2320 {
2321 struct gfar_private *priv = netdev_priv(dev);
2322
2323 disable_napi(priv);
2324
2325 cancel_work_sync(&priv->reset_task);
2326 stop_gfar(dev);
2327
2328 /* Disconnect from the PHY */
2329 phy_disconnect(priv->phydev);
2330 priv->phydev = NULL;
2331
2332 netif_tx_stop_all_queues(dev);
2333
2334 return 0;
2335 }
2336
2337 /* Changes the mac address if the controller is not running. */
2338 static int gfar_set_mac_address(struct net_device *dev)
2339 {
2340 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2341
2342 return 0;
2343 }
2344
2345 /* Check if rx parser should be activated */
2346 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2347 {
2348 struct gfar __iomem *regs;
2349 u32 tempval;
2350
2351 regs = priv->gfargrp[0].regs;
2352
2353 tempval = gfar_read(&regs->rctrl);
2354 /* If parse is no longer required, then disable parser */
2355 if (tempval & RCTRL_REQ_PARSER) {
2356 tempval |= RCTRL_PRSDEP_INIT;
2357 priv->uses_rxfcb = 1;
2358 } else {
2359 tempval &= ~RCTRL_PRSDEP_INIT;
2360 priv->uses_rxfcb = 0;
2361 }
2362 gfar_write(&regs->rctrl, tempval);
2363 }
2364
2365 /* Enables and disables VLAN insertion/extraction */
2366 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2367 {
2368 struct gfar_private *priv = netdev_priv(dev);
2369 struct gfar __iomem *regs = NULL;
2370 unsigned long flags;
2371 u32 tempval;
2372
2373 regs = priv->gfargrp[0].regs;
2374 local_irq_save(flags);
2375 lock_rx_qs(priv);
2376
2377 if (features & NETIF_F_HW_VLAN_CTAG_TX) {
2378 /* Enable VLAN tag insertion */
2379 tempval = gfar_read(&regs->tctrl);
2380 tempval |= TCTRL_VLINS;
2381 gfar_write(&regs->tctrl, tempval);
2382 } else {
2383 /* Disable VLAN tag insertion */
2384 tempval = gfar_read(&regs->tctrl);
2385 tempval &= ~TCTRL_VLINS;
2386 gfar_write(&regs->tctrl, tempval);
2387 }
2388
2389 if (features & NETIF_F_HW_VLAN_CTAG_RX) {
2390 /* Enable VLAN tag extraction */
2391 tempval = gfar_read(&regs->rctrl);
2392 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2393 gfar_write(&regs->rctrl, tempval);
2394 priv->uses_rxfcb = 1;
2395 } else {
2396 /* Disable VLAN tag extraction */
2397 tempval = gfar_read(&regs->rctrl);
2398 tempval &= ~RCTRL_VLEX;
2399 gfar_write(&regs->rctrl, tempval);
2400
2401 gfar_check_rx_parser_mode(priv);
2402 }
2403
2404 gfar_change_mtu(dev, dev->mtu);
2405
2406 unlock_rx_qs(priv);
2407 local_irq_restore(flags);
2408 }
2409
2410 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2411 {
2412 int tempsize, tempval;
2413 struct gfar_private *priv = netdev_priv(dev);
2414 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2415 int oldsize = priv->rx_buffer_size;
2416 int frame_size = new_mtu + ETH_HLEN;
2417
2418 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2419 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2420 return -EINVAL;
2421 }
2422
2423 if (priv->uses_rxfcb)
2424 frame_size += GMAC_FCB_LEN;
2425
2426 frame_size += priv->padding;
2427
2428 tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2429 INCREMENTAL_BUFFER_SIZE;
2430
2431 /* Only stop and start the controller if it isn't already
2432 * stopped, and we changed something
2433 */
2434 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2435 stop_gfar(dev);
2436
2437 priv->rx_buffer_size = tempsize;
2438
2439 dev->mtu = new_mtu;
2440
2441 gfar_write(&regs->mrblr, priv->rx_buffer_size);
2442 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2443
2444 /* If the mtu is larger than the max size for standard
2445 * ethernet frames (ie, a jumbo frame), then set maccfg2
2446 * to allow huge frames, and to check the length
2447 */
2448 tempval = gfar_read(&regs->maccfg2);
2449
2450 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2451 gfar_has_errata(priv, GFAR_ERRATA_74))
2452 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2453 else
2454 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2455
2456 gfar_write(&regs->maccfg2, tempval);
2457
2458 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2459 startup_gfar(dev);
2460
2461 return 0;
2462 }
2463
2464 /* gfar_reset_task gets scheduled when a packet has not been
2465 * transmitted after a set amount of time.
2466 * For now, assume that clearing out all the structures, and
2467 * starting over will fix the problem.
2468 */
2469 static void gfar_reset_task(struct work_struct *work)
2470 {
2471 struct gfar_private *priv = container_of(work, struct gfar_private,
2472 reset_task);
2473 struct net_device *dev = priv->ndev;
2474
2475 if (dev->flags & IFF_UP) {
2476 netif_tx_stop_all_queues(dev);
2477 stop_gfar(dev);
2478 startup_gfar(dev);
2479 netif_tx_start_all_queues(dev);
2480 }
2481
2482 netif_tx_schedule_all(dev);
2483 }
2484
2485 static void gfar_timeout(struct net_device *dev)
2486 {
2487 struct gfar_private *priv = netdev_priv(dev);
2488
2489 dev->stats.tx_errors++;
2490 schedule_work(&priv->reset_task);
2491 }
2492
2493 static void gfar_align_skb(struct sk_buff *skb)
2494 {
2495 /* We need the data buffer to be aligned properly. We will reserve
2496 * as many bytes as needed to align the data properly
2497 */
2498 skb_reserve(skb, RXBUF_ALIGNMENT -
2499 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2500 }
2501
2502 /* Interrupt Handler for Transmit complete */
2503 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2504 {
2505 struct net_device *dev = tx_queue->dev;
2506 struct netdev_queue *txq;
2507 struct gfar_private *priv = netdev_priv(dev);
2508 struct txbd8 *bdp, *next = NULL;
2509 struct txbd8 *lbdp = NULL;
2510 struct txbd8 *base = tx_queue->tx_bd_base;
2511 struct sk_buff *skb;
2512 int skb_dirtytx;
2513 int tx_ring_size = tx_queue->tx_ring_size;
2514 int frags = 0, nr_txbds = 0;
2515 int i;
2516 int howmany = 0;
2517 int tqi = tx_queue->qindex;
2518 unsigned int bytes_sent = 0;
2519 u32 lstatus;
2520 size_t buflen;
2521
2522 txq = netdev_get_tx_queue(dev, tqi);
2523 bdp = tx_queue->dirty_tx;
2524 skb_dirtytx = tx_queue->skb_dirtytx;
2525
2526 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2527 unsigned long flags;
2528
2529 frags = skb_shinfo(skb)->nr_frags;
2530
2531 /* When time stamping, one additional TxBD must be freed.
2532 * Also, we need to dma_unmap_single() the TxPAL.
2533 */
2534 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2535 nr_txbds = frags + 2;
2536 else
2537 nr_txbds = frags + 1;
2538
2539 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2540
2541 lstatus = lbdp->lstatus;
2542
2543 /* Only clean completed frames */
2544 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2545 (lstatus & BD_LENGTH_MASK))
2546 break;
2547
2548 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2549 next = next_txbd(bdp, base, tx_ring_size);
2550 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2551 } else
2552 buflen = bdp->length;
2553
2554 dma_unmap_single(priv->dev, bdp->bufPtr,
2555 buflen, DMA_TO_DEVICE);
2556
2557 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2558 struct skb_shared_hwtstamps shhwtstamps;
2559 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2560
2561 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2562 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2563 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2564 skb_tstamp_tx(skb, &shhwtstamps);
2565 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2566 bdp = next;
2567 }
2568
2569 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2570 bdp = next_txbd(bdp, base, tx_ring_size);
2571
2572 for (i = 0; i < frags; i++) {
2573 dma_unmap_page(priv->dev, bdp->bufPtr,
2574 bdp->length, DMA_TO_DEVICE);
2575 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2576 bdp = next_txbd(bdp, base, tx_ring_size);
2577 }
2578
2579 bytes_sent += GFAR_CB(skb)->bytes_sent;
2580
2581 dev_kfree_skb_any(skb);
2582
2583 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2584
2585 skb_dirtytx = (skb_dirtytx + 1) &
2586 TX_RING_MOD_MASK(tx_ring_size);
2587
2588 howmany++;
2589 spin_lock_irqsave(&tx_queue->txlock, flags);
2590 tx_queue->num_txbdfree += nr_txbds;
2591 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2592 }
2593
2594 /* If we freed a buffer, we can restart transmission, if necessary */
2595 if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2596 netif_wake_subqueue(dev, tqi);
2597
2598 /* Update dirty indicators */
2599 tx_queue->skb_dirtytx = skb_dirtytx;
2600 tx_queue->dirty_tx = bdp;
2601
2602 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2603 }
2604
2605 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2606 {
2607 unsigned long flags;
2608
2609 spin_lock_irqsave(&gfargrp->grplock, flags);
2610 if (napi_schedule_prep(&gfargrp->napi)) {
2611 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2612 __napi_schedule(&gfargrp->napi);
2613 } else {
2614 /* Clear IEVENT, so interrupts aren't called again
2615 * because of the packets that have already arrived.
2616 */
2617 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2618 }
2619 spin_unlock_irqrestore(&gfargrp->grplock, flags);
2620
2621 }
2622
2623 /* Interrupt Handler for Transmit complete */
2624 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2625 {
2626 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2627 return IRQ_HANDLED;
2628 }
2629
2630 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2631 struct sk_buff *skb)
2632 {
2633 struct net_device *dev = rx_queue->dev;
2634 struct gfar_private *priv = netdev_priv(dev);
2635 dma_addr_t buf;
2636
2637 buf = dma_map_single(priv->dev, skb->data,
2638 priv->rx_buffer_size, DMA_FROM_DEVICE);
2639 gfar_init_rxbdp(rx_queue, bdp, buf);
2640 }
2641
2642 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2643 {
2644 struct gfar_private *priv = netdev_priv(dev);
2645 struct sk_buff *skb;
2646
2647 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2648 if (!skb)
2649 return NULL;
2650
2651 gfar_align_skb(skb);
2652
2653 return skb;
2654 }
2655
2656 struct sk_buff *gfar_new_skb(struct net_device *dev)
2657 {
2658 return gfar_alloc_skb(dev);
2659 }
2660
2661 static inline void count_errors(unsigned short status, struct net_device *dev)
2662 {
2663 struct gfar_private *priv = netdev_priv(dev);
2664 struct net_device_stats *stats = &dev->stats;
2665 struct gfar_extra_stats *estats = &priv->extra_stats;
2666
2667 /* If the packet was truncated, none of the other errors matter */
2668 if (status & RXBD_TRUNCATED) {
2669 stats->rx_length_errors++;
2670
2671 atomic64_inc(&estats->rx_trunc);
2672
2673 return;
2674 }
2675 /* Count the errors, if there were any */
2676 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2677 stats->rx_length_errors++;
2678
2679 if (status & RXBD_LARGE)
2680 atomic64_inc(&estats->rx_large);
2681 else
2682 atomic64_inc(&estats->rx_short);
2683 }
2684 if (status & RXBD_NONOCTET) {
2685 stats->rx_frame_errors++;
2686 atomic64_inc(&estats->rx_nonoctet);
2687 }
2688 if (status & RXBD_CRCERR) {
2689 atomic64_inc(&estats->rx_crcerr);
2690 stats->rx_crc_errors++;
2691 }
2692 if (status & RXBD_OVERRUN) {
2693 atomic64_inc(&estats->rx_overrun);
2694 stats->rx_crc_errors++;
2695 }
2696 }
2697
2698 irqreturn_t gfar_receive(int irq, void *grp_id)
2699 {
2700 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2701 return IRQ_HANDLED;
2702 }
2703
2704 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2705 {
2706 /* If valid headers were found, and valid sums
2707 * were verified, then we tell the kernel that no
2708 * checksumming is necessary. Otherwise, it is [FIXME]
2709 */
2710 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2711 skb->ip_summed = CHECKSUM_UNNECESSARY;
2712 else
2713 skb_checksum_none_assert(skb);
2714 }
2715
2716
2717 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2718 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2719 int amount_pull, struct napi_struct *napi)
2720 {
2721 struct gfar_private *priv = netdev_priv(dev);
2722 struct rxfcb *fcb = NULL;
2723
2724 /* fcb is at the beginning if exists */
2725 fcb = (struct rxfcb *)skb->data;
2726
2727 /* Remove the FCB from the skb
2728 * Remove the padded bytes, if there are any
2729 */
2730 if (amount_pull) {
2731 skb_record_rx_queue(skb, fcb->rq);
2732 skb_pull(skb, amount_pull);
2733 }
2734
2735 /* Get receive timestamp from the skb */
2736 if (priv->hwts_rx_en) {
2737 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2738 u64 *ns = (u64 *) skb->data;
2739
2740 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2741 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2742 }
2743
2744 if (priv->padding)
2745 skb_pull(skb, priv->padding);
2746
2747 if (dev->features & NETIF_F_RXCSUM)
2748 gfar_rx_checksum(skb, fcb);
2749
2750 /* Tell the skb what kind of packet this is */
2751 skb->protocol = eth_type_trans(skb, dev);
2752
2753 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2754 * Even if vlan rx accel is disabled, on some chips
2755 * RXFCB_VLN is pseudo randomly set.
2756 */
2757 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2758 fcb->flags & RXFCB_VLN)
2759 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl);
2760
2761 /* Send the packet up the stack */
2762 napi_gro_receive(napi, skb);
2763
2764 }
2765
2766 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2767 * until the budget/quota has been reached. Returns the number
2768 * of frames handled
2769 */
2770 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2771 {
2772 struct net_device *dev = rx_queue->dev;
2773 struct rxbd8 *bdp, *base;
2774 struct sk_buff *skb;
2775 int pkt_len;
2776 int amount_pull;
2777 int howmany = 0;
2778 struct gfar_private *priv = netdev_priv(dev);
2779
2780 /* Get the first full descriptor */
2781 bdp = rx_queue->cur_rx;
2782 base = rx_queue->rx_bd_base;
2783
2784 amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2785
2786 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2787 struct sk_buff *newskb;
2788
2789 rmb();
2790
2791 /* Add another skb for the future */
2792 newskb = gfar_new_skb(dev);
2793
2794 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2795
2796 dma_unmap_single(priv->dev, bdp->bufPtr,
2797 priv->rx_buffer_size, DMA_FROM_DEVICE);
2798
2799 if (unlikely(!(bdp->status & RXBD_ERR) &&
2800 bdp->length > priv->rx_buffer_size))
2801 bdp->status = RXBD_LARGE;
2802
2803 /* We drop the frame if we failed to allocate a new buffer */
2804 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2805 bdp->status & RXBD_ERR)) {
2806 count_errors(bdp->status, dev);
2807
2808 if (unlikely(!newskb))
2809 newskb = skb;
2810 else if (skb)
2811 dev_kfree_skb(skb);
2812 } else {
2813 /* Increment the number of packets */
2814 rx_queue->stats.rx_packets++;
2815 howmany++;
2816
2817 if (likely(skb)) {
2818 pkt_len = bdp->length - ETH_FCS_LEN;
2819 /* Remove the FCS from the packet length */
2820 skb_put(skb, pkt_len);
2821 rx_queue->stats.rx_bytes += pkt_len;
2822 skb_record_rx_queue(skb, rx_queue->qindex);
2823 gfar_process_frame(dev, skb, amount_pull,
2824 &rx_queue->grp->napi);
2825
2826 } else {
2827 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2828 rx_queue->stats.rx_dropped++;
2829 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2830 }
2831
2832 }
2833
2834 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2835
2836 /* Setup the new bdp */
2837 gfar_new_rxbdp(rx_queue, bdp, newskb);
2838
2839 /* Update to the next pointer */
2840 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2841
2842 /* update to point at the next skb */
2843 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2844 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2845 }
2846
2847 /* Update the current rxbd pointer to be the next one */
2848 rx_queue->cur_rx = bdp;
2849
2850 return howmany;
2851 }
2852
2853 static int gfar_poll_sq(struct napi_struct *napi, int budget)
2854 {
2855 struct gfar_priv_grp *gfargrp =
2856 container_of(napi, struct gfar_priv_grp, napi);
2857 struct gfar __iomem *regs = gfargrp->regs;
2858 struct gfar_priv_tx_q *tx_queue = gfargrp->priv->tx_queue[0];
2859 struct gfar_priv_rx_q *rx_queue = gfargrp->priv->rx_queue[0];
2860 int work_done = 0;
2861
2862 /* Clear IEVENT, so interrupts aren't called again
2863 * because of the packets that have already arrived
2864 */
2865 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2866
2867 /* run Tx cleanup to completion */
2868 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2869 gfar_clean_tx_ring(tx_queue);
2870
2871 work_done = gfar_clean_rx_ring(rx_queue, budget);
2872
2873 if (work_done < budget) {
2874 napi_complete(napi);
2875 /* Clear the halt bit in RSTAT */
2876 gfar_write(&regs->rstat, gfargrp->rstat);
2877
2878 gfar_write(&regs->imask, IMASK_DEFAULT);
2879
2880 /* If we are coalescing interrupts, update the timer
2881 * Otherwise, clear it
2882 */
2883 gfar_write(&regs->txic, 0);
2884 if (likely(tx_queue->txcoalescing))
2885 gfar_write(&regs->txic, tx_queue->txic);
2886
2887 gfar_write(&regs->rxic, 0);
2888 if (unlikely(rx_queue->rxcoalescing))
2889 gfar_write(&regs->rxic, rx_queue->rxic);
2890 }
2891
2892 return work_done;
2893 }
2894
2895 static int gfar_poll(struct napi_struct *napi, int budget)
2896 {
2897 struct gfar_priv_grp *gfargrp =
2898 container_of(napi, struct gfar_priv_grp, napi);
2899 struct gfar_private *priv = gfargrp->priv;
2900 struct gfar __iomem *regs = gfargrp->regs;
2901 struct gfar_priv_tx_q *tx_queue = NULL;
2902 struct gfar_priv_rx_q *rx_queue = NULL;
2903 int work_done = 0, work_done_per_q = 0;
2904 int i, budget_per_q = 0;
2905 int has_tx_work;
2906 unsigned long rstat_rxf;
2907 int num_act_queues;
2908
2909 /* Clear IEVENT, so interrupts aren't called again
2910 * because of the packets that have already arrived
2911 */
2912 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2913
2914 rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
2915
2916 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2917 if (num_act_queues)
2918 budget_per_q = budget/num_act_queues;
2919
2920 while (1) {
2921 has_tx_work = 0;
2922 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2923 tx_queue = priv->tx_queue[i];
2924 /* run Tx cleanup to completion */
2925 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2926 gfar_clean_tx_ring(tx_queue);
2927 has_tx_work = 1;
2928 }
2929 }
2930
2931 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2932 /* skip queue if not active */
2933 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2934 continue;
2935
2936 rx_queue = priv->rx_queue[i];
2937 work_done_per_q =
2938 gfar_clean_rx_ring(rx_queue, budget_per_q);
2939 work_done += work_done_per_q;
2940
2941 /* finished processing this queue */
2942 if (work_done_per_q < budget_per_q) {
2943 /* clear active queue hw indication */
2944 gfar_write(&regs->rstat,
2945 RSTAT_CLEAR_RXF0 >> i);
2946 rstat_rxf &= ~(RSTAT_CLEAR_RXF0 >> i);
2947 num_act_queues--;
2948
2949 if (!num_act_queues)
2950 break;
2951 /* recompute budget per Rx queue */
2952 budget_per_q =
2953 (budget - work_done) / num_act_queues;
2954 }
2955 }
2956
2957 if (work_done >= budget)
2958 break;
2959
2960 if (!num_act_queues && !has_tx_work) {
2961
2962 napi_complete(napi);
2963
2964 /* Clear the halt bit in RSTAT */
2965 gfar_write(&regs->rstat, gfargrp->rstat);
2966
2967 gfar_write(&regs->imask, IMASK_DEFAULT);
2968
2969 /* If we are coalescing interrupts, update the timer
2970 * Otherwise, clear it
2971 */
2972 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2973 gfargrp->tx_bit_map);
2974 break;
2975 }
2976 }
2977
2978 return work_done;
2979 }
2980
2981 #ifdef CONFIG_NET_POLL_CONTROLLER
2982 /* Polling 'interrupt' - used by things like netconsole to send skbs
2983 * without having to re-enable interrupts. It's not called while
2984 * the interrupt routine is executing.
2985 */
2986 static void gfar_netpoll(struct net_device *dev)
2987 {
2988 struct gfar_private *priv = netdev_priv(dev);
2989 int i;
2990
2991 /* If the device has multiple interrupts, run tx/rx */
2992 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2993 for (i = 0; i < priv->num_grps; i++) {
2994 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2995
2996 disable_irq(gfar_irq(grp, TX)->irq);
2997 disable_irq(gfar_irq(grp, RX)->irq);
2998 disable_irq(gfar_irq(grp, ER)->irq);
2999 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3000 enable_irq(gfar_irq(grp, ER)->irq);
3001 enable_irq(gfar_irq(grp, RX)->irq);
3002 enable_irq(gfar_irq(grp, TX)->irq);
3003 }
3004 } else {
3005 for (i = 0; i < priv->num_grps; i++) {
3006 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3007
3008 disable_irq(gfar_irq(grp, TX)->irq);
3009 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3010 enable_irq(gfar_irq(grp, TX)->irq);
3011 }
3012 }
3013 }
3014 #endif
3015
3016 /* The interrupt handler for devices with one interrupt */
3017 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3018 {
3019 struct gfar_priv_grp *gfargrp = grp_id;
3020
3021 /* Save ievent for future reference */
3022 u32 events = gfar_read(&gfargrp->regs->ievent);
3023
3024 /* Check for reception */
3025 if (events & IEVENT_RX_MASK)
3026 gfar_receive(irq, grp_id);
3027
3028 /* Check for transmit completion */
3029 if (events & IEVENT_TX_MASK)
3030 gfar_transmit(irq, grp_id);
3031
3032 /* Check for errors */
3033 if (events & IEVENT_ERR_MASK)
3034 gfar_error(irq, grp_id);
3035
3036 return IRQ_HANDLED;
3037 }
3038
3039 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3040 {
3041 struct phy_device *phydev = priv->phydev;
3042 u32 val = 0;
3043
3044 if (!phydev->duplex)
3045 return val;
3046
3047 if (!priv->pause_aneg_en) {
3048 if (priv->tx_pause_en)
3049 val |= MACCFG1_TX_FLOW;
3050 if (priv->rx_pause_en)
3051 val |= MACCFG1_RX_FLOW;
3052 } else {
3053 u16 lcl_adv, rmt_adv;
3054 u8 flowctrl;
3055 /* get link partner capabilities */
3056 rmt_adv = 0;
3057 if (phydev->pause)
3058 rmt_adv = LPA_PAUSE_CAP;
3059 if (phydev->asym_pause)
3060 rmt_adv |= LPA_PAUSE_ASYM;
3061
3062 lcl_adv = mii_advertise_flowctrl(phydev->advertising);
3063
3064 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3065 if (flowctrl & FLOW_CTRL_TX)
3066 val |= MACCFG1_TX_FLOW;
3067 if (flowctrl & FLOW_CTRL_RX)
3068 val |= MACCFG1_RX_FLOW;
3069 }
3070
3071 return val;
3072 }
3073
3074 /* Called every time the controller might need to be made
3075 * aware of new link state. The PHY code conveys this
3076 * information through variables in the phydev structure, and this
3077 * function converts those variables into the appropriate
3078 * register values, and can bring down the device if needed.
3079 */
3080 static void adjust_link(struct net_device *dev)
3081 {
3082 struct gfar_private *priv = netdev_priv(dev);
3083 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3084 unsigned long flags;
3085 struct phy_device *phydev = priv->phydev;
3086 int new_state = 0;
3087
3088 local_irq_save(flags);
3089 lock_tx_qs(priv);
3090
3091 if (phydev->link) {
3092 u32 tempval1 = gfar_read(&regs->maccfg1);
3093 u32 tempval = gfar_read(&regs->maccfg2);
3094 u32 ecntrl = gfar_read(&regs->ecntrl);
3095
3096 /* Now we make sure that we can be in full duplex mode.
3097 * If not, we operate in half-duplex mode.
3098 */
3099 if (phydev->duplex != priv->oldduplex) {
3100 new_state = 1;
3101 if (!(phydev->duplex))
3102 tempval &= ~(MACCFG2_FULL_DUPLEX);
3103 else
3104 tempval |= MACCFG2_FULL_DUPLEX;
3105
3106 priv->oldduplex = phydev->duplex;
3107 }
3108
3109 if (phydev->speed != priv->oldspeed) {
3110 new_state = 1;
3111 switch (phydev->speed) {
3112 case 1000:
3113 tempval =
3114 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3115
3116 ecntrl &= ~(ECNTRL_R100);
3117 break;
3118 case 100:
3119 case 10:
3120 tempval =
3121 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3122
3123 /* Reduced mode distinguishes
3124 * between 10 and 100
3125 */
3126 if (phydev->speed == SPEED_100)
3127 ecntrl |= ECNTRL_R100;
3128 else
3129 ecntrl &= ~(ECNTRL_R100);
3130 break;
3131 default:
3132 netif_warn(priv, link, dev,
3133 "Ack! Speed (%d) is not 10/100/1000!\n",
3134 phydev->speed);
3135 break;
3136 }
3137
3138 priv->oldspeed = phydev->speed;
3139 }
3140
3141 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3142 tempval1 |= gfar_get_flowctrl_cfg(priv);
3143
3144 gfar_write(&regs->maccfg1, tempval1);
3145 gfar_write(&regs->maccfg2, tempval);
3146 gfar_write(&regs->ecntrl, ecntrl);
3147
3148 if (!priv->oldlink) {
3149 new_state = 1;
3150 priv->oldlink = 1;
3151 }
3152 } else if (priv->oldlink) {
3153 new_state = 1;
3154 priv->oldlink = 0;
3155 priv->oldspeed = 0;
3156 priv->oldduplex = -1;
3157 }
3158
3159 if (new_state && netif_msg_link(priv))
3160 phy_print_status(phydev);
3161 unlock_tx_qs(priv);
3162 local_irq_restore(flags);
3163 }
3164
3165 /* Update the hash table based on the current list of multicast
3166 * addresses we subscribe to. Also, change the promiscuity of
3167 * the device based on the flags (this function is called
3168 * whenever dev->flags is changed
3169 */
3170 static void gfar_set_multi(struct net_device *dev)
3171 {
3172 struct netdev_hw_addr *ha;
3173 struct gfar_private *priv = netdev_priv(dev);
3174 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3175 u32 tempval;
3176
3177 if (dev->flags & IFF_PROMISC) {
3178 /* Set RCTRL to PROM */
3179 tempval = gfar_read(&regs->rctrl);
3180 tempval |= RCTRL_PROM;
3181 gfar_write(&regs->rctrl, tempval);
3182 } else {
3183 /* Set RCTRL to not PROM */
3184 tempval = gfar_read(&regs->rctrl);
3185 tempval &= ~(RCTRL_PROM);
3186 gfar_write(&regs->rctrl, tempval);
3187 }
3188
3189 if (dev->flags & IFF_ALLMULTI) {
3190 /* Set the hash to rx all multicast frames */
3191 gfar_write(&regs->igaddr0, 0xffffffff);
3192 gfar_write(&regs->igaddr1, 0xffffffff);
3193 gfar_write(&regs->igaddr2, 0xffffffff);
3194 gfar_write(&regs->igaddr3, 0xffffffff);
3195 gfar_write(&regs->igaddr4, 0xffffffff);
3196 gfar_write(&regs->igaddr5, 0xffffffff);
3197 gfar_write(&regs->igaddr6, 0xffffffff);
3198 gfar_write(&regs->igaddr7, 0xffffffff);
3199 gfar_write(&regs->gaddr0, 0xffffffff);
3200 gfar_write(&regs->gaddr1, 0xffffffff);
3201 gfar_write(&regs->gaddr2, 0xffffffff);
3202 gfar_write(&regs->gaddr3, 0xffffffff);
3203 gfar_write(&regs->gaddr4, 0xffffffff);
3204 gfar_write(&regs->gaddr5, 0xffffffff);
3205 gfar_write(&regs->gaddr6, 0xffffffff);
3206 gfar_write(&regs->gaddr7, 0xffffffff);
3207 } else {
3208 int em_num;
3209 int idx;
3210
3211 /* zero out the hash */
3212 gfar_write(&regs->igaddr0, 0x0);
3213 gfar_write(&regs->igaddr1, 0x0);
3214 gfar_write(&regs->igaddr2, 0x0);
3215 gfar_write(&regs->igaddr3, 0x0);
3216 gfar_write(&regs->igaddr4, 0x0);
3217 gfar_write(&regs->igaddr5, 0x0);
3218 gfar_write(&regs->igaddr6, 0x0);
3219 gfar_write(&regs->igaddr7, 0x0);
3220 gfar_write(&regs->gaddr0, 0x0);
3221 gfar_write(&regs->gaddr1, 0x0);
3222 gfar_write(&regs->gaddr2, 0x0);
3223 gfar_write(&regs->gaddr3, 0x0);
3224 gfar_write(&regs->gaddr4, 0x0);
3225 gfar_write(&regs->gaddr5, 0x0);
3226 gfar_write(&regs->gaddr6, 0x0);
3227 gfar_write(&regs->gaddr7, 0x0);
3228
3229 /* If we have extended hash tables, we need to
3230 * clear the exact match registers to prepare for
3231 * setting them
3232 */
3233 if (priv->extended_hash) {
3234 em_num = GFAR_EM_NUM + 1;
3235 gfar_clear_exact_match(dev);
3236 idx = 1;
3237 } else {
3238 idx = 0;
3239 em_num = 0;
3240 }
3241
3242 if (netdev_mc_empty(dev))
3243 return;
3244
3245 /* Parse the list, and set the appropriate bits */
3246 netdev_for_each_mc_addr(ha, dev) {
3247 if (idx < em_num) {
3248 gfar_set_mac_for_addr(dev, idx, ha->addr);
3249 idx++;
3250 } else
3251 gfar_set_hash_for_addr(dev, ha->addr);
3252 }
3253 }
3254 }
3255
3256
3257 /* Clears each of the exact match registers to zero, so they
3258 * don't interfere with normal reception
3259 */
3260 static void gfar_clear_exact_match(struct net_device *dev)
3261 {
3262 int idx;
3263 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3264
3265 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3266 gfar_set_mac_for_addr(dev, idx, zero_arr);
3267 }
3268
3269 /* Set the appropriate hash bit for the given addr */
3270 /* The algorithm works like so:
3271 * 1) Take the Destination Address (ie the multicast address), and
3272 * do a CRC on it (little endian), and reverse the bits of the
3273 * result.
3274 * 2) Use the 8 most significant bits as a hash into a 256-entry
3275 * table. The table is controlled through 8 32-bit registers:
3276 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3277 * gaddr7. This means that the 3 most significant bits in the
3278 * hash index which gaddr register to use, and the 5 other bits
3279 * indicate which bit (assuming an IBM numbering scheme, which
3280 * for PowerPC (tm) is usually the case) in the register holds
3281 * the entry.
3282 */
3283 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3284 {
3285 u32 tempval;
3286 struct gfar_private *priv = netdev_priv(dev);
3287 u32 result = ether_crc(ETH_ALEN, addr);
3288 int width = priv->hash_width;
3289 u8 whichbit = (result >> (32 - width)) & 0x1f;
3290 u8 whichreg = result >> (32 - width + 5);
3291 u32 value = (1 << (31-whichbit));
3292
3293 tempval = gfar_read(priv->hash_regs[whichreg]);
3294 tempval |= value;
3295 gfar_write(priv->hash_regs[whichreg], tempval);
3296 }
3297
3298
3299 /* There are multiple MAC Address register pairs on some controllers
3300 * This function sets the numth pair to a given address
3301 */
3302 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3303 const u8 *addr)
3304 {
3305 struct gfar_private *priv = netdev_priv(dev);
3306 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3307 int idx;
3308 char tmpbuf[ETH_ALEN];
3309 u32 tempval;
3310 u32 __iomem *macptr = &regs->macstnaddr1;
3311
3312 macptr += num*2;
3313
3314 /* Now copy it into the mac registers backwards, cuz
3315 * little endian is silly
3316 */
3317 for (idx = 0; idx < ETH_ALEN; idx++)
3318 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3319
3320 gfar_write(macptr, *((u32 *) (tmpbuf)));
3321
3322 tempval = *((u32 *) (tmpbuf + 4));
3323
3324 gfar_write(macptr+1, tempval);
3325 }
3326
3327 /* GFAR error interrupt handler */
3328 static irqreturn_t gfar_error(int irq, void *grp_id)
3329 {
3330 struct gfar_priv_grp *gfargrp = grp_id;
3331 struct gfar __iomem *regs = gfargrp->regs;
3332 struct gfar_private *priv= gfargrp->priv;
3333 struct net_device *dev = priv->ndev;
3334
3335 /* Save ievent for future reference */
3336 u32 events = gfar_read(&regs->ievent);
3337
3338 /* Clear IEVENT */
3339 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3340
3341 /* Magic Packet is not an error. */
3342 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3343 (events & IEVENT_MAG))
3344 events &= ~IEVENT_MAG;
3345
3346 /* Hmm... */
3347 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3348 netdev_dbg(dev,
3349 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3350 events, gfar_read(&regs->imask));
3351
3352 /* Update the error counters */
3353 if (events & IEVENT_TXE) {
3354 dev->stats.tx_errors++;
3355
3356 if (events & IEVENT_LC)
3357 dev->stats.tx_window_errors++;
3358 if (events & IEVENT_CRL)
3359 dev->stats.tx_aborted_errors++;
3360 if (events & IEVENT_XFUN) {
3361 unsigned long flags;
3362
3363 netif_dbg(priv, tx_err, dev,
3364 "TX FIFO underrun, packet dropped\n");
3365 dev->stats.tx_dropped++;
3366 atomic64_inc(&priv->extra_stats.tx_underrun);
3367
3368 local_irq_save(flags);
3369 lock_tx_qs(priv);
3370
3371 /* Reactivate the Tx Queues */
3372 gfar_write(&regs->tstat, gfargrp->tstat);
3373
3374 unlock_tx_qs(priv);
3375 local_irq_restore(flags);
3376 }
3377 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3378 }
3379 if (events & IEVENT_BSY) {
3380 dev->stats.rx_errors++;
3381 atomic64_inc(&priv->extra_stats.rx_bsy);
3382
3383 gfar_receive(irq, grp_id);
3384
3385 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3386 gfar_read(&regs->rstat));
3387 }
3388 if (events & IEVENT_BABR) {
3389 dev->stats.rx_errors++;
3390 atomic64_inc(&priv->extra_stats.rx_babr);
3391
3392 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3393 }
3394 if (events & IEVENT_EBERR) {
3395 atomic64_inc(&priv->extra_stats.eberr);
3396 netif_dbg(priv, rx_err, dev, "bus error\n");
3397 }
3398 if (events & IEVENT_RXC)
3399 netif_dbg(priv, rx_status, dev, "control frame\n");
3400
3401 if (events & IEVENT_BABT) {
3402 atomic64_inc(&priv->extra_stats.tx_babt);
3403 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3404 }
3405 return IRQ_HANDLED;
3406 }
3407
3408 static struct of_device_id gfar_match[] =
3409 {
3410 {
3411 .type = "network",
3412 .compatible = "gianfar",
3413 },
3414 {
3415 .compatible = "fsl,etsec2",
3416 },
3417 {},
3418 };
3419 MODULE_DEVICE_TABLE(of, gfar_match);
3420
3421 /* Structure for a device driver */
3422 static struct platform_driver gfar_driver = {
3423 .driver = {
3424 .name = "fsl-gianfar",
3425 .owner = THIS_MODULE,
3426 .pm = GFAR_PM_OPS,
3427 .of_match_table = gfar_match,
3428 },
3429 .probe = gfar_probe,
3430 .remove = gfar_remove,
3431 };
3432
3433 module_platform_driver(gfar_driver);
Linux kernel - Deliverables
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