2 * Copyright (c) 2014-2015 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include "hns_dsaf_mac.h"
11 #include "hns_dsaf_misc.h"
12 #include "hns_dsaf_ppe.h"
13 #include "hns_dsaf_reg.h"
15 static void dsaf_write_sub(struct dsaf_device
*dsaf_dev
, u32 reg
, u32 val
)
17 if (dsaf_dev
->sub_ctrl
)
18 dsaf_write_syscon(dsaf_dev
->sub_ctrl
, reg
, val
);
20 dsaf_write_reg(dsaf_dev
->sc_base
, reg
, val
);
23 static u32
dsaf_read_sub(struct dsaf_device
*dsaf_dev
, u32 reg
)
27 if (dsaf_dev
->sub_ctrl
)
28 ret
= dsaf_read_syscon(dsaf_dev
->sub_ctrl
, reg
);
30 ret
= dsaf_read_reg(dsaf_dev
->sc_base
, reg
);
35 static void hns_cpld_set_led(struct hns_mac_cb
*mac_cb
, int link_status
,
42 pr_err("sfp_led_opt mac_dev is null!\n");
45 if (!mac_cb
->cpld_ctrl
) {
46 dev_err(mac_cb
->dev
, "mac_id=%d, cpld syscon is null !\n",
51 if (speed
== MAC_SPEED_10000
)
54 value
= mac_cb
->cpld_led_value
;
57 dsaf_set_bit(value
, DSAF_LED_LINK_B
, link_status
);
58 dsaf_set_field(value
, DSAF_LED_SPEED_M
,
59 DSAF_LED_SPEED_S
, speed_reg
);
60 dsaf_set_bit(value
, DSAF_LED_DATA_B
, data
);
62 if (value
!= mac_cb
->cpld_led_value
) {
63 dsaf_write_syscon(mac_cb
->cpld_ctrl
,
64 mac_cb
->cpld_ctrl_reg
, value
);
65 mac_cb
->cpld_led_value
= value
;
68 dsaf_write_syscon(mac_cb
->cpld_ctrl
, mac_cb
->cpld_ctrl_reg
,
69 CPLD_LED_DEFAULT_VALUE
);
70 mac_cb
->cpld_led_value
= CPLD_LED_DEFAULT_VALUE
;
74 static void cpld_led_reset(struct hns_mac_cb
*mac_cb
)
76 if (!mac_cb
|| !mac_cb
->cpld_ctrl
)
79 dsaf_write_syscon(mac_cb
->cpld_ctrl
, mac_cb
->cpld_ctrl_reg
,
80 CPLD_LED_DEFAULT_VALUE
);
81 mac_cb
->cpld_led_value
= CPLD_LED_DEFAULT_VALUE
;
84 static int cpld_set_led_id(struct hns_mac_cb
*mac_cb
,
85 enum hnae_led_state status
)
89 mac_cb
->cpld_led_value
=
90 dsaf_read_syscon(mac_cb
->cpld_ctrl
,
91 mac_cb
->cpld_ctrl_reg
);
92 dsaf_set_bit(mac_cb
->cpld_led_value
, DSAF_LED_ANCHOR_B
,
94 dsaf_write_syscon(mac_cb
->cpld_ctrl
, mac_cb
->cpld_ctrl_reg
,
95 mac_cb
->cpld_led_value
);
97 case HNAE_LED_INACTIVE
:
98 dsaf_set_bit(mac_cb
->cpld_led_value
, DSAF_LED_ANCHOR_B
,
99 CPLD_LED_DEFAULT_VALUE
);
100 dsaf_write_syscon(mac_cb
->cpld_ctrl
, mac_cb
->cpld_ctrl_reg
,
101 mac_cb
->cpld_led_value
);
110 #define RESET_REQ_OR_DREQ 1
112 static void hns_dsaf_rst(struct dsaf_device
*dsaf_dev
, bool dereset
)
118 xbar_reg_addr
= DSAF_SUB_SC_XBAR_RESET_REQ_REG
;
119 nt_reg_addr
= DSAF_SUB_SC_NT_RESET_REQ_REG
;
121 xbar_reg_addr
= DSAF_SUB_SC_XBAR_RESET_DREQ_REG
;
122 nt_reg_addr
= DSAF_SUB_SC_NT_RESET_DREQ_REG
;
125 dsaf_write_sub(dsaf_dev
, xbar_reg_addr
, RESET_REQ_OR_DREQ
);
126 dsaf_write_sub(dsaf_dev
, nt_reg_addr
, RESET_REQ_OR_DREQ
);
129 static void hns_dsaf_xge_srst_by_port(struct dsaf_device
*dsaf_dev
, u32 port
,
135 if (port
>= DSAF_XGE_NUM
)
138 reg_val
|= RESET_REQ_OR_DREQ
;
139 reg_val
|= 0x2082082 << dsaf_dev
->mac_cb
[port
]->port_rst_off
;
142 reg_addr
= DSAF_SUB_SC_XGE_RESET_REQ_REG
;
144 reg_addr
= DSAF_SUB_SC_XGE_RESET_DREQ_REG
;
146 dsaf_write_sub(dsaf_dev
, reg_addr
, reg_val
);
149 static void hns_dsaf_xge_core_srst_by_port(struct dsaf_device
*dsaf_dev
,
150 u32 port
, bool dereset
)
155 if (port
>= DSAF_XGE_NUM
)
158 reg_val
|= XGMAC_TRX_CORE_SRST_M
159 << dsaf_dev
->mac_cb
[port
]->port_rst_off
;
162 reg_addr
= DSAF_SUB_SC_XGE_RESET_REQ_REG
;
164 reg_addr
= DSAF_SUB_SC_XGE_RESET_DREQ_REG
;
166 dsaf_write_sub(dsaf_dev
, reg_addr
, reg_val
);
169 static void hns_dsaf_ge_srst_by_port(struct dsaf_device
*dsaf_dev
, u32 port
,
176 if (port
>= DSAF_GE_NUM
)
179 if (!HNS_DSAF_IS_DEBUG(dsaf_dev
)) {
180 reg_val_1
= 0x1 << port
;
181 port_rst_off
= dsaf_dev
->mac_cb
[port
]->port_rst_off
;
182 /* there is difference between V1 and V2 in register.*/
183 if (AE_IS_VER1(dsaf_dev
->dsaf_ver
))
184 reg_val_2
= 0x1041041 << port_rst_off
;
186 reg_val_2
= 0x2082082 << port_rst_off
;
189 dsaf_write_sub(dsaf_dev
, DSAF_SUB_SC_GE_RESET_REQ1_REG
,
192 dsaf_write_sub(dsaf_dev
, DSAF_SUB_SC_GE_RESET_REQ0_REG
,
195 dsaf_write_sub(dsaf_dev
, DSAF_SUB_SC_GE_RESET_DREQ0_REG
,
198 dsaf_write_sub(dsaf_dev
, DSAF_SUB_SC_GE_RESET_DREQ1_REG
,
202 reg_val_1
= 0x15540 << dsaf_dev
->reset_offset
;
203 reg_val_2
= 0x100 << dsaf_dev
->reset_offset
;
206 dsaf_write_sub(dsaf_dev
, DSAF_SUB_SC_GE_RESET_REQ1_REG
,
209 dsaf_write_sub(dsaf_dev
, DSAF_SUB_SC_PPE_RESET_REQ_REG
,
212 dsaf_write_sub(dsaf_dev
, DSAF_SUB_SC_GE_RESET_DREQ1_REG
,
215 dsaf_write_sub(dsaf_dev
, DSAF_SUB_SC_PPE_RESET_DREQ_REG
,
221 static void hns_ppe_srst_by_port(struct dsaf_device
*dsaf_dev
, u32 port
,
227 reg_val
|= RESET_REQ_OR_DREQ
<< dsaf_dev
->mac_cb
[port
]->port_rst_off
;
230 reg_addr
= DSAF_SUB_SC_PPE_RESET_REQ_REG
;
232 reg_addr
= DSAF_SUB_SC_PPE_RESET_DREQ_REG
;
234 dsaf_write_sub(dsaf_dev
, reg_addr
, reg_val
);
237 static void hns_ppe_com_srst(struct dsaf_device
*dsaf_dev
, bool dereset
)
242 if (!HNS_DSAF_IS_DEBUG(dsaf_dev
)) {
243 reg_val
= RESET_REQ_OR_DREQ
;
245 reg_addr
= DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG
;
247 reg_addr
= DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG
;
250 reg_val
= 0x100 << dsaf_dev
->reset_offset
;
253 reg_addr
= DSAF_SUB_SC_PPE_RESET_REQ_REG
;
255 reg_addr
= DSAF_SUB_SC_PPE_RESET_DREQ_REG
;
258 dsaf_write_sub(dsaf_dev
, reg_addr
, reg_val
);
262 * hns_mac_get_sds_mode - get phy ifterface form serdes mode
263 * @mac_cb: mac control block
264 * retuen phy interface
266 static phy_interface_t
hns_mac_get_phy_if(struct hns_mac_cb
*mac_cb
)
270 bool is_ver1
= AE_IS_VER1(mac_cb
->dsaf_dev
->dsaf_ver
);
271 int mac_id
= mac_cb
->mac_id
;
272 phy_interface_t phy_if
;
275 if (HNS_DSAF_IS_DEBUG(mac_cb
->dsaf_dev
))
276 return PHY_INTERFACE_MODE_SGMII
;
278 if (mac_id
>= 0 && mac_id
<= 3)
279 reg
= HNS_MAC_HILINK4_REG
;
281 reg
= HNS_MAC_HILINK3_REG
;
283 if (!HNS_DSAF_IS_DEBUG(mac_cb
->dsaf_dev
) && mac_id
<= 3)
284 reg
= HNS_MAC_HILINK4V2_REG
;
286 reg
= HNS_MAC_HILINK3V2_REG
;
289 mode
= dsaf_read_sub(mac_cb
->dsaf_dev
, reg
);
290 if (dsaf_get_bit(mode
, mac_cb
->port_mode_off
))
291 phy_if
= PHY_INTERFACE_MODE_XGMII
;
293 phy_if
= PHY_INTERFACE_MODE_SGMII
;
298 int hns_mac_get_sfp_prsnt(struct hns_mac_cb
*mac_cb
, int *sfp_prsnt
)
300 if (!mac_cb
->cpld_ctrl
)
303 *sfp_prsnt
= !dsaf_read_syscon(mac_cb
->cpld_ctrl
, mac_cb
->cpld_ctrl_reg
304 + MAC_SFP_PORT_OFFSET
);
310 * hns_mac_config_sds_loopback - set loop back for serdes
311 * @mac_cb: mac control block
312 * retuen 0 == success
314 static int hns_mac_config_sds_loopback(struct hns_mac_cb
*mac_cb
, bool en
)
316 /* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
317 * port 4-7 hilink3 base is serdes_vaddr + 0x00200000
319 u8
*base_addr
= (u8
*)mac_cb
->serdes_vaddr
+
320 (mac_cb
->mac_id
<= 3 ? 0x00280000 : 0x00200000);
321 const u8 lane_id
[] = {
322 0, /* mac 0 -> lane 0 */
323 1, /* mac 1 -> lane 1 */
324 2, /* mac 2 -> lane 2 */
325 3, /* mac 3 -> lane 3 */
326 2, /* mac 4 -> lane 2 */
327 3, /* mac 5 -> lane 3 */
328 0, /* mac 6 -> lane 0 */
329 1 /* mac 7 -> lane 1 */
331 #define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
332 u64 reg_offset
= RX_CSR(lane_id
[mac_cb
->mac_id
], 0);
335 int ret
= hns_mac_get_sfp_prsnt(mac_cb
, &sfp_prsnt
);
337 if (!mac_cb
->phy_dev
) {
339 pr_info("please confirm sfp is present or not\n");
342 pr_info("no sfp in this eth\n");
345 if (mac_cb
->serdes_ctrl
) {
346 u32 origin
= dsaf_read_syscon(mac_cb
->serdes_ctrl
, reg_offset
);
348 dsaf_set_field(origin
, 1ull << 10, 10, en
);
349 dsaf_write_syscon(mac_cb
->serdes_ctrl
, reg_offset
, origin
);
351 dsaf_set_reg_field(base_addr
, reg_offset
, 1ull << 10, 10, en
);
357 struct dsaf_misc_op
*hns_misc_op_get(struct dsaf_device
*dsaf_dev
)
359 struct dsaf_misc_op
*misc_op
;
361 misc_op
= devm_kzalloc(dsaf_dev
->dev
, sizeof(*misc_op
), GFP_KERNEL
);
365 misc_op
->cpld_set_led
= hns_cpld_set_led
;
366 misc_op
->cpld_reset_led
= cpld_led_reset
;
367 misc_op
->cpld_set_led_id
= cpld_set_led_id
;
369 misc_op
->dsaf_reset
= hns_dsaf_rst
;
370 misc_op
->xge_srst
= hns_dsaf_xge_srst_by_port
;
371 misc_op
->xge_core_srst
= hns_dsaf_xge_core_srst_by_port
;
372 misc_op
->ge_srst
= hns_dsaf_ge_srst_by_port
;
373 misc_op
->ppe_srst
= hns_ppe_srst_by_port
;
374 misc_op
->ppe_comm_srst
= hns_ppe_com_srst
;
376 misc_op
->get_phy_if
= hns_mac_get_phy_if
;
377 misc_op
->get_sfp_prsnt
= hns_mac_get_sfp_prsnt
;
379 misc_op
->cfg_serdes_loopback
= hns_mac_config_sds_loopback
;
381 return (void *)misc_op
;