drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

   1 /*
   2  * Copyright (c) 2014-2015 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include "hns_dsaf_mac.h"
  11 #include "hns_dsaf_misc.h"
  12 #include "hns_dsaf_ppe.h"
  13 #include "hns_dsaf_reg.h"
  14
  15 static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val)
  16 {
  17         if (dsaf_dev->sub_ctrl)
  18                 dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val);
  19         else
  20                 dsaf_write_reg(dsaf_dev->sc_base, reg, val);
  21 }
  22
  23 static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg)
  24 {
  25         u32 ret;
  26
  27         if (dsaf_dev->sub_ctrl)
  28                 ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg);
  29         else
  30                 ret = dsaf_read_reg(dsaf_dev->sc_base, reg);
  31
  32         return ret;
  33 }
  34
  35 void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
  36                       u16 speed, int data)
  37 {
  38         int speed_reg = 0;
  39         u8 value;
  40
  41         if (!mac_cb) {
  42                 pr_err("sfp_led_opt mac_dev is null!\n");
  43                 return;
  44         }
  45         if (!mac_cb->cpld_ctrl) {
  46                 dev_err(mac_cb->dev, "mac_id=%d, cpld syscon is null !\n",
  47                         mac_cb->mac_id);
  48                 return;
  49         }
  50
  51         if (speed == MAC_SPEED_10000)
  52                 speed_reg = 1;
  53
  54         value = mac_cb->cpld_led_value;
  55
  56         if (link_status) {
  57                 dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
  58                 dsaf_set_field(value, DSAF_LED_SPEED_M,
  59                                DSAF_LED_SPEED_S, speed_reg);
  60                 dsaf_set_bit(value, DSAF_LED_DATA_B, data);
  61
  62                 if (value != mac_cb->cpld_led_value) {
  63                         dsaf_write_syscon(mac_cb->cpld_ctrl,
  64                                           mac_cb->cpld_ctrl_reg, value);
  65                         mac_cb->cpld_led_value = value;
  66                 }
  67         } else {
  68                 dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
  69                                   CPLD_LED_DEFAULT_VALUE);
  70                 mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
  71         }
  72 }
  73
  74 void cpld_led_reset(struct hns_mac_cb *mac_cb)
  75 {
  76         if (!mac_cb || !mac_cb->cpld_ctrl)
  77                 return;
  78
  79         dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
  80                           CPLD_LED_DEFAULT_VALUE);
  81         mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
  82 }
  83
  84 int cpld_set_led_id(struct hns_mac_cb *mac_cb,
  85                     enum hnae_led_state status)
  86 {
  87         switch (status) {
  88         case HNAE_LED_ACTIVE:
  89                 mac_cb->cpld_led_value =
  90                         dsaf_read_syscon(mac_cb->cpld_ctrl,
  91                                          mac_cb->cpld_ctrl_reg);
  92                 dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
  93                              CPLD_LED_ON_VALUE);
  94                 dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
  95                                   mac_cb->cpld_led_value);
  96                 return 2;
  97         case HNAE_LED_INACTIVE:
  98                 dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
  99                              CPLD_LED_DEFAULT_VALUE);
 100                 dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
 101                                   mac_cb->cpld_led_value);
 102                 break;
 103         default:
 104                 break;
 105         }
 106
 107         return 0;
 108 }
 109
 110 #define RESET_REQ_OR_DREQ 1
 111
 112 void hns_dsaf_rst(struct dsaf_device *dsaf_dev, u32 val)
 113 {
 114         u32 xbar_reg_addr;
 115         u32 nt_reg_addr;
 116
 117         if (!val) {
 118                 xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
 119                 nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
 120         } else {
 121                 xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
 122                 nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
 123         }
 124
 125         dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ);
 126         dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ);
 127 }
 128
 129 void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
 130 {
 131         u32 reg_val = 0;
 132         u32 reg_addr;
 133
 134         if (port >= DSAF_XGE_NUM)
 135                 return;
 136
 137         reg_val |= RESET_REQ_OR_DREQ;
 138         reg_val |= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off;
 139
 140         if (val == 0)
 141                 reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
 142         else
 143                 reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
 144
 145         dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
 146 }
 147
 148 void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
 149                                     u32 port, u32 val)
 150 {
 151         u32 reg_val = 0;
 152         u32 reg_addr;
 153
 154         if (port >= DSAF_XGE_NUM)
 155                 return;
 156
 157         reg_val |= XGMAC_TRX_CORE_SRST_M
 158                 << dsaf_dev->mac_cb[port]->port_rst_off;
 159
 160         if (val == 0)
 161                 reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
 162         else
 163                 reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
 164
 165         dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
 166 }
 167
 168 void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
 169 {
 170         u32 reg_val_1;
 171         u32 reg_val_2;
 172         u32 port_rst_off;
 173
 174         if (port >= DSAF_GE_NUM)
 175                 return;
 176
 177         if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
 178                 reg_val_1  = 0x1 << port;
 179                 port_rst_off = dsaf_dev->mac_cb[port]->port_rst_off;
 180                 /* there is difference between V1 and V2 in register.*/
 181                 if (AE_IS_VER1(dsaf_dev->dsaf_ver))
 182                         reg_val_2  = 0x1041041 << port_rst_off;
 183                 else
 184                         reg_val_2  = 0x2082082 << port_rst_off;
 185
 186                 if (val == 0) {
 187                         dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
 188                                        reg_val_1);
 189
 190                         dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG,
 191                                        reg_val_2);
 192                 } else {
 193                         dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG,
 194                                        reg_val_2);
 195
 196                         dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
 197                                        reg_val_1);
 198                 }
 199         } else {
 200                 reg_val_1 = 0x15540 << dsaf_dev->reset_offset;
 201                 reg_val_2 = 0x100 << dsaf_dev->reset_offset;
 202
 203                 if (val == 0) {
 204                         dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
 205                                        reg_val_1);
 206
 207                         dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG,
 208                                        reg_val_2);
 209                 } else {
 210                         dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
 211                                        reg_val_1);
 212
 213                         dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG,
 214                                        reg_val_2);
 215                 }
 216         }
 217 }
 218
 219 void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
 220 {
 221         u32 reg_val = 0;
 222         u32 reg_addr;
 223
 224         reg_val |= RESET_REQ_OR_DREQ << dsaf_dev->mac_cb[port]->port_rst_off;
 225
 226         if (val == 0)
 227                 reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
 228         else
 229                 reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
 230
 231         dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
 232 }
 233
 234 void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val)
 235 {
 236         struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
 237         u32 reg_val;
 238         u32 reg_addr;
 239
 240         if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
 241                 reg_val = RESET_REQ_OR_DREQ;
 242                 if (val == 0)
 243                         reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
 244                 else
 245                         reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;
 246
 247         } else {
 248                 reg_val = 0x100 << dsaf_dev->reset_offset;
 249
 250                 if (val == 0)
 251                         reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
 252                 else
 253                         reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
 254         }
 255
 256         dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
 257 }
 258
 259 /**
 260  * hns_mac_get_sds_mode - get phy ifterface form serdes mode
 261  * @mac_cb: mac control block
 262  * retuen phy interface
 263  */
 264 phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
 265 {
 266         u32 mode;
 267         u32 reg;
 268         bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
 269         int mac_id = mac_cb->mac_id;
 270         phy_interface_t phy_if;
 271
 272         if (is_ver1) {
 273                 if (HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev))
 274                         return PHY_INTERFACE_MODE_SGMII;
 275
 276                 if (mac_id >= 0 && mac_id <= 3)
 277                         reg = HNS_MAC_HILINK4_REG;
 278                 else
 279                         reg = HNS_MAC_HILINK3_REG;
 280         } else{
 281                 if (!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev) && mac_id <= 3)
 282                         reg = HNS_MAC_HILINK4V2_REG;
 283                 else
 284                         reg = HNS_MAC_HILINK3V2_REG;
 285         }
 286
 287         mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
 288         if (dsaf_get_bit(mode, mac_cb->port_mode_off))
 289                 phy_if = PHY_INTERFACE_MODE_XGMII;
 290         else
 291                 phy_if = PHY_INTERFACE_MODE_SGMII;
 292
 293         return phy_if;
 294 }
 295
 296 int hns_mac_get_sfp_prsnt(struct hns_mac_cb *mac_cb, int *sfp_prsnt)
 297 {
 298         if (!mac_cb->cpld_ctrl)
 299                 return -ENODEV;
 300
 301         *sfp_prsnt = !dsaf_read_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg
 302                                         + MAC_SFP_PORT_OFFSET);
 303
 304         return 0;
 305 }
 306
 307 /**
 308  * hns_mac_config_sds_loopback - set loop back for serdes
 309  * @mac_cb: mac control block
 310  * retuen 0 == success
 311  */
 312 int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, u8 en)
 313 {
 314         /* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
 315          * port 4-7 hilink3 base is serdes_vaddr + 0x00200000
 316          */
 317         u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
 318                        (mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
 319         const u8 lane_id[] = {
 320                 0,      /* mac 0 -> lane 0 */
 321                 1,      /* mac 1 -> lane 1 */
 322                 2,      /* mac 2 -> lane 2 */
 323                 3,      /* mac 3 -> lane 3 */
 324                 2,      /* mac 4 -> lane 2 */
 325                 3,      /* mac 5 -> lane 3 */
 326                 0,      /* mac 6 -> lane 0 */
 327                 1       /* mac 7 -> lane 1 */
 328         };
 329 #define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
 330         u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);
 331
 332         int sfp_prsnt;
 333         int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);
 334
 335         if (!mac_cb->phy_node) {
 336                 if (ret)
 337                         pr_info("please confirm sfp is present or not\n");
 338                 else
 339                         if (!sfp_prsnt)
 340                                 pr_info("no sfp in this eth\n");
 341         }
 342
 343         if (mac_cb->serdes_ctrl) {
 344                 u32 origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);
 345
 346                 dsaf_set_field(origin, 1ull << 10, 10, !!en);
 347                 dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
 348         } else {
 349                 dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, !!en);
 350         }
 351
 352         return 0;
 353 }