2 * Copyright (c) 2014-2015 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include "hns_dsaf_mac.h"
11 #include "hns_dsaf_misc.h"
12 #include "hns_dsaf_ppe.h"
13 #include "hns_dsaf_reg.h"
15 static void dsaf_write_sub(struct dsaf_device
*dsaf_dev
, u32 reg
, u32 val
)
17 if (dsaf_dev
->sub_ctrl
)
18 dsaf_write_syscon(dsaf_dev
->sub_ctrl
, reg
, val
);
20 dsaf_write_reg(dsaf_dev
->sc_base
, reg
, val
);
23 static u32
dsaf_read_sub(struct dsaf_device
*dsaf_dev
, u32 reg
)
27 if (dsaf_dev
->sub_ctrl
)
28 ret
= dsaf_read_syscon(dsaf_dev
->sub_ctrl
, reg
);
30 ret
= dsaf_read_reg(dsaf_dev
->sc_base
, reg
);
35 void hns_cpld_set_led(struct hns_mac_cb
*mac_cb
, int link_status
,
42 pr_err("sfp_led_opt mac_dev is null!\n");
45 if (!mac_cb
->cpld_ctrl
) {
46 dev_err(mac_cb
->dev
, "mac_id=%d, cpld syscon is null !\n",
51 if (speed
== MAC_SPEED_10000
)
54 value
= mac_cb
->cpld_led_value
;
57 dsaf_set_bit(value
, DSAF_LED_LINK_B
, link_status
);
58 dsaf_set_field(value
, DSAF_LED_SPEED_M
,
59 DSAF_LED_SPEED_S
, speed_reg
);
60 dsaf_set_bit(value
, DSAF_LED_DATA_B
, data
);
62 if (value
!= mac_cb
->cpld_led_value
) {
63 dsaf_write_syscon(mac_cb
->cpld_ctrl
,
64 mac_cb
->cpld_ctrl_reg
, value
);
65 mac_cb
->cpld_led_value
= value
;
68 dsaf_write_syscon(mac_cb
->cpld_ctrl
, mac_cb
->cpld_ctrl_reg
,
69 CPLD_LED_DEFAULT_VALUE
);
70 mac_cb
->cpld_led_value
= CPLD_LED_DEFAULT_VALUE
;
74 void cpld_led_reset(struct hns_mac_cb
*mac_cb
)
76 if (!mac_cb
|| !mac_cb
->cpld_ctrl
)
79 dsaf_write_syscon(mac_cb
->cpld_ctrl
, mac_cb
->cpld_ctrl_reg
,
80 CPLD_LED_DEFAULT_VALUE
);
81 mac_cb
->cpld_led_value
= CPLD_LED_DEFAULT_VALUE
;
84 int cpld_set_led_id(struct hns_mac_cb
*mac_cb
,
85 enum hnae_led_state status
)
89 mac_cb
->cpld_led_value
=
90 dsaf_read_syscon(mac_cb
->cpld_ctrl
,
91 mac_cb
->cpld_ctrl_reg
);
92 dsaf_set_bit(mac_cb
->cpld_led_value
, DSAF_LED_ANCHOR_B
,
94 dsaf_write_syscon(mac_cb
->cpld_ctrl
, mac_cb
->cpld_ctrl_reg
,
95 mac_cb
->cpld_led_value
);
97 case HNAE_LED_INACTIVE
:
98 dsaf_set_bit(mac_cb
->cpld_led_value
, DSAF_LED_ANCHOR_B
,
99 CPLD_LED_DEFAULT_VALUE
);
100 dsaf_write_syscon(mac_cb
->cpld_ctrl
, mac_cb
->cpld_ctrl_reg
,
101 mac_cb
->cpld_led_value
);
110 #define RESET_REQ_OR_DREQ 1
112 void hns_dsaf_rst(struct dsaf_device
*dsaf_dev
, u32 val
)
118 xbar_reg_addr
= DSAF_SUB_SC_XBAR_RESET_REQ_REG
;
119 nt_reg_addr
= DSAF_SUB_SC_NT_RESET_REQ_REG
;
121 xbar_reg_addr
= DSAF_SUB_SC_XBAR_RESET_DREQ_REG
;
122 nt_reg_addr
= DSAF_SUB_SC_NT_RESET_DREQ_REG
;
125 dsaf_write_sub(dsaf_dev
, xbar_reg_addr
, RESET_REQ_OR_DREQ
);
126 dsaf_write_sub(dsaf_dev
, nt_reg_addr
, RESET_REQ_OR_DREQ
);
129 void hns_dsaf_xge_srst_by_port(struct dsaf_device
*dsaf_dev
, u32 port
, u32 val
)
134 if (port
>= DSAF_XGE_NUM
)
137 reg_val
|= RESET_REQ_OR_DREQ
;
138 reg_val
|= 0x2082082 << dsaf_dev
->mac_cb
[port
]->port_rst_off
;
141 reg_addr
= DSAF_SUB_SC_XGE_RESET_REQ_REG
;
143 reg_addr
= DSAF_SUB_SC_XGE_RESET_DREQ_REG
;
145 dsaf_write_sub(dsaf_dev
, reg_addr
, reg_val
);
148 void hns_dsaf_xge_core_srst_by_port(struct dsaf_device
*dsaf_dev
,
154 if (port
>= DSAF_XGE_NUM
)
157 reg_val
|= XGMAC_TRX_CORE_SRST_M
158 << dsaf_dev
->mac_cb
[port
]->port_rst_off
;
161 reg_addr
= DSAF_SUB_SC_XGE_RESET_REQ_REG
;
163 reg_addr
= DSAF_SUB_SC_XGE_RESET_DREQ_REG
;
165 dsaf_write_sub(dsaf_dev
, reg_addr
, reg_val
);
168 void hns_dsaf_ge_srst_by_port(struct dsaf_device
*dsaf_dev
, u32 port
, u32 val
)
174 if (port
>= DSAF_GE_NUM
)
177 if (!HNS_DSAF_IS_DEBUG(dsaf_dev
)) {
178 reg_val_1
= 0x1 << port
;
179 port_rst_off
= dsaf_dev
->mac_cb
[port
]->port_rst_off
;
180 /* there is difference between V1 and V2 in register.*/
181 if (AE_IS_VER1(dsaf_dev
->dsaf_ver
))
182 reg_val_2
= 0x1041041 << port_rst_off
;
184 reg_val_2
= 0x2082082 << port_rst_off
;
187 dsaf_write_sub(dsaf_dev
, DSAF_SUB_SC_GE_RESET_REQ1_REG
,
190 dsaf_write_sub(dsaf_dev
, DSAF_SUB_SC_GE_RESET_REQ0_REG
,
193 dsaf_write_sub(dsaf_dev
, DSAF_SUB_SC_GE_RESET_DREQ0_REG
,
196 dsaf_write_sub(dsaf_dev
, DSAF_SUB_SC_GE_RESET_DREQ1_REG
,
200 reg_val_1
= 0x15540 << dsaf_dev
->reset_offset
;
201 reg_val_2
= 0x100 << dsaf_dev
->reset_offset
;
204 dsaf_write_sub(dsaf_dev
, DSAF_SUB_SC_GE_RESET_REQ1_REG
,
207 dsaf_write_sub(dsaf_dev
, DSAF_SUB_SC_PPE_RESET_REQ_REG
,
210 dsaf_write_sub(dsaf_dev
, DSAF_SUB_SC_GE_RESET_DREQ1_REG
,
213 dsaf_write_sub(dsaf_dev
, DSAF_SUB_SC_PPE_RESET_DREQ_REG
,
219 void hns_ppe_srst_by_port(struct dsaf_device
*dsaf_dev
, u32 port
, u32 val
)
224 reg_val
|= RESET_REQ_OR_DREQ
<< dsaf_dev
->mac_cb
[port
]->port_rst_off
;
227 reg_addr
= DSAF_SUB_SC_PPE_RESET_REQ_REG
;
229 reg_addr
= DSAF_SUB_SC_PPE_RESET_DREQ_REG
;
231 dsaf_write_sub(dsaf_dev
, reg_addr
, reg_val
);
234 void hns_ppe_com_srst(struct ppe_common_cb
*ppe_common
, u32 val
)
236 struct dsaf_device
*dsaf_dev
= ppe_common
->dsaf_dev
;
240 if (!HNS_DSAF_IS_DEBUG(dsaf_dev
)) {
241 reg_val
= RESET_REQ_OR_DREQ
;
243 reg_addr
= DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG
;
245 reg_addr
= DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG
;
248 reg_val
= 0x100 << dsaf_dev
->reset_offset
;
251 reg_addr
= DSAF_SUB_SC_PPE_RESET_REQ_REG
;
253 reg_addr
= DSAF_SUB_SC_PPE_RESET_DREQ_REG
;
256 dsaf_write_sub(dsaf_dev
, reg_addr
, reg_val
);
260 * hns_mac_get_sds_mode - get phy ifterface form serdes mode
261 * @mac_cb: mac control block
262 * retuen phy interface
264 phy_interface_t
hns_mac_get_phy_if(struct hns_mac_cb
*mac_cb
)
268 bool is_ver1
= AE_IS_VER1(mac_cb
->dsaf_dev
->dsaf_ver
);
269 int mac_id
= mac_cb
->mac_id
;
270 phy_interface_t phy_if
;
273 if (HNS_DSAF_IS_DEBUG(mac_cb
->dsaf_dev
))
274 return PHY_INTERFACE_MODE_SGMII
;
276 if (mac_id
>= 0 && mac_id
<= 3)
277 reg
= HNS_MAC_HILINK4_REG
;
279 reg
= HNS_MAC_HILINK3_REG
;
281 if (!HNS_DSAF_IS_DEBUG(mac_cb
->dsaf_dev
) && mac_id
<= 3)
282 reg
= HNS_MAC_HILINK4V2_REG
;
284 reg
= HNS_MAC_HILINK3V2_REG
;
287 mode
= dsaf_read_sub(mac_cb
->dsaf_dev
, reg
);
288 if (dsaf_get_bit(mode
, mac_cb
->port_mode_off
))
289 phy_if
= PHY_INTERFACE_MODE_XGMII
;
291 phy_if
= PHY_INTERFACE_MODE_SGMII
;
296 int hns_mac_get_sfp_prsnt(struct hns_mac_cb
*mac_cb
, int *sfp_prsnt
)
298 if (!mac_cb
->cpld_ctrl
)
301 *sfp_prsnt
= !dsaf_read_syscon(mac_cb
->cpld_ctrl
, mac_cb
->cpld_ctrl_reg
302 + MAC_SFP_PORT_OFFSET
);
308 * hns_mac_config_sds_loopback - set loop back for serdes
309 * @mac_cb: mac control block
310 * retuen 0 == success
312 int hns_mac_config_sds_loopback(struct hns_mac_cb
*mac_cb
, u8 en
)
314 /* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
315 * port 4-7 hilink3 base is serdes_vaddr + 0x00200000
317 u8
*base_addr
= (u8
*)mac_cb
->serdes_vaddr
+
318 (mac_cb
->mac_id
<= 3 ? 0x00280000 : 0x00200000);
319 const u8 lane_id
[] = {
320 0, /* mac 0 -> lane 0 */
321 1, /* mac 1 -> lane 1 */
322 2, /* mac 2 -> lane 2 */
323 3, /* mac 3 -> lane 3 */
324 2, /* mac 4 -> lane 2 */
325 3, /* mac 5 -> lane 3 */
326 0, /* mac 6 -> lane 0 */
327 1 /* mac 7 -> lane 1 */
329 #define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
330 u64 reg_offset
= RX_CSR(lane_id
[mac_cb
->mac_id
], 0);
333 int ret
= hns_mac_get_sfp_prsnt(mac_cb
, &sfp_prsnt
);
335 if (!mac_cb
->phy_node
) {
337 pr_info("please confirm sfp is present or not\n");
340 pr_info("no sfp in this eth\n");
343 if (mac_cb
->serdes_ctrl
) {
344 u32 origin
= dsaf_read_syscon(mac_cb
->serdes_ctrl
, reg_offset
);
346 dsaf_set_field(origin
, 1ull << 10, 10, !!en
);
347 dsaf_write_syscon(mac_cb
->serdes_ctrl
, reg_offset
, origin
);
349 dsaf_set_reg_field(base_addr
, reg_offset
, 1ull << 10, 10, !!en
);