2 * Copyright (c) 2014-2015 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/platform_device.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
20 #include "hns_dsaf_ppe.h"
22 void hns_ppe_set_tso_enable(struct hns_ppe_cb
*ppe_cb
, u32 value
)
24 dsaf_set_dev_bit(ppe_cb
, PPEV2_CFG_TSO_EN_REG
, 0, !!value
);
27 void hns_ppe_set_rss_key(struct hns_ppe_cb
*ppe_cb
,
28 const u32 rss_key
[HNS_PPEV2_RSS_KEY_NUM
])
32 for (key_item
= 0; key_item
< HNS_PPEV2_RSS_KEY_NUM
; key_item
++)
33 dsaf_write_dev(ppe_cb
, PPEV2_RSS_KEY_REG
+ key_item
* 0x4,
37 void hns_ppe_set_indir_table(struct hns_ppe_cb
*ppe_cb
,
38 const u32 rss_tab
[HNS_PPEV2_RSS_IND_TBL_SIZE
])
43 for (i
= 0; i
< (HNS_PPEV2_RSS_IND_TBL_SIZE
/ 4); i
++) {
44 reg_value
= dsaf_read_dev(ppe_cb
,
45 PPEV2_INDRECTION_TBL_REG
+ i
* 0x4);
47 dsaf_set_field(reg_value
, PPEV2_CFG_RSS_TBL_4N0_M
,
48 PPEV2_CFG_RSS_TBL_4N0_S
,
49 rss_tab
[i
* 4 + 0] & 0x1F);
50 dsaf_set_field(reg_value
, PPEV2_CFG_RSS_TBL_4N1_M
,
51 PPEV2_CFG_RSS_TBL_4N1_S
,
52 rss_tab
[i
* 4 + 1] & 0x1F);
53 dsaf_set_field(reg_value
, PPEV2_CFG_RSS_TBL_4N2_M
,
54 PPEV2_CFG_RSS_TBL_4N2_S
,
55 rss_tab
[i
* 4 + 2] & 0x1F);
56 dsaf_set_field(reg_value
, PPEV2_CFG_RSS_TBL_4N3_M
,
57 PPEV2_CFG_RSS_TBL_4N3_S
,
58 rss_tab
[i
* 4 + 3] & 0x1F);
60 ppe_cb
, PPEV2_INDRECTION_TBL_REG
+ i
* 0x4, reg_value
);
65 hns_ppe_common_get_ioaddr(struct ppe_common_cb
*ppe_common
)
67 return ppe_common
->dsaf_dev
->ppe_base
+ PPE_COMMON_REG_OFFSET
;
71 * hns_ppe_common_get_cfg - get ppe common config
72 * @dsaf_dev: dasf device
73 * comm_index: common index
74 * retuen 0 - success , negative --fail
76 int hns_ppe_common_get_cfg(struct dsaf_device
*dsaf_dev
, int comm_index
)
78 struct ppe_common_cb
*ppe_common
;
81 if (!HNS_DSAF_IS_DEBUG(dsaf_dev
))
82 ppe_num
= HNS_PPE_SERVICE_NW_ENGINE_NUM
;
84 ppe_num
= HNS_PPE_DEBUG_NW_ENGINE_NUM
;
86 ppe_common
= devm_kzalloc(dsaf_dev
->dev
, sizeof(*ppe_common
) +
87 ppe_num
* sizeof(struct hns_ppe_cb
), GFP_KERNEL
);
91 ppe_common
->ppe_num
= ppe_num
;
92 ppe_common
->dsaf_dev
= dsaf_dev
;
93 ppe_common
->comm_index
= comm_index
;
94 if (!HNS_DSAF_IS_DEBUG(dsaf_dev
))
95 ppe_common
->ppe_mode
= PPE_COMMON_MODE_SERVICE
;
97 ppe_common
->ppe_mode
= PPE_COMMON_MODE_DEBUG
;
98 ppe_common
->dev
= dsaf_dev
->dev
;
100 ppe_common
->io_base
= hns_ppe_common_get_ioaddr(ppe_common
);
102 dsaf_dev
->ppe_common
[comm_index
] = ppe_common
;
107 void hns_ppe_common_free_cfg(struct dsaf_device
*dsaf_dev
, u32 comm_index
)
109 dsaf_dev
->ppe_common
[comm_index
] = NULL
;
112 static void __iomem
*hns_ppe_get_iobase(struct ppe_common_cb
*ppe_common
,
115 return ppe_common
->dsaf_dev
->ppe_base
+ ppe_idx
* PPE_REG_OFFSET
;
118 static void hns_ppe_get_cfg(struct ppe_common_cb
*ppe_common
)
121 struct hns_ppe_cb
*ppe_cb
;
122 u32 ppe_num
= ppe_common
->ppe_num
;
124 for (i
= 0; i
< ppe_num
; i
++) {
125 ppe_cb
= &ppe_common
->ppe_cb
[i
];
126 ppe_cb
->dev
= ppe_common
->dev
;
128 ppe_cb
->ppe_common_cb
= ppe_common
;
130 ppe_cb
->io_base
= hns_ppe_get_iobase(ppe_common
, i
);
135 static void hns_ppe_cnt_clr_ce(struct hns_ppe_cb
*ppe_cb
)
137 dsaf_set_dev_bit(ppe_cb
, PPE_TNL_0_5_CNT_CLR_CE_REG
,
138 PPE_CNT_CLR_CE_B
, 1);
141 static void hns_ppe_set_vlan_strip(struct hns_ppe_cb
*ppe_cb
, int en
)
143 dsaf_write_dev(ppe_cb
, PPEV2_VLAN_STRIP_EN_REG
, en
);
147 * hns_ppe_checksum_hw - set ppe checksum caculate
148 * @ppe_device: ppe device
151 static void hns_ppe_checksum_hw(struct hns_ppe_cb
*ppe_cb
, u32 value
)
153 dsaf_set_dev_field(ppe_cb
, PPE_CFG_PRO_CHECK_EN_REG
,
154 0xfffffff, 0, value
);
157 static void hns_ppe_set_qid_mode(struct ppe_common_cb
*ppe_common
,
158 enum ppe_qid_mode qid_mdoe
)
160 dsaf_set_dev_field(ppe_common
, PPE_COM_CFG_QID_MODE_REG
,
161 PPE_CFG_QID_MODE_CF_QID_MODE_M
,
162 PPE_CFG_QID_MODE_CF_QID_MODE_S
, qid_mdoe
);
166 * hns_ppe_set_qid - set ppe qid
167 * @ppe_common: ppe common device
170 static void hns_ppe_set_qid(struct ppe_common_cb
*ppe_common
, u32 qid
)
172 u32 qid_mod
= dsaf_read_dev(ppe_common
, PPE_COM_CFG_QID_MODE_REG
);
174 if (!dsaf_get_field(qid_mod
, PPE_CFG_QID_MODE_DEF_QID_M
,
175 PPE_CFG_QID_MODE_DEF_QID_S
)) {
176 dsaf_set_field(qid_mod
, PPE_CFG_QID_MODE_DEF_QID_M
,
177 PPE_CFG_QID_MODE_DEF_QID_S
, qid
);
178 dsaf_write_dev(ppe_common
, PPE_COM_CFG_QID_MODE_REG
, qid_mod
);
183 * hns_ppe_set_port_mode - set port mode
184 * @ppe_device: ppe device
187 static void hns_ppe_set_port_mode(struct hns_ppe_cb
*ppe_cb
,
188 enum ppe_port_mode mode
)
190 dsaf_write_dev(ppe_cb
, PPE_CFG_XGE_MODE_REG
, mode
);
194 * hns_ppe_common_init_hw - init ppe common device
195 * @ppe_common: ppe common device
197 * Return 0 on success, negative on failure
199 static int hns_ppe_common_init_hw(struct ppe_common_cb
*ppe_common
)
201 enum ppe_qid_mode qid_mode
;
202 struct dsaf_device
*dsaf_dev
= ppe_common
->dsaf_dev
;
203 enum dsaf_mode dsaf_mode
= dsaf_dev
->dsaf_mode
;
205 dsaf_dev
->misc_op
->ppe_comm_srst(dsaf_dev
, 0);
207 dsaf_dev
->misc_op
->ppe_comm_srst(dsaf_dev
, 1);
210 if (ppe_common
->ppe_mode
== PPE_COMMON_MODE_SERVICE
) {
212 case DSAF_MODE_ENABLE_FIX
:
213 case DSAF_MODE_DISABLE_FIX
:
214 qid_mode
= PPE_QID_MODE0
;
215 hns_ppe_set_qid(ppe_common
, 0);
217 case DSAF_MODE_ENABLE_0VM
:
218 case DSAF_MODE_DISABLE_2PORT_64VM
:
219 qid_mode
= PPE_QID_MODE3
;
221 case DSAF_MODE_ENABLE_8VM
:
222 case DSAF_MODE_DISABLE_2PORT_16VM
:
223 qid_mode
= PPE_QID_MODE4
;
225 case DSAF_MODE_ENABLE_16VM
:
226 case DSAF_MODE_DISABLE_6PORT_0VM
:
227 qid_mode
= PPE_QID_MODE5
;
229 case DSAF_MODE_ENABLE_32VM
:
230 case DSAF_MODE_DISABLE_6PORT_16VM
:
231 qid_mode
= PPE_QID_MODE2
;
233 case DSAF_MODE_ENABLE_128VM
:
234 case DSAF_MODE_DISABLE_6PORT_4VM
:
235 qid_mode
= PPE_QID_MODE1
;
237 case DSAF_MODE_DISABLE_2PORT_8VM
:
238 qid_mode
= PPE_QID_MODE7
;
240 case DSAF_MODE_DISABLE_6PORT_2VM
:
241 qid_mode
= PPE_QID_MODE6
;
244 dev_err(ppe_common
->dev
,
245 "get ppe queue mode failed! dsaf_mode=%d\n",
249 hns_ppe_set_qid_mode(ppe_common
, qid_mode
);
252 dsaf_set_dev_bit(ppe_common
, PPE_COM_COMMON_CNT_CLR_CE_REG
,
253 PPE_COMMON_CNT_CLR_CE_B
, 1);
258 /*clr ppe exception irq*/
259 static void hns_ppe_exc_irq_en(struct hns_ppe_cb
*ppe_cb
, int en
)
261 u32 clr_vlue
= 0xfffffffful
;
262 u32 msk_vlue
= en
? 0xfffffffful
: 0; /*1 is en, 0 is dis*/
265 /*only care bit 0,1,7*/
266 dsaf_set_bit(vld_msk
, 0, 1);
267 dsaf_set_bit(vld_msk
, 1, 1);
268 dsaf_set_bit(vld_msk
, 7, 1);
271 dsaf_write_dev(ppe_cb
, PPE_RINT_REG
, clr_vlue
);
273 /*for some reserved bits, so set 0**/
274 dsaf_write_dev(ppe_cb
, PPE_INTEN_REG
, msk_vlue
& vld_msk
);
278 * ppe_init_hw - init ppe
279 * @ppe_cb: ppe device
281 static void hns_ppe_init_hw(struct hns_ppe_cb
*ppe_cb
)
283 struct ppe_common_cb
*ppe_common_cb
= ppe_cb
->ppe_common_cb
;
284 u32 port
= ppe_cb
->index
;
285 struct dsaf_device
*dsaf_dev
= ppe_common_cb
->dsaf_dev
;
288 /* get default RSS key */
289 netdev_rss_key_fill(ppe_cb
->rss_key
, HNS_PPEV2_RSS_KEY_SIZE
);
291 dsaf_dev
->misc_op
->ppe_srst(dsaf_dev
, port
, 0);
293 dsaf_dev
->misc_op
->ppe_srst(dsaf_dev
, port
, 1);
295 /* clr and msk except irq*/
296 hns_ppe_exc_irq_en(ppe_cb
, 0);
298 if (ppe_common_cb
->ppe_mode
== PPE_COMMON_MODE_DEBUG
) {
299 hns_ppe_set_port_mode(ppe_cb
, PPE_MODE_GE
);
300 dsaf_write_dev(ppe_cb
, PPE_CFG_PAUSE_IDLE_CNT_REG
, 0);
302 hns_ppe_set_port_mode(ppe_cb
, PPE_MODE_XGE
);
305 hns_ppe_checksum_hw(ppe_cb
, 0xffffffff);
306 hns_ppe_cnt_clr_ce(ppe_cb
);
308 if (!AE_IS_VER1(dsaf_dev
->dsaf_ver
)) {
309 hns_ppe_set_vlan_strip(ppe_cb
, 0);
311 dsaf_write_dev(ppe_cb
, PPE_CFG_MAX_FRAME_LEN_REG
,
312 HNS_PPEV2_MAX_FRAME_LEN
);
314 /* set default RSS key in h/w */
315 hns_ppe_set_rss_key(ppe_cb
, ppe_cb
->rss_key
);
317 /* Set default indrection table in h/w */
318 for (i
= 0; i
< HNS_PPEV2_RSS_IND_TBL_SIZE
; i
++)
319 ppe_cb
->rss_indir_table
[i
] = i
;
320 hns_ppe_set_indir_table(ppe_cb
, ppe_cb
->rss_indir_table
);
325 * ppe_uninit_hw - uninit ppe
326 * @ppe_device: ppe device
328 static void hns_ppe_uninit_hw(struct hns_ppe_cb
*ppe_cb
)
331 struct dsaf_device
*dsaf_dev
= ppe_cb
->ppe_common_cb
->dsaf_dev
;
333 if (ppe_cb
->ppe_common_cb
) {
334 port
= ppe_cb
->index
;
335 dsaf_dev
->misc_op
->ppe_srst(dsaf_dev
, port
, 0);
339 void hns_ppe_uninit_ex(struct ppe_common_cb
*ppe_common
)
343 for (i
= 0; i
< ppe_common
->ppe_num
; i
++) {
344 if (ppe_common
->dsaf_dev
->mac_cb
[i
])
345 hns_ppe_uninit_hw(&ppe_common
->ppe_cb
[i
]);
346 memset(&ppe_common
->ppe_cb
[i
], 0, sizeof(struct hns_ppe_cb
));
350 void hns_ppe_uninit(struct dsaf_device
*dsaf_dev
)
354 for (i
= 0; i
< HNS_PPE_COM_NUM
; i
++) {
355 if (dsaf_dev
->ppe_common
[i
])
356 hns_ppe_uninit_ex(dsaf_dev
->ppe_common
[i
]);
357 hns_rcb_common_free_cfg(dsaf_dev
, i
);
358 hns_ppe_common_free_cfg(dsaf_dev
, i
);
363 * hns_ppe_reset - reinit ppe/rcb hw
364 * @dsaf_dev: dasf device
367 void hns_ppe_reset_common(struct dsaf_device
*dsaf_dev
, u8 ppe_common_index
)
371 struct ppe_common_cb
*ppe_common
;
373 ppe_common
= dsaf_dev
->ppe_common
[ppe_common_index
];
374 ret
= hns_ppe_common_init_hw(ppe_common
);
378 for (i
= 0; i
< ppe_common
->ppe_num
; i
++) {
379 /* We only need to initiate ppe when the port exists */
380 if (dsaf_dev
->mac_cb
[i
])
381 hns_ppe_init_hw(&ppe_common
->ppe_cb
[i
]);
384 ret
= hns_rcb_common_init_hw(dsaf_dev
->rcb_common
[ppe_common_index
]);
388 hns_rcb_common_init_commit_hw(dsaf_dev
->rcb_common
[ppe_common_index
]);
391 void hns_ppe_update_stats(struct hns_ppe_cb
*ppe_cb
)
393 struct hns_ppe_hw_stats
*hw_stats
= &ppe_cb
->hw_stats
;
395 hw_stats
->rx_pkts_from_sw
396 += dsaf_read_dev(ppe_cb
, PPE_HIS_RX_SW_PKT_CNT_REG
);
398 += dsaf_read_dev(ppe_cb
, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG
);
399 hw_stats
->rx_drop_no_bd
400 += dsaf_read_dev(ppe_cb
, PPE_HIS_RX_PKT_NO_BUF_CNT_REG
);
401 hw_stats
->rx_alloc_buf_fail
402 += dsaf_read_dev(ppe_cb
, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG
);
403 hw_stats
->rx_alloc_buf_wait
404 += dsaf_read_dev(ppe_cb
, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG
);
405 hw_stats
->rx_drop_no_buf
406 += dsaf_read_dev(ppe_cb
, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG
);
407 hw_stats
->rx_err_fifo_full
408 += dsaf_read_dev(ppe_cb
, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG
);
410 hw_stats
->tx_bd_form_rcb
411 += dsaf_read_dev(ppe_cb
, PPE_HIS_TX_BD_CNT_REG
);
412 hw_stats
->tx_pkts_from_rcb
413 += dsaf_read_dev(ppe_cb
, PPE_HIS_TX_PKT_CNT_REG
);
415 += dsaf_read_dev(ppe_cb
, PPE_HIS_TX_PKT_OK_CNT_REG
);
416 hw_stats
->tx_err_fifo_empty
417 += dsaf_read_dev(ppe_cb
, PPE_HIS_TX_PKT_EPT_CNT_REG
);
418 hw_stats
->tx_err_checksum
419 += dsaf_read_dev(ppe_cb
, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG
);
422 int hns_ppe_get_sset_count(int stringset
)
424 if (stringset
== ETH_SS_STATS
)
425 return ETH_PPE_STATIC_NUM
;
429 int hns_ppe_get_regs_count(void)
431 return ETH_PPE_DUMP_NUM
;
435 * ppe_get_strings - get ppe srting
436 * @ppe_device: ppe device
437 * @stringset: string set type
438 * @data: output string
440 void hns_ppe_get_strings(struct hns_ppe_cb
*ppe_cb
, int stringset
, u8
*data
)
442 char *buff
= (char *)data
;
443 int index
= ppe_cb
->index
;
445 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_rx_sw_pkt", index
);
446 buff
= buff
+ ETH_GSTRING_LEN
;
447 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_rx_pkt_ok", index
);
448 buff
= buff
+ ETH_GSTRING_LEN
;
449 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_rx_drop_pkt_no_bd", index
);
450 buff
= buff
+ ETH_GSTRING_LEN
;
451 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_rx_alloc_buf_fail", index
);
452 buff
= buff
+ ETH_GSTRING_LEN
;
453 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_rx_alloc_buf_wait", index
);
454 buff
= buff
+ ETH_GSTRING_LEN
;
455 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_rx_pkt_drop_no_buf", index
);
456 buff
= buff
+ ETH_GSTRING_LEN
;
457 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_rx_pkt_err_fifo_full", index
);
458 buff
= buff
+ ETH_GSTRING_LEN
;
460 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_tx_bd", index
);
461 buff
= buff
+ ETH_GSTRING_LEN
;
462 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_tx_pkt", index
);
463 buff
= buff
+ ETH_GSTRING_LEN
;
464 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_tx_pkt_ok", index
);
465 buff
= buff
+ ETH_GSTRING_LEN
;
466 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_tx_pkt_err_fifo_empty", index
);
467 buff
= buff
+ ETH_GSTRING_LEN
;
468 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_tx_pkt_err_csum_fail", index
);
471 void hns_ppe_get_stats(struct hns_ppe_cb
*ppe_cb
, u64
*data
)
473 u64
*regs_buff
= data
;
474 struct hns_ppe_hw_stats
*hw_stats
= &ppe_cb
->hw_stats
;
476 regs_buff
[0] = hw_stats
->rx_pkts_from_sw
;
477 regs_buff
[1] = hw_stats
->rx_pkts
;
478 regs_buff
[2] = hw_stats
->rx_drop_no_bd
;
479 regs_buff
[3] = hw_stats
->rx_alloc_buf_fail
;
480 regs_buff
[4] = hw_stats
->rx_alloc_buf_wait
;
481 regs_buff
[5] = hw_stats
->rx_drop_no_buf
;
482 regs_buff
[6] = hw_stats
->rx_err_fifo_full
;
484 regs_buff
[7] = hw_stats
->tx_bd_form_rcb
;
485 regs_buff
[8] = hw_stats
->tx_pkts_from_rcb
;
486 regs_buff
[9] = hw_stats
->tx_pkts
;
487 regs_buff
[10] = hw_stats
->tx_err_fifo_empty
;
488 regs_buff
[11] = hw_stats
->tx_err_checksum
;
492 * hns_ppe_init - init ppe device
493 * @dsaf_dev: dasf device
494 * retuen 0 - success , negative --fail
496 int hns_ppe_init(struct dsaf_device
*dsaf_dev
)
501 for (i
= 0; i
< HNS_PPE_COM_NUM
; i
++) {
502 ret
= hns_ppe_common_get_cfg(dsaf_dev
, i
);
504 goto get_ppe_cfg_fail
;
506 ret
= hns_rcb_common_get_cfg(dsaf_dev
, i
);
508 goto get_rcb_cfg_fail
;
510 hns_ppe_get_cfg(dsaf_dev
->ppe_common
[i
]);
512 hns_rcb_get_cfg(dsaf_dev
->rcb_common
[i
]);
515 for (i
= 0; i
< HNS_PPE_COM_NUM
; i
++)
516 hns_ppe_reset_common(dsaf_dev
, i
);
521 hns_ppe_common_free_cfg(dsaf_dev
, i
);
523 for (k
= i
- 1; k
>= 0; k
--) {
524 hns_rcb_common_free_cfg(dsaf_dev
, k
);
525 hns_ppe_common_free_cfg(dsaf_dev
, k
);
530 void hns_ppe_get_regs(struct hns_ppe_cb
*ppe_cb
, void *data
)
532 struct ppe_common_cb
*ppe_common
= ppe_cb
->ppe_common_cb
;
537 /* ppe common registers */
538 regs
[0] = dsaf_read_dev(ppe_common
, PPE_COM_CFG_QID_MODE_REG
);
539 regs
[1] = dsaf_read_dev(ppe_common
, PPE_COM_INTEN_REG
);
540 regs
[2] = dsaf_read_dev(ppe_common
, PPE_COM_RINT_REG
);
541 regs
[3] = dsaf_read_dev(ppe_common
, PPE_COM_INTSTS_REG
);
542 regs
[4] = dsaf_read_dev(ppe_common
, PPE_COM_COMMON_CNT_CLR_CE_REG
);
544 for (i
= 0; i
< DSAF_TOTAL_QUEUE_NUM
; i
++) {
545 offset
= PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG
+ 0x4 * i
;
546 regs
[5 + i
] = dsaf_read_dev(ppe_common
, offset
);
547 offset
= PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG
+ 0x4 * i
;
548 regs
[5 + i
+ DSAF_TOTAL_QUEUE_NUM
]
549 = dsaf_read_dev(ppe_common
, offset
);
550 offset
= PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG
+ 0x4 * i
;
551 regs
[5 + i
+ DSAF_TOTAL_QUEUE_NUM
* 2]
552 = dsaf_read_dev(ppe_common
, offset
);
553 offset
= PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG
+ 0x4 * i
;
554 regs
[5 + i
+ DSAF_TOTAL_QUEUE_NUM
* 3]
555 = dsaf_read_dev(ppe_common
, offset
);
558 /* mark end of ppe regs */
559 for (i
= 521; i
< 524; i
++)
560 regs
[i
] = 0xeeeeeeee;
562 /* ppe channel registers */
563 regs
[525] = dsaf_read_dev(ppe_cb
, PPE_CFG_TX_FIFO_THRSLD_REG
);
564 regs
[526] = dsaf_read_dev(ppe_cb
, PPE_CFG_RX_FIFO_THRSLD_REG
);
565 regs
[527] = dsaf_read_dev(ppe_cb
, PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG
);
566 regs
[528] = dsaf_read_dev(ppe_cb
, PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG
);
567 regs
[529] = dsaf_read_dev(ppe_cb
, PPE_CFG_PAUSE_IDLE_CNT_REG
);
568 regs
[530] = dsaf_read_dev(ppe_cb
, PPE_CFG_BUS_CTRL_REG
);
569 regs
[531] = dsaf_read_dev(ppe_cb
, PPE_CFG_TNL_TO_BE_RST_REG
);
570 regs
[532] = dsaf_read_dev(ppe_cb
, PPE_CURR_TNL_CAN_RST_REG
);
572 regs
[533] = dsaf_read_dev(ppe_cb
, PPE_CFG_XGE_MODE_REG
);
573 regs
[534] = dsaf_read_dev(ppe_cb
, PPE_CFG_MAX_FRAME_LEN_REG
);
574 regs
[535] = dsaf_read_dev(ppe_cb
, PPE_CFG_RX_PKT_MODE_REG
);
575 regs
[536] = dsaf_read_dev(ppe_cb
, PPE_CFG_RX_VLAN_TAG_REG
);
576 regs
[537] = dsaf_read_dev(ppe_cb
, PPE_CFG_TAG_GEN_REG
);
577 regs
[538] = dsaf_read_dev(ppe_cb
, PPE_CFG_PARSE_TAG_REG
);
578 regs
[539] = dsaf_read_dev(ppe_cb
, PPE_CFG_PRO_CHECK_EN_REG
);
580 regs
[540] = dsaf_read_dev(ppe_cb
, PPE_INTEN_REG
);
581 regs
[541] = dsaf_read_dev(ppe_cb
, PPE_RINT_REG
);
582 regs
[542] = dsaf_read_dev(ppe_cb
, PPE_INTSTS_REG
);
583 regs
[543] = dsaf_read_dev(ppe_cb
, PPE_CFG_RX_PKT_INT_REG
);
585 regs
[544] = dsaf_read_dev(ppe_cb
, PPE_CFG_HEAT_DECT_TIME0_REG
);
586 regs
[545] = dsaf_read_dev(ppe_cb
, PPE_CFG_HEAT_DECT_TIME1_REG
);
589 regs
[546] = dsaf_read_dev(ppe_cb
, PPE_HIS_RX_SW_PKT_CNT_REG
);
590 regs
[547] = dsaf_read_dev(ppe_cb
, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG
);
591 regs
[548] = dsaf_read_dev(ppe_cb
, PPE_HIS_RX_PKT_NO_BUF_CNT_REG
);
592 regs
[549] = dsaf_read_dev(ppe_cb
, PPE_HIS_TX_BD_CNT_REG
);
593 regs
[550] = dsaf_read_dev(ppe_cb
, PPE_HIS_TX_PKT_CNT_REG
);
594 regs
[551] = dsaf_read_dev(ppe_cb
, PPE_HIS_TX_PKT_OK_CNT_REG
);
595 regs
[552] = dsaf_read_dev(ppe_cb
, PPE_HIS_TX_PKT_EPT_CNT_REG
);
596 regs
[553] = dsaf_read_dev(ppe_cb
, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG
);
597 regs
[554] = dsaf_read_dev(ppe_cb
, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG
);
598 regs
[555] = dsaf_read_dev(ppe_cb
, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG
);
599 regs
[556] = dsaf_read_dev(ppe_cb
, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG
);
600 regs
[557] = dsaf_read_dev(ppe_cb
, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG
);
602 regs
[558] = dsaf_read_dev(ppe_cb
, PPE_TNL_0_5_CNT_CLR_CE_REG
);
603 regs
[559] = dsaf_read_dev(ppe_cb
, PPE_CFG_AXI_DBG_REG
);
604 regs
[560] = dsaf_read_dev(ppe_cb
, PPE_HIS_PRO_ERR_REG
);
605 regs
[561] = dsaf_read_dev(ppe_cb
, PPE_HIS_TNL_FIFO_ERR_REG
);
606 regs
[562] = dsaf_read_dev(ppe_cb
, PPE_CURR_CFF_DATA_NUM_REG
);
607 regs
[563] = dsaf_read_dev(ppe_cb
, PPE_CURR_RX_ST_REG
);
608 regs
[564] = dsaf_read_dev(ppe_cb
, PPE_CURR_TX_ST_REG
);
609 regs
[565] = dsaf_read_dev(ppe_cb
, PPE_CURR_RX_FIFO0_REG
);
610 regs
[566] = dsaf_read_dev(ppe_cb
, PPE_CURR_RX_FIFO1_REG
);
611 regs
[567] = dsaf_read_dev(ppe_cb
, PPE_CURR_TX_FIFO0_REG
);
612 regs
[568] = dsaf_read_dev(ppe_cb
, PPE_CURR_TX_FIFO1_REG
);
613 regs
[569] = dsaf_read_dev(ppe_cb
, PPE_ECO0_REG
);
614 regs
[570] = dsaf_read_dev(ppe_cb
, PPE_ECO1_REG
);
615 regs
[571] = dsaf_read_dev(ppe_cb
, PPE_ECO2_REG
);
617 /* mark end of ppe regs */
618 for (i
= 572; i
< 576; i
++)
619 regs
[i
] = 0xeeeeeeee;