2 * Copyright (c) 2014-2015 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/platform_device.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
20 #include "hns_dsaf_ppe.h"
22 void hns_ppe_set_tso_enable(struct hns_ppe_cb
*ppe_cb
, u32 value
)
24 dsaf_set_dev_bit(ppe_cb
, PPEV2_CFG_TSO_EN_REG
, 0, !!value
);
27 void hns_ppe_set_rss_key(struct hns_ppe_cb
*ppe_cb
,
28 const u32 rss_key
[HNS_PPEV2_RSS_KEY_NUM
])
32 for (key_item
= 0; key_item
< HNS_PPEV2_RSS_KEY_NUM
; key_item
++)
33 dsaf_write_dev(ppe_cb
, PPEV2_RSS_KEY_REG
+ key_item
* 0x4,
37 void hns_ppe_set_indir_table(struct hns_ppe_cb
*ppe_cb
,
38 const u32 rss_tab
[HNS_PPEV2_RSS_IND_TBL_SIZE
])
43 for (i
= 0; i
< (HNS_PPEV2_RSS_IND_TBL_SIZE
/ 4); i
++) {
44 reg_value
= dsaf_read_dev(ppe_cb
,
45 PPEV2_INDRECTION_TBL_REG
+ i
* 0x4);
47 dsaf_set_field(reg_value
, PPEV2_CFG_RSS_TBL_4N0_M
,
48 PPEV2_CFG_RSS_TBL_4N0_S
,
49 rss_tab
[i
* 4 + 0] & 0x1F);
50 dsaf_set_field(reg_value
, PPEV2_CFG_RSS_TBL_4N1_M
,
51 PPEV2_CFG_RSS_TBL_4N1_S
,
52 rss_tab
[i
* 4 + 1] & 0x1F);
53 dsaf_set_field(reg_value
, PPEV2_CFG_RSS_TBL_4N2_M
,
54 PPEV2_CFG_RSS_TBL_4N2_S
,
55 rss_tab
[i
* 4 + 2] & 0x1F);
56 dsaf_set_field(reg_value
, PPEV2_CFG_RSS_TBL_4N3_M
,
57 PPEV2_CFG_RSS_TBL_4N3_S
,
58 rss_tab
[i
* 4 + 3] & 0x1F);
60 ppe_cb
, PPEV2_INDRECTION_TBL_REG
+ i
* 0x4, reg_value
);
64 static void __iomem
*hns_ppe_common_get_ioaddr(
65 struct ppe_common_cb
*ppe_common
)
67 void __iomem
*base_addr
;
69 int idx
= ppe_common
->comm_index
;
71 if (idx
== HNS_DSAF_COMM_SERVICE_NW_IDX
)
72 base_addr
= ppe_common
->dsaf_dev
->ppe_base
73 + PPE_COMMON_REG_OFFSET
;
75 base_addr
= ppe_common
->dsaf_dev
->sds_base
76 + (idx
- 1) * HNS_DSAF_DEBUG_NW_REG_OFFSET
77 + PPE_COMMON_REG_OFFSET
;
83 * hns_ppe_common_get_cfg - get ppe common config
84 * @dsaf_dev: dasf device
85 * comm_index: common index
86 * retuen 0 - success , negative --fail
88 int hns_ppe_common_get_cfg(struct dsaf_device
*dsaf_dev
, int comm_index
)
90 struct ppe_common_cb
*ppe_common
;
93 if (comm_index
== HNS_DSAF_COMM_SERVICE_NW_IDX
)
94 ppe_num
= HNS_PPE_SERVICE_NW_ENGINE_NUM
;
96 ppe_num
= HNS_PPE_DEBUG_NW_ENGINE_NUM
;
98 ppe_common
= devm_kzalloc(dsaf_dev
->dev
, sizeof(*ppe_common
) +
99 ppe_num
* sizeof(struct hns_ppe_cb
), GFP_KERNEL
);
103 ppe_common
->ppe_num
= ppe_num
;
104 ppe_common
->dsaf_dev
= dsaf_dev
;
105 ppe_common
->comm_index
= comm_index
;
106 if (comm_index
== HNS_DSAF_COMM_SERVICE_NW_IDX
)
107 ppe_common
->ppe_mode
= PPE_COMMON_MODE_SERVICE
;
109 ppe_common
->ppe_mode
= PPE_COMMON_MODE_DEBUG
;
110 ppe_common
->dev
= dsaf_dev
->dev
;
112 ppe_common
->io_base
= hns_ppe_common_get_ioaddr(ppe_common
);
114 dsaf_dev
->ppe_common
[comm_index
] = ppe_common
;
119 void hns_ppe_common_free_cfg(struct dsaf_device
*dsaf_dev
, u32 comm_index
)
121 dsaf_dev
->ppe_common
[comm_index
] = NULL
;
124 static void __iomem
*hns_ppe_get_iobase(struct ppe_common_cb
*ppe_common
,
127 void __iomem
*base_addr
;
128 int common_idx
= ppe_common
->comm_index
;
130 if (ppe_common
->ppe_mode
== PPE_COMMON_MODE_SERVICE
) {
131 base_addr
= ppe_common
->dsaf_dev
->ppe_base
+
132 ppe_idx
* PPE_REG_OFFSET
;
135 base_addr
= ppe_common
->dsaf_dev
->sds_base
+
136 (common_idx
- 1) * HNS_DSAF_DEBUG_NW_REG_OFFSET
;
142 static int hns_ppe_get_port(struct ppe_common_cb
*ppe_common
, int idx
)
146 if (ppe_common
->ppe_mode
== PPE_COMMON_MODE_SERVICE
)
149 port
= HNS_PPE_SERVICE_NW_ENGINE_NUM
150 + ppe_common
->comm_index
- 1;
155 static void hns_ppe_get_cfg(struct ppe_common_cb
*ppe_common
)
158 struct hns_ppe_cb
*ppe_cb
;
159 u32 ppe_num
= ppe_common
->ppe_num
;
161 for (i
= 0; i
< ppe_num
; i
++) {
162 ppe_cb
= &ppe_common
->ppe_cb
[i
];
163 ppe_cb
->dev
= ppe_common
->dev
;
165 ppe_cb
->ppe_common_cb
= ppe_common
;
167 ppe_cb
->port
= hns_ppe_get_port(ppe_common
, i
);
168 ppe_cb
->io_base
= hns_ppe_get_iobase(ppe_common
, i
);
173 static void hns_ppe_cnt_clr_ce(struct hns_ppe_cb
*ppe_cb
)
175 dsaf_set_dev_bit(ppe_cb
, PPE_TNL_0_5_CNT_CLR_CE_REG
,
176 PPE_CNT_CLR_CE_B
, 1);
179 static void hns_ppe_set_vlan_strip(struct hns_ppe_cb
*ppe_cb
, int en
)
181 dsaf_write_dev(ppe_cb
, PPEV2_VLAN_STRIP_EN_REG
, en
);
185 * hns_ppe_checksum_hw - set ppe checksum caculate
186 * @ppe_device: ppe device
189 static void hns_ppe_checksum_hw(struct hns_ppe_cb
*ppe_cb
, u32 value
)
191 dsaf_set_dev_field(ppe_cb
, PPE_CFG_PRO_CHECK_EN_REG
,
192 0xfffffff, 0, value
);
195 static void hns_ppe_set_qid_mode(struct ppe_common_cb
*ppe_common
,
196 enum ppe_qid_mode qid_mdoe
)
198 dsaf_set_dev_field(ppe_common
, PPE_COM_CFG_QID_MODE_REG
,
199 PPE_CFG_QID_MODE_CF_QID_MODE_M
,
200 PPE_CFG_QID_MODE_CF_QID_MODE_S
, qid_mdoe
);
204 * hns_ppe_set_qid - set ppe qid
205 * @ppe_common: ppe common device
208 static void hns_ppe_set_qid(struct ppe_common_cb
*ppe_common
, u32 qid
)
210 u32 qid_mod
= dsaf_read_dev(ppe_common
, PPE_COM_CFG_QID_MODE_REG
);
212 if (!dsaf_get_field(qid_mod
, PPE_CFG_QID_MODE_DEF_QID_M
,
213 PPE_CFG_QID_MODE_DEF_QID_S
)) {
214 dsaf_set_field(qid_mod
, PPE_CFG_QID_MODE_DEF_QID_M
,
215 PPE_CFG_QID_MODE_DEF_QID_S
, qid
);
216 dsaf_write_dev(ppe_common
, PPE_COM_CFG_QID_MODE_REG
, qid_mod
);
221 * hns_ppe_set_port_mode - set port mode
222 * @ppe_device: ppe device
225 static void hns_ppe_set_port_mode(struct hns_ppe_cb
*ppe_cb
,
226 enum ppe_port_mode mode
)
228 dsaf_write_dev(ppe_cb
, PPE_CFG_XGE_MODE_REG
, mode
);
232 * hns_ppe_common_init_hw - init ppe common device
233 * @ppe_common: ppe common device
235 * Return 0 on success, negative on failure
237 static int hns_ppe_common_init_hw(struct ppe_common_cb
*ppe_common
)
239 enum ppe_qid_mode qid_mode
;
240 enum dsaf_mode dsaf_mode
= ppe_common
->dsaf_dev
->dsaf_mode
;
242 hns_ppe_com_srst(ppe_common
, 0);
244 hns_ppe_com_srst(ppe_common
, 1);
247 if (ppe_common
->ppe_mode
== PPE_COMMON_MODE_SERVICE
) {
249 case DSAF_MODE_ENABLE_FIX
:
250 case DSAF_MODE_DISABLE_FIX
:
251 qid_mode
= PPE_QID_MODE0
;
252 hns_ppe_set_qid(ppe_common
, 0);
254 case DSAF_MODE_ENABLE_0VM
:
255 case DSAF_MODE_DISABLE_2PORT_64VM
:
256 qid_mode
= PPE_QID_MODE3
;
258 case DSAF_MODE_ENABLE_8VM
:
259 case DSAF_MODE_DISABLE_2PORT_16VM
:
260 qid_mode
= PPE_QID_MODE4
;
262 case DSAF_MODE_ENABLE_16VM
:
263 case DSAF_MODE_DISABLE_6PORT_0VM
:
264 qid_mode
= PPE_QID_MODE5
;
266 case DSAF_MODE_ENABLE_32VM
:
267 case DSAF_MODE_DISABLE_6PORT_16VM
:
268 qid_mode
= PPE_QID_MODE2
;
270 case DSAF_MODE_ENABLE_128VM
:
271 case DSAF_MODE_DISABLE_6PORT_4VM
:
272 qid_mode
= PPE_QID_MODE1
;
274 case DSAF_MODE_DISABLE_2PORT_8VM
:
275 qid_mode
= PPE_QID_MODE7
;
277 case DSAF_MODE_DISABLE_6PORT_2VM
:
278 qid_mode
= PPE_QID_MODE6
;
281 dev_err(ppe_common
->dev
,
282 "get ppe queue mode failed! dsaf_mode=%d\n",
286 hns_ppe_set_qid_mode(ppe_common
, qid_mode
);
289 dsaf_set_dev_bit(ppe_common
, PPE_COM_COMMON_CNT_CLR_CE_REG
,
290 PPE_COMMON_CNT_CLR_CE_B
, 1);
295 /*clr ppe exception irq*/
296 static void hns_ppe_exc_irq_en(struct hns_ppe_cb
*ppe_cb
, int en
)
298 u32 clr_vlue
= 0xfffffffful
;
299 u32 msk_vlue
= en
? 0xfffffffful
: 0; /*1 is en, 0 is dis*/
302 /*only care bit 0,1,7*/
303 dsaf_set_bit(vld_msk
, 0, 1);
304 dsaf_set_bit(vld_msk
, 1, 1);
305 dsaf_set_bit(vld_msk
, 7, 1);
308 dsaf_write_dev(ppe_cb
, PPE_RINT_REG
, clr_vlue
);
310 /*for some reserved bits, so set 0**/
311 dsaf_write_dev(ppe_cb
, PPE_INTEN_REG
, msk_vlue
& vld_msk
);
315 * ppe_init_hw - init ppe
316 * @ppe_cb: ppe device
318 static void hns_ppe_init_hw(struct hns_ppe_cb
*ppe_cb
)
320 struct ppe_common_cb
*ppe_common_cb
= ppe_cb
->ppe_common_cb
;
321 u32 port
= ppe_cb
->port
;
322 struct dsaf_device
*dsaf_dev
= ppe_common_cb
->dsaf_dev
;
325 /* get default RSS key */
326 netdev_rss_key_fill(ppe_cb
->rss_key
, HNS_PPEV2_RSS_KEY_SIZE
);
328 hns_ppe_srst_by_port(dsaf_dev
, port
, 0);
330 hns_ppe_srst_by_port(dsaf_dev
, port
, 1);
332 /* clr and msk except irq*/
333 hns_ppe_exc_irq_en(ppe_cb
, 0);
335 if (ppe_common_cb
->ppe_mode
== PPE_COMMON_MODE_DEBUG
)
336 hns_ppe_set_port_mode(ppe_cb
, PPE_MODE_GE
);
338 hns_ppe_set_port_mode(ppe_cb
, PPE_MODE_XGE
);
340 hns_ppe_checksum_hw(ppe_cb
, 0xffffffff);
341 hns_ppe_cnt_clr_ce(ppe_cb
);
343 if (!AE_IS_VER1(dsaf_dev
->dsaf_ver
)) {
344 hns_ppe_set_vlan_strip(ppe_cb
, 0);
346 /* set default RSS key in h/w */
347 hns_ppe_set_rss_key(ppe_cb
, ppe_cb
->rss_key
);
349 /* Set default indrection table in h/w */
350 for (i
= 0; i
< HNS_PPEV2_RSS_IND_TBL_SIZE
; i
++)
351 ppe_cb
->rss_indir_table
[i
] = i
;
352 hns_ppe_set_indir_table(ppe_cb
, ppe_cb
->rss_indir_table
);
357 * ppe_uninit_hw - uninit ppe
358 * @ppe_device: ppe device
360 static void hns_ppe_uninit_hw(struct hns_ppe_cb
*ppe_cb
)
364 if (ppe_cb
->ppe_common_cb
) {
365 port
= ppe_cb
->index
;
366 hns_ppe_srst_by_port(ppe_cb
->ppe_common_cb
->dsaf_dev
, port
, 0);
370 void hns_ppe_uninit_ex(struct ppe_common_cb
*ppe_common
)
374 for (i
= 0; i
< ppe_common
->ppe_num
; i
++) {
375 hns_ppe_uninit_hw(&ppe_common
->ppe_cb
[i
]);
376 memset(&ppe_common
->ppe_cb
[i
], 0, sizeof(struct hns_ppe_cb
));
380 void hns_ppe_uninit(struct dsaf_device
*dsaf_dev
)
384 for (i
= 0; i
< HNS_PPE_COM_NUM
; i
++) {
385 if (dsaf_dev
->ppe_common
[i
])
386 hns_ppe_uninit_ex(dsaf_dev
->ppe_common
[i
]);
387 hns_rcb_common_free_cfg(dsaf_dev
, i
);
388 hns_ppe_common_free_cfg(dsaf_dev
, i
);
393 * hns_ppe_reset - reinit ppe/rcb hw
394 * @dsaf_dev: dasf device
397 void hns_ppe_reset_common(struct dsaf_device
*dsaf_dev
, u8 ppe_common_index
)
401 struct ppe_common_cb
*ppe_common
;
403 ppe_common
= dsaf_dev
->ppe_common
[ppe_common_index
];
404 ret
= hns_ppe_common_init_hw(ppe_common
);
408 for (i
= 0; i
< ppe_common
->ppe_num
; i
++)
409 hns_ppe_init_hw(&ppe_common
->ppe_cb
[i
]);
411 ret
= hns_rcb_common_init_hw(dsaf_dev
->rcb_common
[ppe_common_index
]);
415 hns_rcb_common_init_commit_hw(dsaf_dev
->rcb_common
[ppe_common_index
]);
418 void hns_ppe_update_stats(struct hns_ppe_cb
*ppe_cb
)
420 struct hns_ppe_hw_stats
*hw_stats
= &ppe_cb
->hw_stats
;
422 hw_stats
->rx_pkts_from_sw
423 += dsaf_read_dev(ppe_cb
, PPE_HIS_RX_SW_PKT_CNT_REG
);
425 += dsaf_read_dev(ppe_cb
, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG
);
426 hw_stats
->rx_drop_no_bd
427 += dsaf_read_dev(ppe_cb
, PPE_HIS_RX_PKT_NO_BUF_CNT_REG
);
428 hw_stats
->rx_alloc_buf_fail
429 += dsaf_read_dev(ppe_cb
, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG
);
430 hw_stats
->rx_alloc_buf_wait
431 += dsaf_read_dev(ppe_cb
, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG
);
432 hw_stats
->rx_drop_no_buf
433 += dsaf_read_dev(ppe_cb
, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG
);
434 hw_stats
->rx_err_fifo_full
435 += dsaf_read_dev(ppe_cb
, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG
);
437 hw_stats
->tx_bd_form_rcb
438 += dsaf_read_dev(ppe_cb
, PPE_HIS_TX_BD_CNT_REG
);
439 hw_stats
->tx_pkts_from_rcb
440 += dsaf_read_dev(ppe_cb
, PPE_HIS_TX_PKT_CNT_REG
);
442 += dsaf_read_dev(ppe_cb
, PPE_HIS_TX_PKT_OK_CNT_REG
);
443 hw_stats
->tx_err_fifo_empty
444 += dsaf_read_dev(ppe_cb
, PPE_HIS_TX_PKT_EPT_CNT_REG
);
445 hw_stats
->tx_err_checksum
446 += dsaf_read_dev(ppe_cb
, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG
);
449 int hns_ppe_get_sset_count(int stringset
)
451 if (stringset
== ETH_SS_STATS
)
452 return ETH_PPE_STATIC_NUM
;
456 int hns_ppe_get_regs_count(void)
458 return ETH_PPE_DUMP_NUM
;
462 * ppe_get_strings - get ppe srting
463 * @ppe_device: ppe device
464 * @stringset: string set type
465 * @data: output string
467 void hns_ppe_get_strings(struct hns_ppe_cb
*ppe_cb
, int stringset
, u8
*data
)
469 char *buff
= (char *)data
;
470 int index
= ppe_cb
->index
;
472 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_rx_sw_pkt", index
);
473 buff
= buff
+ ETH_GSTRING_LEN
;
474 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_rx_pkt_ok", index
);
475 buff
= buff
+ ETH_GSTRING_LEN
;
476 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_rx_drop_pkt_no_bd", index
);
477 buff
= buff
+ ETH_GSTRING_LEN
;
478 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_rx_alloc_buf_fail", index
);
479 buff
= buff
+ ETH_GSTRING_LEN
;
480 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_rx_alloc_buf_wait", index
);
481 buff
= buff
+ ETH_GSTRING_LEN
;
482 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_rx_pkt_drop_no_buf", index
);
483 buff
= buff
+ ETH_GSTRING_LEN
;
484 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_rx_pkt_err_fifo_full", index
);
485 buff
= buff
+ ETH_GSTRING_LEN
;
487 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_tx_bd", index
);
488 buff
= buff
+ ETH_GSTRING_LEN
;
489 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_tx_pkt", index
);
490 buff
= buff
+ ETH_GSTRING_LEN
;
491 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_tx_pkt_ok", index
);
492 buff
= buff
+ ETH_GSTRING_LEN
;
493 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_tx_pkt_err_fifo_empty", index
);
494 buff
= buff
+ ETH_GSTRING_LEN
;
495 snprintf(buff
, ETH_GSTRING_LEN
, "ppe%d_tx_pkt_err_csum_fail", index
);
498 void hns_ppe_get_stats(struct hns_ppe_cb
*ppe_cb
, u64
*data
)
500 u64
*regs_buff
= data
;
501 struct hns_ppe_hw_stats
*hw_stats
= &ppe_cb
->hw_stats
;
503 regs_buff
[0] = hw_stats
->rx_pkts_from_sw
;
504 regs_buff
[1] = hw_stats
->rx_pkts
;
505 regs_buff
[2] = hw_stats
->rx_drop_no_bd
;
506 regs_buff
[3] = hw_stats
->rx_alloc_buf_fail
;
507 regs_buff
[4] = hw_stats
->rx_alloc_buf_wait
;
508 regs_buff
[5] = hw_stats
->rx_drop_no_buf
;
509 regs_buff
[6] = hw_stats
->rx_err_fifo_full
;
511 regs_buff
[7] = hw_stats
->tx_bd_form_rcb
;
512 regs_buff
[8] = hw_stats
->tx_pkts_from_rcb
;
513 regs_buff
[9] = hw_stats
->tx_pkts
;
514 regs_buff
[10] = hw_stats
->tx_err_fifo_empty
;
515 regs_buff
[11] = hw_stats
->tx_err_checksum
;
519 * hns_ppe_init - init ppe device
520 * @dsaf_dev: dasf device
521 * retuen 0 - success , negative --fail
523 int hns_ppe_init(struct dsaf_device
*dsaf_dev
)
528 for (i
= 0; i
< HNS_PPE_COM_NUM
; i
++) {
529 ret
= hns_ppe_common_get_cfg(dsaf_dev
, i
);
531 goto get_ppe_cfg_fail
;
533 ret
= hns_rcb_common_get_cfg(dsaf_dev
, i
);
535 goto get_rcb_cfg_fail
;
537 hns_ppe_get_cfg(dsaf_dev
->ppe_common
[i
]);
539 hns_rcb_get_cfg(dsaf_dev
->rcb_common
[i
]);
542 for (i
= 0; i
< HNS_PPE_COM_NUM
; i
++)
543 hns_ppe_reset_common(dsaf_dev
, i
);
548 hns_ppe_common_free_cfg(dsaf_dev
, i
);
550 for (k
= i
- 1; k
>= 0; k
--) {
551 hns_rcb_common_free_cfg(dsaf_dev
, k
);
552 hns_ppe_common_free_cfg(dsaf_dev
, k
);
557 void hns_ppe_get_regs(struct hns_ppe_cb
*ppe_cb
, void *data
)
559 struct ppe_common_cb
*ppe_common
= ppe_cb
->ppe_common_cb
;
564 /* ppe common registers */
565 regs
[0] = dsaf_read_dev(ppe_common
, PPE_COM_CFG_QID_MODE_REG
);
566 regs
[1] = dsaf_read_dev(ppe_common
, PPE_COM_INTEN_REG
);
567 regs
[2] = dsaf_read_dev(ppe_common
, PPE_COM_RINT_REG
);
568 regs
[3] = dsaf_read_dev(ppe_common
, PPE_COM_INTSTS_REG
);
569 regs
[4] = dsaf_read_dev(ppe_common
, PPE_COM_COMMON_CNT_CLR_CE_REG
);
571 for (i
= 0; i
< DSAF_TOTAL_QUEUE_NUM
; i
++) {
572 offset
= PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG
+ 0x4 * i
;
573 regs
[5 + i
] = dsaf_read_dev(ppe_common
, offset
);
574 offset
= PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG
+ 0x4 * i
;
575 regs
[5 + i
+ DSAF_TOTAL_QUEUE_NUM
]
576 = dsaf_read_dev(ppe_common
, offset
);
577 offset
= PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG
+ 0x4 * i
;
578 regs
[5 + i
+ DSAF_TOTAL_QUEUE_NUM
* 2]
579 = dsaf_read_dev(ppe_common
, offset
);
580 offset
= PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG
+ 0x4 * i
;
581 regs
[5 + i
+ DSAF_TOTAL_QUEUE_NUM
* 3]
582 = dsaf_read_dev(ppe_common
, offset
);
585 /* mark end of ppe regs */
586 for (i
= 521; i
< 524; i
++)
587 regs
[i
] = 0xeeeeeeee;
589 /* ppe channel registers */
590 regs
[525] = dsaf_read_dev(ppe_cb
, PPE_CFG_TX_FIFO_THRSLD_REG
);
591 regs
[526] = dsaf_read_dev(ppe_cb
, PPE_CFG_RX_FIFO_THRSLD_REG
);
592 regs
[527] = dsaf_read_dev(ppe_cb
, PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG
);
593 regs
[528] = dsaf_read_dev(ppe_cb
, PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG
);
594 regs
[529] = dsaf_read_dev(ppe_cb
, PPE_CFG_PAUSE_IDLE_CNT_REG
);
595 regs
[530] = dsaf_read_dev(ppe_cb
, PPE_CFG_BUS_CTRL_REG
);
596 regs
[531] = dsaf_read_dev(ppe_cb
, PPE_CFG_TNL_TO_BE_RST_REG
);
597 regs
[532] = dsaf_read_dev(ppe_cb
, PPE_CURR_TNL_CAN_RST_REG
);
599 regs
[533] = dsaf_read_dev(ppe_cb
, PPE_CFG_XGE_MODE_REG
);
600 regs
[534] = dsaf_read_dev(ppe_cb
, PPE_CFG_MAX_FRAME_LEN_REG
);
601 regs
[535] = dsaf_read_dev(ppe_cb
, PPE_CFG_RX_PKT_MODE_REG
);
602 regs
[536] = dsaf_read_dev(ppe_cb
, PPE_CFG_RX_VLAN_TAG_REG
);
603 regs
[537] = dsaf_read_dev(ppe_cb
, PPE_CFG_TAG_GEN_REG
);
604 regs
[538] = dsaf_read_dev(ppe_cb
, PPE_CFG_PARSE_TAG_REG
);
605 regs
[539] = dsaf_read_dev(ppe_cb
, PPE_CFG_PRO_CHECK_EN_REG
);
607 regs
[540] = dsaf_read_dev(ppe_cb
, PPE_INTEN_REG
);
608 regs
[541] = dsaf_read_dev(ppe_cb
, PPE_RINT_REG
);
609 regs
[542] = dsaf_read_dev(ppe_cb
, PPE_INTSTS_REG
);
610 regs
[543] = dsaf_read_dev(ppe_cb
, PPE_CFG_RX_PKT_INT_REG
);
612 regs
[544] = dsaf_read_dev(ppe_cb
, PPE_CFG_HEAT_DECT_TIME0_REG
);
613 regs
[545] = dsaf_read_dev(ppe_cb
, PPE_CFG_HEAT_DECT_TIME1_REG
);
616 regs
[546] = dsaf_read_dev(ppe_cb
, PPE_HIS_RX_SW_PKT_CNT_REG
);
617 regs
[547] = dsaf_read_dev(ppe_cb
, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG
);
618 regs
[548] = dsaf_read_dev(ppe_cb
, PPE_HIS_RX_PKT_NO_BUF_CNT_REG
);
619 regs
[549] = dsaf_read_dev(ppe_cb
, PPE_HIS_TX_BD_CNT_REG
);
620 regs
[550] = dsaf_read_dev(ppe_cb
, PPE_HIS_TX_PKT_CNT_REG
);
621 regs
[551] = dsaf_read_dev(ppe_cb
, PPE_HIS_TX_PKT_OK_CNT_REG
);
622 regs
[552] = dsaf_read_dev(ppe_cb
, PPE_HIS_TX_PKT_EPT_CNT_REG
);
623 regs
[553] = dsaf_read_dev(ppe_cb
, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG
);
624 regs
[554] = dsaf_read_dev(ppe_cb
, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG
);
625 regs
[555] = dsaf_read_dev(ppe_cb
, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG
);
626 regs
[556] = dsaf_read_dev(ppe_cb
, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG
);
627 regs
[557] = dsaf_read_dev(ppe_cb
, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG
);
629 regs
[558] = dsaf_read_dev(ppe_cb
, PPE_TNL_0_5_CNT_CLR_CE_REG
);
630 regs
[559] = dsaf_read_dev(ppe_cb
, PPE_CFG_AXI_DBG_REG
);
631 regs
[560] = dsaf_read_dev(ppe_cb
, PPE_HIS_PRO_ERR_REG
);
632 regs
[561] = dsaf_read_dev(ppe_cb
, PPE_HIS_TNL_FIFO_ERR_REG
);
633 regs
[562] = dsaf_read_dev(ppe_cb
, PPE_CURR_CFF_DATA_NUM_REG
);
634 regs
[563] = dsaf_read_dev(ppe_cb
, PPE_CURR_RX_ST_REG
);
635 regs
[564] = dsaf_read_dev(ppe_cb
, PPE_CURR_TX_ST_REG
);
636 regs
[565] = dsaf_read_dev(ppe_cb
, PPE_CURR_RX_FIFO0_REG
);
637 regs
[566] = dsaf_read_dev(ppe_cb
, PPE_CURR_RX_FIFO1_REG
);
638 regs
[567] = dsaf_read_dev(ppe_cb
, PPE_CURR_TX_FIFO0_REG
);
639 regs
[568] = dsaf_read_dev(ppe_cb
, PPE_CURR_TX_FIFO1_REG
);
640 regs
[569] = dsaf_read_dev(ppe_cb
, PPE_ECO0_REG
);
641 regs
[570] = dsaf_read_dev(ppe_cb
, PPE_ECO1_REG
);
642 regs
[571] = dsaf_read_dev(ppe_cb
, PPE_ECO2_REG
);
644 /* mark end of ppe regs */
645 for (i
= 572; i
< 576; i
++)
646 regs
[i
] = 0xeeeeeeee;