2 * Copyright (c) 2014-2015 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/errno.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/netdevice.h>
19 #include <linux/of_address.h>
21 #include <linux/of_mdio.h>
22 #include <linux/of_platform.h>
23 #include <linux/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/spinlock_types.h>
28 #define MDIO_DRV_NAME "Hi-HNS_MDIO"
29 #define MDIO_BUS_NAME "Hisilicon MII Bus"
30 #define MDIO_DRV_VERSION "1.3.0"
31 #define MDIO_COPYRIGHT "Copyright(c) 2015 Huawei Corporation."
32 #define MDIO_DRV_STRING MDIO_BUS_NAME
33 #define MDIO_DEFAULT_DEVICE_DESCR MDIO_BUS_NAME
35 #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
36 #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
38 #define MDIO_TIMEOUT 1000000
40 struct hns_mdio_device
{
41 void *vbase
; /* mdio reg base address */
42 struct regmap
*subctrl_vbase
;
46 #define MDIO_COMMAND_REG 0x0
47 #define MDIO_ADDR_REG 0x4
48 #define MDIO_WDATA_REG 0x8
49 #define MDIO_RDATA_REG 0xc
50 #define MDIO_STA_REG 0x10
53 #define MDIO_CMD_DEVAD_M 0x1f
54 #define MDIO_CMD_DEVAD_S 0
55 #define MDIO_CMD_PRTAD_M 0x1f
56 #define MDIO_CMD_PRTAD_S 5
57 #define MDIO_CMD_OP_M 0x3
58 #define MDIO_CMD_OP_S 10
59 #define MDIO_CMD_ST_M 0x3
60 #define MDIO_CMD_ST_S 12
61 #define MDIO_CMD_START_B 14
63 #define MDIO_ADDR_DATA_M 0xffff
64 #define MDIO_ADDR_DATA_S 0
66 #define MDIO_WDATA_DATA_M 0xffff
67 #define MDIO_WDATA_DATA_S 0
69 #define MDIO_RDATA_DATA_M 0xffff
70 #define MDIO_RDATA_DATA_S 0
72 #define MDIO_STATE_STA_B 0
75 MDIO_ST_CLAUSE_45
= 0,
79 enum mdio_c22_op_seq
{
84 enum mdio_c45_op_seq
{
85 MDIO_C45_WRITE_ADDR
= 0,
87 MDIO_C45_READ_INCREMENT
,
91 /* peri subctrl reg */
92 #define MDIO_SC_CLK_EN 0x338
93 #define MDIO_SC_CLK_DIS 0x33C
94 #define MDIO_SC_RESET_REQ 0xA38
95 #define MDIO_SC_RESET_DREQ 0xA3C
96 #define MDIO_SC_CTRL 0x2010
97 #define MDIO_SC_CLK_ST 0x531C
98 #define MDIO_SC_RESET_ST 0x5A1C
100 static void mdio_write_reg(void *base
, u32 reg
, u32 value
)
102 u8 __iomem
*reg_addr
= (u8 __iomem
*)base
;
104 writel_relaxed(value
, reg_addr
+ reg
);
107 #define MDIO_WRITE_REG(a, reg, value) \
108 mdio_write_reg((a)->vbase, (reg), (value))
110 static u32
mdio_read_reg(void *base
, u32 reg
)
112 u8 __iomem
*reg_addr
= (u8 __iomem
*)base
;
114 return readl_relaxed(reg_addr
+ reg
);
117 #define mdio_set_field(origin, mask, shift, val) \
119 (origin) &= (~((mask) << (shift))); \
120 (origin) |= (((val) & (mask)) << (shift)); \
123 #define mdio_get_field(origin, mask, shift) (((origin) >> (shift)) & (mask))
125 static void mdio_set_reg_field(void *base
, u32 reg
, u32 mask
, u32 shift
,
128 u32 origin
= mdio_read_reg(base
, reg
);
130 mdio_set_field(origin
, mask
, shift
, val
);
131 mdio_write_reg(base
, reg
, origin
);
134 #define MDIO_SET_REG_FIELD(dev, reg, mask, shift, val) \
135 mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val))
137 static u32
mdio_get_reg_field(void *base
, u32 reg
, u32 mask
, u32 shift
)
141 origin
= mdio_read_reg(base
, reg
);
142 return mdio_get_field(origin
, mask
, shift
);
145 #define MDIO_GET_REG_FIELD(dev, reg, mask, shift) \
146 mdio_get_reg_field((dev)->vbase, (reg), (mask), (shift))
148 #define MDIO_GET_REG_BIT(dev, reg, bit) \
149 mdio_get_reg_field((dev)->vbase, (reg), 0x1ull, (bit))
151 #define MDIO_CHECK_SET_ST 1
152 #define MDIO_CHECK_CLR_ST 0
154 static int mdio_sc_cfg_reg_write(struct hns_mdio_device
*mdio_dev
,
155 u32 cfg_reg
, u32 set_val
,
156 u32 st_reg
, u32 st_msk
, u8 check_st
)
161 regmap_write(mdio_dev
->subctrl_vbase
, cfg_reg
, set_val
);
163 for (time_cnt
= MDIO_TIMEOUT
; time_cnt
; time_cnt
--) {
164 regmap_read(mdio_dev
->subctrl_vbase
, st_reg
, ®_value
);
166 if ((!!check_st
) == (!!reg_value
))
170 if ((!!check_st
) != (!!reg_value
))
176 static int hns_mdio_wait_ready(struct mii_bus
*bus
)
178 struct hns_mdio_device
*mdio_dev
= bus
->priv
;
180 u32 cmd_reg_value
= 1;
182 /* waitting for MDIO_COMMAND_REG 's mdio_start==0 */
183 /* after that can do read or write*/
184 for (i
= 0; cmd_reg_value
; i
++) {
185 cmd_reg_value
= MDIO_GET_REG_BIT(mdio_dev
,
188 if (i
== MDIO_TIMEOUT
)
195 static void hns_mdio_cmd_write(struct hns_mdio_device
*mdio_dev
,
196 u8 is_c45
, u8 op
, u8 phy_id
, u16 cmd
)
199 u8 st
= is_c45
? MDIO_ST_CLAUSE_45
: MDIO_ST_CLAUSE_22
;
201 cmd_reg_value
= st
<< MDIO_CMD_ST_S
;
202 cmd_reg_value
|= op
<< MDIO_CMD_OP_S
;
204 (phy_id
& MDIO_CMD_PRTAD_M
) << MDIO_CMD_PRTAD_S
;
205 cmd_reg_value
|= (cmd
& MDIO_CMD_DEVAD_M
) << MDIO_CMD_DEVAD_S
;
206 cmd_reg_value
|= 1 << MDIO_CMD_START_B
;
208 MDIO_WRITE_REG(mdio_dev
, MDIO_COMMAND_REG
, cmd_reg_value
);
212 * hns_mdio_write - access phy register
215 * @regnum: register num
216 * @value: register value
218 * Return 0 on success, negative on failure
220 static int hns_mdio_write(struct mii_bus
*bus
,
221 int phy_id
, int regnum
, u16 data
)
224 struct hns_mdio_device
*mdio_dev
= (struct hns_mdio_device
*)bus
->priv
;
225 u8 devad
= ((regnum
>> 16) & 0x1f);
226 u8 is_c45
= !!(regnum
& MII_ADDR_C45
);
227 u16 reg
= (u16
)(regnum
& 0xffff);
231 dev_dbg(&bus
->dev
, "mdio write %s,base is %p\n",
232 bus
->id
, mdio_dev
->vbase
);
233 dev_dbg(&bus
->dev
, "phy id=%d, is_c45=%d, devad=%d, reg=%#x, write data=%d\n",
234 phy_id
, is_c45
, devad
, reg
, data
);
237 ret
= hns_mdio_wait_ready(bus
);
239 dev_err(&bus
->dev
, "MDIO bus is busy\n");
247 /* config the cmd-reg to write addr*/
248 MDIO_SET_REG_FIELD(mdio_dev
, MDIO_ADDR_REG
, MDIO_ADDR_DATA_M
,
249 MDIO_ADDR_DATA_S
, reg
);
251 hns_mdio_cmd_write(mdio_dev
, is_c45
,
252 MDIO_C45_WRITE_ADDR
, phy_id
, devad
);
254 /* check for read or write opt is finished */
255 ret
= hns_mdio_wait_ready(bus
);
257 dev_err(&bus
->dev
, "MDIO bus is busy\n");
261 /* config the data needed writing */
263 op
= MDIO_C45_WRITE_ADDR
;
266 MDIO_SET_REG_FIELD(mdio_dev
, MDIO_WDATA_REG
, MDIO_WDATA_DATA_M
,
267 MDIO_WDATA_DATA_S
, data
);
269 hns_mdio_cmd_write(mdio_dev
, is_c45
, op
, phy_id
, cmd_reg_cfg
);
275 * hns_mdio_read - access phy register
278 * @regnum: register num
279 * @value: register value
281 * Return phy register value
283 static int hns_mdio_read(struct mii_bus
*bus
, int phy_id
, int regnum
)
287 u8 devad
= ((regnum
>> 16) & 0x1f);
288 u8 is_c45
= !!(regnum
& MII_ADDR_C45
);
289 u16 reg
= (u16
)(regnum
& 0xffff);
290 struct hns_mdio_device
*mdio_dev
= (struct hns_mdio_device
*)bus
->priv
;
292 dev_dbg(&bus
->dev
, "mdio read %s,base is %p\n",
293 bus
->id
, mdio_dev
->vbase
);
294 dev_dbg(&bus
->dev
, "phy id=%d, is_c45=%d, devad=%d, reg=%#x!\n",
295 phy_id
, is_c45
, devad
, reg
);
297 /* Step 1: wait for ready */
298 ret
= hns_mdio_wait_ready(bus
);
300 dev_err(&bus
->dev
, "MDIO bus is busy\n");
305 hns_mdio_cmd_write(mdio_dev
, is_c45
,
306 MDIO_C22_READ
, phy_id
, reg
);
308 MDIO_SET_REG_FIELD(mdio_dev
, MDIO_ADDR_REG
, MDIO_ADDR_DATA_M
,
309 MDIO_ADDR_DATA_S
, reg
);
311 /* Step 2; config the cmd-reg to write addr*/
312 hns_mdio_cmd_write(mdio_dev
, is_c45
,
313 MDIO_C45_WRITE_ADDR
, phy_id
, devad
);
315 /* Step 3: check for read or write opt is finished */
316 ret
= hns_mdio_wait_ready(bus
);
318 dev_err(&bus
->dev
, "MDIO bus is busy\n");
322 hns_mdio_cmd_write(mdio_dev
, is_c45
,
323 MDIO_C45_WRITE_ADDR
, phy_id
, devad
);
326 /* Step 5: waitting for MDIO_COMMAND_REG 's mdio_start==0,*/
327 /* check for read or write opt is finished */
328 ret
= hns_mdio_wait_ready(bus
);
330 dev_err(&bus
->dev
, "MDIO bus is busy\n");
334 reg_val
= MDIO_GET_REG_BIT(mdio_dev
, MDIO_STA_REG
, MDIO_STATE_STA_B
);
336 dev_err(&bus
->dev
, " ERROR! MDIO Read failed!\n");
340 /* Step 6; get out data*/
341 reg_val
= (u16
)MDIO_GET_REG_FIELD(mdio_dev
, MDIO_RDATA_REG
,
342 MDIO_RDATA_DATA_M
, MDIO_RDATA_DATA_S
);
348 * hns_mdio_reset - reset mdio bus
351 * Return 0 on success, negative on failure
353 static int hns_mdio_reset(struct mii_bus
*bus
)
355 struct hns_mdio_device
*mdio_dev
= (struct hns_mdio_device
*)bus
->priv
;
358 if (dev_of_node(bus
->parent
)) {
359 if (!mdio_dev
->subctrl_vbase
) {
360 dev_err(&bus
->dev
, "mdio sys ctl reg has not maped\n");
364 /* 1. reset req, and read reset st check */
365 ret
= mdio_sc_cfg_reg_write(mdio_dev
, MDIO_SC_RESET_REQ
, 0x1,
366 MDIO_SC_RESET_ST
, 0x1,
369 dev_err(&bus
->dev
, "MDIO reset fail\n");
373 /* 2. dis clk, and read clk st check */
374 ret
= mdio_sc_cfg_reg_write(mdio_dev
, MDIO_SC_CLK_DIS
,
375 0x1, MDIO_SC_CLK_ST
, 0x1,
378 dev_err(&bus
->dev
, "MDIO dis clk fail\n");
382 /* 3. reset dreq, and read reset st check */
383 ret
= mdio_sc_cfg_reg_write(mdio_dev
, MDIO_SC_RESET_DREQ
, 0x1,
384 MDIO_SC_RESET_ST
, 0x1,
387 dev_err(&bus
->dev
, "MDIO dis clk fail\n");
391 /* 4. en clk, and read clk st check */
392 ret
= mdio_sc_cfg_reg_write(mdio_dev
, MDIO_SC_CLK_EN
,
393 0x1, MDIO_SC_CLK_ST
, 0x1,
396 dev_err(&bus
->dev
, "MDIO en clk fail\n");
397 } else if (is_acpi_node(bus
->parent
->fwnode
)) {
400 s
= acpi_evaluate_object(ACPI_HANDLE(bus
->parent
),
402 if (ACPI_FAILURE(s
)) {
403 dev_err(&bus
->dev
, "Reset failed, return:%#x\n", s
);
409 dev_err(&bus
->dev
, "Can not get cfg data from DT or ACPI\n");
416 * hns_mdio_probe - probe mdio device
417 * @pdev: mdio platform device
419 * Return 0 on success, negative on failure
421 static int hns_mdio_probe(struct platform_device
*pdev
)
423 struct hns_mdio_device
*mdio_dev
;
424 struct mii_bus
*new_bus
;
425 struct resource
*res
;
429 dev_err(NULL
, "pdev is NULL!\r\n");
433 mdio_dev
= devm_kzalloc(&pdev
->dev
, sizeof(*mdio_dev
), GFP_KERNEL
);
437 new_bus
= devm_mdiobus_alloc(&pdev
->dev
);
439 dev_err(&pdev
->dev
, "mdiobus_alloc fail!\n");
443 new_bus
->name
= MDIO_BUS_NAME
;
444 new_bus
->read
= hns_mdio_read
;
445 new_bus
->write
= hns_mdio_write
;
446 new_bus
->reset
= hns_mdio_reset
;
447 new_bus
->priv
= mdio_dev
;
448 new_bus
->parent
= &pdev
->dev
;
450 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
451 mdio_dev
->vbase
= devm_ioremap_resource(&pdev
->dev
, res
);
452 if (IS_ERR(mdio_dev
->vbase
)) {
453 ret
= PTR_ERR(mdio_dev
->vbase
);
457 platform_set_drvdata(pdev
, new_bus
);
458 snprintf(new_bus
->id
, MII_BUS_ID_SIZE
, "%s-%s", "Mii",
459 dev_name(&pdev
->dev
));
460 if (dev_of_node(&pdev
->dev
)) {
461 mdio_dev
->subctrl_vbase
= syscon_node_to_regmap(
462 of_parse_phandle(pdev
->dev
.of_node
,
463 "subctrl-vbase", 0));
464 if (IS_ERR(mdio_dev
->subctrl_vbase
)) {
465 dev_warn(&pdev
->dev
, "no syscon hisilicon,peri-c-subctrl\n");
466 mdio_dev
->subctrl_vbase
= NULL
;
468 ret
= of_mdiobus_register(new_bus
, pdev
->dev
.of_node
);
469 } else if (is_acpi_node(pdev
->dev
.fwnode
)) {
470 /* Clear all the IRQ properties */
471 memset(new_bus
->irq
, PHY_POLL
, 4 * PHY_MAX_ADDR
);
473 /* Mask out all PHYs from auto probing. */
474 new_bus
->phy_mask
= ~0;
476 /* Register the MDIO bus */
477 ret
= mdiobus_register(new_bus
);
479 dev_err(&pdev
->dev
, "Can not get cfg data from DT or ACPI\n");
484 dev_err(&pdev
->dev
, "Cannot register as MDIO bus!\n");
485 platform_set_drvdata(pdev
, NULL
);
493 * hns_mdio_remove - remove mdio device
494 * @pdev: mdio platform device
496 * Return 0 on success, negative on failure
498 static int hns_mdio_remove(struct platform_device
*pdev
)
502 bus
= platform_get_drvdata(pdev
);
504 mdiobus_unregister(bus
);
505 platform_set_drvdata(pdev
, NULL
);
509 static const struct of_device_id hns_mdio_match
[] = {
510 {.compatible
= "hisilicon,mdio"},
511 {.compatible
= "hisilicon,hns-mdio"},
515 static const struct acpi_device_id hns_mdio_acpi_match
[] = {
519 MODULE_DEVICE_TABLE(acpi
, hns_mdio_acpi_match
);
521 static struct platform_driver hns_mdio_driver
= {
522 .probe
= hns_mdio_probe
,
523 .remove
= hns_mdio_remove
,
525 .name
= MDIO_DRV_NAME
,
526 .of_match_table
= hns_mdio_match
,
527 .acpi_match_table
= ACPI_PTR(hns_mdio_acpi_match
),
531 module_platform_driver(hns_mdio_driver
);
533 MODULE_LICENSE("GPL");
534 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
535 MODULE_DESCRIPTION("Hisilicon HNS MDIO driver");
536 MODULE_ALIAS("platform:" MDIO_DRV_NAME
);