projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
e1000e: cleanup unusually placed comments
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / 82571.c
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /* 82571EB Gigabit Ethernet Controller
30 * 82571EB Gigabit Ethernet Controller (Copper)
31 * 82571EB Gigabit Ethernet Controller (Fiber)
32 * 82571EB Dual Port Gigabit Mezzanine Adapter
33 * 82571EB Quad Port Gigabit Mezzanine Adapter
34 * 82571PT Gigabit PT Quad Port Server ExpressModule
35 * 82572EI Gigabit Ethernet Controller (Copper)
36 * 82572EI Gigabit Ethernet Controller (Fiber)
37 * 82572EI Gigabit Ethernet Controller
38 * 82573V Gigabit Ethernet Controller (Copper)
39 * 82573E Gigabit Ethernet Controller (Copper)
40 * 82573L Gigabit Ethernet Controller
41 * 82574L Gigabit Network Connection
42 * 82583V Gigabit Network Connection
43 */
44
45 #include "e1000.h"
46
47 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
48 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
49 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
50 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
51 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
52 u16 words, u16 *data);
53 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
54 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
55 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
56 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
57 static s32 e1000_led_on_82574(struct e1000_hw *hw);
58 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
59 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
60 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
61 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
62 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
63 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);
64 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);
65
66 /**
67 * e1000_init_phy_params_82571 - Init PHY func ptrs.
68 * @hw: pointer to the HW structure
69 **/
70 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
71 {
72 struct e1000_phy_info *phy = &hw->phy;
73 s32 ret_val;
74
75 if (hw->phy.media_type != e1000_media_type_copper) {
76 phy->type = e1000_phy_none;
77 return 0;
78 }
79
80 phy->addr = 1;
81 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
82 phy->reset_delay_us = 100;
83
84 phy->ops.power_up = e1000_power_up_phy_copper;
85 phy->ops.power_down = e1000_power_down_phy_copper_82571;
86
87 switch (hw->mac.type) {
88 case e1000_82571:
89 case e1000_82572:
90 phy->type = e1000_phy_igp_2;
91 break;
92 case e1000_82573:
93 phy->type = e1000_phy_m88;
94 break;
95 case e1000_82574:
96 case e1000_82583:
97 phy->type = e1000_phy_bm;
98 phy->ops.acquire = e1000_get_hw_semaphore_82574;
99 phy->ops.release = e1000_put_hw_semaphore_82574;
100 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
101 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
102 break;
103 default:
104 return -E1000_ERR_PHY;
105 break;
106 }
107
108 /* This can only be done after all function pointers are setup. */
109 ret_val = e1000_get_phy_id_82571(hw);
110 if (ret_val) {
111 e_dbg("Error getting PHY ID\n");
112 return ret_val;
113 }
114
115 /* Verify phy id */
116 switch (hw->mac.type) {
117 case e1000_82571:
118 case e1000_82572:
119 if (phy->id != IGP01E1000_I_PHY_ID)
120 ret_val = -E1000_ERR_PHY;
121 break;
122 case e1000_82573:
123 if (phy->id != M88E1111_I_PHY_ID)
124 ret_val = -E1000_ERR_PHY;
125 break;
126 case e1000_82574:
127 case e1000_82583:
128 if (phy->id != BME1000_E_PHY_ID_R2)
129 ret_val = -E1000_ERR_PHY;
130 break;
131 default:
132 ret_val = -E1000_ERR_PHY;
133 break;
134 }
135
136 if (ret_val)
137 e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
138
139 return ret_val;
140 }
141
142 /**
143 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
144 * @hw: pointer to the HW structure
145 **/
146 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
147 {
148 struct e1000_nvm_info *nvm = &hw->nvm;
149 u32 eecd = er32(EECD);
150 u16 size;
151
152 nvm->opcode_bits = 8;
153 nvm->delay_usec = 1;
154 switch (nvm->override) {
155 case e1000_nvm_override_spi_large:
156 nvm->page_size = 32;
157 nvm->address_bits = 16;
158 break;
159 case e1000_nvm_override_spi_small:
160 nvm->page_size = 8;
161 nvm->address_bits = 8;
162 break;
163 default:
164 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
165 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
166 break;
167 }
168
169 switch (hw->mac.type) {
170 case e1000_82573:
171 case e1000_82574:
172 case e1000_82583:
173 if (((eecd >> 15) & 0x3) == 0x3) {
174 nvm->type = e1000_nvm_flash_hw;
175 nvm->word_size = 2048;
176 /* Autonomous Flash update bit must be cleared due
177 * to Flash update issue.
178 */
179 eecd &= ~E1000_EECD_AUPDEN;
180 ew32(EECD, eecd);
181 break;
182 }
183 /* Fall Through */
184 default:
185 nvm->type = e1000_nvm_eeprom_spi;
186 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
187 E1000_EECD_SIZE_EX_SHIFT);
188 /* Added to a constant, "size" becomes the left-shift value
189 * for setting word_size.
190 */
191 size += NVM_WORD_SIZE_BASE_SHIFT;
192
193 /* EEPROM access above 16k is unsupported */
194 if (size > 14)
195 size = 14;
196 nvm->word_size = 1 << size;
197 break;
198 }
199
200 /* Function Pointers */
201 switch (hw->mac.type) {
202 case e1000_82574:
203 case e1000_82583:
204 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
205 nvm->ops.release = e1000_put_hw_semaphore_82574;
206 break;
207 default:
208 break;
209 }
210
211 return 0;
212 }
213
214 /**
215 * e1000_init_mac_params_82571 - Init MAC func ptrs.
216 * @hw: pointer to the HW structure
217 **/
218 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
219 {
220 struct e1000_mac_info *mac = &hw->mac;
221 u32 swsm = 0;
222 u32 swsm2 = 0;
223 bool force_clear_smbi = false;
224
225 /* Set media type and media-dependent function pointers */
226 switch (hw->adapter->pdev->device) {
227 case E1000_DEV_ID_82571EB_FIBER:
228 case E1000_DEV_ID_82572EI_FIBER:
229 case E1000_DEV_ID_82571EB_QUAD_FIBER:
230 hw->phy.media_type = e1000_media_type_fiber;
231 mac->ops.setup_physical_interface =
232 e1000_setup_fiber_serdes_link_82571;
233 mac->ops.check_for_link = e1000e_check_for_fiber_link;
234 mac->ops.get_link_up_info =
235 e1000e_get_speed_and_duplex_fiber_serdes;
236 break;
237 case E1000_DEV_ID_82571EB_SERDES:
238 case E1000_DEV_ID_82571EB_SERDES_DUAL:
239 case E1000_DEV_ID_82571EB_SERDES_QUAD:
240 case E1000_DEV_ID_82572EI_SERDES:
241 hw->phy.media_type = e1000_media_type_internal_serdes;
242 mac->ops.setup_physical_interface =
243 e1000_setup_fiber_serdes_link_82571;
244 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
245 mac->ops.get_link_up_info =
246 e1000e_get_speed_and_duplex_fiber_serdes;
247 break;
248 default:
249 hw->phy.media_type = e1000_media_type_copper;
250 mac->ops.setup_physical_interface =
251 e1000_setup_copper_link_82571;
252 mac->ops.check_for_link = e1000e_check_for_copper_link;
253 mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper;
254 break;
255 }
256
257 /* Set mta register count */
258 mac->mta_reg_count = 128;
259 /* Set rar entry count */
260 mac->rar_entry_count = E1000_RAR_ENTRIES;
261 /* Adaptive IFS supported */
262 mac->adaptive_ifs = true;
263
264 /* MAC-specific function pointers */
265 switch (hw->mac.type) {
266 case e1000_82573:
267 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
268 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
269 mac->ops.led_on = e1000e_led_on_generic;
270 mac->ops.blink_led = e1000e_blink_led_generic;
271
272 /* FWSM register */
273 mac->has_fwsm = true;
274 /* ARC supported; valid only if manageability features are
275 * enabled.
276 */
277 mac->arc_subsystem_valid = !!(er32(FWSM) &
278 E1000_FWSM_MODE_MASK);
279 break;
280 case e1000_82574:
281 case e1000_82583:
282 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
283 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
284 mac->ops.led_on = e1000_led_on_82574;
285 break;
286 default:
287 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
288 mac->ops.led_on = e1000e_led_on_generic;
289 mac->ops.blink_led = e1000e_blink_led_generic;
290
291 /* FWSM register */
292 mac->has_fwsm = true;
293 break;
294 }
295
296 /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
297 * first NVM or PHY access. This should be done for single-port
298 * devices, and for one port only on dual-port devices so that
299 * for those devices we can still use the SMBI lock to synchronize
300 * inter-port accesses to the PHY & NVM.
301 */
302 switch (hw->mac.type) {
303 case e1000_82571:
304 case e1000_82572:
305 swsm2 = er32(SWSM2);
306
307 if (!(swsm2 & E1000_SWSM2_LOCK)) {
308 /* Only do this for the first interface on this card */
309 ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK);
310 force_clear_smbi = true;
311 } else {
312 force_clear_smbi = false;
313 }
314 break;
315 default:
316 force_clear_smbi = true;
317 break;
318 }
319
320 if (force_clear_smbi) {
321 /* Make sure SWSM.SMBI is clear */
322 swsm = er32(SWSM);
323 if (swsm & E1000_SWSM_SMBI) {
324 /* This bit should not be set on a first interface, and
325 * indicates that the bootagent or EFI code has
326 * improperly left this bit enabled
327 */
328 e_dbg("Please update your 82571 Bootagent\n");
329 }
330 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
331 }
332
333 /* Initialize device specific counter of SMBI acquisition timeouts. */
334 hw->dev_spec.e82571.smb_counter = 0;
335
336 return 0;
337 }
338
339 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
340 {
341 struct e1000_hw *hw = &adapter->hw;
342 static int global_quad_port_a; /* global port a indication */
343 struct pci_dev *pdev = adapter->pdev;
344 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
345 s32 rc;
346
347 rc = e1000_init_mac_params_82571(hw);
348 if (rc)
349 return rc;
350
351 rc = e1000_init_nvm_params_82571(hw);
352 if (rc)
353 return rc;
354
355 rc = e1000_init_phy_params_82571(hw);
356 if (rc)
357 return rc;
358
359 /* tag quad port adapters first, it's used below */
360 switch (pdev->device) {
361 case E1000_DEV_ID_82571EB_QUAD_COPPER:
362 case E1000_DEV_ID_82571EB_QUAD_FIBER:
363 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
364 case E1000_DEV_ID_82571PT_QUAD_COPPER:
365 adapter->flags |= FLAG_IS_QUAD_PORT;
366 /* mark the first port */
367 if (global_quad_port_a == 0)
368 adapter->flags |= FLAG_IS_QUAD_PORT_A;
369 /* Reset for multiple quad port adapters */
370 global_quad_port_a++;
371 if (global_quad_port_a == 4)
372 global_quad_port_a = 0;
373 break;
374 default:
375 break;
376 }
377
378 switch (adapter->hw.mac.type) {
379 case e1000_82571:
380 /* these dual ports don't have WoL on port B at all */
381 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
382 (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
383 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
384 (is_port_b))
385 adapter->flags &= ~FLAG_HAS_WOL;
386 /* quad ports only support WoL on port A */
387 if (adapter->flags & FLAG_IS_QUAD_PORT &&
388 (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
389 adapter->flags &= ~FLAG_HAS_WOL;
390 /* Does not support WoL on any port */
391 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
392 adapter->flags &= ~FLAG_HAS_WOL;
393 break;
394 case e1000_82573:
395 if (pdev->device == E1000_DEV_ID_82573L) {
396 adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
397 adapter->max_hw_frame_size = DEFAULT_JUMBO;
398 }
399 break;
400 default:
401 break;
402 }
403
404 return 0;
405 }
406
407 /**
408 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
409 * @hw: pointer to the HW structure
410 *
411 * Reads the PHY registers and stores the PHY ID and possibly the PHY
412 * revision in the hardware structure.
413 **/
414 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
415 {
416 struct e1000_phy_info *phy = &hw->phy;
417 s32 ret_val;
418 u16 phy_id = 0;
419
420 switch (hw->mac.type) {
421 case e1000_82571:
422 case e1000_82572:
423 /* The 82571 firmware may still be configuring the PHY.
424 * In this case, we cannot access the PHY until the
425 * configuration is done. So we explicitly set the
426 * PHY ID.
427 */
428 phy->id = IGP01E1000_I_PHY_ID;
429 break;
430 case e1000_82573:
431 return e1000e_get_phy_id(hw);
432 break;
433 case e1000_82574:
434 case e1000_82583:
435 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
436 if (ret_val)
437 return ret_val;
438
439 phy->id = (u32)(phy_id << 16);
440 udelay(20);
441 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
442 if (ret_val)
443 return ret_val;
444
445 phy->id |= (u32)(phy_id);
446 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
447 break;
448 default:
449 return -E1000_ERR_PHY;
450 break;
451 }
452
453 return 0;
454 }
455
456 /**
457 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
458 * @hw: pointer to the HW structure
459 *
460 * Acquire the HW semaphore to access the PHY or NVM
461 **/
462 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
463 {
464 u32 swsm;
465 s32 sw_timeout = hw->nvm.word_size + 1;
466 s32 fw_timeout = hw->nvm.word_size + 1;
467 s32 i = 0;
468
469 /* If we have timedout 3 times on trying to acquire
470 * the inter-port SMBI semaphore, there is old code
471 * operating on the other port, and it is not
472 * releasing SMBI. Modify the number of times that
473 * we try for the semaphore to interwork with this
474 * older code.
475 */
476 if (hw->dev_spec.e82571.smb_counter > 2)
477 sw_timeout = 1;
478
479 /* Get the SW semaphore */
480 while (i < sw_timeout) {
481 swsm = er32(SWSM);
482 if (!(swsm & E1000_SWSM_SMBI))
483 break;
484
485 udelay(50);
486 i++;
487 }
488
489 if (i == sw_timeout) {
490 e_dbg("Driver can't access device - SMBI bit is set.\n");
491 hw->dev_spec.e82571.smb_counter++;
492 }
493 /* Get the FW semaphore. */
494 for (i = 0; i < fw_timeout; i++) {
495 swsm = er32(SWSM);
496 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
497
498 /* Semaphore acquired if bit latched */
499 if (er32(SWSM) & E1000_SWSM_SWESMBI)
500 break;
501
502 udelay(50);
503 }
504
505 if (i == fw_timeout) {
506 /* Release semaphores */
507 e1000_put_hw_semaphore_82571(hw);
508 e_dbg("Driver can't access the NVM\n");
509 return -E1000_ERR_NVM;
510 }
511
512 return 0;
513 }
514
515 /**
516 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
517 * @hw: pointer to the HW structure
518 *
519 * Release hardware semaphore used to access the PHY or NVM
520 **/
521 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
522 {
523 u32 swsm;
524
525 swsm = er32(SWSM);
526 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
527 ew32(SWSM, swsm);
528 }
529
530 /**
531 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
532 * @hw: pointer to the HW structure
533 *
534 * Acquire the HW semaphore during reset.
535 *
536 **/
537 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
538 {
539 u32 extcnf_ctrl;
540 s32 i = 0;
541
542 extcnf_ctrl = er32(EXTCNF_CTRL);
543 do {
544 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
545 ew32(EXTCNF_CTRL, extcnf_ctrl);
546 extcnf_ctrl = er32(EXTCNF_CTRL);
547
548 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
549 break;
550
551 usleep_range(2000, 4000);
552 i++;
553 } while (i < MDIO_OWNERSHIP_TIMEOUT);
554
555 if (i == MDIO_OWNERSHIP_TIMEOUT) {
556 /* Release semaphores */
557 e1000_put_hw_semaphore_82573(hw);
558 e_dbg("Driver can't access the PHY\n");
559 return -E1000_ERR_PHY;
560 }
561
562 return 0;
563 }
564
565 /**
566 * e1000_put_hw_semaphore_82573 - Release hardware semaphore
567 * @hw: pointer to the HW structure
568 *
569 * Release hardware semaphore used during reset.
570 *
571 **/
572 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
573 {
574 u32 extcnf_ctrl;
575
576 extcnf_ctrl = er32(EXTCNF_CTRL);
577 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
578 ew32(EXTCNF_CTRL, extcnf_ctrl);
579 }
580
581 static DEFINE_MUTEX(swflag_mutex);
582
583 /**
584 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
585 * @hw: pointer to the HW structure
586 *
587 * Acquire the HW semaphore to access the PHY or NVM.
588 *
589 **/
590 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
591 {
592 s32 ret_val;
593
594 mutex_lock(&swflag_mutex);
595 ret_val = e1000_get_hw_semaphore_82573(hw);
596 if (ret_val)
597 mutex_unlock(&swflag_mutex);
598 return ret_val;
599 }
600
601 /**
602 * e1000_put_hw_semaphore_82574 - Release hardware semaphore
603 * @hw: pointer to the HW structure
604 *
605 * Release hardware semaphore used to access the PHY or NVM
606 *
607 **/
608 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
609 {
610 e1000_put_hw_semaphore_82573(hw);
611 mutex_unlock(&swflag_mutex);
612 }
613
614 /**
615 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
616 * @hw: pointer to the HW structure
617 * @active: true to enable LPLU, false to disable
618 *
619 * Sets the LPLU D0 state according to the active flag.
620 * LPLU will not be activated unless the
621 * device autonegotiation advertisement meets standards of
622 * either 10 or 10/100 or 10/100/1000 at all duplexes.
623 * This is a function pointer entry point only called by
624 * PHY setup routines.
625 **/
626 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
627 {
628 u32 data = er32(POEMB);
629
630 if (active)
631 data |= E1000_PHY_CTRL_D0A_LPLU;
632 else
633 data &= ~E1000_PHY_CTRL_D0A_LPLU;
634
635 ew32(POEMB, data);
636 return 0;
637 }
638
639 /**
640 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
641 * @hw: pointer to the HW structure
642 * @active: boolean used to enable/disable lplu
643 *
644 * The low power link up (lplu) state is set to the power management level D3
645 * when active is true, else clear lplu for D3. LPLU
646 * is used during Dx states where the power conservation is most important.
647 * During driver activity, SmartSpeed should be enabled so performance is
648 * maintained.
649 **/
650 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
651 {
652 u32 data = er32(POEMB);
653
654 if (!active) {
655 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
656 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
657 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
658 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
659 data |= E1000_PHY_CTRL_NOND0A_LPLU;
660 }
661
662 ew32(POEMB, data);
663 return 0;
664 }
665
666 /**
667 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
668 * @hw: pointer to the HW structure
669 *
670 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
671 * Then for non-82573 hardware, set the EEPROM access request bit and wait
672 * for EEPROM access grant bit. If the access grant bit is not set, release
673 * hardware semaphore.
674 **/
675 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
676 {
677 s32 ret_val;
678
679 ret_val = e1000_get_hw_semaphore_82571(hw);
680 if (ret_val)
681 return ret_val;
682
683 switch (hw->mac.type) {
684 case e1000_82573:
685 break;
686 default:
687 ret_val = e1000e_acquire_nvm(hw);
688 break;
689 }
690
691 if (ret_val)
692 e1000_put_hw_semaphore_82571(hw);
693
694 return ret_val;
695 }
696
697 /**
698 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
699 * @hw: pointer to the HW structure
700 *
701 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
702 **/
703 static void e1000_release_nvm_82571(struct e1000_hw *hw)
704 {
705 e1000e_release_nvm(hw);
706 e1000_put_hw_semaphore_82571(hw);
707 }
708
709 /**
710 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
711 * @hw: pointer to the HW structure
712 * @offset: offset within the EEPROM to be written to
713 * @words: number of words to write
714 * @data: 16 bit word(s) to be written to the EEPROM
715 *
716 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
717 *
718 * If e1000e_update_nvm_checksum is not called after this function, the
719 * EEPROM will most likely contain an invalid checksum.
720 **/
721 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
722 u16 *data)
723 {
724 s32 ret_val;
725
726 switch (hw->mac.type) {
727 case e1000_82573:
728 case e1000_82574:
729 case e1000_82583:
730 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
731 break;
732 case e1000_82571:
733 case e1000_82572:
734 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
735 break;
736 default:
737 ret_val = -E1000_ERR_NVM;
738 break;
739 }
740
741 return ret_val;
742 }
743
744 /**
745 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
746 * @hw: pointer to the HW structure
747 *
748 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
749 * up to the checksum. Then calculates the EEPROM checksum and writes the
750 * value to the EEPROM.
751 **/
752 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
753 {
754 u32 eecd;
755 s32 ret_val;
756 u16 i;
757
758 ret_val = e1000e_update_nvm_checksum_generic(hw);
759 if (ret_val)
760 return ret_val;
761
762 /* If our nvm is an EEPROM, then we're done
763 * otherwise, commit the checksum to the flash NVM.
764 */
765 if (hw->nvm.type != e1000_nvm_flash_hw)
766 return 0;
767
768 /* Check for pending operations. */
769 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
770 usleep_range(1000, 2000);
771 if (!(er32(EECD) & E1000_EECD_FLUPD))
772 break;
773 }
774
775 if (i == E1000_FLASH_UPDATES)
776 return -E1000_ERR_NVM;
777
778 /* Reset the firmware if using STM opcode. */
779 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
780 /* The enabling of and the actual reset must be done
781 * in two write cycles.
782 */
783 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
784 e1e_flush();
785 ew32(HICR, E1000_HICR_FW_RESET);
786 }
787
788 /* Commit the write to flash */
789 eecd = er32(EECD) | E1000_EECD_FLUPD;
790 ew32(EECD, eecd);
791
792 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
793 usleep_range(1000, 2000);
794 if (!(er32(EECD) & E1000_EECD_FLUPD))
795 break;
796 }
797
798 if (i == E1000_FLASH_UPDATES)
799 return -E1000_ERR_NVM;
800
801 return 0;
802 }
803
804 /**
805 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
806 * @hw: pointer to the HW structure
807 *
808 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
809 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
810 **/
811 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
812 {
813 if (hw->nvm.type == e1000_nvm_flash_hw)
814 e1000_fix_nvm_checksum_82571(hw);
815
816 return e1000e_validate_nvm_checksum_generic(hw);
817 }
818
819 /**
820 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
821 * @hw: pointer to the HW structure
822 * @offset: offset within the EEPROM to be written to
823 * @words: number of words to write
824 * @data: 16 bit word(s) to be written to the EEPROM
825 *
826 * After checking for invalid values, poll the EEPROM to ensure the previous
827 * command has completed before trying to write the next word. After write
828 * poll for completion.
829 *
830 * If e1000e_update_nvm_checksum is not called after this function, the
831 * EEPROM will most likely contain an invalid checksum.
832 **/
833 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
834 u16 words, u16 *data)
835 {
836 struct e1000_nvm_info *nvm = &hw->nvm;
837 u32 i, eewr = 0;
838 s32 ret_val = 0;
839
840 /* A check for invalid values: offset too large, too many words,
841 * and not enough words.
842 */
843 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
844 (words == 0)) {
845 e_dbg("nvm parameter(s) out of bounds\n");
846 return -E1000_ERR_NVM;
847 }
848
849 for (i = 0; i < words; i++) {
850 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
851 ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
852 E1000_NVM_RW_REG_START);
853
854 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
855 if (ret_val)
856 break;
857
858 ew32(EEWR, eewr);
859
860 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
861 if (ret_val)
862 break;
863 }
864
865 return ret_val;
866 }
867
868 /**
869 * e1000_get_cfg_done_82571 - Poll for configuration done
870 * @hw: pointer to the HW structure
871 *
872 * Reads the management control register for the config done bit to be set.
873 **/
874 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
875 {
876 s32 timeout = PHY_CFG_TIMEOUT;
877
878 while (timeout) {
879 if (er32(EEMNGCTL) &
880 E1000_NVM_CFG_DONE_PORT_0)
881 break;
882 usleep_range(1000, 2000);
883 timeout--;
884 }
885 if (!timeout) {
886 e_dbg("MNG configuration cycle has not completed.\n");
887 return -E1000_ERR_RESET;
888 }
889
890 return 0;
891 }
892
893 /**
894 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
895 * @hw: pointer to the HW structure
896 * @active: true to enable LPLU, false to disable
897 *
898 * Sets the LPLU D0 state according to the active flag. When activating LPLU
899 * this function also disables smart speed and vice versa. LPLU will not be
900 * activated unless the device autonegotiation advertisement meets standards
901 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
902 * pointer entry point only called by PHY setup routines.
903 **/
904 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
905 {
906 struct e1000_phy_info *phy = &hw->phy;
907 s32 ret_val;
908 u16 data;
909
910 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
911 if (ret_val)
912 return ret_val;
913
914 if (active) {
915 data |= IGP02E1000_PM_D0_LPLU;
916 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
917 if (ret_val)
918 return ret_val;
919
920 /* When LPLU is enabled, we should disable SmartSpeed */
921 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
922 if (ret_val)
923 return ret_val;
924 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
925 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
926 if (ret_val)
927 return ret_val;
928 } else {
929 data &= ~IGP02E1000_PM_D0_LPLU;
930 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
931 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
932 * during Dx states where the power conservation is most
933 * important. During driver activity we should enable
934 * SmartSpeed, so performance is maintained.
935 */
936 if (phy->smart_speed == e1000_smart_speed_on) {
937 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
938 &data);
939 if (ret_val)
940 return ret_val;
941
942 data |= IGP01E1000_PSCFR_SMART_SPEED;
943 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
944 data);
945 if (ret_val)
946 return ret_val;
947 } else if (phy->smart_speed == e1000_smart_speed_off) {
948 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
949 &data);
950 if (ret_val)
951 return ret_val;
952
953 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
954 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
955 data);
956 if (ret_val)
957 return ret_val;
958 }
959 }
960
961 return 0;
962 }
963
964 /**
965 * e1000_reset_hw_82571 - Reset hardware
966 * @hw: pointer to the HW structure
967 *
968 * This resets the hardware into a known state.
969 **/
970 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
971 {
972 u32 ctrl, ctrl_ext, eecd, tctl;
973 s32 ret_val;
974
975 /* Prevent the PCI-E bus from sticking if there is no TLP connection
976 * on the last TLP read/write transaction when MAC is reset.
977 */
978 ret_val = e1000e_disable_pcie_master(hw);
979 if (ret_val)
980 e_dbg("PCI-E Master disable polling has failed.\n");
981
982 e_dbg("Masking off all interrupts\n");
983 ew32(IMC, 0xffffffff);
984
985 ew32(RCTL, 0);
986 tctl = er32(TCTL);
987 tctl &= ~E1000_TCTL_EN;
988 ew32(TCTL, tctl);
989 e1e_flush();
990
991 usleep_range(10000, 20000);
992
993 /* Must acquire the MDIO ownership before MAC reset.
994 * Ownership defaults to firmware after a reset.
995 */
996 switch (hw->mac.type) {
997 case e1000_82573:
998 ret_val = e1000_get_hw_semaphore_82573(hw);
999 break;
1000 case e1000_82574:
1001 case e1000_82583:
1002 ret_val = e1000_get_hw_semaphore_82574(hw);
1003 break;
1004 default:
1005 break;
1006 }
1007 if (ret_val)
1008 e_dbg("Cannot acquire MDIO ownership\n");
1009
1010 ctrl = er32(CTRL);
1011
1012 e_dbg("Issuing a global reset to MAC\n");
1013 ew32(CTRL, ctrl | E1000_CTRL_RST);
1014
1015 /* Must release MDIO ownership and mutex after MAC reset. */
1016 switch (hw->mac.type) {
1017 case e1000_82574:
1018 case e1000_82583:
1019 e1000_put_hw_semaphore_82574(hw);
1020 break;
1021 default:
1022 break;
1023 }
1024
1025 if (hw->nvm.type == e1000_nvm_flash_hw) {
1026 udelay(10);
1027 ctrl_ext = er32(CTRL_EXT);
1028 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1029 ew32(CTRL_EXT, ctrl_ext);
1030 e1e_flush();
1031 }
1032
1033 ret_val = e1000e_get_auto_rd_done(hw);
1034 if (ret_val)
1035 /* We don't want to continue accessing MAC registers. */
1036 return ret_val;
1037
1038 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1039 * Need to wait for Phy configuration completion before accessing
1040 * NVM and Phy.
1041 */
1042
1043 switch (hw->mac.type) {
1044 case e1000_82571:
1045 case e1000_82572:
1046 /* REQ and GNT bits need to be cleared when using AUTO_RD
1047 * to access the EEPROM.
1048 */
1049 eecd = er32(EECD);
1050 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1051 ew32(EECD, eecd);
1052 break;
1053 case e1000_82573:
1054 case e1000_82574:
1055 case e1000_82583:
1056 msleep(25);
1057 break;
1058 default:
1059 break;
1060 }
1061
1062 /* Clear any pending interrupt events. */
1063 ew32(IMC, 0xffffffff);
1064 er32(ICR);
1065
1066 if (hw->mac.type == e1000_82571) {
1067 /* Install any alternate MAC address into RAR0 */
1068 ret_val = e1000_check_alt_mac_addr_generic(hw);
1069 if (ret_val)
1070 return ret_val;
1071
1072 e1000e_set_laa_state_82571(hw, true);
1073 }
1074
1075 /* Reinitialize the 82571 serdes link state machine */
1076 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1077 hw->mac.serdes_link_state = e1000_serdes_link_down;
1078
1079 return 0;
1080 }
1081
1082 /**
1083 * e1000_init_hw_82571 - Initialize hardware
1084 * @hw: pointer to the HW structure
1085 *
1086 * This inits the hardware readying it for operation.
1087 **/
1088 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1089 {
1090 struct e1000_mac_info *mac = &hw->mac;
1091 u32 reg_data;
1092 s32 ret_val;
1093 u16 i, rar_count = mac->rar_entry_count;
1094
1095 e1000_initialize_hw_bits_82571(hw);
1096
1097 /* Initialize identification LED */
1098 ret_val = mac->ops.id_led_init(hw);
1099 /* An error is not fatal and we should not stop init due to this */
1100 if (ret_val)
1101 e_dbg("Error initializing identification LED\n");
1102
1103 /* Disabling VLAN filtering */
1104 e_dbg("Initializing the IEEE VLAN\n");
1105 mac->ops.clear_vfta(hw);
1106
1107 /* Setup the receive address.
1108 * If, however, a locally administered address was assigned to the
1109 * 82571, we must reserve a RAR for it to work around an issue where
1110 * resetting one port will reload the MAC on the other port.
1111 */
1112 if (e1000e_get_laa_state_82571(hw))
1113 rar_count--;
1114 e1000e_init_rx_addrs(hw, rar_count);
1115
1116 /* Zero out the Multicast HASH table */
1117 e_dbg("Zeroing the MTA\n");
1118 for (i = 0; i < mac->mta_reg_count; i++)
1119 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1120
1121 /* Setup link and flow control */
1122 ret_val = mac->ops.setup_link(hw);
1123
1124 /* Set the transmit descriptor write-back policy */
1125 reg_data = er32(TXDCTL(0));
1126 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1127 E1000_TXDCTL_FULL_TX_DESC_WB |
1128 E1000_TXDCTL_COUNT_DESC);
1129 ew32(TXDCTL(0), reg_data);
1130
1131 /* ...for both queues. */
1132 switch (mac->type) {
1133 case e1000_82573:
1134 e1000e_enable_tx_pkt_filtering(hw);
1135 /* fall through */
1136 case e1000_82574:
1137 case e1000_82583:
1138 reg_data = er32(GCR);
1139 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1140 ew32(GCR, reg_data);
1141 break;
1142 default:
1143 reg_data = er32(TXDCTL(1));
1144 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1145 E1000_TXDCTL_FULL_TX_DESC_WB |
1146 E1000_TXDCTL_COUNT_DESC);
1147 ew32(TXDCTL(1), reg_data);
1148 break;
1149 }
1150
1151 /* Clear all of the statistics registers (clear on read). It is
1152 * important that we do this after we have tried to establish link
1153 * because the symbol error count will increment wildly if there
1154 * is no link.
1155 */
1156 e1000_clear_hw_cntrs_82571(hw);
1157
1158 return ret_val;
1159 }
1160
1161 /**
1162 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1163 * @hw: pointer to the HW structure
1164 *
1165 * Initializes required hardware-dependent bits needed for normal operation.
1166 **/
1167 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1168 {
1169 u32 reg;
1170
1171 /* Transmit Descriptor Control 0 */
1172 reg = er32(TXDCTL(0));
1173 reg |= (1 << 22);
1174 ew32(TXDCTL(0), reg);
1175
1176 /* Transmit Descriptor Control 1 */
1177 reg = er32(TXDCTL(1));
1178 reg |= (1 << 22);
1179 ew32(TXDCTL(1), reg);
1180
1181 /* Transmit Arbitration Control 0 */
1182 reg = er32(TARC(0));
1183 reg &= ~(0xF << 27); /* 30:27 */
1184 switch (hw->mac.type) {
1185 case e1000_82571:
1186 case e1000_82572:
1187 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1188 break;
1189 case e1000_82574:
1190 case e1000_82583:
1191 reg |= (1 << 26);
1192 break;
1193 default:
1194 break;
1195 }
1196 ew32(TARC(0), reg);
1197
1198 /* Transmit Arbitration Control 1 */
1199 reg = er32(TARC(1));
1200 switch (hw->mac.type) {
1201 case e1000_82571:
1202 case e1000_82572:
1203 reg &= ~((1 << 29) | (1 << 30));
1204 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1205 if (er32(TCTL) & E1000_TCTL_MULR)
1206 reg &= ~(1 << 28);
1207 else
1208 reg |= (1 << 28);
1209 ew32(TARC(1), reg);
1210 break;
1211 default:
1212 break;
1213 }
1214
1215 /* Device Control */
1216 switch (hw->mac.type) {
1217 case e1000_82573:
1218 case e1000_82574:
1219 case e1000_82583:
1220 reg = er32(CTRL);
1221 reg &= ~(1 << 29);
1222 ew32(CTRL, reg);
1223 break;
1224 default:
1225 break;
1226 }
1227
1228 /* Extended Device Control */
1229 switch (hw->mac.type) {
1230 case e1000_82573:
1231 case e1000_82574:
1232 case e1000_82583:
1233 reg = er32(CTRL_EXT);
1234 reg &= ~(1 << 23);
1235 reg |= (1 << 22);
1236 ew32(CTRL_EXT, reg);
1237 break;
1238 default:
1239 break;
1240 }
1241
1242 if (hw->mac.type == e1000_82571) {
1243 reg = er32(PBA_ECC);
1244 reg |= E1000_PBA_ECC_CORR_EN;
1245 ew32(PBA_ECC, reg);
1246 }
1247
1248 /* Workaround for hardware errata.
1249 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1250 */
1251 if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) {
1252 reg = er32(CTRL_EXT);
1253 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1254 ew32(CTRL_EXT, reg);
1255 }
1256
1257 /* Disable IPv6 extension header parsing because some malformed
1258 * IPv6 headers can hang the Rx.
1259 */
1260 if (hw->mac.type <= e1000_82573) {
1261 reg = er32(RFCTL);
1262 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1263 ew32(RFCTL, reg);
1264 }
1265
1266 /* PCI-Ex Control Registers */
1267 switch (hw->mac.type) {
1268 case e1000_82574:
1269 case e1000_82583:
1270 reg = er32(GCR);
1271 reg |= (1 << 22);
1272 ew32(GCR, reg);
1273
1274 /* Workaround for hardware errata.
1275 * apply workaround for hardware errata documented in errata
1276 * docs Fixes issue where some error prone or unreliable PCIe
1277 * completions are occurring, particularly with ASPM enabled.
1278 * Without fix, issue can cause Tx timeouts.
1279 */
1280 reg = er32(GCR2);
1281 reg |= 1;
1282 ew32(GCR2, reg);
1283 break;
1284 default:
1285 break;
1286 }
1287 }
1288
1289 /**
1290 * e1000_clear_vfta_82571 - Clear VLAN filter table
1291 * @hw: pointer to the HW structure
1292 *
1293 * Clears the register array which contains the VLAN filter table by
1294 * setting all the values to 0.
1295 **/
1296 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1297 {
1298 u32 offset;
1299 u32 vfta_value = 0;
1300 u32 vfta_offset = 0;
1301 u32 vfta_bit_in_reg = 0;
1302
1303 switch (hw->mac.type) {
1304 case e1000_82573:
1305 case e1000_82574:
1306 case e1000_82583:
1307 if (hw->mng_cookie.vlan_id != 0) {
1308 /* The VFTA is a 4096b bit-field, each identifying
1309 * a single VLAN ID. The following operations
1310 * determine which 32b entry (i.e. offset) into the
1311 * array we want to set the VLAN ID (i.e. bit) of
1312 * the manageability unit.
1313 */
1314 vfta_offset = (hw->mng_cookie.vlan_id >>
1315 E1000_VFTA_ENTRY_SHIFT) &
1316 E1000_VFTA_ENTRY_MASK;
1317 vfta_bit_in_reg =
1318 1 << (hw->mng_cookie.vlan_id &
1319 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1320 }
1321 break;
1322 default:
1323 break;
1324 }
1325 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1326 /* If the offset we want to clear is the same offset of the
1327 * manageability VLAN ID, then clear all bits except that of
1328 * the manageability unit.
1329 */
1330 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1331 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1332 e1e_flush();
1333 }
1334 }
1335
1336 /**
1337 * e1000_check_mng_mode_82574 - Check manageability is enabled
1338 * @hw: pointer to the HW structure
1339 *
1340 * Reads the NVM Initialization Control Word 2 and returns true
1341 * (>0) if any manageability is enabled, else false (0).
1342 **/
1343 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1344 {
1345 u16 data;
1346
1347 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1348 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1349 }
1350
1351 /**
1352 * e1000_led_on_82574 - Turn LED on
1353 * @hw: pointer to the HW structure
1354 *
1355 * Turn LED on.
1356 **/
1357 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1358 {
1359 u32 ctrl;
1360 u32 i;
1361
1362 ctrl = hw->mac.ledctl_mode2;
1363 if (!(E1000_STATUS_LU & er32(STATUS))) {
1364 /* If no link, then turn LED on by setting the invert bit
1365 * for each LED that's "on" (0x0E) in ledctl_mode2.
1366 */
1367 for (i = 0; i < 4; i++)
1368 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1369 E1000_LEDCTL_MODE_LED_ON)
1370 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1371 }
1372 ew32(LEDCTL, ctrl);
1373
1374 return 0;
1375 }
1376
1377 /**
1378 * e1000_check_phy_82574 - check 82574 phy hung state
1379 * @hw: pointer to the HW structure
1380 *
1381 * Returns whether phy is hung or not
1382 **/
1383 bool e1000_check_phy_82574(struct e1000_hw *hw)
1384 {
1385 u16 status_1kbt = 0;
1386 u16 receive_errors = 0;
1387 s32 ret_val;
1388
1389 /* Read PHY Receive Error counter first, if its is max - all F's then
1390 * read the Base1000T status register If both are max then PHY is hung.
1391 */
1392 ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
1393 if (ret_val)
1394 return false;
1395 if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1396 ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
1397 if (ret_val)
1398 return false;
1399 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1400 E1000_IDLE_ERROR_COUNT_MASK)
1401 return true;
1402 }
1403
1404 return false;
1405 }
1406
1407 /**
1408 * e1000_setup_link_82571 - Setup flow control and link settings
1409 * @hw: pointer to the HW structure
1410 *
1411 * Determines which flow control settings to use, then configures flow
1412 * control. Calls the appropriate media-specific link configuration
1413 * function. Assuming the adapter has a valid link partner, a valid link
1414 * should be established. Assumes the hardware has previously been reset
1415 * and the transmitter and receiver are not enabled.
1416 **/
1417 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1418 {
1419 /* 82573 does not have a word in the NVM to determine
1420 * the default flow control setting, so we explicitly
1421 * set it to full.
1422 */
1423 switch (hw->mac.type) {
1424 case e1000_82573:
1425 case e1000_82574:
1426 case e1000_82583:
1427 if (hw->fc.requested_mode == e1000_fc_default)
1428 hw->fc.requested_mode = e1000_fc_full;
1429 break;
1430 default:
1431 break;
1432 }
1433
1434 return e1000e_setup_link_generic(hw);
1435 }
1436
1437 /**
1438 * e1000_setup_copper_link_82571 - Configure copper link settings
1439 * @hw: pointer to the HW structure
1440 *
1441 * Configures the link for auto-neg or forced speed and duplex. Then we check
1442 * for link, once link is established calls to configure collision distance
1443 * and flow control are called.
1444 **/
1445 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1446 {
1447 u32 ctrl;
1448 s32 ret_val;
1449
1450 ctrl = er32(CTRL);
1451 ctrl |= E1000_CTRL_SLU;
1452 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1453 ew32(CTRL, ctrl);
1454
1455 switch (hw->phy.type) {
1456 case e1000_phy_m88:
1457 case e1000_phy_bm:
1458 ret_val = e1000e_copper_link_setup_m88(hw);
1459 break;
1460 case e1000_phy_igp_2:
1461 ret_val = e1000e_copper_link_setup_igp(hw);
1462 break;
1463 default:
1464 return -E1000_ERR_PHY;
1465 break;
1466 }
1467
1468 if (ret_val)
1469 return ret_val;
1470
1471 return e1000e_setup_copper_link(hw);
1472 }
1473
1474 /**
1475 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1476 * @hw: pointer to the HW structure
1477 *
1478 * Configures collision distance and flow control for fiber and serdes links.
1479 * Upon successful setup, poll for link.
1480 **/
1481 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1482 {
1483 switch (hw->mac.type) {
1484 case e1000_82571:
1485 case e1000_82572:
1486 /* If SerDes loopback mode is entered, there is no form
1487 * of reset to take the adapter out of that mode. So we
1488 * have to explicitly take the adapter out of loopback
1489 * mode. This prevents drivers from twiddling their thumbs
1490 * if another tool failed to take it out of loopback mode.
1491 */
1492 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1493 break;
1494 default:
1495 break;
1496 }
1497
1498 return e1000e_setup_fiber_serdes_link(hw);
1499 }
1500
1501 /**
1502 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1503 * @hw: pointer to the HW structure
1504 *
1505 * Reports the link state as up or down.
1506 *
1507 * If autonegotiation is supported by the link partner, the link state is
1508 * determined by the result of autonegotiation. This is the most likely case.
1509 * If autonegotiation is not supported by the link partner, and the link
1510 * has a valid signal, force the link up.
1511 *
1512 * The link state is represented internally here by 4 states:
1513 *
1514 * 1) down
1515 * 2) autoneg_progress
1516 * 3) autoneg_complete (the link successfully autonegotiated)
1517 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1518 *
1519 **/
1520 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1521 {
1522 struct e1000_mac_info *mac = &hw->mac;
1523 u32 rxcw;
1524 u32 ctrl;
1525 u32 status;
1526 u32 txcw;
1527 u32 i;
1528 s32 ret_val = 0;
1529
1530 ctrl = er32(CTRL);
1531 status = er32(STATUS);
1532 er32(RXCW);
1533 /* SYNCH bit and IV bit are sticky */
1534 udelay(10);
1535 rxcw = er32(RXCW);
1536
1537 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1538 /* Receiver is synchronized with no invalid bits. */
1539 switch (mac->serdes_link_state) {
1540 case e1000_serdes_link_autoneg_complete:
1541 if (!(status & E1000_STATUS_LU)) {
1542 /* We have lost link, retry autoneg before
1543 * reporting link failure
1544 */
1545 mac->serdes_link_state =
1546 e1000_serdes_link_autoneg_progress;
1547 mac->serdes_has_link = false;
1548 e_dbg("AN_UP -> AN_PROG\n");
1549 } else {
1550 mac->serdes_has_link = true;
1551 }
1552 break;
1553
1554 case e1000_serdes_link_forced_up:
1555 /* If we are receiving /C/ ordered sets, re-enable
1556 * auto-negotiation in the TXCW register and disable
1557 * forced link in the Device Control register in an
1558 * attempt to auto-negotiate with our link partner.
1559 */
1560 if (rxcw & E1000_RXCW_C) {
1561 /* Enable autoneg, and unforce link up */
1562 ew32(TXCW, mac->txcw);
1563 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1564 mac->serdes_link_state =
1565 e1000_serdes_link_autoneg_progress;
1566 mac->serdes_has_link = false;
1567 e_dbg("FORCED_UP -> AN_PROG\n");
1568 } else {
1569 mac->serdes_has_link = true;
1570 }
1571 break;
1572
1573 case e1000_serdes_link_autoneg_progress:
1574 if (rxcw & E1000_RXCW_C) {
1575 /* We received /C/ ordered sets, meaning the
1576 * link partner has autonegotiated, and we can
1577 * trust the Link Up (LU) status bit.
1578 */
1579 if (status & E1000_STATUS_LU) {
1580 mac->serdes_link_state =
1581 e1000_serdes_link_autoneg_complete;
1582 e_dbg("AN_PROG -> AN_UP\n");
1583 mac->serdes_has_link = true;
1584 } else {
1585 /* Autoneg completed, but failed. */
1586 mac->serdes_link_state =
1587 e1000_serdes_link_down;
1588 e_dbg("AN_PROG -> DOWN\n");
1589 }
1590 } else {
1591 /* The link partner did not autoneg.
1592 * Force link up and full duplex, and change
1593 * state to forced.
1594 */
1595 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1596 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1597 ew32(CTRL, ctrl);
1598
1599 /* Configure Flow Control after link up. */
1600 ret_val = e1000e_config_fc_after_link_up(hw);
1601 if (ret_val) {
1602 e_dbg("Error config flow control\n");
1603 break;
1604 }
1605 mac->serdes_link_state =
1606 e1000_serdes_link_forced_up;
1607 mac->serdes_has_link = true;
1608 e_dbg("AN_PROG -> FORCED_UP\n");
1609 }
1610 break;
1611
1612 case e1000_serdes_link_down:
1613 default:
1614 /* The link was down but the receiver has now gained
1615 * valid sync, so lets see if we can bring the link
1616 * up.
1617 */
1618 ew32(TXCW, mac->txcw);
1619 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1620 mac->serdes_link_state =
1621 e1000_serdes_link_autoneg_progress;
1622 mac->serdes_has_link = false;
1623 e_dbg("DOWN -> AN_PROG\n");
1624 break;
1625 }
1626 } else {
1627 if (!(rxcw & E1000_RXCW_SYNCH)) {
1628 mac->serdes_has_link = false;
1629 mac->serdes_link_state = e1000_serdes_link_down;
1630 e_dbg("ANYSTATE -> DOWN\n");
1631 } else {
1632 /* Check several times, if SYNCH bit and CONFIG
1633 * bit both are consistently 1 then simply ignore
1634 * the IV bit and restart Autoneg
1635 */
1636 for (i = 0; i < AN_RETRY_COUNT; i++) {
1637 udelay(10);
1638 rxcw = er32(RXCW);
1639 if ((rxcw & E1000_RXCW_SYNCH) &&
1640 (rxcw & E1000_RXCW_C))
1641 continue;
1642
1643 if (rxcw & E1000_RXCW_IV) {
1644 mac->serdes_has_link = false;
1645 mac->serdes_link_state =
1646 e1000_serdes_link_down;
1647 e_dbg("ANYSTATE -> DOWN\n");
1648 break;
1649 }
1650 }
1651
1652 if (i == AN_RETRY_COUNT) {
1653 txcw = er32(TXCW);
1654 txcw |= E1000_TXCW_ANE;
1655 ew32(TXCW, txcw);
1656 mac->serdes_link_state =
1657 e1000_serdes_link_autoneg_progress;
1658 mac->serdes_has_link = false;
1659 e_dbg("ANYSTATE -> AN_PROG\n");
1660 }
1661 }
1662 }
1663
1664 return ret_val;
1665 }
1666
1667 /**
1668 * e1000_valid_led_default_82571 - Verify a valid default LED config
1669 * @hw: pointer to the HW structure
1670 * @data: pointer to the NVM (EEPROM)
1671 *
1672 * Read the EEPROM for the current default LED configuration. If the
1673 * LED configuration is not valid, set to a valid LED configuration.
1674 **/
1675 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1676 {
1677 s32 ret_val;
1678
1679 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1680 if (ret_val) {
1681 e_dbg("NVM Read Error\n");
1682 return ret_val;
1683 }
1684
1685 switch (hw->mac.type) {
1686 case e1000_82573:
1687 case e1000_82574:
1688 case e1000_82583:
1689 if (*data == ID_LED_RESERVED_F746)
1690 *data = ID_LED_DEFAULT_82573;
1691 break;
1692 default:
1693 if (*data == ID_LED_RESERVED_0000 ||
1694 *data == ID_LED_RESERVED_FFFF)
1695 *data = ID_LED_DEFAULT;
1696 break;
1697 }
1698
1699 return 0;
1700 }
1701
1702 /**
1703 * e1000e_get_laa_state_82571 - Get locally administered address state
1704 * @hw: pointer to the HW structure
1705 *
1706 * Retrieve and return the current locally administered address state.
1707 **/
1708 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1709 {
1710 if (hw->mac.type != e1000_82571)
1711 return false;
1712
1713 return hw->dev_spec.e82571.laa_is_present;
1714 }
1715
1716 /**
1717 * e1000e_set_laa_state_82571 - Set locally administered address state
1718 * @hw: pointer to the HW structure
1719 * @state: enable/disable locally administered address
1720 *
1721 * Enable/Disable the current locally administered address state.
1722 **/
1723 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1724 {
1725 if (hw->mac.type != e1000_82571)
1726 return;
1727
1728 hw->dev_spec.e82571.laa_is_present = state;
1729
1730 /* If workaround is activated... */
1731 if (state)
1732 /* Hold a copy of the LAA in RAR[14] This is done so that
1733 * between the time RAR[0] gets clobbered and the time it
1734 * gets fixed, the actual LAA is in one of the RARs and no
1735 * incoming packets directed to this port are dropped.
1736 * Eventually the LAA will be in RAR[0] and RAR[14].
1737 */
1738 hw->mac.ops.rar_set(hw, hw->mac.addr,
1739 hw->mac.rar_entry_count - 1);
1740 }
1741
1742 /**
1743 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1744 * @hw: pointer to the HW structure
1745 *
1746 * Verifies that the EEPROM has completed the update. After updating the
1747 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1748 * the checksum fix is not implemented, we need to set the bit and update
1749 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1750 * we need to return bad checksum.
1751 **/
1752 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1753 {
1754 struct e1000_nvm_info *nvm = &hw->nvm;
1755 s32 ret_val;
1756 u16 data;
1757
1758 if (nvm->type != e1000_nvm_flash_hw)
1759 return 0;
1760
1761 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
1762 * 10h-12h. Checksum may need to be fixed.
1763 */
1764 ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1765 if (ret_val)
1766 return ret_val;
1767
1768 if (!(data & 0x10)) {
1769 /* Read 0x23 and check bit 15. This bit is a 1
1770 * when the checksum has already been fixed. If
1771 * the checksum is still wrong and this bit is a
1772 * 1, we need to return bad checksum. Otherwise,
1773 * we need to set this bit to a 1 and update the
1774 * checksum.
1775 */
1776 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1777 if (ret_val)
1778 return ret_val;
1779
1780 if (!(data & 0x8000)) {
1781 data |= 0x8000;
1782 ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1783 if (ret_val)
1784 return ret_val;
1785 ret_val = e1000e_update_nvm_checksum(hw);
1786 if (ret_val)
1787 return ret_val;
1788 }
1789 }
1790
1791 return 0;
1792 }
1793
1794 /**
1795 * e1000_read_mac_addr_82571 - Read device MAC address
1796 * @hw: pointer to the HW structure
1797 **/
1798 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1799 {
1800 if (hw->mac.type == e1000_82571) {
1801 s32 ret_val;
1802
1803 /* If there's an alternate MAC address place it in RAR0
1804 * so that it will override the Si installed default perm
1805 * address.
1806 */
1807 ret_val = e1000_check_alt_mac_addr_generic(hw);
1808 if (ret_val)
1809 return ret_val;
1810 }
1811
1812 return e1000_read_mac_addr_generic(hw);
1813 }
1814
1815 /**
1816 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1817 * @hw: pointer to the HW structure
1818 *
1819 * In the case of a PHY power down to save power, or to turn off link during a
1820 * driver unload, or wake on lan is not enabled, remove the link.
1821 **/
1822 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1823 {
1824 struct e1000_phy_info *phy = &hw->phy;
1825 struct e1000_mac_info *mac = &hw->mac;
1826
1827 if (!phy->ops.check_reset_block)
1828 return;
1829
1830 /* If the management interface is not enabled, then power down */
1831 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1832 e1000_power_down_phy_copper(hw);
1833 }
1834
1835 /**
1836 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1837 * @hw: pointer to the HW structure
1838 *
1839 * Clears the hardware counters by reading the counter registers.
1840 **/
1841 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1842 {
1843 e1000e_clear_hw_cntrs_base(hw);
1844
1845 er32(PRC64);
1846 er32(PRC127);
1847 er32(PRC255);
1848 er32(PRC511);
1849 er32(PRC1023);
1850 er32(PRC1522);
1851 er32(PTC64);
1852 er32(PTC127);
1853 er32(PTC255);
1854 er32(PTC511);
1855 er32(PTC1023);
1856 er32(PTC1522);
1857
1858 er32(ALGNERRC);
1859 er32(RXERRC);
1860 er32(TNCRS);
1861 er32(CEXTERR);
1862 er32(TSCTC);
1863 er32(TSCTFC);
1864
1865 er32(MGTPRC);
1866 er32(MGTPDC);
1867 er32(MGTPTC);
1868
1869 er32(IAC);
1870 er32(ICRXOC);
1871
1872 er32(ICRXPTC);
1873 er32(ICRXATC);
1874 er32(ICTXPTC);
1875 er32(ICTXATC);
1876 er32(ICTXQEC);
1877 er32(ICTXQMTC);
1878 er32(ICRXDMTC);
1879 }
1880
1881 static const struct e1000_mac_operations e82571_mac_ops = {
1882 /* .check_mng_mode: mac type dependent */
1883 /* .check_for_link: media type dependent */
1884 .id_led_init = e1000e_id_led_init_generic,
1885 .cleanup_led = e1000e_cleanup_led_generic,
1886 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571,
1887 .get_bus_info = e1000e_get_bus_info_pcie,
1888 .set_lan_id = e1000_set_lan_id_multi_port_pcie,
1889 /* .get_link_up_info: media type dependent */
1890 /* .led_on: mac type dependent */
1891 .led_off = e1000e_led_off_generic,
1892 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1893 .write_vfta = e1000_write_vfta_generic,
1894 .clear_vfta = e1000_clear_vfta_82571,
1895 .reset_hw = e1000_reset_hw_82571,
1896 .init_hw = e1000_init_hw_82571,
1897 .setup_link = e1000_setup_link_82571,
1898 /* .setup_physical_interface: media type dependent */
1899 .setup_led = e1000e_setup_led_generic,
1900 .config_collision_dist = e1000e_config_collision_dist_generic,
1901 .read_mac_addr = e1000_read_mac_addr_82571,
1902 .rar_set = e1000e_rar_set_generic,
1903 };
1904
1905 static const struct e1000_phy_operations e82_phy_ops_igp = {
1906 .acquire = e1000_get_hw_semaphore_82571,
1907 .check_polarity = e1000_check_polarity_igp,
1908 .check_reset_block = e1000e_check_reset_block_generic,
1909 .commit = NULL,
1910 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp,
1911 .get_cfg_done = e1000_get_cfg_done_82571,
1912 .get_cable_length = e1000e_get_cable_length_igp_2,
1913 .get_info = e1000e_get_phy_info_igp,
1914 .read_reg = e1000e_read_phy_reg_igp,
1915 .release = e1000_put_hw_semaphore_82571,
1916 .reset = e1000e_phy_hw_reset_generic,
1917 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1918 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1919 .write_reg = e1000e_write_phy_reg_igp,
1920 .cfg_on_link_up = NULL,
1921 };
1922
1923 static const struct e1000_phy_operations e82_phy_ops_m88 = {
1924 .acquire = e1000_get_hw_semaphore_82571,
1925 .check_polarity = e1000_check_polarity_m88,
1926 .check_reset_block = e1000e_check_reset_block_generic,
1927 .commit = e1000e_phy_sw_reset,
1928 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1929 .get_cfg_done = e1000e_get_cfg_done_generic,
1930 .get_cable_length = e1000e_get_cable_length_m88,
1931 .get_info = e1000e_get_phy_info_m88,
1932 .read_reg = e1000e_read_phy_reg_m88,
1933 .release = e1000_put_hw_semaphore_82571,
1934 .reset = e1000e_phy_hw_reset_generic,
1935 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1936 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1937 .write_reg = e1000e_write_phy_reg_m88,
1938 .cfg_on_link_up = NULL,
1939 };
1940
1941 static const struct e1000_phy_operations e82_phy_ops_bm = {
1942 .acquire = e1000_get_hw_semaphore_82571,
1943 .check_polarity = e1000_check_polarity_m88,
1944 .check_reset_block = e1000e_check_reset_block_generic,
1945 .commit = e1000e_phy_sw_reset,
1946 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1947 .get_cfg_done = e1000e_get_cfg_done_generic,
1948 .get_cable_length = e1000e_get_cable_length_m88,
1949 .get_info = e1000e_get_phy_info_m88,
1950 .read_reg = e1000e_read_phy_reg_bm2,
1951 .release = e1000_put_hw_semaphore_82571,
1952 .reset = e1000e_phy_hw_reset_generic,
1953 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1954 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1955 .write_reg = e1000e_write_phy_reg_bm2,
1956 .cfg_on_link_up = NULL,
1957 };
1958
1959 static const struct e1000_nvm_operations e82571_nvm_ops = {
1960 .acquire = e1000_acquire_nvm_82571,
1961 .read = e1000e_read_nvm_eerd,
1962 .release = e1000_release_nvm_82571,
1963 .reload = e1000e_reload_nvm_generic,
1964 .update = e1000_update_nvm_checksum_82571,
1965 .valid_led_default = e1000_valid_led_default_82571,
1966 .validate = e1000_validate_nvm_checksum_82571,
1967 .write = e1000_write_nvm_82571,
1968 };
1969
1970 const struct e1000_info e1000_82571_info = {
1971 .mac = e1000_82571,
1972 .flags = FLAG_HAS_HW_VLAN_FILTER
1973 | FLAG_HAS_JUMBO_FRAMES
1974 | FLAG_HAS_WOL
1975 | FLAG_APME_IN_CTRL3
1976 | FLAG_HAS_CTRLEXT_ON_LOAD
1977 | FLAG_HAS_SMART_POWER_DOWN
1978 | FLAG_RESET_OVERWRITES_LAA /* errata */
1979 | FLAG_TARC_SPEED_MODE_BIT /* errata */
1980 | FLAG_APME_CHECK_PORT_B,
1981 .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
1982 | FLAG2_DMA_BURST,
1983 .pba = 38,
1984 .max_hw_frame_size = DEFAULT_JUMBO,
1985 .get_variants = e1000_get_variants_82571,
1986 .mac_ops = &e82571_mac_ops,
1987 .phy_ops = &e82_phy_ops_igp,
1988 .nvm_ops = &e82571_nvm_ops,
1989 };
1990
1991 const struct e1000_info e1000_82572_info = {
1992 .mac = e1000_82572,
1993 .flags = FLAG_HAS_HW_VLAN_FILTER
1994 | FLAG_HAS_JUMBO_FRAMES
1995 | FLAG_HAS_WOL
1996 | FLAG_APME_IN_CTRL3
1997 | FLAG_HAS_CTRLEXT_ON_LOAD
1998 | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1999 .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
2000 | FLAG2_DMA_BURST,
2001 .pba = 38,
2002 .max_hw_frame_size = DEFAULT_JUMBO,
2003 .get_variants = e1000_get_variants_82571,
2004 .mac_ops = &e82571_mac_ops,
2005 .phy_ops = &e82_phy_ops_igp,
2006 .nvm_ops = &e82571_nvm_ops,
2007 };
2008
2009 const struct e1000_info e1000_82573_info = {
2010 .mac = e1000_82573,
2011 .flags = FLAG_HAS_HW_VLAN_FILTER
2012 | FLAG_HAS_WOL
2013 | FLAG_APME_IN_CTRL3
2014 | FLAG_HAS_SMART_POWER_DOWN
2015 | FLAG_HAS_AMT
2016 | FLAG_HAS_SWSM_ON_LOAD,
2017 .flags2 = FLAG2_DISABLE_ASPM_L1
2018 | FLAG2_DISABLE_ASPM_L0S,
2019 .pba = 20,
2020 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
2021 .get_variants = e1000_get_variants_82571,
2022 .mac_ops = &e82571_mac_ops,
2023 .phy_ops = &e82_phy_ops_m88,
2024 .nvm_ops = &e82571_nvm_ops,
2025 };
2026
2027 const struct e1000_info e1000_82574_info = {
2028 .mac = e1000_82574,
2029 .flags = FLAG_HAS_HW_VLAN_FILTER
2030 | FLAG_HAS_MSIX
2031 | FLAG_HAS_JUMBO_FRAMES
2032 | FLAG_HAS_WOL
2033 | FLAG_HAS_HW_TIMESTAMP
2034 | FLAG_APME_IN_CTRL3
2035 | FLAG_HAS_SMART_POWER_DOWN
2036 | FLAG_HAS_AMT
2037 | FLAG_HAS_CTRLEXT_ON_LOAD,
2038 .flags2 = FLAG2_CHECK_PHY_HANG
2039 | FLAG2_DISABLE_ASPM_L0S
2040 | FLAG2_DISABLE_ASPM_L1
2041 | FLAG2_NO_DISABLE_RX
2042 | FLAG2_DMA_BURST,
2043 .pba = 32,
2044 .max_hw_frame_size = DEFAULT_JUMBO,
2045 .get_variants = e1000_get_variants_82571,
2046 .mac_ops = &e82571_mac_ops,
2047 .phy_ops = &e82_phy_ops_bm,
2048 .nvm_ops = &e82571_nvm_ops,
2049 };
2050
2051 const struct e1000_info e1000_82583_info = {
2052 .mac = e1000_82583,
2053 .flags = FLAG_HAS_HW_VLAN_FILTER
2054 | FLAG_HAS_WOL
2055 | FLAG_HAS_HW_TIMESTAMP
2056 | FLAG_APME_IN_CTRL3
2057 | FLAG_HAS_SMART_POWER_DOWN
2058 | FLAG_HAS_AMT
2059 | FLAG_HAS_JUMBO_FRAMES
2060 | FLAG_HAS_CTRLEXT_ON_LOAD,
2061 .flags2 = FLAG2_DISABLE_ASPM_L0S
2062 | FLAG2_NO_DISABLE_RX,
2063 .pba = 32,
2064 .max_hw_frame_size = DEFAULT_JUMBO,
2065 .get_variants = e1000_get_variants_82571,
2066 .mac_ops = &e82571_mac_ops,
2067 .phy_ops = &e82_phy_ops_bm,
2068 .nvm_ops = &e82571_nvm_ops,
2069 };
Linux kernel - Deliverables
This page took 0.079491 seconds and 5 git commands to generate.