drivers/net/ethernet/intel/e1000e/e1000.h

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /* Linux PRO/1000 Ethernet Driver main header file */
  30
  31 #ifndef _E1000_H_
  32 #define _E1000_H_
  33
  34 #include <linux/bitops.h>
  35 #include <linux/types.h>
  36 #include <linux/timer.h>
  37 #include <linux/workqueue.h>
  38 #include <linux/io.h>
  39 #include <linux/netdevice.h>
  40 #include <linux/pci.h>
  41 #include <linux/pci-aspm.h>
  42 #include <linux/crc32.h>
  43 #include <linux/if_vlan.h>
  44 #include <linux/clocksource.h>
  45 #include <linux/net_tstamp.h>
  46 #include <linux/ptp_clock_kernel.h>
  47 #include <linux/ptp_classify.h>
  48 #include <linux/mii.h>
  49 #include "hw.h"
  50
  51 struct e1000_info;
  52
  53 #define e_dbg(format, arg...) \
  54         netdev_dbg(hw->adapter->netdev, format, ## arg)
  55 #define e_err(format, arg...) \
  56         netdev_err(adapter->netdev, format, ## arg)
  57 #define e_info(format, arg...) \
  58         netdev_info(adapter->netdev, format, ## arg)
  59 #define e_warn(format, arg...) \
  60         netdev_warn(adapter->netdev, format, ## arg)
  61 #define e_notice(format, arg...) \
  62         netdev_notice(adapter->netdev, format, ## arg)
  63
  64
  65 /* Interrupt modes, as used by the IntMode parameter */
  66 #define E1000E_INT_MODE_LEGACY          0
  67 #define E1000E_INT_MODE_MSI             1
  68 #define E1000E_INT_MODE_MSIX            2
  69
  70 /* Tx/Rx descriptor defines */
  71 #define E1000_DEFAULT_TXD               256
  72 #define E1000_MAX_TXD                   4096
  73 #define E1000_MIN_TXD                   64
  74
  75 #define E1000_DEFAULT_RXD               256
  76 #define E1000_MAX_RXD                   4096
  77 #define E1000_MIN_RXD                   64
  78
  79 #define E1000_MIN_ITR_USECS             10 /* 100000 irq/sec */
  80 #define E1000_MAX_ITR_USECS             10000 /* 100    irq/sec */
  81
  82 #define E1000_FC_PAUSE_TIME             0x0680 /* 858 usec */
  83
  84 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
  85 /* How many Rx Buffers do we bundle into one write to the hardware ? */
  86 #define E1000_RX_BUFFER_WRITE           16 /* Must be power of 2 */
  87
  88 #define AUTO_ALL_MODES                  0
  89 #define E1000_EEPROM_APME               0x0400
  90
  91 #define E1000_MNG_VLAN_NONE             (-1)
  92
  93 /* Number of packet split data buffers (not including the header buffer) */
  94 #define PS_PAGE_BUFFERS                 (MAX_PS_BUFFERS - 1)
  95
  96 #define DEFAULT_JUMBO                   9234
  97
  98 /* BM/HV Specific Registers */
  99 #define BM_PORT_CTRL_PAGE                 769
 100
 101 #define PHY_UPPER_SHIFT                   21
 102 #define BM_PHY_REG(page, reg) \
 103         (((reg) & MAX_PHY_REG_ADDRESS) |\
 104          (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
 105          (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
 106
 107 /* BM PHY Copper Specific Status */
 108 #define BM_CS_STATUS                      17
 109 #define BM_CS_STATUS_LINK_UP              0x0400
 110 #define BM_CS_STATUS_RESOLVED             0x0800
 111 #define BM_CS_STATUS_SPEED_MASK           0xC000
 112 #define BM_CS_STATUS_SPEED_1000           0x8000
 113
 114 /* 82577 Mobile Phy Status Register */
 115 #define HV_M_STATUS                       26
 116 #define HV_M_STATUS_AUTONEG_COMPLETE      0x1000
 117 #define HV_M_STATUS_SPEED_MASK            0x0300
 118 #define HV_M_STATUS_SPEED_1000            0x0200
 119 #define HV_M_STATUS_LINK_UP               0x0040
 120
 121 /* Time to wait before putting the device into D3 if there's no link (in ms). */
 122 #define LINK_TIMEOUT            100
 123
 124 /* Count for polling __E1000_RESET condition every 10-20msec.
 125  * Experimentation has shown the reset can take approximately 210msec.
 126  */
 127 #define E1000_CHECK_RESET_COUNT         25
 128
 129 #define DEFAULT_RDTR                    0
 130 #define DEFAULT_RADV                    8
 131 #define BURST_RDTR                      0x20
 132 #define BURST_RADV                      0x20
 133
 134 /* in the case of WTHRESH, it appears at least the 82571/2 hardware
 135  * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
 136  * WTHRESH=4, so a setting of 5 gives the most efficient bus
 137  * utilization but to avoid possible Tx stalls, set it to 1
 138  */
 139 #define E1000_TXDCTL_DMA_BURST_ENABLE                          \
 140         (E1000_TXDCTL_GRAN | /* set descriptor granularity */  \
 141          E1000_TXDCTL_COUNT_DESC |                             \
 142          (1 << 16) | /* wthresh must be +1 more than desired */\
 143          (1 << 8)  | /* hthresh */                             \
 144          0x1f)       /* pthresh */
 145
 146 #define E1000_RXDCTL_DMA_BURST_ENABLE                          \
 147         (0x01000000 | /* set descriptor granularity */         \
 148          (4 << 16)  | /* set writeback threshold    */         \
 149          (4 << 8)   | /* set prefetch threshold     */         \
 150          0x20)        /* set hthresh                */
 151
 152 #define E1000_TIDV_FPD (1 << 31)
 153 #define E1000_RDTR_FPD (1 << 31)
 154
 155 enum e1000_boards {
 156         board_82571,
 157         board_82572,
 158         board_82573,
 159         board_82574,
 160         board_82583,
 161         board_80003es2lan,
 162         board_ich8lan,
 163         board_ich9lan,
 164         board_ich10lan,
 165         board_pchlan,
 166         board_pch2lan,
 167         board_pch_lpt,
 168 };
 169
 170 struct e1000_ps_page {
 171         struct page *page;
 172         u64 dma; /* must be u64 - written to hw */
 173 };
 174
 175 /* wrappers around a pointer to a socket buffer,
 176  * so a DMA handle can be stored along with the buffer
 177  */
 178 struct e1000_buffer {
 179         dma_addr_t dma;
 180         struct sk_buff *skb;
 181         union {
 182                 /* Tx */
 183                 struct {
 184                         unsigned long time_stamp;
 185                         u16 length;
 186                         u16 next_to_watch;
 187                         unsigned int segs;
 188                         unsigned int bytecount;
 189                         u16 mapped_as_page;
 190                 };
 191                 /* Rx */
 192                 struct {
 193                         /* arrays of page information for packet split */
 194                         struct e1000_ps_page *ps_pages;
 195                         struct page *page;
 196                 };
 197         };
 198 };
 199
 200 struct e1000_ring {
 201         struct e1000_adapter *adapter;  /* back pointer to adapter */
 202         void *desc;                     /* pointer to ring memory  */
 203         dma_addr_t dma;                 /* phys address of ring    */
 204         unsigned int size;              /* length of ring in bytes */
 205         unsigned int count;             /* number of desc. in ring */
 206
 207         u16 next_to_use;
 208         u16 next_to_clean;
 209
 210         void __iomem *head;
 211         void __iomem *tail;
 212
 213         /* array of buffer information structs */
 214         struct e1000_buffer *buffer_info;
 215
 216         char name[IFNAMSIZ + 5];
 217         u32 ims_val;
 218         u32 itr_val;
 219         void __iomem *itr_register;
 220         int set_itr;
 221
 222         struct sk_buff *rx_skb_top;
 223 };
 224
 225 /* PHY register snapshot values */
 226 struct e1000_phy_regs {
 227         u16 bmcr;               /* basic mode control register    */
 228         u16 bmsr;               /* basic mode status register     */
 229         u16 advertise;          /* auto-negotiation advertisement */
 230         u16 lpa;                /* link partner ability register  */
 231         u16 expansion;          /* auto-negotiation expansion reg */
 232         u16 ctrl1000;           /* 1000BASE-T control register    */
 233         u16 stat1000;           /* 1000BASE-T status register     */
 234         u16 estatus;            /* extended status register       */
 235 };
 236
 237 /* board specific private data structure */
 238 struct e1000_adapter {
 239         struct timer_list watchdog_timer;
 240         struct timer_list phy_info_timer;
 241         struct timer_list blink_timer;
 242
 243         struct work_struct reset_task;
 244         struct work_struct watchdog_task;
 245
 246         const struct e1000_info *ei;
 247
 248         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 249         u32 bd_number;
 250         u32 rx_buffer_len;
 251         u16 mng_vlan_id;
 252         u16 link_speed;
 253         u16 link_duplex;
 254         u16 eeprom_vers;
 255
 256         /* track device up/down/testing state */
 257         unsigned long state;
 258
 259         /* Interrupt Throttle Rate */
 260         u32 itr;
 261         u32 itr_setting;
 262         u16 tx_itr;
 263         u16 rx_itr;
 264
 265         /* Tx */
 266         struct e1000_ring *tx_ring /* One per active queue */
 267                                                 ____cacheline_aligned_in_smp;
 268         u32 tx_fifo_limit;
 269
 270         struct napi_struct napi;
 271
 272         unsigned int uncorr_errors;     /* uncorrectable ECC errors */
 273         unsigned int corr_errors;       /* correctable ECC errors */
 274         unsigned int restart_queue;
 275         u32 txd_cmd;
 276
 277         bool detect_tx_hung;
 278         bool tx_hang_recheck;
 279         u8 tx_timeout_factor;
 280
 281         u32 tx_int_delay;
 282         u32 tx_abs_int_delay;
 283
 284         unsigned int total_tx_bytes;
 285         unsigned int total_tx_packets;
 286         unsigned int total_rx_bytes;
 287         unsigned int total_rx_packets;
 288
 289         /* Tx stats */
 290         u64 tpt_old;
 291         u64 colc_old;
 292         u32 gotc;
 293         u64 gotc_old;
 294         u32 tx_timeout_count;
 295         u32 tx_fifo_head;
 296         u32 tx_head_addr;
 297         u32 tx_fifo_size;
 298         u32 tx_dma_failed;
 299
 300         /* Rx */
 301         bool (*clean_rx) (struct e1000_ring *ring, int *work_done,
 302                           int work_to_do) ____cacheline_aligned_in_smp;
 303         void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count,
 304                               gfp_t gfp);
 305         struct e1000_ring *rx_ring;
 306
 307         u32 rx_int_delay;
 308         u32 rx_abs_int_delay;
 309
 310         /* Rx stats */
 311         u64 hw_csum_err;
 312         u64 hw_csum_good;
 313         u64 rx_hdr_split;
 314         u32 gorc;
 315         u64 gorc_old;
 316         u32 alloc_rx_buff_failed;
 317         u32 rx_dma_failed;
 318         u32 rx_hwtstamp_cleared;
 319
 320         unsigned int rx_ps_pages;
 321         u16 rx_ps_bsize0;
 322         u32 max_frame_size;
 323         u32 min_frame_size;
 324
 325         /* OS defined structs */
 326         struct net_device *netdev;
 327         struct pci_dev *pdev;
 328
 329         /* structs defined in e1000_hw.h */
 330         struct e1000_hw hw;
 331
 332         spinlock_t stats64_lock;        /* protects statistics counters */
 333         struct e1000_hw_stats stats;
 334         struct e1000_phy_info phy_info;
 335         struct e1000_phy_stats phy_stats;
 336
 337         /* Snapshot of PHY registers */
 338         struct e1000_phy_regs phy_regs;
 339
 340         struct e1000_ring test_tx_ring;
 341         struct e1000_ring test_rx_ring;
 342         u32 test_icr;
 343
 344         u32 msg_enable;
 345         unsigned int num_vectors;
 346         struct msix_entry *msix_entries;
 347         int int_mode;
 348         u32 eiac_mask;
 349
 350         u32 eeprom_wol;
 351         u32 wol;
 352         u32 pba;
 353         u32 max_hw_frame_size;
 354
 355         bool fc_autoneg;
 356
 357         unsigned int flags;
 358         unsigned int flags2;
 359         struct work_struct downshift_task;
 360         struct work_struct update_phy_task;
 361         struct work_struct print_hang_task;
 362
 363         bool idle_check;
 364         int phy_hang_count;
 365
 366         u16 tx_ring_count;
 367         u16 rx_ring_count;
 368
 369         struct hwtstamp_config hwtstamp_config;
 370         struct delayed_work systim_overflow_work;
 371         struct sk_buff *tx_hwtstamp_skb;
 372         struct work_struct tx_hwtstamp_work;
 373         spinlock_t systim_lock; /* protects SYSTIML/H regsters */
 374         struct cyclecounter cc;
 375         struct timecounter tc;
 376         struct ptp_clock *ptp_clock;
 377         struct ptp_clock_info ptp_clock_info;
 378 };
 379
 380 struct e1000_info {
 381         enum e1000_mac_type     mac;
 382         unsigned int            flags;
 383         unsigned int            flags2;
 384         u32                     pba;
 385         u32                     max_hw_frame_size;
 386         s32                     (*get_variants)(struct e1000_adapter *);
 387         const struct e1000_mac_operations *mac_ops;
 388         const struct e1000_phy_operations *phy_ops;
 389         const struct e1000_nvm_operations *nvm_ops;
 390 };
 391
 392 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);
 393
 394 /* The system time is maintained by a 64-bit counter comprised of the 32-bit
 395  * SYSTIMH and SYSTIML registers.  How the counter increments (and therefore
 396  * its resolution) is based on the contents of the TIMINCA register - it
 397  * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
 398  * For the best accuracy, the incperiod should be as small as possible.  The
 399  * incvalue is scaled by a factor as large as possible (while still fitting
 400  * in bits 23:0) so that relatively small clock corrections can be made.
 401  *
 402  * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
 403  * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
 404  * bits to count nanoseconds leaving the rest for fractional nonseconds.
 405  */
 406 #define INCVALUE_96MHz          125
 407 #define INCVALUE_SHIFT_96MHz    17
 408 #define INCPERIOD_SHIFT_96MHz   2
 409 #define INCPERIOD_96MHz         (12 >> INCPERIOD_SHIFT_96MHz)
 410
 411 #define INCVALUE_25MHz          40
 412 #define INCVALUE_SHIFT_25MHz    18
 413 #define INCPERIOD_25MHz         1
 414
 415 /* Another drawback of scaling the incvalue by a large factor is the
 416  * 64-bit SYSTIM register overflows more quickly.  This is dealt with
 417  * by simply reading the clock before it overflows.
 418  *
 419  * Clock        ns bits Overflows after
 420  * ~~~~~~       ~~~~~~~ ~~~~~~~~~~~~~~~
 421  * 96MHz        47-bit  2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
 422  * 25MHz        46-bit  2^46 / 10^9 / 3600 = 19.55 hours
 423  */
 424 #define E1000_SYSTIM_OVERFLOW_PERIOD    (HZ * 60 * 60 * 4)
 425
 426 /* hardware capability, feature, and workaround flags */
 427 #define FLAG_HAS_AMT                      (1 << 0)
 428 #define FLAG_HAS_FLASH                    (1 << 1)
 429 #define FLAG_HAS_HW_VLAN_FILTER           (1 << 2)
 430 #define FLAG_HAS_WOL                      (1 << 3)
 431 /* reserved bit4 */
 432 #define FLAG_HAS_CTRLEXT_ON_LOAD          (1 << 5)
 433 #define FLAG_HAS_SWSM_ON_LOAD             (1 << 6)
 434 #define FLAG_HAS_JUMBO_FRAMES             (1 << 7)
 435 #define FLAG_READ_ONLY_NVM                (1 << 8)
 436 #define FLAG_IS_ICH                       (1 << 9)
 437 #define FLAG_HAS_MSIX                     (1 << 10)
 438 #define FLAG_HAS_SMART_POWER_DOWN         (1 << 11)
 439 #define FLAG_IS_QUAD_PORT_A               (1 << 12)
 440 #define FLAG_IS_QUAD_PORT                 (1 << 13)
 441 #define FLAG_HAS_HW_TIMESTAMP             (1 << 14)
 442 #define FLAG_APME_IN_WUC                  (1 << 15)
 443 #define FLAG_APME_IN_CTRL3                (1 << 16)
 444 #define FLAG_APME_CHECK_PORT_B            (1 << 17)
 445 #define FLAG_DISABLE_FC_PAUSE_TIME        (1 << 18)
 446 #define FLAG_NO_WAKE_UCAST                (1 << 19)
 447 #define FLAG_MNG_PT_ENABLED               (1 << 20)
 448 #define FLAG_RESET_OVERWRITES_LAA         (1 << 21)
 449 #define FLAG_TARC_SPEED_MODE_BIT          (1 << 22)
 450 #define FLAG_TARC_SET_BIT_ZERO            (1 << 23)
 451 #define FLAG_RX_NEEDS_RESTART             (1 << 24)
 452 #define FLAG_LSC_GIG_SPEED_DROP           (1 << 25)
 453 #define FLAG_SMART_POWER_DOWN             (1 << 26)
 454 #define FLAG_MSI_ENABLED                  (1 << 27)
 455 /* reserved (1 << 28) */
 456 #define FLAG_TSO_FORCE                    (1 << 29)
 457 #define FLAG_RESTART_NOW                  (1 << 30)
 458 #define FLAG_MSI_TEST_FAILED              (1 << 31)
 459
 460 #define FLAG2_CRC_STRIPPING               (1 << 0)
 461 #define FLAG2_HAS_PHY_WAKEUP              (1 << 1)
 462 #define FLAG2_IS_DISCARDING               (1 << 2)
 463 #define FLAG2_DISABLE_ASPM_L1             (1 << 3)
 464 #define FLAG2_HAS_PHY_STATS               (1 << 4)
 465 #define FLAG2_HAS_EEE                     (1 << 5)
 466 #define FLAG2_DMA_BURST                   (1 << 6)
 467 #define FLAG2_DISABLE_ASPM_L0S            (1 << 7)
 468 #define FLAG2_DISABLE_AIM                 (1 << 8)
 469 #define FLAG2_CHECK_PHY_HANG              (1 << 9)
 470 #define FLAG2_NO_DISABLE_RX               (1 << 10)
 471 #define FLAG2_PCIM2PCI_ARBITER_WA         (1 << 11)
 472 #define FLAG2_DFLT_CRC_STRIPPING          (1 << 12)
 473 #define FLAG2_CHECK_RX_HWTSTAMP           (1 << 13)
 474
 475 #define E1000_RX_DESC_PS(R, i)      \
 476         (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
 477 #define E1000_RX_DESC_EXT(R, i)     \
 478         (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
 479 #define E1000_GET_DESC(R, i, type)      (&(((struct type *)((R).desc))[i]))
 480 #define E1000_TX_DESC(R, i)             E1000_GET_DESC(R, i, e1000_tx_desc)
 481 #define E1000_CONTEXT_DESC(R, i)        E1000_GET_DESC(R, i, e1000_context_desc)
 482
 483 enum e1000_state_t {
 484         __E1000_TESTING,
 485         __E1000_RESETTING,
 486         __E1000_ACCESS_SHARED_RESOURCE,
 487         __E1000_DOWN
 488 };
 489
 490 enum latency_range {
 491         lowest_latency = 0,
 492         low_latency = 1,
 493         bulk_latency = 2,
 494         latency_invalid = 255
 495 };
 496
 497 extern char e1000e_driver_name[];
 498 extern const char e1000e_driver_version[];
 499
 500 extern void e1000e_check_options(struct e1000_adapter *adapter);
 501 extern void e1000e_set_ethtool_ops(struct net_device *netdev);
 502
 503 extern int e1000e_up(struct e1000_adapter *adapter);
 504 extern void e1000e_down(struct e1000_adapter *adapter);
 505 extern void e1000e_reinit_locked(struct e1000_adapter *adapter);
 506 extern void e1000e_reset(struct e1000_adapter *adapter);
 507 extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
 508 extern int e1000e_setup_rx_resources(struct e1000_ring *ring);
 509 extern int e1000e_setup_tx_resources(struct e1000_ring *ring);
 510 extern void e1000e_free_rx_resources(struct e1000_ring *ring);
 511 extern void e1000e_free_tx_resources(struct e1000_ring *ring);
 512 extern struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
 513                                                     struct rtnl_link_stats64
 514                                                     *stats);
 515 extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
 516 extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
 517 extern void e1000e_get_hw_control(struct e1000_adapter *adapter);
 518 extern void e1000e_release_hw_control(struct e1000_adapter *adapter);
 519 extern void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
 520
 521 extern unsigned int copybreak;
 522
 523 extern const struct e1000_info e1000_82571_info;
 524 extern const struct e1000_info e1000_82572_info;
 525 extern const struct e1000_info e1000_82573_info;
 526 extern const struct e1000_info e1000_82574_info;
 527 extern const struct e1000_info e1000_82583_info;
 528 extern const struct e1000_info e1000_ich8_info;
 529 extern const struct e1000_info e1000_ich9_info;
 530 extern const struct e1000_info e1000_ich10_info;
 531 extern const struct e1000_info e1000_pch_info;
 532 extern const struct e1000_info e1000_pch2_info;
 533 extern const struct e1000_info e1000_pch_lpt_info;
 534 extern const struct e1000_info e1000_es2_info;
 535
 536 extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
 537                                          u32 pba_num_size);
 538
 539 extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
 540
 541 extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
 542 extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
 543 extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
 544 extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
 545 extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
 546 extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
 547 extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
 548 extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
 549 extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
 550 extern s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
 551 extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
 552 extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
 553                                           u16 *data);
 554 extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
 555 extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
 556 extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
 557 extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
 558                                            u16 data);
 559 extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
 560 extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
 561 extern s32 e1000e_get_cfg_done_generic(struct e1000_hw *hw);
 562 extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
 563 extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
 564 extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
 565 extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
 566 extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
 567 extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
 568 extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
 569 extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
 570 extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
 571 extern s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
 572                                                  u16 *phy_reg);
 573 extern s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
 574                                                   u16 *phy_reg);
 575 extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
 576 extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
 577 extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
 578 extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
 579 extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
 580                                         u16 data);
 581 extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
 582 extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
 583                                        u16 *data);
 584 extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
 585                                u32 usec_interval, bool *success);
 586 extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
 587 extern void e1000_power_up_phy_copper(struct e1000_hw *hw);
 588 extern void e1000_power_down_phy_copper(struct e1000_hw *hw);
 589 extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
 590 extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
 591 extern s32 e1000e_check_downshift(struct e1000_hw *hw);
 592 extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
 593 extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
 594                                         u16 *data);
 595 extern s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
 596                                       u16 *data);
 597 extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
 598 extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
 599                                          u16 data);
 600 extern s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
 601                                        u16 data);
 602 extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
 603 extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
 604 extern s32 e1000_check_polarity_82577(struct e1000_hw *hw);
 605 extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
 606 extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
 607 extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
 608
 609 extern s32 e1000_check_polarity_m88(struct e1000_hw *hw);
 610 extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
 611 extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
 612 extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
 613 extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
 614 extern void e1000e_ptp_init(struct e1000_adapter *adapter);
 615 extern void e1000e_ptp_remove(struct e1000_adapter *adapter);
 616
 617 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
 618 {
 619         return hw->phy.ops.reset(hw);
 620 }
 621
 622 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
 623 {
 624         return hw->phy.ops.read_reg(hw, offset, data);
 625 }
 626
 627 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
 628 {
 629         return hw->phy.ops.read_reg_locked(hw, offset, data);
 630 }
 631
 632 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
 633 {
 634         return hw->phy.ops.write_reg(hw, offset, data);
 635 }
 636
 637 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
 638 {
 639         return hw->phy.ops.write_reg_locked(hw, offset, data);
 640 }
 641
 642 extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
 643 extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
 644 extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
 645 extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
 646 extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
 647 extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
 648 extern void e1000e_release_nvm(struct e1000_hw *hw);
 649 extern void e1000e_reload_nvm_generic(struct e1000_hw *hw);
 650 extern s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
 651
 652 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
 653 {
 654         if (hw->mac.ops.read_mac_addr)
 655                 return hw->mac.ops.read_mac_addr(hw);
 656
 657         return e1000_read_mac_addr_generic(hw);
 658 }
 659
 660 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
 661 {
 662         return hw->nvm.ops.validate(hw);
 663 }
 664
 665 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
 666 {
 667         return hw->nvm.ops.update(hw);
 668 }
 669
 670 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 671 {
 672         return hw->nvm.ops.read(hw, offset, words, data);
 673 }
 674
 675 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 676 {
 677         return hw->nvm.ops.write(hw, offset, words, data);
 678 }
 679
 680 static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
 681 {
 682         return hw->phy.ops.get_info(hw);
 683 }
 684
 685 extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
 686 extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
 687 extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
 688
 689 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
 690 {
 691         return readl(hw->hw_addr + reg);
 692 }
 693
 694 #define er32(reg)       __er32(hw, E1000_##reg)
 695
 696 /**
 697  * __ew32_prepare - prepare to write to MAC CSR register on certain parts
 698  * @hw: pointer to the HW structure
 699  *
 700  * When updating the MAC CSR registers, the Manageability Engine (ME) could
 701  * be accessing the registers at the same time.  Normally, this is handled in
 702  * h/w by an arbiter but on some parts there is a bug that acknowledges Host
 703  * accesses later than it should which could result in the register to have
 704  * an incorrect value.  Workaround this by checking the FWSM register which
 705  * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
 706  * and try again a number of times.
 707  **/
 708 static inline s32 __ew32_prepare(struct e1000_hw *hw)
 709 {
 710         s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
 711
 712         while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
 713                 udelay(50);
 714
 715         return i;
 716 }
 717
 718 static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
 719 {
 720         if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
 721                 __ew32_prepare(hw);
 722
 723         writel(val, hw->hw_addr + reg);
 724 }
 725
 726 #define ew32(reg, val)  __ew32(hw, E1000_##reg, (val))
 727
 728 #define e1e_flush()     er32(STATUS)
 729
 730 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
 731         (__ew32((a), (reg + ((offset) << 2)), (value)))
 732
 733 #define E1000_READ_REG_ARRAY(a, reg, offset) \
 734         (readl((a)->hw_addr + reg + ((offset) << 2)))
 735
 736 #endif /* _E1000_H_ */