1 /* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2014 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 /* Linux PRO/1000 Ethernet Driver main header file */
27 #include <linux/bitops.h>
28 #include <linux/types.h>
29 #include <linux/timer.h>
30 #include <linux/workqueue.h>
32 #include <linux/netdevice.h>
33 #include <linux/pci.h>
34 #include <linux/pci-aspm.h>
35 #include <linux/crc32.h>
36 #include <linux/if_vlan.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/ptp_classify.h>
41 #include <linux/mii.h>
42 #include <linux/mdio.h>
47 #define e_dbg(format, arg...) \
48 netdev_dbg(hw->adapter->netdev, format, ## arg)
49 #define e_err(format, arg...) \
50 netdev_err(adapter->netdev, format, ## arg)
51 #define e_info(format, arg...) \
52 netdev_info(adapter->netdev, format, ## arg)
53 #define e_warn(format, arg...) \
54 netdev_warn(adapter->netdev, format, ## arg)
55 #define e_notice(format, arg...) \
56 netdev_notice(adapter->netdev, format, ## arg)
58 /* Interrupt modes, as used by the IntMode parameter */
59 #define E1000E_INT_MODE_LEGACY 0
60 #define E1000E_INT_MODE_MSI 1
61 #define E1000E_INT_MODE_MSIX 2
63 /* Tx/Rx descriptor defines */
64 #define E1000_DEFAULT_TXD 256
65 #define E1000_MAX_TXD 4096
66 #define E1000_MIN_TXD 64
68 #define E1000_DEFAULT_RXD 256
69 #define E1000_MAX_RXD 4096
70 #define E1000_MIN_RXD 64
72 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
73 #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
75 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
77 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
78 /* How many Rx Buffers do we bundle into one write to the hardware ? */
79 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
81 #define AUTO_ALL_MODES 0
82 #define E1000_EEPROM_APME 0x0400
84 #define E1000_MNG_VLAN_NONE (-1)
86 #define DEFAULT_JUMBO 9234
88 /* Time to wait before putting the device into D3 if there's no link (in ms). */
89 #define LINK_TIMEOUT 100
91 /* Count for polling __E1000_RESET condition every 10-20msec.
92 * Experimentation has shown the reset can take approximately 210msec.
94 #define E1000_CHECK_RESET_COUNT 25
96 #define DEFAULT_RDTR 0
97 #define DEFAULT_RADV 8
98 #define BURST_RDTR 0x20
99 #define BURST_RADV 0x20
101 /* in the case of WTHRESH, it appears at least the 82571/2 hardware
102 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
103 * WTHRESH=4, so a setting of 5 gives the most efficient bus
104 * utilization but to avoid possible Tx stalls, set it to 1
106 #define E1000_TXDCTL_DMA_BURST_ENABLE \
107 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
108 E1000_TXDCTL_COUNT_DESC | \
109 (1 << 16) | /* wthresh must be +1 more than desired */\
110 (1 << 8) | /* hthresh */ \
113 #define E1000_RXDCTL_DMA_BURST_ENABLE \
114 (0x01000000 | /* set descriptor granularity */ \
115 (4 << 16) | /* set writeback threshold */ \
116 (4 << 8) | /* set prefetch threshold */ \
117 0x20) /* set hthresh */
119 #define E1000_TIDV_FPD (1 << 31)
120 #define E1000_RDTR_FPD (1 << 31)
138 struct e1000_ps_page
{
140 u64 dma
; /* must be u64 - written to hw */
143 /* wrappers around a pointer to a socket buffer,
144 * so a DMA handle can be stored along with the buffer
146 struct e1000_buffer
{
152 unsigned long time_stamp
;
156 unsigned int bytecount
;
161 /* arrays of page information for packet split */
162 struct e1000_ps_page
*ps_pages
;
169 struct e1000_adapter
*adapter
; /* back pointer to adapter */
170 void *desc
; /* pointer to ring memory */
171 dma_addr_t dma
; /* phys address of ring */
172 unsigned int size
; /* length of ring in bytes */
173 unsigned int count
; /* number of desc. in ring */
181 /* array of buffer information structs */
182 struct e1000_buffer
*buffer_info
;
184 char name
[IFNAMSIZ
+ 5];
187 void __iomem
*itr_register
;
190 struct sk_buff
*rx_skb_top
;
193 /* PHY register snapshot values */
194 struct e1000_phy_regs
{
195 u16 bmcr
; /* basic mode control register */
196 u16 bmsr
; /* basic mode status register */
197 u16 advertise
; /* auto-negotiation advertisement */
198 u16 lpa
; /* link partner ability register */
199 u16 expansion
; /* auto-negotiation expansion reg */
200 u16 ctrl1000
; /* 1000BASE-T control register */
201 u16 stat1000
; /* 1000BASE-T status register */
202 u16 estatus
; /* extended status register */
205 /* board specific private data structure */
206 struct e1000_adapter
{
207 struct timer_list watchdog_timer
;
208 struct timer_list phy_info_timer
;
209 struct timer_list blink_timer
;
211 struct work_struct reset_task
;
212 struct work_struct watchdog_task
;
214 const struct e1000_info
*ei
;
216 unsigned long active_vlans
[BITS_TO_LONGS(VLAN_N_VID
)];
224 /* track device up/down/testing state */
227 /* Interrupt Throttle Rate */
233 /* Tx - one ring per active queue */
234 struct e1000_ring
*tx_ring ____cacheline_aligned_in_smp
;
237 struct napi_struct napi
;
239 unsigned int uncorr_errors
; /* uncorrectable ECC errors */
240 unsigned int corr_errors
; /* correctable ECC errors */
241 unsigned int restart_queue
;
245 bool tx_hang_recheck
;
246 u8 tx_timeout_factor
;
249 u32 tx_abs_int_delay
;
251 unsigned int total_tx_bytes
;
252 unsigned int total_tx_packets
;
253 unsigned int total_rx_bytes
;
254 unsigned int total_rx_packets
;
261 u32 tx_timeout_count
;
266 u32 tx_hwtstamp_timeouts
;
269 bool (*clean_rx
)(struct e1000_ring
*ring
, int *work_done
,
270 int work_to_do
) ____cacheline_aligned_in_smp
;
271 void (*alloc_rx_buf
)(struct e1000_ring
*ring
, int cleaned_count
,
273 struct e1000_ring
*rx_ring
;
276 u32 rx_abs_int_delay
;
284 u32 alloc_rx_buff_failed
;
286 u32 rx_hwtstamp_cleared
;
288 unsigned int rx_ps_pages
;
293 /* OS defined structs */
294 struct net_device
*netdev
;
295 struct pci_dev
*pdev
;
297 /* structs defined in e1000_hw.h */
300 spinlock_t stats64_lock
; /* protects statistics counters */
301 struct e1000_hw_stats stats
;
302 struct e1000_phy_info phy_info
;
303 struct e1000_phy_stats phy_stats
;
305 /* Snapshot of PHY registers */
306 struct e1000_phy_regs phy_regs
;
308 struct e1000_ring test_tx_ring
;
309 struct e1000_ring test_rx_ring
;
313 unsigned int num_vectors
;
314 struct msix_entry
*msix_entries
;
321 u32 max_hw_frame_size
;
327 struct work_struct downshift_task
;
328 struct work_struct update_phy_task
;
329 struct work_struct print_hang_task
;
336 struct hwtstamp_config hwtstamp_config
;
337 struct delayed_work systim_overflow_work
;
338 struct sk_buff
*tx_hwtstamp_skb
;
339 unsigned long tx_hwtstamp_start
;
340 struct work_struct tx_hwtstamp_work
;
341 spinlock_t systim_lock
; /* protects SYSTIML/H regsters */
342 struct cyclecounter cc
;
343 struct timecounter tc
;
344 struct ptp_clock
*ptp_clock
;
345 struct ptp_clock_info ptp_clock_info
;
346 struct pm_qos_request pm_qos_req
;
352 enum e1000_mac_type mac
;
356 u32 max_hw_frame_size
;
357 s32 (*get_variants
)(struct e1000_adapter
*);
358 const struct e1000_mac_operations
*mac_ops
;
359 const struct e1000_phy_operations
*phy_ops
;
360 const struct e1000_nvm_operations
*nvm_ops
;
363 s32
e1000e_get_base_timinca(struct e1000_adapter
*adapter
, u32
*timinca
);
365 /* The system time is maintained by a 64-bit counter comprised of the 32-bit
366 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore
367 * its resolution) is based on the contents of the TIMINCA register - it
368 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
369 * For the best accuracy, the incperiod should be as small as possible. The
370 * incvalue is scaled by a factor as large as possible (while still fitting
371 * in bits 23:0) so that relatively small clock corrections can be made.
373 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
374 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
375 * bits to count nanoseconds leaving the rest for fractional nonseconds.
377 #define INCVALUE_96MHz 125
378 #define INCVALUE_SHIFT_96MHz 17
379 #define INCPERIOD_SHIFT_96MHz 2
380 #define INCPERIOD_96MHz (12 >> INCPERIOD_SHIFT_96MHz)
382 #define INCVALUE_25MHz 40
383 #define INCVALUE_SHIFT_25MHz 18
384 #define INCPERIOD_25MHz 1
386 /* Another drawback of scaling the incvalue by a large factor is the
387 * 64-bit SYSTIM register overflows more quickly. This is dealt with
388 * by simply reading the clock before it overflows.
390 * Clock ns bits Overflows after
391 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~
392 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
393 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours
395 #define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4)
396 #define E1000_MAX_82574_SYSTIM_REREADS 50
397 #define E1000_82574_SYSTIM_EPSILON (1ULL << 35ULL)
399 /* hardware capability, feature, and workaround flags */
400 #define FLAG_HAS_AMT (1 << 0)
401 #define FLAG_HAS_FLASH (1 << 1)
402 #define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
403 #define FLAG_HAS_WOL (1 << 3)
405 #define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
406 #define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
407 #define FLAG_HAS_JUMBO_FRAMES (1 << 7)
408 #define FLAG_READ_ONLY_NVM (1 << 8)
409 #define FLAG_IS_ICH (1 << 9)
410 #define FLAG_HAS_MSIX (1 << 10)
411 #define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
412 #define FLAG_IS_QUAD_PORT_A (1 << 12)
413 #define FLAG_IS_QUAD_PORT (1 << 13)
414 #define FLAG_HAS_HW_TIMESTAMP (1 << 14)
415 #define FLAG_APME_IN_WUC (1 << 15)
416 #define FLAG_APME_IN_CTRL3 (1 << 16)
417 #define FLAG_APME_CHECK_PORT_B (1 << 17)
418 #define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
419 #define FLAG_NO_WAKE_UCAST (1 << 19)
420 #define FLAG_MNG_PT_ENABLED (1 << 20)
421 #define FLAG_RESET_OVERWRITES_LAA (1 << 21)
422 #define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
423 #define FLAG_TARC_SET_BIT_ZERO (1 << 23)
424 #define FLAG_RX_NEEDS_RESTART (1 << 24)
425 #define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
426 #define FLAG_SMART_POWER_DOWN (1 << 26)
427 #define FLAG_MSI_ENABLED (1 << 27)
428 /* reserved (1 << 28) */
429 #define FLAG_TSO_FORCE (1 << 29)
430 #define FLAG_RESTART_NOW (1 << 30)
431 #define FLAG_MSI_TEST_FAILED (1 << 31)
433 #define FLAG2_CRC_STRIPPING (1 << 0)
434 #define FLAG2_HAS_PHY_WAKEUP (1 << 1)
435 #define FLAG2_IS_DISCARDING (1 << 2)
436 #define FLAG2_DISABLE_ASPM_L1 (1 << 3)
437 #define FLAG2_HAS_PHY_STATS (1 << 4)
438 #define FLAG2_HAS_EEE (1 << 5)
439 #define FLAG2_DMA_BURST (1 << 6)
440 #define FLAG2_DISABLE_ASPM_L0S (1 << 7)
441 #define FLAG2_DISABLE_AIM (1 << 8)
442 #define FLAG2_CHECK_PHY_HANG (1 << 9)
443 #define FLAG2_NO_DISABLE_RX (1 << 10)
444 #define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11)
445 #define FLAG2_DFLT_CRC_STRIPPING (1 << 12)
446 #define FLAG2_CHECK_RX_HWTSTAMP (1 << 13)
448 #define E1000_RX_DESC_PS(R, i) \
449 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
450 #define E1000_RX_DESC_EXT(R, i) \
451 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
452 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
453 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
454 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
459 __E1000_ACCESS_SHARED_RESOURCE
,
467 latency_invalid
= 255
470 extern char e1000e_driver_name
[];
471 extern const char e1000e_driver_version
[];
473 void e1000e_check_options(struct e1000_adapter
*adapter
);
474 void e1000e_set_ethtool_ops(struct net_device
*netdev
);
476 int e1000e_up(struct e1000_adapter
*adapter
);
477 void e1000e_down(struct e1000_adapter
*adapter
, bool reset
);
478 void e1000e_reinit_locked(struct e1000_adapter
*adapter
);
479 void e1000e_reset(struct e1000_adapter
*adapter
);
480 void e1000e_power_up_phy(struct e1000_adapter
*adapter
);
481 int e1000e_setup_rx_resources(struct e1000_ring
*ring
);
482 int e1000e_setup_tx_resources(struct e1000_ring
*ring
);
483 void e1000e_free_rx_resources(struct e1000_ring
*ring
);
484 void e1000e_free_tx_resources(struct e1000_ring
*ring
);
485 struct rtnl_link_stats64
*e1000e_get_stats64(struct net_device
*netdev
,
486 struct rtnl_link_stats64
*stats
);
487 void e1000e_set_interrupt_capability(struct e1000_adapter
*adapter
);
488 void e1000e_reset_interrupt_capability(struct e1000_adapter
*adapter
);
489 void e1000e_get_hw_control(struct e1000_adapter
*adapter
);
490 void e1000e_release_hw_control(struct e1000_adapter
*adapter
);
491 void e1000e_write_itr(struct e1000_adapter
*adapter
, u32 itr
);
493 extern unsigned int copybreak
;
495 extern const struct e1000_info e1000_82571_info
;
496 extern const struct e1000_info e1000_82572_info
;
497 extern const struct e1000_info e1000_82573_info
;
498 extern const struct e1000_info e1000_82574_info
;
499 extern const struct e1000_info e1000_82583_info
;
500 extern const struct e1000_info e1000_ich8_info
;
501 extern const struct e1000_info e1000_ich9_info
;
502 extern const struct e1000_info e1000_ich10_info
;
503 extern const struct e1000_info e1000_pch_info
;
504 extern const struct e1000_info e1000_pch2_info
;
505 extern const struct e1000_info e1000_pch_lpt_info
;
506 extern const struct e1000_info e1000_pch_spt_info
;
507 extern const struct e1000_info e1000_es2_info
;
509 void e1000e_ptp_init(struct e1000_adapter
*adapter
);
510 void e1000e_ptp_remove(struct e1000_adapter
*adapter
);
512 static inline s32
e1000_phy_hw_reset(struct e1000_hw
*hw
)
514 return hw
->phy
.ops
.reset(hw
);
517 static inline s32
e1e_rphy(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
519 return hw
->phy
.ops
.read_reg(hw
, offset
, data
);
522 static inline s32
e1e_rphy_locked(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
524 return hw
->phy
.ops
.read_reg_locked(hw
, offset
, data
);
527 static inline s32
e1e_wphy(struct e1000_hw
*hw
, u32 offset
, u16 data
)
529 return hw
->phy
.ops
.write_reg(hw
, offset
, data
);
532 static inline s32
e1e_wphy_locked(struct e1000_hw
*hw
, u32 offset
, u16 data
)
534 return hw
->phy
.ops
.write_reg_locked(hw
, offset
, data
);
537 void e1000e_reload_nvm_generic(struct e1000_hw
*hw
);
539 static inline s32
e1000e_read_mac_addr(struct e1000_hw
*hw
)
541 if (hw
->mac
.ops
.read_mac_addr
)
542 return hw
->mac
.ops
.read_mac_addr(hw
);
544 return e1000_read_mac_addr_generic(hw
);
547 static inline s32
e1000_validate_nvm_checksum(struct e1000_hw
*hw
)
549 return hw
->nvm
.ops
.validate(hw
);
552 static inline s32
e1000e_update_nvm_checksum(struct e1000_hw
*hw
)
554 return hw
->nvm
.ops
.update(hw
);
557 static inline s32
e1000_read_nvm(struct e1000_hw
*hw
, u16 offset
, u16 words
,
560 return hw
->nvm
.ops
.read(hw
, offset
, words
, data
);
563 static inline s32
e1000_write_nvm(struct e1000_hw
*hw
, u16 offset
, u16 words
,
566 return hw
->nvm
.ops
.write(hw
, offset
, words
, data
);
569 static inline s32
e1000_get_phy_info(struct e1000_hw
*hw
)
571 return hw
->phy
.ops
.get_info(hw
);
574 static inline u32
__er32(struct e1000_hw
*hw
, unsigned long reg
)
576 return readl(hw
->hw_addr
+ reg
);
579 #define er32(reg) __er32(hw, E1000_##reg)
581 s32
__ew32_prepare(struct e1000_hw
*hw
);
582 void __ew32(struct e1000_hw
*hw
, unsigned long reg
, u32 val
);
584 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
586 #define e1e_flush() er32(STATUS)
588 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
589 (__ew32((a), (reg + ((offset) << 2)), (value)))
591 #define E1000_READ_REG_ARRAY(a, reg, offset) \
592 (readl((a)->hw_addr + reg + ((offset) << 2)))
594 #endif /* _E1000_H_ */