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Merge branch 'x86-debug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / ich8lan.c
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
55 * 82579LM Gigabit Network Connection
56 * 82579V Gigabit Network Connection
57 */
58
59 #include "e1000.h"
60
61 #define ICH_FLASH_GFPREG 0x0000
62 #define ICH_FLASH_HSFSTS 0x0004
63 #define ICH_FLASH_HSFCTL 0x0006
64 #define ICH_FLASH_FADDR 0x0008
65 #define ICH_FLASH_FDATA0 0x0010
66 #define ICH_FLASH_PR0 0x0074
67
68 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
71 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
72 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
73
74 #define ICH_CYCLE_READ 0
75 #define ICH_CYCLE_WRITE 2
76 #define ICH_CYCLE_ERASE 3
77
78 #define FLASH_GFPREG_BASE_MASK 0x1FFF
79 #define FLASH_SECTOR_ADDR_SHIFT 12
80
81 #define ICH_FLASH_SEG_SIZE_256 256
82 #define ICH_FLASH_SEG_SIZE_4K 4096
83 #define ICH_FLASH_SEG_SIZE_8K 8192
84 #define ICH_FLASH_SEG_SIZE_64K 65536
85
86
87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
88 /* FW established a valid mode */
89 #define E1000_ICH_FWSM_FW_VALID 0x00008000
90
91 #define E1000_ICH_MNG_IAMT_MODE 0x2
92
93 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
94 (ID_LED_DEF1_OFF2 << 8) | \
95 (ID_LED_DEF1_ON2 << 4) | \
96 (ID_LED_DEF1_DEF2))
97
98 #define E1000_ICH_NVM_SIG_WORD 0x13
99 #define E1000_ICH_NVM_SIG_MASK 0xC000
100 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
101 #define E1000_ICH_NVM_SIG_VALUE 0x80
102
103 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
104
105 #define E1000_FEXTNVM_SW_CONFIG 1
106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
107
108 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000
109 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000
110
111 #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
112 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
113 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
114
115 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
116
117 #define E1000_ICH_RAR_ENTRIES 7
118 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
119 #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
120
121 #define PHY_PAGE_SHIFT 5
122 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
123 ((reg) & MAX_PHY_REG_ADDRESS))
124 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
125 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
126
127 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
128 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
129 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
130
131 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
132
133 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
134
135 /* SMBus Control Phy Register */
136 #define CV_SMB_CTRL PHY_REG(769, 23)
137 #define CV_SMB_CTRL_FORCE_SMBUS 0x0001
138
139 /* SMBus Address Phy Register */
140 #define HV_SMB_ADDR PHY_REG(768, 26)
141 #define HV_SMB_ADDR_MASK 0x007F
142 #define HV_SMB_ADDR_PEC_EN 0x0200
143 #define HV_SMB_ADDR_VALID 0x0080
144 #define HV_SMB_ADDR_FREQ_MASK 0x1100
145 #define HV_SMB_ADDR_FREQ_LOW_SHIFT 8
146 #define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12
147
148 /* PHY Power Management Control */
149 #define HV_PM_CTRL PHY_REG(770, 17)
150 #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100
151
152 /* PHY Low Power Idle Control */
153 #define I82579_LPI_CTRL PHY_REG(772, 20)
154 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000
155 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80
156
157 /* EMI Registers */
158 #define I82579_EMI_ADDR 0x10
159 #define I82579_EMI_DATA 0x11
160 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
161 #define I82579_MSE_THRESHOLD 0x084F /* Mean Square Error Threshold */
162 #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */
163 #define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */
164 #define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */
165 #define I217_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE supported */
166
167 /* Intel Rapid Start Technology Support */
168 #define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70)
169 #define I217_PROXY_CTRL_AUTO_DISABLE 0x0080
170 #define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28)
171 #define I217_SxCTRL_ENABLE_LPI_RESET 0x1000
172 #define I217_CGFREG PHY_REG(772, 29)
173 #define I217_CGFREG_ENABLE_MTA_RESET 0x0002
174 #define I217_MEMPWR PHY_REG(772, 26)
175 #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
176
177 /* Strapping Option Register - RO */
178 #define E1000_STRAP 0x0000C
179 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
180 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
181 #define E1000_STRAP_SMT_FREQ_MASK 0x00003000
182 #define E1000_STRAP_SMT_FREQ_SHIFT 12
183
184 /* OEM Bits Phy Register */
185 #define HV_OEM_BITS PHY_REG(768, 25)
186 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
187 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
188 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
189
190 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
191 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
192
193 /* KMRN Mode Control */
194 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
195 #define HV_KMRN_MDIO_SLOW 0x0400
196
197 /* KMRN FIFO Control and Status */
198 #define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16)
199 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000
200 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12
201
202 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
203 /* Offset 04h HSFSTS */
204 union ich8_hws_flash_status {
205 struct ich8_hsfsts {
206 u16 flcdone :1; /* bit 0 Flash Cycle Done */
207 u16 flcerr :1; /* bit 1 Flash Cycle Error */
208 u16 dael :1; /* bit 2 Direct Access error Log */
209 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
210 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
211 u16 reserved1 :2; /* bit 13:6 Reserved */
212 u16 reserved2 :6; /* bit 13:6 Reserved */
213 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
214 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
215 } hsf_status;
216 u16 regval;
217 };
218
219 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
220 /* Offset 06h FLCTL */
221 union ich8_hws_flash_ctrl {
222 struct ich8_hsflctl {
223 u16 flcgo :1; /* 0 Flash Cycle Go */
224 u16 flcycle :2; /* 2:1 Flash Cycle */
225 u16 reserved :5; /* 7:3 Reserved */
226 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
227 u16 flockdn :6; /* 15:10 Reserved */
228 } hsf_ctrl;
229 u16 regval;
230 };
231
232 /* ICH Flash Region Access Permissions */
233 union ich8_hws_flash_regacc {
234 struct ich8_flracc {
235 u32 grra :8; /* 0:7 GbE region Read Access */
236 u32 grwa :8; /* 8:15 GbE region Write Access */
237 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
238 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
239 } hsf_flregacc;
240 u16 regval;
241 };
242
243 /* ICH Flash Protected Region */
244 union ich8_flash_protected_range {
245 struct ich8_pr {
246 u32 base:13; /* 0:12 Protected Range Base */
247 u32 reserved1:2; /* 13:14 Reserved */
248 u32 rpe:1; /* 15 Read Protection Enable */
249 u32 limit:13; /* 16:28 Protected Range Limit */
250 u32 reserved2:2; /* 29:30 Reserved */
251 u32 wpe:1; /* 31 Write Protection Enable */
252 } range;
253 u32 regval;
254 };
255
256 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
257 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
258 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
259 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
260 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
261 u32 offset, u8 byte);
262 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
263 u8 *data);
264 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
265 u16 *data);
266 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
267 u8 size, u16 *data);
268 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
269 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
270 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
271 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
272 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
273 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
274 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
275 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
276 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
277 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
278 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
279 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
280 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
281 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
282 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
283 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
284 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
285 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
286 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
287 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
288 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
289 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
290
291 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
292 {
293 return readw(hw->flash_address + reg);
294 }
295
296 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
297 {
298 return readl(hw->flash_address + reg);
299 }
300
301 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
302 {
303 writew(val, hw->flash_address + reg);
304 }
305
306 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
307 {
308 writel(val, hw->flash_address + reg);
309 }
310
311 #define er16flash(reg) __er16flash(hw, (reg))
312 #define er32flash(reg) __er32flash(hw, (reg))
313 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
314 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
315
316 /**
317 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
318 * @hw: pointer to the HW structure
319 *
320 * Test access to the PHY registers by reading the PHY ID registers. If
321 * the PHY ID is already known (e.g. resume path) compare it with known ID,
322 * otherwise assume the read PHY ID is correct if it is valid.
323 *
324 * Assumes the sw/fw/hw semaphore is already acquired.
325 **/
326 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
327 {
328 u16 phy_reg = 0;
329 u32 phy_id = 0;
330 s32 ret_val;
331 u16 retry_count;
332
333 for (retry_count = 0; retry_count < 2; retry_count++) {
334 ret_val = e1e_rphy_locked(hw, PHY_ID1, &phy_reg);
335 if (ret_val || (phy_reg == 0xFFFF))
336 continue;
337 phy_id = (u32)(phy_reg << 16);
338
339 ret_val = e1e_rphy_locked(hw, PHY_ID2, &phy_reg);
340 if (ret_val || (phy_reg == 0xFFFF)) {
341 phy_id = 0;
342 continue;
343 }
344 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
345 break;
346 }
347
348 if (hw->phy.id) {
349 if (hw->phy.id == phy_id)
350 return true;
351 } else if (phy_id) {
352 hw->phy.id = phy_id;
353 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
354 return true;
355 }
356
357 /*
358 * In case the PHY needs to be in mdio slow mode,
359 * set slow mode and try to get the PHY id again.
360 */
361 hw->phy.ops.release(hw);
362 ret_val = e1000_set_mdio_slow_mode_hv(hw);
363 if (!ret_val)
364 ret_val = e1000e_get_phy_id(hw);
365 hw->phy.ops.acquire(hw);
366
367 return !ret_val;
368 }
369
370 /**
371 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
372 * @hw: pointer to the HW structure
373 *
374 * Workarounds/flow necessary for PHY initialization during driver load
375 * and resume paths.
376 **/
377 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
378 {
379 u32 mac_reg, fwsm = er32(FWSM);
380 s32 ret_val;
381 u16 phy_reg;
382
383 ret_val = hw->phy.ops.acquire(hw);
384 if (ret_val) {
385 e_dbg("Failed to initialize PHY flow\n");
386 return ret_val;
387 }
388
389 /*
390 * The MAC-PHY interconnect may be in SMBus mode. If the PHY is
391 * inaccessible and resetting the PHY is not blocked, toggle the
392 * LANPHYPC Value bit to force the interconnect to PCIe mode.
393 */
394 switch (hw->mac.type) {
395 case e1000_pch_lpt:
396 if (e1000_phy_is_accessible_pchlan(hw))
397 break;
398
399 /*
400 * Before toggling LANPHYPC, see if PHY is accessible by
401 * forcing MAC to SMBus mode first.
402 */
403 mac_reg = er32(CTRL_EXT);
404 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
405 ew32(CTRL_EXT, mac_reg);
406
407 /* fall-through */
408 case e1000_pch2lan:
409 /*
410 * Gate automatic PHY configuration by hardware on
411 * non-managed 82579
412 */
413 if ((hw->mac.type == e1000_pch2lan) &&
414 !(fwsm & E1000_ICH_FWSM_FW_VALID))
415 e1000_gate_hw_phy_config_ich8lan(hw, true);
416
417 if (e1000_phy_is_accessible_pchlan(hw)) {
418 if (hw->mac.type == e1000_pch_lpt) {
419 /* Unforce SMBus mode in PHY */
420 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
421 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
422 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
423
424 /* Unforce SMBus mode in MAC */
425 mac_reg = er32(CTRL_EXT);
426 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
427 ew32(CTRL_EXT, mac_reg);
428 }
429 break;
430 }
431
432 /* fall-through */
433 case e1000_pchlan:
434 if ((hw->mac.type == e1000_pchlan) &&
435 (fwsm & E1000_ICH_FWSM_FW_VALID))
436 break;
437
438 if (hw->phy.ops.check_reset_block(hw)) {
439 e_dbg("Required LANPHYPC toggle blocked by ME\n");
440 break;
441 }
442
443 e_dbg("Toggling LANPHYPC\n");
444
445 /* Set Phy Config Counter to 50msec */
446 mac_reg = er32(FEXTNVM3);
447 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
448 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
449 ew32(FEXTNVM3, mac_reg);
450
451 /* Toggle LANPHYPC Value bit */
452 mac_reg = er32(CTRL);
453 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
454 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
455 ew32(CTRL, mac_reg);
456 e1e_flush();
457 udelay(10);
458 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
459 ew32(CTRL, mac_reg);
460 e1e_flush();
461 if (hw->mac.type < e1000_pch_lpt) {
462 msleep(50);
463 } else {
464 u16 count = 20;
465 do {
466 usleep_range(5000, 10000);
467 } while (!(er32(CTRL_EXT) &
468 E1000_CTRL_EXT_LPCD) && count--);
469 }
470 break;
471 default:
472 break;
473 }
474
475 hw->phy.ops.release(hw);
476
477 /*
478 * Reset the PHY before any access to it. Doing so, ensures
479 * that the PHY is in a known good state before we read/write
480 * PHY registers. The generic reset is sufficient here,
481 * because we haven't determined the PHY type yet.
482 */
483 ret_val = e1000e_phy_hw_reset_generic(hw);
484
485 /* Ungate automatic PHY configuration on non-managed 82579 */
486 if ((hw->mac.type == e1000_pch2lan) &&
487 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
488 usleep_range(10000, 20000);
489 e1000_gate_hw_phy_config_ich8lan(hw, false);
490 }
491
492 return ret_val;
493 }
494
495 /**
496 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
497 * @hw: pointer to the HW structure
498 *
499 * Initialize family-specific PHY parameters and function pointers.
500 **/
501 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
502 {
503 struct e1000_phy_info *phy = &hw->phy;
504 s32 ret_val = 0;
505
506 phy->addr = 1;
507 phy->reset_delay_us = 100;
508
509 phy->ops.set_page = e1000_set_page_igp;
510 phy->ops.read_reg = e1000_read_phy_reg_hv;
511 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
512 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
513 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
514 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
515 phy->ops.write_reg = e1000_write_phy_reg_hv;
516 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
517 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
518 phy->ops.power_up = e1000_power_up_phy_copper;
519 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
520 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
521
522 phy->id = e1000_phy_unknown;
523
524 ret_val = e1000_init_phy_workarounds_pchlan(hw);
525 if (ret_val)
526 return ret_val;
527
528 if (phy->id == e1000_phy_unknown)
529 switch (hw->mac.type) {
530 default:
531 ret_val = e1000e_get_phy_id(hw);
532 if (ret_val)
533 return ret_val;
534 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
535 break;
536 /* fall-through */
537 case e1000_pch2lan:
538 case e1000_pch_lpt:
539 /*
540 * In case the PHY needs to be in mdio slow mode,
541 * set slow mode and try to get the PHY id again.
542 */
543 ret_val = e1000_set_mdio_slow_mode_hv(hw);
544 if (ret_val)
545 return ret_val;
546 ret_val = e1000e_get_phy_id(hw);
547 if (ret_val)
548 return ret_val;
549 break;
550 }
551 phy->type = e1000e_get_phy_type_from_id(phy->id);
552
553 switch (phy->type) {
554 case e1000_phy_82577:
555 case e1000_phy_82579:
556 case e1000_phy_i217:
557 phy->ops.check_polarity = e1000_check_polarity_82577;
558 phy->ops.force_speed_duplex =
559 e1000_phy_force_speed_duplex_82577;
560 phy->ops.get_cable_length = e1000_get_cable_length_82577;
561 phy->ops.get_info = e1000_get_phy_info_82577;
562 phy->ops.commit = e1000e_phy_sw_reset;
563 break;
564 case e1000_phy_82578:
565 phy->ops.check_polarity = e1000_check_polarity_m88;
566 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
567 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
568 phy->ops.get_info = e1000e_get_phy_info_m88;
569 break;
570 default:
571 ret_val = -E1000_ERR_PHY;
572 break;
573 }
574
575 return ret_val;
576 }
577
578 /**
579 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
580 * @hw: pointer to the HW structure
581 *
582 * Initialize family-specific PHY parameters and function pointers.
583 **/
584 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
585 {
586 struct e1000_phy_info *phy = &hw->phy;
587 s32 ret_val;
588 u16 i = 0;
589
590 phy->addr = 1;
591 phy->reset_delay_us = 100;
592
593 phy->ops.power_up = e1000_power_up_phy_copper;
594 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
595
596 /*
597 * We may need to do this twice - once for IGP and if that fails,
598 * we'll set BM func pointers and try again
599 */
600 ret_val = e1000e_determine_phy_address(hw);
601 if (ret_val) {
602 phy->ops.write_reg = e1000e_write_phy_reg_bm;
603 phy->ops.read_reg = e1000e_read_phy_reg_bm;
604 ret_val = e1000e_determine_phy_address(hw);
605 if (ret_val) {
606 e_dbg("Cannot determine PHY addr. Erroring out\n");
607 return ret_val;
608 }
609 }
610
611 phy->id = 0;
612 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
613 (i++ < 100)) {
614 usleep_range(1000, 2000);
615 ret_val = e1000e_get_phy_id(hw);
616 if (ret_val)
617 return ret_val;
618 }
619
620 /* Verify phy id */
621 switch (phy->id) {
622 case IGP03E1000_E_PHY_ID:
623 phy->type = e1000_phy_igp_3;
624 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
625 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
626 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
627 phy->ops.get_info = e1000e_get_phy_info_igp;
628 phy->ops.check_polarity = e1000_check_polarity_igp;
629 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
630 break;
631 case IFE_E_PHY_ID:
632 case IFE_PLUS_E_PHY_ID:
633 case IFE_C_E_PHY_ID:
634 phy->type = e1000_phy_ife;
635 phy->autoneg_mask = E1000_ALL_NOT_GIG;
636 phy->ops.get_info = e1000_get_phy_info_ife;
637 phy->ops.check_polarity = e1000_check_polarity_ife;
638 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
639 break;
640 case BME1000_E_PHY_ID:
641 phy->type = e1000_phy_bm;
642 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
643 phy->ops.read_reg = e1000e_read_phy_reg_bm;
644 phy->ops.write_reg = e1000e_write_phy_reg_bm;
645 phy->ops.commit = e1000e_phy_sw_reset;
646 phy->ops.get_info = e1000e_get_phy_info_m88;
647 phy->ops.check_polarity = e1000_check_polarity_m88;
648 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
649 break;
650 default:
651 return -E1000_ERR_PHY;
652 break;
653 }
654
655 return 0;
656 }
657
658 /**
659 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
660 * @hw: pointer to the HW structure
661 *
662 * Initialize family-specific NVM parameters and function
663 * pointers.
664 **/
665 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
666 {
667 struct e1000_nvm_info *nvm = &hw->nvm;
668 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
669 u32 gfpreg, sector_base_addr, sector_end_addr;
670 u16 i;
671
672 /* Can't read flash registers if the register set isn't mapped. */
673 if (!hw->flash_address) {
674 e_dbg("ERROR: Flash registers not mapped\n");
675 return -E1000_ERR_CONFIG;
676 }
677
678 nvm->type = e1000_nvm_flash_sw;
679
680 gfpreg = er32flash(ICH_FLASH_GFPREG);
681
682 /*
683 * sector_X_addr is a "sector"-aligned address (4096 bytes)
684 * Add 1 to sector_end_addr since this sector is included in
685 * the overall size.
686 */
687 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
688 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
689
690 /* flash_base_addr is byte-aligned */
691 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
692
693 /*
694 * find total size of the NVM, then cut in half since the total
695 * size represents two separate NVM banks.
696 */
697 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
698 << FLASH_SECTOR_ADDR_SHIFT;
699 nvm->flash_bank_size /= 2;
700 /* Adjust to word count */
701 nvm->flash_bank_size /= sizeof(u16);
702
703 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
704
705 /* Clear shadow ram */
706 for (i = 0; i < nvm->word_size; i++) {
707 dev_spec->shadow_ram[i].modified = false;
708 dev_spec->shadow_ram[i].value = 0xFFFF;
709 }
710
711 return 0;
712 }
713
714 /**
715 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
716 * @hw: pointer to the HW structure
717 *
718 * Initialize family-specific MAC parameters and function
719 * pointers.
720 **/
721 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
722 {
723 struct e1000_mac_info *mac = &hw->mac;
724
725 /* Set media type function pointer */
726 hw->phy.media_type = e1000_media_type_copper;
727
728 /* Set mta register count */
729 mac->mta_reg_count = 32;
730 /* Set rar entry count */
731 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
732 if (mac->type == e1000_ich8lan)
733 mac->rar_entry_count--;
734 /* FWSM register */
735 mac->has_fwsm = true;
736 /* ARC subsystem not supported */
737 mac->arc_subsystem_valid = false;
738 /* Adaptive IFS supported */
739 mac->adaptive_ifs = true;
740
741 /* LED and other operations */
742 switch (mac->type) {
743 case e1000_ich8lan:
744 case e1000_ich9lan:
745 case e1000_ich10lan:
746 /* check management mode */
747 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
748 /* ID LED init */
749 mac->ops.id_led_init = e1000e_id_led_init_generic;
750 /* blink LED */
751 mac->ops.blink_led = e1000e_blink_led_generic;
752 /* setup LED */
753 mac->ops.setup_led = e1000e_setup_led_generic;
754 /* cleanup LED */
755 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
756 /* turn on/off LED */
757 mac->ops.led_on = e1000_led_on_ich8lan;
758 mac->ops.led_off = e1000_led_off_ich8lan;
759 break;
760 case e1000_pch2lan:
761 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
762 mac->ops.rar_set = e1000_rar_set_pch2lan;
763 /* fall-through */
764 case e1000_pch_lpt:
765 case e1000_pchlan:
766 /* check management mode */
767 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
768 /* ID LED init */
769 mac->ops.id_led_init = e1000_id_led_init_pchlan;
770 /* setup LED */
771 mac->ops.setup_led = e1000_setup_led_pchlan;
772 /* cleanup LED */
773 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
774 /* turn on/off LED */
775 mac->ops.led_on = e1000_led_on_pchlan;
776 mac->ops.led_off = e1000_led_off_pchlan;
777 break;
778 default:
779 break;
780 }
781
782 if (mac->type == e1000_pch_lpt) {
783 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
784 mac->ops.rar_set = e1000_rar_set_pch_lpt;
785 }
786
787 /* Enable PCS Lock-loss workaround for ICH8 */
788 if (mac->type == e1000_ich8lan)
789 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
790
791 /*
792 * Gate automatic PHY configuration by hardware on managed
793 * 82579 and i217
794 */
795 if ((mac->type == e1000_pch2lan || mac->type == e1000_pch_lpt) &&
796 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
797 e1000_gate_hw_phy_config_ich8lan(hw, true);
798
799 return 0;
800 }
801
802 /**
803 * e1000_set_eee_pchlan - Enable/disable EEE support
804 * @hw: pointer to the HW structure
805 *
806 * Enable/disable EEE based on setting in dev_spec structure. The bits in
807 * the LPI Control register will remain set only if/when link is up.
808 **/
809 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
810 {
811 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
812 s32 ret_val = 0;
813 u16 phy_reg;
814
815 if ((hw->phy.type != e1000_phy_82579) &&
816 (hw->phy.type != e1000_phy_i217))
817 return 0;
818
819 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
820 if (ret_val)
821 return ret_val;
822
823 if (dev_spec->eee_disable)
824 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
825 else
826 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
827
828 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
829 if (ret_val)
830 return ret_val;
831
832 if ((hw->phy.type == e1000_phy_i217) && !dev_spec->eee_disable) {
833 /* Save off link partner's EEE ability */
834 ret_val = hw->phy.ops.acquire(hw);
835 if (ret_val)
836 return ret_val;
837 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR,
838 I217_EEE_LP_ABILITY);
839 if (ret_val)
840 goto release;
841 e1e_rphy_locked(hw, I82579_EMI_DATA, &dev_spec->eee_lp_ability);
842
843 /*
844 * EEE is not supported in 100Half, so ignore partner's EEE
845 * in 100 ability if full-duplex is not advertised.
846 */
847 e1e_rphy_locked(hw, PHY_LP_ABILITY, &phy_reg);
848 if (!(phy_reg & NWAY_LPAR_100TX_FD_CAPS))
849 dev_spec->eee_lp_ability &= ~I217_EEE_100_SUPPORTED;
850 release:
851 hw->phy.ops.release(hw);
852 }
853
854 return 0;
855 }
856
857 /**
858 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
859 * @hw: pointer to the HW structure
860 *
861 * Checks to see of the link status of the hardware has changed. If a
862 * change in link status has been detected, then we read the PHY registers
863 * to get the current speed/duplex if link exists.
864 **/
865 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
866 {
867 struct e1000_mac_info *mac = &hw->mac;
868 s32 ret_val;
869 bool link;
870 u16 phy_reg;
871
872 /*
873 * We only want to go out to the PHY registers to see if Auto-Neg
874 * has completed and/or if our link status has changed. The
875 * get_link_status flag is set upon receiving a Link Status
876 * Change or Rx Sequence Error interrupt.
877 */
878 if (!mac->get_link_status)
879 return 0;
880
881 /*
882 * First we want to see if the MII Status Register reports
883 * link. If so, then we want to get the current speed/duplex
884 * of the PHY.
885 */
886 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
887 if (ret_val)
888 return ret_val;
889
890 if (hw->mac.type == e1000_pchlan) {
891 ret_val = e1000_k1_gig_workaround_hv(hw, link);
892 if (ret_val)
893 return ret_val;
894 }
895
896 /* Clear link partner's EEE ability */
897 hw->dev_spec.ich8lan.eee_lp_ability = 0;
898
899 if (!link)
900 return 0; /* No link detected */
901
902 mac->get_link_status = false;
903
904 switch (hw->mac.type) {
905 case e1000_pch2lan:
906 ret_val = e1000_k1_workaround_lv(hw);
907 if (ret_val)
908 return ret_val;
909 /* fall-thru */
910 case e1000_pchlan:
911 if (hw->phy.type == e1000_phy_82578) {
912 ret_val = e1000_link_stall_workaround_hv(hw);
913 if (ret_val)
914 return ret_val;
915 }
916
917 /*
918 * Workaround for PCHx parts in half-duplex:
919 * Set the number of preambles removed from the packet
920 * when it is passed from the PHY to the MAC to prevent
921 * the MAC from misinterpreting the packet type.
922 */
923 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
924 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
925
926 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
927 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
928
929 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
930 break;
931 default:
932 break;
933 }
934
935 /*
936 * Check if there was DownShift, must be checked
937 * immediately after link-up
938 */
939 e1000e_check_downshift(hw);
940
941 /* Enable/Disable EEE after link up */
942 ret_val = e1000_set_eee_pchlan(hw);
943 if (ret_val)
944 return ret_val;
945
946 /*
947 * If we are forcing speed/duplex, then we simply return since
948 * we have already determined whether we have link or not.
949 */
950 if (!mac->autoneg)
951 return -E1000_ERR_CONFIG;
952
953 /*
954 * Auto-Neg is enabled. Auto Speed Detection takes care
955 * of MAC speed/duplex configuration. So we only need to
956 * configure Collision Distance in the MAC.
957 */
958 mac->ops.config_collision_dist(hw);
959
960 /*
961 * Configure Flow Control now that Auto-Neg has completed.
962 * First, we need to restore the desired flow control
963 * settings because we may have had to re-autoneg with a
964 * different link partner.
965 */
966 ret_val = e1000e_config_fc_after_link_up(hw);
967 if (ret_val)
968 e_dbg("Error configuring flow control\n");
969
970 return ret_val;
971 }
972
973 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
974 {
975 struct e1000_hw *hw = &adapter->hw;
976 s32 rc;
977
978 rc = e1000_init_mac_params_ich8lan(hw);
979 if (rc)
980 return rc;
981
982 rc = e1000_init_nvm_params_ich8lan(hw);
983 if (rc)
984 return rc;
985
986 switch (hw->mac.type) {
987 case e1000_ich8lan:
988 case e1000_ich9lan:
989 case e1000_ich10lan:
990 rc = e1000_init_phy_params_ich8lan(hw);
991 break;
992 case e1000_pchlan:
993 case e1000_pch2lan:
994 case e1000_pch_lpt:
995 rc = e1000_init_phy_params_pchlan(hw);
996 break;
997 default:
998 break;
999 }
1000 if (rc)
1001 return rc;
1002
1003 /*
1004 * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1005 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1006 */
1007 if ((adapter->hw.phy.type == e1000_phy_ife) ||
1008 ((adapter->hw.mac.type >= e1000_pch2lan) &&
1009 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1010 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1011 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
1012
1013 hw->mac.ops.blink_led = NULL;
1014 }
1015
1016 if ((adapter->hw.mac.type == e1000_ich8lan) &&
1017 (adapter->hw.phy.type != e1000_phy_ife))
1018 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1019
1020 /* Enable workaround for 82579 w/ ME enabled */
1021 if ((adapter->hw.mac.type == e1000_pch2lan) &&
1022 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1023 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1024
1025 /* Disable EEE by default until IEEE802.3az spec is finalized */
1026 if (adapter->flags2 & FLAG2_HAS_EEE)
1027 adapter->hw.dev_spec.ich8lan.eee_disable = true;
1028
1029 return 0;
1030 }
1031
1032 static DEFINE_MUTEX(nvm_mutex);
1033
1034 /**
1035 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1036 * @hw: pointer to the HW structure
1037 *
1038 * Acquires the mutex for performing NVM operations.
1039 **/
1040 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1041 {
1042 mutex_lock(&nvm_mutex);
1043
1044 return 0;
1045 }
1046
1047 /**
1048 * e1000_release_nvm_ich8lan - Release NVM mutex
1049 * @hw: pointer to the HW structure
1050 *
1051 * Releases the mutex used while performing NVM operations.
1052 **/
1053 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1054 {
1055 mutex_unlock(&nvm_mutex);
1056 }
1057
1058 /**
1059 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1060 * @hw: pointer to the HW structure
1061 *
1062 * Acquires the software control flag for performing PHY and select
1063 * MAC CSR accesses.
1064 **/
1065 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1066 {
1067 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1068 s32 ret_val = 0;
1069
1070 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1071 &hw->adapter->state)) {
1072 e_dbg("contention for Phy access\n");
1073 return -E1000_ERR_PHY;
1074 }
1075
1076 while (timeout) {
1077 extcnf_ctrl = er32(EXTCNF_CTRL);
1078 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1079 break;
1080
1081 mdelay(1);
1082 timeout--;
1083 }
1084
1085 if (!timeout) {
1086 e_dbg("SW has already locked the resource.\n");
1087 ret_val = -E1000_ERR_CONFIG;
1088 goto out;
1089 }
1090
1091 timeout = SW_FLAG_TIMEOUT;
1092
1093 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1094 ew32(EXTCNF_CTRL, extcnf_ctrl);
1095
1096 while (timeout) {
1097 extcnf_ctrl = er32(EXTCNF_CTRL);
1098 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1099 break;
1100
1101 mdelay(1);
1102 timeout--;
1103 }
1104
1105 if (!timeout) {
1106 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1107 er32(FWSM), extcnf_ctrl);
1108 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1109 ew32(EXTCNF_CTRL, extcnf_ctrl);
1110 ret_val = -E1000_ERR_CONFIG;
1111 goto out;
1112 }
1113
1114 out:
1115 if (ret_val)
1116 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1117
1118 return ret_val;
1119 }
1120
1121 /**
1122 * e1000_release_swflag_ich8lan - Release software control flag
1123 * @hw: pointer to the HW structure
1124 *
1125 * Releases the software control flag for performing PHY and select
1126 * MAC CSR accesses.
1127 **/
1128 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1129 {
1130 u32 extcnf_ctrl;
1131
1132 extcnf_ctrl = er32(EXTCNF_CTRL);
1133
1134 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1135 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1136 ew32(EXTCNF_CTRL, extcnf_ctrl);
1137 } else {
1138 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1139 }
1140
1141 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1142 }
1143
1144 /**
1145 * e1000_check_mng_mode_ich8lan - Checks management mode
1146 * @hw: pointer to the HW structure
1147 *
1148 * This checks if the adapter has any manageability enabled.
1149 * This is a function pointer entry point only called by read/write
1150 * routines for the PHY and NVM parts.
1151 **/
1152 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1153 {
1154 u32 fwsm;
1155
1156 fwsm = er32(FWSM);
1157 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1158 ((fwsm & E1000_FWSM_MODE_MASK) ==
1159 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1160 }
1161
1162 /**
1163 * e1000_check_mng_mode_pchlan - Checks management mode
1164 * @hw: pointer to the HW structure
1165 *
1166 * This checks if the adapter has iAMT enabled.
1167 * This is a function pointer entry point only called by read/write
1168 * routines for the PHY and NVM parts.
1169 **/
1170 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1171 {
1172 u32 fwsm;
1173
1174 fwsm = er32(FWSM);
1175 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1176 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1177 }
1178
1179 /**
1180 * e1000_rar_set_pch2lan - Set receive address register
1181 * @hw: pointer to the HW structure
1182 * @addr: pointer to the receive address
1183 * @index: receive address array register
1184 *
1185 * Sets the receive address array register at index to the address passed
1186 * in by addr. For 82579, RAR[0] is the base address register that is to
1187 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1188 * Use SHRA[0-3] in place of those reserved for ME.
1189 **/
1190 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1191 {
1192 u32 rar_low, rar_high;
1193
1194 /*
1195 * HW expects these in little endian so we reverse the byte order
1196 * from network order (big endian) to little endian
1197 */
1198 rar_low = ((u32)addr[0] |
1199 ((u32)addr[1] << 8) |
1200 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1201
1202 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1203
1204 /* If MAC address zero, no need to set the AV bit */
1205 if (rar_low || rar_high)
1206 rar_high |= E1000_RAH_AV;
1207
1208 if (index == 0) {
1209 ew32(RAL(index), rar_low);
1210 e1e_flush();
1211 ew32(RAH(index), rar_high);
1212 e1e_flush();
1213 return;
1214 }
1215
1216 if (index < hw->mac.rar_entry_count) {
1217 s32 ret_val;
1218
1219 ret_val = e1000_acquire_swflag_ich8lan(hw);
1220 if (ret_val)
1221 goto out;
1222
1223 ew32(SHRAL(index - 1), rar_low);
1224 e1e_flush();
1225 ew32(SHRAH(index - 1), rar_high);
1226 e1e_flush();
1227
1228 e1000_release_swflag_ich8lan(hw);
1229
1230 /* verify the register updates */
1231 if ((er32(SHRAL(index - 1)) == rar_low) &&
1232 (er32(SHRAH(index - 1)) == rar_high))
1233 return;
1234
1235 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1236 (index - 1), er32(FWSM));
1237 }
1238
1239 out:
1240 e_dbg("Failed to write receive address at index %d\n", index);
1241 }
1242
1243 /**
1244 * e1000_rar_set_pch_lpt - Set receive address registers
1245 * @hw: pointer to the HW structure
1246 * @addr: pointer to the receive address
1247 * @index: receive address array register
1248 *
1249 * Sets the receive address register array at index to the address passed
1250 * in by addr. For LPT, RAR[0] is the base address register that is to
1251 * contain the MAC address. SHRA[0-10] are the shared receive address
1252 * registers that are shared between the Host and manageability engine (ME).
1253 **/
1254 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1255 {
1256 u32 rar_low, rar_high;
1257 u32 wlock_mac;
1258
1259 /*
1260 * HW expects these in little endian so we reverse the byte order
1261 * from network order (big endian) to little endian
1262 */
1263 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1264 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1265
1266 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1267
1268 /* If MAC address zero, no need to set the AV bit */
1269 if (rar_low || rar_high)
1270 rar_high |= E1000_RAH_AV;
1271
1272 if (index == 0) {
1273 ew32(RAL(index), rar_low);
1274 e1e_flush();
1275 ew32(RAH(index), rar_high);
1276 e1e_flush();
1277 return;
1278 }
1279
1280 /*
1281 * The manageability engine (ME) can lock certain SHRAR registers that
1282 * it is using - those registers are unavailable for use.
1283 */
1284 if (index < hw->mac.rar_entry_count) {
1285 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1286 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1287
1288 /* Check if all SHRAR registers are locked */
1289 if (wlock_mac == 1)
1290 goto out;
1291
1292 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1293 s32 ret_val;
1294
1295 ret_val = e1000_acquire_swflag_ich8lan(hw);
1296
1297 if (ret_val)
1298 goto out;
1299
1300 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1301 e1e_flush();
1302 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1303 e1e_flush();
1304
1305 e1000_release_swflag_ich8lan(hw);
1306
1307 /* verify the register updates */
1308 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1309 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1310 return;
1311 }
1312 }
1313
1314 out:
1315 e_dbg("Failed to write receive address at index %d\n", index);
1316 }
1317
1318 /**
1319 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1320 * @hw: pointer to the HW structure
1321 *
1322 * Checks if firmware is blocking the reset of the PHY.
1323 * This is a function pointer entry point only called by
1324 * reset routines.
1325 **/
1326 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1327 {
1328 u32 fwsm;
1329
1330 fwsm = er32(FWSM);
1331
1332 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
1333 }
1334
1335 /**
1336 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1337 * @hw: pointer to the HW structure
1338 *
1339 * Assumes semaphore already acquired.
1340 *
1341 **/
1342 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1343 {
1344 u16 phy_data;
1345 u32 strap = er32(STRAP);
1346 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1347 E1000_STRAP_SMT_FREQ_SHIFT;
1348 s32 ret_val = 0;
1349
1350 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1351
1352 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1353 if (ret_val)
1354 return ret_val;
1355
1356 phy_data &= ~HV_SMB_ADDR_MASK;
1357 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1358 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1359
1360 if (hw->phy.type == e1000_phy_i217) {
1361 /* Restore SMBus frequency */
1362 if (freq--) {
1363 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1364 phy_data |= (freq & (1 << 0)) <<
1365 HV_SMB_ADDR_FREQ_LOW_SHIFT;
1366 phy_data |= (freq & (1 << 1)) <<
1367 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1368 } else {
1369 e_dbg("Unsupported SMB frequency in PHY\n");
1370 }
1371 }
1372
1373 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1374 }
1375
1376 /**
1377 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1378 * @hw: pointer to the HW structure
1379 *
1380 * SW should configure the LCD from the NVM extended configuration region
1381 * as a workaround for certain parts.
1382 **/
1383 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1384 {
1385 struct e1000_phy_info *phy = &hw->phy;
1386 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1387 s32 ret_val = 0;
1388 u16 word_addr, reg_data, reg_addr, phy_page = 0;
1389
1390 /*
1391 * Initialize the PHY from the NVM on ICH platforms. This
1392 * is needed due to an issue where the NVM configuration is
1393 * not properly autoloaded after power transitions.
1394 * Therefore, after each PHY reset, we will load the
1395 * configuration data out of the NVM manually.
1396 */
1397 switch (hw->mac.type) {
1398 case e1000_ich8lan:
1399 if (phy->type != e1000_phy_igp_3)
1400 return ret_val;
1401
1402 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1403 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1404 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1405 break;
1406 }
1407 /* Fall-thru */
1408 case e1000_pchlan:
1409 case e1000_pch2lan:
1410 case e1000_pch_lpt:
1411 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1412 break;
1413 default:
1414 return ret_val;
1415 }
1416
1417 ret_val = hw->phy.ops.acquire(hw);
1418 if (ret_val)
1419 return ret_val;
1420
1421 data = er32(FEXTNVM);
1422 if (!(data & sw_cfg_mask))
1423 goto release;
1424
1425 /*
1426 * Make sure HW does not configure LCD from PHY
1427 * extended configuration before SW configuration
1428 */
1429 data = er32(EXTCNF_CTRL);
1430 if ((hw->mac.type < e1000_pch2lan) &&
1431 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
1432 goto release;
1433
1434 cnf_size = er32(EXTCNF_SIZE);
1435 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1436 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1437 if (!cnf_size)
1438 goto release;
1439
1440 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1441 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1442
1443 if (((hw->mac.type == e1000_pchlan) &&
1444 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1445 (hw->mac.type > e1000_pchlan)) {
1446 /*
1447 * HW configures the SMBus address and LEDs when the
1448 * OEM and LCD Write Enable bits are set in the NVM.
1449 * When both NVM bits are cleared, SW will configure
1450 * them instead.
1451 */
1452 ret_val = e1000_write_smbus_addr(hw);
1453 if (ret_val)
1454 goto release;
1455
1456 data = er32(LEDCTL);
1457 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1458 (u16)data);
1459 if (ret_val)
1460 goto release;
1461 }
1462
1463 /* Configure LCD from extended configuration region. */
1464
1465 /* cnf_base_addr is in DWORD */
1466 word_addr = (u16)(cnf_base_addr << 1);
1467
1468 for (i = 0; i < cnf_size; i++) {
1469 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1470 &reg_data);
1471 if (ret_val)
1472 goto release;
1473
1474 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1475 1, &reg_addr);
1476 if (ret_val)
1477 goto release;
1478
1479 /* Save off the PHY page for future writes. */
1480 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1481 phy_page = reg_data;
1482 continue;
1483 }
1484
1485 reg_addr &= PHY_REG_MASK;
1486 reg_addr |= phy_page;
1487
1488 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
1489 if (ret_val)
1490 goto release;
1491 }
1492
1493 release:
1494 hw->phy.ops.release(hw);
1495 return ret_val;
1496 }
1497
1498 /**
1499 * e1000_k1_gig_workaround_hv - K1 Si workaround
1500 * @hw: pointer to the HW structure
1501 * @link: link up bool flag
1502 *
1503 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1504 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1505 * If link is down, the function will restore the default K1 setting located
1506 * in the NVM.
1507 **/
1508 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1509 {
1510 s32 ret_val = 0;
1511 u16 status_reg = 0;
1512 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1513
1514 if (hw->mac.type != e1000_pchlan)
1515 return 0;
1516
1517 /* Wrap the whole flow with the sw flag */
1518 ret_val = hw->phy.ops.acquire(hw);
1519 if (ret_val)
1520 return ret_val;
1521
1522 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1523 if (link) {
1524 if (hw->phy.type == e1000_phy_82578) {
1525 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
1526 &status_reg);
1527 if (ret_val)
1528 goto release;
1529
1530 status_reg &= BM_CS_STATUS_LINK_UP |
1531 BM_CS_STATUS_RESOLVED |
1532 BM_CS_STATUS_SPEED_MASK;
1533
1534 if (status_reg == (BM_CS_STATUS_LINK_UP |
1535 BM_CS_STATUS_RESOLVED |
1536 BM_CS_STATUS_SPEED_1000))
1537 k1_enable = false;
1538 }
1539
1540 if (hw->phy.type == e1000_phy_82577) {
1541 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
1542 if (ret_val)
1543 goto release;
1544
1545 status_reg &= HV_M_STATUS_LINK_UP |
1546 HV_M_STATUS_AUTONEG_COMPLETE |
1547 HV_M_STATUS_SPEED_MASK;
1548
1549 if (status_reg == (HV_M_STATUS_LINK_UP |
1550 HV_M_STATUS_AUTONEG_COMPLETE |
1551 HV_M_STATUS_SPEED_1000))
1552 k1_enable = false;
1553 }
1554
1555 /* Link stall fix for link up */
1556 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
1557 if (ret_val)
1558 goto release;
1559
1560 } else {
1561 /* Link stall fix for link down */
1562 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
1563 if (ret_val)
1564 goto release;
1565 }
1566
1567 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1568
1569 release:
1570 hw->phy.ops.release(hw);
1571
1572 return ret_val;
1573 }
1574
1575 /**
1576 * e1000_configure_k1_ich8lan - Configure K1 power state
1577 * @hw: pointer to the HW structure
1578 * @enable: K1 state to configure
1579 *
1580 * Configure the K1 power state based on the provided parameter.
1581 * Assumes semaphore already acquired.
1582 *
1583 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1584 **/
1585 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1586 {
1587 s32 ret_val = 0;
1588 u32 ctrl_reg = 0;
1589 u32 ctrl_ext = 0;
1590 u32 reg = 0;
1591 u16 kmrn_reg = 0;
1592
1593 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1594 &kmrn_reg);
1595 if (ret_val)
1596 return ret_val;
1597
1598 if (k1_enable)
1599 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1600 else
1601 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1602
1603 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1604 kmrn_reg);
1605 if (ret_val)
1606 return ret_val;
1607
1608 udelay(20);
1609 ctrl_ext = er32(CTRL_EXT);
1610 ctrl_reg = er32(CTRL);
1611
1612 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1613 reg |= E1000_CTRL_FRCSPD;
1614 ew32(CTRL, reg);
1615
1616 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1617 e1e_flush();
1618 udelay(20);
1619 ew32(CTRL, ctrl_reg);
1620 ew32(CTRL_EXT, ctrl_ext);
1621 e1e_flush();
1622 udelay(20);
1623
1624 return 0;
1625 }
1626
1627 /**
1628 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1629 * @hw: pointer to the HW structure
1630 * @d0_state: boolean if entering d0 or d3 device state
1631 *
1632 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1633 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1634 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1635 **/
1636 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1637 {
1638 s32 ret_val = 0;
1639 u32 mac_reg;
1640 u16 oem_reg;
1641
1642 if (hw->mac.type < e1000_pchlan)
1643 return ret_val;
1644
1645 ret_val = hw->phy.ops.acquire(hw);
1646 if (ret_val)
1647 return ret_val;
1648
1649 if (hw->mac.type == e1000_pchlan) {
1650 mac_reg = er32(EXTCNF_CTRL);
1651 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1652 goto release;
1653 }
1654
1655 mac_reg = er32(FEXTNVM);
1656 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1657 goto release;
1658
1659 mac_reg = er32(PHY_CTRL);
1660
1661 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
1662 if (ret_val)
1663 goto release;
1664
1665 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1666
1667 if (d0_state) {
1668 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1669 oem_reg |= HV_OEM_BITS_GBE_DIS;
1670
1671 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1672 oem_reg |= HV_OEM_BITS_LPLU;
1673 } else {
1674 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1675 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1676 oem_reg |= HV_OEM_BITS_GBE_DIS;
1677
1678 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1679 E1000_PHY_CTRL_NOND0A_LPLU))
1680 oem_reg |= HV_OEM_BITS_LPLU;
1681 }
1682
1683 /* Set Restart auto-neg to activate the bits */
1684 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
1685 !hw->phy.ops.check_reset_block(hw))
1686 oem_reg |= HV_OEM_BITS_RESTART_AN;
1687
1688 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
1689
1690 release:
1691 hw->phy.ops.release(hw);
1692
1693 return ret_val;
1694 }
1695
1696
1697 /**
1698 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1699 * @hw: pointer to the HW structure
1700 **/
1701 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1702 {
1703 s32 ret_val;
1704 u16 data;
1705
1706 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1707 if (ret_val)
1708 return ret_val;
1709
1710 data |= HV_KMRN_MDIO_SLOW;
1711
1712 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1713
1714 return ret_val;
1715 }
1716
1717 /**
1718 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1719 * done after every PHY reset.
1720 **/
1721 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1722 {
1723 s32 ret_val = 0;
1724 u16 phy_data;
1725
1726 if (hw->mac.type != e1000_pchlan)
1727 return 0;
1728
1729 /* Set MDIO slow mode before any other MDIO access */
1730 if (hw->phy.type == e1000_phy_82577) {
1731 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1732 if (ret_val)
1733 return ret_val;
1734 }
1735
1736 if (((hw->phy.type == e1000_phy_82577) &&
1737 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1738 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1739 /* Disable generation of early preamble */
1740 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1741 if (ret_val)
1742 return ret_val;
1743
1744 /* Preamble tuning for SSC */
1745 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
1746 if (ret_val)
1747 return ret_val;
1748 }
1749
1750 if (hw->phy.type == e1000_phy_82578) {
1751 /*
1752 * Return registers to default by doing a soft reset then
1753 * writing 0x3140 to the control register.
1754 */
1755 if (hw->phy.revision < 2) {
1756 e1000e_phy_sw_reset(hw);
1757 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1758 }
1759 }
1760
1761 /* Select page 0 */
1762 ret_val = hw->phy.ops.acquire(hw);
1763 if (ret_val)
1764 return ret_val;
1765
1766 hw->phy.addr = 1;
1767 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1768 hw->phy.ops.release(hw);
1769 if (ret_val)
1770 return ret_val;
1771
1772 /*
1773 * Configure the K1 Si workaround during phy reset assuming there is
1774 * link so that it disables K1 if link is in 1Gbps.
1775 */
1776 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1777 if (ret_val)
1778 return ret_val;
1779
1780 /* Workaround for link disconnects on a busy hub in half duplex */
1781 ret_val = hw->phy.ops.acquire(hw);
1782 if (ret_val)
1783 return ret_val;
1784 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1785 if (ret_val)
1786 goto release;
1787 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
1788 release:
1789 hw->phy.ops.release(hw);
1790
1791 return ret_val;
1792 }
1793
1794 /**
1795 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1796 * @hw: pointer to the HW structure
1797 **/
1798 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1799 {
1800 u32 mac_reg;
1801 u16 i, phy_reg = 0;
1802 s32 ret_val;
1803
1804 ret_val = hw->phy.ops.acquire(hw);
1805 if (ret_val)
1806 return;
1807 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1808 if (ret_val)
1809 goto release;
1810
1811 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1812 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1813 mac_reg = er32(RAL(i));
1814 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1815 (u16)(mac_reg & 0xFFFF));
1816 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1817 (u16)((mac_reg >> 16) & 0xFFFF));
1818
1819 mac_reg = er32(RAH(i));
1820 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1821 (u16)(mac_reg & 0xFFFF));
1822 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1823 (u16)((mac_reg & E1000_RAH_AV)
1824 >> 16));
1825 }
1826
1827 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1828
1829 release:
1830 hw->phy.ops.release(hw);
1831 }
1832
1833 /**
1834 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1835 * with 82579 PHY
1836 * @hw: pointer to the HW structure
1837 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1838 **/
1839 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1840 {
1841 s32 ret_val = 0;
1842 u16 phy_reg, data;
1843 u32 mac_reg;
1844 u16 i;
1845
1846 if (hw->mac.type < e1000_pch2lan)
1847 return 0;
1848
1849 /* disable Rx path while enabling/disabling workaround */
1850 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1851 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1852 if (ret_val)
1853 return ret_val;
1854
1855 if (enable) {
1856 /*
1857 * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1858 * SHRAL/H) and initial CRC values to the MAC
1859 */
1860 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1861 u8 mac_addr[ETH_ALEN] = {0};
1862 u32 addr_high, addr_low;
1863
1864 addr_high = er32(RAH(i));
1865 if (!(addr_high & E1000_RAH_AV))
1866 continue;
1867 addr_low = er32(RAL(i));
1868 mac_addr[0] = (addr_low & 0xFF);
1869 mac_addr[1] = ((addr_low >> 8) & 0xFF);
1870 mac_addr[2] = ((addr_low >> 16) & 0xFF);
1871 mac_addr[3] = ((addr_low >> 24) & 0xFF);
1872 mac_addr[4] = (addr_high & 0xFF);
1873 mac_addr[5] = ((addr_high >> 8) & 0xFF);
1874
1875 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1876 }
1877
1878 /* Write Rx addresses to the PHY */
1879 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1880
1881 /* Enable jumbo frame workaround in the MAC */
1882 mac_reg = er32(FFLT_DBG);
1883 mac_reg &= ~(1 << 14);
1884 mac_reg |= (7 << 15);
1885 ew32(FFLT_DBG, mac_reg);
1886
1887 mac_reg = er32(RCTL);
1888 mac_reg |= E1000_RCTL_SECRC;
1889 ew32(RCTL, mac_reg);
1890
1891 ret_val = e1000e_read_kmrn_reg(hw,
1892 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1893 &data);
1894 if (ret_val)
1895 return ret_val;
1896 ret_val = e1000e_write_kmrn_reg(hw,
1897 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1898 data | (1 << 0));
1899 if (ret_val)
1900 return ret_val;
1901 ret_val = e1000e_read_kmrn_reg(hw,
1902 E1000_KMRNCTRLSTA_HD_CTRL,
1903 &data);
1904 if (ret_val)
1905 return ret_val;
1906 data &= ~(0xF << 8);
1907 data |= (0xB << 8);
1908 ret_val = e1000e_write_kmrn_reg(hw,
1909 E1000_KMRNCTRLSTA_HD_CTRL,
1910 data);
1911 if (ret_val)
1912 return ret_val;
1913
1914 /* Enable jumbo frame workaround in the PHY */
1915 e1e_rphy(hw, PHY_REG(769, 23), &data);
1916 data &= ~(0x7F << 5);
1917 data |= (0x37 << 5);
1918 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1919 if (ret_val)
1920 return ret_val;
1921 e1e_rphy(hw, PHY_REG(769, 16), &data);
1922 data &= ~(1 << 13);
1923 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1924 if (ret_val)
1925 return ret_val;
1926 e1e_rphy(hw, PHY_REG(776, 20), &data);
1927 data &= ~(0x3FF << 2);
1928 data |= (0x1A << 2);
1929 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1930 if (ret_val)
1931 return ret_val;
1932 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
1933 if (ret_val)
1934 return ret_val;
1935 e1e_rphy(hw, HV_PM_CTRL, &data);
1936 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1937 if (ret_val)
1938 return ret_val;
1939 } else {
1940 /* Write MAC register values back to h/w defaults */
1941 mac_reg = er32(FFLT_DBG);
1942 mac_reg &= ~(0xF << 14);
1943 ew32(FFLT_DBG, mac_reg);
1944
1945 mac_reg = er32(RCTL);
1946 mac_reg &= ~E1000_RCTL_SECRC;
1947 ew32(RCTL, mac_reg);
1948
1949 ret_val = e1000e_read_kmrn_reg(hw,
1950 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1951 &data);
1952 if (ret_val)
1953 return ret_val;
1954 ret_val = e1000e_write_kmrn_reg(hw,
1955 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1956 data & ~(1 << 0));
1957 if (ret_val)
1958 return ret_val;
1959 ret_val = e1000e_read_kmrn_reg(hw,
1960 E1000_KMRNCTRLSTA_HD_CTRL,
1961 &data);
1962 if (ret_val)
1963 return ret_val;
1964 data &= ~(0xF << 8);
1965 data |= (0xB << 8);
1966 ret_val = e1000e_write_kmrn_reg(hw,
1967 E1000_KMRNCTRLSTA_HD_CTRL,
1968 data);
1969 if (ret_val)
1970 return ret_val;
1971
1972 /* Write PHY register values back to h/w defaults */
1973 e1e_rphy(hw, PHY_REG(769, 23), &data);
1974 data &= ~(0x7F << 5);
1975 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1976 if (ret_val)
1977 return ret_val;
1978 e1e_rphy(hw, PHY_REG(769, 16), &data);
1979 data |= (1 << 13);
1980 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1981 if (ret_val)
1982 return ret_val;
1983 e1e_rphy(hw, PHY_REG(776, 20), &data);
1984 data &= ~(0x3FF << 2);
1985 data |= (0x8 << 2);
1986 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1987 if (ret_val)
1988 return ret_val;
1989 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1990 if (ret_val)
1991 return ret_val;
1992 e1e_rphy(hw, HV_PM_CTRL, &data);
1993 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1994 if (ret_val)
1995 return ret_val;
1996 }
1997
1998 /* re-enable Rx path after enabling/disabling workaround */
1999 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
2000 }
2001
2002 /**
2003 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2004 * done after every PHY reset.
2005 **/
2006 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2007 {
2008 s32 ret_val = 0;
2009
2010 if (hw->mac.type != e1000_pch2lan)
2011 return 0;
2012
2013 /* Set MDIO slow mode before any other MDIO access */
2014 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2015
2016 ret_val = hw->phy.ops.acquire(hw);
2017 if (ret_val)
2018 return ret_val;
2019 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, I82579_MSE_THRESHOLD);
2020 if (ret_val)
2021 goto release;
2022 /* set MSE higher to enable link to stay up when noise is high */
2023 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, 0x0034);
2024 if (ret_val)
2025 goto release;
2026 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, I82579_MSE_LINK_DOWN);
2027 if (ret_val)
2028 goto release;
2029 /* drop link after 5 times MSE threshold was reached */
2030 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, 0x0005);
2031 release:
2032 hw->phy.ops.release(hw);
2033
2034 return ret_val;
2035 }
2036
2037 /**
2038 * e1000_k1_gig_workaround_lv - K1 Si workaround
2039 * @hw: pointer to the HW structure
2040 *
2041 * Workaround to set the K1 beacon duration for 82579 parts
2042 **/
2043 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2044 {
2045 s32 ret_val = 0;
2046 u16 status_reg = 0;
2047 u32 mac_reg;
2048 u16 phy_reg;
2049
2050 if (hw->mac.type != e1000_pch2lan)
2051 return 0;
2052
2053 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
2054 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2055 if (ret_val)
2056 return ret_val;
2057
2058 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2059 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2060 mac_reg = er32(FEXTNVM4);
2061 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2062
2063 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
2064 if (ret_val)
2065 return ret_val;
2066
2067 if (status_reg & HV_M_STATUS_SPEED_1000) {
2068 u16 pm_phy_reg;
2069
2070 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
2071 phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2072 /* LV 1G Packet drop issue wa */
2073 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2074 if (ret_val)
2075 return ret_val;
2076 pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
2077 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2078 if (ret_val)
2079 return ret_val;
2080 } else {
2081 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2082 phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2083 }
2084 ew32(FEXTNVM4, mac_reg);
2085 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
2086 }
2087
2088 return ret_val;
2089 }
2090
2091 /**
2092 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2093 * @hw: pointer to the HW structure
2094 * @gate: boolean set to true to gate, false to ungate
2095 *
2096 * Gate/ungate the automatic PHY configuration via hardware; perform
2097 * the configuration via software instead.
2098 **/
2099 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2100 {
2101 u32 extcnf_ctrl;
2102
2103 if (hw->mac.type < e1000_pch2lan)
2104 return;
2105
2106 extcnf_ctrl = er32(EXTCNF_CTRL);
2107
2108 if (gate)
2109 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2110 else
2111 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2112
2113 ew32(EXTCNF_CTRL, extcnf_ctrl);
2114 }
2115
2116 /**
2117 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2118 * @hw: pointer to the HW structure
2119 *
2120 * Check the appropriate indication the MAC has finished configuring the
2121 * PHY after a software reset.
2122 **/
2123 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2124 {
2125 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2126
2127 /* Wait for basic configuration completes before proceeding */
2128 do {
2129 data = er32(STATUS);
2130 data &= E1000_STATUS_LAN_INIT_DONE;
2131 udelay(100);
2132 } while ((!data) && --loop);
2133
2134 /*
2135 * If basic configuration is incomplete before the above loop
2136 * count reaches 0, loading the configuration from NVM will
2137 * leave the PHY in a bad state possibly resulting in no link.
2138 */
2139 if (loop == 0)
2140 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2141
2142 /* Clear the Init Done bit for the next init event */
2143 data = er32(STATUS);
2144 data &= ~E1000_STATUS_LAN_INIT_DONE;
2145 ew32(STATUS, data);
2146 }
2147
2148 /**
2149 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2150 * @hw: pointer to the HW structure
2151 **/
2152 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2153 {
2154 s32 ret_val = 0;
2155 u16 reg;
2156
2157 if (hw->phy.ops.check_reset_block(hw))
2158 return 0;
2159
2160 /* Allow time for h/w to get to quiescent state after reset */
2161 usleep_range(10000, 20000);
2162
2163 /* Perform any necessary post-reset workarounds */
2164 switch (hw->mac.type) {
2165 case e1000_pchlan:
2166 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2167 if (ret_val)
2168 return ret_val;
2169 break;
2170 case e1000_pch2lan:
2171 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2172 if (ret_val)
2173 return ret_val;
2174 break;
2175 default:
2176 break;
2177 }
2178
2179 /* Clear the host wakeup bit after lcd reset */
2180 if (hw->mac.type >= e1000_pchlan) {
2181 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2182 reg &= ~BM_WUC_HOST_WU_BIT;
2183 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2184 }
2185
2186 /* Configure the LCD with the extended configuration region in NVM */
2187 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2188 if (ret_val)
2189 return ret_val;
2190
2191 /* Configure the LCD with the OEM bits in NVM */
2192 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2193
2194 if (hw->mac.type == e1000_pch2lan) {
2195 /* Ungate automatic PHY configuration on non-managed 82579 */
2196 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2197 usleep_range(10000, 20000);
2198 e1000_gate_hw_phy_config_ich8lan(hw, false);
2199 }
2200
2201 /* Set EEE LPI Update Timer to 200usec */
2202 ret_val = hw->phy.ops.acquire(hw);
2203 if (ret_val)
2204 return ret_val;
2205 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR,
2206 I82579_LPI_UPDATE_TIMER);
2207 if (!ret_val)
2208 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, 0x1387);
2209 hw->phy.ops.release(hw);
2210 }
2211
2212 return ret_val;
2213 }
2214
2215 /**
2216 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2217 * @hw: pointer to the HW structure
2218 *
2219 * Resets the PHY
2220 * This is a function pointer entry point called by drivers
2221 * or other shared routines.
2222 **/
2223 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2224 {
2225 s32 ret_val = 0;
2226
2227 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2228 if ((hw->mac.type == e1000_pch2lan) &&
2229 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2230 e1000_gate_hw_phy_config_ich8lan(hw, true);
2231
2232 ret_val = e1000e_phy_hw_reset_generic(hw);
2233 if (ret_val)
2234 return ret_val;
2235
2236 return e1000_post_phy_reset_ich8lan(hw);
2237 }
2238
2239 /**
2240 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2241 * @hw: pointer to the HW structure
2242 * @active: true to enable LPLU, false to disable
2243 *
2244 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2245 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2246 * the phy speed. This function will manually set the LPLU bit and restart
2247 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2248 * since it configures the same bit.
2249 **/
2250 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2251 {
2252 s32 ret_val = 0;
2253 u16 oem_reg;
2254
2255 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2256 if (ret_val)
2257 return ret_val;
2258
2259 if (active)
2260 oem_reg |= HV_OEM_BITS_LPLU;
2261 else
2262 oem_reg &= ~HV_OEM_BITS_LPLU;
2263
2264 if (!hw->phy.ops.check_reset_block(hw))
2265 oem_reg |= HV_OEM_BITS_RESTART_AN;
2266
2267 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2268 }
2269
2270 /**
2271 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2272 * @hw: pointer to the HW structure
2273 * @active: true to enable LPLU, false to disable
2274 *
2275 * Sets the LPLU D0 state according to the active flag. When
2276 * activating LPLU this function also disables smart speed
2277 * and vice versa. LPLU will not be activated unless the
2278 * device autonegotiation advertisement meets standards of
2279 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2280 * This is a function pointer entry point only called by
2281 * PHY setup routines.
2282 **/
2283 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2284 {
2285 struct e1000_phy_info *phy = &hw->phy;
2286 u32 phy_ctrl;
2287 s32 ret_val = 0;
2288 u16 data;
2289
2290 if (phy->type == e1000_phy_ife)
2291 return 0;
2292
2293 phy_ctrl = er32(PHY_CTRL);
2294
2295 if (active) {
2296 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2297 ew32(PHY_CTRL, phy_ctrl);
2298
2299 if (phy->type != e1000_phy_igp_3)
2300 return 0;
2301
2302 /*
2303 * Call gig speed drop workaround on LPLU before accessing
2304 * any PHY registers
2305 */
2306 if (hw->mac.type == e1000_ich8lan)
2307 e1000e_gig_downshift_workaround_ich8lan(hw);
2308
2309 /* When LPLU is enabled, we should disable SmartSpeed */
2310 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2311 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2312 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2313 if (ret_val)
2314 return ret_val;
2315 } else {
2316 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2317 ew32(PHY_CTRL, phy_ctrl);
2318
2319 if (phy->type != e1000_phy_igp_3)
2320 return 0;
2321
2322 /*
2323 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
2324 * during Dx states where the power conservation is most
2325 * important. During driver activity we should enable
2326 * SmartSpeed, so performance is maintained.
2327 */
2328 if (phy->smart_speed == e1000_smart_speed_on) {
2329 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2330 &data);
2331 if (ret_val)
2332 return ret_val;
2333
2334 data |= IGP01E1000_PSCFR_SMART_SPEED;
2335 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2336 data);
2337 if (ret_val)
2338 return ret_val;
2339 } else if (phy->smart_speed == e1000_smart_speed_off) {
2340 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2341 &data);
2342 if (ret_val)
2343 return ret_val;
2344
2345 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2346 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2347 data);
2348 if (ret_val)
2349 return ret_val;
2350 }
2351 }
2352
2353 return 0;
2354 }
2355
2356 /**
2357 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2358 * @hw: pointer to the HW structure
2359 * @active: true to enable LPLU, false to disable
2360 *
2361 * Sets the LPLU D3 state according to the active flag. When
2362 * activating LPLU this function also disables smart speed
2363 * and vice versa. LPLU will not be activated unless the
2364 * device autonegotiation advertisement meets standards of
2365 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2366 * This is a function pointer entry point only called by
2367 * PHY setup routines.
2368 **/
2369 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2370 {
2371 struct e1000_phy_info *phy = &hw->phy;
2372 u32 phy_ctrl;
2373 s32 ret_val = 0;
2374 u16 data;
2375
2376 phy_ctrl = er32(PHY_CTRL);
2377
2378 if (!active) {
2379 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2380 ew32(PHY_CTRL, phy_ctrl);
2381
2382 if (phy->type != e1000_phy_igp_3)
2383 return 0;
2384
2385 /*
2386 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
2387 * during Dx states where the power conservation is most
2388 * important. During driver activity we should enable
2389 * SmartSpeed, so performance is maintained.
2390 */
2391 if (phy->smart_speed == e1000_smart_speed_on) {
2392 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2393 &data);
2394 if (ret_val)
2395 return ret_val;
2396
2397 data |= IGP01E1000_PSCFR_SMART_SPEED;
2398 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2399 data);
2400 if (ret_val)
2401 return ret_val;
2402 } else if (phy->smart_speed == e1000_smart_speed_off) {
2403 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2404 &data);
2405 if (ret_val)
2406 return ret_val;
2407
2408 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2409 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2410 data);
2411 if (ret_val)
2412 return ret_val;
2413 }
2414 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2415 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2416 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2417 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2418 ew32(PHY_CTRL, phy_ctrl);
2419
2420 if (phy->type != e1000_phy_igp_3)
2421 return 0;
2422
2423 /*
2424 * Call gig speed drop workaround on LPLU before accessing
2425 * any PHY registers
2426 */
2427 if (hw->mac.type == e1000_ich8lan)
2428 e1000e_gig_downshift_workaround_ich8lan(hw);
2429
2430 /* When LPLU is enabled, we should disable SmartSpeed */
2431 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2432 if (ret_val)
2433 return ret_val;
2434
2435 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2436 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2437 }
2438
2439 return ret_val;
2440 }
2441
2442 /**
2443 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2444 * @hw: pointer to the HW structure
2445 * @bank: pointer to the variable that returns the active bank
2446 *
2447 * Reads signature byte from the NVM using the flash access registers.
2448 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2449 **/
2450 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2451 {
2452 u32 eecd;
2453 struct e1000_nvm_info *nvm = &hw->nvm;
2454 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2455 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2456 u8 sig_byte = 0;
2457 s32 ret_val;
2458
2459 switch (hw->mac.type) {
2460 case e1000_ich8lan:
2461 case e1000_ich9lan:
2462 eecd = er32(EECD);
2463 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2464 E1000_EECD_SEC1VAL_VALID_MASK) {
2465 if (eecd & E1000_EECD_SEC1VAL)
2466 *bank = 1;
2467 else
2468 *bank = 0;
2469
2470 return 0;
2471 }
2472 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2473 /* fall-thru */
2474 default:
2475 /* set bank to 0 in case flash read fails */
2476 *bank = 0;
2477
2478 /* Check bank 0 */
2479 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2480 &sig_byte);
2481 if (ret_val)
2482 return ret_val;
2483 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2484 E1000_ICH_NVM_SIG_VALUE) {
2485 *bank = 0;
2486 return 0;
2487 }
2488
2489 /* Check bank 1 */
2490 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2491 bank1_offset,
2492 &sig_byte);
2493 if (ret_val)
2494 return ret_val;
2495 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2496 E1000_ICH_NVM_SIG_VALUE) {
2497 *bank = 1;
2498 return 0;
2499 }
2500
2501 e_dbg("ERROR: No valid NVM bank present\n");
2502 return -E1000_ERR_NVM;
2503 }
2504 }
2505
2506 /**
2507 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
2508 * @hw: pointer to the HW structure
2509 * @offset: The offset (in bytes) of the word(s) to read.
2510 * @words: Size of data to read in words
2511 * @data: Pointer to the word(s) to read at offset.
2512 *
2513 * Reads a word(s) from the NVM using the flash access registers.
2514 **/
2515 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2516 u16 *data)
2517 {
2518 struct e1000_nvm_info *nvm = &hw->nvm;
2519 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2520 u32 act_offset;
2521 s32 ret_val = 0;
2522 u32 bank = 0;
2523 u16 i, word;
2524
2525 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2526 (words == 0)) {
2527 e_dbg("nvm parameter(s) out of bounds\n");
2528 ret_val = -E1000_ERR_NVM;
2529 goto out;
2530 }
2531
2532 nvm->ops.acquire(hw);
2533
2534 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2535 if (ret_val) {
2536 e_dbg("Could not detect valid bank, assuming bank 0\n");
2537 bank = 0;
2538 }
2539
2540 act_offset = (bank) ? nvm->flash_bank_size : 0;
2541 act_offset += offset;
2542
2543 ret_val = 0;
2544 for (i = 0; i < words; i++) {
2545 if (dev_spec->shadow_ram[offset+i].modified) {
2546 data[i] = dev_spec->shadow_ram[offset+i].value;
2547 } else {
2548 ret_val = e1000_read_flash_word_ich8lan(hw,
2549 act_offset + i,
2550 &word);
2551 if (ret_val)
2552 break;
2553 data[i] = word;
2554 }
2555 }
2556
2557 nvm->ops.release(hw);
2558
2559 out:
2560 if (ret_val)
2561 e_dbg("NVM read error: %d\n", ret_val);
2562
2563 return ret_val;
2564 }
2565
2566 /**
2567 * e1000_flash_cycle_init_ich8lan - Initialize flash
2568 * @hw: pointer to the HW structure
2569 *
2570 * This function does initial flash setup so that a new read/write/erase cycle
2571 * can be started.
2572 **/
2573 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2574 {
2575 union ich8_hws_flash_status hsfsts;
2576 s32 ret_val = -E1000_ERR_NVM;
2577
2578 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2579
2580 /* Check if the flash descriptor is valid */
2581 if (!hsfsts.hsf_status.fldesvalid) {
2582 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
2583 return -E1000_ERR_NVM;
2584 }
2585
2586 /* Clear FCERR and DAEL in hw status by writing 1 */
2587 hsfsts.hsf_status.flcerr = 1;
2588 hsfsts.hsf_status.dael = 1;
2589
2590 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2591
2592 /*
2593 * Either we should have a hardware SPI cycle in progress
2594 * bit to check against, in order to start a new cycle or
2595 * FDONE bit should be changed in the hardware so that it
2596 * is 1 after hardware reset, which can then be used as an
2597 * indication whether a cycle is in progress or has been
2598 * completed.
2599 */
2600
2601 if (!hsfsts.hsf_status.flcinprog) {
2602 /*
2603 * There is no cycle running at present,
2604 * so we can start a cycle.
2605 * Begin by setting Flash Cycle Done.
2606 */
2607 hsfsts.hsf_status.flcdone = 1;
2608 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2609 ret_val = 0;
2610 } else {
2611 s32 i;
2612
2613 /*
2614 * Otherwise poll for sometime so the current
2615 * cycle has a chance to end before giving up.
2616 */
2617 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2618 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2619 if (!hsfsts.hsf_status.flcinprog) {
2620 ret_val = 0;
2621 break;
2622 }
2623 udelay(1);
2624 }
2625 if (!ret_val) {
2626 /*
2627 * Successful in waiting for previous cycle to timeout,
2628 * now set the Flash Cycle Done.
2629 */
2630 hsfsts.hsf_status.flcdone = 1;
2631 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2632 } else {
2633 e_dbg("Flash controller busy, cannot get access\n");
2634 }
2635 }
2636
2637 return ret_val;
2638 }
2639
2640 /**
2641 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2642 * @hw: pointer to the HW structure
2643 * @timeout: maximum time to wait for completion
2644 *
2645 * This function starts a flash cycle and waits for its completion.
2646 **/
2647 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2648 {
2649 union ich8_hws_flash_ctrl hsflctl;
2650 union ich8_hws_flash_status hsfsts;
2651 u32 i = 0;
2652
2653 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2654 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2655 hsflctl.hsf_ctrl.flcgo = 1;
2656 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2657
2658 /* wait till FDONE bit is set to 1 */
2659 do {
2660 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2661 if (hsfsts.hsf_status.flcdone)
2662 break;
2663 udelay(1);
2664 } while (i++ < timeout);
2665
2666 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
2667 return 0;
2668
2669 return -E1000_ERR_NVM;
2670 }
2671
2672 /**
2673 * e1000_read_flash_word_ich8lan - Read word from flash
2674 * @hw: pointer to the HW structure
2675 * @offset: offset to data location
2676 * @data: pointer to the location for storing the data
2677 *
2678 * Reads the flash word at offset into data. Offset is converted
2679 * to bytes before read.
2680 **/
2681 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2682 u16 *data)
2683 {
2684 /* Must convert offset into bytes. */
2685 offset <<= 1;
2686
2687 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2688 }
2689
2690 /**
2691 * e1000_read_flash_byte_ich8lan - Read byte from flash
2692 * @hw: pointer to the HW structure
2693 * @offset: The offset of the byte to read.
2694 * @data: Pointer to a byte to store the value read.
2695 *
2696 * Reads a single byte from the NVM using the flash access registers.
2697 **/
2698 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2699 u8 *data)
2700 {
2701 s32 ret_val;
2702 u16 word = 0;
2703
2704 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2705 if (ret_val)
2706 return ret_val;
2707
2708 *data = (u8)word;
2709
2710 return 0;
2711 }
2712
2713 /**
2714 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2715 * @hw: pointer to the HW structure
2716 * @offset: The offset (in bytes) of the byte or word to read.
2717 * @size: Size of data to read, 1=byte 2=word
2718 * @data: Pointer to the word to store the value read.
2719 *
2720 * Reads a byte or word from the NVM using the flash access registers.
2721 **/
2722 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2723 u8 size, u16 *data)
2724 {
2725 union ich8_hws_flash_status hsfsts;
2726 union ich8_hws_flash_ctrl hsflctl;
2727 u32 flash_linear_addr;
2728 u32 flash_data = 0;
2729 s32 ret_val = -E1000_ERR_NVM;
2730 u8 count = 0;
2731
2732 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2733 return -E1000_ERR_NVM;
2734
2735 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2736 hw->nvm.flash_base_addr;
2737
2738 do {
2739 udelay(1);
2740 /* Steps */
2741 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2742 if (ret_val)
2743 break;
2744
2745 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2746 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2747 hsflctl.hsf_ctrl.fldbcount = size - 1;
2748 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2749 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2750
2751 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2752
2753 ret_val = e1000_flash_cycle_ich8lan(hw,
2754 ICH_FLASH_READ_COMMAND_TIMEOUT);
2755
2756 /*
2757 * Check if FCERR is set to 1, if set to 1, clear it
2758 * and try the whole sequence a few more times, else
2759 * read in (shift in) the Flash Data0, the order is
2760 * least significant byte first msb to lsb
2761 */
2762 if (!ret_val) {
2763 flash_data = er32flash(ICH_FLASH_FDATA0);
2764 if (size == 1)
2765 *data = (u8)(flash_data & 0x000000FF);
2766 else if (size == 2)
2767 *data = (u16)(flash_data & 0x0000FFFF);
2768 break;
2769 } else {
2770 /*
2771 * If we've gotten here, then things are probably
2772 * completely hosed, but if the error condition is
2773 * detected, it won't hurt to give it another try...
2774 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2775 */
2776 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2777 if (hsfsts.hsf_status.flcerr) {
2778 /* Repeat for some time before giving up. */
2779 continue;
2780 } else if (!hsfsts.hsf_status.flcdone) {
2781 e_dbg("Timeout error - flash cycle did not complete.\n");
2782 break;
2783 }
2784 }
2785 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2786
2787 return ret_val;
2788 }
2789
2790 /**
2791 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2792 * @hw: pointer to the HW structure
2793 * @offset: The offset (in bytes) of the word(s) to write.
2794 * @words: Size of data to write in words
2795 * @data: Pointer to the word(s) to write at offset.
2796 *
2797 * Writes a byte or word to the NVM using the flash access registers.
2798 **/
2799 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2800 u16 *data)
2801 {
2802 struct e1000_nvm_info *nvm = &hw->nvm;
2803 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2804 u16 i;
2805
2806 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2807 (words == 0)) {
2808 e_dbg("nvm parameter(s) out of bounds\n");
2809 return -E1000_ERR_NVM;
2810 }
2811
2812 nvm->ops.acquire(hw);
2813
2814 for (i = 0; i < words; i++) {
2815 dev_spec->shadow_ram[offset+i].modified = true;
2816 dev_spec->shadow_ram[offset+i].value = data[i];
2817 }
2818
2819 nvm->ops.release(hw);
2820
2821 return 0;
2822 }
2823
2824 /**
2825 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2826 * @hw: pointer to the HW structure
2827 *
2828 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2829 * which writes the checksum to the shadow ram. The changes in the shadow
2830 * ram are then committed to the EEPROM by processing each bank at a time
2831 * checking for the modified bit and writing only the pending changes.
2832 * After a successful commit, the shadow ram is cleared and is ready for
2833 * future writes.
2834 **/
2835 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2836 {
2837 struct e1000_nvm_info *nvm = &hw->nvm;
2838 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2839 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2840 s32 ret_val;
2841 u16 data;
2842
2843 ret_val = e1000e_update_nvm_checksum_generic(hw);
2844 if (ret_val)
2845 goto out;
2846
2847 if (nvm->type != e1000_nvm_flash_sw)
2848 goto out;
2849
2850 nvm->ops.acquire(hw);
2851
2852 /*
2853 * We're writing to the opposite bank so if we're on bank 1,
2854 * write to bank 0 etc. We also need to erase the segment that
2855 * is going to be written
2856 */
2857 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2858 if (ret_val) {
2859 e_dbg("Could not detect valid bank, assuming bank 0\n");
2860 bank = 0;
2861 }
2862
2863 if (bank == 0) {
2864 new_bank_offset = nvm->flash_bank_size;
2865 old_bank_offset = 0;
2866 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2867 if (ret_val)
2868 goto release;
2869 } else {
2870 old_bank_offset = nvm->flash_bank_size;
2871 new_bank_offset = 0;
2872 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2873 if (ret_val)
2874 goto release;
2875 }
2876
2877 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2878 /*
2879 * Determine whether to write the value stored
2880 * in the other NVM bank or a modified value stored
2881 * in the shadow RAM
2882 */
2883 if (dev_spec->shadow_ram[i].modified) {
2884 data = dev_spec->shadow_ram[i].value;
2885 } else {
2886 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2887 old_bank_offset,
2888 &data);
2889 if (ret_val)
2890 break;
2891 }
2892
2893 /*
2894 * If the word is 0x13, then make sure the signature bits
2895 * (15:14) are 11b until the commit has completed.
2896 * This will allow us to write 10b which indicates the
2897 * signature is valid. We want to do this after the write
2898 * has completed so that we don't mark the segment valid
2899 * while the write is still in progress
2900 */
2901 if (i == E1000_ICH_NVM_SIG_WORD)
2902 data |= E1000_ICH_NVM_SIG_MASK;
2903
2904 /* Convert offset to bytes. */
2905 act_offset = (i + new_bank_offset) << 1;
2906
2907 udelay(100);
2908 /* Write the bytes to the new bank. */
2909 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2910 act_offset,
2911 (u8)data);
2912 if (ret_val)
2913 break;
2914
2915 udelay(100);
2916 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2917 act_offset + 1,
2918 (u8)(data >> 8));
2919 if (ret_val)
2920 break;
2921 }
2922
2923 /*
2924 * Don't bother writing the segment valid bits if sector
2925 * programming failed.
2926 */
2927 if (ret_val) {
2928 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2929 e_dbg("Flash commit failed.\n");
2930 goto release;
2931 }
2932
2933 /*
2934 * Finally validate the new segment by setting bit 15:14
2935 * to 10b in word 0x13 , this can be done without an
2936 * erase as well since these bits are 11 to start with
2937 * and we need to change bit 14 to 0b
2938 */
2939 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2940 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2941 if (ret_val)
2942 goto release;
2943
2944 data &= 0xBFFF;
2945 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2946 act_offset * 2 + 1,
2947 (u8)(data >> 8));
2948 if (ret_val)
2949 goto release;
2950
2951 /*
2952 * And invalidate the previously valid segment by setting
2953 * its signature word (0x13) high_byte to 0b. This can be
2954 * done without an erase because flash erase sets all bits
2955 * to 1's. We can write 1's to 0's without an erase
2956 */
2957 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2958 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2959 if (ret_val)
2960 goto release;
2961
2962 /* Great! Everything worked, we can now clear the cached entries. */
2963 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2964 dev_spec->shadow_ram[i].modified = false;
2965 dev_spec->shadow_ram[i].value = 0xFFFF;
2966 }
2967
2968 release:
2969 nvm->ops.release(hw);
2970
2971 /*
2972 * Reload the EEPROM, or else modifications will not appear
2973 * until after the next adapter reset.
2974 */
2975 if (!ret_val) {
2976 nvm->ops.reload(hw);
2977 usleep_range(10000, 20000);
2978 }
2979
2980 out:
2981 if (ret_val)
2982 e_dbg("NVM update error: %d\n", ret_val);
2983
2984 return ret_val;
2985 }
2986
2987 /**
2988 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2989 * @hw: pointer to the HW structure
2990 *
2991 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2992 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2993 * calculated, in which case we need to calculate the checksum and set bit 6.
2994 **/
2995 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2996 {
2997 s32 ret_val;
2998 u16 data;
2999
3000 /*
3001 * Read 0x19 and check bit 6. If this bit is 0, the checksum
3002 * needs to be fixed. This bit is an indication that the NVM
3003 * was prepared by OEM software and did not calculate the
3004 * checksum...a likely scenario.
3005 */
3006 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
3007 if (ret_val)
3008 return ret_val;
3009
3010 if (!(data & 0x40)) {
3011 data |= 0x40;
3012 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
3013 if (ret_val)
3014 return ret_val;
3015 ret_val = e1000e_update_nvm_checksum(hw);
3016 if (ret_val)
3017 return ret_val;
3018 }
3019
3020 return e1000e_validate_nvm_checksum_generic(hw);
3021 }
3022
3023 /**
3024 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
3025 * @hw: pointer to the HW structure
3026 *
3027 * To prevent malicious write/erase of the NVM, set it to be read-only
3028 * so that the hardware ignores all write/erase cycles of the NVM via
3029 * the flash control registers. The shadow-ram copy of the NVM will
3030 * still be updated, however any updates to this copy will not stick
3031 * across driver reloads.
3032 **/
3033 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
3034 {
3035 struct e1000_nvm_info *nvm = &hw->nvm;
3036 union ich8_flash_protected_range pr0;
3037 union ich8_hws_flash_status hsfsts;
3038 u32 gfpreg;
3039
3040 nvm->ops.acquire(hw);
3041
3042 gfpreg = er32flash(ICH_FLASH_GFPREG);
3043
3044 /* Write-protect GbE Sector of NVM */
3045 pr0.regval = er32flash(ICH_FLASH_PR0);
3046 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
3047 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
3048 pr0.range.wpe = true;
3049 ew32flash(ICH_FLASH_PR0, pr0.regval);
3050
3051 /*
3052 * Lock down a subset of GbE Flash Control Registers, e.g.
3053 * PR0 to prevent the write-protection from being lifted.
3054 * Once FLOCKDN is set, the registers protected by it cannot
3055 * be written until FLOCKDN is cleared by a hardware reset.
3056 */
3057 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3058 hsfsts.hsf_status.flockdn = true;
3059 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3060
3061 nvm->ops.release(hw);
3062 }
3063
3064 /**
3065 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3066 * @hw: pointer to the HW structure
3067 * @offset: The offset (in bytes) of the byte/word to read.
3068 * @size: Size of data to read, 1=byte 2=word
3069 * @data: The byte(s) to write to the NVM.
3070 *
3071 * Writes one/two bytes to the NVM using the flash access registers.
3072 **/
3073 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3074 u8 size, u16 data)
3075 {
3076 union ich8_hws_flash_status hsfsts;
3077 union ich8_hws_flash_ctrl hsflctl;
3078 u32 flash_linear_addr;
3079 u32 flash_data = 0;
3080 s32 ret_val;
3081 u8 count = 0;
3082
3083 if (size < 1 || size > 2 || data > size * 0xff ||
3084 offset > ICH_FLASH_LINEAR_ADDR_MASK)
3085 return -E1000_ERR_NVM;
3086
3087 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3088 hw->nvm.flash_base_addr;
3089
3090 do {
3091 udelay(1);
3092 /* Steps */
3093 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3094 if (ret_val)
3095 break;
3096
3097 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3098 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3099 hsflctl.hsf_ctrl.fldbcount = size -1;
3100 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3101 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3102
3103 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3104
3105 if (size == 1)
3106 flash_data = (u32)data & 0x00FF;
3107 else
3108 flash_data = (u32)data;
3109
3110 ew32flash(ICH_FLASH_FDATA0, flash_data);
3111
3112 /*
3113 * check if FCERR is set to 1 , if set to 1, clear it
3114 * and try the whole sequence a few more times else done
3115 */
3116 ret_val = e1000_flash_cycle_ich8lan(hw,
3117 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3118 if (!ret_val)
3119 break;
3120
3121 /*
3122 * If we're here, then things are most likely
3123 * completely hosed, but if the error condition
3124 * is detected, it won't hurt to give it another
3125 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3126 */
3127 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3128 if (hsfsts.hsf_status.flcerr)
3129 /* Repeat for some time before giving up. */
3130 continue;
3131 if (!hsfsts.hsf_status.flcdone) {
3132 e_dbg("Timeout error - flash cycle did not complete.\n");
3133 break;
3134 }
3135 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3136
3137 return ret_val;
3138 }
3139
3140 /**
3141 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3142 * @hw: pointer to the HW structure
3143 * @offset: The index of the byte to read.
3144 * @data: The byte to write to the NVM.
3145 *
3146 * Writes a single byte to the NVM using the flash access registers.
3147 **/
3148 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3149 u8 data)
3150 {
3151 u16 word = (u16)data;
3152
3153 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3154 }
3155
3156 /**
3157 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3158 * @hw: pointer to the HW structure
3159 * @offset: The offset of the byte to write.
3160 * @byte: The byte to write to the NVM.
3161 *
3162 * Writes a single byte to the NVM using the flash access registers.
3163 * Goes through a retry algorithm before giving up.
3164 **/
3165 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3166 u32 offset, u8 byte)
3167 {
3168 s32 ret_val;
3169 u16 program_retries;
3170
3171 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3172 if (!ret_val)
3173 return ret_val;
3174
3175 for (program_retries = 0; program_retries < 100; program_retries++) {
3176 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
3177 udelay(100);
3178 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3179 if (!ret_val)
3180 break;
3181 }
3182 if (program_retries == 100)
3183 return -E1000_ERR_NVM;
3184
3185 return 0;
3186 }
3187
3188 /**
3189 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3190 * @hw: pointer to the HW structure
3191 * @bank: 0 for first bank, 1 for second bank, etc.
3192 *
3193 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3194 * bank N is 4096 * N + flash_reg_addr.
3195 **/
3196 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3197 {
3198 struct e1000_nvm_info *nvm = &hw->nvm;
3199 union ich8_hws_flash_status hsfsts;
3200 union ich8_hws_flash_ctrl hsflctl;
3201 u32 flash_linear_addr;
3202 /* bank size is in 16bit words - adjust to bytes */
3203 u32 flash_bank_size = nvm->flash_bank_size * 2;
3204 s32 ret_val;
3205 s32 count = 0;
3206 s32 j, iteration, sector_size;
3207
3208 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3209
3210 /*
3211 * Determine HW Sector size: Read BERASE bits of hw flash status
3212 * register
3213 * 00: The Hw sector is 256 bytes, hence we need to erase 16
3214 * consecutive sectors. The start index for the nth Hw sector
3215 * can be calculated as = bank * 4096 + n * 256
3216 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3217 * The start index for the nth Hw sector can be calculated
3218 * as = bank * 4096
3219 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3220 * (ich9 only, otherwise error condition)
3221 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3222 */
3223 switch (hsfsts.hsf_status.berasesz) {
3224 case 0:
3225 /* Hw sector size 256 */
3226 sector_size = ICH_FLASH_SEG_SIZE_256;
3227 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3228 break;
3229 case 1:
3230 sector_size = ICH_FLASH_SEG_SIZE_4K;
3231 iteration = 1;
3232 break;
3233 case 2:
3234 sector_size = ICH_FLASH_SEG_SIZE_8K;
3235 iteration = 1;
3236 break;
3237 case 3:
3238 sector_size = ICH_FLASH_SEG_SIZE_64K;
3239 iteration = 1;
3240 break;
3241 default:
3242 return -E1000_ERR_NVM;
3243 }
3244
3245 /* Start with the base address, then add the sector offset. */
3246 flash_linear_addr = hw->nvm.flash_base_addr;
3247 flash_linear_addr += (bank) ? flash_bank_size : 0;
3248
3249 for (j = 0; j < iteration ; j++) {
3250 do {
3251 /* Steps */
3252 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3253 if (ret_val)
3254 return ret_val;
3255
3256 /*
3257 * Write a value 11 (block Erase) in Flash
3258 * Cycle field in hw flash control
3259 */
3260 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3261 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3262 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3263
3264 /*
3265 * Write the last 24 bits of an index within the
3266 * block into Flash Linear address field in Flash
3267 * Address.
3268 */
3269 flash_linear_addr += (j * sector_size);
3270 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3271
3272 ret_val = e1000_flash_cycle_ich8lan(hw,
3273 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
3274 if (!ret_val)
3275 break;
3276
3277 /*
3278 * Check if FCERR is set to 1. If 1,
3279 * clear it and try the whole sequence
3280 * a few more times else Done
3281 */
3282 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3283 if (hsfsts.hsf_status.flcerr)
3284 /* repeat for some time before giving up */
3285 continue;
3286 else if (!hsfsts.hsf_status.flcdone)
3287 return ret_val;
3288 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3289 }
3290
3291 return 0;
3292 }
3293
3294 /**
3295 * e1000_valid_led_default_ich8lan - Set the default LED settings
3296 * @hw: pointer to the HW structure
3297 * @data: Pointer to the LED settings
3298 *
3299 * Reads the LED default settings from the NVM to data. If the NVM LED
3300 * settings is all 0's or F's, set the LED default to a valid LED default
3301 * setting.
3302 **/
3303 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3304 {
3305 s32 ret_val;
3306
3307 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
3308 if (ret_val) {
3309 e_dbg("NVM Read Error\n");
3310 return ret_val;
3311 }
3312
3313 if (*data == ID_LED_RESERVED_0000 ||
3314 *data == ID_LED_RESERVED_FFFF)
3315 *data = ID_LED_DEFAULT_ICH8LAN;
3316
3317 return 0;
3318 }
3319
3320 /**
3321 * e1000_id_led_init_pchlan - store LED configurations
3322 * @hw: pointer to the HW structure
3323 *
3324 * PCH does not control LEDs via the LEDCTL register, rather it uses
3325 * the PHY LED configuration register.
3326 *
3327 * PCH also does not have an "always on" or "always off" mode which
3328 * complicates the ID feature. Instead of using the "on" mode to indicate
3329 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
3330 * use "link_up" mode. The LEDs will still ID on request if there is no
3331 * link based on logic in e1000_led_[on|off]_pchlan().
3332 **/
3333 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3334 {
3335 struct e1000_mac_info *mac = &hw->mac;
3336 s32 ret_val;
3337 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3338 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3339 u16 data, i, temp, shift;
3340
3341 /* Get default ID LED modes */
3342 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3343 if (ret_val)
3344 return ret_val;
3345
3346 mac->ledctl_default = er32(LEDCTL);
3347 mac->ledctl_mode1 = mac->ledctl_default;
3348 mac->ledctl_mode2 = mac->ledctl_default;
3349
3350 for (i = 0; i < 4; i++) {
3351 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3352 shift = (i * 5);
3353 switch (temp) {
3354 case ID_LED_ON1_DEF2:
3355 case ID_LED_ON1_ON2:
3356 case ID_LED_ON1_OFF2:
3357 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3358 mac->ledctl_mode1 |= (ledctl_on << shift);
3359 break;
3360 case ID_LED_OFF1_DEF2:
3361 case ID_LED_OFF1_ON2:
3362 case ID_LED_OFF1_OFF2:
3363 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3364 mac->ledctl_mode1 |= (ledctl_off << shift);
3365 break;
3366 default:
3367 /* Do nothing */
3368 break;
3369 }
3370 switch (temp) {
3371 case ID_LED_DEF1_ON2:
3372 case ID_LED_ON1_ON2:
3373 case ID_LED_OFF1_ON2:
3374 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3375 mac->ledctl_mode2 |= (ledctl_on << shift);
3376 break;
3377 case ID_LED_DEF1_OFF2:
3378 case ID_LED_ON1_OFF2:
3379 case ID_LED_OFF1_OFF2:
3380 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3381 mac->ledctl_mode2 |= (ledctl_off << shift);
3382 break;
3383 default:
3384 /* Do nothing */
3385 break;
3386 }
3387 }
3388
3389 return 0;
3390 }
3391
3392 /**
3393 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3394 * @hw: pointer to the HW structure
3395 *
3396 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3397 * register, so the the bus width is hard coded.
3398 **/
3399 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3400 {
3401 struct e1000_bus_info *bus = &hw->bus;
3402 s32 ret_val;
3403
3404 ret_val = e1000e_get_bus_info_pcie(hw);
3405
3406 /*
3407 * ICH devices are "PCI Express"-ish. They have
3408 * a configuration space, but do not contain
3409 * PCI Express Capability registers, so bus width
3410 * must be hardcoded.
3411 */
3412 if (bus->width == e1000_bus_width_unknown)
3413 bus->width = e1000_bus_width_pcie_x1;
3414
3415 return ret_val;
3416 }
3417
3418 /**
3419 * e1000_reset_hw_ich8lan - Reset the hardware
3420 * @hw: pointer to the HW structure
3421 *
3422 * Does a full reset of the hardware which includes a reset of the PHY and
3423 * MAC.
3424 **/
3425 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3426 {
3427 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3428 u16 kum_cfg;
3429 u32 ctrl, reg;
3430 s32 ret_val;
3431
3432 /*
3433 * Prevent the PCI-E bus from sticking if there is no TLP connection
3434 * on the last TLP read/write transaction when MAC is reset.
3435 */
3436 ret_val = e1000e_disable_pcie_master(hw);
3437 if (ret_val)
3438 e_dbg("PCI-E Master disable polling has failed.\n");
3439
3440 e_dbg("Masking off all interrupts\n");
3441 ew32(IMC, 0xffffffff);
3442
3443 /*
3444 * Disable the Transmit and Receive units. Then delay to allow
3445 * any pending transactions to complete before we hit the MAC
3446 * with the global reset.
3447 */
3448 ew32(RCTL, 0);
3449 ew32(TCTL, E1000_TCTL_PSP);
3450 e1e_flush();
3451
3452 usleep_range(10000, 20000);
3453
3454 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3455 if (hw->mac.type == e1000_ich8lan) {
3456 /* Set Tx and Rx buffer allocation to 8k apiece. */
3457 ew32(PBA, E1000_PBA_8K);
3458 /* Set Packet Buffer Size to 16k. */
3459 ew32(PBS, E1000_PBS_16K);
3460 }
3461
3462 if (hw->mac.type == e1000_pchlan) {
3463 /* Save the NVM K1 bit setting */
3464 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
3465 if (ret_val)
3466 return ret_val;
3467
3468 if (kum_cfg & E1000_NVM_K1_ENABLE)
3469 dev_spec->nvm_k1_enabled = true;
3470 else
3471 dev_spec->nvm_k1_enabled = false;
3472 }
3473
3474 ctrl = er32(CTRL);
3475
3476 if (!hw->phy.ops.check_reset_block(hw)) {
3477 /*
3478 * Full-chip reset requires MAC and PHY reset at the same
3479 * time to make sure the interface between MAC and the
3480 * external PHY is reset.
3481 */
3482 ctrl |= E1000_CTRL_PHY_RST;
3483
3484 /*
3485 * Gate automatic PHY configuration by hardware on
3486 * non-managed 82579
3487 */
3488 if ((hw->mac.type == e1000_pch2lan) &&
3489 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3490 e1000_gate_hw_phy_config_ich8lan(hw, true);
3491 }
3492 ret_val = e1000_acquire_swflag_ich8lan(hw);
3493 e_dbg("Issuing a global reset to ich8lan\n");
3494 ew32(CTRL, (ctrl | E1000_CTRL_RST));
3495 /* cannot issue a flush here because it hangs the hardware */
3496 msleep(20);
3497
3498 /* Set Phy Config Counter to 50msec */
3499 if (hw->mac.type == e1000_pch2lan) {
3500 reg = er32(FEXTNVM3);
3501 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
3502 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
3503 ew32(FEXTNVM3, reg);
3504 }
3505
3506 if (!ret_val)
3507 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3508
3509 if (ctrl & E1000_CTRL_PHY_RST) {
3510 ret_val = hw->phy.ops.get_cfg_done(hw);
3511 if (ret_val)
3512 return ret_val;
3513
3514 ret_val = e1000_post_phy_reset_ich8lan(hw);
3515 if (ret_val)
3516 return ret_val;
3517 }
3518
3519 /*
3520 * For PCH, this write will make sure that any noise
3521 * will be detected as a CRC error and be dropped rather than show up
3522 * as a bad packet to the DMA engine.
3523 */
3524 if (hw->mac.type == e1000_pchlan)
3525 ew32(CRC_OFFSET, 0x65656565);
3526
3527 ew32(IMC, 0xffffffff);
3528 er32(ICR);
3529
3530 reg = er32(KABGTXD);
3531 reg |= E1000_KABGTXD_BGSQLBIAS;
3532 ew32(KABGTXD, reg);
3533
3534 return 0;
3535 }
3536
3537 /**
3538 * e1000_init_hw_ich8lan - Initialize the hardware
3539 * @hw: pointer to the HW structure
3540 *
3541 * Prepares the hardware for transmit and receive by doing the following:
3542 * - initialize hardware bits
3543 * - initialize LED identification
3544 * - setup receive address registers
3545 * - setup flow control
3546 * - setup transmit descriptors
3547 * - clear statistics
3548 **/
3549 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3550 {
3551 struct e1000_mac_info *mac = &hw->mac;
3552 u32 ctrl_ext, txdctl, snoop;
3553 s32 ret_val;
3554 u16 i;
3555
3556 e1000_initialize_hw_bits_ich8lan(hw);
3557
3558 /* Initialize identification LED */
3559 ret_val = mac->ops.id_led_init(hw);
3560 if (ret_val)
3561 e_dbg("Error initializing identification LED\n");
3562 /* This is not fatal and we should not stop init due to this */
3563
3564 /* Setup the receive address. */
3565 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3566
3567 /* Zero out the Multicast HASH table */
3568 e_dbg("Zeroing the MTA\n");
3569 for (i = 0; i < mac->mta_reg_count; i++)
3570 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3571
3572 /*
3573 * The 82578 Rx buffer will stall if wakeup is enabled in host and
3574 * the ME. Disable wakeup by clearing the host wakeup bit.
3575 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3576 */
3577 if (hw->phy.type == e1000_phy_82578) {
3578 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3579 i &= ~BM_WUC_HOST_WU_BIT;
3580 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3581 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3582 if (ret_val)
3583 return ret_val;
3584 }
3585
3586 /* Setup link and flow control */
3587 ret_val = mac->ops.setup_link(hw);
3588
3589 /* Set the transmit descriptor write-back policy for both queues */
3590 txdctl = er32(TXDCTL(0));
3591 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3592 E1000_TXDCTL_FULL_TX_DESC_WB;
3593 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3594 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3595 ew32(TXDCTL(0), txdctl);
3596 txdctl = er32(TXDCTL(1));
3597 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3598 E1000_TXDCTL_FULL_TX_DESC_WB;
3599 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3600 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3601 ew32(TXDCTL(1), txdctl);
3602
3603 /*
3604 * ICH8 has opposite polarity of no_snoop bits.
3605 * By default, we should use snoop behavior.
3606 */
3607 if (mac->type == e1000_ich8lan)
3608 snoop = PCIE_ICH8_SNOOP_ALL;
3609 else
3610 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3611 e1000e_set_pcie_no_snoop(hw, snoop);
3612
3613 ctrl_ext = er32(CTRL_EXT);
3614 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3615 ew32(CTRL_EXT, ctrl_ext);
3616
3617 /*
3618 * Clear all of the statistics registers (clear on read). It is
3619 * important that we do this after we have tried to establish link
3620 * because the symbol error count will increment wildly if there
3621 * is no link.
3622 */
3623 e1000_clear_hw_cntrs_ich8lan(hw);
3624
3625 return ret_val;
3626 }
3627 /**
3628 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3629 * @hw: pointer to the HW structure
3630 *
3631 * Sets/Clears required hardware bits necessary for correctly setting up the
3632 * hardware for transmit and receive.
3633 **/
3634 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3635 {
3636 u32 reg;
3637
3638 /* Extended Device Control */
3639 reg = er32(CTRL_EXT);
3640 reg |= (1 << 22);
3641 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3642 if (hw->mac.type >= e1000_pchlan)
3643 reg |= E1000_CTRL_EXT_PHYPDEN;
3644 ew32(CTRL_EXT, reg);
3645
3646 /* Transmit Descriptor Control 0 */
3647 reg = er32(TXDCTL(0));
3648 reg |= (1 << 22);
3649 ew32(TXDCTL(0), reg);
3650
3651 /* Transmit Descriptor Control 1 */
3652 reg = er32(TXDCTL(1));
3653 reg |= (1 << 22);
3654 ew32(TXDCTL(1), reg);
3655
3656 /* Transmit Arbitration Control 0 */
3657 reg = er32(TARC(0));
3658 if (hw->mac.type == e1000_ich8lan)
3659 reg |= (1 << 28) | (1 << 29);
3660 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3661 ew32(TARC(0), reg);
3662
3663 /* Transmit Arbitration Control 1 */
3664 reg = er32(TARC(1));
3665 if (er32(TCTL) & E1000_TCTL_MULR)
3666 reg &= ~(1 << 28);
3667 else
3668 reg |= (1 << 28);
3669 reg |= (1 << 24) | (1 << 26) | (1 << 30);
3670 ew32(TARC(1), reg);
3671
3672 /* Device Status */
3673 if (hw->mac.type == e1000_ich8lan) {
3674 reg = er32(STATUS);
3675 reg &= ~(1 << 31);
3676 ew32(STATUS, reg);
3677 }
3678
3679 /*
3680 * work-around descriptor data corruption issue during nfs v2 udp
3681 * traffic, just disable the nfs filtering capability
3682 */
3683 reg = er32(RFCTL);
3684 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3685
3686 /*
3687 * Disable IPv6 extension header parsing because some malformed
3688 * IPv6 headers can hang the Rx.
3689 */
3690 if (hw->mac.type == e1000_ich8lan)
3691 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
3692 ew32(RFCTL, reg);
3693 }
3694
3695 /**
3696 * e1000_setup_link_ich8lan - Setup flow control and link settings
3697 * @hw: pointer to the HW structure
3698 *
3699 * Determines which flow control settings to use, then configures flow
3700 * control. Calls the appropriate media-specific link configuration
3701 * function. Assuming the adapter has a valid link partner, a valid link
3702 * should be established. Assumes the hardware has previously been reset
3703 * and the transmitter and receiver are not enabled.
3704 **/
3705 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3706 {
3707 s32 ret_val;
3708
3709 if (hw->phy.ops.check_reset_block(hw))
3710 return 0;
3711
3712 /*
3713 * ICH parts do not have a word in the NVM to determine
3714 * the default flow control setting, so we explicitly
3715 * set it to full.
3716 */
3717 if (hw->fc.requested_mode == e1000_fc_default) {
3718 /* Workaround h/w hang when Tx flow control enabled */
3719 if (hw->mac.type == e1000_pchlan)
3720 hw->fc.requested_mode = e1000_fc_rx_pause;
3721 else
3722 hw->fc.requested_mode = e1000_fc_full;
3723 }
3724
3725 /*
3726 * Save off the requested flow control mode for use later. Depending
3727 * on the link partner's capabilities, we may or may not use this mode.
3728 */
3729 hw->fc.current_mode = hw->fc.requested_mode;
3730
3731 e_dbg("After fix-ups FlowControl is now = %x\n",
3732 hw->fc.current_mode);
3733
3734 /* Continue to configure the copper link. */
3735 ret_val = hw->mac.ops.setup_physical_interface(hw);
3736 if (ret_val)
3737 return ret_val;
3738
3739 ew32(FCTTV, hw->fc.pause_time);
3740 if ((hw->phy.type == e1000_phy_82578) ||
3741 (hw->phy.type == e1000_phy_82579) ||
3742 (hw->phy.type == e1000_phy_i217) ||
3743 (hw->phy.type == e1000_phy_82577)) {
3744 ew32(FCRTV_PCH, hw->fc.refresh_time);
3745
3746 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3747 hw->fc.pause_time);
3748 if (ret_val)
3749 return ret_val;
3750 }
3751
3752 return e1000e_set_fc_watermarks(hw);
3753 }
3754
3755 /**
3756 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3757 * @hw: pointer to the HW structure
3758 *
3759 * Configures the kumeran interface to the PHY to wait the appropriate time
3760 * when polling the PHY, then call the generic setup_copper_link to finish
3761 * configuring the copper link.
3762 **/
3763 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3764 {
3765 u32 ctrl;
3766 s32 ret_val;
3767 u16 reg_data;
3768
3769 ctrl = er32(CTRL);
3770 ctrl |= E1000_CTRL_SLU;
3771 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3772 ew32(CTRL, ctrl);
3773
3774 /*
3775 * Set the mac to wait the maximum time between each iteration
3776 * and increase the max iterations when polling the phy;
3777 * this fixes erroneous timeouts at 10Mbps.
3778 */
3779 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3780 if (ret_val)
3781 return ret_val;
3782 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3783 &reg_data);
3784 if (ret_val)
3785 return ret_val;
3786 reg_data |= 0x3F;
3787 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3788 reg_data);
3789 if (ret_val)
3790 return ret_val;
3791
3792 switch (hw->phy.type) {
3793 case e1000_phy_igp_3:
3794 ret_val = e1000e_copper_link_setup_igp(hw);
3795 if (ret_val)
3796 return ret_val;
3797 break;
3798 case e1000_phy_bm:
3799 case e1000_phy_82578:
3800 ret_val = e1000e_copper_link_setup_m88(hw);
3801 if (ret_val)
3802 return ret_val;
3803 break;
3804 case e1000_phy_82577:
3805 case e1000_phy_82579:
3806 case e1000_phy_i217:
3807 ret_val = e1000_copper_link_setup_82577(hw);
3808 if (ret_val)
3809 return ret_val;
3810 break;
3811 case e1000_phy_ife:
3812 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3813 if (ret_val)
3814 return ret_val;
3815
3816 reg_data &= ~IFE_PMC_AUTO_MDIX;
3817
3818 switch (hw->phy.mdix) {
3819 case 1:
3820 reg_data &= ~IFE_PMC_FORCE_MDIX;
3821 break;
3822 case 2:
3823 reg_data |= IFE_PMC_FORCE_MDIX;
3824 break;
3825 case 0:
3826 default:
3827 reg_data |= IFE_PMC_AUTO_MDIX;
3828 break;
3829 }
3830 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3831 if (ret_val)
3832 return ret_val;
3833 break;
3834 default:
3835 break;
3836 }
3837
3838 return e1000e_setup_copper_link(hw);
3839 }
3840
3841 /**
3842 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3843 * @hw: pointer to the HW structure
3844 * @speed: pointer to store current link speed
3845 * @duplex: pointer to store the current link duplex
3846 *
3847 * Calls the generic get_speed_and_duplex to retrieve the current link
3848 * information and then calls the Kumeran lock loss workaround for links at
3849 * gigabit speeds.
3850 **/
3851 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3852 u16 *duplex)
3853 {
3854 s32 ret_val;
3855
3856 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3857 if (ret_val)
3858 return ret_val;
3859
3860 if ((hw->mac.type == e1000_ich8lan) &&
3861 (hw->phy.type == e1000_phy_igp_3) &&
3862 (*speed == SPEED_1000)) {
3863 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3864 }
3865
3866 return ret_val;
3867 }
3868
3869 /**
3870 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3871 * @hw: pointer to the HW structure
3872 *
3873 * Work-around for 82566 Kumeran PCS lock loss:
3874 * On link status change (i.e. PCI reset, speed change) and link is up and
3875 * speed is gigabit-
3876 * 0) if workaround is optionally disabled do nothing
3877 * 1) wait 1ms for Kumeran link to come up
3878 * 2) check Kumeran Diagnostic register PCS lock loss bit
3879 * 3) if not set the link is locked (all is good), otherwise...
3880 * 4) reset the PHY
3881 * 5) repeat up to 10 times
3882 * Note: this is only called for IGP3 copper when speed is 1gb.
3883 **/
3884 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3885 {
3886 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3887 u32 phy_ctrl;
3888 s32 ret_val;
3889 u16 i, data;
3890 bool link;
3891
3892 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3893 return 0;
3894
3895 /*
3896 * Make sure link is up before proceeding. If not just return.
3897 * Attempting this while link is negotiating fouled up link
3898 * stability
3899 */
3900 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3901 if (!link)
3902 return 0;
3903
3904 for (i = 0; i < 10; i++) {
3905 /* read once to clear */
3906 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3907 if (ret_val)
3908 return ret_val;
3909 /* and again to get new status */
3910 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3911 if (ret_val)
3912 return ret_val;
3913
3914 /* check for PCS lock */
3915 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3916 return 0;
3917
3918 /* Issue PHY reset */
3919 e1000_phy_hw_reset(hw);
3920 mdelay(5);
3921 }
3922 /* Disable GigE link negotiation */
3923 phy_ctrl = er32(PHY_CTRL);
3924 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3925 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3926 ew32(PHY_CTRL, phy_ctrl);
3927
3928 /*
3929 * Call gig speed drop workaround on Gig disable before accessing
3930 * any PHY registers
3931 */
3932 e1000e_gig_downshift_workaround_ich8lan(hw);
3933
3934 /* unable to acquire PCS lock */
3935 return -E1000_ERR_PHY;
3936 }
3937
3938 /**
3939 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3940 * @hw: pointer to the HW structure
3941 * @state: boolean value used to set the current Kumeran workaround state
3942 *
3943 * If ICH8, set the current Kumeran workaround state (enabled - true
3944 * /disabled - false).
3945 **/
3946 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3947 bool state)
3948 {
3949 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3950
3951 if (hw->mac.type != e1000_ich8lan) {
3952 e_dbg("Workaround applies to ICH8 only.\n");
3953 return;
3954 }
3955
3956 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3957 }
3958
3959 /**
3960 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3961 * @hw: pointer to the HW structure
3962 *
3963 * Workaround for 82566 power-down on D3 entry:
3964 * 1) disable gigabit link
3965 * 2) write VR power-down enable
3966 * 3) read it back
3967 * Continue if successful, else issue LCD reset and repeat
3968 **/
3969 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3970 {
3971 u32 reg;
3972 u16 data;
3973 u8 retry = 0;
3974
3975 if (hw->phy.type != e1000_phy_igp_3)
3976 return;
3977
3978 /* Try the workaround twice (if needed) */
3979 do {
3980 /* Disable link */
3981 reg = er32(PHY_CTRL);
3982 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3983 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3984 ew32(PHY_CTRL, reg);
3985
3986 /*
3987 * Call gig speed drop workaround on Gig disable before
3988 * accessing any PHY registers
3989 */
3990 if (hw->mac.type == e1000_ich8lan)
3991 e1000e_gig_downshift_workaround_ich8lan(hw);
3992
3993 /* Write VR power-down enable */
3994 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3995 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3996 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3997
3998 /* Read it back and test */
3999 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4000 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4001 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4002 break;
4003
4004 /* Issue PHY reset and repeat at most one more time */
4005 reg = er32(CTRL);
4006 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
4007 retry++;
4008 } while (retry);
4009 }
4010
4011 /**
4012 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4013 * @hw: pointer to the HW structure
4014 *
4015 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4016 * LPLU, Gig disable, MDIC PHY reset):
4017 * 1) Set Kumeran Near-end loopback
4018 * 2) Clear Kumeran Near-end loopback
4019 * Should only be called for ICH8[m] devices with any 1G Phy.
4020 **/
4021 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4022 {
4023 s32 ret_val;
4024 u16 reg_data;
4025
4026 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
4027 return;
4028
4029 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4030 &reg_data);
4031 if (ret_val)
4032 return;
4033 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4034 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4035 reg_data);
4036 if (ret_val)
4037 return;
4038 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4039 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4040 reg_data);
4041 }
4042
4043 /**
4044 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4045 * @hw: pointer to the HW structure
4046 *
4047 * During S0 to Sx transition, it is possible the link remains at gig
4048 * instead of negotiating to a lower speed. Before going to Sx, set
4049 * 'Gig Disable' to force link speed negotiation to a lower speed based on
4050 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
4051 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4052 * needs to be written.
4053 * Parts that support (and are linked to a partner which support) EEE in
4054 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4055 * than 10Mbps w/o EEE.
4056 **/
4057 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4058 {
4059 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4060 u32 phy_ctrl;
4061 s32 ret_val;
4062
4063 phy_ctrl = er32(PHY_CTRL);
4064 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4065 if (hw->phy.type == e1000_phy_i217) {
4066 u16 phy_reg;
4067
4068 ret_val = hw->phy.ops.acquire(hw);
4069 if (ret_val)
4070 goto out;
4071
4072 if (!dev_spec->eee_disable) {
4073 u16 eee_advert;
4074
4075 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR,
4076 I217_EEE_ADVERTISEMENT);
4077 if (ret_val)
4078 goto release;
4079 e1e_rphy_locked(hw, I82579_EMI_DATA, &eee_advert);
4080
4081 /*
4082 * Disable LPLU if both link partners support 100BaseT
4083 * EEE and 100Full is advertised on both ends of the
4084 * link.
4085 */
4086 if ((eee_advert & I217_EEE_100_SUPPORTED) &&
4087 (dev_spec->eee_lp_ability &
4088 I217_EEE_100_SUPPORTED) &&
4089 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
4090 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4091 E1000_PHY_CTRL_NOND0A_LPLU);
4092 }
4093
4094 /*
4095 * For i217 Intel Rapid Start Technology support,
4096 * when the system is going into Sx and no manageability engine
4097 * is present, the driver must configure proxy to reset only on
4098 * power good. LPI (Low Power Idle) state must also reset only
4099 * on power good, as well as the MTA (Multicast table array).
4100 * The SMBus release must also be disabled on LCD reset.
4101 */
4102 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4103
4104 /* Enable proxy to reset only on power good. */
4105 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
4106 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4107 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
4108
4109 /*
4110 * Set bit enable LPI (EEE) to reset only on
4111 * power good.
4112 */
4113 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
4114 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4115 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
4116
4117 /* Disable the SMB release on LCD reset. */
4118 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4119 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4120 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4121 }
4122
4123 /*
4124 * Enable MTA to reset for Intel Rapid Start Technology
4125 * Support
4126 */
4127 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4128 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4129 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4130
4131 release:
4132 hw->phy.ops.release(hw);
4133 }
4134 out:
4135 ew32(PHY_CTRL, phy_ctrl);
4136
4137 if (hw->mac.type == e1000_ich8lan)
4138 e1000e_gig_downshift_workaround_ich8lan(hw);
4139
4140 if (hw->mac.type >= e1000_pchlan) {
4141 e1000_oem_bits_config_ich8lan(hw, false);
4142
4143 /* Reset PHY to activate OEM bits on 82577/8 */
4144 if (hw->mac.type == e1000_pchlan)
4145 e1000e_phy_hw_reset_generic(hw);
4146
4147 ret_val = hw->phy.ops.acquire(hw);
4148 if (ret_val)
4149 return;
4150 e1000_write_smbus_addr(hw);
4151 hw->phy.ops.release(hw);
4152 }
4153 }
4154
4155 /**
4156 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4157 * @hw: pointer to the HW structure
4158 *
4159 * During Sx to S0 transitions on non-managed devices or managed devices
4160 * on which PHY resets are not blocked, if the PHY registers cannot be
4161 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4162 * the PHY.
4163 * On i217, setup Intel Rapid Start Technology.
4164 **/
4165 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4166 {
4167 s32 ret_val;
4168
4169 if (hw->mac.type < e1000_pch2lan)
4170 return;
4171
4172 ret_val = e1000_init_phy_workarounds_pchlan(hw);
4173 if (ret_val) {
4174 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
4175 return;
4176 }
4177
4178 /*
4179 * For i217 Intel Rapid Start Technology support when the system
4180 * is transitioning from Sx and no manageability engine is present
4181 * configure SMBus to restore on reset, disable proxy, and enable
4182 * the reset on MTA (Multicast table array).
4183 */
4184 if (hw->phy.type == e1000_phy_i217) {
4185 u16 phy_reg;
4186
4187 ret_val = hw->phy.ops.acquire(hw);
4188 if (ret_val) {
4189 e_dbg("Failed to setup iRST\n");
4190 return;
4191 }
4192
4193 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4194 /*
4195 * Restore clear on SMB if no manageability engine
4196 * is present
4197 */
4198 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4199 if (ret_val)
4200 goto release;
4201 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4202 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4203
4204 /* Disable Proxy */
4205 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
4206 }
4207 /* Enable reset on MTA */
4208 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4209 if (ret_val)
4210 goto release;
4211 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4212 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4213 release:
4214 if (ret_val)
4215 e_dbg("Error %d in resume workarounds\n", ret_val);
4216 hw->phy.ops.release(hw);
4217 }
4218 }
4219
4220 /**
4221 * e1000_cleanup_led_ich8lan - Restore the default LED operation
4222 * @hw: pointer to the HW structure
4223 *
4224 * Return the LED back to the default configuration.
4225 **/
4226 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4227 {
4228 if (hw->phy.type == e1000_phy_ife)
4229 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
4230
4231 ew32(LEDCTL, hw->mac.ledctl_default);
4232 return 0;
4233 }
4234
4235 /**
4236 * e1000_led_on_ich8lan - Turn LEDs on
4237 * @hw: pointer to the HW structure
4238 *
4239 * Turn on the LEDs.
4240 **/
4241 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4242 {
4243 if (hw->phy.type == e1000_phy_ife)
4244 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4245 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4246
4247 ew32(LEDCTL, hw->mac.ledctl_mode2);
4248 return 0;
4249 }
4250
4251 /**
4252 * e1000_led_off_ich8lan - Turn LEDs off
4253 * @hw: pointer to the HW structure
4254 *
4255 * Turn off the LEDs.
4256 **/
4257 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4258 {
4259 if (hw->phy.type == e1000_phy_ife)
4260 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4261 (IFE_PSCL_PROBE_MODE |
4262 IFE_PSCL_PROBE_LEDS_OFF));
4263
4264 ew32(LEDCTL, hw->mac.ledctl_mode1);
4265 return 0;
4266 }
4267
4268 /**
4269 * e1000_setup_led_pchlan - Configures SW controllable LED
4270 * @hw: pointer to the HW structure
4271 *
4272 * This prepares the SW controllable LED for use.
4273 **/
4274 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4275 {
4276 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
4277 }
4278
4279 /**
4280 * e1000_cleanup_led_pchlan - Restore the default LED operation
4281 * @hw: pointer to the HW structure
4282 *
4283 * Return the LED back to the default configuration.
4284 **/
4285 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4286 {
4287 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
4288 }
4289
4290 /**
4291 * e1000_led_on_pchlan - Turn LEDs on
4292 * @hw: pointer to the HW structure
4293 *
4294 * Turn on the LEDs.
4295 **/
4296 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4297 {
4298 u16 data = (u16)hw->mac.ledctl_mode2;
4299 u32 i, led;
4300
4301 /*
4302 * If no link, then turn LED on by setting the invert bit
4303 * for each LED that's mode is "link_up" in ledctl_mode2.
4304 */
4305 if (!(er32(STATUS) & E1000_STATUS_LU)) {
4306 for (i = 0; i < 3; i++) {
4307 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4308 if ((led & E1000_PHY_LED0_MODE_MASK) !=
4309 E1000_LEDCTL_MODE_LINK_UP)
4310 continue;
4311 if (led & E1000_PHY_LED0_IVRT)
4312 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4313 else
4314 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4315 }
4316 }
4317
4318 return e1e_wphy(hw, HV_LED_CONFIG, data);
4319 }
4320
4321 /**
4322 * e1000_led_off_pchlan - Turn LEDs off
4323 * @hw: pointer to the HW structure
4324 *
4325 * Turn off the LEDs.
4326 **/
4327 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4328 {
4329 u16 data = (u16)hw->mac.ledctl_mode1;
4330 u32 i, led;
4331
4332 /*
4333 * If no link, then turn LED off by clearing the invert bit
4334 * for each LED that's mode is "link_up" in ledctl_mode1.
4335 */
4336 if (!(er32(STATUS) & E1000_STATUS_LU)) {
4337 for (i = 0; i < 3; i++) {
4338 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4339 if ((led & E1000_PHY_LED0_MODE_MASK) !=
4340 E1000_LEDCTL_MODE_LINK_UP)
4341 continue;
4342 if (led & E1000_PHY_LED0_IVRT)
4343 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4344 else
4345 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4346 }
4347 }
4348
4349 return e1e_wphy(hw, HV_LED_CONFIG, data);
4350 }
4351
4352 /**
4353 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
4354 * @hw: pointer to the HW structure
4355 *
4356 * Read appropriate register for the config done bit for completion status
4357 * and configure the PHY through s/w for EEPROM-less parts.
4358 *
4359 * NOTE: some silicon which is EEPROM-less will fail trying to read the
4360 * config done bit, so only an error is logged and continues. If we were
4361 * to return with error, EEPROM-less silicon would not be able to be reset
4362 * or change link.
4363 **/
4364 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4365 {
4366 s32 ret_val = 0;
4367 u32 bank = 0;
4368 u32 status;
4369
4370 e1000e_get_cfg_done(hw);
4371
4372 /* Wait for indication from h/w that it has completed basic config */
4373 if (hw->mac.type >= e1000_ich10lan) {
4374 e1000_lan_init_done_ich8lan(hw);
4375 } else {
4376 ret_val = e1000e_get_auto_rd_done(hw);
4377 if (ret_val) {
4378 /*
4379 * When auto config read does not complete, do not
4380 * return with an error. This can happen in situations
4381 * where there is no eeprom and prevents getting link.
4382 */
4383 e_dbg("Auto Read Done did not complete\n");
4384 ret_val = 0;
4385 }
4386 }
4387
4388 /* Clear PHY Reset Asserted bit */
4389 status = er32(STATUS);
4390 if (status & E1000_STATUS_PHYRA)
4391 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
4392 else
4393 e_dbg("PHY Reset Asserted not set - needs delay\n");
4394
4395 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
4396 if (hw->mac.type <= e1000_ich9lan) {
4397 if (!(er32(EECD) & E1000_EECD_PRES) &&
4398 (hw->phy.type == e1000_phy_igp_3)) {
4399 e1000e_phy_init_script_igp3(hw);
4400 }
4401 } else {
4402 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4403 /* Maybe we should do a basic PHY config */
4404 e_dbg("EEPROM not present\n");
4405 ret_val = -E1000_ERR_CONFIG;
4406 }
4407 }
4408
4409 return ret_val;
4410 }
4411
4412 /**
4413 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4414 * @hw: pointer to the HW structure
4415 *
4416 * In the case of a PHY power down to save power, or to turn off link during a
4417 * driver unload, or wake on lan is not enabled, remove the link.
4418 **/
4419 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4420 {
4421 /* If the management interface is not enabled, then power down */
4422 if (!(hw->mac.ops.check_mng_mode(hw) ||
4423 hw->phy.ops.check_reset_block(hw)))
4424 e1000_power_down_phy_copper(hw);
4425 }
4426
4427 /**
4428 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4429 * @hw: pointer to the HW structure
4430 *
4431 * Clears hardware counters specific to the silicon family and calls
4432 * clear_hw_cntrs_generic to clear all general purpose counters.
4433 **/
4434 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4435 {
4436 u16 phy_data;
4437 s32 ret_val;
4438
4439 e1000e_clear_hw_cntrs_base(hw);
4440
4441 er32(ALGNERRC);
4442 er32(RXERRC);
4443 er32(TNCRS);
4444 er32(CEXTERR);
4445 er32(TSCTC);
4446 er32(TSCTFC);
4447
4448 er32(MGTPRC);
4449 er32(MGTPDC);
4450 er32(MGTPTC);
4451
4452 er32(IAC);
4453 er32(ICRXOC);
4454
4455 /* Clear PHY statistics registers */
4456 if ((hw->phy.type == e1000_phy_82578) ||
4457 (hw->phy.type == e1000_phy_82579) ||
4458 (hw->phy.type == e1000_phy_i217) ||
4459 (hw->phy.type == e1000_phy_82577)) {
4460 ret_val = hw->phy.ops.acquire(hw);
4461 if (ret_val)
4462 return;
4463 ret_val = hw->phy.ops.set_page(hw,
4464 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4465 if (ret_val)
4466 goto release;
4467 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4468 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4469 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4470 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4471 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4472 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4473 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4474 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4475 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4476 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4477 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4478 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4479 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4480 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4481 release:
4482 hw->phy.ops.release(hw);
4483 }
4484 }
4485
4486 static const struct e1000_mac_operations ich8_mac_ops = {
4487 /* check_mng_mode dependent on mac type */
4488 .check_for_link = e1000_check_for_copper_link_ich8lan,
4489 /* cleanup_led dependent on mac type */
4490 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
4491 .get_bus_info = e1000_get_bus_info_ich8lan,
4492 .set_lan_id = e1000_set_lan_id_single_port,
4493 .get_link_up_info = e1000_get_link_up_info_ich8lan,
4494 /* led_on dependent on mac type */
4495 /* led_off dependent on mac type */
4496 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
4497 .reset_hw = e1000_reset_hw_ich8lan,
4498 .init_hw = e1000_init_hw_ich8lan,
4499 .setup_link = e1000_setup_link_ich8lan,
4500 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
4501 /* id_led_init dependent on mac type */
4502 .config_collision_dist = e1000e_config_collision_dist_generic,
4503 .rar_set = e1000e_rar_set_generic,
4504 };
4505
4506 static const struct e1000_phy_operations ich8_phy_ops = {
4507 .acquire = e1000_acquire_swflag_ich8lan,
4508 .check_reset_block = e1000_check_reset_block_ich8lan,
4509 .commit = NULL,
4510 .get_cfg_done = e1000_get_cfg_done_ich8lan,
4511 .get_cable_length = e1000e_get_cable_length_igp_2,
4512 .read_reg = e1000e_read_phy_reg_igp,
4513 .release = e1000_release_swflag_ich8lan,
4514 .reset = e1000_phy_hw_reset_ich8lan,
4515 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
4516 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
4517 .write_reg = e1000e_write_phy_reg_igp,
4518 };
4519
4520 static const struct e1000_nvm_operations ich8_nvm_ops = {
4521 .acquire = e1000_acquire_nvm_ich8lan,
4522 .read = e1000_read_nvm_ich8lan,
4523 .release = e1000_release_nvm_ich8lan,
4524 .reload = e1000e_reload_nvm_generic,
4525 .update = e1000_update_nvm_checksum_ich8lan,
4526 .valid_led_default = e1000_valid_led_default_ich8lan,
4527 .validate = e1000_validate_nvm_checksum_ich8lan,
4528 .write = e1000_write_nvm_ich8lan,
4529 };
4530
4531 const struct e1000_info e1000_ich8_info = {
4532 .mac = e1000_ich8lan,
4533 .flags = FLAG_HAS_WOL
4534 | FLAG_IS_ICH
4535 | FLAG_HAS_CTRLEXT_ON_LOAD
4536 | FLAG_HAS_AMT
4537 | FLAG_HAS_FLASH
4538 | FLAG_APME_IN_WUC,
4539 .pba = 8,
4540 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
4541 .get_variants = e1000_get_variants_ich8lan,
4542 .mac_ops = &ich8_mac_ops,
4543 .phy_ops = &ich8_phy_ops,
4544 .nvm_ops = &ich8_nvm_ops,
4545 };
4546
4547 const struct e1000_info e1000_ich9_info = {
4548 .mac = e1000_ich9lan,
4549 .flags = FLAG_HAS_JUMBO_FRAMES
4550 | FLAG_IS_ICH
4551 | FLAG_HAS_WOL
4552 | FLAG_HAS_CTRLEXT_ON_LOAD
4553 | FLAG_HAS_AMT
4554 | FLAG_HAS_FLASH
4555 | FLAG_APME_IN_WUC,
4556 .pba = 18,
4557 .max_hw_frame_size = DEFAULT_JUMBO,
4558 .get_variants = e1000_get_variants_ich8lan,
4559 .mac_ops = &ich8_mac_ops,
4560 .phy_ops = &ich8_phy_ops,
4561 .nvm_ops = &ich8_nvm_ops,
4562 };
4563
4564 const struct e1000_info e1000_ich10_info = {
4565 .mac = e1000_ich10lan,
4566 .flags = FLAG_HAS_JUMBO_FRAMES
4567 | FLAG_IS_ICH
4568 | FLAG_HAS_WOL
4569 | FLAG_HAS_CTRLEXT_ON_LOAD
4570 | FLAG_HAS_AMT
4571 | FLAG_HAS_FLASH
4572 | FLAG_APME_IN_WUC,
4573 .pba = 18,
4574 .max_hw_frame_size = DEFAULT_JUMBO,
4575 .get_variants = e1000_get_variants_ich8lan,
4576 .mac_ops = &ich8_mac_ops,
4577 .phy_ops = &ich8_phy_ops,
4578 .nvm_ops = &ich8_nvm_ops,
4579 };
4580
4581 const struct e1000_info e1000_pch_info = {
4582 .mac = e1000_pchlan,
4583 .flags = FLAG_IS_ICH
4584 | FLAG_HAS_WOL
4585 | FLAG_HAS_CTRLEXT_ON_LOAD
4586 | FLAG_HAS_AMT
4587 | FLAG_HAS_FLASH
4588 | FLAG_HAS_JUMBO_FRAMES
4589 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4590 | FLAG_APME_IN_WUC,
4591 .flags2 = FLAG2_HAS_PHY_STATS,
4592 .pba = 26,
4593 .max_hw_frame_size = 4096,
4594 .get_variants = e1000_get_variants_ich8lan,
4595 .mac_ops = &ich8_mac_ops,
4596 .phy_ops = &ich8_phy_ops,
4597 .nvm_ops = &ich8_nvm_ops,
4598 };
4599
4600 const struct e1000_info e1000_pch2_info = {
4601 .mac = e1000_pch2lan,
4602 .flags = FLAG_IS_ICH
4603 | FLAG_HAS_WOL
4604 | FLAG_HAS_CTRLEXT_ON_LOAD
4605 | FLAG_HAS_AMT
4606 | FLAG_HAS_FLASH
4607 | FLAG_HAS_JUMBO_FRAMES
4608 | FLAG_APME_IN_WUC,
4609 .flags2 = FLAG2_HAS_PHY_STATS
4610 | FLAG2_HAS_EEE,
4611 .pba = 26,
4612 .max_hw_frame_size = DEFAULT_JUMBO,
4613 .get_variants = e1000_get_variants_ich8lan,
4614 .mac_ops = &ich8_mac_ops,
4615 .phy_ops = &ich8_phy_ops,
4616 .nvm_ops = &ich8_nvm_ops,
4617 };
4618
4619 const struct e1000_info e1000_pch_lpt_info = {
4620 .mac = e1000_pch_lpt,
4621 .flags = FLAG_IS_ICH
4622 | FLAG_HAS_WOL
4623 | FLAG_HAS_CTRLEXT_ON_LOAD
4624 | FLAG_HAS_AMT
4625 | FLAG_HAS_FLASH
4626 | FLAG_HAS_JUMBO_FRAMES
4627 | FLAG_APME_IN_WUC,
4628 .flags2 = FLAG2_HAS_PHY_STATS
4629 | FLAG2_HAS_EEE,
4630 .pba = 26,
4631 .max_hw_frame_size = DEFAULT_JUMBO,
4632 .get_variants = e1000_get_variants_ich8lan,
4633 .mac_ops = &ich8_mac_ops,
4634 .phy_ops = &ich8_phy_ops,
4635 .nvm_ops = &ich8_nvm_ops,
4636 };
Linux kernel - Deliverables
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