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Merge tag 'fixes-non-critical-3.15' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / ich8lan.c
1 /* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
21
22 /* 82562G 10/100 Network Connection
23 * 82562G-2 10/100 Network Connection
24 * 82562GT 10/100 Network Connection
25 * 82562GT-2 10/100 Network Connection
26 * 82562V 10/100 Network Connection
27 * 82562V-2 10/100 Network Connection
28 * 82566DC-2 Gigabit Network Connection
29 * 82566DC Gigabit Network Connection
30 * 82566DM-2 Gigabit Network Connection
31 * 82566DM Gigabit Network Connection
32 * 82566MC Gigabit Network Connection
33 * 82566MM Gigabit Network Connection
34 * 82567LM Gigabit Network Connection
35 * 82567LF Gigabit Network Connection
36 * 82567V Gigabit Network Connection
37 * 82567LM-2 Gigabit Network Connection
38 * 82567LF-2 Gigabit Network Connection
39 * 82567V-2 Gigabit Network Connection
40 * 82567LF-3 Gigabit Network Connection
41 * 82567LM-3 Gigabit Network Connection
42 * 82567LM-4 Gigabit Network Connection
43 * 82577LM Gigabit Network Connection
44 * 82577LC Gigabit Network Connection
45 * 82578DM Gigabit Network Connection
46 * 82578DC Gigabit Network Connection
47 * 82579LM Gigabit Network Connection
48 * 82579V Gigabit Network Connection
49 * Ethernet Connection I217-LM
50 * Ethernet Connection I217-V
51 * Ethernet Connection I218-V
52 * Ethernet Connection I218-LM
53 * Ethernet Connection (2) I218-LM
54 * Ethernet Connection (2) I218-V
55 * Ethernet Connection (3) I218-LM
56 * Ethernet Connection (3) I218-V
57 */
58
59 #include "e1000.h"
60
61 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
62 /* Offset 04h HSFSTS */
63 union ich8_hws_flash_status {
64 struct ich8_hsfsts {
65 u16 flcdone:1; /* bit 0 Flash Cycle Done */
66 u16 flcerr:1; /* bit 1 Flash Cycle Error */
67 u16 dael:1; /* bit 2 Direct Access error Log */
68 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
69 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
70 u16 reserved1:2; /* bit 13:6 Reserved */
71 u16 reserved2:6; /* bit 13:6 Reserved */
72 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
73 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
74 } hsf_status;
75 u16 regval;
76 };
77
78 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
79 /* Offset 06h FLCTL */
80 union ich8_hws_flash_ctrl {
81 struct ich8_hsflctl {
82 u16 flcgo:1; /* 0 Flash Cycle Go */
83 u16 flcycle:2; /* 2:1 Flash Cycle */
84 u16 reserved:5; /* 7:3 Reserved */
85 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
86 u16 flockdn:6; /* 15:10 Reserved */
87 } hsf_ctrl;
88 u16 regval;
89 };
90
91 /* ICH Flash Region Access Permissions */
92 union ich8_hws_flash_regacc {
93 struct ich8_flracc {
94 u32 grra:8; /* 0:7 GbE region Read Access */
95 u32 grwa:8; /* 8:15 GbE region Write Access */
96 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
97 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
98 } hsf_flregacc;
99 u16 regval;
100 };
101
102 /* ICH Flash Protected Region */
103 union ich8_flash_protected_range {
104 struct ich8_pr {
105 u32 base:13; /* 0:12 Protected Range Base */
106 u32 reserved1:2; /* 13:14 Reserved */
107 u32 rpe:1; /* 15 Read Protection Enable */
108 u32 limit:13; /* 16:28 Protected Range Limit */
109 u32 reserved2:2; /* 29:30 Reserved */
110 u32 wpe:1; /* 31 Write Protection Enable */
111 } range;
112 u32 regval;
113 };
114
115 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
116 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
117 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
118 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
119 u32 offset, u8 byte);
120 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
121 u8 *data);
122 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
123 u16 *data);
124 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
125 u8 size, u16 *data);
126 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
127 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
128 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
129 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
130 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
131 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
132 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
133 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
134 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
135 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
136 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
137 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
138 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
139 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
140 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
141 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
142 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
143 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
144 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
145 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
146 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
147 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
148 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
149
150 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
151 {
152 return readw(hw->flash_address + reg);
153 }
154
155 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
156 {
157 return readl(hw->flash_address + reg);
158 }
159
160 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
161 {
162 writew(val, hw->flash_address + reg);
163 }
164
165 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
166 {
167 writel(val, hw->flash_address + reg);
168 }
169
170 #define er16flash(reg) __er16flash(hw, (reg))
171 #define er32flash(reg) __er32flash(hw, (reg))
172 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
173 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
174
175 /**
176 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
177 * @hw: pointer to the HW structure
178 *
179 * Test access to the PHY registers by reading the PHY ID registers. If
180 * the PHY ID is already known (e.g. resume path) compare it with known ID,
181 * otherwise assume the read PHY ID is correct if it is valid.
182 *
183 * Assumes the sw/fw/hw semaphore is already acquired.
184 **/
185 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
186 {
187 u16 phy_reg = 0;
188 u32 phy_id = 0;
189 s32 ret_val;
190 u16 retry_count;
191 u32 mac_reg = 0;
192
193 for (retry_count = 0; retry_count < 2; retry_count++) {
194 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
195 if (ret_val || (phy_reg == 0xFFFF))
196 continue;
197 phy_id = (u32)(phy_reg << 16);
198
199 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
200 if (ret_val || (phy_reg == 0xFFFF)) {
201 phy_id = 0;
202 continue;
203 }
204 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
205 break;
206 }
207
208 if (hw->phy.id) {
209 if (hw->phy.id == phy_id)
210 goto out;
211 } else if (phy_id) {
212 hw->phy.id = phy_id;
213 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
214 goto out;
215 }
216
217 /* In case the PHY needs to be in mdio slow mode,
218 * set slow mode and try to get the PHY id again.
219 */
220 hw->phy.ops.release(hw);
221 ret_val = e1000_set_mdio_slow_mode_hv(hw);
222 if (!ret_val)
223 ret_val = e1000e_get_phy_id(hw);
224 hw->phy.ops.acquire(hw);
225
226 if (ret_val)
227 return false;
228 out:
229 if (hw->mac.type == e1000_pch_lpt) {
230 /* Unforce SMBus mode in PHY */
231 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
232 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
233 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
234
235 /* Unforce SMBus mode in MAC */
236 mac_reg = er32(CTRL_EXT);
237 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
238 ew32(CTRL_EXT, mac_reg);
239 }
240
241 return true;
242 }
243
244 /**
245 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
246 * @hw: pointer to the HW structure
247 *
248 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
249 * used to reset the PHY to a quiescent state when necessary.
250 **/
251 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
252 {
253 u32 mac_reg;
254
255 /* Set Phy Config Counter to 50msec */
256 mac_reg = er32(FEXTNVM3);
257 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
258 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
259 ew32(FEXTNVM3, mac_reg);
260
261 /* Toggle LANPHYPC Value bit */
262 mac_reg = er32(CTRL);
263 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
264 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
265 ew32(CTRL, mac_reg);
266 e1e_flush();
267 usleep_range(10, 20);
268 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
269 ew32(CTRL, mac_reg);
270 e1e_flush();
271
272 if (hw->mac.type < e1000_pch_lpt) {
273 msleep(50);
274 } else {
275 u16 count = 20;
276
277 do {
278 usleep_range(5000, 10000);
279 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
280
281 msleep(30);
282 }
283 }
284
285 /**
286 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
287 * @hw: pointer to the HW structure
288 *
289 * Workarounds/flow necessary for PHY initialization during driver load
290 * and resume paths.
291 **/
292 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
293 {
294 struct e1000_adapter *adapter = hw->adapter;
295 u32 mac_reg, fwsm = er32(FWSM);
296 s32 ret_val;
297
298 /* Gate automatic PHY configuration by hardware on managed and
299 * non-managed 82579 and newer adapters.
300 */
301 e1000_gate_hw_phy_config_ich8lan(hw, true);
302
303 /* It is not possible to be certain of the current state of ULP
304 * so forcibly disable it.
305 */
306 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
307 e1000_disable_ulp_lpt_lp(hw, true);
308
309 ret_val = hw->phy.ops.acquire(hw);
310 if (ret_val) {
311 e_dbg("Failed to initialize PHY flow\n");
312 goto out;
313 }
314
315 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
316 * inaccessible and resetting the PHY is not blocked, toggle the
317 * LANPHYPC Value bit to force the interconnect to PCIe mode.
318 */
319 switch (hw->mac.type) {
320 case e1000_pch_lpt:
321 if (e1000_phy_is_accessible_pchlan(hw))
322 break;
323
324 /* Before toggling LANPHYPC, see if PHY is accessible by
325 * forcing MAC to SMBus mode first.
326 */
327 mac_reg = er32(CTRL_EXT);
328 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
329 ew32(CTRL_EXT, mac_reg);
330
331 /* Wait 50 milliseconds for MAC to finish any retries
332 * that it might be trying to perform from previous
333 * attempts to acknowledge any phy read requests.
334 */
335 msleep(50);
336
337 /* fall-through */
338 case e1000_pch2lan:
339 if (e1000_phy_is_accessible_pchlan(hw))
340 break;
341
342 /* fall-through */
343 case e1000_pchlan:
344 if ((hw->mac.type == e1000_pchlan) &&
345 (fwsm & E1000_ICH_FWSM_FW_VALID))
346 break;
347
348 if (hw->phy.ops.check_reset_block(hw)) {
349 e_dbg("Required LANPHYPC toggle blocked by ME\n");
350 ret_val = -E1000_ERR_PHY;
351 break;
352 }
353
354 /* Toggle LANPHYPC Value bit */
355 e1000_toggle_lanphypc_pch_lpt(hw);
356 if (hw->mac.type >= e1000_pch_lpt) {
357 if (e1000_phy_is_accessible_pchlan(hw))
358 break;
359
360 /* Toggling LANPHYPC brings the PHY out of SMBus mode
361 * so ensure that the MAC is also out of SMBus mode
362 */
363 mac_reg = er32(CTRL_EXT);
364 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
365 ew32(CTRL_EXT, mac_reg);
366
367 if (e1000_phy_is_accessible_pchlan(hw))
368 break;
369
370 ret_val = -E1000_ERR_PHY;
371 }
372 break;
373 default:
374 break;
375 }
376
377 hw->phy.ops.release(hw);
378 if (!ret_val) {
379
380 /* Check to see if able to reset PHY. Print error if not */
381 if (hw->phy.ops.check_reset_block(hw)) {
382 e_err("Reset blocked by ME\n");
383 goto out;
384 }
385
386 /* Reset the PHY before any access to it. Doing so, ensures
387 * that the PHY is in a known good state before we read/write
388 * PHY registers. The generic reset is sufficient here,
389 * because we haven't determined the PHY type yet.
390 */
391 ret_val = e1000e_phy_hw_reset_generic(hw);
392 if (ret_val)
393 goto out;
394
395 /* On a successful reset, possibly need to wait for the PHY
396 * to quiesce to an accessible state before returning control
397 * to the calling function. If the PHY does not quiesce, then
398 * return E1000E_BLK_PHY_RESET, as this is the condition that
399 * the PHY is in.
400 */
401 ret_val = hw->phy.ops.check_reset_block(hw);
402 if (ret_val)
403 e_err("ME blocked access to PHY after reset\n");
404 }
405
406 out:
407 /* Ungate automatic PHY configuration on non-managed 82579 */
408 if ((hw->mac.type == e1000_pch2lan) &&
409 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
410 usleep_range(10000, 20000);
411 e1000_gate_hw_phy_config_ich8lan(hw, false);
412 }
413
414 return ret_val;
415 }
416
417 /**
418 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
419 * @hw: pointer to the HW structure
420 *
421 * Initialize family-specific PHY parameters and function pointers.
422 **/
423 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
424 {
425 struct e1000_phy_info *phy = &hw->phy;
426 s32 ret_val;
427
428 phy->addr = 1;
429 phy->reset_delay_us = 100;
430
431 phy->ops.set_page = e1000_set_page_igp;
432 phy->ops.read_reg = e1000_read_phy_reg_hv;
433 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
434 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
435 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
436 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
437 phy->ops.write_reg = e1000_write_phy_reg_hv;
438 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
439 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
440 phy->ops.power_up = e1000_power_up_phy_copper;
441 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
442 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
443
444 phy->id = e1000_phy_unknown;
445
446 ret_val = e1000_init_phy_workarounds_pchlan(hw);
447 if (ret_val)
448 return ret_val;
449
450 if (phy->id == e1000_phy_unknown)
451 switch (hw->mac.type) {
452 default:
453 ret_val = e1000e_get_phy_id(hw);
454 if (ret_val)
455 return ret_val;
456 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
457 break;
458 /* fall-through */
459 case e1000_pch2lan:
460 case e1000_pch_lpt:
461 /* In case the PHY needs to be in mdio slow mode,
462 * set slow mode and try to get the PHY id again.
463 */
464 ret_val = e1000_set_mdio_slow_mode_hv(hw);
465 if (ret_val)
466 return ret_val;
467 ret_val = e1000e_get_phy_id(hw);
468 if (ret_val)
469 return ret_val;
470 break;
471 }
472 phy->type = e1000e_get_phy_type_from_id(phy->id);
473
474 switch (phy->type) {
475 case e1000_phy_82577:
476 case e1000_phy_82579:
477 case e1000_phy_i217:
478 phy->ops.check_polarity = e1000_check_polarity_82577;
479 phy->ops.force_speed_duplex =
480 e1000_phy_force_speed_duplex_82577;
481 phy->ops.get_cable_length = e1000_get_cable_length_82577;
482 phy->ops.get_info = e1000_get_phy_info_82577;
483 phy->ops.commit = e1000e_phy_sw_reset;
484 break;
485 case e1000_phy_82578:
486 phy->ops.check_polarity = e1000_check_polarity_m88;
487 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
488 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
489 phy->ops.get_info = e1000e_get_phy_info_m88;
490 break;
491 default:
492 ret_val = -E1000_ERR_PHY;
493 break;
494 }
495
496 return ret_val;
497 }
498
499 /**
500 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
501 * @hw: pointer to the HW structure
502 *
503 * Initialize family-specific PHY parameters and function pointers.
504 **/
505 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
506 {
507 struct e1000_phy_info *phy = &hw->phy;
508 s32 ret_val;
509 u16 i = 0;
510
511 phy->addr = 1;
512 phy->reset_delay_us = 100;
513
514 phy->ops.power_up = e1000_power_up_phy_copper;
515 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
516
517 /* We may need to do this twice - once for IGP and if that fails,
518 * we'll set BM func pointers and try again
519 */
520 ret_val = e1000e_determine_phy_address(hw);
521 if (ret_val) {
522 phy->ops.write_reg = e1000e_write_phy_reg_bm;
523 phy->ops.read_reg = e1000e_read_phy_reg_bm;
524 ret_val = e1000e_determine_phy_address(hw);
525 if (ret_val) {
526 e_dbg("Cannot determine PHY addr. Erroring out\n");
527 return ret_val;
528 }
529 }
530
531 phy->id = 0;
532 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
533 (i++ < 100)) {
534 usleep_range(1000, 2000);
535 ret_val = e1000e_get_phy_id(hw);
536 if (ret_val)
537 return ret_val;
538 }
539
540 /* Verify phy id */
541 switch (phy->id) {
542 case IGP03E1000_E_PHY_ID:
543 phy->type = e1000_phy_igp_3;
544 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
545 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
546 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
547 phy->ops.get_info = e1000e_get_phy_info_igp;
548 phy->ops.check_polarity = e1000_check_polarity_igp;
549 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
550 break;
551 case IFE_E_PHY_ID:
552 case IFE_PLUS_E_PHY_ID:
553 case IFE_C_E_PHY_ID:
554 phy->type = e1000_phy_ife;
555 phy->autoneg_mask = E1000_ALL_NOT_GIG;
556 phy->ops.get_info = e1000_get_phy_info_ife;
557 phy->ops.check_polarity = e1000_check_polarity_ife;
558 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
559 break;
560 case BME1000_E_PHY_ID:
561 phy->type = e1000_phy_bm;
562 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
563 phy->ops.read_reg = e1000e_read_phy_reg_bm;
564 phy->ops.write_reg = e1000e_write_phy_reg_bm;
565 phy->ops.commit = e1000e_phy_sw_reset;
566 phy->ops.get_info = e1000e_get_phy_info_m88;
567 phy->ops.check_polarity = e1000_check_polarity_m88;
568 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
569 break;
570 default:
571 return -E1000_ERR_PHY;
572 break;
573 }
574
575 return 0;
576 }
577
578 /**
579 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
580 * @hw: pointer to the HW structure
581 *
582 * Initialize family-specific NVM parameters and function
583 * pointers.
584 **/
585 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
586 {
587 struct e1000_nvm_info *nvm = &hw->nvm;
588 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
589 u32 gfpreg, sector_base_addr, sector_end_addr;
590 u16 i;
591
592 /* Can't read flash registers if the register set isn't mapped. */
593 if (!hw->flash_address) {
594 e_dbg("ERROR: Flash registers not mapped\n");
595 return -E1000_ERR_CONFIG;
596 }
597
598 nvm->type = e1000_nvm_flash_sw;
599
600 gfpreg = er32flash(ICH_FLASH_GFPREG);
601
602 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
603 * Add 1 to sector_end_addr since this sector is included in
604 * the overall size.
605 */
606 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
607 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
608
609 /* flash_base_addr is byte-aligned */
610 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
611
612 /* find total size of the NVM, then cut in half since the total
613 * size represents two separate NVM banks.
614 */
615 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
616 << FLASH_SECTOR_ADDR_SHIFT);
617 nvm->flash_bank_size /= 2;
618 /* Adjust to word count */
619 nvm->flash_bank_size /= sizeof(u16);
620
621 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
622
623 /* Clear shadow ram */
624 for (i = 0; i < nvm->word_size; i++) {
625 dev_spec->shadow_ram[i].modified = false;
626 dev_spec->shadow_ram[i].value = 0xFFFF;
627 }
628
629 return 0;
630 }
631
632 /**
633 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
634 * @hw: pointer to the HW structure
635 *
636 * Initialize family-specific MAC parameters and function
637 * pointers.
638 **/
639 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
640 {
641 struct e1000_mac_info *mac = &hw->mac;
642
643 /* Set media type function pointer */
644 hw->phy.media_type = e1000_media_type_copper;
645
646 /* Set mta register count */
647 mac->mta_reg_count = 32;
648 /* Set rar entry count */
649 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
650 if (mac->type == e1000_ich8lan)
651 mac->rar_entry_count--;
652 /* FWSM register */
653 mac->has_fwsm = true;
654 /* ARC subsystem not supported */
655 mac->arc_subsystem_valid = false;
656 /* Adaptive IFS supported */
657 mac->adaptive_ifs = true;
658
659 /* LED and other operations */
660 switch (mac->type) {
661 case e1000_ich8lan:
662 case e1000_ich9lan:
663 case e1000_ich10lan:
664 /* check management mode */
665 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
666 /* ID LED init */
667 mac->ops.id_led_init = e1000e_id_led_init_generic;
668 /* blink LED */
669 mac->ops.blink_led = e1000e_blink_led_generic;
670 /* setup LED */
671 mac->ops.setup_led = e1000e_setup_led_generic;
672 /* cleanup LED */
673 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
674 /* turn on/off LED */
675 mac->ops.led_on = e1000_led_on_ich8lan;
676 mac->ops.led_off = e1000_led_off_ich8lan;
677 break;
678 case e1000_pch2lan:
679 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
680 mac->ops.rar_set = e1000_rar_set_pch2lan;
681 /* fall-through */
682 case e1000_pch_lpt:
683 case e1000_pchlan:
684 /* check management mode */
685 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
686 /* ID LED init */
687 mac->ops.id_led_init = e1000_id_led_init_pchlan;
688 /* setup LED */
689 mac->ops.setup_led = e1000_setup_led_pchlan;
690 /* cleanup LED */
691 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
692 /* turn on/off LED */
693 mac->ops.led_on = e1000_led_on_pchlan;
694 mac->ops.led_off = e1000_led_off_pchlan;
695 break;
696 default:
697 break;
698 }
699
700 if (mac->type == e1000_pch_lpt) {
701 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
702 mac->ops.rar_set = e1000_rar_set_pch_lpt;
703 mac->ops.setup_physical_interface =
704 e1000_setup_copper_link_pch_lpt;
705 }
706
707 /* Enable PCS Lock-loss workaround for ICH8 */
708 if (mac->type == e1000_ich8lan)
709 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
710
711 return 0;
712 }
713
714 /**
715 * __e1000_access_emi_reg_locked - Read/write EMI register
716 * @hw: pointer to the HW structure
717 * @addr: EMI address to program
718 * @data: pointer to value to read/write from/to the EMI address
719 * @read: boolean flag to indicate read or write
720 *
721 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
722 **/
723 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
724 u16 *data, bool read)
725 {
726 s32 ret_val;
727
728 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
729 if (ret_val)
730 return ret_val;
731
732 if (read)
733 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
734 else
735 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
736
737 return ret_val;
738 }
739
740 /**
741 * e1000_read_emi_reg_locked - Read Extended Management Interface register
742 * @hw: pointer to the HW structure
743 * @addr: EMI address to program
744 * @data: value to be read from the EMI address
745 *
746 * Assumes the SW/FW/HW Semaphore is already acquired.
747 **/
748 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
749 {
750 return __e1000_access_emi_reg_locked(hw, addr, data, true);
751 }
752
753 /**
754 * e1000_write_emi_reg_locked - Write Extended Management Interface register
755 * @hw: pointer to the HW structure
756 * @addr: EMI address to program
757 * @data: value to be written to the EMI address
758 *
759 * Assumes the SW/FW/HW Semaphore is already acquired.
760 **/
761 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
762 {
763 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
764 }
765
766 /**
767 * e1000_set_eee_pchlan - Enable/disable EEE support
768 * @hw: pointer to the HW structure
769 *
770 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
771 * the link and the EEE capabilities of the link partner. The LPI Control
772 * register bits will remain set only if/when link is up.
773 *
774 * EEE LPI must not be asserted earlier than one second after link is up.
775 * On 82579, EEE LPI should not be enabled until such time otherwise there
776 * can be link issues with some switches. Other devices can have EEE LPI
777 * enabled immediately upon link up since they have a timer in hardware which
778 * prevents LPI from being asserted too early.
779 **/
780 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
781 {
782 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
783 s32 ret_val;
784 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
785
786 switch (hw->phy.type) {
787 case e1000_phy_82579:
788 lpa = I82579_EEE_LP_ABILITY;
789 pcs_status = I82579_EEE_PCS_STATUS;
790 adv_addr = I82579_EEE_ADVERTISEMENT;
791 break;
792 case e1000_phy_i217:
793 lpa = I217_EEE_LP_ABILITY;
794 pcs_status = I217_EEE_PCS_STATUS;
795 adv_addr = I217_EEE_ADVERTISEMENT;
796 break;
797 default:
798 return 0;
799 }
800
801 ret_val = hw->phy.ops.acquire(hw);
802 if (ret_val)
803 return ret_val;
804
805 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
806 if (ret_val)
807 goto release;
808
809 /* Clear bits that enable EEE in various speeds */
810 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
811
812 /* Enable EEE if not disabled by user */
813 if (!dev_spec->eee_disable) {
814 /* Save off link partner's EEE ability */
815 ret_val = e1000_read_emi_reg_locked(hw, lpa,
816 &dev_spec->eee_lp_ability);
817 if (ret_val)
818 goto release;
819
820 /* Read EEE advertisement */
821 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
822 if (ret_val)
823 goto release;
824
825 /* Enable EEE only for speeds in which the link partner is
826 * EEE capable and for which we advertise EEE.
827 */
828 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
829 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
830
831 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
832 e1e_rphy_locked(hw, MII_LPA, &data);
833 if (data & LPA_100FULL)
834 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
835 else
836 /* EEE is not supported in 100Half, so ignore
837 * partner's EEE in 100 ability if full-duplex
838 * is not advertised.
839 */
840 dev_spec->eee_lp_ability &=
841 ~I82579_EEE_100_SUPPORTED;
842 }
843 }
844
845 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
846 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
847 if (ret_val)
848 goto release;
849
850 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
851 release:
852 hw->phy.ops.release(hw);
853
854 return ret_val;
855 }
856
857 /**
858 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
859 * @hw: pointer to the HW structure
860 * @link: link up bool flag
861 *
862 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
863 * preventing further DMA write requests. Workaround the issue by disabling
864 * the de-assertion of the clock request when in 1Gpbs mode.
865 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
866 * speeds in order to avoid Tx hangs.
867 **/
868 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
869 {
870 u32 fextnvm6 = er32(FEXTNVM6);
871 u32 status = er32(STATUS);
872 s32 ret_val = 0;
873 u16 reg;
874
875 if (link && (status & E1000_STATUS_SPEED_1000)) {
876 ret_val = hw->phy.ops.acquire(hw);
877 if (ret_val)
878 return ret_val;
879
880 ret_val =
881 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
882 &reg);
883 if (ret_val)
884 goto release;
885
886 ret_val =
887 e1000e_write_kmrn_reg_locked(hw,
888 E1000_KMRNCTRLSTA_K1_CONFIG,
889 reg &
890 ~E1000_KMRNCTRLSTA_K1_ENABLE);
891 if (ret_val)
892 goto release;
893
894 usleep_range(10, 20);
895
896 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
897
898 ret_val =
899 e1000e_write_kmrn_reg_locked(hw,
900 E1000_KMRNCTRLSTA_K1_CONFIG,
901 reg);
902 release:
903 hw->phy.ops.release(hw);
904 } else {
905 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
906 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
907
908 if (!link || ((status & E1000_STATUS_SPEED_100) &&
909 (status & E1000_STATUS_FD)))
910 goto update_fextnvm6;
911
912 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
913 if (ret_val)
914 return ret_val;
915
916 /* Clear link status transmit timeout */
917 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
918
919 if (status & E1000_STATUS_SPEED_100) {
920 /* Set inband Tx timeout to 5x10us for 100Half */
921 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
922
923 /* Do not extend the K1 entry latency for 100Half */
924 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
925 } else {
926 /* Set inband Tx timeout to 50x10us for 10Full/Half */
927 reg |= 50 <<
928 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
929
930 /* Extend the K1 entry latency for 10 Mbps */
931 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
932 }
933
934 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
935 if (ret_val)
936 return ret_val;
937
938 update_fextnvm6:
939 ew32(FEXTNVM6, fextnvm6);
940 }
941
942 return ret_val;
943 }
944
945 /**
946 * e1000_platform_pm_pch_lpt - Set platform power management values
947 * @hw: pointer to the HW structure
948 * @link: bool indicating link status
949 *
950 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
951 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
952 * when link is up (which must not exceed the maximum latency supported
953 * by the platform), otherwise specify there is no LTR requirement.
954 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
955 * latencies in the LTR Extended Capability Structure in the PCIe Extended
956 * Capability register set, on this device LTR is set by writing the
957 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
958 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
959 * message to the PMC.
960 **/
961 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
962 {
963 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
964 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
965 u16 lat_enc = 0; /* latency encoded */
966
967 if (link) {
968 u16 speed, duplex, scale = 0;
969 u16 max_snoop, max_nosnoop;
970 u16 max_ltr_enc; /* max LTR latency encoded */
971 s64 lat_ns; /* latency (ns) */
972 s64 value;
973 u32 rxa;
974
975 if (!hw->adapter->max_frame_size) {
976 e_dbg("max_frame_size not set.\n");
977 return -E1000_ERR_CONFIG;
978 }
979
980 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
981 if (!speed) {
982 e_dbg("Speed not set.\n");
983 return -E1000_ERR_CONFIG;
984 }
985
986 /* Rx Packet Buffer Allocation size (KB) */
987 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
988
989 /* Determine the maximum latency tolerated by the device.
990 *
991 * Per the PCIe spec, the tolerated latencies are encoded as
992 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
993 * a 10-bit value (0-1023) to provide a range from 1 ns to
994 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
995 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
996 */
997 lat_ns = ((s64)rxa * 1024 -
998 (2 * (s64)hw->adapter->max_frame_size)) * 8 * 1000;
999 if (lat_ns < 0)
1000 lat_ns = 0;
1001 else
1002 do_div(lat_ns, speed);
1003
1004 value = lat_ns;
1005 while (value > PCI_LTR_VALUE_MASK) {
1006 scale++;
1007 value = DIV_ROUND_UP(value, (1 << 5));
1008 }
1009 if (scale > E1000_LTRV_SCALE_MAX) {
1010 e_dbg("Invalid LTR latency scale %d\n", scale);
1011 return -E1000_ERR_CONFIG;
1012 }
1013 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1014
1015 /* Determine the maximum latency tolerated by the platform */
1016 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1017 &max_snoop);
1018 pci_read_config_word(hw->adapter->pdev,
1019 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1020 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1021
1022 if (lat_enc > max_ltr_enc)
1023 lat_enc = max_ltr_enc;
1024 }
1025
1026 /* Set Snoop and No-Snoop latencies the same */
1027 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1028 ew32(LTRV, reg);
1029
1030 return 0;
1031 }
1032
1033 /**
1034 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1035 * @hw: pointer to the HW structure
1036 * @to_sx: boolean indicating a system power state transition to Sx
1037 *
1038 * When link is down, configure ULP mode to significantly reduce the power
1039 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1040 * ME firmware to start the ULP configuration. If not on an ME enabled
1041 * system, configure the ULP mode by software.
1042 */
1043 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1044 {
1045 u32 mac_reg;
1046 s32 ret_val = 0;
1047 u16 phy_reg;
1048
1049 if ((hw->mac.type < e1000_pch_lpt) ||
1050 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1051 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1052 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1053 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1054 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1055 return 0;
1056
1057 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1058 /* Request ME configure ULP mode in the PHY */
1059 mac_reg = er32(H2ME);
1060 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1061 ew32(H2ME, mac_reg);
1062
1063 goto out;
1064 }
1065
1066 if (!to_sx) {
1067 int i = 0;
1068
1069 /* Poll up to 5 seconds for Cable Disconnected indication */
1070 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1071 /* Bail if link is re-acquired */
1072 if (er32(STATUS) & E1000_STATUS_LU)
1073 return -E1000_ERR_PHY;
1074
1075 if (i++ == 100)
1076 break;
1077
1078 msleep(50);
1079 }
1080 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1081 (er32(FEXT) &
1082 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1083 }
1084
1085 ret_val = hw->phy.ops.acquire(hw);
1086 if (ret_val)
1087 goto out;
1088
1089 /* Force SMBus mode in PHY */
1090 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1091 if (ret_val)
1092 goto release;
1093 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1094 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1095
1096 /* Force SMBus mode in MAC */
1097 mac_reg = er32(CTRL_EXT);
1098 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1099 ew32(CTRL_EXT, mac_reg);
1100
1101 /* Set Inband ULP Exit, Reset to SMBus mode and
1102 * Disable SMBus Release on PERST# in PHY
1103 */
1104 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1105 if (ret_val)
1106 goto release;
1107 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1108 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1109 if (to_sx) {
1110 if (er32(WUFC) & E1000_WUFC_LNKC)
1111 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1112
1113 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1114 } else {
1115 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1116 }
1117 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1118
1119 /* Set Disable SMBus Release on PERST# in MAC */
1120 mac_reg = er32(FEXTNVM7);
1121 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1122 ew32(FEXTNVM7, mac_reg);
1123
1124 /* Commit ULP changes in PHY by starting auto ULP configuration */
1125 phy_reg |= I218_ULP_CONFIG1_START;
1126 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1127 release:
1128 hw->phy.ops.release(hw);
1129 out:
1130 if (ret_val)
1131 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1132 else
1133 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1134
1135 return ret_val;
1136 }
1137
1138 /**
1139 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1140 * @hw: pointer to the HW structure
1141 * @force: boolean indicating whether or not to force disabling ULP
1142 *
1143 * Un-configure ULP mode when link is up, the system is transitioned from
1144 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1145 * system, poll for an indication from ME that ULP has been un-configured.
1146 * If not on an ME enabled system, un-configure the ULP mode by software.
1147 *
1148 * During nominal operation, this function is called when link is acquired
1149 * to disable ULP mode (force=false); otherwise, for example when unloading
1150 * the driver or during Sx->S0 transitions, this is called with force=true
1151 * to forcibly disable ULP.
1152 */
1153 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1154 {
1155 s32 ret_val = 0;
1156 u32 mac_reg;
1157 u16 phy_reg;
1158 int i = 0;
1159
1160 if ((hw->mac.type < e1000_pch_lpt) ||
1161 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1162 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1163 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1164 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1165 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1166 return 0;
1167
1168 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1169 if (force) {
1170 /* Request ME un-configure ULP mode in the PHY */
1171 mac_reg = er32(H2ME);
1172 mac_reg &= ~E1000_H2ME_ULP;
1173 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1174 ew32(H2ME, mac_reg);
1175 }
1176
1177 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1178 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1179 if (i++ == 10) {
1180 ret_val = -E1000_ERR_PHY;
1181 goto out;
1182 }
1183
1184 usleep_range(10000, 20000);
1185 }
1186 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1187
1188 if (force) {
1189 mac_reg = er32(H2ME);
1190 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1191 ew32(H2ME, mac_reg);
1192 } else {
1193 /* Clear H2ME.ULP after ME ULP configuration */
1194 mac_reg = er32(H2ME);
1195 mac_reg &= ~E1000_H2ME_ULP;
1196 ew32(H2ME, mac_reg);
1197 }
1198
1199 goto out;
1200 }
1201
1202 ret_val = hw->phy.ops.acquire(hw);
1203 if (ret_val)
1204 goto out;
1205
1206 if (force)
1207 /* Toggle LANPHYPC Value bit */
1208 e1000_toggle_lanphypc_pch_lpt(hw);
1209
1210 /* Unforce SMBus mode in PHY */
1211 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1212 if (ret_val) {
1213 /* The MAC might be in PCIe mode, so temporarily force to
1214 * SMBus mode in order to access the PHY.
1215 */
1216 mac_reg = er32(CTRL_EXT);
1217 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1218 ew32(CTRL_EXT, mac_reg);
1219
1220 msleep(50);
1221
1222 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1223 &phy_reg);
1224 if (ret_val)
1225 goto release;
1226 }
1227 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1228 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1229
1230 /* Unforce SMBus mode in MAC */
1231 mac_reg = er32(CTRL_EXT);
1232 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1233 ew32(CTRL_EXT, mac_reg);
1234
1235 /* When ULP mode was previously entered, K1 was disabled by the
1236 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1237 */
1238 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1239 if (ret_val)
1240 goto release;
1241 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1242 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1243
1244 /* Clear ULP enabled configuration */
1245 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1246 if (ret_val)
1247 goto release;
1248 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1249 I218_ULP_CONFIG1_STICKY_ULP |
1250 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1251 I218_ULP_CONFIG1_WOL_HOST |
1252 I218_ULP_CONFIG1_INBAND_EXIT |
1253 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1254 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1255
1256 /* Commit ULP changes by starting auto ULP configuration */
1257 phy_reg |= I218_ULP_CONFIG1_START;
1258 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1259
1260 /* Clear Disable SMBus Release on PERST# in MAC */
1261 mac_reg = er32(FEXTNVM7);
1262 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1263 ew32(FEXTNVM7, mac_reg);
1264
1265 release:
1266 hw->phy.ops.release(hw);
1267 if (force) {
1268 e1000_phy_hw_reset(hw);
1269 msleep(50);
1270 }
1271 out:
1272 if (ret_val)
1273 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1274 else
1275 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1276
1277 return ret_val;
1278 }
1279
1280 /**
1281 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1282 * @hw: pointer to the HW structure
1283 *
1284 * Checks to see of the link status of the hardware has changed. If a
1285 * change in link status has been detected, then we read the PHY registers
1286 * to get the current speed/duplex if link exists.
1287 **/
1288 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1289 {
1290 struct e1000_mac_info *mac = &hw->mac;
1291 s32 ret_val;
1292 bool link;
1293 u16 phy_reg;
1294
1295 /* We only want to go out to the PHY registers to see if Auto-Neg
1296 * has completed and/or if our link status has changed. The
1297 * get_link_status flag is set upon receiving a Link Status
1298 * Change or Rx Sequence Error interrupt.
1299 */
1300 if (!mac->get_link_status)
1301 return 0;
1302
1303 /* First we want to see if the MII Status Register reports
1304 * link. If so, then we want to get the current speed/duplex
1305 * of the PHY.
1306 */
1307 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1308 if (ret_val)
1309 return ret_val;
1310
1311 if (hw->mac.type == e1000_pchlan) {
1312 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1313 if (ret_val)
1314 return ret_val;
1315 }
1316
1317 /* When connected at 10Mbps half-duplex, 82579 parts are excessively
1318 * aggressive resulting in many collisions. To avoid this, increase
1319 * the IPG and reduce Rx latency in the PHY.
1320 */
1321 if ((hw->mac.type == e1000_pch2lan) && link) {
1322 u32 reg;
1323 reg = er32(STATUS);
1324 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1325 reg = er32(TIPG);
1326 reg &= ~E1000_TIPG_IPGT_MASK;
1327 reg |= 0xFF;
1328 ew32(TIPG, reg);
1329
1330 /* Reduce Rx latency in analog PHY */
1331 ret_val = hw->phy.ops.acquire(hw);
1332 if (ret_val)
1333 return ret_val;
1334
1335 ret_val =
1336 e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0);
1337
1338 hw->phy.ops.release(hw);
1339
1340 if (ret_val)
1341 return ret_val;
1342 }
1343 }
1344
1345 /* Work-around I218 hang issue */
1346 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1347 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1348 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1349 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1350 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1351 if (ret_val)
1352 return ret_val;
1353 }
1354
1355 if (hw->mac.type == e1000_pch_lpt) {
1356 /* Set platform power management values for
1357 * Latency Tolerance Reporting (LTR)
1358 */
1359 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1360 if (ret_val)
1361 return ret_val;
1362 }
1363
1364 /* Clear link partner's EEE ability */
1365 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1366
1367 if (!link)
1368 return 0; /* No link detected */
1369
1370 mac->get_link_status = false;
1371
1372 switch (hw->mac.type) {
1373 case e1000_pch2lan:
1374 ret_val = e1000_k1_workaround_lv(hw);
1375 if (ret_val)
1376 return ret_val;
1377 /* fall-thru */
1378 case e1000_pchlan:
1379 if (hw->phy.type == e1000_phy_82578) {
1380 ret_val = e1000_link_stall_workaround_hv(hw);
1381 if (ret_val)
1382 return ret_val;
1383 }
1384
1385 /* Workaround for PCHx parts in half-duplex:
1386 * Set the number of preambles removed from the packet
1387 * when it is passed from the PHY to the MAC to prevent
1388 * the MAC from misinterpreting the packet type.
1389 */
1390 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1391 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1392
1393 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1394 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1395
1396 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1397 break;
1398 default:
1399 break;
1400 }
1401
1402 /* Check if there was DownShift, must be checked
1403 * immediately after link-up
1404 */
1405 e1000e_check_downshift(hw);
1406
1407 /* Enable/Disable EEE after link up */
1408 if (hw->phy.type > e1000_phy_82579) {
1409 ret_val = e1000_set_eee_pchlan(hw);
1410 if (ret_val)
1411 return ret_val;
1412 }
1413
1414 /* If we are forcing speed/duplex, then we simply return since
1415 * we have already determined whether we have link or not.
1416 */
1417 if (!mac->autoneg)
1418 return -E1000_ERR_CONFIG;
1419
1420 /* Auto-Neg is enabled. Auto Speed Detection takes care
1421 * of MAC speed/duplex configuration. So we only need to
1422 * configure Collision Distance in the MAC.
1423 */
1424 mac->ops.config_collision_dist(hw);
1425
1426 /* Configure Flow Control now that Auto-Neg has completed.
1427 * First, we need to restore the desired flow control
1428 * settings because we may have had to re-autoneg with a
1429 * different link partner.
1430 */
1431 ret_val = e1000e_config_fc_after_link_up(hw);
1432 if (ret_val)
1433 e_dbg("Error configuring flow control\n");
1434
1435 return ret_val;
1436 }
1437
1438 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1439 {
1440 struct e1000_hw *hw = &adapter->hw;
1441 s32 rc;
1442
1443 rc = e1000_init_mac_params_ich8lan(hw);
1444 if (rc)
1445 return rc;
1446
1447 rc = e1000_init_nvm_params_ich8lan(hw);
1448 if (rc)
1449 return rc;
1450
1451 switch (hw->mac.type) {
1452 case e1000_ich8lan:
1453 case e1000_ich9lan:
1454 case e1000_ich10lan:
1455 rc = e1000_init_phy_params_ich8lan(hw);
1456 break;
1457 case e1000_pchlan:
1458 case e1000_pch2lan:
1459 case e1000_pch_lpt:
1460 rc = e1000_init_phy_params_pchlan(hw);
1461 break;
1462 default:
1463 break;
1464 }
1465 if (rc)
1466 return rc;
1467
1468 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1469 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1470 */
1471 if ((adapter->hw.phy.type == e1000_phy_ife) ||
1472 ((adapter->hw.mac.type >= e1000_pch2lan) &&
1473 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1474 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1475 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
1476
1477 hw->mac.ops.blink_led = NULL;
1478 }
1479
1480 if ((adapter->hw.mac.type == e1000_ich8lan) &&
1481 (adapter->hw.phy.type != e1000_phy_ife))
1482 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1483
1484 /* Enable workaround for 82579 w/ ME enabled */
1485 if ((adapter->hw.mac.type == e1000_pch2lan) &&
1486 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1487 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1488
1489 return 0;
1490 }
1491
1492 static DEFINE_MUTEX(nvm_mutex);
1493
1494 /**
1495 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1496 * @hw: pointer to the HW structure
1497 *
1498 * Acquires the mutex for performing NVM operations.
1499 **/
1500 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1501 {
1502 mutex_lock(&nvm_mutex);
1503
1504 return 0;
1505 }
1506
1507 /**
1508 * e1000_release_nvm_ich8lan - Release NVM mutex
1509 * @hw: pointer to the HW structure
1510 *
1511 * Releases the mutex used while performing NVM operations.
1512 **/
1513 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1514 {
1515 mutex_unlock(&nvm_mutex);
1516 }
1517
1518 /**
1519 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1520 * @hw: pointer to the HW structure
1521 *
1522 * Acquires the software control flag for performing PHY and select
1523 * MAC CSR accesses.
1524 **/
1525 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1526 {
1527 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1528 s32 ret_val = 0;
1529
1530 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1531 &hw->adapter->state)) {
1532 e_dbg("contention for Phy access\n");
1533 return -E1000_ERR_PHY;
1534 }
1535
1536 while (timeout) {
1537 extcnf_ctrl = er32(EXTCNF_CTRL);
1538 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1539 break;
1540
1541 mdelay(1);
1542 timeout--;
1543 }
1544
1545 if (!timeout) {
1546 e_dbg("SW has already locked the resource.\n");
1547 ret_val = -E1000_ERR_CONFIG;
1548 goto out;
1549 }
1550
1551 timeout = SW_FLAG_TIMEOUT;
1552
1553 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1554 ew32(EXTCNF_CTRL, extcnf_ctrl);
1555
1556 while (timeout) {
1557 extcnf_ctrl = er32(EXTCNF_CTRL);
1558 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1559 break;
1560
1561 mdelay(1);
1562 timeout--;
1563 }
1564
1565 if (!timeout) {
1566 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1567 er32(FWSM), extcnf_ctrl);
1568 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1569 ew32(EXTCNF_CTRL, extcnf_ctrl);
1570 ret_val = -E1000_ERR_CONFIG;
1571 goto out;
1572 }
1573
1574 out:
1575 if (ret_val)
1576 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1577
1578 return ret_val;
1579 }
1580
1581 /**
1582 * e1000_release_swflag_ich8lan - Release software control flag
1583 * @hw: pointer to the HW structure
1584 *
1585 * Releases the software control flag for performing PHY and select
1586 * MAC CSR accesses.
1587 **/
1588 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1589 {
1590 u32 extcnf_ctrl;
1591
1592 extcnf_ctrl = er32(EXTCNF_CTRL);
1593
1594 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1595 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1596 ew32(EXTCNF_CTRL, extcnf_ctrl);
1597 } else {
1598 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1599 }
1600
1601 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1602 }
1603
1604 /**
1605 * e1000_check_mng_mode_ich8lan - Checks management mode
1606 * @hw: pointer to the HW structure
1607 *
1608 * This checks if the adapter has any manageability enabled.
1609 * This is a function pointer entry point only called by read/write
1610 * routines for the PHY and NVM parts.
1611 **/
1612 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1613 {
1614 u32 fwsm;
1615
1616 fwsm = er32(FWSM);
1617 return ((fwsm & E1000_ICH_FWSM_FW_VALID) &&
1618 ((fwsm & E1000_FWSM_MODE_MASK) ==
1619 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)));
1620 }
1621
1622 /**
1623 * e1000_check_mng_mode_pchlan - Checks management mode
1624 * @hw: pointer to the HW structure
1625 *
1626 * This checks if the adapter has iAMT enabled.
1627 * This is a function pointer entry point only called by read/write
1628 * routines for the PHY and NVM parts.
1629 **/
1630 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1631 {
1632 u32 fwsm;
1633
1634 fwsm = er32(FWSM);
1635 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1636 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1637 }
1638
1639 /**
1640 * e1000_rar_set_pch2lan - Set receive address register
1641 * @hw: pointer to the HW structure
1642 * @addr: pointer to the receive address
1643 * @index: receive address array register
1644 *
1645 * Sets the receive address array register at index to the address passed
1646 * in by addr. For 82579, RAR[0] is the base address register that is to
1647 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1648 * Use SHRA[0-3] in place of those reserved for ME.
1649 **/
1650 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1651 {
1652 u32 rar_low, rar_high;
1653
1654 /* HW expects these in little endian so we reverse the byte order
1655 * from network order (big endian) to little endian
1656 */
1657 rar_low = ((u32)addr[0] |
1658 ((u32)addr[1] << 8) |
1659 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1660
1661 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1662
1663 /* If MAC address zero, no need to set the AV bit */
1664 if (rar_low || rar_high)
1665 rar_high |= E1000_RAH_AV;
1666
1667 if (index == 0) {
1668 ew32(RAL(index), rar_low);
1669 e1e_flush();
1670 ew32(RAH(index), rar_high);
1671 e1e_flush();
1672 return;
1673 }
1674
1675 /* RAR[1-6] are owned by manageability. Skip those and program the
1676 * next address into the SHRA register array.
1677 */
1678 if (index < (u32)(hw->mac.rar_entry_count)) {
1679 s32 ret_val;
1680
1681 ret_val = e1000_acquire_swflag_ich8lan(hw);
1682 if (ret_val)
1683 goto out;
1684
1685 ew32(SHRAL(index - 1), rar_low);
1686 e1e_flush();
1687 ew32(SHRAH(index - 1), rar_high);
1688 e1e_flush();
1689
1690 e1000_release_swflag_ich8lan(hw);
1691
1692 /* verify the register updates */
1693 if ((er32(SHRAL(index - 1)) == rar_low) &&
1694 (er32(SHRAH(index - 1)) == rar_high))
1695 return;
1696
1697 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1698 (index - 1), er32(FWSM));
1699 }
1700
1701 out:
1702 e_dbg("Failed to write receive address at index %d\n", index);
1703 }
1704
1705 /**
1706 * e1000_rar_set_pch_lpt - Set receive address registers
1707 * @hw: pointer to the HW structure
1708 * @addr: pointer to the receive address
1709 * @index: receive address array register
1710 *
1711 * Sets the receive address register array at index to the address passed
1712 * in by addr. For LPT, RAR[0] is the base address register that is to
1713 * contain the MAC address. SHRA[0-10] are the shared receive address
1714 * registers that are shared between the Host and manageability engine (ME).
1715 **/
1716 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1717 {
1718 u32 rar_low, rar_high;
1719 u32 wlock_mac;
1720
1721 /* HW expects these in little endian so we reverse the byte order
1722 * from network order (big endian) to little endian
1723 */
1724 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1725 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1726
1727 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1728
1729 /* If MAC address zero, no need to set the AV bit */
1730 if (rar_low || rar_high)
1731 rar_high |= E1000_RAH_AV;
1732
1733 if (index == 0) {
1734 ew32(RAL(index), rar_low);
1735 e1e_flush();
1736 ew32(RAH(index), rar_high);
1737 e1e_flush();
1738 return;
1739 }
1740
1741 /* The manageability engine (ME) can lock certain SHRAR registers that
1742 * it is using - those registers are unavailable for use.
1743 */
1744 if (index < hw->mac.rar_entry_count) {
1745 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1746 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1747
1748 /* Check if all SHRAR registers are locked */
1749 if (wlock_mac == 1)
1750 goto out;
1751
1752 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1753 s32 ret_val;
1754
1755 ret_val = e1000_acquire_swflag_ich8lan(hw);
1756
1757 if (ret_val)
1758 goto out;
1759
1760 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1761 e1e_flush();
1762 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1763 e1e_flush();
1764
1765 e1000_release_swflag_ich8lan(hw);
1766
1767 /* verify the register updates */
1768 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1769 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1770 return;
1771 }
1772 }
1773
1774 out:
1775 e_dbg("Failed to write receive address at index %d\n", index);
1776 }
1777
1778 /**
1779 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1780 * @hw: pointer to the HW structure
1781 *
1782 * Checks if firmware is blocking the reset of the PHY.
1783 * This is a function pointer entry point only called by
1784 * reset routines.
1785 **/
1786 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1787 {
1788 bool blocked = false;
1789 int i = 0;
1790
1791 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
1792 (i++ < 10))
1793 usleep_range(10000, 20000);
1794 return blocked ? E1000_BLK_PHY_RESET : 0;
1795 }
1796
1797 /**
1798 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1799 * @hw: pointer to the HW structure
1800 *
1801 * Assumes semaphore already acquired.
1802 *
1803 **/
1804 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1805 {
1806 u16 phy_data;
1807 u32 strap = er32(STRAP);
1808 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1809 E1000_STRAP_SMT_FREQ_SHIFT;
1810 s32 ret_val;
1811
1812 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1813
1814 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1815 if (ret_val)
1816 return ret_val;
1817
1818 phy_data &= ~HV_SMB_ADDR_MASK;
1819 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1820 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1821
1822 if (hw->phy.type == e1000_phy_i217) {
1823 /* Restore SMBus frequency */
1824 if (freq--) {
1825 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1826 phy_data |= (freq & (1 << 0)) <<
1827 HV_SMB_ADDR_FREQ_LOW_SHIFT;
1828 phy_data |= (freq & (1 << 1)) <<
1829 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1830 } else {
1831 e_dbg("Unsupported SMB frequency in PHY\n");
1832 }
1833 }
1834
1835 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1836 }
1837
1838 /**
1839 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1840 * @hw: pointer to the HW structure
1841 *
1842 * SW should configure the LCD from the NVM extended configuration region
1843 * as a workaround for certain parts.
1844 **/
1845 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1846 {
1847 struct e1000_phy_info *phy = &hw->phy;
1848 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1849 s32 ret_val = 0;
1850 u16 word_addr, reg_data, reg_addr, phy_page = 0;
1851
1852 /* Initialize the PHY from the NVM on ICH platforms. This
1853 * is needed due to an issue where the NVM configuration is
1854 * not properly autoloaded after power transitions.
1855 * Therefore, after each PHY reset, we will load the
1856 * configuration data out of the NVM manually.
1857 */
1858 switch (hw->mac.type) {
1859 case e1000_ich8lan:
1860 if (phy->type != e1000_phy_igp_3)
1861 return ret_val;
1862
1863 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1864 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1865 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1866 break;
1867 }
1868 /* Fall-thru */
1869 case e1000_pchlan:
1870 case e1000_pch2lan:
1871 case e1000_pch_lpt:
1872 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1873 break;
1874 default:
1875 return ret_val;
1876 }
1877
1878 ret_val = hw->phy.ops.acquire(hw);
1879 if (ret_val)
1880 return ret_val;
1881
1882 data = er32(FEXTNVM);
1883 if (!(data & sw_cfg_mask))
1884 goto release;
1885
1886 /* Make sure HW does not configure LCD from PHY
1887 * extended configuration before SW configuration
1888 */
1889 data = er32(EXTCNF_CTRL);
1890 if ((hw->mac.type < e1000_pch2lan) &&
1891 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
1892 goto release;
1893
1894 cnf_size = er32(EXTCNF_SIZE);
1895 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1896 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1897 if (!cnf_size)
1898 goto release;
1899
1900 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1901 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1902
1903 if (((hw->mac.type == e1000_pchlan) &&
1904 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1905 (hw->mac.type > e1000_pchlan)) {
1906 /* HW configures the SMBus address and LEDs when the
1907 * OEM and LCD Write Enable bits are set in the NVM.
1908 * When both NVM bits are cleared, SW will configure
1909 * them instead.
1910 */
1911 ret_val = e1000_write_smbus_addr(hw);
1912 if (ret_val)
1913 goto release;
1914
1915 data = er32(LEDCTL);
1916 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1917 (u16)data);
1918 if (ret_val)
1919 goto release;
1920 }
1921
1922 /* Configure LCD from extended configuration region. */
1923
1924 /* cnf_base_addr is in DWORD */
1925 word_addr = (u16)(cnf_base_addr << 1);
1926
1927 for (i = 0; i < cnf_size; i++) {
1928 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
1929 if (ret_val)
1930 goto release;
1931
1932 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1933 1, &reg_addr);
1934 if (ret_val)
1935 goto release;
1936
1937 /* Save off the PHY page for future writes. */
1938 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1939 phy_page = reg_data;
1940 continue;
1941 }
1942
1943 reg_addr &= PHY_REG_MASK;
1944 reg_addr |= phy_page;
1945
1946 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
1947 if (ret_val)
1948 goto release;
1949 }
1950
1951 release:
1952 hw->phy.ops.release(hw);
1953 return ret_val;
1954 }
1955
1956 /**
1957 * e1000_k1_gig_workaround_hv - K1 Si workaround
1958 * @hw: pointer to the HW structure
1959 * @link: link up bool flag
1960 *
1961 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1962 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1963 * If link is down, the function will restore the default K1 setting located
1964 * in the NVM.
1965 **/
1966 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1967 {
1968 s32 ret_val = 0;
1969 u16 status_reg = 0;
1970 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1971
1972 if (hw->mac.type != e1000_pchlan)
1973 return 0;
1974
1975 /* Wrap the whole flow with the sw flag */
1976 ret_val = hw->phy.ops.acquire(hw);
1977 if (ret_val)
1978 return ret_val;
1979
1980 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1981 if (link) {
1982 if (hw->phy.type == e1000_phy_82578) {
1983 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
1984 &status_reg);
1985 if (ret_val)
1986 goto release;
1987
1988 status_reg &= (BM_CS_STATUS_LINK_UP |
1989 BM_CS_STATUS_RESOLVED |
1990 BM_CS_STATUS_SPEED_MASK);
1991
1992 if (status_reg == (BM_CS_STATUS_LINK_UP |
1993 BM_CS_STATUS_RESOLVED |
1994 BM_CS_STATUS_SPEED_1000))
1995 k1_enable = false;
1996 }
1997
1998 if (hw->phy.type == e1000_phy_82577) {
1999 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2000 if (ret_val)
2001 goto release;
2002
2003 status_reg &= (HV_M_STATUS_LINK_UP |
2004 HV_M_STATUS_AUTONEG_COMPLETE |
2005 HV_M_STATUS_SPEED_MASK);
2006
2007 if (status_reg == (HV_M_STATUS_LINK_UP |
2008 HV_M_STATUS_AUTONEG_COMPLETE |
2009 HV_M_STATUS_SPEED_1000))
2010 k1_enable = false;
2011 }
2012
2013 /* Link stall fix for link up */
2014 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2015 if (ret_val)
2016 goto release;
2017
2018 } else {
2019 /* Link stall fix for link down */
2020 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2021 if (ret_val)
2022 goto release;
2023 }
2024
2025 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2026
2027 release:
2028 hw->phy.ops.release(hw);
2029
2030 return ret_val;
2031 }
2032
2033 /**
2034 * e1000_configure_k1_ich8lan - Configure K1 power state
2035 * @hw: pointer to the HW structure
2036 * @enable: K1 state to configure
2037 *
2038 * Configure the K1 power state based on the provided parameter.
2039 * Assumes semaphore already acquired.
2040 *
2041 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2042 **/
2043 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2044 {
2045 s32 ret_val;
2046 u32 ctrl_reg = 0;
2047 u32 ctrl_ext = 0;
2048 u32 reg = 0;
2049 u16 kmrn_reg = 0;
2050
2051 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2052 &kmrn_reg);
2053 if (ret_val)
2054 return ret_val;
2055
2056 if (k1_enable)
2057 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2058 else
2059 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2060
2061 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2062 kmrn_reg);
2063 if (ret_val)
2064 return ret_val;
2065
2066 usleep_range(20, 40);
2067 ctrl_ext = er32(CTRL_EXT);
2068 ctrl_reg = er32(CTRL);
2069
2070 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2071 reg |= E1000_CTRL_FRCSPD;
2072 ew32(CTRL, reg);
2073
2074 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2075 e1e_flush();
2076 usleep_range(20, 40);
2077 ew32(CTRL, ctrl_reg);
2078 ew32(CTRL_EXT, ctrl_ext);
2079 e1e_flush();
2080 usleep_range(20, 40);
2081
2082 return 0;
2083 }
2084
2085 /**
2086 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2087 * @hw: pointer to the HW structure
2088 * @d0_state: boolean if entering d0 or d3 device state
2089 *
2090 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2091 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2092 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2093 **/
2094 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2095 {
2096 s32 ret_val = 0;
2097 u32 mac_reg;
2098 u16 oem_reg;
2099
2100 if (hw->mac.type < e1000_pchlan)
2101 return ret_val;
2102
2103 ret_val = hw->phy.ops.acquire(hw);
2104 if (ret_val)
2105 return ret_val;
2106
2107 if (hw->mac.type == e1000_pchlan) {
2108 mac_reg = er32(EXTCNF_CTRL);
2109 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2110 goto release;
2111 }
2112
2113 mac_reg = er32(FEXTNVM);
2114 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2115 goto release;
2116
2117 mac_reg = er32(PHY_CTRL);
2118
2119 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2120 if (ret_val)
2121 goto release;
2122
2123 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2124
2125 if (d0_state) {
2126 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2127 oem_reg |= HV_OEM_BITS_GBE_DIS;
2128
2129 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2130 oem_reg |= HV_OEM_BITS_LPLU;
2131 } else {
2132 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2133 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2134 oem_reg |= HV_OEM_BITS_GBE_DIS;
2135
2136 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2137 E1000_PHY_CTRL_NOND0A_LPLU))
2138 oem_reg |= HV_OEM_BITS_LPLU;
2139 }
2140
2141 /* Set Restart auto-neg to activate the bits */
2142 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2143 !hw->phy.ops.check_reset_block(hw))
2144 oem_reg |= HV_OEM_BITS_RESTART_AN;
2145
2146 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2147
2148 release:
2149 hw->phy.ops.release(hw);
2150
2151 return ret_val;
2152 }
2153
2154 /**
2155 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2156 * @hw: pointer to the HW structure
2157 **/
2158 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2159 {
2160 s32 ret_val;
2161 u16 data;
2162
2163 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2164 if (ret_val)
2165 return ret_val;
2166
2167 data |= HV_KMRN_MDIO_SLOW;
2168
2169 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2170
2171 return ret_val;
2172 }
2173
2174 /**
2175 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2176 * done after every PHY reset.
2177 **/
2178 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2179 {
2180 s32 ret_val = 0;
2181 u16 phy_data;
2182
2183 if (hw->mac.type != e1000_pchlan)
2184 return 0;
2185
2186 /* Set MDIO slow mode before any other MDIO access */
2187 if (hw->phy.type == e1000_phy_82577) {
2188 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2189 if (ret_val)
2190 return ret_val;
2191 }
2192
2193 if (((hw->phy.type == e1000_phy_82577) &&
2194 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2195 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2196 /* Disable generation of early preamble */
2197 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2198 if (ret_val)
2199 return ret_val;
2200
2201 /* Preamble tuning for SSC */
2202 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2203 if (ret_val)
2204 return ret_val;
2205 }
2206
2207 if (hw->phy.type == e1000_phy_82578) {
2208 /* Return registers to default by doing a soft reset then
2209 * writing 0x3140 to the control register.
2210 */
2211 if (hw->phy.revision < 2) {
2212 e1000e_phy_sw_reset(hw);
2213 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2214 }
2215 }
2216
2217 /* Select page 0 */
2218 ret_val = hw->phy.ops.acquire(hw);
2219 if (ret_val)
2220 return ret_val;
2221
2222 hw->phy.addr = 1;
2223 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2224 hw->phy.ops.release(hw);
2225 if (ret_val)
2226 return ret_val;
2227
2228 /* Configure the K1 Si workaround during phy reset assuming there is
2229 * link so that it disables K1 if link is in 1Gbps.
2230 */
2231 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2232 if (ret_val)
2233 return ret_val;
2234
2235 /* Workaround for link disconnects on a busy hub in half duplex */
2236 ret_val = hw->phy.ops.acquire(hw);
2237 if (ret_val)
2238 return ret_val;
2239 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2240 if (ret_val)
2241 goto release;
2242 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2243 if (ret_val)
2244 goto release;
2245
2246 /* set MSE higher to enable link to stay up when noise is high */
2247 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2248 release:
2249 hw->phy.ops.release(hw);
2250
2251 return ret_val;
2252 }
2253
2254 /**
2255 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2256 * @hw: pointer to the HW structure
2257 **/
2258 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2259 {
2260 u32 mac_reg;
2261 u16 i, phy_reg = 0;
2262 s32 ret_val;
2263
2264 ret_val = hw->phy.ops.acquire(hw);
2265 if (ret_val)
2266 return;
2267 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2268 if (ret_val)
2269 goto release;
2270
2271 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2272 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2273 mac_reg = er32(RAL(i));
2274 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2275 (u16)(mac_reg & 0xFFFF));
2276 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2277 (u16)((mac_reg >> 16) & 0xFFFF));
2278
2279 mac_reg = er32(RAH(i));
2280 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2281 (u16)(mac_reg & 0xFFFF));
2282 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2283 (u16)((mac_reg & E1000_RAH_AV)
2284 >> 16));
2285 }
2286
2287 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2288
2289 release:
2290 hw->phy.ops.release(hw);
2291 }
2292
2293 /**
2294 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2295 * with 82579 PHY
2296 * @hw: pointer to the HW structure
2297 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2298 **/
2299 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2300 {
2301 s32 ret_val = 0;
2302 u16 phy_reg, data;
2303 u32 mac_reg;
2304 u16 i;
2305
2306 if (hw->mac.type < e1000_pch2lan)
2307 return 0;
2308
2309 /* disable Rx path while enabling/disabling workaround */
2310 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2311 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
2312 if (ret_val)
2313 return ret_val;
2314
2315 if (enable) {
2316 /* Write Rx addresses (rar_entry_count for RAL/H, and
2317 * SHRAL/H) and initial CRC values to the MAC
2318 */
2319 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2320 u8 mac_addr[ETH_ALEN] = { 0 };
2321 u32 addr_high, addr_low;
2322
2323 addr_high = er32(RAH(i));
2324 if (!(addr_high & E1000_RAH_AV))
2325 continue;
2326 addr_low = er32(RAL(i));
2327 mac_addr[0] = (addr_low & 0xFF);
2328 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2329 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2330 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2331 mac_addr[4] = (addr_high & 0xFF);
2332 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2333
2334 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2335 }
2336
2337 /* Write Rx addresses to the PHY */
2338 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2339
2340 /* Enable jumbo frame workaround in the MAC */
2341 mac_reg = er32(FFLT_DBG);
2342 mac_reg &= ~(1 << 14);
2343 mac_reg |= (7 << 15);
2344 ew32(FFLT_DBG, mac_reg);
2345
2346 mac_reg = er32(RCTL);
2347 mac_reg |= E1000_RCTL_SECRC;
2348 ew32(RCTL, mac_reg);
2349
2350 ret_val = e1000e_read_kmrn_reg(hw,
2351 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2352 &data);
2353 if (ret_val)
2354 return ret_val;
2355 ret_val = e1000e_write_kmrn_reg(hw,
2356 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2357 data | (1 << 0));
2358 if (ret_val)
2359 return ret_val;
2360 ret_val = e1000e_read_kmrn_reg(hw,
2361 E1000_KMRNCTRLSTA_HD_CTRL,
2362 &data);
2363 if (ret_val)
2364 return ret_val;
2365 data &= ~(0xF << 8);
2366 data |= (0xB << 8);
2367 ret_val = e1000e_write_kmrn_reg(hw,
2368 E1000_KMRNCTRLSTA_HD_CTRL,
2369 data);
2370 if (ret_val)
2371 return ret_val;
2372
2373 /* Enable jumbo frame workaround in the PHY */
2374 e1e_rphy(hw, PHY_REG(769, 23), &data);
2375 data &= ~(0x7F << 5);
2376 data |= (0x37 << 5);
2377 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2378 if (ret_val)
2379 return ret_val;
2380 e1e_rphy(hw, PHY_REG(769, 16), &data);
2381 data &= ~(1 << 13);
2382 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2383 if (ret_val)
2384 return ret_val;
2385 e1e_rphy(hw, PHY_REG(776, 20), &data);
2386 data &= ~(0x3FF << 2);
2387 data |= (0x1A << 2);
2388 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2389 if (ret_val)
2390 return ret_val;
2391 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2392 if (ret_val)
2393 return ret_val;
2394 e1e_rphy(hw, HV_PM_CTRL, &data);
2395 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
2396 if (ret_val)
2397 return ret_val;
2398 } else {
2399 /* Write MAC register values back to h/w defaults */
2400 mac_reg = er32(FFLT_DBG);
2401 mac_reg &= ~(0xF << 14);
2402 ew32(FFLT_DBG, mac_reg);
2403
2404 mac_reg = er32(RCTL);
2405 mac_reg &= ~E1000_RCTL_SECRC;
2406 ew32(RCTL, mac_reg);
2407
2408 ret_val = e1000e_read_kmrn_reg(hw,
2409 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2410 &data);
2411 if (ret_val)
2412 return ret_val;
2413 ret_val = e1000e_write_kmrn_reg(hw,
2414 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2415 data & ~(1 << 0));
2416 if (ret_val)
2417 return ret_val;
2418 ret_val = e1000e_read_kmrn_reg(hw,
2419 E1000_KMRNCTRLSTA_HD_CTRL,
2420 &data);
2421 if (ret_val)
2422 return ret_val;
2423 data &= ~(0xF << 8);
2424 data |= (0xB << 8);
2425 ret_val = e1000e_write_kmrn_reg(hw,
2426 E1000_KMRNCTRLSTA_HD_CTRL,
2427 data);
2428 if (ret_val)
2429 return ret_val;
2430
2431 /* Write PHY register values back to h/w defaults */
2432 e1e_rphy(hw, PHY_REG(769, 23), &data);
2433 data &= ~(0x7F << 5);
2434 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2435 if (ret_val)
2436 return ret_val;
2437 e1e_rphy(hw, PHY_REG(769, 16), &data);
2438 data |= (1 << 13);
2439 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2440 if (ret_val)
2441 return ret_val;
2442 e1e_rphy(hw, PHY_REG(776, 20), &data);
2443 data &= ~(0x3FF << 2);
2444 data |= (0x8 << 2);
2445 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2446 if (ret_val)
2447 return ret_val;
2448 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2449 if (ret_val)
2450 return ret_val;
2451 e1e_rphy(hw, HV_PM_CTRL, &data);
2452 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
2453 if (ret_val)
2454 return ret_val;
2455 }
2456
2457 /* re-enable Rx path after enabling/disabling workaround */
2458 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
2459 }
2460
2461 /**
2462 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2463 * done after every PHY reset.
2464 **/
2465 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2466 {
2467 s32 ret_val = 0;
2468
2469 if (hw->mac.type != e1000_pch2lan)
2470 return 0;
2471
2472 /* Set MDIO slow mode before any other MDIO access */
2473 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2474 if (ret_val)
2475 return ret_val;
2476
2477 ret_val = hw->phy.ops.acquire(hw);
2478 if (ret_val)
2479 return ret_val;
2480 /* set MSE higher to enable link to stay up when noise is high */
2481 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2482 if (ret_val)
2483 goto release;
2484 /* drop link after 5 times MSE threshold was reached */
2485 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2486 release:
2487 hw->phy.ops.release(hw);
2488
2489 return ret_val;
2490 }
2491
2492 /**
2493 * e1000_k1_gig_workaround_lv - K1 Si workaround
2494 * @hw: pointer to the HW structure
2495 *
2496 * Workaround to set the K1 beacon duration for 82579 parts
2497 **/
2498 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2499 {
2500 s32 ret_val = 0;
2501 u16 status_reg = 0;
2502 u32 mac_reg;
2503 u16 phy_reg;
2504
2505 if (hw->mac.type != e1000_pch2lan)
2506 return 0;
2507
2508 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
2509 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2510 if (ret_val)
2511 return ret_val;
2512
2513 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2514 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2515 mac_reg = er32(FEXTNVM4);
2516 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2517
2518 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
2519 if (ret_val)
2520 return ret_val;
2521
2522 if (status_reg & HV_M_STATUS_SPEED_1000) {
2523 u16 pm_phy_reg;
2524
2525 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
2526 phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2527 /* LV 1G Packet drop issue wa */
2528 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2529 if (ret_val)
2530 return ret_val;
2531 pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
2532 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2533 if (ret_val)
2534 return ret_val;
2535 } else {
2536 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2537 phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2538 }
2539 ew32(FEXTNVM4, mac_reg);
2540 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
2541 }
2542
2543 return ret_val;
2544 }
2545
2546 /**
2547 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2548 * @hw: pointer to the HW structure
2549 * @gate: boolean set to true to gate, false to ungate
2550 *
2551 * Gate/ungate the automatic PHY configuration via hardware; perform
2552 * the configuration via software instead.
2553 **/
2554 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2555 {
2556 u32 extcnf_ctrl;
2557
2558 if (hw->mac.type < e1000_pch2lan)
2559 return;
2560
2561 extcnf_ctrl = er32(EXTCNF_CTRL);
2562
2563 if (gate)
2564 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2565 else
2566 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2567
2568 ew32(EXTCNF_CTRL, extcnf_ctrl);
2569 }
2570
2571 /**
2572 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2573 * @hw: pointer to the HW structure
2574 *
2575 * Check the appropriate indication the MAC has finished configuring the
2576 * PHY after a software reset.
2577 **/
2578 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2579 {
2580 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2581
2582 /* Wait for basic configuration completes before proceeding */
2583 do {
2584 data = er32(STATUS);
2585 data &= E1000_STATUS_LAN_INIT_DONE;
2586 usleep_range(100, 200);
2587 } while ((!data) && --loop);
2588
2589 /* If basic configuration is incomplete before the above loop
2590 * count reaches 0, loading the configuration from NVM will
2591 * leave the PHY in a bad state possibly resulting in no link.
2592 */
2593 if (loop == 0)
2594 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2595
2596 /* Clear the Init Done bit for the next init event */
2597 data = er32(STATUS);
2598 data &= ~E1000_STATUS_LAN_INIT_DONE;
2599 ew32(STATUS, data);
2600 }
2601
2602 /**
2603 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2604 * @hw: pointer to the HW structure
2605 **/
2606 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2607 {
2608 s32 ret_val = 0;
2609 u16 reg;
2610
2611 if (hw->phy.ops.check_reset_block(hw))
2612 return 0;
2613
2614 /* Allow time for h/w to get to quiescent state after reset */
2615 usleep_range(10000, 20000);
2616
2617 /* Perform any necessary post-reset workarounds */
2618 switch (hw->mac.type) {
2619 case e1000_pchlan:
2620 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2621 if (ret_val)
2622 return ret_val;
2623 break;
2624 case e1000_pch2lan:
2625 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2626 if (ret_val)
2627 return ret_val;
2628 break;
2629 default:
2630 break;
2631 }
2632
2633 /* Clear the host wakeup bit after lcd reset */
2634 if (hw->mac.type >= e1000_pchlan) {
2635 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2636 reg &= ~BM_WUC_HOST_WU_BIT;
2637 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2638 }
2639
2640 /* Configure the LCD with the extended configuration region in NVM */
2641 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2642 if (ret_val)
2643 return ret_val;
2644
2645 /* Configure the LCD with the OEM bits in NVM */
2646 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2647
2648 if (hw->mac.type == e1000_pch2lan) {
2649 /* Ungate automatic PHY configuration on non-managed 82579 */
2650 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2651 usleep_range(10000, 20000);
2652 e1000_gate_hw_phy_config_ich8lan(hw, false);
2653 }
2654
2655 /* Set EEE LPI Update Timer to 200usec */
2656 ret_val = hw->phy.ops.acquire(hw);
2657 if (ret_val)
2658 return ret_val;
2659 ret_val = e1000_write_emi_reg_locked(hw,
2660 I82579_LPI_UPDATE_TIMER,
2661 0x1387);
2662 hw->phy.ops.release(hw);
2663 }
2664
2665 return ret_val;
2666 }
2667
2668 /**
2669 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2670 * @hw: pointer to the HW structure
2671 *
2672 * Resets the PHY
2673 * This is a function pointer entry point called by drivers
2674 * or other shared routines.
2675 **/
2676 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2677 {
2678 s32 ret_val = 0;
2679
2680 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2681 if ((hw->mac.type == e1000_pch2lan) &&
2682 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2683 e1000_gate_hw_phy_config_ich8lan(hw, true);
2684
2685 ret_val = e1000e_phy_hw_reset_generic(hw);
2686 if (ret_val)
2687 return ret_val;
2688
2689 return e1000_post_phy_reset_ich8lan(hw);
2690 }
2691
2692 /**
2693 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2694 * @hw: pointer to the HW structure
2695 * @active: true to enable LPLU, false to disable
2696 *
2697 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2698 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2699 * the phy speed. This function will manually set the LPLU bit and restart
2700 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2701 * since it configures the same bit.
2702 **/
2703 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2704 {
2705 s32 ret_val;
2706 u16 oem_reg;
2707
2708 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2709 if (ret_val)
2710 return ret_val;
2711
2712 if (active)
2713 oem_reg |= HV_OEM_BITS_LPLU;
2714 else
2715 oem_reg &= ~HV_OEM_BITS_LPLU;
2716
2717 if (!hw->phy.ops.check_reset_block(hw))
2718 oem_reg |= HV_OEM_BITS_RESTART_AN;
2719
2720 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2721 }
2722
2723 /**
2724 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2725 * @hw: pointer to the HW structure
2726 * @active: true to enable LPLU, false to disable
2727 *
2728 * Sets the LPLU D0 state according to the active flag. When
2729 * activating LPLU this function also disables smart speed
2730 * and vice versa. LPLU will not be activated unless the
2731 * device autonegotiation advertisement meets standards of
2732 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2733 * This is a function pointer entry point only called by
2734 * PHY setup routines.
2735 **/
2736 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2737 {
2738 struct e1000_phy_info *phy = &hw->phy;
2739 u32 phy_ctrl;
2740 s32 ret_val = 0;
2741 u16 data;
2742
2743 if (phy->type == e1000_phy_ife)
2744 return 0;
2745
2746 phy_ctrl = er32(PHY_CTRL);
2747
2748 if (active) {
2749 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2750 ew32(PHY_CTRL, phy_ctrl);
2751
2752 if (phy->type != e1000_phy_igp_3)
2753 return 0;
2754
2755 /* Call gig speed drop workaround on LPLU before accessing
2756 * any PHY registers
2757 */
2758 if (hw->mac.type == e1000_ich8lan)
2759 e1000e_gig_downshift_workaround_ich8lan(hw);
2760
2761 /* When LPLU is enabled, we should disable SmartSpeed */
2762 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2763 if (ret_val)
2764 return ret_val;
2765 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2766 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2767 if (ret_val)
2768 return ret_val;
2769 } else {
2770 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2771 ew32(PHY_CTRL, phy_ctrl);
2772
2773 if (phy->type != e1000_phy_igp_3)
2774 return 0;
2775
2776 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2777 * during Dx states where the power conservation is most
2778 * important. During driver activity we should enable
2779 * SmartSpeed, so performance is maintained.
2780 */
2781 if (phy->smart_speed == e1000_smart_speed_on) {
2782 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2783 &data);
2784 if (ret_val)
2785 return ret_val;
2786
2787 data |= IGP01E1000_PSCFR_SMART_SPEED;
2788 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2789 data);
2790 if (ret_val)
2791 return ret_val;
2792 } else if (phy->smart_speed == e1000_smart_speed_off) {
2793 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2794 &data);
2795 if (ret_val)
2796 return ret_val;
2797
2798 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2799 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2800 data);
2801 if (ret_val)
2802 return ret_val;
2803 }
2804 }
2805
2806 return 0;
2807 }
2808
2809 /**
2810 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2811 * @hw: pointer to the HW structure
2812 * @active: true to enable LPLU, false to disable
2813 *
2814 * Sets the LPLU D3 state according to the active flag. When
2815 * activating LPLU this function also disables smart speed
2816 * and vice versa. LPLU will not be activated unless the
2817 * device autonegotiation advertisement meets standards of
2818 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2819 * This is a function pointer entry point only called by
2820 * PHY setup routines.
2821 **/
2822 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2823 {
2824 struct e1000_phy_info *phy = &hw->phy;
2825 u32 phy_ctrl;
2826 s32 ret_val = 0;
2827 u16 data;
2828
2829 phy_ctrl = er32(PHY_CTRL);
2830
2831 if (!active) {
2832 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2833 ew32(PHY_CTRL, phy_ctrl);
2834
2835 if (phy->type != e1000_phy_igp_3)
2836 return 0;
2837
2838 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2839 * during Dx states where the power conservation is most
2840 * important. During driver activity we should enable
2841 * SmartSpeed, so performance is maintained.
2842 */
2843 if (phy->smart_speed == e1000_smart_speed_on) {
2844 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2845 &data);
2846 if (ret_val)
2847 return ret_val;
2848
2849 data |= IGP01E1000_PSCFR_SMART_SPEED;
2850 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2851 data);
2852 if (ret_val)
2853 return ret_val;
2854 } else if (phy->smart_speed == e1000_smart_speed_off) {
2855 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2856 &data);
2857 if (ret_val)
2858 return ret_val;
2859
2860 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2861 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2862 data);
2863 if (ret_val)
2864 return ret_val;
2865 }
2866 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2867 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2868 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2869 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2870 ew32(PHY_CTRL, phy_ctrl);
2871
2872 if (phy->type != e1000_phy_igp_3)
2873 return 0;
2874
2875 /* Call gig speed drop workaround on LPLU before accessing
2876 * any PHY registers
2877 */
2878 if (hw->mac.type == e1000_ich8lan)
2879 e1000e_gig_downshift_workaround_ich8lan(hw);
2880
2881 /* When LPLU is enabled, we should disable SmartSpeed */
2882 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2883 if (ret_val)
2884 return ret_val;
2885
2886 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2887 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2888 }
2889
2890 return ret_val;
2891 }
2892
2893 /**
2894 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2895 * @hw: pointer to the HW structure
2896 * @bank: pointer to the variable that returns the active bank
2897 *
2898 * Reads signature byte from the NVM using the flash access registers.
2899 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2900 **/
2901 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2902 {
2903 u32 eecd;
2904 struct e1000_nvm_info *nvm = &hw->nvm;
2905 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2906 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2907 u8 sig_byte = 0;
2908 s32 ret_val;
2909
2910 switch (hw->mac.type) {
2911 case e1000_ich8lan:
2912 case e1000_ich9lan:
2913 eecd = er32(EECD);
2914 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2915 E1000_EECD_SEC1VAL_VALID_MASK) {
2916 if (eecd & E1000_EECD_SEC1VAL)
2917 *bank = 1;
2918 else
2919 *bank = 0;
2920
2921 return 0;
2922 }
2923 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2924 /* fall-thru */
2925 default:
2926 /* set bank to 0 in case flash read fails */
2927 *bank = 0;
2928
2929 /* Check bank 0 */
2930 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2931 &sig_byte);
2932 if (ret_val)
2933 return ret_val;
2934 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2935 E1000_ICH_NVM_SIG_VALUE) {
2936 *bank = 0;
2937 return 0;
2938 }
2939
2940 /* Check bank 1 */
2941 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2942 bank1_offset,
2943 &sig_byte);
2944 if (ret_val)
2945 return ret_val;
2946 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2947 E1000_ICH_NVM_SIG_VALUE) {
2948 *bank = 1;
2949 return 0;
2950 }
2951
2952 e_dbg("ERROR: No valid NVM bank present\n");
2953 return -E1000_ERR_NVM;
2954 }
2955 }
2956
2957 /**
2958 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
2959 * @hw: pointer to the HW structure
2960 * @offset: The offset (in bytes) of the word(s) to read.
2961 * @words: Size of data to read in words
2962 * @data: Pointer to the word(s) to read at offset.
2963 *
2964 * Reads a word(s) from the NVM using the flash access registers.
2965 **/
2966 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2967 u16 *data)
2968 {
2969 struct e1000_nvm_info *nvm = &hw->nvm;
2970 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2971 u32 act_offset;
2972 s32 ret_val = 0;
2973 u32 bank = 0;
2974 u16 i, word;
2975
2976 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2977 (words == 0)) {
2978 e_dbg("nvm parameter(s) out of bounds\n");
2979 ret_val = -E1000_ERR_NVM;
2980 goto out;
2981 }
2982
2983 nvm->ops.acquire(hw);
2984
2985 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2986 if (ret_val) {
2987 e_dbg("Could not detect valid bank, assuming bank 0\n");
2988 bank = 0;
2989 }
2990
2991 act_offset = (bank) ? nvm->flash_bank_size : 0;
2992 act_offset += offset;
2993
2994 ret_val = 0;
2995 for (i = 0; i < words; i++) {
2996 if (dev_spec->shadow_ram[offset + i].modified) {
2997 data[i] = dev_spec->shadow_ram[offset + i].value;
2998 } else {
2999 ret_val = e1000_read_flash_word_ich8lan(hw,
3000 act_offset + i,
3001 &word);
3002 if (ret_val)
3003 break;
3004 data[i] = word;
3005 }
3006 }
3007
3008 nvm->ops.release(hw);
3009
3010 out:
3011 if (ret_val)
3012 e_dbg("NVM read error: %d\n", ret_val);
3013
3014 return ret_val;
3015 }
3016
3017 /**
3018 * e1000_flash_cycle_init_ich8lan - Initialize flash
3019 * @hw: pointer to the HW structure
3020 *
3021 * This function does initial flash setup so that a new read/write/erase cycle
3022 * can be started.
3023 **/
3024 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3025 {
3026 union ich8_hws_flash_status hsfsts;
3027 s32 ret_val = -E1000_ERR_NVM;
3028
3029 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3030
3031 /* Check if the flash descriptor is valid */
3032 if (!hsfsts.hsf_status.fldesvalid) {
3033 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
3034 return -E1000_ERR_NVM;
3035 }
3036
3037 /* Clear FCERR and DAEL in hw status by writing 1 */
3038 hsfsts.hsf_status.flcerr = 1;
3039 hsfsts.hsf_status.dael = 1;
3040
3041 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3042
3043 /* Either we should have a hardware SPI cycle in progress
3044 * bit to check against, in order to start a new cycle or
3045 * FDONE bit should be changed in the hardware so that it
3046 * is 1 after hardware reset, which can then be used as an
3047 * indication whether a cycle is in progress or has been
3048 * completed.
3049 */
3050
3051 if (!hsfsts.hsf_status.flcinprog) {
3052 /* There is no cycle running at present,
3053 * so we can start a cycle.
3054 * Begin by setting Flash Cycle Done.
3055 */
3056 hsfsts.hsf_status.flcdone = 1;
3057 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3058 ret_val = 0;
3059 } else {
3060 s32 i;
3061
3062 /* Otherwise poll for sometime so the current
3063 * cycle has a chance to end before giving up.
3064 */
3065 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3066 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3067 if (!hsfsts.hsf_status.flcinprog) {
3068 ret_val = 0;
3069 break;
3070 }
3071 udelay(1);
3072 }
3073 if (!ret_val) {
3074 /* Successful in waiting for previous cycle to timeout,
3075 * now set the Flash Cycle Done.
3076 */
3077 hsfsts.hsf_status.flcdone = 1;
3078 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3079 } else {
3080 e_dbg("Flash controller busy, cannot get access\n");
3081 }
3082 }
3083
3084 return ret_val;
3085 }
3086
3087 /**
3088 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3089 * @hw: pointer to the HW structure
3090 * @timeout: maximum time to wait for completion
3091 *
3092 * This function starts a flash cycle and waits for its completion.
3093 **/
3094 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3095 {
3096 union ich8_hws_flash_ctrl hsflctl;
3097 union ich8_hws_flash_status hsfsts;
3098 u32 i = 0;
3099
3100 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3101 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3102 hsflctl.hsf_ctrl.flcgo = 1;
3103 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3104
3105 /* wait till FDONE bit is set to 1 */
3106 do {
3107 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3108 if (hsfsts.hsf_status.flcdone)
3109 break;
3110 udelay(1);
3111 } while (i++ < timeout);
3112
3113 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3114 return 0;
3115
3116 return -E1000_ERR_NVM;
3117 }
3118
3119 /**
3120 * e1000_read_flash_word_ich8lan - Read word from flash
3121 * @hw: pointer to the HW structure
3122 * @offset: offset to data location
3123 * @data: pointer to the location for storing the data
3124 *
3125 * Reads the flash word at offset into data. Offset is converted
3126 * to bytes before read.
3127 **/
3128 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3129 u16 *data)
3130 {
3131 /* Must convert offset into bytes. */
3132 offset <<= 1;
3133
3134 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3135 }
3136
3137 /**
3138 * e1000_read_flash_byte_ich8lan - Read byte from flash
3139 * @hw: pointer to the HW structure
3140 * @offset: The offset of the byte to read.
3141 * @data: Pointer to a byte to store the value read.
3142 *
3143 * Reads a single byte from the NVM using the flash access registers.
3144 **/
3145 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3146 u8 *data)
3147 {
3148 s32 ret_val;
3149 u16 word = 0;
3150
3151 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3152 if (ret_val)
3153 return ret_val;
3154
3155 *data = (u8)word;
3156
3157 return 0;
3158 }
3159
3160 /**
3161 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3162 * @hw: pointer to the HW structure
3163 * @offset: The offset (in bytes) of the byte or word to read.
3164 * @size: Size of data to read, 1=byte 2=word
3165 * @data: Pointer to the word to store the value read.
3166 *
3167 * Reads a byte or word from the NVM using the flash access registers.
3168 **/
3169 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3170 u8 size, u16 *data)
3171 {
3172 union ich8_hws_flash_status hsfsts;
3173 union ich8_hws_flash_ctrl hsflctl;
3174 u32 flash_linear_addr;
3175 u32 flash_data = 0;
3176 s32 ret_val = -E1000_ERR_NVM;
3177 u8 count = 0;
3178
3179 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3180 return -E1000_ERR_NVM;
3181
3182 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3183 hw->nvm.flash_base_addr);
3184
3185 do {
3186 udelay(1);
3187 /* Steps */
3188 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3189 if (ret_val)
3190 break;
3191
3192 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3193 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3194 hsflctl.hsf_ctrl.fldbcount = size - 1;
3195 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3196 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3197
3198 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3199
3200 ret_val =
3201 e1000_flash_cycle_ich8lan(hw,
3202 ICH_FLASH_READ_COMMAND_TIMEOUT);
3203
3204 /* Check if FCERR is set to 1, if set to 1, clear it
3205 * and try the whole sequence a few more times, else
3206 * read in (shift in) the Flash Data0, the order is
3207 * least significant byte first msb to lsb
3208 */
3209 if (!ret_val) {
3210 flash_data = er32flash(ICH_FLASH_FDATA0);
3211 if (size == 1)
3212 *data = (u8)(flash_data & 0x000000FF);
3213 else if (size == 2)
3214 *data = (u16)(flash_data & 0x0000FFFF);
3215 break;
3216 } else {
3217 /* If we've gotten here, then things are probably
3218 * completely hosed, but if the error condition is
3219 * detected, it won't hurt to give it another try...
3220 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3221 */
3222 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3223 if (hsfsts.hsf_status.flcerr) {
3224 /* Repeat for some time before giving up. */
3225 continue;
3226 } else if (!hsfsts.hsf_status.flcdone) {
3227 e_dbg("Timeout error - flash cycle did not complete.\n");
3228 break;
3229 }
3230 }
3231 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3232
3233 return ret_val;
3234 }
3235
3236 /**
3237 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3238 * @hw: pointer to the HW structure
3239 * @offset: The offset (in bytes) of the word(s) to write.
3240 * @words: Size of data to write in words
3241 * @data: Pointer to the word(s) to write at offset.
3242 *
3243 * Writes a byte or word to the NVM using the flash access registers.
3244 **/
3245 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3246 u16 *data)
3247 {
3248 struct e1000_nvm_info *nvm = &hw->nvm;
3249 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3250 u16 i;
3251
3252 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3253 (words == 0)) {
3254 e_dbg("nvm parameter(s) out of bounds\n");
3255 return -E1000_ERR_NVM;
3256 }
3257
3258 nvm->ops.acquire(hw);
3259
3260 for (i = 0; i < words; i++) {
3261 dev_spec->shadow_ram[offset + i].modified = true;
3262 dev_spec->shadow_ram[offset + i].value = data[i];
3263 }
3264
3265 nvm->ops.release(hw);
3266
3267 return 0;
3268 }
3269
3270 /**
3271 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3272 * @hw: pointer to the HW structure
3273 *
3274 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3275 * which writes the checksum to the shadow ram. The changes in the shadow
3276 * ram are then committed to the EEPROM by processing each bank at a time
3277 * checking for the modified bit and writing only the pending changes.
3278 * After a successful commit, the shadow ram is cleared and is ready for
3279 * future writes.
3280 **/
3281 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3282 {
3283 struct e1000_nvm_info *nvm = &hw->nvm;
3284 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3285 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3286 s32 ret_val;
3287 u16 data;
3288
3289 ret_val = e1000e_update_nvm_checksum_generic(hw);
3290 if (ret_val)
3291 goto out;
3292
3293 if (nvm->type != e1000_nvm_flash_sw)
3294 goto out;
3295
3296 nvm->ops.acquire(hw);
3297
3298 /* We're writing to the opposite bank so if we're on bank 1,
3299 * write to bank 0 etc. We also need to erase the segment that
3300 * is going to be written
3301 */
3302 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3303 if (ret_val) {
3304 e_dbg("Could not detect valid bank, assuming bank 0\n");
3305 bank = 0;
3306 }
3307
3308 if (bank == 0) {
3309 new_bank_offset = nvm->flash_bank_size;
3310 old_bank_offset = 0;
3311 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3312 if (ret_val)
3313 goto release;
3314 } else {
3315 old_bank_offset = nvm->flash_bank_size;
3316 new_bank_offset = 0;
3317 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3318 if (ret_val)
3319 goto release;
3320 }
3321
3322 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3323 /* Determine whether to write the value stored
3324 * in the other NVM bank or a modified value stored
3325 * in the shadow RAM
3326 */
3327 if (dev_spec->shadow_ram[i].modified) {
3328 data = dev_spec->shadow_ram[i].value;
3329 } else {
3330 ret_val = e1000_read_flash_word_ich8lan(hw, i +
3331 old_bank_offset,
3332 &data);
3333 if (ret_val)
3334 break;
3335 }
3336
3337 /* If the word is 0x13, then make sure the signature bits
3338 * (15:14) are 11b until the commit has completed.
3339 * This will allow us to write 10b which indicates the
3340 * signature is valid. We want to do this after the write
3341 * has completed so that we don't mark the segment valid
3342 * while the write is still in progress
3343 */
3344 if (i == E1000_ICH_NVM_SIG_WORD)
3345 data |= E1000_ICH_NVM_SIG_MASK;
3346
3347 /* Convert offset to bytes. */
3348 act_offset = (i + new_bank_offset) << 1;
3349
3350 usleep_range(100, 200);
3351 /* Write the bytes to the new bank. */
3352 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3353 act_offset,
3354 (u8)data);
3355 if (ret_val)
3356 break;
3357
3358 usleep_range(100, 200);
3359 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3360 act_offset + 1,
3361 (u8)(data >> 8));
3362 if (ret_val)
3363 break;
3364 }
3365
3366 /* Don't bother writing the segment valid bits if sector
3367 * programming failed.
3368 */
3369 if (ret_val) {
3370 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3371 e_dbg("Flash commit failed.\n");
3372 goto release;
3373 }
3374
3375 /* Finally validate the new segment by setting bit 15:14
3376 * to 10b in word 0x13 , this can be done without an
3377 * erase as well since these bits are 11 to start with
3378 * and we need to change bit 14 to 0b
3379 */
3380 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3381 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3382 if (ret_val)
3383 goto release;
3384
3385 data &= 0xBFFF;
3386 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3387 act_offset * 2 + 1,
3388 (u8)(data >> 8));
3389 if (ret_val)
3390 goto release;
3391
3392 /* And invalidate the previously valid segment by setting
3393 * its signature word (0x13) high_byte to 0b. This can be
3394 * done without an erase because flash erase sets all bits
3395 * to 1's. We can write 1's to 0's without an erase
3396 */
3397 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3398 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3399 if (ret_val)
3400 goto release;
3401
3402 /* Great! Everything worked, we can now clear the cached entries. */
3403 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3404 dev_spec->shadow_ram[i].modified = false;
3405 dev_spec->shadow_ram[i].value = 0xFFFF;
3406 }
3407
3408 release:
3409 nvm->ops.release(hw);
3410
3411 /* Reload the EEPROM, or else modifications will not appear
3412 * until after the next adapter reset.
3413 */
3414 if (!ret_val) {
3415 nvm->ops.reload(hw);
3416 usleep_range(10000, 20000);
3417 }
3418
3419 out:
3420 if (ret_val)
3421 e_dbg("NVM update error: %d\n", ret_val);
3422
3423 return ret_val;
3424 }
3425
3426 /**
3427 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3428 * @hw: pointer to the HW structure
3429 *
3430 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3431 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
3432 * calculated, in which case we need to calculate the checksum and set bit 6.
3433 **/
3434 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3435 {
3436 s32 ret_val;
3437 u16 data;
3438 u16 word;
3439 u16 valid_csum_mask;
3440
3441 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
3442 * the checksum needs to be fixed. This bit is an indication that
3443 * the NVM was prepared by OEM software and did not calculate
3444 * the checksum...a likely scenario.
3445 */
3446 switch (hw->mac.type) {
3447 case e1000_pch_lpt:
3448 word = NVM_COMPAT;
3449 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3450 break;
3451 default:
3452 word = NVM_FUTURE_INIT_WORD1;
3453 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3454 break;
3455 }
3456
3457 ret_val = e1000_read_nvm(hw, word, 1, &data);
3458 if (ret_val)
3459 return ret_val;
3460
3461 if (!(data & valid_csum_mask)) {
3462 data |= valid_csum_mask;
3463 ret_val = e1000_write_nvm(hw, word, 1, &data);
3464 if (ret_val)
3465 return ret_val;
3466 ret_val = e1000e_update_nvm_checksum(hw);
3467 if (ret_val)
3468 return ret_val;
3469 }
3470
3471 return e1000e_validate_nvm_checksum_generic(hw);
3472 }
3473
3474 /**
3475 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
3476 * @hw: pointer to the HW structure
3477 *
3478 * To prevent malicious write/erase of the NVM, set it to be read-only
3479 * so that the hardware ignores all write/erase cycles of the NVM via
3480 * the flash control registers. The shadow-ram copy of the NVM will
3481 * still be updated, however any updates to this copy will not stick
3482 * across driver reloads.
3483 **/
3484 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
3485 {
3486 struct e1000_nvm_info *nvm = &hw->nvm;
3487 union ich8_flash_protected_range pr0;
3488 union ich8_hws_flash_status hsfsts;
3489 u32 gfpreg;
3490
3491 nvm->ops.acquire(hw);
3492
3493 gfpreg = er32flash(ICH_FLASH_GFPREG);
3494
3495 /* Write-protect GbE Sector of NVM */
3496 pr0.regval = er32flash(ICH_FLASH_PR0);
3497 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
3498 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
3499 pr0.range.wpe = true;
3500 ew32flash(ICH_FLASH_PR0, pr0.regval);
3501
3502 /* Lock down a subset of GbE Flash Control Registers, e.g.
3503 * PR0 to prevent the write-protection from being lifted.
3504 * Once FLOCKDN is set, the registers protected by it cannot
3505 * be written until FLOCKDN is cleared by a hardware reset.
3506 */
3507 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3508 hsfsts.hsf_status.flockdn = true;
3509 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3510
3511 nvm->ops.release(hw);
3512 }
3513
3514 /**
3515 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3516 * @hw: pointer to the HW structure
3517 * @offset: The offset (in bytes) of the byte/word to read.
3518 * @size: Size of data to read, 1=byte 2=word
3519 * @data: The byte(s) to write to the NVM.
3520 *
3521 * Writes one/two bytes to the NVM using the flash access registers.
3522 **/
3523 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3524 u8 size, u16 data)
3525 {
3526 union ich8_hws_flash_status hsfsts;
3527 union ich8_hws_flash_ctrl hsflctl;
3528 u32 flash_linear_addr;
3529 u32 flash_data = 0;
3530 s32 ret_val;
3531 u8 count = 0;
3532
3533 if (size < 1 || size > 2 || data > size * 0xff ||
3534 offset > ICH_FLASH_LINEAR_ADDR_MASK)
3535 return -E1000_ERR_NVM;
3536
3537 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3538 hw->nvm.flash_base_addr);
3539
3540 do {
3541 udelay(1);
3542 /* Steps */
3543 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3544 if (ret_val)
3545 break;
3546
3547 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3548 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3549 hsflctl.hsf_ctrl.fldbcount = size - 1;
3550 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3551 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3552
3553 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3554
3555 if (size == 1)
3556 flash_data = (u32)data & 0x00FF;
3557 else
3558 flash_data = (u32)data;
3559
3560 ew32flash(ICH_FLASH_FDATA0, flash_data);
3561
3562 /* check if FCERR is set to 1 , if set to 1, clear it
3563 * and try the whole sequence a few more times else done
3564 */
3565 ret_val =
3566 e1000_flash_cycle_ich8lan(hw,
3567 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3568 if (!ret_val)
3569 break;
3570
3571 /* If we're here, then things are most likely
3572 * completely hosed, but if the error condition
3573 * is detected, it won't hurt to give it another
3574 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3575 */
3576 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3577 if (hsfsts.hsf_status.flcerr)
3578 /* Repeat for some time before giving up. */
3579 continue;
3580 if (!hsfsts.hsf_status.flcdone) {
3581 e_dbg("Timeout error - flash cycle did not complete.\n");
3582 break;
3583 }
3584 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3585
3586 return ret_val;
3587 }
3588
3589 /**
3590 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3591 * @hw: pointer to the HW structure
3592 * @offset: The index of the byte to read.
3593 * @data: The byte to write to the NVM.
3594 *
3595 * Writes a single byte to the NVM using the flash access registers.
3596 **/
3597 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3598 u8 data)
3599 {
3600 u16 word = (u16)data;
3601
3602 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3603 }
3604
3605 /**
3606 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3607 * @hw: pointer to the HW structure
3608 * @offset: The offset of the byte to write.
3609 * @byte: The byte to write to the NVM.
3610 *
3611 * Writes a single byte to the NVM using the flash access registers.
3612 * Goes through a retry algorithm before giving up.
3613 **/
3614 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3615 u32 offset, u8 byte)
3616 {
3617 s32 ret_val;
3618 u16 program_retries;
3619
3620 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3621 if (!ret_val)
3622 return ret_val;
3623
3624 for (program_retries = 0; program_retries < 100; program_retries++) {
3625 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
3626 usleep_range(100, 200);
3627 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3628 if (!ret_val)
3629 break;
3630 }
3631 if (program_retries == 100)
3632 return -E1000_ERR_NVM;
3633
3634 return 0;
3635 }
3636
3637 /**
3638 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3639 * @hw: pointer to the HW structure
3640 * @bank: 0 for first bank, 1 for second bank, etc.
3641 *
3642 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3643 * bank N is 4096 * N + flash_reg_addr.
3644 **/
3645 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3646 {
3647 struct e1000_nvm_info *nvm = &hw->nvm;
3648 union ich8_hws_flash_status hsfsts;
3649 union ich8_hws_flash_ctrl hsflctl;
3650 u32 flash_linear_addr;
3651 /* bank size is in 16bit words - adjust to bytes */
3652 u32 flash_bank_size = nvm->flash_bank_size * 2;
3653 s32 ret_val;
3654 s32 count = 0;
3655 s32 j, iteration, sector_size;
3656
3657 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3658
3659 /* Determine HW Sector size: Read BERASE bits of hw flash status
3660 * register
3661 * 00: The Hw sector is 256 bytes, hence we need to erase 16
3662 * consecutive sectors. The start index for the nth Hw sector
3663 * can be calculated as = bank * 4096 + n * 256
3664 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3665 * The start index for the nth Hw sector can be calculated
3666 * as = bank * 4096
3667 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3668 * (ich9 only, otherwise error condition)
3669 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3670 */
3671 switch (hsfsts.hsf_status.berasesz) {
3672 case 0:
3673 /* Hw sector size 256 */
3674 sector_size = ICH_FLASH_SEG_SIZE_256;
3675 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3676 break;
3677 case 1:
3678 sector_size = ICH_FLASH_SEG_SIZE_4K;
3679 iteration = 1;
3680 break;
3681 case 2:
3682 sector_size = ICH_FLASH_SEG_SIZE_8K;
3683 iteration = 1;
3684 break;
3685 case 3:
3686 sector_size = ICH_FLASH_SEG_SIZE_64K;
3687 iteration = 1;
3688 break;
3689 default:
3690 return -E1000_ERR_NVM;
3691 }
3692
3693 /* Start with the base address, then add the sector offset. */
3694 flash_linear_addr = hw->nvm.flash_base_addr;
3695 flash_linear_addr += (bank) ? flash_bank_size : 0;
3696
3697 for (j = 0; j < iteration; j++) {
3698 do {
3699 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3700
3701 /* Steps */
3702 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3703 if (ret_val)
3704 return ret_val;
3705
3706 /* Write a value 11 (block Erase) in Flash
3707 * Cycle field in hw flash control
3708 */
3709 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3710 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3711 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3712
3713 /* Write the last 24 bits of an index within the
3714 * block into Flash Linear address field in Flash
3715 * Address.
3716 */
3717 flash_linear_addr += (j * sector_size);
3718 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3719
3720 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
3721 if (!ret_val)
3722 break;
3723
3724 /* Check if FCERR is set to 1. If 1,
3725 * clear it and try the whole sequence
3726 * a few more times else Done
3727 */
3728 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3729 if (hsfsts.hsf_status.flcerr)
3730 /* repeat for some time before giving up */
3731 continue;
3732 else if (!hsfsts.hsf_status.flcdone)
3733 return ret_val;
3734 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3735 }
3736
3737 return 0;
3738 }
3739
3740 /**
3741 * e1000_valid_led_default_ich8lan - Set the default LED settings
3742 * @hw: pointer to the HW structure
3743 * @data: Pointer to the LED settings
3744 *
3745 * Reads the LED default settings from the NVM to data. If the NVM LED
3746 * settings is all 0's or F's, set the LED default to a valid LED default
3747 * setting.
3748 **/
3749 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3750 {
3751 s32 ret_val;
3752
3753 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
3754 if (ret_val) {
3755 e_dbg("NVM Read Error\n");
3756 return ret_val;
3757 }
3758
3759 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
3760 *data = ID_LED_DEFAULT_ICH8LAN;
3761
3762 return 0;
3763 }
3764
3765 /**
3766 * e1000_id_led_init_pchlan - store LED configurations
3767 * @hw: pointer to the HW structure
3768 *
3769 * PCH does not control LEDs via the LEDCTL register, rather it uses
3770 * the PHY LED configuration register.
3771 *
3772 * PCH also does not have an "always on" or "always off" mode which
3773 * complicates the ID feature. Instead of using the "on" mode to indicate
3774 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
3775 * use "link_up" mode. The LEDs will still ID on request if there is no
3776 * link based on logic in e1000_led_[on|off]_pchlan().
3777 **/
3778 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3779 {
3780 struct e1000_mac_info *mac = &hw->mac;
3781 s32 ret_val;
3782 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3783 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3784 u16 data, i, temp, shift;
3785
3786 /* Get default ID LED modes */
3787 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3788 if (ret_val)
3789 return ret_val;
3790
3791 mac->ledctl_default = er32(LEDCTL);
3792 mac->ledctl_mode1 = mac->ledctl_default;
3793 mac->ledctl_mode2 = mac->ledctl_default;
3794
3795 for (i = 0; i < 4; i++) {
3796 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3797 shift = (i * 5);
3798 switch (temp) {
3799 case ID_LED_ON1_DEF2:
3800 case ID_LED_ON1_ON2:
3801 case ID_LED_ON1_OFF2:
3802 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3803 mac->ledctl_mode1 |= (ledctl_on << shift);
3804 break;
3805 case ID_LED_OFF1_DEF2:
3806 case ID_LED_OFF1_ON2:
3807 case ID_LED_OFF1_OFF2:
3808 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3809 mac->ledctl_mode1 |= (ledctl_off << shift);
3810 break;
3811 default:
3812 /* Do nothing */
3813 break;
3814 }
3815 switch (temp) {
3816 case ID_LED_DEF1_ON2:
3817 case ID_LED_ON1_ON2:
3818 case ID_LED_OFF1_ON2:
3819 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3820 mac->ledctl_mode2 |= (ledctl_on << shift);
3821 break;
3822 case ID_LED_DEF1_OFF2:
3823 case ID_LED_ON1_OFF2:
3824 case ID_LED_OFF1_OFF2:
3825 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3826 mac->ledctl_mode2 |= (ledctl_off << shift);
3827 break;
3828 default:
3829 /* Do nothing */
3830 break;
3831 }
3832 }
3833
3834 return 0;
3835 }
3836
3837 /**
3838 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3839 * @hw: pointer to the HW structure
3840 *
3841 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3842 * register, so the the bus width is hard coded.
3843 **/
3844 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3845 {
3846 struct e1000_bus_info *bus = &hw->bus;
3847 s32 ret_val;
3848
3849 ret_val = e1000e_get_bus_info_pcie(hw);
3850
3851 /* ICH devices are "PCI Express"-ish. They have
3852 * a configuration space, but do not contain
3853 * PCI Express Capability registers, so bus width
3854 * must be hardcoded.
3855 */
3856 if (bus->width == e1000_bus_width_unknown)
3857 bus->width = e1000_bus_width_pcie_x1;
3858
3859 return ret_val;
3860 }
3861
3862 /**
3863 * e1000_reset_hw_ich8lan - Reset the hardware
3864 * @hw: pointer to the HW structure
3865 *
3866 * Does a full reset of the hardware which includes a reset of the PHY and
3867 * MAC.
3868 **/
3869 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3870 {
3871 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3872 u16 kum_cfg;
3873 u32 ctrl, reg;
3874 s32 ret_val;
3875
3876 /* Prevent the PCI-E bus from sticking if there is no TLP connection
3877 * on the last TLP read/write transaction when MAC is reset.
3878 */
3879 ret_val = e1000e_disable_pcie_master(hw);
3880 if (ret_val)
3881 e_dbg("PCI-E Master disable polling has failed.\n");
3882
3883 e_dbg("Masking off all interrupts\n");
3884 ew32(IMC, 0xffffffff);
3885
3886 /* Disable the Transmit and Receive units. Then delay to allow
3887 * any pending transactions to complete before we hit the MAC
3888 * with the global reset.
3889 */
3890 ew32(RCTL, 0);
3891 ew32(TCTL, E1000_TCTL_PSP);
3892 e1e_flush();
3893
3894 usleep_range(10000, 20000);
3895
3896 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3897 if (hw->mac.type == e1000_ich8lan) {
3898 /* Set Tx and Rx buffer allocation to 8k apiece. */
3899 ew32(PBA, E1000_PBA_8K);
3900 /* Set Packet Buffer Size to 16k. */
3901 ew32(PBS, E1000_PBS_16K);
3902 }
3903
3904 if (hw->mac.type == e1000_pchlan) {
3905 /* Save the NVM K1 bit setting */
3906 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
3907 if (ret_val)
3908 return ret_val;
3909
3910 if (kum_cfg & E1000_NVM_K1_ENABLE)
3911 dev_spec->nvm_k1_enabled = true;
3912 else
3913 dev_spec->nvm_k1_enabled = false;
3914 }
3915
3916 ctrl = er32(CTRL);
3917
3918 if (!hw->phy.ops.check_reset_block(hw)) {
3919 /* Full-chip reset requires MAC and PHY reset at the same
3920 * time to make sure the interface between MAC and the
3921 * external PHY is reset.
3922 */
3923 ctrl |= E1000_CTRL_PHY_RST;
3924
3925 /* Gate automatic PHY configuration by hardware on
3926 * non-managed 82579
3927 */
3928 if ((hw->mac.type == e1000_pch2lan) &&
3929 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3930 e1000_gate_hw_phy_config_ich8lan(hw, true);
3931 }
3932 ret_val = e1000_acquire_swflag_ich8lan(hw);
3933 e_dbg("Issuing a global reset to ich8lan\n");
3934 ew32(CTRL, (ctrl | E1000_CTRL_RST));
3935 /* cannot issue a flush here because it hangs the hardware */
3936 msleep(20);
3937
3938 /* Set Phy Config Counter to 50msec */
3939 if (hw->mac.type == e1000_pch2lan) {
3940 reg = er32(FEXTNVM3);
3941 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
3942 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
3943 ew32(FEXTNVM3, reg);
3944 }
3945
3946 if (!ret_val)
3947 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3948
3949 if (ctrl & E1000_CTRL_PHY_RST) {
3950 ret_val = hw->phy.ops.get_cfg_done(hw);
3951 if (ret_val)
3952 return ret_val;
3953
3954 ret_val = e1000_post_phy_reset_ich8lan(hw);
3955 if (ret_val)
3956 return ret_val;
3957 }
3958
3959 /* For PCH, this write will make sure that any noise
3960 * will be detected as a CRC error and be dropped rather than show up
3961 * as a bad packet to the DMA engine.
3962 */
3963 if (hw->mac.type == e1000_pchlan)
3964 ew32(CRC_OFFSET, 0x65656565);
3965
3966 ew32(IMC, 0xffffffff);
3967 er32(ICR);
3968
3969 reg = er32(KABGTXD);
3970 reg |= E1000_KABGTXD_BGSQLBIAS;
3971 ew32(KABGTXD, reg);
3972
3973 return 0;
3974 }
3975
3976 /**
3977 * e1000_init_hw_ich8lan - Initialize the hardware
3978 * @hw: pointer to the HW structure
3979 *
3980 * Prepares the hardware for transmit and receive by doing the following:
3981 * - initialize hardware bits
3982 * - initialize LED identification
3983 * - setup receive address registers
3984 * - setup flow control
3985 * - setup transmit descriptors
3986 * - clear statistics
3987 **/
3988 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3989 {
3990 struct e1000_mac_info *mac = &hw->mac;
3991 u32 ctrl_ext, txdctl, snoop;
3992 s32 ret_val;
3993 u16 i;
3994
3995 e1000_initialize_hw_bits_ich8lan(hw);
3996
3997 /* Initialize identification LED */
3998 ret_val = mac->ops.id_led_init(hw);
3999 /* An error is not fatal and we should not stop init due to this */
4000 if (ret_val)
4001 e_dbg("Error initializing identification LED\n");
4002
4003 /* Setup the receive address. */
4004 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4005
4006 /* Zero out the Multicast HASH table */
4007 e_dbg("Zeroing the MTA\n");
4008 for (i = 0; i < mac->mta_reg_count; i++)
4009 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4010
4011 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4012 * the ME. Disable wakeup by clearing the host wakeup bit.
4013 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4014 */
4015 if (hw->phy.type == e1000_phy_82578) {
4016 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4017 i &= ~BM_WUC_HOST_WU_BIT;
4018 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4019 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4020 if (ret_val)
4021 return ret_val;
4022 }
4023
4024 /* Setup link and flow control */
4025 ret_val = mac->ops.setup_link(hw);
4026
4027 /* Set the transmit descriptor write-back policy for both queues */
4028 txdctl = er32(TXDCTL(0));
4029 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4030 E1000_TXDCTL_FULL_TX_DESC_WB);
4031 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4032 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4033 ew32(TXDCTL(0), txdctl);
4034 txdctl = er32(TXDCTL(1));
4035 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4036 E1000_TXDCTL_FULL_TX_DESC_WB);
4037 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4038 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4039 ew32(TXDCTL(1), txdctl);
4040
4041 /* ICH8 has opposite polarity of no_snoop bits.
4042 * By default, we should use snoop behavior.
4043 */
4044 if (mac->type == e1000_ich8lan)
4045 snoop = PCIE_ICH8_SNOOP_ALL;
4046 else
4047 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4048 e1000e_set_pcie_no_snoop(hw, snoop);
4049
4050 ctrl_ext = er32(CTRL_EXT);
4051 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4052 ew32(CTRL_EXT, ctrl_ext);
4053
4054 /* Clear all of the statistics registers (clear on read). It is
4055 * important that we do this after we have tried to establish link
4056 * because the symbol error count will increment wildly if there
4057 * is no link.
4058 */
4059 e1000_clear_hw_cntrs_ich8lan(hw);
4060
4061 return ret_val;
4062 }
4063
4064 /**
4065 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4066 * @hw: pointer to the HW structure
4067 *
4068 * Sets/Clears required hardware bits necessary for correctly setting up the
4069 * hardware for transmit and receive.
4070 **/
4071 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4072 {
4073 u32 reg;
4074
4075 /* Extended Device Control */
4076 reg = er32(CTRL_EXT);
4077 reg |= (1 << 22);
4078 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4079 if (hw->mac.type >= e1000_pchlan)
4080 reg |= E1000_CTRL_EXT_PHYPDEN;
4081 ew32(CTRL_EXT, reg);
4082
4083 /* Transmit Descriptor Control 0 */
4084 reg = er32(TXDCTL(0));
4085 reg |= (1 << 22);
4086 ew32(TXDCTL(0), reg);
4087
4088 /* Transmit Descriptor Control 1 */
4089 reg = er32(TXDCTL(1));
4090 reg |= (1 << 22);
4091 ew32(TXDCTL(1), reg);
4092
4093 /* Transmit Arbitration Control 0 */
4094 reg = er32(TARC(0));
4095 if (hw->mac.type == e1000_ich8lan)
4096 reg |= (1 << 28) | (1 << 29);
4097 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4098 ew32(TARC(0), reg);
4099
4100 /* Transmit Arbitration Control 1 */
4101 reg = er32(TARC(1));
4102 if (er32(TCTL) & E1000_TCTL_MULR)
4103 reg &= ~(1 << 28);
4104 else
4105 reg |= (1 << 28);
4106 reg |= (1 << 24) | (1 << 26) | (1 << 30);
4107 ew32(TARC(1), reg);
4108
4109 /* Device Status */
4110 if (hw->mac.type == e1000_ich8lan) {
4111 reg = er32(STATUS);
4112 reg &= ~(1 << 31);
4113 ew32(STATUS, reg);
4114 }
4115
4116 /* work-around descriptor data corruption issue during nfs v2 udp
4117 * traffic, just disable the nfs filtering capability
4118 */
4119 reg = er32(RFCTL);
4120 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4121
4122 /* Disable IPv6 extension header parsing because some malformed
4123 * IPv6 headers can hang the Rx.
4124 */
4125 if (hw->mac.type == e1000_ich8lan)
4126 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4127 ew32(RFCTL, reg);
4128
4129 /* Enable ECC on Lynxpoint */
4130 if (hw->mac.type == e1000_pch_lpt) {
4131 reg = er32(PBECCSTS);
4132 reg |= E1000_PBECCSTS_ECC_ENABLE;
4133 ew32(PBECCSTS, reg);
4134
4135 reg = er32(CTRL);
4136 reg |= E1000_CTRL_MEHE;
4137 ew32(CTRL, reg);
4138 }
4139 }
4140
4141 /**
4142 * e1000_setup_link_ich8lan - Setup flow control and link settings
4143 * @hw: pointer to the HW structure
4144 *
4145 * Determines which flow control settings to use, then configures flow
4146 * control. Calls the appropriate media-specific link configuration
4147 * function. Assuming the adapter has a valid link partner, a valid link
4148 * should be established. Assumes the hardware has previously been reset
4149 * and the transmitter and receiver are not enabled.
4150 **/
4151 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4152 {
4153 s32 ret_val;
4154
4155 if (hw->phy.ops.check_reset_block(hw))
4156 return 0;
4157
4158 /* ICH parts do not have a word in the NVM to determine
4159 * the default flow control setting, so we explicitly
4160 * set it to full.
4161 */
4162 if (hw->fc.requested_mode == e1000_fc_default) {
4163 /* Workaround h/w hang when Tx flow control enabled */
4164 if (hw->mac.type == e1000_pchlan)
4165 hw->fc.requested_mode = e1000_fc_rx_pause;
4166 else
4167 hw->fc.requested_mode = e1000_fc_full;
4168 }
4169
4170 /* Save off the requested flow control mode for use later. Depending
4171 * on the link partner's capabilities, we may or may not use this mode.
4172 */
4173 hw->fc.current_mode = hw->fc.requested_mode;
4174
4175 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
4176
4177 /* Continue to configure the copper link. */
4178 ret_val = hw->mac.ops.setup_physical_interface(hw);
4179 if (ret_val)
4180 return ret_val;
4181
4182 ew32(FCTTV, hw->fc.pause_time);
4183 if ((hw->phy.type == e1000_phy_82578) ||
4184 (hw->phy.type == e1000_phy_82579) ||
4185 (hw->phy.type == e1000_phy_i217) ||
4186 (hw->phy.type == e1000_phy_82577)) {
4187 ew32(FCRTV_PCH, hw->fc.refresh_time);
4188
4189 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
4190 hw->fc.pause_time);
4191 if (ret_val)
4192 return ret_val;
4193 }
4194
4195 return e1000e_set_fc_watermarks(hw);
4196 }
4197
4198 /**
4199 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4200 * @hw: pointer to the HW structure
4201 *
4202 * Configures the kumeran interface to the PHY to wait the appropriate time
4203 * when polling the PHY, then call the generic setup_copper_link to finish
4204 * configuring the copper link.
4205 **/
4206 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4207 {
4208 u32 ctrl;
4209 s32 ret_val;
4210 u16 reg_data;
4211
4212 ctrl = er32(CTRL);
4213 ctrl |= E1000_CTRL_SLU;
4214 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4215 ew32(CTRL, ctrl);
4216
4217 /* Set the mac to wait the maximum time between each iteration
4218 * and increase the max iterations when polling the phy;
4219 * this fixes erroneous timeouts at 10Mbps.
4220 */
4221 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
4222 if (ret_val)
4223 return ret_val;
4224 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4225 &reg_data);
4226 if (ret_val)
4227 return ret_val;
4228 reg_data |= 0x3F;
4229 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4230 reg_data);
4231 if (ret_val)
4232 return ret_val;
4233
4234 switch (hw->phy.type) {
4235 case e1000_phy_igp_3:
4236 ret_val = e1000e_copper_link_setup_igp(hw);
4237 if (ret_val)
4238 return ret_val;
4239 break;
4240 case e1000_phy_bm:
4241 case e1000_phy_82578:
4242 ret_val = e1000e_copper_link_setup_m88(hw);
4243 if (ret_val)
4244 return ret_val;
4245 break;
4246 case e1000_phy_82577:
4247 case e1000_phy_82579:
4248 ret_val = e1000_copper_link_setup_82577(hw);
4249 if (ret_val)
4250 return ret_val;
4251 break;
4252 case e1000_phy_ife:
4253 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
4254 if (ret_val)
4255 return ret_val;
4256
4257 reg_data &= ~IFE_PMC_AUTO_MDIX;
4258
4259 switch (hw->phy.mdix) {
4260 case 1:
4261 reg_data &= ~IFE_PMC_FORCE_MDIX;
4262 break;
4263 case 2:
4264 reg_data |= IFE_PMC_FORCE_MDIX;
4265 break;
4266 case 0:
4267 default:
4268 reg_data |= IFE_PMC_AUTO_MDIX;
4269 break;
4270 }
4271 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
4272 if (ret_val)
4273 return ret_val;
4274 break;
4275 default:
4276 break;
4277 }
4278
4279 return e1000e_setup_copper_link(hw);
4280 }
4281
4282 /**
4283 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4284 * @hw: pointer to the HW structure
4285 *
4286 * Calls the PHY specific link setup function and then calls the
4287 * generic setup_copper_link to finish configuring the link for
4288 * Lynxpoint PCH devices
4289 **/
4290 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4291 {
4292 u32 ctrl;
4293 s32 ret_val;
4294
4295 ctrl = er32(CTRL);
4296 ctrl |= E1000_CTRL_SLU;
4297 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4298 ew32(CTRL, ctrl);
4299
4300 ret_val = e1000_copper_link_setup_82577(hw);
4301 if (ret_val)
4302 return ret_val;
4303
4304 return e1000e_setup_copper_link(hw);
4305 }
4306
4307 /**
4308 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4309 * @hw: pointer to the HW structure
4310 * @speed: pointer to store current link speed
4311 * @duplex: pointer to store the current link duplex
4312 *
4313 * Calls the generic get_speed_and_duplex to retrieve the current link
4314 * information and then calls the Kumeran lock loss workaround for links at
4315 * gigabit speeds.
4316 **/
4317 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4318 u16 *duplex)
4319 {
4320 s32 ret_val;
4321
4322 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
4323 if (ret_val)
4324 return ret_val;
4325
4326 if ((hw->mac.type == e1000_ich8lan) &&
4327 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
4328 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4329 }
4330
4331 return ret_val;
4332 }
4333
4334 /**
4335 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4336 * @hw: pointer to the HW structure
4337 *
4338 * Work-around for 82566 Kumeran PCS lock loss:
4339 * On link status change (i.e. PCI reset, speed change) and link is up and
4340 * speed is gigabit-
4341 * 0) if workaround is optionally disabled do nothing
4342 * 1) wait 1ms for Kumeran link to come up
4343 * 2) check Kumeran Diagnostic register PCS lock loss bit
4344 * 3) if not set the link is locked (all is good), otherwise...
4345 * 4) reset the PHY
4346 * 5) repeat up to 10 times
4347 * Note: this is only called for IGP3 copper when speed is 1gb.
4348 **/
4349 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4350 {
4351 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4352 u32 phy_ctrl;
4353 s32 ret_val;
4354 u16 i, data;
4355 bool link;
4356
4357 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4358 return 0;
4359
4360 /* Make sure link is up before proceeding. If not just return.
4361 * Attempting this while link is negotiating fouled up link
4362 * stability
4363 */
4364 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
4365 if (!link)
4366 return 0;
4367
4368 for (i = 0; i < 10; i++) {
4369 /* read once to clear */
4370 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4371 if (ret_val)
4372 return ret_val;
4373 /* and again to get new status */
4374 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4375 if (ret_val)
4376 return ret_val;
4377
4378 /* check for PCS lock */
4379 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4380 return 0;
4381
4382 /* Issue PHY reset */
4383 e1000_phy_hw_reset(hw);
4384 mdelay(5);
4385 }
4386 /* Disable GigE link negotiation */
4387 phy_ctrl = er32(PHY_CTRL);
4388 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4389 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4390 ew32(PHY_CTRL, phy_ctrl);
4391
4392 /* Call gig speed drop workaround on Gig disable before accessing
4393 * any PHY registers
4394 */
4395 e1000e_gig_downshift_workaround_ich8lan(hw);
4396
4397 /* unable to acquire PCS lock */
4398 return -E1000_ERR_PHY;
4399 }
4400
4401 /**
4402 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4403 * @hw: pointer to the HW structure
4404 * @state: boolean value used to set the current Kumeran workaround state
4405 *
4406 * If ICH8, set the current Kumeran workaround state (enabled - true
4407 * /disabled - false).
4408 **/
4409 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4410 bool state)
4411 {
4412 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4413
4414 if (hw->mac.type != e1000_ich8lan) {
4415 e_dbg("Workaround applies to ICH8 only.\n");
4416 return;
4417 }
4418
4419 dev_spec->kmrn_lock_loss_workaround_enabled = state;
4420 }
4421
4422 /**
4423 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4424 * @hw: pointer to the HW structure
4425 *
4426 * Workaround for 82566 power-down on D3 entry:
4427 * 1) disable gigabit link
4428 * 2) write VR power-down enable
4429 * 3) read it back
4430 * Continue if successful, else issue LCD reset and repeat
4431 **/
4432 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4433 {
4434 u32 reg;
4435 u16 data;
4436 u8 retry = 0;
4437
4438 if (hw->phy.type != e1000_phy_igp_3)
4439 return;
4440
4441 /* Try the workaround twice (if needed) */
4442 do {
4443 /* Disable link */
4444 reg = er32(PHY_CTRL);
4445 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4446 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4447 ew32(PHY_CTRL, reg);
4448
4449 /* Call gig speed drop workaround on Gig disable before
4450 * accessing any PHY registers
4451 */
4452 if (hw->mac.type == e1000_ich8lan)
4453 e1000e_gig_downshift_workaround_ich8lan(hw);
4454
4455 /* Write VR power-down enable */
4456 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4457 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4458 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4459
4460 /* Read it back and test */
4461 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4462 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4463 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4464 break;
4465
4466 /* Issue PHY reset and repeat at most one more time */
4467 reg = er32(CTRL);
4468 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
4469 retry++;
4470 } while (retry);
4471 }
4472
4473 /**
4474 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4475 * @hw: pointer to the HW structure
4476 *
4477 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4478 * LPLU, Gig disable, MDIC PHY reset):
4479 * 1) Set Kumeran Near-end loopback
4480 * 2) Clear Kumeran Near-end loopback
4481 * Should only be called for ICH8[m] devices with any 1G Phy.
4482 **/
4483 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4484 {
4485 s32 ret_val;
4486 u16 reg_data;
4487
4488 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
4489 return;
4490
4491 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4492 &reg_data);
4493 if (ret_val)
4494 return;
4495 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4496 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4497 reg_data);
4498 if (ret_val)
4499 return;
4500 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4501 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
4502 }
4503
4504 /**
4505 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4506 * @hw: pointer to the HW structure
4507 *
4508 * During S0 to Sx transition, it is possible the link remains at gig
4509 * instead of negotiating to a lower speed. Before going to Sx, set
4510 * 'Gig Disable' to force link speed negotiation to a lower speed based on
4511 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
4512 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4513 * needs to be written.
4514 * Parts that support (and are linked to a partner which support) EEE in
4515 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4516 * than 10Mbps w/o EEE.
4517 **/
4518 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4519 {
4520 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4521 u32 phy_ctrl;
4522 s32 ret_val;
4523
4524 phy_ctrl = er32(PHY_CTRL);
4525 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4526
4527 if (hw->phy.type == e1000_phy_i217) {
4528 u16 phy_reg, device_id = hw->adapter->pdev->device;
4529
4530 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4531 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4532 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4533 (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4534 u32 fextnvm6 = er32(FEXTNVM6);
4535
4536 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4537 }
4538
4539 ret_val = hw->phy.ops.acquire(hw);
4540 if (ret_val)
4541 goto out;
4542
4543 if (!dev_spec->eee_disable) {
4544 u16 eee_advert;
4545
4546 ret_val =
4547 e1000_read_emi_reg_locked(hw,
4548 I217_EEE_ADVERTISEMENT,
4549 &eee_advert);
4550 if (ret_val)
4551 goto release;
4552
4553 /* Disable LPLU if both link partners support 100BaseT
4554 * EEE and 100Full is advertised on both ends of the
4555 * link.
4556 */
4557 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4558 (dev_spec->eee_lp_ability &
4559 I82579_EEE_100_SUPPORTED) &&
4560 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
4561 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4562 E1000_PHY_CTRL_NOND0A_LPLU);
4563 }
4564
4565 /* For i217 Intel Rapid Start Technology support,
4566 * when the system is going into Sx and no manageability engine
4567 * is present, the driver must configure proxy to reset only on
4568 * power good. LPI (Low Power Idle) state must also reset only
4569 * on power good, as well as the MTA (Multicast table array).
4570 * The SMBus release must also be disabled on LCD reset.
4571 */
4572 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4573 /* Enable proxy to reset only on power good. */
4574 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
4575 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4576 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
4577
4578 /* Set bit enable LPI (EEE) to reset only on
4579 * power good.
4580 */
4581 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
4582 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4583 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
4584
4585 /* Disable the SMB release on LCD reset. */
4586 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4587 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4588 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4589 }
4590
4591 /* Enable MTA to reset for Intel Rapid Start Technology
4592 * Support
4593 */
4594 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4595 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4596 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4597
4598 release:
4599 hw->phy.ops.release(hw);
4600 }
4601 out:
4602 ew32(PHY_CTRL, phy_ctrl);
4603
4604 if (hw->mac.type == e1000_ich8lan)
4605 e1000e_gig_downshift_workaround_ich8lan(hw);
4606
4607 if (hw->mac.type >= e1000_pchlan) {
4608 e1000_oem_bits_config_ich8lan(hw, false);
4609
4610 /* Reset PHY to activate OEM bits on 82577/8 */
4611 if (hw->mac.type == e1000_pchlan)
4612 e1000e_phy_hw_reset_generic(hw);
4613
4614 ret_val = hw->phy.ops.acquire(hw);
4615 if (ret_val)
4616 return;
4617 e1000_write_smbus_addr(hw);
4618 hw->phy.ops.release(hw);
4619 }
4620 }
4621
4622 /**
4623 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4624 * @hw: pointer to the HW structure
4625 *
4626 * During Sx to S0 transitions on non-managed devices or managed devices
4627 * on which PHY resets are not blocked, if the PHY registers cannot be
4628 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4629 * the PHY.
4630 * On i217, setup Intel Rapid Start Technology.
4631 **/
4632 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4633 {
4634 s32 ret_val;
4635
4636 if (hw->mac.type < e1000_pch2lan)
4637 return;
4638
4639 ret_val = e1000_init_phy_workarounds_pchlan(hw);
4640 if (ret_val) {
4641 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
4642 return;
4643 }
4644
4645 /* For i217 Intel Rapid Start Technology support when the system
4646 * is transitioning from Sx and no manageability engine is present
4647 * configure SMBus to restore on reset, disable proxy, and enable
4648 * the reset on MTA (Multicast table array).
4649 */
4650 if (hw->phy.type == e1000_phy_i217) {
4651 u16 phy_reg;
4652
4653 ret_val = hw->phy.ops.acquire(hw);
4654 if (ret_val) {
4655 e_dbg("Failed to setup iRST\n");
4656 return;
4657 }
4658
4659 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4660 /* Restore clear on SMB if no manageability engine
4661 * is present
4662 */
4663 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4664 if (ret_val)
4665 goto release;
4666 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4667 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4668
4669 /* Disable Proxy */
4670 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
4671 }
4672 /* Enable reset on MTA */
4673 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4674 if (ret_val)
4675 goto release;
4676 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4677 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4678 release:
4679 if (ret_val)
4680 e_dbg("Error %d in resume workarounds\n", ret_val);
4681 hw->phy.ops.release(hw);
4682 }
4683 }
4684
4685 /**
4686 * e1000_cleanup_led_ich8lan - Restore the default LED operation
4687 * @hw: pointer to the HW structure
4688 *
4689 * Return the LED back to the default configuration.
4690 **/
4691 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4692 {
4693 if (hw->phy.type == e1000_phy_ife)
4694 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
4695
4696 ew32(LEDCTL, hw->mac.ledctl_default);
4697 return 0;
4698 }
4699
4700 /**
4701 * e1000_led_on_ich8lan - Turn LEDs on
4702 * @hw: pointer to the HW structure
4703 *
4704 * Turn on the LEDs.
4705 **/
4706 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4707 {
4708 if (hw->phy.type == e1000_phy_ife)
4709 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4710 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4711
4712 ew32(LEDCTL, hw->mac.ledctl_mode2);
4713 return 0;
4714 }
4715
4716 /**
4717 * e1000_led_off_ich8lan - Turn LEDs off
4718 * @hw: pointer to the HW structure
4719 *
4720 * Turn off the LEDs.
4721 **/
4722 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4723 {
4724 if (hw->phy.type == e1000_phy_ife)
4725 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4726 (IFE_PSCL_PROBE_MODE |
4727 IFE_PSCL_PROBE_LEDS_OFF));
4728
4729 ew32(LEDCTL, hw->mac.ledctl_mode1);
4730 return 0;
4731 }
4732
4733 /**
4734 * e1000_setup_led_pchlan - Configures SW controllable LED
4735 * @hw: pointer to the HW structure
4736 *
4737 * This prepares the SW controllable LED for use.
4738 **/
4739 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4740 {
4741 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
4742 }
4743
4744 /**
4745 * e1000_cleanup_led_pchlan - Restore the default LED operation
4746 * @hw: pointer to the HW structure
4747 *
4748 * Return the LED back to the default configuration.
4749 **/
4750 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4751 {
4752 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
4753 }
4754
4755 /**
4756 * e1000_led_on_pchlan - Turn LEDs on
4757 * @hw: pointer to the HW structure
4758 *
4759 * Turn on the LEDs.
4760 **/
4761 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4762 {
4763 u16 data = (u16)hw->mac.ledctl_mode2;
4764 u32 i, led;
4765
4766 /* If no link, then turn LED on by setting the invert bit
4767 * for each LED that's mode is "link_up" in ledctl_mode2.
4768 */
4769 if (!(er32(STATUS) & E1000_STATUS_LU)) {
4770 for (i = 0; i < 3; i++) {
4771 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4772 if ((led & E1000_PHY_LED0_MODE_MASK) !=
4773 E1000_LEDCTL_MODE_LINK_UP)
4774 continue;
4775 if (led & E1000_PHY_LED0_IVRT)
4776 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4777 else
4778 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4779 }
4780 }
4781
4782 return e1e_wphy(hw, HV_LED_CONFIG, data);
4783 }
4784
4785 /**
4786 * e1000_led_off_pchlan - Turn LEDs off
4787 * @hw: pointer to the HW structure
4788 *
4789 * Turn off the LEDs.
4790 **/
4791 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4792 {
4793 u16 data = (u16)hw->mac.ledctl_mode1;
4794 u32 i, led;
4795
4796 /* If no link, then turn LED off by clearing the invert bit
4797 * for each LED that's mode is "link_up" in ledctl_mode1.
4798 */
4799 if (!(er32(STATUS) & E1000_STATUS_LU)) {
4800 for (i = 0; i < 3; i++) {
4801 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4802 if ((led & E1000_PHY_LED0_MODE_MASK) !=
4803 E1000_LEDCTL_MODE_LINK_UP)
4804 continue;
4805 if (led & E1000_PHY_LED0_IVRT)
4806 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4807 else
4808 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4809 }
4810 }
4811
4812 return e1e_wphy(hw, HV_LED_CONFIG, data);
4813 }
4814
4815 /**
4816 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
4817 * @hw: pointer to the HW structure
4818 *
4819 * Read appropriate register for the config done bit for completion status
4820 * and configure the PHY through s/w for EEPROM-less parts.
4821 *
4822 * NOTE: some silicon which is EEPROM-less will fail trying to read the
4823 * config done bit, so only an error is logged and continues. If we were
4824 * to return with error, EEPROM-less silicon would not be able to be reset
4825 * or change link.
4826 **/
4827 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4828 {
4829 s32 ret_val = 0;
4830 u32 bank = 0;
4831 u32 status;
4832
4833 e1000e_get_cfg_done_generic(hw);
4834
4835 /* Wait for indication from h/w that it has completed basic config */
4836 if (hw->mac.type >= e1000_ich10lan) {
4837 e1000_lan_init_done_ich8lan(hw);
4838 } else {
4839 ret_val = e1000e_get_auto_rd_done(hw);
4840 if (ret_val) {
4841 /* When auto config read does not complete, do not
4842 * return with an error. This can happen in situations
4843 * where there is no eeprom and prevents getting link.
4844 */
4845 e_dbg("Auto Read Done did not complete\n");
4846 ret_val = 0;
4847 }
4848 }
4849
4850 /* Clear PHY Reset Asserted bit */
4851 status = er32(STATUS);
4852 if (status & E1000_STATUS_PHYRA)
4853 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
4854 else
4855 e_dbg("PHY Reset Asserted not set - needs delay\n");
4856
4857 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
4858 if (hw->mac.type <= e1000_ich9lan) {
4859 if (!(er32(EECD) & E1000_EECD_PRES) &&
4860 (hw->phy.type == e1000_phy_igp_3)) {
4861 e1000e_phy_init_script_igp3(hw);
4862 }
4863 } else {
4864 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4865 /* Maybe we should do a basic PHY config */
4866 e_dbg("EEPROM not present\n");
4867 ret_val = -E1000_ERR_CONFIG;
4868 }
4869 }
4870
4871 return ret_val;
4872 }
4873
4874 /**
4875 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4876 * @hw: pointer to the HW structure
4877 *
4878 * In the case of a PHY power down to save power, or to turn off link during a
4879 * driver unload, or wake on lan is not enabled, remove the link.
4880 **/
4881 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4882 {
4883 /* If the management interface is not enabled, then power down */
4884 if (!(hw->mac.ops.check_mng_mode(hw) ||
4885 hw->phy.ops.check_reset_block(hw)))
4886 e1000_power_down_phy_copper(hw);
4887 }
4888
4889 /**
4890 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4891 * @hw: pointer to the HW structure
4892 *
4893 * Clears hardware counters specific to the silicon family and calls
4894 * clear_hw_cntrs_generic to clear all general purpose counters.
4895 **/
4896 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4897 {
4898 u16 phy_data;
4899 s32 ret_val;
4900
4901 e1000e_clear_hw_cntrs_base(hw);
4902
4903 er32(ALGNERRC);
4904 er32(RXERRC);
4905 er32(TNCRS);
4906 er32(CEXTERR);
4907 er32(TSCTC);
4908 er32(TSCTFC);
4909
4910 er32(MGTPRC);
4911 er32(MGTPDC);
4912 er32(MGTPTC);
4913
4914 er32(IAC);
4915 er32(ICRXOC);
4916
4917 /* Clear PHY statistics registers */
4918 if ((hw->phy.type == e1000_phy_82578) ||
4919 (hw->phy.type == e1000_phy_82579) ||
4920 (hw->phy.type == e1000_phy_i217) ||
4921 (hw->phy.type == e1000_phy_82577)) {
4922 ret_val = hw->phy.ops.acquire(hw);
4923 if (ret_val)
4924 return;
4925 ret_val = hw->phy.ops.set_page(hw,
4926 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4927 if (ret_val)
4928 goto release;
4929 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4930 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4931 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4932 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4933 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4934 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4935 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4936 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4937 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4938 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4939 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4940 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4941 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4942 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4943 release:
4944 hw->phy.ops.release(hw);
4945 }
4946 }
4947
4948 static const struct e1000_mac_operations ich8_mac_ops = {
4949 /* check_mng_mode dependent on mac type */
4950 .check_for_link = e1000_check_for_copper_link_ich8lan,
4951 /* cleanup_led dependent on mac type */
4952 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
4953 .get_bus_info = e1000_get_bus_info_ich8lan,
4954 .set_lan_id = e1000_set_lan_id_single_port,
4955 .get_link_up_info = e1000_get_link_up_info_ich8lan,
4956 /* led_on dependent on mac type */
4957 /* led_off dependent on mac type */
4958 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
4959 .reset_hw = e1000_reset_hw_ich8lan,
4960 .init_hw = e1000_init_hw_ich8lan,
4961 .setup_link = e1000_setup_link_ich8lan,
4962 .setup_physical_interface = e1000_setup_copper_link_ich8lan,
4963 /* id_led_init dependent on mac type */
4964 .config_collision_dist = e1000e_config_collision_dist_generic,
4965 .rar_set = e1000e_rar_set_generic,
4966 };
4967
4968 static const struct e1000_phy_operations ich8_phy_ops = {
4969 .acquire = e1000_acquire_swflag_ich8lan,
4970 .check_reset_block = e1000_check_reset_block_ich8lan,
4971 .commit = NULL,
4972 .get_cfg_done = e1000_get_cfg_done_ich8lan,
4973 .get_cable_length = e1000e_get_cable_length_igp_2,
4974 .read_reg = e1000e_read_phy_reg_igp,
4975 .release = e1000_release_swflag_ich8lan,
4976 .reset = e1000_phy_hw_reset_ich8lan,
4977 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
4978 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
4979 .write_reg = e1000e_write_phy_reg_igp,
4980 };
4981
4982 static const struct e1000_nvm_operations ich8_nvm_ops = {
4983 .acquire = e1000_acquire_nvm_ich8lan,
4984 .read = e1000_read_nvm_ich8lan,
4985 .release = e1000_release_nvm_ich8lan,
4986 .reload = e1000e_reload_nvm_generic,
4987 .update = e1000_update_nvm_checksum_ich8lan,
4988 .valid_led_default = e1000_valid_led_default_ich8lan,
4989 .validate = e1000_validate_nvm_checksum_ich8lan,
4990 .write = e1000_write_nvm_ich8lan,
4991 };
4992
4993 const struct e1000_info e1000_ich8_info = {
4994 .mac = e1000_ich8lan,
4995 .flags = FLAG_HAS_WOL
4996 | FLAG_IS_ICH
4997 | FLAG_HAS_CTRLEXT_ON_LOAD
4998 | FLAG_HAS_AMT
4999 | FLAG_HAS_FLASH
5000 | FLAG_APME_IN_WUC,
5001 .pba = 8,
5002 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
5003 .get_variants = e1000_get_variants_ich8lan,
5004 .mac_ops = &ich8_mac_ops,
5005 .phy_ops = &ich8_phy_ops,
5006 .nvm_ops = &ich8_nvm_ops,
5007 };
5008
5009 const struct e1000_info e1000_ich9_info = {
5010 .mac = e1000_ich9lan,
5011 .flags = FLAG_HAS_JUMBO_FRAMES
5012 | FLAG_IS_ICH
5013 | FLAG_HAS_WOL
5014 | FLAG_HAS_CTRLEXT_ON_LOAD
5015 | FLAG_HAS_AMT
5016 | FLAG_HAS_FLASH
5017 | FLAG_APME_IN_WUC,
5018 .pba = 18,
5019 .max_hw_frame_size = DEFAULT_JUMBO,
5020 .get_variants = e1000_get_variants_ich8lan,
5021 .mac_ops = &ich8_mac_ops,
5022 .phy_ops = &ich8_phy_ops,
5023 .nvm_ops = &ich8_nvm_ops,
5024 };
5025
5026 const struct e1000_info e1000_ich10_info = {
5027 .mac = e1000_ich10lan,
5028 .flags = FLAG_HAS_JUMBO_FRAMES
5029 | FLAG_IS_ICH
5030 | FLAG_HAS_WOL
5031 | FLAG_HAS_CTRLEXT_ON_LOAD
5032 | FLAG_HAS_AMT
5033 | FLAG_HAS_FLASH
5034 | FLAG_APME_IN_WUC,
5035 .pba = 18,
5036 .max_hw_frame_size = DEFAULT_JUMBO,
5037 .get_variants = e1000_get_variants_ich8lan,
5038 .mac_ops = &ich8_mac_ops,
5039 .phy_ops = &ich8_phy_ops,
5040 .nvm_ops = &ich8_nvm_ops,
5041 };
5042
5043 const struct e1000_info e1000_pch_info = {
5044 .mac = e1000_pchlan,
5045 .flags = FLAG_IS_ICH
5046 | FLAG_HAS_WOL
5047 | FLAG_HAS_CTRLEXT_ON_LOAD
5048 | FLAG_HAS_AMT
5049 | FLAG_HAS_FLASH
5050 | FLAG_HAS_JUMBO_FRAMES
5051 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5052 | FLAG_APME_IN_WUC,
5053 .flags2 = FLAG2_HAS_PHY_STATS,
5054 .pba = 26,
5055 .max_hw_frame_size = 4096,
5056 .get_variants = e1000_get_variants_ich8lan,
5057 .mac_ops = &ich8_mac_ops,
5058 .phy_ops = &ich8_phy_ops,
5059 .nvm_ops = &ich8_nvm_ops,
5060 };
5061
5062 const struct e1000_info e1000_pch2_info = {
5063 .mac = e1000_pch2lan,
5064 .flags = FLAG_IS_ICH
5065 | FLAG_HAS_WOL
5066 | FLAG_HAS_HW_TIMESTAMP
5067 | FLAG_HAS_CTRLEXT_ON_LOAD
5068 | FLAG_HAS_AMT
5069 | FLAG_HAS_FLASH
5070 | FLAG_HAS_JUMBO_FRAMES
5071 | FLAG_APME_IN_WUC,
5072 .flags2 = FLAG2_HAS_PHY_STATS
5073 | FLAG2_HAS_EEE,
5074 .pba = 26,
5075 .max_hw_frame_size = 9018,
5076 .get_variants = e1000_get_variants_ich8lan,
5077 .mac_ops = &ich8_mac_ops,
5078 .phy_ops = &ich8_phy_ops,
5079 .nvm_ops = &ich8_nvm_ops,
5080 };
5081
5082 const struct e1000_info e1000_pch_lpt_info = {
5083 .mac = e1000_pch_lpt,
5084 .flags = FLAG_IS_ICH
5085 | FLAG_HAS_WOL
5086 | FLAG_HAS_HW_TIMESTAMP
5087 | FLAG_HAS_CTRLEXT_ON_LOAD
5088 | FLAG_HAS_AMT
5089 | FLAG_HAS_FLASH
5090 | FLAG_HAS_JUMBO_FRAMES
5091 | FLAG_APME_IN_WUC,
5092 .flags2 = FLAG2_HAS_PHY_STATS
5093 | FLAG2_HAS_EEE,
5094 .pba = 26,
5095 .max_hw_frame_size = 9018,
5096 .get_variants = e1000_get_variants_ich8lan,
5097 .mac_ops = &ich8_mac_ops,
5098 .phy_ops = &ich8_phy_ops,
5099 .nvm_ops = &ich8_nvm_ops,
5100 };
Linux kernel - Deliverables
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