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[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/vmalloc.h>
36 #include <linux/pagemap.h>
37 #include <linux/delay.h>
38 #include <linux/netdevice.h>
39 #include <linux/interrupt.h>
40 #include <linux/tcp.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/ethtool.h>
46 #include <linux/if_vlan.h>
47 #include <linux/cpu.h>
48 #include <linux/smp.h>
49 #include <linux/pm_qos.h>
50 #include <linux/pm_runtime.h>
51 #include <linux/aer.h>
52 #include <linux/prefetch.h>
53
54 #include "e1000.h"
55
56 #define DRV_EXTRAVERSION "-k"
57
58 #define DRV_VERSION "2.2.14" DRV_EXTRAVERSION
59 char e1000e_driver_name[] = "e1000e";
60 const char e1000e_driver_version[] = DRV_VERSION;
61
62 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
63 static int debug = -1;
64 module_param(debug, int, 0);
65 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
66
67 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
68
69 static const struct e1000_info *e1000_info_tbl[] = {
70 [board_82571] = &e1000_82571_info,
71 [board_82572] = &e1000_82572_info,
72 [board_82573] = &e1000_82573_info,
73 [board_82574] = &e1000_82574_info,
74 [board_82583] = &e1000_82583_info,
75 [board_80003es2lan] = &e1000_es2_info,
76 [board_ich8lan] = &e1000_ich8_info,
77 [board_ich9lan] = &e1000_ich9_info,
78 [board_ich10lan] = &e1000_ich10_info,
79 [board_pchlan] = &e1000_pch_info,
80 [board_pch2lan] = &e1000_pch2_info,
81 [board_pch_lpt] = &e1000_pch_lpt_info,
82 };
83
84 struct e1000_reg_info {
85 u32 ofs;
86 char *name;
87 };
88
89 static const struct e1000_reg_info e1000_reg_info_tbl[] = {
90
91 /* General Registers */
92 {E1000_CTRL, "CTRL"},
93 {E1000_STATUS, "STATUS"},
94 {E1000_CTRL_EXT, "CTRL_EXT"},
95
96 /* Interrupt Registers */
97 {E1000_ICR, "ICR"},
98
99 /* Rx Registers */
100 {E1000_RCTL, "RCTL"},
101 {E1000_RDLEN(0), "RDLEN"},
102 {E1000_RDH(0), "RDH"},
103 {E1000_RDT(0), "RDT"},
104 {E1000_RDTR, "RDTR"},
105 {E1000_RXDCTL(0), "RXDCTL"},
106 {E1000_ERT, "ERT"},
107 {E1000_RDBAL(0), "RDBAL"},
108 {E1000_RDBAH(0), "RDBAH"},
109 {E1000_RDFH, "RDFH"},
110 {E1000_RDFT, "RDFT"},
111 {E1000_RDFHS, "RDFHS"},
112 {E1000_RDFTS, "RDFTS"},
113 {E1000_RDFPC, "RDFPC"},
114
115 /* Tx Registers */
116 {E1000_TCTL, "TCTL"},
117 {E1000_TDBAL(0), "TDBAL"},
118 {E1000_TDBAH(0), "TDBAH"},
119 {E1000_TDLEN(0), "TDLEN"},
120 {E1000_TDH(0), "TDH"},
121 {E1000_TDT(0), "TDT"},
122 {E1000_TIDV, "TIDV"},
123 {E1000_TXDCTL(0), "TXDCTL"},
124 {E1000_TADV, "TADV"},
125 {E1000_TARC(0), "TARC"},
126 {E1000_TDFH, "TDFH"},
127 {E1000_TDFT, "TDFT"},
128 {E1000_TDFHS, "TDFHS"},
129 {E1000_TDFTS, "TDFTS"},
130 {E1000_TDFPC, "TDFPC"},
131
132 /* List Terminator */
133 {0, NULL}
134 };
135
136 /**
137 * e1000_regdump - register printout routine
138 * @hw: pointer to the HW structure
139 * @reginfo: pointer to the register info table
140 **/
141 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
142 {
143 int n = 0;
144 char rname[16];
145 u32 regs[8];
146
147 switch (reginfo->ofs) {
148 case E1000_RXDCTL(0):
149 for (n = 0; n < 2; n++)
150 regs[n] = __er32(hw, E1000_RXDCTL(n));
151 break;
152 case E1000_TXDCTL(0):
153 for (n = 0; n < 2; n++)
154 regs[n] = __er32(hw, E1000_TXDCTL(n));
155 break;
156 case E1000_TARC(0):
157 for (n = 0; n < 2; n++)
158 regs[n] = __er32(hw, E1000_TARC(n));
159 break;
160 default:
161 pr_info("%-15s %08x\n",
162 reginfo->name, __er32(hw, reginfo->ofs));
163 return;
164 }
165
166 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
167 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
168 }
169
170 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
171 struct e1000_buffer *bi)
172 {
173 int i;
174 struct e1000_ps_page *ps_page;
175
176 for (i = 0; i < adapter->rx_ps_pages; i++) {
177 ps_page = &bi->ps_pages[i];
178
179 if (ps_page->page) {
180 pr_info("packet dump for ps_page %d:\n", i);
181 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
182 16, 1, page_address(ps_page->page),
183 PAGE_SIZE, true);
184 }
185 }
186 }
187
188 /**
189 * e1000e_dump - Print registers, Tx-ring and Rx-ring
190 * @adapter: board private structure
191 **/
192 static void e1000e_dump(struct e1000_adapter *adapter)
193 {
194 struct net_device *netdev = adapter->netdev;
195 struct e1000_hw *hw = &adapter->hw;
196 struct e1000_reg_info *reginfo;
197 struct e1000_ring *tx_ring = adapter->tx_ring;
198 struct e1000_tx_desc *tx_desc;
199 struct my_u0 {
200 __le64 a;
201 __le64 b;
202 } *u0;
203 struct e1000_buffer *buffer_info;
204 struct e1000_ring *rx_ring = adapter->rx_ring;
205 union e1000_rx_desc_packet_split *rx_desc_ps;
206 union e1000_rx_desc_extended *rx_desc;
207 struct my_u1 {
208 __le64 a;
209 __le64 b;
210 __le64 c;
211 __le64 d;
212 } *u1;
213 u32 staterr;
214 int i = 0;
215
216 if (!netif_msg_hw(adapter))
217 return;
218
219 /* Print netdevice Info */
220 if (netdev) {
221 dev_info(&adapter->pdev->dev, "Net device Info\n");
222 pr_info("Device Name state trans_start last_rx\n");
223 pr_info("%-15s %016lX %016lX %016lX\n",
224 netdev->name, netdev->state, netdev->trans_start,
225 netdev->last_rx);
226 }
227
228 /* Print Registers */
229 dev_info(&adapter->pdev->dev, "Register Dump\n");
230 pr_info(" Register Name Value\n");
231 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
232 reginfo->name; reginfo++) {
233 e1000_regdump(hw, reginfo);
234 }
235
236 /* Print Tx Ring Summary */
237 if (!netdev || !netif_running(netdev))
238 return;
239
240 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
241 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
242 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
243 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
244 0, tx_ring->next_to_use, tx_ring->next_to_clean,
245 (unsigned long long)buffer_info->dma,
246 buffer_info->length,
247 buffer_info->next_to_watch,
248 (unsigned long long)buffer_info->time_stamp);
249
250 /* Print Tx Ring */
251 if (!netif_msg_tx_done(adapter))
252 goto rx_ring_summary;
253
254 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
255
256 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
257 *
258 * Legacy Transmit Descriptor
259 * +--------------------------------------------------------------+
260 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
261 * +--------------------------------------------------------------+
262 * 8 | Special | CSS | Status | CMD | CSO | Length |
263 * +--------------------------------------------------------------+
264 * 63 48 47 36 35 32 31 24 23 16 15 0
265 *
266 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
267 * 63 48 47 40 39 32 31 16 15 8 7 0
268 * +----------------------------------------------------------------+
269 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
270 * +----------------------------------------------------------------+
271 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
272 * +----------------------------------------------------------------+
273 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
274 *
275 * Extended Data Descriptor (DTYP=0x1)
276 * +----------------------------------------------------------------+
277 * 0 | Buffer Address [63:0] |
278 * +----------------------------------------------------------------+
279 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
280 * +----------------------------------------------------------------+
281 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
282 */
283 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
284 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
285 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
286 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
287 const char *next_desc;
288 tx_desc = E1000_TX_DESC(*tx_ring, i);
289 buffer_info = &tx_ring->buffer_info[i];
290 u0 = (struct my_u0 *)tx_desc;
291 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
292 next_desc = " NTC/U";
293 else if (i == tx_ring->next_to_use)
294 next_desc = " NTU";
295 else if (i == tx_ring->next_to_clean)
296 next_desc = " NTC";
297 else
298 next_desc = "";
299 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
300 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
301 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
302 i,
303 (unsigned long long)le64_to_cpu(u0->a),
304 (unsigned long long)le64_to_cpu(u0->b),
305 (unsigned long long)buffer_info->dma,
306 buffer_info->length, buffer_info->next_to_watch,
307 (unsigned long long)buffer_info->time_stamp,
308 buffer_info->skb, next_desc);
309
310 if (netif_msg_pktdata(adapter) && buffer_info->skb)
311 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
312 16, 1, buffer_info->skb->data,
313 buffer_info->skb->len, true);
314 }
315
316 /* Print Rx Ring Summary */
317 rx_ring_summary:
318 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
319 pr_info("Queue [NTU] [NTC]\n");
320 pr_info(" %5d %5X %5X\n",
321 0, rx_ring->next_to_use, rx_ring->next_to_clean);
322
323 /* Print Rx Ring */
324 if (!netif_msg_rx_status(adapter))
325 return;
326
327 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
328 switch (adapter->rx_ps_pages) {
329 case 1:
330 case 2:
331 case 3:
332 /* [Extended] Packet Split Receive Descriptor Format
333 *
334 * +-----------------------------------------------------+
335 * 0 | Buffer Address 0 [63:0] |
336 * +-----------------------------------------------------+
337 * 8 | Buffer Address 1 [63:0] |
338 * +-----------------------------------------------------+
339 * 16 | Buffer Address 2 [63:0] |
340 * +-----------------------------------------------------+
341 * 24 | Buffer Address 3 [63:0] |
342 * +-----------------------------------------------------+
343 */
344 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
345 /* [Extended] Receive Descriptor (Write-Back) Format
346 *
347 * 63 48 47 32 31 13 12 8 7 4 3 0
348 * +------------------------------------------------------+
349 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
350 * | Checksum | Ident | | Queue | | Type |
351 * +------------------------------------------------------+
352 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
353 * +------------------------------------------------------+
354 * 63 48 47 32 31 20 19 0
355 */
356 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
357 for (i = 0; i < rx_ring->count; i++) {
358 const char *next_desc;
359 buffer_info = &rx_ring->buffer_info[i];
360 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
361 u1 = (struct my_u1 *)rx_desc_ps;
362 staterr =
363 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
364
365 if (i == rx_ring->next_to_use)
366 next_desc = " NTU";
367 else if (i == rx_ring->next_to_clean)
368 next_desc = " NTC";
369 else
370 next_desc = "";
371
372 if (staterr & E1000_RXD_STAT_DD) {
373 /* Descriptor Done */
374 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
375 "RWB", i,
376 (unsigned long long)le64_to_cpu(u1->a),
377 (unsigned long long)le64_to_cpu(u1->b),
378 (unsigned long long)le64_to_cpu(u1->c),
379 (unsigned long long)le64_to_cpu(u1->d),
380 buffer_info->skb, next_desc);
381 } else {
382 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
383 "R ", i,
384 (unsigned long long)le64_to_cpu(u1->a),
385 (unsigned long long)le64_to_cpu(u1->b),
386 (unsigned long long)le64_to_cpu(u1->c),
387 (unsigned long long)le64_to_cpu(u1->d),
388 (unsigned long long)buffer_info->dma,
389 buffer_info->skb, next_desc);
390
391 if (netif_msg_pktdata(adapter))
392 e1000e_dump_ps_pages(adapter,
393 buffer_info);
394 }
395 }
396 break;
397 default:
398 case 0:
399 /* Extended Receive Descriptor (Read) Format
400 *
401 * +-----------------------------------------------------+
402 * 0 | Buffer Address [63:0] |
403 * +-----------------------------------------------------+
404 * 8 | Reserved |
405 * +-----------------------------------------------------+
406 */
407 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
408 /* Extended Receive Descriptor (Write-Back) Format
409 *
410 * 63 48 47 32 31 24 23 4 3 0
411 * +------------------------------------------------------+
412 * | RSS Hash | | | |
413 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
414 * | Packet | IP | | | Type |
415 * | Checksum | Ident | | | |
416 * +------------------------------------------------------+
417 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
418 * +------------------------------------------------------+
419 * 63 48 47 32 31 20 19 0
420 */
421 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
422
423 for (i = 0; i < rx_ring->count; i++) {
424 const char *next_desc;
425
426 buffer_info = &rx_ring->buffer_info[i];
427 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
428 u1 = (struct my_u1 *)rx_desc;
429 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
430
431 if (i == rx_ring->next_to_use)
432 next_desc = " NTU";
433 else if (i == rx_ring->next_to_clean)
434 next_desc = " NTC";
435 else
436 next_desc = "";
437
438 if (staterr & E1000_RXD_STAT_DD) {
439 /* Descriptor Done */
440 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
441 "RWB", i,
442 (unsigned long long)le64_to_cpu(u1->a),
443 (unsigned long long)le64_to_cpu(u1->b),
444 buffer_info->skb, next_desc);
445 } else {
446 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
447 "R ", i,
448 (unsigned long long)le64_to_cpu(u1->a),
449 (unsigned long long)le64_to_cpu(u1->b),
450 (unsigned long long)buffer_info->dma,
451 buffer_info->skb, next_desc);
452
453 if (netif_msg_pktdata(adapter) &&
454 buffer_info->skb)
455 print_hex_dump(KERN_INFO, "",
456 DUMP_PREFIX_ADDRESS, 16,
457 1,
458 buffer_info->skb->data,
459 adapter->rx_buffer_len,
460 true);
461 }
462 }
463 }
464 }
465
466 /**
467 * e1000_desc_unused - calculate if we have unused descriptors
468 **/
469 static int e1000_desc_unused(struct e1000_ring *ring)
470 {
471 if (ring->next_to_clean > ring->next_to_use)
472 return ring->next_to_clean - ring->next_to_use - 1;
473
474 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
475 }
476
477 /**
478 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
479 * @adapter: board private structure
480 * @hwtstamps: time stamp structure to update
481 * @systim: unsigned 64bit system time value.
482 *
483 * Convert the system time value stored in the RX/TXSTMP registers into a
484 * hwtstamp which can be used by the upper level time stamping functions.
485 *
486 * The 'systim_lock' spinlock is used to protect the consistency of the
487 * system time value. This is needed because reading the 64 bit time
488 * value involves reading two 32 bit registers. The first read latches the
489 * value.
490 **/
491 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
492 struct skb_shared_hwtstamps *hwtstamps,
493 u64 systim)
494 {
495 u64 ns;
496 unsigned long flags;
497
498 spin_lock_irqsave(&adapter->systim_lock, flags);
499 ns = timecounter_cyc2time(&adapter->tc, systim);
500 spin_unlock_irqrestore(&adapter->systim_lock, flags);
501
502 memset(hwtstamps, 0, sizeof(*hwtstamps));
503 hwtstamps->hwtstamp = ns_to_ktime(ns);
504 }
505
506 /**
507 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
508 * @adapter: board private structure
509 * @status: descriptor extended error and status field
510 * @skb: particular skb to include time stamp
511 *
512 * If the time stamp is valid, convert it into the timecounter ns value
513 * and store that result into the shhwtstamps structure which is passed
514 * up the network stack.
515 **/
516 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
517 struct sk_buff *skb)
518 {
519 struct e1000_hw *hw = &adapter->hw;
520 u64 rxstmp;
521
522 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
523 !(status & E1000_RXDEXT_STATERR_TST) ||
524 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
525 return;
526
527 /* The Rx time stamp registers contain the time stamp. No other
528 * received packet will be time stamped until the Rx time stamp
529 * registers are read. Because only one packet can be time stamped
530 * at a time, the register values must belong to this packet and
531 * therefore none of the other additional attributes need to be
532 * compared.
533 */
534 rxstmp = (u64)er32(RXSTMPL);
535 rxstmp |= (u64)er32(RXSTMPH) << 32;
536 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
537
538 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
539 }
540
541 /**
542 * e1000_receive_skb - helper function to handle Rx indications
543 * @adapter: board private structure
544 * @staterr: descriptor extended error and status field as written by hardware
545 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
546 * @skb: pointer to sk_buff to be indicated to stack
547 **/
548 static void e1000_receive_skb(struct e1000_adapter *adapter,
549 struct net_device *netdev, struct sk_buff *skb,
550 u32 staterr, __le16 vlan)
551 {
552 u16 tag = le16_to_cpu(vlan);
553
554 e1000e_rx_hwtstamp(adapter, staterr, skb);
555
556 skb->protocol = eth_type_trans(skb, netdev);
557
558 if (staterr & E1000_RXD_STAT_VP)
559 __vlan_hwaccel_put_tag(skb, tag);
560
561 napi_gro_receive(&adapter->napi, skb);
562 }
563
564 /**
565 * e1000_rx_checksum - Receive Checksum Offload
566 * @adapter: board private structure
567 * @status_err: receive descriptor status and error fields
568 * @csum: receive descriptor csum field
569 * @sk_buff: socket buffer with received data
570 **/
571 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
572 struct sk_buff *skb)
573 {
574 u16 status = (u16)status_err;
575 u8 errors = (u8)(status_err >> 24);
576
577 skb_checksum_none_assert(skb);
578
579 /* Rx checksum disabled */
580 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
581 return;
582
583 /* Ignore Checksum bit is set */
584 if (status & E1000_RXD_STAT_IXSM)
585 return;
586
587 /* TCP/UDP checksum error bit or IP checksum error bit is set */
588 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
589 /* let the stack verify checksum errors */
590 adapter->hw_csum_err++;
591 return;
592 }
593
594 /* TCP/UDP Checksum has not been calculated */
595 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
596 return;
597
598 /* It must be a TCP or UDP packet with a valid checksum */
599 skb->ip_summed = CHECKSUM_UNNECESSARY;
600 adapter->hw_csum_good++;
601 }
602
603 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
604 {
605 struct e1000_adapter *adapter = rx_ring->adapter;
606 struct e1000_hw *hw = &adapter->hw;
607 s32 ret_val = __ew32_prepare(hw);
608
609 writel(i, rx_ring->tail);
610
611 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
612 u32 rctl = er32(RCTL);
613 ew32(RCTL, rctl & ~E1000_RCTL_EN);
614 e_err("ME firmware caused invalid RDT - resetting\n");
615 schedule_work(&adapter->reset_task);
616 }
617 }
618
619 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
620 {
621 struct e1000_adapter *adapter = tx_ring->adapter;
622 struct e1000_hw *hw = &adapter->hw;
623 s32 ret_val = __ew32_prepare(hw);
624
625 writel(i, tx_ring->tail);
626
627 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
628 u32 tctl = er32(TCTL);
629 ew32(TCTL, tctl & ~E1000_TCTL_EN);
630 e_err("ME firmware caused invalid TDT - resetting\n");
631 schedule_work(&adapter->reset_task);
632 }
633 }
634
635 /**
636 * e1000_alloc_rx_buffers - Replace used receive buffers
637 * @rx_ring: Rx descriptor ring
638 **/
639 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
640 int cleaned_count, gfp_t gfp)
641 {
642 struct e1000_adapter *adapter = rx_ring->adapter;
643 struct net_device *netdev = adapter->netdev;
644 struct pci_dev *pdev = adapter->pdev;
645 union e1000_rx_desc_extended *rx_desc;
646 struct e1000_buffer *buffer_info;
647 struct sk_buff *skb;
648 unsigned int i;
649 unsigned int bufsz = adapter->rx_buffer_len;
650
651 i = rx_ring->next_to_use;
652 buffer_info = &rx_ring->buffer_info[i];
653
654 while (cleaned_count--) {
655 skb = buffer_info->skb;
656 if (skb) {
657 skb_trim(skb, 0);
658 goto map_skb;
659 }
660
661 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
662 if (!skb) {
663 /* Better luck next round */
664 adapter->alloc_rx_buff_failed++;
665 break;
666 }
667
668 buffer_info->skb = skb;
669 map_skb:
670 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
671 adapter->rx_buffer_len,
672 DMA_FROM_DEVICE);
673 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
674 dev_err(&pdev->dev, "Rx DMA map failed\n");
675 adapter->rx_dma_failed++;
676 break;
677 }
678
679 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
680 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
681
682 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
683 /* Force memory writes to complete before letting h/w
684 * know there are new descriptors to fetch. (Only
685 * applicable for weak-ordered memory model archs,
686 * such as IA-64).
687 */
688 wmb();
689 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
690 e1000e_update_rdt_wa(rx_ring, i);
691 else
692 writel(i, rx_ring->tail);
693 }
694 i++;
695 if (i == rx_ring->count)
696 i = 0;
697 buffer_info = &rx_ring->buffer_info[i];
698 }
699
700 rx_ring->next_to_use = i;
701 }
702
703 /**
704 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
705 * @rx_ring: Rx descriptor ring
706 **/
707 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
708 int cleaned_count, gfp_t gfp)
709 {
710 struct e1000_adapter *adapter = rx_ring->adapter;
711 struct net_device *netdev = adapter->netdev;
712 struct pci_dev *pdev = adapter->pdev;
713 union e1000_rx_desc_packet_split *rx_desc;
714 struct e1000_buffer *buffer_info;
715 struct e1000_ps_page *ps_page;
716 struct sk_buff *skb;
717 unsigned int i, j;
718
719 i = rx_ring->next_to_use;
720 buffer_info = &rx_ring->buffer_info[i];
721
722 while (cleaned_count--) {
723 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
724
725 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
726 ps_page = &buffer_info->ps_pages[j];
727 if (j >= adapter->rx_ps_pages) {
728 /* all unused desc entries get hw null ptr */
729 rx_desc->read.buffer_addr[j + 1] =
730 ~cpu_to_le64(0);
731 continue;
732 }
733 if (!ps_page->page) {
734 ps_page->page = alloc_page(gfp);
735 if (!ps_page->page) {
736 adapter->alloc_rx_buff_failed++;
737 goto no_buffers;
738 }
739 ps_page->dma = dma_map_page(&pdev->dev,
740 ps_page->page,
741 0, PAGE_SIZE,
742 DMA_FROM_DEVICE);
743 if (dma_mapping_error(&pdev->dev,
744 ps_page->dma)) {
745 dev_err(&adapter->pdev->dev,
746 "Rx DMA page map failed\n");
747 adapter->rx_dma_failed++;
748 goto no_buffers;
749 }
750 }
751 /* Refresh the desc even if buffer_addrs
752 * didn't change because each write-back
753 * erases this info.
754 */
755 rx_desc->read.buffer_addr[j + 1] =
756 cpu_to_le64(ps_page->dma);
757 }
758
759 skb = __netdev_alloc_skb_ip_align(netdev,
760 adapter->rx_ps_bsize0,
761 gfp);
762
763 if (!skb) {
764 adapter->alloc_rx_buff_failed++;
765 break;
766 }
767
768 buffer_info->skb = skb;
769 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
770 adapter->rx_ps_bsize0,
771 DMA_FROM_DEVICE);
772 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
773 dev_err(&pdev->dev, "Rx DMA map failed\n");
774 adapter->rx_dma_failed++;
775 /* cleanup skb */
776 dev_kfree_skb_any(skb);
777 buffer_info->skb = NULL;
778 break;
779 }
780
781 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
782
783 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
784 /* Force memory writes to complete before letting h/w
785 * know there are new descriptors to fetch. (Only
786 * applicable for weak-ordered memory model archs,
787 * such as IA-64).
788 */
789 wmb();
790 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
791 e1000e_update_rdt_wa(rx_ring, i << 1);
792 else
793 writel(i << 1, rx_ring->tail);
794 }
795
796 i++;
797 if (i == rx_ring->count)
798 i = 0;
799 buffer_info = &rx_ring->buffer_info[i];
800 }
801
802 no_buffers:
803 rx_ring->next_to_use = i;
804 }
805
806 /**
807 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
808 * @rx_ring: Rx descriptor ring
809 * @cleaned_count: number of buffers to allocate this pass
810 **/
811
812 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
813 int cleaned_count, gfp_t gfp)
814 {
815 struct e1000_adapter *adapter = rx_ring->adapter;
816 struct net_device *netdev = adapter->netdev;
817 struct pci_dev *pdev = adapter->pdev;
818 union e1000_rx_desc_extended *rx_desc;
819 struct e1000_buffer *buffer_info;
820 struct sk_buff *skb;
821 unsigned int i;
822 unsigned int bufsz = 256 - 16; /* for skb_reserve */
823
824 i = rx_ring->next_to_use;
825 buffer_info = &rx_ring->buffer_info[i];
826
827 while (cleaned_count--) {
828 skb = buffer_info->skb;
829 if (skb) {
830 skb_trim(skb, 0);
831 goto check_page;
832 }
833
834 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
835 if (unlikely(!skb)) {
836 /* Better luck next round */
837 adapter->alloc_rx_buff_failed++;
838 break;
839 }
840
841 buffer_info->skb = skb;
842 check_page:
843 /* allocate a new page if necessary */
844 if (!buffer_info->page) {
845 buffer_info->page = alloc_page(gfp);
846 if (unlikely(!buffer_info->page)) {
847 adapter->alloc_rx_buff_failed++;
848 break;
849 }
850 }
851
852 if (!buffer_info->dma)
853 buffer_info->dma = dma_map_page(&pdev->dev,
854 buffer_info->page, 0,
855 PAGE_SIZE,
856 DMA_FROM_DEVICE);
857
858 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
859 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
860
861 if (unlikely(++i == rx_ring->count))
862 i = 0;
863 buffer_info = &rx_ring->buffer_info[i];
864 }
865
866 if (likely(rx_ring->next_to_use != i)) {
867 rx_ring->next_to_use = i;
868 if (unlikely(i-- == 0))
869 i = (rx_ring->count - 1);
870
871 /* Force memory writes to complete before letting h/w
872 * know there are new descriptors to fetch. (Only
873 * applicable for weak-ordered memory model archs,
874 * such as IA-64).
875 */
876 wmb();
877 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
878 e1000e_update_rdt_wa(rx_ring, i);
879 else
880 writel(i, rx_ring->tail);
881 }
882 }
883
884 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
885 struct sk_buff *skb)
886 {
887 if (netdev->features & NETIF_F_RXHASH)
888 skb->rxhash = le32_to_cpu(rss);
889 }
890
891 /**
892 * e1000_clean_rx_irq - Send received data up the network stack
893 * @rx_ring: Rx descriptor ring
894 *
895 * the return value indicates whether actual cleaning was done, there
896 * is no guarantee that everything was cleaned
897 **/
898 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
899 int work_to_do)
900 {
901 struct e1000_adapter *adapter = rx_ring->adapter;
902 struct net_device *netdev = adapter->netdev;
903 struct pci_dev *pdev = adapter->pdev;
904 struct e1000_hw *hw = &adapter->hw;
905 union e1000_rx_desc_extended *rx_desc, *next_rxd;
906 struct e1000_buffer *buffer_info, *next_buffer;
907 u32 length, staterr;
908 unsigned int i;
909 int cleaned_count = 0;
910 bool cleaned = false;
911 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
912
913 i = rx_ring->next_to_clean;
914 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
915 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
916 buffer_info = &rx_ring->buffer_info[i];
917
918 while (staterr & E1000_RXD_STAT_DD) {
919 struct sk_buff *skb;
920
921 if (*work_done >= work_to_do)
922 break;
923 (*work_done)++;
924 rmb(); /* read descriptor and rx_buffer_info after status DD */
925
926 skb = buffer_info->skb;
927 buffer_info->skb = NULL;
928
929 prefetch(skb->data - NET_IP_ALIGN);
930
931 i++;
932 if (i == rx_ring->count)
933 i = 0;
934 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
935 prefetch(next_rxd);
936
937 next_buffer = &rx_ring->buffer_info[i];
938
939 cleaned = true;
940 cleaned_count++;
941 dma_unmap_single(&pdev->dev,
942 buffer_info->dma,
943 adapter->rx_buffer_len,
944 DMA_FROM_DEVICE);
945 buffer_info->dma = 0;
946
947 length = le16_to_cpu(rx_desc->wb.upper.length);
948
949 /* !EOP means multiple descriptors were used to store a single
950 * packet, if that's the case we need to toss it. In fact, we
951 * need to toss every packet with the EOP bit clear and the
952 * next frame that _does_ have the EOP bit set, as it is by
953 * definition only a frame fragment
954 */
955 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
956 adapter->flags2 |= FLAG2_IS_DISCARDING;
957
958 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
959 /* All receives must fit into a single buffer */
960 e_dbg("Receive packet consumed multiple buffers\n");
961 /* recycle */
962 buffer_info->skb = skb;
963 if (staterr & E1000_RXD_STAT_EOP)
964 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
965 goto next_desc;
966 }
967
968 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
969 !(netdev->features & NETIF_F_RXALL))) {
970 /* recycle */
971 buffer_info->skb = skb;
972 goto next_desc;
973 }
974
975 /* adjust length to remove Ethernet CRC */
976 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
977 /* If configured to store CRC, don't subtract FCS,
978 * but keep the FCS bytes out of the total_rx_bytes
979 * counter
980 */
981 if (netdev->features & NETIF_F_RXFCS)
982 total_rx_bytes -= 4;
983 else
984 length -= 4;
985 }
986
987 total_rx_bytes += length;
988 total_rx_packets++;
989
990 /* code added for copybreak, this should improve
991 * performance for small packets with large amounts
992 * of reassembly being done in the stack
993 */
994 if (length < copybreak) {
995 struct sk_buff *new_skb =
996 netdev_alloc_skb_ip_align(netdev, length);
997 if (new_skb) {
998 skb_copy_to_linear_data_offset(new_skb,
999 -NET_IP_ALIGN,
1000 (skb->data -
1001 NET_IP_ALIGN),
1002 (length +
1003 NET_IP_ALIGN));
1004 /* save the skb in buffer_info as good */
1005 buffer_info->skb = skb;
1006 skb = new_skb;
1007 }
1008 /* else just continue with the old one */
1009 }
1010 /* end copybreak code */
1011 skb_put(skb, length);
1012
1013 /* Receive Checksum Offload */
1014 e1000_rx_checksum(adapter, staterr, skb);
1015
1016 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1017
1018 e1000_receive_skb(adapter, netdev, skb, staterr,
1019 rx_desc->wb.upper.vlan);
1020
1021 next_desc:
1022 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1023
1024 /* return some buffers to hardware, one at a time is too slow */
1025 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1026 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1027 GFP_ATOMIC);
1028 cleaned_count = 0;
1029 }
1030
1031 /* use prefetched values */
1032 rx_desc = next_rxd;
1033 buffer_info = next_buffer;
1034
1035 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1036 }
1037 rx_ring->next_to_clean = i;
1038
1039 cleaned_count = e1000_desc_unused(rx_ring);
1040 if (cleaned_count)
1041 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1042
1043 adapter->total_rx_bytes += total_rx_bytes;
1044 adapter->total_rx_packets += total_rx_packets;
1045 return cleaned;
1046 }
1047
1048 static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1049 struct e1000_buffer *buffer_info)
1050 {
1051 struct e1000_adapter *adapter = tx_ring->adapter;
1052
1053 if (buffer_info->dma) {
1054 if (buffer_info->mapped_as_page)
1055 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1056 buffer_info->length, DMA_TO_DEVICE);
1057 else
1058 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1059 buffer_info->length, DMA_TO_DEVICE);
1060 buffer_info->dma = 0;
1061 }
1062 if (buffer_info->skb) {
1063 dev_kfree_skb_any(buffer_info->skb);
1064 buffer_info->skb = NULL;
1065 }
1066 buffer_info->time_stamp = 0;
1067 }
1068
1069 static void e1000_print_hw_hang(struct work_struct *work)
1070 {
1071 struct e1000_adapter *adapter = container_of(work,
1072 struct e1000_adapter,
1073 print_hang_task);
1074 struct net_device *netdev = adapter->netdev;
1075 struct e1000_ring *tx_ring = adapter->tx_ring;
1076 unsigned int i = tx_ring->next_to_clean;
1077 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1078 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
1079 struct e1000_hw *hw = &adapter->hw;
1080 u16 phy_status, phy_1000t_status, phy_ext_status;
1081 u16 pci_status;
1082
1083 if (test_bit(__E1000_DOWN, &adapter->state))
1084 return;
1085
1086 if (!adapter->tx_hang_recheck &&
1087 (adapter->flags2 & FLAG2_DMA_BURST)) {
1088 /* May be block on write-back, flush and detect again
1089 * flush pending descriptor writebacks to memory
1090 */
1091 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1092 /* execute the writes immediately */
1093 e1e_flush();
1094 /* Due to rare timing issues, write to TIDV again to ensure
1095 * the write is successful
1096 */
1097 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1098 /* execute the writes immediately */
1099 e1e_flush();
1100 adapter->tx_hang_recheck = true;
1101 return;
1102 }
1103 /* Real hang detected */
1104 adapter->tx_hang_recheck = false;
1105 netif_stop_queue(netdev);
1106
1107 e1e_rphy(hw, MII_BMSR, &phy_status);
1108 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1109 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
1110
1111 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1112
1113 /* detected Hardware unit hang */
1114 e_err("Detected Hardware Unit Hang:\n"
1115 " TDH <%x>\n"
1116 " TDT <%x>\n"
1117 " next_to_use <%x>\n"
1118 " next_to_clean <%x>\n"
1119 "buffer_info[next_to_clean]:\n"
1120 " time_stamp <%lx>\n"
1121 " next_to_watch <%x>\n"
1122 " jiffies <%lx>\n"
1123 " next_to_watch.status <%x>\n"
1124 "MAC Status <%x>\n"
1125 "PHY Status <%x>\n"
1126 "PHY 1000BASE-T Status <%x>\n"
1127 "PHY Extended Status <%x>\n"
1128 "PCI Status <%x>\n",
1129 readl(tx_ring->head),
1130 readl(tx_ring->tail),
1131 tx_ring->next_to_use,
1132 tx_ring->next_to_clean,
1133 tx_ring->buffer_info[eop].time_stamp,
1134 eop,
1135 jiffies,
1136 eop_desc->upper.fields.status,
1137 er32(STATUS),
1138 phy_status,
1139 phy_1000t_status,
1140 phy_ext_status,
1141 pci_status);
1142
1143 /* Suggest workaround for known h/w issue */
1144 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1145 e_err("Try turning off Tx pause (flow control) via ethtool\n");
1146 }
1147
1148 /**
1149 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1150 * @work: pointer to work struct
1151 *
1152 * This work function polls the TSYNCTXCTL valid bit to determine when a
1153 * timestamp has been taken for the current stored skb. The timestamp must
1154 * be for this skb because only one such packet is allowed in the queue.
1155 */
1156 static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1157 {
1158 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1159 tx_hwtstamp_work);
1160 struct e1000_hw *hw = &adapter->hw;
1161
1162 if (!adapter->tx_hwtstamp_skb)
1163 return;
1164
1165 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1166 struct skb_shared_hwtstamps shhwtstamps;
1167 u64 txstmp;
1168
1169 txstmp = er32(TXSTMPL);
1170 txstmp |= (u64)er32(TXSTMPH) << 32;
1171
1172 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1173
1174 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps);
1175 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1176 adapter->tx_hwtstamp_skb = NULL;
1177 } else {
1178 /* reschedule to check later */
1179 schedule_work(&adapter->tx_hwtstamp_work);
1180 }
1181 }
1182
1183 /**
1184 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1185 * @tx_ring: Tx descriptor ring
1186 *
1187 * the return value indicates whether actual cleaning was done, there
1188 * is no guarantee that everything was cleaned
1189 **/
1190 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
1191 {
1192 struct e1000_adapter *adapter = tx_ring->adapter;
1193 struct net_device *netdev = adapter->netdev;
1194 struct e1000_hw *hw = &adapter->hw;
1195 struct e1000_tx_desc *tx_desc, *eop_desc;
1196 struct e1000_buffer *buffer_info;
1197 unsigned int i, eop;
1198 unsigned int count = 0;
1199 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
1200 unsigned int bytes_compl = 0, pkts_compl = 0;
1201
1202 i = tx_ring->next_to_clean;
1203 eop = tx_ring->buffer_info[i].next_to_watch;
1204 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1205
1206 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1207 (count < tx_ring->count)) {
1208 bool cleaned = false;
1209 rmb(); /* read buffer_info after eop_desc */
1210 for (; !cleaned; count++) {
1211 tx_desc = E1000_TX_DESC(*tx_ring, i);
1212 buffer_info = &tx_ring->buffer_info[i];
1213 cleaned = (i == eop);
1214
1215 if (cleaned) {
1216 total_tx_packets += buffer_info->segs;
1217 total_tx_bytes += buffer_info->bytecount;
1218 if (buffer_info->skb) {
1219 bytes_compl += buffer_info->skb->len;
1220 pkts_compl++;
1221 }
1222 }
1223
1224 e1000_put_txbuf(tx_ring, buffer_info);
1225 tx_desc->upper.data = 0;
1226
1227 i++;
1228 if (i == tx_ring->count)
1229 i = 0;
1230 }
1231
1232 if (i == tx_ring->next_to_use)
1233 break;
1234 eop = tx_ring->buffer_info[i].next_to_watch;
1235 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1236 }
1237
1238 tx_ring->next_to_clean = i;
1239
1240 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1241
1242 #define TX_WAKE_THRESHOLD 32
1243 if (count && netif_carrier_ok(netdev) &&
1244 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
1245 /* Make sure that anybody stopping the queue after this
1246 * sees the new next_to_clean.
1247 */
1248 smp_mb();
1249
1250 if (netif_queue_stopped(netdev) &&
1251 !(test_bit(__E1000_DOWN, &adapter->state))) {
1252 netif_wake_queue(netdev);
1253 ++adapter->restart_queue;
1254 }
1255 }
1256
1257 if (adapter->detect_tx_hung) {
1258 /* Detect a transmit hang in hardware, this serializes the
1259 * check with the clearing of time_stamp and movement of i
1260 */
1261 adapter->detect_tx_hung = false;
1262 if (tx_ring->buffer_info[i].time_stamp &&
1263 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
1264 + (adapter->tx_timeout_factor * HZ)) &&
1265 !(er32(STATUS) & E1000_STATUS_TXOFF))
1266 schedule_work(&adapter->print_hang_task);
1267 else
1268 adapter->tx_hang_recheck = false;
1269 }
1270 adapter->total_tx_bytes += total_tx_bytes;
1271 adapter->total_tx_packets += total_tx_packets;
1272 return count < tx_ring->count;
1273 }
1274
1275 /**
1276 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1277 * @rx_ring: Rx descriptor ring
1278 *
1279 * the return value indicates whether actual cleaning was done, there
1280 * is no guarantee that everything was cleaned
1281 **/
1282 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1283 int work_to_do)
1284 {
1285 struct e1000_adapter *adapter = rx_ring->adapter;
1286 struct e1000_hw *hw = &adapter->hw;
1287 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1288 struct net_device *netdev = adapter->netdev;
1289 struct pci_dev *pdev = adapter->pdev;
1290 struct e1000_buffer *buffer_info, *next_buffer;
1291 struct e1000_ps_page *ps_page;
1292 struct sk_buff *skb;
1293 unsigned int i, j;
1294 u32 length, staterr;
1295 int cleaned_count = 0;
1296 bool cleaned = false;
1297 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1298
1299 i = rx_ring->next_to_clean;
1300 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1301 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1302 buffer_info = &rx_ring->buffer_info[i];
1303
1304 while (staterr & E1000_RXD_STAT_DD) {
1305 if (*work_done >= work_to_do)
1306 break;
1307 (*work_done)++;
1308 skb = buffer_info->skb;
1309 rmb(); /* read descriptor and rx_buffer_info after status DD */
1310
1311 /* in the packet split case this is header only */
1312 prefetch(skb->data - NET_IP_ALIGN);
1313
1314 i++;
1315 if (i == rx_ring->count)
1316 i = 0;
1317 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1318 prefetch(next_rxd);
1319
1320 next_buffer = &rx_ring->buffer_info[i];
1321
1322 cleaned = true;
1323 cleaned_count++;
1324 dma_unmap_single(&pdev->dev, buffer_info->dma,
1325 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
1326 buffer_info->dma = 0;
1327
1328 /* see !EOP comment in other Rx routine */
1329 if (!(staterr & E1000_RXD_STAT_EOP))
1330 adapter->flags2 |= FLAG2_IS_DISCARDING;
1331
1332 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
1333 e_dbg("Packet Split buffers didn't pick up the full packet\n");
1334 dev_kfree_skb_irq(skb);
1335 if (staterr & E1000_RXD_STAT_EOP)
1336 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1337 goto next_desc;
1338 }
1339
1340 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1341 !(netdev->features & NETIF_F_RXALL))) {
1342 dev_kfree_skb_irq(skb);
1343 goto next_desc;
1344 }
1345
1346 length = le16_to_cpu(rx_desc->wb.middle.length0);
1347
1348 if (!length) {
1349 e_dbg("Last part of the packet spanning multiple descriptors\n");
1350 dev_kfree_skb_irq(skb);
1351 goto next_desc;
1352 }
1353
1354 /* Good Receive */
1355 skb_put(skb, length);
1356
1357 {
1358 /* this looks ugly, but it seems compiler issues make
1359 * it more efficient than reusing j
1360 */
1361 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1362
1363 /* page alloc/put takes too long and effects small
1364 * packet throughput, so unsplit small packets and
1365 * save the alloc/put only valid in softirq (napi)
1366 * context to call kmap_*
1367 */
1368 if (l1 && (l1 <= copybreak) &&
1369 ((length + l1) <= adapter->rx_ps_bsize0)) {
1370 u8 *vaddr;
1371
1372 ps_page = &buffer_info->ps_pages[0];
1373
1374 /* there is no documentation about how to call
1375 * kmap_atomic, so we can't hold the mapping
1376 * very long
1377 */
1378 dma_sync_single_for_cpu(&pdev->dev,
1379 ps_page->dma,
1380 PAGE_SIZE,
1381 DMA_FROM_DEVICE);
1382 vaddr = kmap_atomic(ps_page->page);
1383 memcpy(skb_tail_pointer(skb), vaddr, l1);
1384 kunmap_atomic(vaddr);
1385 dma_sync_single_for_device(&pdev->dev,
1386 ps_page->dma,
1387 PAGE_SIZE,
1388 DMA_FROM_DEVICE);
1389
1390 /* remove the CRC */
1391 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1392 if (!(netdev->features & NETIF_F_RXFCS))
1393 l1 -= 4;
1394 }
1395
1396 skb_put(skb, l1);
1397 goto copydone;
1398 } /* if */
1399 }
1400
1401 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1402 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1403 if (!length)
1404 break;
1405
1406 ps_page = &buffer_info->ps_pages[j];
1407 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1408 DMA_FROM_DEVICE);
1409 ps_page->dma = 0;
1410 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1411 ps_page->page = NULL;
1412 skb->len += length;
1413 skb->data_len += length;
1414 skb->truesize += PAGE_SIZE;
1415 }
1416
1417 /* strip the ethernet crc, problem is we're using pages now so
1418 * this whole operation can get a little cpu intensive
1419 */
1420 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1421 if (!(netdev->features & NETIF_F_RXFCS))
1422 pskb_trim(skb, skb->len - 4);
1423 }
1424
1425 copydone:
1426 total_rx_bytes += skb->len;
1427 total_rx_packets++;
1428
1429 e1000_rx_checksum(adapter, staterr, skb);
1430
1431 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1432
1433 if (rx_desc->wb.upper.header_status &
1434 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1435 adapter->rx_hdr_split++;
1436
1437 e1000_receive_skb(adapter, netdev, skb, staterr,
1438 rx_desc->wb.middle.vlan);
1439
1440 next_desc:
1441 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1442 buffer_info->skb = NULL;
1443
1444 /* return some buffers to hardware, one at a time is too slow */
1445 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1446 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1447 GFP_ATOMIC);
1448 cleaned_count = 0;
1449 }
1450
1451 /* use prefetched values */
1452 rx_desc = next_rxd;
1453 buffer_info = next_buffer;
1454
1455 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1456 }
1457 rx_ring->next_to_clean = i;
1458
1459 cleaned_count = e1000_desc_unused(rx_ring);
1460 if (cleaned_count)
1461 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1462
1463 adapter->total_rx_bytes += total_rx_bytes;
1464 adapter->total_rx_packets += total_rx_packets;
1465 return cleaned;
1466 }
1467
1468 /**
1469 * e1000_consume_page - helper function
1470 **/
1471 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1472 u16 length)
1473 {
1474 bi->page = NULL;
1475 skb->len += length;
1476 skb->data_len += length;
1477 skb->truesize += PAGE_SIZE;
1478 }
1479
1480 /**
1481 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1482 * @adapter: board private structure
1483 *
1484 * the return value indicates whether actual cleaning was done, there
1485 * is no guarantee that everything was cleaned
1486 **/
1487 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1488 int work_to_do)
1489 {
1490 struct e1000_adapter *adapter = rx_ring->adapter;
1491 struct net_device *netdev = adapter->netdev;
1492 struct pci_dev *pdev = adapter->pdev;
1493 union e1000_rx_desc_extended *rx_desc, *next_rxd;
1494 struct e1000_buffer *buffer_info, *next_buffer;
1495 u32 length, staterr;
1496 unsigned int i;
1497 int cleaned_count = 0;
1498 bool cleaned = false;
1499 unsigned int total_rx_bytes=0, total_rx_packets=0;
1500
1501 i = rx_ring->next_to_clean;
1502 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1503 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1504 buffer_info = &rx_ring->buffer_info[i];
1505
1506 while (staterr & E1000_RXD_STAT_DD) {
1507 struct sk_buff *skb;
1508
1509 if (*work_done >= work_to_do)
1510 break;
1511 (*work_done)++;
1512 rmb(); /* read descriptor and rx_buffer_info after status DD */
1513
1514 skb = buffer_info->skb;
1515 buffer_info->skb = NULL;
1516
1517 ++i;
1518 if (i == rx_ring->count)
1519 i = 0;
1520 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
1521 prefetch(next_rxd);
1522
1523 next_buffer = &rx_ring->buffer_info[i];
1524
1525 cleaned = true;
1526 cleaned_count++;
1527 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1528 DMA_FROM_DEVICE);
1529 buffer_info->dma = 0;
1530
1531 length = le16_to_cpu(rx_desc->wb.upper.length);
1532
1533 /* errors is only valid for DD + EOP descriptors */
1534 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1535 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1536 !(netdev->features & NETIF_F_RXALL)))) {
1537 /* recycle both page and skb */
1538 buffer_info->skb = skb;
1539 /* an error means any chain goes out the window too */
1540 if (rx_ring->rx_skb_top)
1541 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1542 rx_ring->rx_skb_top = NULL;
1543 goto next_desc;
1544 }
1545
1546 #define rxtop (rx_ring->rx_skb_top)
1547 if (!(staterr & E1000_RXD_STAT_EOP)) {
1548 /* this descriptor is only the beginning (or middle) */
1549 if (!rxtop) {
1550 /* this is the beginning of a chain */
1551 rxtop = skb;
1552 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1553 0, length);
1554 } else {
1555 /* this is the middle of a chain */
1556 skb_fill_page_desc(rxtop,
1557 skb_shinfo(rxtop)->nr_frags,
1558 buffer_info->page, 0, length);
1559 /* re-use the skb, only consumed the page */
1560 buffer_info->skb = skb;
1561 }
1562 e1000_consume_page(buffer_info, rxtop, length);
1563 goto next_desc;
1564 } else {
1565 if (rxtop) {
1566 /* end of the chain */
1567 skb_fill_page_desc(rxtop,
1568 skb_shinfo(rxtop)->nr_frags,
1569 buffer_info->page, 0, length);
1570 /* re-use the current skb, we only consumed the
1571 * page
1572 */
1573 buffer_info->skb = skb;
1574 skb = rxtop;
1575 rxtop = NULL;
1576 e1000_consume_page(buffer_info, skb, length);
1577 } else {
1578 /* no chain, got EOP, this buf is the packet
1579 * copybreak to save the put_page/alloc_page
1580 */
1581 if (length <= copybreak &&
1582 skb_tailroom(skb) >= length) {
1583 u8 *vaddr;
1584 vaddr = kmap_atomic(buffer_info->page);
1585 memcpy(skb_tail_pointer(skb), vaddr,
1586 length);
1587 kunmap_atomic(vaddr);
1588 /* re-use the page, so don't erase
1589 * buffer_info->page
1590 */
1591 skb_put(skb, length);
1592 } else {
1593 skb_fill_page_desc(skb, 0,
1594 buffer_info->page, 0,
1595 length);
1596 e1000_consume_page(buffer_info, skb,
1597 length);
1598 }
1599 }
1600 }
1601
1602 /* Receive Checksum Offload */
1603 e1000_rx_checksum(adapter, staterr, skb);
1604
1605 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1606
1607 /* probably a little skewed due to removing CRC */
1608 total_rx_bytes += skb->len;
1609 total_rx_packets++;
1610
1611 /* eth type trans needs skb->data to point to something */
1612 if (!pskb_may_pull(skb, ETH_HLEN)) {
1613 e_err("pskb_may_pull failed.\n");
1614 dev_kfree_skb_irq(skb);
1615 goto next_desc;
1616 }
1617
1618 e1000_receive_skb(adapter, netdev, skb, staterr,
1619 rx_desc->wb.upper.vlan);
1620
1621 next_desc:
1622 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1623
1624 /* return some buffers to hardware, one at a time is too slow */
1625 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
1626 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1627 GFP_ATOMIC);
1628 cleaned_count = 0;
1629 }
1630
1631 /* use prefetched values */
1632 rx_desc = next_rxd;
1633 buffer_info = next_buffer;
1634
1635 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1636 }
1637 rx_ring->next_to_clean = i;
1638
1639 cleaned_count = e1000_desc_unused(rx_ring);
1640 if (cleaned_count)
1641 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1642
1643 adapter->total_rx_bytes += total_rx_bytes;
1644 adapter->total_rx_packets += total_rx_packets;
1645 return cleaned;
1646 }
1647
1648 /**
1649 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1650 * @rx_ring: Rx descriptor ring
1651 **/
1652 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
1653 {
1654 struct e1000_adapter *adapter = rx_ring->adapter;
1655 struct e1000_buffer *buffer_info;
1656 struct e1000_ps_page *ps_page;
1657 struct pci_dev *pdev = adapter->pdev;
1658 unsigned int i, j;
1659
1660 /* Free all the Rx ring sk_buffs */
1661 for (i = 0; i < rx_ring->count; i++) {
1662 buffer_info = &rx_ring->buffer_info[i];
1663 if (buffer_info->dma) {
1664 if (adapter->clean_rx == e1000_clean_rx_irq)
1665 dma_unmap_single(&pdev->dev, buffer_info->dma,
1666 adapter->rx_buffer_len,
1667 DMA_FROM_DEVICE);
1668 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
1669 dma_unmap_page(&pdev->dev, buffer_info->dma,
1670 PAGE_SIZE,
1671 DMA_FROM_DEVICE);
1672 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
1673 dma_unmap_single(&pdev->dev, buffer_info->dma,
1674 adapter->rx_ps_bsize0,
1675 DMA_FROM_DEVICE);
1676 buffer_info->dma = 0;
1677 }
1678
1679 if (buffer_info->page) {
1680 put_page(buffer_info->page);
1681 buffer_info->page = NULL;
1682 }
1683
1684 if (buffer_info->skb) {
1685 dev_kfree_skb(buffer_info->skb);
1686 buffer_info->skb = NULL;
1687 }
1688
1689 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1690 ps_page = &buffer_info->ps_pages[j];
1691 if (!ps_page->page)
1692 break;
1693 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1694 DMA_FROM_DEVICE);
1695 ps_page->dma = 0;
1696 put_page(ps_page->page);
1697 ps_page->page = NULL;
1698 }
1699 }
1700
1701 /* there also may be some cached data from a chained receive */
1702 if (rx_ring->rx_skb_top) {
1703 dev_kfree_skb(rx_ring->rx_skb_top);
1704 rx_ring->rx_skb_top = NULL;
1705 }
1706
1707 /* Zero out the descriptor ring */
1708 memset(rx_ring->desc, 0, rx_ring->size);
1709
1710 rx_ring->next_to_clean = 0;
1711 rx_ring->next_to_use = 0;
1712 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1713
1714 writel(0, rx_ring->head);
1715 if (rx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
1716 e1000e_update_rdt_wa(rx_ring, 0);
1717 else
1718 writel(0, rx_ring->tail);
1719 }
1720
1721 static void e1000e_downshift_workaround(struct work_struct *work)
1722 {
1723 struct e1000_adapter *adapter = container_of(work,
1724 struct e1000_adapter, downshift_task);
1725
1726 if (test_bit(__E1000_DOWN, &adapter->state))
1727 return;
1728
1729 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1730 }
1731
1732 /**
1733 * e1000_intr_msi - Interrupt Handler
1734 * @irq: interrupt number
1735 * @data: pointer to a network interface device structure
1736 **/
1737 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
1738 {
1739 struct net_device *netdev = data;
1740 struct e1000_adapter *adapter = netdev_priv(netdev);
1741 struct e1000_hw *hw = &adapter->hw;
1742 u32 icr = er32(ICR);
1743
1744 /* read ICR disables interrupts using IAM */
1745 if (icr & E1000_ICR_LSC) {
1746 hw->mac.get_link_status = true;
1747 /* ICH8 workaround-- Call gig speed drop workaround on cable
1748 * disconnect (LSC) before accessing any PHY registers
1749 */
1750 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1751 (!(er32(STATUS) & E1000_STATUS_LU)))
1752 schedule_work(&adapter->downshift_task);
1753
1754 /* 80003ES2LAN workaround-- For packet buffer work-around on
1755 * link down event; disable receives here in the ISR and reset
1756 * adapter in watchdog
1757 */
1758 if (netif_carrier_ok(netdev) &&
1759 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1760 /* disable receives */
1761 u32 rctl = er32(RCTL);
1762 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1763 adapter->flags |= FLAG_RESTART_NOW;
1764 }
1765 /* guard against interrupt when we're going down */
1766 if (!test_bit(__E1000_DOWN, &adapter->state))
1767 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1768 }
1769
1770 /* Reset on uncorrectable ECC error */
1771 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1772 u32 pbeccsts = er32(PBECCSTS);
1773
1774 adapter->corr_errors +=
1775 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1776 adapter->uncorr_errors +=
1777 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1778 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1779
1780 /* Do the reset outside of interrupt context */
1781 schedule_work(&adapter->reset_task);
1782
1783 /* return immediately since reset is imminent */
1784 return IRQ_HANDLED;
1785 }
1786
1787 if (napi_schedule_prep(&adapter->napi)) {
1788 adapter->total_tx_bytes = 0;
1789 adapter->total_tx_packets = 0;
1790 adapter->total_rx_bytes = 0;
1791 adapter->total_rx_packets = 0;
1792 __napi_schedule(&adapter->napi);
1793 }
1794
1795 return IRQ_HANDLED;
1796 }
1797
1798 /**
1799 * e1000_intr - Interrupt Handler
1800 * @irq: interrupt number
1801 * @data: pointer to a network interface device structure
1802 **/
1803 static irqreturn_t e1000_intr(int __always_unused irq, void *data)
1804 {
1805 struct net_device *netdev = data;
1806 struct e1000_adapter *adapter = netdev_priv(netdev);
1807 struct e1000_hw *hw = &adapter->hw;
1808 u32 rctl, icr = er32(ICR);
1809
1810 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
1811 return IRQ_NONE; /* Not our interrupt */
1812
1813 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1814 * not set, then the adapter didn't send an interrupt
1815 */
1816 if (!(icr & E1000_ICR_INT_ASSERTED))
1817 return IRQ_NONE;
1818
1819 /* Interrupt Auto-Mask...upon reading ICR,
1820 * interrupts are masked. No need for the
1821 * IMC write
1822 */
1823
1824 if (icr & E1000_ICR_LSC) {
1825 hw->mac.get_link_status = true;
1826 /* ICH8 workaround-- Call gig speed drop workaround on cable
1827 * disconnect (LSC) before accessing any PHY registers
1828 */
1829 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1830 (!(er32(STATUS) & E1000_STATUS_LU)))
1831 schedule_work(&adapter->downshift_task);
1832
1833 /* 80003ES2LAN workaround--
1834 * For packet buffer work-around on link down event;
1835 * disable receives here in the ISR and
1836 * reset adapter in watchdog
1837 */
1838 if (netif_carrier_ok(netdev) &&
1839 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1840 /* disable receives */
1841 rctl = er32(RCTL);
1842 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1843 adapter->flags |= FLAG_RESTART_NOW;
1844 }
1845 /* guard against interrupt when we're going down */
1846 if (!test_bit(__E1000_DOWN, &adapter->state))
1847 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1848 }
1849
1850 /* Reset on uncorrectable ECC error */
1851 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1852 u32 pbeccsts = er32(PBECCSTS);
1853
1854 adapter->corr_errors +=
1855 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1856 adapter->uncorr_errors +=
1857 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1858 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1859
1860 /* Do the reset outside of interrupt context */
1861 schedule_work(&adapter->reset_task);
1862
1863 /* return immediately since reset is imminent */
1864 return IRQ_HANDLED;
1865 }
1866
1867 if (napi_schedule_prep(&adapter->napi)) {
1868 adapter->total_tx_bytes = 0;
1869 adapter->total_tx_packets = 0;
1870 adapter->total_rx_bytes = 0;
1871 adapter->total_rx_packets = 0;
1872 __napi_schedule(&adapter->napi);
1873 }
1874
1875 return IRQ_HANDLED;
1876 }
1877
1878 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
1879 {
1880 struct net_device *netdev = data;
1881 struct e1000_adapter *adapter = netdev_priv(netdev);
1882 struct e1000_hw *hw = &adapter->hw;
1883 u32 icr = er32(ICR);
1884
1885 if (!(icr & E1000_ICR_INT_ASSERTED)) {
1886 if (!test_bit(__E1000_DOWN, &adapter->state))
1887 ew32(IMS, E1000_IMS_OTHER);
1888 return IRQ_NONE;
1889 }
1890
1891 if (icr & adapter->eiac_mask)
1892 ew32(ICS, (icr & adapter->eiac_mask));
1893
1894 if (icr & E1000_ICR_OTHER) {
1895 if (!(icr & E1000_ICR_LSC))
1896 goto no_link_interrupt;
1897 hw->mac.get_link_status = true;
1898 /* guard against interrupt when we're going down */
1899 if (!test_bit(__E1000_DOWN, &adapter->state))
1900 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1901 }
1902
1903 no_link_interrupt:
1904 if (!test_bit(__E1000_DOWN, &adapter->state))
1905 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
1906
1907 return IRQ_HANDLED;
1908 }
1909
1910 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
1911 {
1912 struct net_device *netdev = data;
1913 struct e1000_adapter *adapter = netdev_priv(netdev);
1914 struct e1000_hw *hw = &adapter->hw;
1915 struct e1000_ring *tx_ring = adapter->tx_ring;
1916
1917
1918 adapter->total_tx_bytes = 0;
1919 adapter->total_tx_packets = 0;
1920
1921 if (!e1000_clean_tx_irq(tx_ring))
1922 /* Ring was not completely cleaned, so fire another interrupt */
1923 ew32(ICS, tx_ring->ims_val);
1924
1925 return IRQ_HANDLED;
1926 }
1927
1928 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
1929 {
1930 struct net_device *netdev = data;
1931 struct e1000_adapter *adapter = netdev_priv(netdev);
1932 struct e1000_ring *rx_ring = adapter->rx_ring;
1933
1934 /* Write the ITR value calculated at the end of the
1935 * previous interrupt.
1936 */
1937 if (rx_ring->set_itr) {
1938 writel(1000000000 / (rx_ring->itr_val * 256),
1939 rx_ring->itr_register);
1940 rx_ring->set_itr = 0;
1941 }
1942
1943 if (napi_schedule_prep(&adapter->napi)) {
1944 adapter->total_rx_bytes = 0;
1945 adapter->total_rx_packets = 0;
1946 __napi_schedule(&adapter->napi);
1947 }
1948 return IRQ_HANDLED;
1949 }
1950
1951 /**
1952 * e1000_configure_msix - Configure MSI-X hardware
1953 *
1954 * e1000_configure_msix sets up the hardware to properly
1955 * generate MSI-X interrupts.
1956 **/
1957 static void e1000_configure_msix(struct e1000_adapter *adapter)
1958 {
1959 struct e1000_hw *hw = &adapter->hw;
1960 struct e1000_ring *rx_ring = adapter->rx_ring;
1961 struct e1000_ring *tx_ring = adapter->tx_ring;
1962 int vector = 0;
1963 u32 ctrl_ext, ivar = 0;
1964
1965 adapter->eiac_mask = 0;
1966
1967 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1968 if (hw->mac.type == e1000_82574) {
1969 u32 rfctl = er32(RFCTL);
1970 rfctl |= E1000_RFCTL_ACK_DIS;
1971 ew32(RFCTL, rfctl);
1972 }
1973
1974 #define E1000_IVAR_INT_ALLOC_VALID 0x8
1975 /* Configure Rx vector */
1976 rx_ring->ims_val = E1000_IMS_RXQ0;
1977 adapter->eiac_mask |= rx_ring->ims_val;
1978 if (rx_ring->itr_val)
1979 writel(1000000000 / (rx_ring->itr_val * 256),
1980 rx_ring->itr_register);
1981 else
1982 writel(1, rx_ring->itr_register);
1983 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1984
1985 /* Configure Tx vector */
1986 tx_ring->ims_val = E1000_IMS_TXQ0;
1987 vector++;
1988 if (tx_ring->itr_val)
1989 writel(1000000000 / (tx_ring->itr_val * 256),
1990 tx_ring->itr_register);
1991 else
1992 writel(1, tx_ring->itr_register);
1993 adapter->eiac_mask |= tx_ring->ims_val;
1994 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1995
1996 /* set vector for Other Causes, e.g. link changes */
1997 vector++;
1998 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1999 if (rx_ring->itr_val)
2000 writel(1000000000 / (rx_ring->itr_val * 256),
2001 hw->hw_addr + E1000_EITR_82574(vector));
2002 else
2003 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2004
2005 /* Cause Tx interrupts on every write back */
2006 ivar |= (1 << 31);
2007
2008 ew32(IVAR, ivar);
2009
2010 /* enable MSI-X PBA support */
2011 ctrl_ext = er32(CTRL_EXT);
2012 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
2013
2014 /* Auto-Mask Other interrupts upon ICR read */
2015 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
2016 ctrl_ext |= E1000_CTRL_EXT_EIAME;
2017 ew32(CTRL_EXT, ctrl_ext);
2018 e1e_flush();
2019 }
2020
2021 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2022 {
2023 if (adapter->msix_entries) {
2024 pci_disable_msix(adapter->pdev);
2025 kfree(adapter->msix_entries);
2026 adapter->msix_entries = NULL;
2027 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2028 pci_disable_msi(adapter->pdev);
2029 adapter->flags &= ~FLAG_MSI_ENABLED;
2030 }
2031 }
2032
2033 /**
2034 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2035 *
2036 * Attempt to configure interrupts using the best available
2037 * capabilities of the hardware and kernel.
2038 **/
2039 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2040 {
2041 int err;
2042 int i;
2043
2044 switch (adapter->int_mode) {
2045 case E1000E_INT_MODE_MSIX:
2046 if (adapter->flags & FLAG_HAS_MSIX) {
2047 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2048 adapter->msix_entries = kcalloc(adapter->num_vectors,
2049 sizeof(struct msix_entry),
2050 GFP_KERNEL);
2051 if (adapter->msix_entries) {
2052 for (i = 0; i < adapter->num_vectors; i++)
2053 adapter->msix_entries[i].entry = i;
2054
2055 err = pci_enable_msix(adapter->pdev,
2056 adapter->msix_entries,
2057 adapter->num_vectors);
2058 if (err == 0)
2059 return;
2060 }
2061 /* MSI-X failed, so fall through and try MSI */
2062 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
2063 e1000e_reset_interrupt_capability(adapter);
2064 }
2065 adapter->int_mode = E1000E_INT_MODE_MSI;
2066 /* Fall through */
2067 case E1000E_INT_MODE_MSI:
2068 if (!pci_enable_msi(adapter->pdev)) {
2069 adapter->flags |= FLAG_MSI_ENABLED;
2070 } else {
2071 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2072 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
2073 }
2074 /* Fall through */
2075 case E1000E_INT_MODE_LEGACY:
2076 /* Don't do anything; this is the system default */
2077 break;
2078 }
2079
2080 /* store the number of vectors being used */
2081 adapter->num_vectors = 1;
2082 }
2083
2084 /**
2085 * e1000_request_msix - Initialize MSI-X interrupts
2086 *
2087 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2088 * kernel.
2089 **/
2090 static int e1000_request_msix(struct e1000_adapter *adapter)
2091 {
2092 struct net_device *netdev = adapter->netdev;
2093 int err = 0, vector = 0;
2094
2095 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2096 snprintf(adapter->rx_ring->name,
2097 sizeof(adapter->rx_ring->name) - 1,
2098 "%s-rx-0", netdev->name);
2099 else
2100 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2101 err = request_irq(adapter->msix_entries[vector].vector,
2102 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
2103 netdev);
2104 if (err)
2105 return err;
2106 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2107 E1000_EITR_82574(vector);
2108 adapter->rx_ring->itr_val = adapter->itr;
2109 vector++;
2110
2111 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2112 snprintf(adapter->tx_ring->name,
2113 sizeof(adapter->tx_ring->name) - 1,
2114 "%s-tx-0", netdev->name);
2115 else
2116 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2117 err = request_irq(adapter->msix_entries[vector].vector,
2118 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
2119 netdev);
2120 if (err)
2121 return err;
2122 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2123 E1000_EITR_82574(vector);
2124 adapter->tx_ring->itr_val = adapter->itr;
2125 vector++;
2126
2127 err = request_irq(adapter->msix_entries[vector].vector,
2128 e1000_msix_other, 0, netdev->name, netdev);
2129 if (err)
2130 return err;
2131
2132 e1000_configure_msix(adapter);
2133
2134 return 0;
2135 }
2136
2137 /**
2138 * e1000_request_irq - initialize interrupts
2139 *
2140 * Attempts to configure interrupts using the best available
2141 * capabilities of the hardware and kernel.
2142 **/
2143 static int e1000_request_irq(struct e1000_adapter *adapter)
2144 {
2145 struct net_device *netdev = adapter->netdev;
2146 int err;
2147
2148 if (adapter->msix_entries) {
2149 err = e1000_request_msix(adapter);
2150 if (!err)
2151 return err;
2152 /* fall back to MSI */
2153 e1000e_reset_interrupt_capability(adapter);
2154 adapter->int_mode = E1000E_INT_MODE_MSI;
2155 e1000e_set_interrupt_capability(adapter);
2156 }
2157 if (adapter->flags & FLAG_MSI_ENABLED) {
2158 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
2159 netdev->name, netdev);
2160 if (!err)
2161 return err;
2162
2163 /* fall back to legacy interrupt */
2164 e1000e_reset_interrupt_capability(adapter);
2165 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2166 }
2167
2168 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
2169 netdev->name, netdev);
2170 if (err)
2171 e_err("Unable to allocate interrupt, Error: %d\n", err);
2172
2173 return err;
2174 }
2175
2176 static void e1000_free_irq(struct e1000_adapter *adapter)
2177 {
2178 struct net_device *netdev = adapter->netdev;
2179
2180 if (adapter->msix_entries) {
2181 int vector = 0;
2182
2183 free_irq(adapter->msix_entries[vector].vector, netdev);
2184 vector++;
2185
2186 free_irq(adapter->msix_entries[vector].vector, netdev);
2187 vector++;
2188
2189 /* Other Causes interrupt vector */
2190 free_irq(adapter->msix_entries[vector].vector, netdev);
2191 return;
2192 }
2193
2194 free_irq(adapter->pdev->irq, netdev);
2195 }
2196
2197 /**
2198 * e1000_irq_disable - Mask off interrupt generation on the NIC
2199 **/
2200 static void e1000_irq_disable(struct e1000_adapter *adapter)
2201 {
2202 struct e1000_hw *hw = &adapter->hw;
2203
2204 ew32(IMC, ~0);
2205 if (adapter->msix_entries)
2206 ew32(EIAC_82574, 0);
2207 e1e_flush();
2208
2209 if (adapter->msix_entries) {
2210 int i;
2211 for (i = 0; i < adapter->num_vectors; i++)
2212 synchronize_irq(adapter->msix_entries[i].vector);
2213 } else {
2214 synchronize_irq(adapter->pdev->irq);
2215 }
2216 }
2217
2218 /**
2219 * e1000_irq_enable - Enable default interrupt generation settings
2220 **/
2221 static void e1000_irq_enable(struct e1000_adapter *adapter)
2222 {
2223 struct e1000_hw *hw = &adapter->hw;
2224
2225 if (adapter->msix_entries) {
2226 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2227 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
2228 } else if (hw->mac.type == e1000_pch_lpt) {
2229 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
2230 } else {
2231 ew32(IMS, IMS_ENABLE_MASK);
2232 }
2233 e1e_flush();
2234 }
2235
2236 /**
2237 * e1000e_get_hw_control - get control of the h/w from f/w
2238 * @adapter: address of board private structure
2239 *
2240 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2241 * For ASF and Pass Through versions of f/w this means that
2242 * the driver is loaded. For AMT version (only with 82573)
2243 * of the f/w this means that the network i/f is open.
2244 **/
2245 void e1000e_get_hw_control(struct e1000_adapter *adapter)
2246 {
2247 struct e1000_hw *hw = &adapter->hw;
2248 u32 ctrl_ext;
2249 u32 swsm;
2250
2251 /* Let firmware know the driver has taken over */
2252 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2253 swsm = er32(SWSM);
2254 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2255 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2256 ctrl_ext = er32(CTRL_EXT);
2257 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2258 }
2259 }
2260
2261 /**
2262 * e1000e_release_hw_control - release control of the h/w to f/w
2263 * @adapter: address of board private structure
2264 *
2265 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2266 * For ASF and Pass Through versions of f/w this means that the
2267 * driver is no longer loaded. For AMT version (only with 82573) i
2268 * of the f/w this means that the network i/f is closed.
2269 *
2270 **/
2271 void e1000e_release_hw_control(struct e1000_adapter *adapter)
2272 {
2273 struct e1000_hw *hw = &adapter->hw;
2274 u32 ctrl_ext;
2275 u32 swsm;
2276
2277 /* Let firmware taken over control of h/w */
2278 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2279 swsm = er32(SWSM);
2280 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2281 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2282 ctrl_ext = er32(CTRL_EXT);
2283 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2284 }
2285 }
2286
2287 /**
2288 * e1000_alloc_ring_dma - allocate memory for a ring structure
2289 **/
2290 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2291 struct e1000_ring *ring)
2292 {
2293 struct pci_dev *pdev = adapter->pdev;
2294
2295 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2296 GFP_KERNEL);
2297 if (!ring->desc)
2298 return -ENOMEM;
2299
2300 return 0;
2301 }
2302
2303 /**
2304 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2305 * @tx_ring: Tx descriptor ring
2306 *
2307 * Return 0 on success, negative on failure
2308 **/
2309 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
2310 {
2311 struct e1000_adapter *adapter = tx_ring->adapter;
2312 int err = -ENOMEM, size;
2313
2314 size = sizeof(struct e1000_buffer) * tx_ring->count;
2315 tx_ring->buffer_info = vzalloc(size);
2316 if (!tx_ring->buffer_info)
2317 goto err;
2318
2319 /* round up to nearest 4K */
2320 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2321 tx_ring->size = ALIGN(tx_ring->size, 4096);
2322
2323 err = e1000_alloc_ring_dma(adapter, tx_ring);
2324 if (err)
2325 goto err;
2326
2327 tx_ring->next_to_use = 0;
2328 tx_ring->next_to_clean = 0;
2329
2330 return 0;
2331 err:
2332 vfree(tx_ring->buffer_info);
2333 e_err("Unable to allocate memory for the transmit descriptor ring\n");
2334 return err;
2335 }
2336
2337 /**
2338 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2339 * @rx_ring: Rx descriptor ring
2340 *
2341 * Returns 0 on success, negative on failure
2342 **/
2343 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
2344 {
2345 struct e1000_adapter *adapter = rx_ring->adapter;
2346 struct e1000_buffer *buffer_info;
2347 int i, size, desc_len, err = -ENOMEM;
2348
2349 size = sizeof(struct e1000_buffer) * rx_ring->count;
2350 rx_ring->buffer_info = vzalloc(size);
2351 if (!rx_ring->buffer_info)
2352 goto err;
2353
2354 for (i = 0; i < rx_ring->count; i++) {
2355 buffer_info = &rx_ring->buffer_info[i];
2356 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2357 sizeof(struct e1000_ps_page),
2358 GFP_KERNEL);
2359 if (!buffer_info->ps_pages)
2360 goto err_pages;
2361 }
2362
2363 desc_len = sizeof(union e1000_rx_desc_packet_split);
2364
2365 /* Round up to nearest 4K */
2366 rx_ring->size = rx_ring->count * desc_len;
2367 rx_ring->size = ALIGN(rx_ring->size, 4096);
2368
2369 err = e1000_alloc_ring_dma(adapter, rx_ring);
2370 if (err)
2371 goto err_pages;
2372
2373 rx_ring->next_to_clean = 0;
2374 rx_ring->next_to_use = 0;
2375 rx_ring->rx_skb_top = NULL;
2376
2377 return 0;
2378
2379 err_pages:
2380 for (i = 0; i < rx_ring->count; i++) {
2381 buffer_info = &rx_ring->buffer_info[i];
2382 kfree(buffer_info->ps_pages);
2383 }
2384 err:
2385 vfree(rx_ring->buffer_info);
2386 e_err("Unable to allocate memory for the receive descriptor ring\n");
2387 return err;
2388 }
2389
2390 /**
2391 * e1000_clean_tx_ring - Free Tx Buffers
2392 * @tx_ring: Tx descriptor ring
2393 **/
2394 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
2395 {
2396 struct e1000_adapter *adapter = tx_ring->adapter;
2397 struct e1000_buffer *buffer_info;
2398 unsigned long size;
2399 unsigned int i;
2400
2401 for (i = 0; i < tx_ring->count; i++) {
2402 buffer_info = &tx_ring->buffer_info[i];
2403 e1000_put_txbuf(tx_ring, buffer_info);
2404 }
2405
2406 netdev_reset_queue(adapter->netdev);
2407 size = sizeof(struct e1000_buffer) * tx_ring->count;
2408 memset(tx_ring->buffer_info, 0, size);
2409
2410 memset(tx_ring->desc, 0, tx_ring->size);
2411
2412 tx_ring->next_to_use = 0;
2413 tx_ring->next_to_clean = 0;
2414
2415 writel(0, tx_ring->head);
2416 if (tx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2417 e1000e_update_tdt_wa(tx_ring, 0);
2418 else
2419 writel(0, tx_ring->tail);
2420 }
2421
2422 /**
2423 * e1000e_free_tx_resources - Free Tx Resources per Queue
2424 * @tx_ring: Tx descriptor ring
2425 *
2426 * Free all transmit software resources
2427 **/
2428 void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
2429 {
2430 struct e1000_adapter *adapter = tx_ring->adapter;
2431 struct pci_dev *pdev = adapter->pdev;
2432
2433 e1000_clean_tx_ring(tx_ring);
2434
2435 vfree(tx_ring->buffer_info);
2436 tx_ring->buffer_info = NULL;
2437
2438 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2439 tx_ring->dma);
2440 tx_ring->desc = NULL;
2441 }
2442
2443 /**
2444 * e1000e_free_rx_resources - Free Rx Resources
2445 * @rx_ring: Rx descriptor ring
2446 *
2447 * Free all receive software resources
2448 **/
2449 void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
2450 {
2451 struct e1000_adapter *adapter = rx_ring->adapter;
2452 struct pci_dev *pdev = adapter->pdev;
2453 int i;
2454
2455 e1000_clean_rx_ring(rx_ring);
2456
2457 for (i = 0; i < rx_ring->count; i++)
2458 kfree(rx_ring->buffer_info[i].ps_pages);
2459
2460 vfree(rx_ring->buffer_info);
2461 rx_ring->buffer_info = NULL;
2462
2463 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2464 rx_ring->dma);
2465 rx_ring->desc = NULL;
2466 }
2467
2468 /**
2469 * e1000_update_itr - update the dynamic ITR value based on statistics
2470 * @adapter: pointer to adapter
2471 * @itr_setting: current adapter->itr
2472 * @packets: the number of packets during this measurement interval
2473 * @bytes: the number of bytes during this measurement interval
2474 *
2475 * Stores a new ITR value based on packets and byte
2476 * counts during the last interrupt. The advantage of per interrupt
2477 * computation is faster updates and more accurate ITR for the current
2478 * traffic pattern. Constants in this function were computed
2479 * based on theoretical maximum wire speed and thresholds were set based
2480 * on testing data as well as attempting to minimize response time
2481 * while increasing bulk throughput. This functionality is controlled
2482 * by the InterruptThrottleRate module parameter.
2483 **/
2484 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
2485 {
2486 unsigned int retval = itr_setting;
2487
2488 if (packets == 0)
2489 return itr_setting;
2490
2491 switch (itr_setting) {
2492 case lowest_latency:
2493 /* handle TSO and jumbo frames */
2494 if (bytes/packets > 8000)
2495 retval = bulk_latency;
2496 else if ((packets < 5) && (bytes > 512))
2497 retval = low_latency;
2498 break;
2499 case low_latency: /* 50 usec aka 20000 ints/s */
2500 if (bytes > 10000) {
2501 /* this if handles the TSO accounting */
2502 if (bytes/packets > 8000)
2503 retval = bulk_latency;
2504 else if ((packets < 10) || ((bytes/packets) > 1200))
2505 retval = bulk_latency;
2506 else if ((packets > 35))
2507 retval = lowest_latency;
2508 } else if (bytes/packets > 2000) {
2509 retval = bulk_latency;
2510 } else if (packets <= 2 && bytes < 512) {
2511 retval = lowest_latency;
2512 }
2513 break;
2514 case bulk_latency: /* 250 usec aka 4000 ints/s */
2515 if (bytes > 25000) {
2516 if (packets > 35)
2517 retval = low_latency;
2518 } else if (bytes < 6000) {
2519 retval = low_latency;
2520 }
2521 break;
2522 }
2523
2524 return retval;
2525 }
2526
2527 static void e1000_set_itr(struct e1000_adapter *adapter)
2528 {
2529 u16 current_itr;
2530 u32 new_itr = adapter->itr;
2531
2532 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2533 if (adapter->link_speed != SPEED_1000) {
2534 current_itr = 0;
2535 new_itr = 4000;
2536 goto set_itr_now;
2537 }
2538
2539 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2540 new_itr = 0;
2541 goto set_itr_now;
2542 }
2543
2544 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2545 adapter->total_tx_packets,
2546 adapter->total_tx_bytes);
2547 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2548 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2549 adapter->tx_itr = low_latency;
2550
2551 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2552 adapter->total_rx_packets,
2553 adapter->total_rx_bytes);
2554 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2555 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2556 adapter->rx_itr = low_latency;
2557
2558 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2559
2560 switch (current_itr) {
2561 /* counts and packets in update_itr are dependent on these numbers */
2562 case lowest_latency:
2563 new_itr = 70000;
2564 break;
2565 case low_latency:
2566 new_itr = 20000; /* aka hwitr = ~200 */
2567 break;
2568 case bulk_latency:
2569 new_itr = 4000;
2570 break;
2571 default:
2572 break;
2573 }
2574
2575 set_itr_now:
2576 if (new_itr != adapter->itr) {
2577 /* this attempts to bias the interrupt rate towards Bulk
2578 * by adding intermediate steps when interrupt rate is
2579 * increasing
2580 */
2581 new_itr = new_itr > adapter->itr ?
2582 min(adapter->itr + (new_itr >> 2), new_itr) :
2583 new_itr;
2584 adapter->itr = new_itr;
2585 adapter->rx_ring->itr_val = new_itr;
2586 if (adapter->msix_entries)
2587 adapter->rx_ring->set_itr = 1;
2588 else
2589 e1000e_write_itr(adapter, new_itr);
2590 }
2591 }
2592
2593 /**
2594 * e1000e_write_itr - write the ITR value to the appropriate registers
2595 * @adapter: address of board private structure
2596 * @itr: new ITR value to program
2597 *
2598 * e1000e_write_itr determines if the adapter is in MSI-X mode
2599 * and, if so, writes the EITR registers with the ITR value.
2600 * Otherwise, it writes the ITR value into the ITR register.
2601 **/
2602 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2603 {
2604 struct e1000_hw *hw = &adapter->hw;
2605 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2606
2607 if (adapter->msix_entries) {
2608 int vector;
2609
2610 for (vector = 0; vector < adapter->num_vectors; vector++)
2611 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2612 } else {
2613 ew32(ITR, new_itr);
2614 }
2615 }
2616
2617 /**
2618 * e1000_alloc_queues - Allocate memory for all rings
2619 * @adapter: board private structure to initialize
2620 **/
2621 static int e1000_alloc_queues(struct e1000_adapter *adapter)
2622 {
2623 int size = sizeof(struct e1000_ring);
2624
2625 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
2626 if (!adapter->tx_ring)
2627 goto err;
2628 adapter->tx_ring->count = adapter->tx_ring_count;
2629 adapter->tx_ring->adapter = adapter;
2630
2631 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
2632 if (!adapter->rx_ring)
2633 goto err;
2634 adapter->rx_ring->count = adapter->rx_ring_count;
2635 adapter->rx_ring->adapter = adapter;
2636
2637 return 0;
2638 err:
2639 e_err("Unable to allocate memory for queues\n");
2640 kfree(adapter->rx_ring);
2641 kfree(adapter->tx_ring);
2642 return -ENOMEM;
2643 }
2644
2645 /**
2646 * e1000e_poll - NAPI Rx polling callback
2647 * @napi: struct associated with this polling callback
2648 * @weight: number of packets driver is allowed to process this poll
2649 **/
2650 static int e1000e_poll(struct napi_struct *napi, int weight)
2651 {
2652 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2653 napi);
2654 struct e1000_hw *hw = &adapter->hw;
2655 struct net_device *poll_dev = adapter->netdev;
2656 int tx_cleaned = 1, work_done = 0;
2657
2658 adapter = netdev_priv(poll_dev);
2659
2660 if (!adapter->msix_entries ||
2661 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2662 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
2663
2664 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
2665
2666 if (!tx_cleaned)
2667 work_done = weight;
2668
2669 /* If weight not fully consumed, exit the polling mode */
2670 if (work_done < weight) {
2671 if (adapter->itr_setting & 3)
2672 e1000_set_itr(adapter);
2673 napi_complete(napi);
2674 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2675 if (adapter->msix_entries)
2676 ew32(IMS, adapter->rx_ring->ims_val);
2677 else
2678 e1000_irq_enable(adapter);
2679 }
2680 }
2681
2682 return work_done;
2683 }
2684
2685 static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2686 {
2687 struct e1000_adapter *adapter = netdev_priv(netdev);
2688 struct e1000_hw *hw = &adapter->hw;
2689 u32 vfta, index;
2690
2691 /* don't update vlan cookie if already programmed */
2692 if ((adapter->hw.mng_cookie.status &
2693 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2694 (vid == adapter->mng_vlan_id))
2695 return 0;
2696
2697 /* add VID to filter table */
2698 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2699 index = (vid >> 5) & 0x7F;
2700 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2701 vfta |= (1 << (vid & 0x1F));
2702 hw->mac.ops.write_vfta(hw, index, vfta);
2703 }
2704
2705 set_bit(vid, adapter->active_vlans);
2706
2707 return 0;
2708 }
2709
2710 static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2711 {
2712 struct e1000_adapter *adapter = netdev_priv(netdev);
2713 struct e1000_hw *hw = &adapter->hw;
2714 u32 vfta, index;
2715
2716 if ((adapter->hw.mng_cookie.status &
2717 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2718 (vid == adapter->mng_vlan_id)) {
2719 /* release control to f/w */
2720 e1000e_release_hw_control(adapter);
2721 return 0;
2722 }
2723
2724 /* remove VID from filter table */
2725 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2726 index = (vid >> 5) & 0x7F;
2727 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2728 vfta &= ~(1 << (vid & 0x1F));
2729 hw->mac.ops.write_vfta(hw, index, vfta);
2730 }
2731
2732 clear_bit(vid, adapter->active_vlans);
2733
2734 return 0;
2735 }
2736
2737 /**
2738 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2739 * @adapter: board private structure to initialize
2740 **/
2741 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
2742 {
2743 struct net_device *netdev = adapter->netdev;
2744 struct e1000_hw *hw = &adapter->hw;
2745 u32 rctl;
2746
2747 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2748 /* disable VLAN receive filtering */
2749 rctl = er32(RCTL);
2750 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2751 ew32(RCTL, rctl);
2752
2753 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2754 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2755 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
2756 }
2757 }
2758 }
2759
2760 /**
2761 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2762 * @adapter: board private structure to initialize
2763 **/
2764 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2765 {
2766 struct e1000_hw *hw = &adapter->hw;
2767 u32 rctl;
2768
2769 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2770 /* enable VLAN receive filtering */
2771 rctl = er32(RCTL);
2772 rctl |= E1000_RCTL_VFE;
2773 rctl &= ~E1000_RCTL_CFIEN;
2774 ew32(RCTL, rctl);
2775 }
2776 }
2777
2778 /**
2779 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2780 * @adapter: board private structure to initialize
2781 **/
2782 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
2783 {
2784 struct e1000_hw *hw = &adapter->hw;
2785 u32 ctrl;
2786
2787 /* disable VLAN tag insert/strip */
2788 ctrl = er32(CTRL);
2789 ctrl &= ~E1000_CTRL_VME;
2790 ew32(CTRL, ctrl);
2791 }
2792
2793 /**
2794 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2795 * @adapter: board private structure to initialize
2796 **/
2797 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2798 {
2799 struct e1000_hw *hw = &adapter->hw;
2800 u32 ctrl;
2801
2802 /* enable VLAN tag insert/strip */
2803 ctrl = er32(CTRL);
2804 ctrl |= E1000_CTRL_VME;
2805 ew32(CTRL, ctrl);
2806 }
2807
2808 static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2809 {
2810 struct net_device *netdev = adapter->netdev;
2811 u16 vid = adapter->hw.mng_cookie.vlan_id;
2812 u16 old_vid = adapter->mng_vlan_id;
2813
2814 if (adapter->hw.mng_cookie.status &
2815 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2816 e1000_vlan_rx_add_vid(netdev, vid);
2817 adapter->mng_vlan_id = vid;
2818 }
2819
2820 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2821 e1000_vlan_rx_kill_vid(netdev, old_vid);
2822 }
2823
2824 static void e1000_restore_vlan(struct e1000_adapter *adapter)
2825 {
2826 u16 vid;
2827
2828 e1000_vlan_rx_add_vid(adapter->netdev, 0);
2829
2830 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2831 e1000_vlan_rx_add_vid(adapter->netdev, vid);
2832 }
2833
2834 static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2835 {
2836 struct e1000_hw *hw = &adapter->hw;
2837 u32 manc, manc2h, mdef, i, j;
2838
2839 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2840 return;
2841
2842 manc = er32(MANC);
2843
2844 /* enable receiving management packets to the host. this will probably
2845 * generate destination unreachable messages from the host OS, but
2846 * the packets will be handled on SMBUS
2847 */
2848 manc |= E1000_MANC_EN_MNG2HOST;
2849 manc2h = er32(MANC2H);
2850
2851 switch (hw->mac.type) {
2852 default:
2853 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2854 break;
2855 case e1000_82574:
2856 case e1000_82583:
2857 /* Check if IPMI pass-through decision filter already exists;
2858 * if so, enable it.
2859 */
2860 for (i = 0, j = 0; i < 8; i++) {
2861 mdef = er32(MDEF(i));
2862
2863 /* Ignore filters with anything other than IPMI ports */
2864 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2865 continue;
2866
2867 /* Enable this decision filter in MANC2H */
2868 if (mdef)
2869 manc2h |= (1 << i);
2870
2871 j |= mdef;
2872 }
2873
2874 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2875 break;
2876
2877 /* Create new decision filter in an empty filter */
2878 for (i = 0, j = 0; i < 8; i++)
2879 if (er32(MDEF(i)) == 0) {
2880 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2881 E1000_MDEF_PORT_664));
2882 manc2h |= (1 << 1);
2883 j++;
2884 break;
2885 }
2886
2887 if (!j)
2888 e_warn("Unable to create IPMI pass-through filter\n");
2889 break;
2890 }
2891
2892 ew32(MANC2H, manc2h);
2893 ew32(MANC, manc);
2894 }
2895
2896 /**
2897 * e1000_configure_tx - Configure Transmit Unit after Reset
2898 * @adapter: board private structure
2899 *
2900 * Configure the Tx unit of the MAC after a reset.
2901 **/
2902 static void e1000_configure_tx(struct e1000_adapter *adapter)
2903 {
2904 struct e1000_hw *hw = &adapter->hw;
2905 struct e1000_ring *tx_ring = adapter->tx_ring;
2906 u64 tdba;
2907 u32 tdlen, tarc;
2908
2909 /* Setup the HW Tx Head and Tail descriptor pointers */
2910 tdba = tx_ring->dma;
2911 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
2912 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2913 ew32(TDBAH(0), (tdba >> 32));
2914 ew32(TDLEN(0), tdlen);
2915 ew32(TDH(0), 0);
2916 ew32(TDT(0), 0);
2917 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2918 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
2919
2920 /* Set the Tx Interrupt Delay register */
2921 ew32(TIDV, adapter->tx_int_delay);
2922 /* Tx irq moderation */
2923 ew32(TADV, adapter->tx_abs_int_delay);
2924
2925 if (adapter->flags2 & FLAG2_DMA_BURST) {
2926 u32 txdctl = er32(TXDCTL(0));
2927 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2928 E1000_TXDCTL_WTHRESH);
2929 /* set up some performance related parameters to encourage the
2930 * hardware to use the bus more efficiently in bursts, depends
2931 * on the tx_int_delay to be enabled,
2932 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2933 * hthresh = 1 ==> prefetch when one or more available
2934 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2935 * BEWARE: this seems to work but should be considered first if
2936 * there are Tx hangs or other Tx related bugs
2937 */
2938 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2939 ew32(TXDCTL(0), txdctl);
2940 }
2941 /* erratum work around: set txdctl the same for both queues */
2942 ew32(TXDCTL(1), er32(TXDCTL(0)));
2943
2944 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
2945 tarc = er32(TARC(0));
2946 /* set the speed mode bit, we'll clear it if we're not at
2947 * gigabit link later
2948 */
2949 #define SPEED_MODE_BIT (1 << 21)
2950 tarc |= SPEED_MODE_BIT;
2951 ew32(TARC(0), tarc);
2952 }
2953
2954 /* errata: program both queues to unweighted RR */
2955 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
2956 tarc = er32(TARC(0));
2957 tarc |= 1;
2958 ew32(TARC(0), tarc);
2959 tarc = er32(TARC(1));
2960 tarc |= 1;
2961 ew32(TARC(1), tarc);
2962 }
2963
2964 /* Setup Transmit Descriptor Settings for eop descriptor */
2965 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2966
2967 /* only set IDE if we are delaying interrupts using the timers */
2968 if (adapter->tx_int_delay)
2969 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2970
2971 /* enable Report Status bit */
2972 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2973
2974 hw->mac.ops.config_collision_dist(hw);
2975 }
2976
2977 /**
2978 * e1000_setup_rctl - configure the receive control registers
2979 * @adapter: Board private structure
2980 **/
2981 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2982 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2983 static void e1000_setup_rctl(struct e1000_adapter *adapter)
2984 {
2985 struct e1000_hw *hw = &adapter->hw;
2986 u32 rctl, rfctl;
2987 u32 pages = 0;
2988
2989 /* Workaround Si errata on PCHx - configure jumbo frame flow */
2990 if (hw->mac.type >= e1000_pch2lan) {
2991 s32 ret_val;
2992
2993 if (adapter->netdev->mtu > ETH_DATA_LEN)
2994 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
2995 else
2996 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
2997
2998 if (ret_val)
2999 e_dbg("failed to enable jumbo frame workaround mode\n");
3000 }
3001
3002 /* Program MC offset vector base */
3003 rctl = er32(RCTL);
3004 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3005 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3006 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3007 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3008
3009 /* Do not Store bad packets */
3010 rctl &= ~E1000_RCTL_SBP;
3011
3012 /* Enable Long Packet receive */
3013 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3014 rctl &= ~E1000_RCTL_LPE;
3015 else
3016 rctl |= E1000_RCTL_LPE;
3017
3018 /* Some systems expect that the CRC is included in SMBUS traffic. The
3019 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3020 * host memory when this is enabled
3021 */
3022 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3023 rctl |= E1000_RCTL_SECRC;
3024
3025 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3026 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3027 u16 phy_data;
3028
3029 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3030 phy_data &= 0xfff8;
3031 phy_data |= (1 << 2);
3032 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3033
3034 e1e_rphy(hw, 22, &phy_data);
3035 phy_data &= 0x0fff;
3036 phy_data |= (1 << 14);
3037 e1e_wphy(hw, 0x10, 0x2823);
3038 e1e_wphy(hw, 0x11, 0x0003);
3039 e1e_wphy(hw, 22, phy_data);
3040 }
3041
3042 /* Setup buffer sizes */
3043 rctl &= ~E1000_RCTL_SZ_4096;
3044 rctl |= E1000_RCTL_BSEX;
3045 switch (adapter->rx_buffer_len) {
3046 case 2048:
3047 default:
3048 rctl |= E1000_RCTL_SZ_2048;
3049 rctl &= ~E1000_RCTL_BSEX;
3050 break;
3051 case 4096:
3052 rctl |= E1000_RCTL_SZ_4096;
3053 break;
3054 case 8192:
3055 rctl |= E1000_RCTL_SZ_8192;
3056 break;
3057 case 16384:
3058 rctl |= E1000_RCTL_SZ_16384;
3059 break;
3060 }
3061
3062 /* Enable Extended Status in all Receive Descriptors */
3063 rfctl = er32(RFCTL);
3064 rfctl |= E1000_RFCTL_EXTEN;
3065 ew32(RFCTL, rfctl);
3066
3067 /* 82571 and greater support packet-split where the protocol
3068 * header is placed in skb->data and the packet data is
3069 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3070 * In the case of a non-split, skb->data is linearly filled,
3071 * followed by the page buffers. Therefore, skb->data is
3072 * sized to hold the largest protocol header.
3073 *
3074 * allocations using alloc_page take too long for regular MTU
3075 * so only enable packet split for jumbo frames
3076 *
3077 * Using pages when the page size is greater than 16k wastes
3078 * a lot of memory, since we allocate 3 pages at all times
3079 * per packet.
3080 */
3081 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
3082 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
3083 adapter->rx_ps_pages = pages;
3084 else
3085 adapter->rx_ps_pages = 0;
3086
3087 if (adapter->rx_ps_pages) {
3088 u32 psrctl = 0;
3089
3090 /* Enable Packet split descriptors */
3091 rctl |= E1000_RCTL_DTYP_PS;
3092
3093 psrctl |= adapter->rx_ps_bsize0 >>
3094 E1000_PSRCTL_BSIZE0_SHIFT;
3095
3096 switch (adapter->rx_ps_pages) {
3097 case 3:
3098 psrctl |= PAGE_SIZE <<
3099 E1000_PSRCTL_BSIZE3_SHIFT;
3100 case 2:
3101 psrctl |= PAGE_SIZE <<
3102 E1000_PSRCTL_BSIZE2_SHIFT;
3103 case 1:
3104 psrctl |= PAGE_SIZE >>
3105 E1000_PSRCTL_BSIZE1_SHIFT;
3106 break;
3107 }
3108
3109 ew32(PSRCTL, psrctl);
3110 }
3111
3112 /* This is useful for sniffing bad packets. */
3113 if (adapter->netdev->features & NETIF_F_RXALL) {
3114 /* UPE and MPE will be handled by normal PROMISC logic
3115 * in e1000e_set_rx_mode
3116 */
3117 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3118 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3119 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3120
3121 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3122 E1000_RCTL_DPF | /* Allow filtered pause */
3123 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3124 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3125 * and that breaks VLANs.
3126 */
3127 }
3128
3129 ew32(RCTL, rctl);
3130 /* just started the receive unit, no need to restart */
3131 adapter->flags &= ~FLAG_RESTART_NOW;
3132 }
3133
3134 /**
3135 * e1000_configure_rx - Configure Receive Unit after Reset
3136 * @adapter: board private structure
3137 *
3138 * Configure the Rx unit of the MAC after a reset.
3139 **/
3140 static void e1000_configure_rx(struct e1000_adapter *adapter)
3141 {
3142 struct e1000_hw *hw = &adapter->hw;
3143 struct e1000_ring *rx_ring = adapter->rx_ring;
3144 u64 rdba;
3145 u32 rdlen, rctl, rxcsum, ctrl_ext;
3146
3147 if (adapter->rx_ps_pages) {
3148 /* this is a 32 byte descriptor */
3149 rdlen = rx_ring->count *
3150 sizeof(union e1000_rx_desc_packet_split);
3151 adapter->clean_rx = e1000_clean_rx_irq_ps;
3152 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
3153 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
3154 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3155 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3156 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
3157 } else {
3158 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3159 adapter->clean_rx = e1000_clean_rx_irq;
3160 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3161 }
3162
3163 /* disable receives while setting up the descriptors */
3164 rctl = er32(RCTL);
3165 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3166 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3167 e1e_flush();
3168 usleep_range(10000, 20000);
3169
3170 if (adapter->flags2 & FLAG2_DMA_BURST) {
3171 /* set the writeback threshold (only takes effect if the RDTR
3172 * is set). set GRAN=1 and write back up to 0x4 worth, and
3173 * enable prefetching of 0x20 Rx descriptors
3174 * granularity = 01
3175 * wthresh = 04,
3176 * hthresh = 04,
3177 * pthresh = 0x20
3178 */
3179 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3180 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3181
3182 /* override the delay timers for enabling bursting, only if
3183 * the value was not set by the user via module options
3184 */
3185 if (adapter->rx_int_delay == DEFAULT_RDTR)
3186 adapter->rx_int_delay = BURST_RDTR;
3187 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3188 adapter->rx_abs_int_delay = BURST_RADV;
3189 }
3190
3191 /* set the Receive Delay Timer Register */
3192 ew32(RDTR, adapter->rx_int_delay);
3193
3194 /* irq moderation */
3195 ew32(RADV, adapter->rx_abs_int_delay);
3196 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
3197 e1000e_write_itr(adapter, adapter->itr);
3198
3199 ctrl_ext = er32(CTRL_EXT);
3200 /* Auto-Mask interrupts upon ICR access */
3201 ctrl_ext |= E1000_CTRL_EXT_IAME;
3202 ew32(IAM, 0xffffffff);
3203 ew32(CTRL_EXT, ctrl_ext);
3204 e1e_flush();
3205
3206 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3207 * the Base and Length of the Rx Descriptor Ring
3208 */
3209 rdba = rx_ring->dma;
3210 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3211 ew32(RDBAH(0), (rdba >> 32));
3212 ew32(RDLEN(0), rdlen);
3213 ew32(RDH(0), 0);
3214 ew32(RDT(0), 0);
3215 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3216 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
3217
3218 /* Enable Receive Checksum Offload for TCP and UDP */
3219 rxcsum = er32(RXCSUM);
3220 if (adapter->netdev->features & NETIF_F_RXCSUM)
3221 rxcsum |= E1000_RXCSUM_TUOFL;
3222 else
3223 rxcsum &= ~E1000_RXCSUM_TUOFL;
3224 ew32(RXCSUM, rxcsum);
3225
3226 /* With jumbo frames, excessive C-state transition latencies result
3227 * in dropped transactions.
3228 */
3229 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3230 u32 lat =
3231 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3232 adapter->max_frame_size) * 8 / 1000;
3233
3234 if (adapter->flags & FLAG_IS_ICH) {
3235 u32 rxdctl = er32(RXDCTL(0));
3236 ew32(RXDCTL(0), rxdctl | 0x3);
3237 }
3238
3239 pm_qos_update_request(&adapter->netdev->pm_qos_req, lat);
3240 } else {
3241 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3242 PM_QOS_DEFAULT_VALUE);
3243 }
3244
3245 /* Enable Receives */
3246 ew32(RCTL, rctl);
3247 }
3248
3249 /**
3250 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3251 * @netdev: network interface device structure
3252 *
3253 * Writes multicast address list to the MTA hash table.
3254 * Returns: -ENOMEM on failure
3255 * 0 on no addresses written
3256 * X on writing X addresses to MTA
3257 */
3258 static int e1000e_write_mc_addr_list(struct net_device *netdev)
3259 {
3260 struct e1000_adapter *adapter = netdev_priv(netdev);
3261 struct e1000_hw *hw = &adapter->hw;
3262 struct netdev_hw_addr *ha;
3263 u8 *mta_list;
3264 int i;
3265
3266 if (netdev_mc_empty(netdev)) {
3267 /* nothing to program, so clear mc list */
3268 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3269 return 0;
3270 }
3271
3272 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3273 if (!mta_list)
3274 return -ENOMEM;
3275
3276 /* update_mc_addr_list expects a packed array of only addresses. */
3277 i = 0;
3278 netdev_for_each_mc_addr(ha, netdev)
3279 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3280
3281 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3282 kfree(mta_list);
3283
3284 return netdev_mc_count(netdev);
3285 }
3286
3287 /**
3288 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3289 * @netdev: network interface device structure
3290 *
3291 * Writes unicast address list to the RAR table.
3292 * Returns: -ENOMEM on failure/insufficient address space
3293 * 0 on no addresses written
3294 * X on writing X addresses to the RAR table
3295 **/
3296 static int e1000e_write_uc_addr_list(struct net_device *netdev)
3297 {
3298 struct e1000_adapter *adapter = netdev_priv(netdev);
3299 struct e1000_hw *hw = &adapter->hw;
3300 unsigned int rar_entries = hw->mac.rar_entry_count;
3301 int count = 0;
3302
3303 /* save a rar entry for our hardware address */
3304 rar_entries--;
3305
3306 /* save a rar entry for the LAA workaround */
3307 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3308 rar_entries--;
3309
3310 /* return ENOMEM indicating insufficient memory for addresses */
3311 if (netdev_uc_count(netdev) > rar_entries)
3312 return -ENOMEM;
3313
3314 if (!netdev_uc_empty(netdev) && rar_entries) {
3315 struct netdev_hw_addr *ha;
3316
3317 /* write the addresses in reverse order to avoid write
3318 * combining
3319 */
3320 netdev_for_each_uc_addr(ha, netdev) {
3321 if (!rar_entries)
3322 break;
3323 hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3324 count++;
3325 }
3326 }
3327
3328 /* zero out the remaining RAR entries not used above */
3329 for (; rar_entries > 0; rar_entries--) {
3330 ew32(RAH(rar_entries), 0);
3331 ew32(RAL(rar_entries), 0);
3332 }
3333 e1e_flush();
3334
3335 return count;
3336 }
3337
3338 /**
3339 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3340 * @netdev: network interface device structure
3341 *
3342 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3343 * address list or the network interface flags are updated. This routine is
3344 * responsible for configuring the hardware for proper unicast, multicast,
3345 * promiscuous mode, and all-multi behavior.
3346 **/
3347 static void e1000e_set_rx_mode(struct net_device *netdev)
3348 {
3349 struct e1000_adapter *adapter = netdev_priv(netdev);
3350 struct e1000_hw *hw = &adapter->hw;
3351 u32 rctl;
3352
3353 /* Check for Promiscuous and All Multicast modes */
3354 rctl = er32(RCTL);
3355
3356 /* clear the affected bits */
3357 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3358
3359 if (netdev->flags & IFF_PROMISC) {
3360 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3361 /* Do not hardware filter VLANs in promisc mode */
3362 e1000e_vlan_filter_disable(adapter);
3363 } else {
3364 int count;
3365
3366 if (netdev->flags & IFF_ALLMULTI) {
3367 rctl |= E1000_RCTL_MPE;
3368 } else {
3369 /* Write addresses to the MTA, if the attempt fails
3370 * then we should just turn on promiscuous mode so
3371 * that we can at least receive multicast traffic
3372 */
3373 count = e1000e_write_mc_addr_list(netdev);
3374 if (count < 0)
3375 rctl |= E1000_RCTL_MPE;
3376 }
3377 e1000e_vlan_filter_enable(adapter);
3378 /* Write addresses to available RAR registers, if there is not
3379 * sufficient space to store all the addresses then enable
3380 * unicast promiscuous mode
3381 */
3382 count = e1000e_write_uc_addr_list(netdev);
3383 if (count < 0)
3384 rctl |= E1000_RCTL_UPE;
3385 }
3386
3387 ew32(RCTL, rctl);
3388
3389 if (netdev->features & NETIF_F_HW_VLAN_RX)
3390 e1000e_vlan_strip_enable(adapter);
3391 else
3392 e1000e_vlan_strip_disable(adapter);
3393 }
3394
3395 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3396 {
3397 struct e1000_hw *hw = &adapter->hw;
3398 u32 mrqc, rxcsum;
3399 int i;
3400 static const u32 rsskey[10] = {
3401 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3402 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3403 };
3404
3405 /* Fill out hash function seed */
3406 for (i = 0; i < 10; i++)
3407 ew32(RSSRK(i), rsskey[i]);
3408
3409 /* Direct all traffic to queue 0 */
3410 for (i = 0; i < 32; i++)
3411 ew32(RETA(i), 0);
3412
3413 /* Disable raw packet checksumming so that RSS hash is placed in
3414 * descriptor on writeback.
3415 */
3416 rxcsum = er32(RXCSUM);
3417 rxcsum |= E1000_RXCSUM_PCSD;
3418
3419 ew32(RXCSUM, rxcsum);
3420
3421 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3422 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3423 E1000_MRQC_RSS_FIELD_IPV6 |
3424 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3425 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3426
3427 ew32(MRQC, mrqc);
3428 }
3429
3430 /**
3431 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3432 * @adapter: board private structure
3433 * @timinca: pointer to returned time increment attributes
3434 *
3435 * Get attributes for incrementing the System Time Register SYSTIML/H at
3436 * the default base frequency, and set the cyclecounter shift value.
3437 **/
3438 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3439 {
3440 struct e1000_hw *hw = &adapter->hw;
3441 u32 incvalue, incperiod, shift;
3442
3443 /* Make sure clock is enabled on I217 before checking the frequency */
3444 if ((hw->mac.type == e1000_pch_lpt) &&
3445 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3446 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3447 u32 fextnvm7 = er32(FEXTNVM7);
3448
3449 if (!(fextnvm7 & (1 << 0))) {
3450 ew32(FEXTNVM7, fextnvm7 | (1 << 0));
3451 e1e_flush();
3452 }
3453 }
3454
3455 switch (hw->mac.type) {
3456 case e1000_pch2lan:
3457 case e1000_pch_lpt:
3458 /* On I217, the clock frequency is 25MHz or 96MHz as
3459 * indicated by the System Clock Frequency Indication
3460 */
3461 if ((hw->mac.type != e1000_pch_lpt) ||
3462 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
3463 /* Stable 96MHz frequency */
3464 incperiod = INCPERIOD_96MHz;
3465 incvalue = INCVALUE_96MHz;
3466 shift = INCVALUE_SHIFT_96MHz;
3467 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz;
3468 break;
3469 }
3470 /* fall-through */
3471 case e1000_82574:
3472 case e1000_82583:
3473 /* Stable 25MHz frequency */
3474 incperiod = INCPERIOD_25MHz;
3475 incvalue = INCVALUE_25MHz;
3476 shift = INCVALUE_SHIFT_25MHz;
3477 adapter->cc.shift = shift;
3478 break;
3479 default:
3480 return -EINVAL;
3481 }
3482
3483 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3484 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3485
3486 return 0;
3487 }
3488
3489 /**
3490 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3491 * @adapter: board private structure
3492 *
3493 * Outgoing time stamping can be enabled and disabled. Play nice and
3494 * disable it when requested, although it shouldn't cause any overhead
3495 * when no packet needs it. At most one packet in the queue may be
3496 * marked for time stamping, otherwise it would be impossible to tell
3497 * for sure to which packet the hardware time stamp belongs.
3498 *
3499 * Incoming time stamping has to be configured via the hardware filters.
3500 * Not all combinations are supported, in particular event type has to be
3501 * specified. Matching the kind of event packet is not supported, with the
3502 * exception of "all V2 events regardless of level 2 or 4".
3503 **/
3504 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter)
3505 {
3506 struct e1000_hw *hw = &adapter->hw;
3507 struct hwtstamp_config *config = &adapter->hwtstamp_config;
3508 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3509 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
3510 u32 rxmtrl = 0;
3511 u16 rxudp = 0;
3512 bool is_l4 = false;
3513 bool is_l2 = false;
3514 u32 regval;
3515 s32 ret_val;
3516
3517 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3518 return -EINVAL;
3519
3520 /* flags reserved for future extensions - must be zero */
3521 if (config->flags)
3522 return -EINVAL;
3523
3524 switch (config->tx_type) {
3525 case HWTSTAMP_TX_OFF:
3526 tsync_tx_ctl = 0;
3527 break;
3528 case HWTSTAMP_TX_ON:
3529 break;
3530 default:
3531 return -ERANGE;
3532 }
3533
3534 switch (config->rx_filter) {
3535 case HWTSTAMP_FILTER_NONE:
3536 tsync_rx_ctl = 0;
3537 break;
3538 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3539 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3540 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3541 is_l4 = true;
3542 break;
3543 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3544 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3545 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3546 is_l4 = true;
3547 break;
3548 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3549 /* Also time stamps V2 L2 Path Delay Request/Response */
3550 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3551 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3552 is_l2 = true;
3553 break;
3554 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3555 /* Also time stamps V2 L2 Path Delay Request/Response. */
3556 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3557 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3558 is_l2 = true;
3559 break;
3560 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3561 /* Hardware cannot filter just V2 L4 Sync messages;
3562 * fall-through to V2 (both L2 and L4) Sync.
3563 */
3564 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3565 /* Also time stamps V2 Path Delay Request/Response. */
3566 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3567 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3568 is_l2 = true;
3569 is_l4 = true;
3570 break;
3571 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3572 /* Hardware cannot filter just V2 L4 Delay Request messages;
3573 * fall-through to V2 (both L2 and L4) Delay Request.
3574 */
3575 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3576 /* Also time stamps V2 Path Delay Request/Response. */
3577 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3578 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3579 is_l2 = true;
3580 is_l4 = true;
3581 break;
3582 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3583 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3584 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3585 * fall-through to all V2 (both L2 and L4) Events.
3586 */
3587 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3588 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3589 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3590 is_l2 = true;
3591 is_l4 = true;
3592 break;
3593 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3594 /* For V1, the hardware can only filter Sync messages or
3595 * Delay Request messages but not both so fall-through to
3596 * time stamp all packets.
3597 */
3598 case HWTSTAMP_FILTER_ALL:
3599 is_l2 = true;
3600 is_l4 = true;
3601 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3602 config->rx_filter = HWTSTAMP_FILTER_ALL;
3603 break;
3604 default:
3605 return -ERANGE;
3606 }
3607
3608 /* enable/disable Tx h/w time stamping */
3609 regval = er32(TSYNCTXCTL);
3610 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3611 regval |= tsync_tx_ctl;
3612 ew32(TSYNCTXCTL, regval);
3613 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3614 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3615 e_err("Timesync Tx Control register not set as expected\n");
3616 return -EAGAIN;
3617 }
3618
3619 /* enable/disable Rx h/w time stamping */
3620 regval = er32(TSYNCRXCTL);
3621 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3622 regval |= tsync_rx_ctl;
3623 ew32(TSYNCRXCTL, regval);
3624 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3625 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3626 (regval & (E1000_TSYNCRXCTL_ENABLED |
3627 E1000_TSYNCRXCTL_TYPE_MASK))) {
3628 e_err("Timesync Rx Control register not set as expected\n");
3629 return -EAGAIN;
3630 }
3631
3632 /* L2: define ethertype filter for time stamped packets */
3633 if (is_l2)
3634 rxmtrl |= ETH_P_1588;
3635
3636 /* define which PTP packets get time stamped */
3637 ew32(RXMTRL, rxmtrl);
3638
3639 /* Filter by destination port */
3640 if (is_l4) {
3641 rxudp = PTP_EV_PORT;
3642 cpu_to_be16s(&rxudp);
3643 }
3644 ew32(RXUDP, rxudp);
3645
3646 e1e_flush();
3647
3648 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3649 er32(RXSTMPH);
3650 er32(TXSTMPH);
3651
3652 /* Get and set the System Time Register SYSTIM base frequency */
3653 ret_val = e1000e_get_base_timinca(adapter, &regval);
3654 if (ret_val)
3655 return ret_val;
3656 ew32(TIMINCA, regval);
3657
3658 /* reset the ns time counter */
3659 timecounter_init(&adapter->tc, &adapter->cc,
3660 ktime_to_ns(ktime_get_real()));
3661
3662 return 0;
3663 }
3664
3665 /**
3666 * e1000_configure - configure the hardware for Rx and Tx
3667 * @adapter: private board structure
3668 **/
3669 static void e1000_configure(struct e1000_adapter *adapter)
3670 {
3671 struct e1000_ring *rx_ring = adapter->rx_ring;
3672
3673 e1000e_set_rx_mode(adapter->netdev);
3674
3675 e1000_restore_vlan(adapter);
3676 e1000_init_manageability_pt(adapter);
3677
3678 e1000_configure_tx(adapter);
3679
3680 if (adapter->netdev->features & NETIF_F_RXHASH)
3681 e1000e_setup_rss_hash(adapter);
3682 e1000_setup_rctl(adapter);
3683 e1000_configure_rx(adapter);
3684 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
3685 }
3686
3687 /**
3688 * e1000e_power_up_phy - restore link in case the phy was powered down
3689 * @adapter: address of board private structure
3690 *
3691 * The phy may be powered down to save power and turn off link when the
3692 * driver is unloaded and wake on lan is not enabled (among others)
3693 * *** this routine MUST be followed by a call to e1000e_reset ***
3694 **/
3695 void e1000e_power_up_phy(struct e1000_adapter *adapter)
3696 {
3697 if (adapter->hw.phy.ops.power_up)
3698 adapter->hw.phy.ops.power_up(&adapter->hw);
3699
3700 adapter->hw.mac.ops.setup_link(&adapter->hw);
3701 }
3702
3703 /**
3704 * e1000_power_down_phy - Power down the PHY
3705 *
3706 * Power down the PHY so no link is implied when interface is down.
3707 * The PHY cannot be powered down if management or WoL is active.
3708 */
3709 static void e1000_power_down_phy(struct e1000_adapter *adapter)
3710 {
3711 /* WoL is enabled */
3712 if (adapter->wol)
3713 return;
3714
3715 if (adapter->hw.phy.ops.power_down)
3716 adapter->hw.phy.ops.power_down(&adapter->hw);
3717 }
3718
3719 /**
3720 * e1000e_reset - bring the hardware into a known good state
3721 *
3722 * This function boots the hardware and enables some settings that
3723 * require a configuration cycle of the hardware - those cannot be
3724 * set/changed during runtime. After reset the device needs to be
3725 * properly configured for Rx, Tx etc.
3726 */
3727 void e1000e_reset(struct e1000_adapter *adapter)
3728 {
3729 struct e1000_mac_info *mac = &adapter->hw.mac;
3730 struct e1000_fc_info *fc = &adapter->hw.fc;
3731 struct e1000_hw *hw = &adapter->hw;
3732 u32 tx_space, min_tx_space, min_rx_space;
3733 u32 pba = adapter->pba;
3734 u16 hwm;
3735
3736 /* reset Packet Buffer Allocation to default */
3737 ew32(PBA, pba);
3738
3739 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
3740 /* To maintain wire speed transmits, the Tx FIFO should be
3741 * large enough to accommodate two full transmit packets,
3742 * rounded up to the next 1KB and expressed in KB. Likewise,
3743 * the Rx FIFO should be large enough to accommodate at least
3744 * one full receive packet and is similarly rounded up and
3745 * expressed in KB.
3746 */
3747 pba = er32(PBA);
3748 /* upper 16 bits has Tx packet buffer allocation size in KB */
3749 tx_space = pba >> 16;
3750 /* lower 16 bits has Rx packet buffer allocation size in KB */
3751 pba &= 0xffff;
3752 /* the Tx fifo also stores 16 bytes of information about the Tx
3753 * but don't include ethernet FCS because hardware appends it
3754 */
3755 min_tx_space = (adapter->max_frame_size +
3756 sizeof(struct e1000_tx_desc) -
3757 ETH_FCS_LEN) * 2;
3758 min_tx_space = ALIGN(min_tx_space, 1024);
3759 min_tx_space >>= 10;
3760 /* software strips receive CRC, so leave room for it */
3761 min_rx_space = adapter->max_frame_size;
3762 min_rx_space = ALIGN(min_rx_space, 1024);
3763 min_rx_space >>= 10;
3764
3765 /* If current Tx allocation is less than the min Tx FIFO size,
3766 * and the min Tx FIFO size is less than the current Rx FIFO
3767 * allocation, take space away from current Rx allocation
3768 */
3769 if ((tx_space < min_tx_space) &&
3770 ((min_tx_space - tx_space) < pba)) {
3771 pba -= min_tx_space - tx_space;
3772
3773 /* if short on Rx space, Rx wins and must trump Tx
3774 * adjustment
3775 */
3776 if (pba < min_rx_space)
3777 pba = min_rx_space;
3778 }
3779
3780 ew32(PBA, pba);
3781 }
3782
3783 /* flow control settings
3784 *
3785 * The high water mark must be low enough to fit one full frame
3786 * (or the size used for early receive) above it in the Rx FIFO.
3787 * Set it to the lower of:
3788 * - 90% of the Rx FIFO size, and
3789 * - the full Rx FIFO size minus one full frame
3790 */
3791 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3792 fc->pause_time = 0xFFFF;
3793 else
3794 fc->pause_time = E1000_FC_PAUSE_TIME;
3795 fc->send_xon = true;
3796 fc->current_mode = fc->requested_mode;
3797
3798 switch (hw->mac.type) {
3799 case e1000_ich9lan:
3800 case e1000_ich10lan:
3801 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3802 pba = 14;
3803 ew32(PBA, pba);
3804 fc->high_water = 0x2800;
3805 fc->low_water = fc->high_water - 8;
3806 break;
3807 }
3808 /* fall-through */
3809 default:
3810 hwm = min(((pba << 10) * 9 / 10),
3811 ((pba << 10) - adapter->max_frame_size));
3812
3813 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3814 fc->low_water = fc->high_water - 8;
3815 break;
3816 case e1000_pchlan:
3817 /* Workaround PCH LOM adapter hangs with certain network
3818 * loads. If hangs persist, try disabling Tx flow control.
3819 */
3820 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3821 fc->high_water = 0x3500;
3822 fc->low_water = 0x1500;
3823 } else {
3824 fc->high_water = 0x5000;
3825 fc->low_water = 0x3000;
3826 }
3827 fc->refresh_time = 0x1000;
3828 break;
3829 case e1000_pch2lan:
3830 case e1000_pch_lpt:
3831 fc->refresh_time = 0x0400;
3832
3833 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
3834 fc->high_water = 0x05C20;
3835 fc->low_water = 0x05048;
3836 fc->pause_time = 0x0650;
3837 break;
3838 }
3839
3840 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
3841 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
3842 break;
3843 }
3844
3845 /* Alignment of Tx data is on an arbitrary byte boundary with the
3846 * maximum size per Tx descriptor limited only to the transmit
3847 * allocation of the packet buffer minus 96 bytes with an upper
3848 * limit of 24KB due to receive synchronization limitations.
3849 */
3850 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
3851 24 << 10);
3852
3853 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
3854 * fit in receive buffer.
3855 */
3856 if (adapter->itr_setting & 0x3) {
3857 if ((adapter->max_frame_size * 2) > (pba << 10)) {
3858 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3859 dev_info(&adapter->pdev->dev,
3860 "Interrupt Throttle Rate turned off\n");
3861 adapter->flags2 |= FLAG2_DISABLE_AIM;
3862 e1000e_write_itr(adapter, 0);
3863 }
3864 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3865 dev_info(&adapter->pdev->dev,
3866 "Interrupt Throttle Rate turned on\n");
3867 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3868 adapter->itr = 20000;
3869 e1000e_write_itr(adapter, adapter->itr);
3870 }
3871 }
3872
3873 /* Allow time for pending master requests to run */
3874 mac->ops.reset_hw(hw);
3875
3876 /* For parts with AMT enabled, let the firmware know
3877 * that the network interface is in control
3878 */
3879 if (adapter->flags & FLAG_HAS_AMT)
3880 e1000e_get_hw_control(adapter);
3881
3882 ew32(WUC, 0);
3883
3884 if (mac->ops.init_hw(hw))
3885 e_err("Hardware Error\n");
3886
3887 e1000_update_mng_vlan(adapter);
3888
3889 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3890 ew32(VET, ETH_P_8021Q);
3891
3892 e1000e_reset_adaptive(hw);
3893
3894 /* initialize systim and reset the ns time counter */
3895 e1000e_config_hwtstamp(adapter);
3896
3897 if (!netif_running(adapter->netdev) &&
3898 !test_bit(__E1000_TESTING, &adapter->state)) {
3899 e1000_power_down_phy(adapter);
3900 return;
3901 }
3902
3903 e1000_get_phy_info(hw);
3904
3905 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3906 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
3907 u16 phy_data = 0;
3908 /* speed up time to link by disabling smart power down, ignore
3909 * the return value of this function because there is nothing
3910 * different we would do if it failed
3911 */
3912 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3913 phy_data &= ~IGP02E1000_PM_SPD;
3914 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3915 }
3916 }
3917
3918 int e1000e_up(struct e1000_adapter *adapter)
3919 {
3920 struct e1000_hw *hw = &adapter->hw;
3921
3922 /* hardware has been reset, we need to reload some things */
3923 e1000_configure(adapter);
3924
3925 clear_bit(__E1000_DOWN, &adapter->state);
3926
3927 if (adapter->msix_entries)
3928 e1000_configure_msix(adapter);
3929 e1000_irq_enable(adapter);
3930
3931 netif_start_queue(adapter->netdev);
3932
3933 /* fire a link change interrupt to start the watchdog */
3934 if (adapter->msix_entries)
3935 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3936 else
3937 ew32(ICS, E1000_ICS_LSC);
3938
3939 return 0;
3940 }
3941
3942 static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3943 {
3944 struct e1000_hw *hw = &adapter->hw;
3945
3946 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3947 return;
3948
3949 /* flush pending descriptor writebacks to memory */
3950 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3951 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3952
3953 /* execute the writes immediately */
3954 e1e_flush();
3955
3956 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
3957 * write is successful
3958 */
3959 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3960 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3961
3962 /* execute the writes immediately */
3963 e1e_flush();
3964 }
3965
3966 static void e1000e_update_stats(struct e1000_adapter *adapter);
3967
3968 void e1000e_down(struct e1000_adapter *adapter)
3969 {
3970 struct net_device *netdev = adapter->netdev;
3971 struct e1000_hw *hw = &adapter->hw;
3972 u32 tctl, rctl;
3973
3974 /* signal that we're down so the interrupt handler does not
3975 * reschedule our watchdog timer
3976 */
3977 set_bit(__E1000_DOWN, &adapter->state);
3978
3979 /* disable receives in the hardware */
3980 rctl = er32(RCTL);
3981 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3982 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3983 /* flush and sleep below */
3984
3985 netif_stop_queue(netdev);
3986
3987 /* disable transmits in the hardware */
3988 tctl = er32(TCTL);
3989 tctl &= ~E1000_TCTL_EN;
3990 ew32(TCTL, tctl);
3991
3992 /* flush both disables and wait for them to finish */
3993 e1e_flush();
3994 usleep_range(10000, 20000);
3995
3996 e1000_irq_disable(adapter);
3997
3998 del_timer_sync(&adapter->watchdog_timer);
3999 del_timer_sync(&adapter->phy_info_timer);
4000
4001 netif_carrier_off(netdev);
4002
4003 spin_lock(&adapter->stats64_lock);
4004 e1000e_update_stats(adapter);
4005 spin_unlock(&adapter->stats64_lock);
4006
4007 e1000e_flush_descriptors(adapter);
4008 e1000_clean_tx_ring(adapter->tx_ring);
4009 e1000_clean_rx_ring(adapter->rx_ring);
4010
4011 adapter->link_speed = 0;
4012 adapter->link_duplex = 0;
4013
4014 if (!pci_channel_offline(adapter->pdev))
4015 e1000e_reset(adapter);
4016
4017 /* TODO: for power management, we could drop the link and
4018 * pci_disable_device here.
4019 */
4020 }
4021
4022 void e1000e_reinit_locked(struct e1000_adapter *adapter)
4023 {
4024 might_sleep();
4025 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4026 usleep_range(1000, 2000);
4027 e1000e_down(adapter);
4028 e1000e_up(adapter);
4029 clear_bit(__E1000_RESETTING, &adapter->state);
4030 }
4031
4032 /**
4033 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4034 * @cc: cyclecounter structure
4035 **/
4036 static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
4037 {
4038 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4039 cc);
4040 struct e1000_hw *hw = &adapter->hw;
4041 cycle_t systim;
4042
4043 /* latch SYSTIMH on read of SYSTIML */
4044 systim = (cycle_t)er32(SYSTIML);
4045 systim |= (cycle_t)er32(SYSTIMH) << 32;
4046
4047 return systim;
4048 }
4049
4050 /**
4051 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4052 * @adapter: board private structure to initialize
4053 *
4054 * e1000_sw_init initializes the Adapter private data structure.
4055 * Fields are initialized based on PCI device information and
4056 * OS network device settings (MTU size).
4057 **/
4058 static int e1000_sw_init(struct e1000_adapter *adapter)
4059 {
4060 struct net_device *netdev = adapter->netdev;
4061
4062 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
4063 adapter->rx_ps_bsize0 = 128;
4064 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4065 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4066 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4067 adapter->rx_ring_count = E1000_DEFAULT_RXD;
4068
4069 spin_lock_init(&adapter->stats64_lock);
4070
4071 e1000e_set_interrupt_capability(adapter);
4072
4073 if (e1000_alloc_queues(adapter))
4074 return -ENOMEM;
4075
4076 /* Setup hardware time stamping cyclecounter */
4077 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4078 adapter->cc.read = e1000e_cyclecounter_read;
4079 adapter->cc.mask = CLOCKSOURCE_MASK(64);
4080 adapter->cc.mult = 1;
4081 /* cc.shift set in e1000e_get_base_tininca() */
4082
4083 spin_lock_init(&adapter->systim_lock);
4084 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4085 }
4086
4087 /* Explicitly disable IRQ since the NIC can be in any state. */
4088 e1000_irq_disable(adapter);
4089
4090 set_bit(__E1000_DOWN, &adapter->state);
4091 return 0;
4092 }
4093
4094 /**
4095 * e1000_intr_msi_test - Interrupt Handler
4096 * @irq: interrupt number
4097 * @data: pointer to a network interface device structure
4098 **/
4099 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
4100 {
4101 struct net_device *netdev = data;
4102 struct e1000_adapter *adapter = netdev_priv(netdev);
4103 struct e1000_hw *hw = &adapter->hw;
4104 u32 icr = er32(ICR);
4105
4106 e_dbg("icr is %08X\n", icr);
4107 if (icr & E1000_ICR_RXSEQ) {
4108 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
4109 /* Force memory writes to complete before acknowledging the
4110 * interrupt is handled.
4111 */
4112 wmb();
4113 }
4114
4115 return IRQ_HANDLED;
4116 }
4117
4118 /**
4119 * e1000_test_msi_interrupt - Returns 0 for successful test
4120 * @adapter: board private struct
4121 *
4122 * code flow taken from tg3.c
4123 **/
4124 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4125 {
4126 struct net_device *netdev = adapter->netdev;
4127 struct e1000_hw *hw = &adapter->hw;
4128 int err;
4129
4130 /* poll_enable hasn't been called yet, so don't need disable */
4131 /* clear any pending events */
4132 er32(ICR);
4133
4134 /* free the real vector and request a test handler */
4135 e1000_free_irq(adapter);
4136 e1000e_reset_interrupt_capability(adapter);
4137
4138 /* Assume that the test fails, if it succeeds then the test
4139 * MSI irq handler will unset this flag
4140 */
4141 adapter->flags |= FLAG_MSI_TEST_FAILED;
4142
4143 err = pci_enable_msi(adapter->pdev);
4144 if (err)
4145 goto msi_test_failed;
4146
4147 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
4148 netdev->name, netdev);
4149 if (err) {
4150 pci_disable_msi(adapter->pdev);
4151 goto msi_test_failed;
4152 }
4153
4154 /* Force memory writes to complete before enabling and firing an
4155 * interrupt.
4156 */
4157 wmb();
4158
4159 e1000_irq_enable(adapter);
4160
4161 /* fire an unusual interrupt on the test handler */
4162 ew32(ICS, E1000_ICS_RXSEQ);
4163 e1e_flush();
4164 msleep(100);
4165
4166 e1000_irq_disable(adapter);
4167
4168 rmb(); /* read flags after interrupt has been fired */
4169
4170 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4171 adapter->int_mode = E1000E_INT_MODE_LEGACY;
4172 e_info("MSI interrupt test failed, using legacy interrupt.\n");
4173 } else {
4174 e_dbg("MSI interrupt test succeeded!\n");
4175 }
4176
4177 free_irq(adapter->pdev->irq, netdev);
4178 pci_disable_msi(adapter->pdev);
4179
4180 msi_test_failed:
4181 e1000e_set_interrupt_capability(adapter);
4182 return e1000_request_irq(adapter);
4183 }
4184
4185 /**
4186 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4187 * @adapter: board private struct
4188 *
4189 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4190 **/
4191 static int e1000_test_msi(struct e1000_adapter *adapter)
4192 {
4193 int err;
4194 u16 pci_cmd;
4195
4196 if (!(adapter->flags & FLAG_MSI_ENABLED))
4197 return 0;
4198
4199 /* disable SERR in case the MSI write causes a master abort */
4200 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4201 if (pci_cmd & PCI_COMMAND_SERR)
4202 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4203 pci_cmd & ~PCI_COMMAND_SERR);
4204
4205 err = e1000_test_msi_interrupt(adapter);
4206
4207 /* re-enable SERR */
4208 if (pci_cmd & PCI_COMMAND_SERR) {
4209 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4210 pci_cmd |= PCI_COMMAND_SERR;
4211 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4212 }
4213
4214 return err;
4215 }
4216
4217 /**
4218 * e1000_open - Called when a network interface is made active
4219 * @netdev: network interface device structure
4220 *
4221 * Returns 0 on success, negative value on failure
4222 *
4223 * The open entry point is called when a network interface is made
4224 * active by the system (IFF_UP). At this point all resources needed
4225 * for transmit and receive operations are allocated, the interrupt
4226 * handler is registered with the OS, the watchdog timer is started,
4227 * and the stack is notified that the interface is ready.
4228 **/
4229 static int e1000_open(struct net_device *netdev)
4230 {
4231 struct e1000_adapter *adapter = netdev_priv(netdev);
4232 struct e1000_hw *hw = &adapter->hw;
4233 struct pci_dev *pdev = adapter->pdev;
4234 int err;
4235
4236 /* disallow open during test */
4237 if (test_bit(__E1000_TESTING, &adapter->state))
4238 return -EBUSY;
4239
4240 pm_runtime_get_sync(&pdev->dev);
4241
4242 netif_carrier_off(netdev);
4243
4244 /* allocate transmit descriptors */
4245 err = e1000e_setup_tx_resources(adapter->tx_ring);
4246 if (err)
4247 goto err_setup_tx;
4248
4249 /* allocate receive descriptors */
4250 err = e1000e_setup_rx_resources(adapter->rx_ring);
4251 if (err)
4252 goto err_setup_rx;
4253
4254 /* If AMT is enabled, let the firmware know that the network
4255 * interface is now open and reset the part to a known state.
4256 */
4257 if (adapter->flags & FLAG_HAS_AMT) {
4258 e1000e_get_hw_control(adapter);
4259 e1000e_reset(adapter);
4260 }
4261
4262 e1000e_power_up_phy(adapter);
4263
4264 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4265 if ((adapter->hw.mng_cookie.status &
4266 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4267 e1000_update_mng_vlan(adapter);
4268
4269 /* DMA latency requirement to workaround jumbo issue */
4270 pm_qos_add_request(&adapter->netdev->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
4271 PM_QOS_DEFAULT_VALUE);
4272
4273 /* before we allocate an interrupt, we must be ready to handle it.
4274 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4275 * as soon as we call pci_request_irq, so we have to setup our
4276 * clean_rx handler before we do so.
4277 */
4278 e1000_configure(adapter);
4279
4280 err = e1000_request_irq(adapter);
4281 if (err)
4282 goto err_req_irq;
4283
4284 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4285 * ignore e1000e MSI messages, which means we need to test our MSI
4286 * interrupt now
4287 */
4288 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
4289 err = e1000_test_msi(adapter);
4290 if (err) {
4291 e_err("Interrupt allocation failed\n");
4292 goto err_req_irq;
4293 }
4294 }
4295
4296 /* From here on the code is the same as e1000e_up() */
4297 clear_bit(__E1000_DOWN, &adapter->state);
4298
4299 napi_enable(&adapter->napi);
4300
4301 e1000_irq_enable(adapter);
4302
4303 adapter->tx_hang_recheck = false;
4304 netif_start_queue(netdev);
4305
4306 adapter->idle_check = true;
4307 pm_runtime_put(&pdev->dev);
4308
4309 /* fire a link status change interrupt to start the watchdog */
4310 if (adapter->msix_entries)
4311 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
4312 else
4313 ew32(ICS, E1000_ICS_LSC);
4314
4315 return 0;
4316
4317 err_req_irq:
4318 e1000e_release_hw_control(adapter);
4319 e1000_power_down_phy(adapter);
4320 e1000e_free_rx_resources(adapter->rx_ring);
4321 err_setup_rx:
4322 e1000e_free_tx_resources(adapter->tx_ring);
4323 err_setup_tx:
4324 e1000e_reset(adapter);
4325 pm_runtime_put_sync(&pdev->dev);
4326
4327 return err;
4328 }
4329
4330 /**
4331 * e1000_close - Disables a network interface
4332 * @netdev: network interface device structure
4333 *
4334 * Returns 0, this is not allowed to fail
4335 *
4336 * The close entry point is called when an interface is de-activated
4337 * by the OS. The hardware is still under the drivers control, but
4338 * needs to be disabled. A global MAC reset is issued to stop the
4339 * hardware, and all transmit and receive resources are freed.
4340 **/
4341 static int e1000_close(struct net_device *netdev)
4342 {
4343 struct e1000_adapter *adapter = netdev_priv(netdev);
4344 struct pci_dev *pdev = adapter->pdev;
4345 int count = E1000_CHECK_RESET_COUNT;
4346
4347 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4348 usleep_range(10000, 20000);
4349
4350 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
4351
4352 pm_runtime_get_sync(&pdev->dev);
4353
4354 napi_disable(&adapter->napi);
4355
4356 if (!test_bit(__E1000_DOWN, &adapter->state)) {
4357 e1000e_down(adapter);
4358 e1000_free_irq(adapter);
4359 }
4360 e1000_power_down_phy(adapter);
4361
4362 e1000e_free_tx_resources(adapter->tx_ring);
4363 e1000e_free_rx_resources(adapter->rx_ring);
4364
4365 /* kill manageability vlan ID if supported, but not if a vlan with
4366 * the same ID is registered on the host OS (let 8021q kill it)
4367 */
4368 if (adapter->hw.mng_cookie.status &
4369 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4370 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4371
4372 /* If AMT is enabled, let the firmware know that the network
4373 * interface is now closed
4374 */
4375 if ((adapter->flags & FLAG_HAS_AMT) &&
4376 !test_bit(__E1000_TESTING, &adapter->state))
4377 e1000e_release_hw_control(adapter);
4378
4379 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
4380
4381 pm_runtime_put_sync(&pdev->dev);
4382
4383 return 0;
4384 }
4385 /**
4386 * e1000_set_mac - Change the Ethernet Address of the NIC
4387 * @netdev: network interface device structure
4388 * @p: pointer to an address structure
4389 *
4390 * Returns 0 on success, negative on failure
4391 **/
4392 static int e1000_set_mac(struct net_device *netdev, void *p)
4393 {
4394 struct e1000_adapter *adapter = netdev_priv(netdev);
4395 struct e1000_hw *hw = &adapter->hw;
4396 struct sockaddr *addr = p;
4397
4398 if (!is_valid_ether_addr(addr->sa_data))
4399 return -EADDRNOTAVAIL;
4400
4401 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4402 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4403
4404 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4405
4406 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4407 /* activate the work around */
4408 e1000e_set_laa_state_82571(&adapter->hw, 1);
4409
4410 /* Hold a copy of the LAA in RAR[14] This is done so that
4411 * between the time RAR[0] gets clobbered and the time it
4412 * gets fixed (in e1000_watchdog), the actual LAA is in one
4413 * of the RARs and no incoming packets directed to this port
4414 * are dropped. Eventually the LAA will be in RAR[0] and
4415 * RAR[14]
4416 */
4417 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4418 adapter->hw.mac.rar_entry_count - 1);
4419 }
4420
4421 return 0;
4422 }
4423
4424 /**
4425 * e1000e_update_phy_task - work thread to update phy
4426 * @work: pointer to our work struct
4427 *
4428 * this worker thread exists because we must acquire a
4429 * semaphore to read the phy, which we could msleep while
4430 * waiting for it, and we can't msleep in a timer.
4431 **/
4432 static void e1000e_update_phy_task(struct work_struct *work)
4433 {
4434 struct e1000_adapter *adapter = container_of(work,
4435 struct e1000_adapter, update_phy_task);
4436
4437 if (test_bit(__E1000_DOWN, &adapter->state))
4438 return;
4439
4440 e1000_get_phy_info(&adapter->hw);
4441 }
4442
4443 /**
4444 * e1000_update_phy_info - timre call-back to update PHY info
4445 * @data: pointer to adapter cast into an unsigned long
4446 *
4447 * Need to wait a few seconds after link up to get diagnostic information from
4448 * the phy
4449 **/
4450 static void e1000_update_phy_info(unsigned long data)
4451 {
4452 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
4453
4454 if (test_bit(__E1000_DOWN, &adapter->state))
4455 return;
4456
4457 schedule_work(&adapter->update_phy_task);
4458 }
4459
4460 /**
4461 * e1000e_update_phy_stats - Update the PHY statistics counters
4462 * @adapter: board private structure
4463 *
4464 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4465 **/
4466 static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4467 {
4468 struct e1000_hw *hw = &adapter->hw;
4469 s32 ret_val;
4470 u16 phy_data;
4471
4472 ret_val = hw->phy.ops.acquire(hw);
4473 if (ret_val)
4474 return;
4475
4476 /* A page set is expensive so check if already on desired page.
4477 * If not, set to the page with the PHY status registers.
4478 */
4479 hw->phy.addr = 1;
4480 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4481 &phy_data);
4482 if (ret_val)
4483 goto release;
4484 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4485 ret_val = hw->phy.ops.set_page(hw,
4486 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4487 if (ret_val)
4488 goto release;
4489 }
4490
4491 /* Single Collision Count */
4492 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4493 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4494 if (!ret_val)
4495 adapter->stats.scc += phy_data;
4496
4497 /* Excessive Collision Count */
4498 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4499 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4500 if (!ret_val)
4501 adapter->stats.ecol += phy_data;
4502
4503 /* Multiple Collision Count */
4504 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4505 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4506 if (!ret_val)
4507 adapter->stats.mcc += phy_data;
4508
4509 /* Late Collision Count */
4510 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4511 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4512 if (!ret_val)
4513 adapter->stats.latecol += phy_data;
4514
4515 /* Collision Count - also used for adaptive IFS */
4516 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4517 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4518 if (!ret_val)
4519 hw->mac.collision_delta = phy_data;
4520
4521 /* Defer Count */
4522 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4523 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4524 if (!ret_val)
4525 adapter->stats.dc += phy_data;
4526
4527 /* Transmit with no CRS */
4528 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4529 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4530 if (!ret_val)
4531 adapter->stats.tncrs += phy_data;
4532
4533 release:
4534 hw->phy.ops.release(hw);
4535 }
4536
4537 /**
4538 * e1000e_update_stats - Update the board statistics counters
4539 * @adapter: board private structure
4540 **/
4541 static void e1000e_update_stats(struct e1000_adapter *adapter)
4542 {
4543 struct net_device *netdev = adapter->netdev;
4544 struct e1000_hw *hw = &adapter->hw;
4545 struct pci_dev *pdev = adapter->pdev;
4546
4547 /* Prevent stats update while adapter is being reset, or if the pci
4548 * connection is down.
4549 */
4550 if (adapter->link_speed == 0)
4551 return;
4552 if (pci_channel_offline(pdev))
4553 return;
4554
4555 adapter->stats.crcerrs += er32(CRCERRS);
4556 adapter->stats.gprc += er32(GPRC);
4557 adapter->stats.gorc += er32(GORCL);
4558 er32(GORCH); /* Clear gorc */
4559 adapter->stats.bprc += er32(BPRC);
4560 adapter->stats.mprc += er32(MPRC);
4561 adapter->stats.roc += er32(ROC);
4562
4563 adapter->stats.mpc += er32(MPC);
4564
4565 /* Half-duplex statistics */
4566 if (adapter->link_duplex == HALF_DUPLEX) {
4567 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4568 e1000e_update_phy_stats(adapter);
4569 } else {
4570 adapter->stats.scc += er32(SCC);
4571 adapter->stats.ecol += er32(ECOL);
4572 adapter->stats.mcc += er32(MCC);
4573 adapter->stats.latecol += er32(LATECOL);
4574 adapter->stats.dc += er32(DC);
4575
4576 hw->mac.collision_delta = er32(COLC);
4577
4578 if ((hw->mac.type != e1000_82574) &&
4579 (hw->mac.type != e1000_82583))
4580 adapter->stats.tncrs += er32(TNCRS);
4581 }
4582 adapter->stats.colc += hw->mac.collision_delta;
4583 }
4584
4585 adapter->stats.xonrxc += er32(XONRXC);
4586 adapter->stats.xontxc += er32(XONTXC);
4587 adapter->stats.xoffrxc += er32(XOFFRXC);
4588 adapter->stats.xofftxc += er32(XOFFTXC);
4589 adapter->stats.gptc += er32(GPTC);
4590 adapter->stats.gotc += er32(GOTCL);
4591 er32(GOTCH); /* Clear gotc */
4592 adapter->stats.rnbc += er32(RNBC);
4593 adapter->stats.ruc += er32(RUC);
4594
4595 adapter->stats.mptc += er32(MPTC);
4596 adapter->stats.bptc += er32(BPTC);
4597
4598 /* used for adaptive IFS */
4599
4600 hw->mac.tx_packet_delta = er32(TPT);
4601 adapter->stats.tpt += hw->mac.tx_packet_delta;
4602
4603 adapter->stats.algnerrc += er32(ALGNERRC);
4604 adapter->stats.rxerrc += er32(RXERRC);
4605 adapter->stats.cexterr += er32(CEXTERR);
4606 adapter->stats.tsctc += er32(TSCTC);
4607 adapter->stats.tsctfc += er32(TSCTFC);
4608
4609 /* Fill out the OS statistics structure */
4610 netdev->stats.multicast = adapter->stats.mprc;
4611 netdev->stats.collisions = adapter->stats.colc;
4612
4613 /* Rx Errors */
4614
4615 /* RLEC on some newer hardware can be incorrect so build
4616 * our own version based on RUC and ROC
4617 */
4618 netdev->stats.rx_errors = adapter->stats.rxerrc +
4619 adapter->stats.crcerrs + adapter->stats.algnerrc +
4620 adapter->stats.ruc + adapter->stats.roc +
4621 adapter->stats.cexterr;
4622 netdev->stats.rx_length_errors = adapter->stats.ruc +
4623 adapter->stats.roc;
4624 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4625 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4626 netdev->stats.rx_missed_errors = adapter->stats.mpc;
4627
4628 /* Tx Errors */
4629 netdev->stats.tx_errors = adapter->stats.ecol +
4630 adapter->stats.latecol;
4631 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4632 netdev->stats.tx_window_errors = adapter->stats.latecol;
4633 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
4634
4635 /* Tx Dropped needs to be maintained elsewhere */
4636
4637 /* Management Stats */
4638 adapter->stats.mgptc += er32(MGTPTC);
4639 adapter->stats.mgprc += er32(MGTPRC);
4640 adapter->stats.mgpdc += er32(MGTPDC);
4641
4642 /* Correctable ECC Errors */
4643 if (hw->mac.type == e1000_pch_lpt) {
4644 u32 pbeccsts = er32(PBECCSTS);
4645 adapter->corr_errors +=
4646 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
4647 adapter->uncorr_errors +=
4648 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
4649 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4650 }
4651 }
4652
4653 /**
4654 * e1000_phy_read_status - Update the PHY register status snapshot
4655 * @adapter: board private structure
4656 **/
4657 static void e1000_phy_read_status(struct e1000_adapter *adapter)
4658 {
4659 struct e1000_hw *hw = &adapter->hw;
4660 struct e1000_phy_regs *phy = &adapter->phy_regs;
4661
4662 if ((er32(STATUS) & E1000_STATUS_LU) &&
4663 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
4664 int ret_val;
4665
4666 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
4667 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
4668 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
4669 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
4670 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
4671 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
4672 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
4673 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
4674 if (ret_val)
4675 e_warn("Error reading PHY register\n");
4676 } else {
4677 /* Do not read PHY registers if link is not up
4678 * Set values to typical power-on defaults
4679 */
4680 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4681 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4682 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4683 BMSR_ERCAP);
4684 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4685 ADVERTISE_ALL | ADVERTISE_CSMA);
4686 phy->lpa = 0;
4687 phy->expansion = EXPANSION_ENABLENPAGE;
4688 phy->ctrl1000 = ADVERTISE_1000FULL;
4689 phy->stat1000 = 0;
4690 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4691 }
4692 }
4693
4694 static void e1000_print_link_info(struct e1000_adapter *adapter)
4695 {
4696 struct e1000_hw *hw = &adapter->hw;
4697 u32 ctrl = er32(CTRL);
4698
4699 /* Link status message must follow this format for user tools */
4700 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4701 adapter->netdev->name, adapter->link_speed,
4702 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4703 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4704 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4705 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
4706 }
4707
4708 static bool e1000e_has_link(struct e1000_adapter *adapter)
4709 {
4710 struct e1000_hw *hw = &adapter->hw;
4711 bool link_active = false;
4712 s32 ret_val = 0;
4713
4714 /* get_link_status is set on LSC (link status) interrupt or
4715 * Rx sequence error interrupt. get_link_status will stay
4716 * false until the check_for_link establishes link
4717 * for copper adapters ONLY
4718 */
4719 switch (hw->phy.media_type) {
4720 case e1000_media_type_copper:
4721 if (hw->mac.get_link_status) {
4722 ret_val = hw->mac.ops.check_for_link(hw);
4723 link_active = !hw->mac.get_link_status;
4724 } else {
4725 link_active = true;
4726 }
4727 break;
4728 case e1000_media_type_fiber:
4729 ret_val = hw->mac.ops.check_for_link(hw);
4730 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4731 break;
4732 case e1000_media_type_internal_serdes:
4733 ret_val = hw->mac.ops.check_for_link(hw);
4734 link_active = adapter->hw.mac.serdes_has_link;
4735 break;
4736 default:
4737 case e1000_media_type_unknown:
4738 break;
4739 }
4740
4741 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4742 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4743 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
4744 e_info("Gigabit has been disabled, downgrading speed\n");
4745 }
4746
4747 return link_active;
4748 }
4749
4750 static void e1000e_enable_receives(struct e1000_adapter *adapter)
4751 {
4752 /* make sure the receive unit is started */
4753 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
4754 (adapter->flags & FLAG_RESTART_NOW)) {
4755 struct e1000_hw *hw = &adapter->hw;
4756 u32 rctl = er32(RCTL);
4757 ew32(RCTL, rctl | E1000_RCTL_EN);
4758 adapter->flags &= ~FLAG_RESTART_NOW;
4759 }
4760 }
4761
4762 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4763 {
4764 struct e1000_hw *hw = &adapter->hw;
4765
4766 /* With 82574 controllers, PHY needs to be checked periodically
4767 * for hung state and reset, if two calls return true
4768 */
4769 if (e1000_check_phy_82574(hw))
4770 adapter->phy_hang_count++;
4771 else
4772 adapter->phy_hang_count = 0;
4773
4774 if (adapter->phy_hang_count > 1) {
4775 adapter->phy_hang_count = 0;
4776 schedule_work(&adapter->reset_task);
4777 }
4778 }
4779
4780 /**
4781 * e1000_watchdog - Timer Call-back
4782 * @data: pointer to adapter cast into an unsigned long
4783 **/
4784 static void e1000_watchdog(unsigned long data)
4785 {
4786 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
4787
4788 /* Do the rest outside of interrupt context */
4789 schedule_work(&adapter->watchdog_task);
4790
4791 /* TODO: make this use queue_delayed_work() */
4792 }
4793
4794 static void e1000_watchdog_task(struct work_struct *work)
4795 {
4796 struct e1000_adapter *adapter = container_of(work,
4797 struct e1000_adapter, watchdog_task);
4798 struct net_device *netdev = adapter->netdev;
4799 struct e1000_mac_info *mac = &adapter->hw.mac;
4800 struct e1000_phy_info *phy = &adapter->hw.phy;
4801 struct e1000_ring *tx_ring = adapter->tx_ring;
4802 struct e1000_hw *hw = &adapter->hw;
4803 u32 link, tctl;
4804
4805 if (test_bit(__E1000_DOWN, &adapter->state))
4806 return;
4807
4808 link = e1000e_has_link(adapter);
4809 if ((netif_carrier_ok(netdev)) && link) {
4810 /* Cancel scheduled suspend requests. */
4811 pm_runtime_resume(netdev->dev.parent);
4812
4813 e1000e_enable_receives(adapter);
4814 goto link_up;
4815 }
4816
4817 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4818 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4819 e1000_update_mng_vlan(adapter);
4820
4821 if (link) {
4822 if (!netif_carrier_ok(netdev)) {
4823 bool txb2b = true;
4824
4825 /* Cancel scheduled suspend requests. */
4826 pm_runtime_resume(netdev->dev.parent);
4827
4828 /* update snapshot of PHY registers on LSC */
4829 e1000_phy_read_status(adapter);
4830 mac->ops.get_link_up_info(&adapter->hw,
4831 &adapter->link_speed,
4832 &adapter->link_duplex);
4833 e1000_print_link_info(adapter);
4834 /* On supported PHYs, check for duplex mismatch only
4835 * if link has autonegotiated at 10/100 half
4836 */
4837 if ((hw->phy.type == e1000_phy_igp_3 ||
4838 hw->phy.type == e1000_phy_bm) &&
4839 (hw->mac.autoneg == true) &&
4840 (adapter->link_speed == SPEED_10 ||
4841 adapter->link_speed == SPEED_100) &&
4842 (adapter->link_duplex == HALF_DUPLEX)) {
4843 u16 autoneg_exp;
4844
4845 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
4846
4847 if (!(autoneg_exp & EXPANSION_NWAY))
4848 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
4849 }
4850
4851 /* adjust timeout factor according to speed/duplex */
4852 adapter->tx_timeout_factor = 1;
4853 switch (adapter->link_speed) {
4854 case SPEED_10:
4855 txb2b = false;
4856 adapter->tx_timeout_factor = 16;
4857 break;
4858 case SPEED_100:
4859 txb2b = false;
4860 adapter->tx_timeout_factor = 10;
4861 break;
4862 }
4863
4864 /* workaround: re-program speed mode bit after
4865 * link-up event
4866 */
4867 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4868 !txb2b) {
4869 u32 tarc0;
4870 tarc0 = er32(TARC(0));
4871 tarc0 &= ~SPEED_MODE_BIT;
4872 ew32(TARC(0), tarc0);
4873 }
4874
4875 /* disable TSO for pcie and 10/100 speeds, to avoid
4876 * some hardware issues
4877 */
4878 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4879 switch (adapter->link_speed) {
4880 case SPEED_10:
4881 case SPEED_100:
4882 e_info("10/100 speed: disabling TSO\n");
4883 netdev->features &= ~NETIF_F_TSO;
4884 netdev->features &= ~NETIF_F_TSO6;
4885 break;
4886 case SPEED_1000:
4887 netdev->features |= NETIF_F_TSO;
4888 netdev->features |= NETIF_F_TSO6;
4889 break;
4890 default:
4891 /* oops */
4892 break;
4893 }
4894 }
4895
4896 /* enable transmits in the hardware, need to do this
4897 * after setting TARC(0)
4898 */
4899 tctl = er32(TCTL);
4900 tctl |= E1000_TCTL_EN;
4901 ew32(TCTL, tctl);
4902
4903 /* Perform any post-link-up configuration before
4904 * reporting link up.
4905 */
4906 if (phy->ops.cfg_on_link_up)
4907 phy->ops.cfg_on_link_up(hw);
4908
4909 netif_carrier_on(netdev);
4910
4911 if (!test_bit(__E1000_DOWN, &adapter->state))
4912 mod_timer(&adapter->phy_info_timer,
4913 round_jiffies(jiffies + 2 * HZ));
4914 }
4915 } else {
4916 if (netif_carrier_ok(netdev)) {
4917 adapter->link_speed = 0;
4918 adapter->link_duplex = 0;
4919 /* Link status message must follow this format */
4920 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
4921 netif_carrier_off(netdev);
4922 if (!test_bit(__E1000_DOWN, &adapter->state))
4923 mod_timer(&adapter->phy_info_timer,
4924 round_jiffies(jiffies + 2 * HZ));
4925
4926 /* The link is lost so the controller stops DMA.
4927 * If there is queued Tx work that cannot be done
4928 * or if on an 8000ES2LAN which requires a Rx packet
4929 * buffer work-around on link down event, reset the
4930 * controller to flush the Tx/Rx packet buffers.
4931 * (Do the reset outside of interrupt context).
4932 */
4933 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) ||
4934 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
4935 adapter->flags |= FLAG_RESTART_NOW;
4936 else
4937 pm_schedule_suspend(netdev->dev.parent,
4938 LINK_TIMEOUT);
4939 }
4940 }
4941
4942 link_up:
4943 spin_lock(&adapter->stats64_lock);
4944 e1000e_update_stats(adapter);
4945
4946 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4947 adapter->tpt_old = adapter->stats.tpt;
4948 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4949 adapter->colc_old = adapter->stats.colc;
4950
4951 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4952 adapter->gorc_old = adapter->stats.gorc;
4953 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4954 adapter->gotc_old = adapter->stats.gotc;
4955 spin_unlock(&adapter->stats64_lock);
4956
4957 if (adapter->flags & FLAG_RESTART_NOW) {
4958 schedule_work(&adapter->reset_task);
4959 /* return immediately since reset is imminent */
4960 return;
4961 }
4962
4963 e1000e_update_adaptive(&adapter->hw);
4964
4965 /* Simple mode for Interrupt Throttle Rate (ITR) */
4966 if (adapter->itr_setting == 4) {
4967 /* Symmetric Tx/Rx gets a reduced ITR=2000;
4968 * Total asymmetrical Tx or Rx gets ITR=8000;
4969 * everyone else is between 2000-8000.
4970 */
4971 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
4972 u32 dif = (adapter->gotc > adapter->gorc ?
4973 adapter->gotc - adapter->gorc :
4974 adapter->gorc - adapter->gotc) / 10000;
4975 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
4976
4977 e1000e_write_itr(adapter, itr);
4978 }
4979
4980 /* Cause software interrupt to ensure Rx ring is cleaned */
4981 if (adapter->msix_entries)
4982 ew32(ICS, adapter->rx_ring->ims_val);
4983 else
4984 ew32(ICS, E1000_ICS_RXDMT0);
4985
4986 /* flush pending descriptors to memory before detecting Tx hang */
4987 e1000e_flush_descriptors(adapter);
4988
4989 /* Force detection of hung controller every watchdog period */
4990 adapter->detect_tx_hung = true;
4991
4992 /* With 82571 controllers, LAA may be overwritten due to controller
4993 * reset from the other port. Set the appropriate LAA in RAR[0]
4994 */
4995 if (e1000e_get_laa_state_82571(hw))
4996 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
4997
4998 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
4999 e1000e_check_82574_phy_workaround(adapter);
5000
5001 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5002 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5003 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5004 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5005 er32(RXSTMPH);
5006 adapter->rx_hwtstamp_cleared++;
5007 } else {
5008 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5009 }
5010 }
5011
5012 /* Reset the timer */
5013 if (!test_bit(__E1000_DOWN, &adapter->state))
5014 mod_timer(&adapter->watchdog_timer,
5015 round_jiffies(jiffies + 2 * HZ));
5016 }
5017
5018 #define E1000_TX_FLAGS_CSUM 0x00000001
5019 #define E1000_TX_FLAGS_VLAN 0x00000002
5020 #define E1000_TX_FLAGS_TSO 0x00000004
5021 #define E1000_TX_FLAGS_IPV4 0x00000008
5022 #define E1000_TX_FLAGS_NO_FCS 0x00000010
5023 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5024 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5025 #define E1000_TX_FLAGS_VLAN_SHIFT 16
5026
5027 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
5028 {
5029 struct e1000_context_desc *context_desc;
5030 struct e1000_buffer *buffer_info;
5031 unsigned int i;
5032 u32 cmd_length = 0;
5033 u16 ipcse = 0, mss;
5034 u8 ipcss, ipcso, tucss, tucso, hdr_len;
5035
5036 if (!skb_is_gso(skb))
5037 return 0;
5038
5039 if (skb_header_cloned(skb)) {
5040 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5041
5042 if (err)
5043 return err;
5044 }
5045
5046 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5047 mss = skb_shinfo(skb)->gso_size;
5048 if (skb->protocol == htons(ETH_P_IP)) {
5049 struct iphdr *iph = ip_hdr(skb);
5050 iph->tot_len = 0;
5051 iph->check = 0;
5052 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
5053 0, IPPROTO_TCP, 0);
5054 cmd_length = E1000_TXD_CMD_IP;
5055 ipcse = skb_transport_offset(skb) - 1;
5056 } else if (skb_is_gso_v6(skb)) {
5057 ipv6_hdr(skb)->payload_len = 0;
5058 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5059 &ipv6_hdr(skb)->daddr,
5060 0, IPPROTO_TCP, 0);
5061 ipcse = 0;
5062 }
5063 ipcss = skb_network_offset(skb);
5064 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5065 tucss = skb_transport_offset(skb);
5066 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
5067
5068 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5069 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5070
5071 i = tx_ring->next_to_use;
5072 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5073 buffer_info = &tx_ring->buffer_info[i];
5074
5075 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5076 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5077 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5078 context_desc->upper_setup.tcp_fields.tucss = tucss;
5079 context_desc->upper_setup.tcp_fields.tucso = tucso;
5080 context_desc->upper_setup.tcp_fields.tucse = 0;
5081 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5082 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5083 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5084
5085 buffer_info->time_stamp = jiffies;
5086 buffer_info->next_to_watch = i;
5087
5088 i++;
5089 if (i == tx_ring->count)
5090 i = 0;
5091 tx_ring->next_to_use = i;
5092
5093 return 1;
5094 }
5095
5096 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
5097 {
5098 struct e1000_adapter *adapter = tx_ring->adapter;
5099 struct e1000_context_desc *context_desc;
5100 struct e1000_buffer *buffer_info;
5101 unsigned int i;
5102 u8 css;
5103 u32 cmd_len = E1000_TXD_CMD_DEXT;
5104 __be16 protocol;
5105
5106 if (skb->ip_summed != CHECKSUM_PARTIAL)
5107 return 0;
5108
5109 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
5110 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
5111 else
5112 protocol = skb->protocol;
5113
5114 switch (protocol) {
5115 case cpu_to_be16(ETH_P_IP):
5116 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5117 cmd_len |= E1000_TXD_CMD_TCP;
5118 break;
5119 case cpu_to_be16(ETH_P_IPV6):
5120 /* XXX not handling all IPV6 headers */
5121 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5122 cmd_len |= E1000_TXD_CMD_TCP;
5123 break;
5124 default:
5125 if (unlikely(net_ratelimit()))
5126 e_warn("checksum_partial proto=%x!\n",
5127 be16_to_cpu(protocol));
5128 break;
5129 }
5130
5131 css = skb_checksum_start_offset(skb);
5132
5133 i = tx_ring->next_to_use;
5134 buffer_info = &tx_ring->buffer_info[i];
5135 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5136
5137 context_desc->lower_setup.ip_config = 0;
5138 context_desc->upper_setup.tcp_fields.tucss = css;
5139 context_desc->upper_setup.tcp_fields.tucso =
5140 css + skb->csum_offset;
5141 context_desc->upper_setup.tcp_fields.tucse = 0;
5142 context_desc->tcp_seg_setup.data = 0;
5143 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5144
5145 buffer_info->time_stamp = jiffies;
5146 buffer_info->next_to_watch = i;
5147
5148 i++;
5149 if (i == tx_ring->count)
5150 i = 0;
5151 tx_ring->next_to_use = i;
5152
5153 return 1;
5154 }
5155
5156 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5157 unsigned int first, unsigned int max_per_txd,
5158 unsigned int nr_frags)
5159 {
5160 struct e1000_adapter *adapter = tx_ring->adapter;
5161 struct pci_dev *pdev = adapter->pdev;
5162 struct e1000_buffer *buffer_info;
5163 unsigned int len = skb_headlen(skb);
5164 unsigned int offset = 0, size, count = 0, i;
5165 unsigned int f, bytecount, segs;
5166
5167 i = tx_ring->next_to_use;
5168
5169 while (len) {
5170 buffer_info = &tx_ring->buffer_info[i];
5171 size = min(len, max_per_txd);
5172
5173 buffer_info->length = size;
5174 buffer_info->time_stamp = jiffies;
5175 buffer_info->next_to_watch = i;
5176 buffer_info->dma = dma_map_single(&pdev->dev,
5177 skb->data + offset,
5178 size, DMA_TO_DEVICE);
5179 buffer_info->mapped_as_page = false;
5180 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5181 goto dma_error;
5182
5183 len -= size;
5184 offset += size;
5185 count++;
5186
5187 if (len) {
5188 i++;
5189 if (i == tx_ring->count)
5190 i = 0;
5191 }
5192 }
5193
5194 for (f = 0; f < nr_frags; f++) {
5195 const struct skb_frag_struct *frag;
5196
5197 frag = &skb_shinfo(skb)->frags[f];
5198 len = skb_frag_size(frag);
5199 offset = 0;
5200
5201 while (len) {
5202 i++;
5203 if (i == tx_ring->count)
5204 i = 0;
5205
5206 buffer_info = &tx_ring->buffer_info[i];
5207 size = min(len, max_per_txd);
5208
5209 buffer_info->length = size;
5210 buffer_info->time_stamp = jiffies;
5211 buffer_info->next_to_watch = i;
5212 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5213 offset, size, DMA_TO_DEVICE);
5214 buffer_info->mapped_as_page = true;
5215 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5216 goto dma_error;
5217
5218 len -= size;
5219 offset += size;
5220 count++;
5221 }
5222 }
5223
5224 segs = skb_shinfo(skb)->gso_segs ? : 1;
5225 /* multiply data chunks by size of headers */
5226 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5227
5228 tx_ring->buffer_info[i].skb = skb;
5229 tx_ring->buffer_info[i].segs = segs;
5230 tx_ring->buffer_info[i].bytecount = bytecount;
5231 tx_ring->buffer_info[first].next_to_watch = i;
5232
5233 return count;
5234
5235 dma_error:
5236 dev_err(&pdev->dev, "Tx DMA map failed\n");
5237 buffer_info->dma = 0;
5238 if (count)
5239 count--;
5240
5241 while (count--) {
5242 if (i == 0)
5243 i += tx_ring->count;
5244 i--;
5245 buffer_info = &tx_ring->buffer_info[i];
5246 e1000_put_txbuf(tx_ring, buffer_info);
5247 }
5248
5249 return 0;
5250 }
5251
5252 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
5253 {
5254 struct e1000_adapter *adapter = tx_ring->adapter;
5255 struct e1000_tx_desc *tx_desc = NULL;
5256 struct e1000_buffer *buffer_info;
5257 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5258 unsigned int i;
5259
5260 if (tx_flags & E1000_TX_FLAGS_TSO) {
5261 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5262 E1000_TXD_CMD_TSE;
5263 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5264
5265 if (tx_flags & E1000_TX_FLAGS_IPV4)
5266 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5267 }
5268
5269 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5270 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5271 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5272 }
5273
5274 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5275 txd_lower |= E1000_TXD_CMD_VLE;
5276 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5277 }
5278
5279 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5280 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5281
5282 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5283 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5284 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5285 }
5286
5287 i = tx_ring->next_to_use;
5288
5289 do {
5290 buffer_info = &tx_ring->buffer_info[i];
5291 tx_desc = E1000_TX_DESC(*tx_ring, i);
5292 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5293 tx_desc->lower.data =
5294 cpu_to_le32(txd_lower | buffer_info->length);
5295 tx_desc->upper.data = cpu_to_le32(txd_upper);
5296
5297 i++;
5298 if (i == tx_ring->count)
5299 i = 0;
5300 } while (--count > 0);
5301
5302 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5303
5304 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5305 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5306 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5307
5308 /* Force memory writes to complete before letting h/w
5309 * know there are new descriptors to fetch. (Only
5310 * applicable for weak-ordered memory model archs,
5311 * such as IA-64).
5312 */
5313 wmb();
5314
5315 tx_ring->next_to_use = i;
5316
5317 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5318 e1000e_update_tdt_wa(tx_ring, i);
5319 else
5320 writel(i, tx_ring->tail);
5321
5322 /* we need this if more than one processor can write to our tail
5323 * at a time, it synchronizes IO on IA64/Altix systems
5324 */
5325 mmiowb();
5326 }
5327
5328 #define MINIMUM_DHCP_PACKET_SIZE 282
5329 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5330 struct sk_buff *skb)
5331 {
5332 struct e1000_hw *hw = &adapter->hw;
5333 u16 length, offset;
5334
5335 if (vlan_tx_tag_present(skb) &&
5336 !((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5337 (adapter->hw.mng_cookie.status &
5338 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5339 return 0;
5340
5341 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5342 return 0;
5343
5344 if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
5345 return 0;
5346
5347 {
5348 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
5349 struct udphdr *udp;
5350
5351 if (ip->protocol != IPPROTO_UDP)
5352 return 0;
5353
5354 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5355 if (ntohs(udp->dest) != 67)
5356 return 0;
5357
5358 offset = (u8 *)udp + 8 - skb->data;
5359 length = skb->len - offset;
5360 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5361 }
5362
5363 return 0;
5364 }
5365
5366 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5367 {
5368 struct e1000_adapter *adapter = tx_ring->adapter;
5369
5370 netif_stop_queue(adapter->netdev);
5371 /* Herbert's original patch had:
5372 * smp_mb__after_netif_stop_queue();
5373 * but since that doesn't exist yet, just open code it.
5374 */
5375 smp_mb();
5376
5377 /* We need to check again in a case another CPU has just
5378 * made room available.
5379 */
5380 if (e1000_desc_unused(tx_ring) < size)
5381 return -EBUSY;
5382
5383 /* A reprieve! */
5384 netif_start_queue(adapter->netdev);
5385 ++adapter->restart_queue;
5386 return 0;
5387 }
5388
5389 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5390 {
5391 BUG_ON(size > tx_ring->count);
5392
5393 if (e1000_desc_unused(tx_ring) >= size)
5394 return 0;
5395 return __e1000_maybe_stop_tx(tx_ring, size);
5396 }
5397
5398 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5399 struct net_device *netdev)
5400 {
5401 struct e1000_adapter *adapter = netdev_priv(netdev);
5402 struct e1000_ring *tx_ring = adapter->tx_ring;
5403 unsigned int first;
5404 unsigned int tx_flags = 0;
5405 unsigned int len = skb_headlen(skb);
5406 unsigned int nr_frags;
5407 unsigned int mss;
5408 int count = 0;
5409 int tso;
5410 unsigned int f;
5411
5412 if (test_bit(__E1000_DOWN, &adapter->state)) {
5413 dev_kfree_skb_any(skb);
5414 return NETDEV_TX_OK;
5415 }
5416
5417 if (skb->len <= 0) {
5418 dev_kfree_skb_any(skb);
5419 return NETDEV_TX_OK;
5420 }
5421
5422 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5423 * pad skb in order to meet this minimum size requirement
5424 */
5425 if (unlikely(skb->len < 17)) {
5426 if (skb_pad(skb, 17 - skb->len))
5427 return NETDEV_TX_OK;
5428 skb->len = 17;
5429 skb_set_tail_pointer(skb, 17);
5430 }
5431
5432 mss = skb_shinfo(skb)->gso_size;
5433 if (mss) {
5434 u8 hdr_len;
5435
5436 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5437 * points to just header, pull a few bytes of payload from
5438 * frags into skb->data
5439 */
5440 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5441 /* we do this workaround for ES2LAN, but it is un-necessary,
5442 * avoiding it could save a lot of cycles
5443 */
5444 if (skb->data_len && (hdr_len == len)) {
5445 unsigned int pull_size;
5446
5447 pull_size = min_t(unsigned int, 4, skb->data_len);
5448 if (!__pskb_pull_tail(skb, pull_size)) {
5449 e_err("__pskb_pull_tail failed.\n");
5450 dev_kfree_skb_any(skb);
5451 return NETDEV_TX_OK;
5452 }
5453 len = skb_headlen(skb);
5454 }
5455 }
5456
5457 /* reserve a descriptor for the offload context */
5458 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5459 count++;
5460 count++;
5461
5462 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
5463
5464 nr_frags = skb_shinfo(skb)->nr_frags;
5465 for (f = 0; f < nr_frags; f++)
5466 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5467 adapter->tx_fifo_limit);
5468
5469 if (adapter->hw.mac.tx_pkt_filtering)
5470 e1000_transfer_dhcp_info(adapter, skb);
5471
5472 /* need: count + 2 desc gap to keep tail from touching
5473 * head, otherwise try next time
5474 */
5475 if (e1000_maybe_stop_tx(tx_ring, count + 2))
5476 return NETDEV_TX_BUSY;
5477
5478 if (vlan_tx_tag_present(skb)) {
5479 tx_flags |= E1000_TX_FLAGS_VLAN;
5480 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5481 }
5482
5483 first = tx_ring->next_to_use;
5484
5485 tso = e1000_tso(tx_ring, skb);
5486 if (tso < 0) {
5487 dev_kfree_skb_any(skb);
5488 return NETDEV_TX_OK;
5489 }
5490
5491 if (tso)
5492 tx_flags |= E1000_TX_FLAGS_TSO;
5493 else if (e1000_tx_csum(tx_ring, skb))
5494 tx_flags |= E1000_TX_FLAGS_CSUM;
5495
5496 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5497 * 82571 hardware supports TSO capabilities for IPv6 as well...
5498 * no longer assume, we must.
5499 */
5500 if (skb->protocol == htons(ETH_P_IP))
5501 tx_flags |= E1000_TX_FLAGS_IPV4;
5502
5503 if (unlikely(skb->no_fcs))
5504 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5505
5506 /* if count is 0 then mapping error has occurred */
5507 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5508 nr_frags);
5509 if (count) {
5510 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5511 !adapter->tx_hwtstamp_skb)) {
5512 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5513 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5514 adapter->tx_hwtstamp_skb = skb_get(skb);
5515 schedule_work(&adapter->tx_hwtstamp_work);
5516 } else {
5517 skb_tx_timestamp(skb);
5518 }
5519
5520 netdev_sent_queue(netdev, skb->len);
5521 e1000_tx_queue(tx_ring, tx_flags, count);
5522 /* Make sure there is space in the ring for the next send. */
5523 e1000_maybe_stop_tx(tx_ring,
5524 (MAX_SKB_FRAGS *
5525 DIV_ROUND_UP(PAGE_SIZE,
5526 adapter->tx_fifo_limit) + 2));
5527 } else {
5528 dev_kfree_skb_any(skb);
5529 tx_ring->buffer_info[first].time_stamp = 0;
5530 tx_ring->next_to_use = first;
5531 }
5532
5533 return NETDEV_TX_OK;
5534 }
5535
5536 /**
5537 * e1000_tx_timeout - Respond to a Tx Hang
5538 * @netdev: network interface device structure
5539 **/
5540 static void e1000_tx_timeout(struct net_device *netdev)
5541 {
5542 struct e1000_adapter *adapter = netdev_priv(netdev);
5543
5544 /* Do the reset outside of interrupt context */
5545 adapter->tx_timeout_count++;
5546 schedule_work(&adapter->reset_task);
5547 }
5548
5549 static void e1000_reset_task(struct work_struct *work)
5550 {
5551 struct e1000_adapter *adapter;
5552 adapter = container_of(work, struct e1000_adapter, reset_task);
5553
5554 /* don't run the task if already down */
5555 if (test_bit(__E1000_DOWN, &adapter->state))
5556 return;
5557
5558 if (!(adapter->flags & FLAG_RESTART_NOW)) {
5559 e1000e_dump(adapter);
5560 e_err("Reset adapter unexpectedly\n");
5561 }
5562 e1000e_reinit_locked(adapter);
5563 }
5564
5565 /**
5566 * e1000_get_stats64 - Get System Network Statistics
5567 * @netdev: network interface device structure
5568 * @stats: rtnl_link_stats64 pointer
5569 *
5570 * Returns the address of the device statistics structure.
5571 **/
5572 struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5573 struct rtnl_link_stats64 *stats)
5574 {
5575 struct e1000_adapter *adapter = netdev_priv(netdev);
5576
5577 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5578 spin_lock(&adapter->stats64_lock);
5579 e1000e_update_stats(adapter);
5580 /* Fill out the OS statistics structure */
5581 stats->rx_bytes = adapter->stats.gorc;
5582 stats->rx_packets = adapter->stats.gprc;
5583 stats->tx_bytes = adapter->stats.gotc;
5584 stats->tx_packets = adapter->stats.gptc;
5585 stats->multicast = adapter->stats.mprc;
5586 stats->collisions = adapter->stats.colc;
5587
5588 /* Rx Errors */
5589
5590 /* RLEC on some newer hardware can be incorrect so build
5591 * our own version based on RUC and ROC
5592 */
5593 stats->rx_errors = adapter->stats.rxerrc +
5594 adapter->stats.crcerrs + adapter->stats.algnerrc +
5595 adapter->stats.ruc + adapter->stats.roc +
5596 adapter->stats.cexterr;
5597 stats->rx_length_errors = adapter->stats.ruc +
5598 adapter->stats.roc;
5599 stats->rx_crc_errors = adapter->stats.crcerrs;
5600 stats->rx_frame_errors = adapter->stats.algnerrc;
5601 stats->rx_missed_errors = adapter->stats.mpc;
5602
5603 /* Tx Errors */
5604 stats->tx_errors = adapter->stats.ecol +
5605 adapter->stats.latecol;
5606 stats->tx_aborted_errors = adapter->stats.ecol;
5607 stats->tx_window_errors = adapter->stats.latecol;
5608 stats->tx_carrier_errors = adapter->stats.tncrs;
5609
5610 /* Tx Dropped needs to be maintained elsewhere */
5611
5612 spin_unlock(&adapter->stats64_lock);
5613 return stats;
5614 }
5615
5616 /**
5617 * e1000_change_mtu - Change the Maximum Transfer Unit
5618 * @netdev: network interface device structure
5619 * @new_mtu: new value for maximum frame size
5620 *
5621 * Returns 0 on success, negative on failure
5622 **/
5623 static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5624 {
5625 struct e1000_adapter *adapter = netdev_priv(netdev);
5626 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5627
5628 /* Jumbo frame support */
5629 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
5630 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5631 e_err("Jumbo Frames not supported.\n");
5632 return -EINVAL;
5633 }
5634
5635 /* Supported frame sizes */
5636 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5637 (max_frame > adapter->max_hw_frame_size)) {
5638 e_err("Unsupported MTU setting\n");
5639 return -EINVAL;
5640 }
5641
5642 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5643 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
5644 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5645 (new_mtu > ETH_DATA_LEN)) {
5646 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
5647 return -EINVAL;
5648 }
5649
5650 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
5651 usleep_range(1000, 2000);
5652 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
5653 adapter->max_frame_size = max_frame;
5654 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5655 netdev->mtu = new_mtu;
5656 if (netif_running(netdev))
5657 e1000e_down(adapter);
5658
5659 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
5660 * means we reserve 2 more, this pushes us to allocate from the next
5661 * larger slab size.
5662 * i.e. RXBUFFER_2048 --> size-4096 slab
5663 * However with the new *_jumbo_rx* routines, jumbo receives will use
5664 * fragmented skbs
5665 */
5666
5667 if (max_frame <= 2048)
5668 adapter->rx_buffer_len = 2048;
5669 else
5670 adapter->rx_buffer_len = 4096;
5671
5672 /* adjust allocation if LPE protects us, and we aren't using SBP */
5673 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
5674 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
5675 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
5676 + ETH_FCS_LEN;
5677
5678 if (netif_running(netdev))
5679 e1000e_up(adapter);
5680 else
5681 e1000e_reset(adapter);
5682
5683 clear_bit(__E1000_RESETTING, &adapter->state);
5684
5685 return 0;
5686 }
5687
5688 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5689 int cmd)
5690 {
5691 struct e1000_adapter *adapter = netdev_priv(netdev);
5692 struct mii_ioctl_data *data = if_mii(ifr);
5693
5694 if (adapter->hw.phy.media_type != e1000_media_type_copper)
5695 return -EOPNOTSUPP;
5696
5697 switch (cmd) {
5698 case SIOCGMIIPHY:
5699 data->phy_id = adapter->hw.phy.addr;
5700 break;
5701 case SIOCGMIIREG:
5702 e1000_phy_read_status(adapter);
5703
5704 switch (data->reg_num & 0x1F) {
5705 case MII_BMCR:
5706 data->val_out = adapter->phy_regs.bmcr;
5707 break;
5708 case MII_BMSR:
5709 data->val_out = adapter->phy_regs.bmsr;
5710 break;
5711 case MII_PHYSID1:
5712 data->val_out = (adapter->hw.phy.id >> 16);
5713 break;
5714 case MII_PHYSID2:
5715 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5716 break;
5717 case MII_ADVERTISE:
5718 data->val_out = adapter->phy_regs.advertise;
5719 break;
5720 case MII_LPA:
5721 data->val_out = adapter->phy_regs.lpa;
5722 break;
5723 case MII_EXPANSION:
5724 data->val_out = adapter->phy_regs.expansion;
5725 break;
5726 case MII_CTRL1000:
5727 data->val_out = adapter->phy_regs.ctrl1000;
5728 break;
5729 case MII_STAT1000:
5730 data->val_out = adapter->phy_regs.stat1000;
5731 break;
5732 case MII_ESTATUS:
5733 data->val_out = adapter->phy_regs.estatus;
5734 break;
5735 default:
5736 return -EIO;
5737 }
5738 break;
5739 case SIOCSMIIREG:
5740 default:
5741 return -EOPNOTSUPP;
5742 }
5743 return 0;
5744 }
5745
5746 /**
5747 * e1000e_hwtstamp_ioctl - control hardware time stamping
5748 * @netdev: network interface device structure
5749 * @ifreq: interface request
5750 *
5751 * Outgoing time stamping can be enabled and disabled. Play nice and
5752 * disable it when requested, although it shouldn't cause any overhead
5753 * when no packet needs it. At most one packet in the queue may be
5754 * marked for time stamping, otherwise it would be impossible to tell
5755 * for sure to which packet the hardware time stamp belongs.
5756 *
5757 * Incoming time stamping has to be configured via the hardware filters.
5758 * Not all combinations are supported, in particular event type has to be
5759 * specified. Matching the kind of event packet is not supported, with the
5760 * exception of "all V2 events regardless of level 2 or 4".
5761 **/
5762 static int e1000e_hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr)
5763 {
5764 struct e1000_adapter *adapter = netdev_priv(netdev);
5765 struct hwtstamp_config config;
5766 int ret_val;
5767
5768 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5769 return -EFAULT;
5770
5771 adapter->hwtstamp_config = config;
5772
5773 ret_val = e1000e_config_hwtstamp(adapter);
5774 if (ret_val)
5775 return ret_val;
5776
5777 config = adapter->hwtstamp_config;
5778
5779 switch (config.rx_filter) {
5780 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5781 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5782 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5783 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5784 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5785 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5786 /* With V2 type filters which specify a Sync or Delay Request,
5787 * Path Delay Request/Response messages are also time stamped
5788 * by hardware so notify the caller the requested packets plus
5789 * some others are time stamped.
5790 */
5791 config.rx_filter = HWTSTAMP_FILTER_SOME;
5792 break;
5793 default:
5794 break;
5795 }
5796
5797 return copy_to_user(ifr->ifr_data, &config,
5798 sizeof(config)) ? -EFAULT : 0;
5799 }
5800
5801 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5802 {
5803 switch (cmd) {
5804 case SIOCGMIIPHY:
5805 case SIOCGMIIREG:
5806 case SIOCSMIIREG:
5807 return e1000_mii_ioctl(netdev, ifr, cmd);
5808 case SIOCSHWTSTAMP:
5809 return e1000e_hwtstamp_ioctl(netdev, ifr);
5810 default:
5811 return -EOPNOTSUPP;
5812 }
5813 }
5814
5815 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5816 {
5817 struct e1000_hw *hw = &adapter->hw;
5818 u32 i, mac_reg;
5819 u16 phy_reg, wuc_enable;
5820 int retval;
5821
5822 /* copy MAC RARs to PHY RARs */
5823 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
5824
5825 retval = hw->phy.ops.acquire(hw);
5826 if (retval) {
5827 e_err("Could not acquire PHY\n");
5828 return retval;
5829 }
5830
5831 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5832 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5833 if (retval)
5834 goto release;
5835
5836 /* copy MAC MTA to PHY MTA - only needed for pchlan */
5837 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5838 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
5839 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5840 (u16)(mac_reg & 0xFFFF));
5841 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5842 (u16)((mac_reg >> 16) & 0xFFFF));
5843 }
5844
5845 /* configure PHY Rx Control register */
5846 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
5847 mac_reg = er32(RCTL);
5848 if (mac_reg & E1000_RCTL_UPE)
5849 phy_reg |= BM_RCTL_UPE;
5850 if (mac_reg & E1000_RCTL_MPE)
5851 phy_reg |= BM_RCTL_MPE;
5852 phy_reg &= ~(BM_RCTL_MO_MASK);
5853 if (mac_reg & E1000_RCTL_MO_3)
5854 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
5855 << BM_RCTL_MO_SHIFT);
5856 if (mac_reg & E1000_RCTL_BAM)
5857 phy_reg |= BM_RCTL_BAM;
5858 if (mac_reg & E1000_RCTL_PMCF)
5859 phy_reg |= BM_RCTL_PMCF;
5860 mac_reg = er32(CTRL);
5861 if (mac_reg & E1000_CTRL_RFCE)
5862 phy_reg |= BM_RCTL_RFCE;
5863 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
5864
5865 /* enable PHY wakeup in MAC register */
5866 ew32(WUFC, wufc);
5867 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5868
5869 /* configure and enable PHY wakeup in PHY registers */
5870 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5871 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
5872
5873 /* activate PHY wakeup */
5874 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5875 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5876 if (retval)
5877 e_err("Could not set PHY Host Wakeup bit\n");
5878 release:
5879 hw->phy.ops.release(hw);
5880
5881 return retval;
5882 }
5883
5884 static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
5885 bool runtime)
5886 {
5887 struct net_device *netdev = pci_get_drvdata(pdev);
5888 struct e1000_adapter *adapter = netdev_priv(netdev);
5889 struct e1000_hw *hw = &adapter->hw;
5890 u32 ctrl, ctrl_ext, rctl, status;
5891 /* Runtime suspend should only enable wakeup for link changes */
5892 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
5893 int retval = 0;
5894
5895 netif_device_detach(netdev);
5896
5897 if (netif_running(netdev)) {
5898 int count = E1000_CHECK_RESET_COUNT;
5899
5900 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
5901 usleep_range(10000, 20000);
5902
5903 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5904 e1000e_down(adapter);
5905 e1000_free_irq(adapter);
5906 }
5907 e1000e_reset_interrupt_capability(adapter);
5908
5909 retval = pci_save_state(pdev);
5910 if (retval)
5911 return retval;
5912
5913 status = er32(STATUS);
5914 if (status & E1000_STATUS_LU)
5915 wufc &= ~E1000_WUFC_LNKC;
5916
5917 if (wufc) {
5918 e1000_setup_rctl(adapter);
5919 e1000e_set_rx_mode(netdev);
5920
5921 /* turn on all-multi mode if wake on multicast is enabled */
5922 if (wufc & E1000_WUFC_MC) {
5923 rctl = er32(RCTL);
5924 rctl |= E1000_RCTL_MPE;
5925 ew32(RCTL, rctl);
5926 }
5927
5928 ctrl = er32(CTRL);
5929 /* advertise wake from D3Cold */
5930 #define E1000_CTRL_ADVD3WUC 0x00100000
5931 /* phy power management enable */
5932 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5933 ctrl |= E1000_CTRL_ADVD3WUC;
5934 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5935 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
5936 ew32(CTRL, ctrl);
5937
5938 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5939 adapter->hw.phy.media_type ==
5940 e1000_media_type_internal_serdes) {
5941 /* keep the laser running in D3 */
5942 ctrl_ext = er32(CTRL_EXT);
5943 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
5944 ew32(CTRL_EXT, ctrl_ext);
5945 }
5946
5947 if (adapter->flags & FLAG_IS_ICH)
5948 e1000_suspend_workarounds_ich8lan(&adapter->hw);
5949
5950 /* Allow time for pending master requests to run */
5951 e1000e_disable_pcie_master(&adapter->hw);
5952
5953 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
5954 /* enable wakeup by the PHY */
5955 retval = e1000_init_phy_wakeup(adapter, wufc);
5956 if (retval)
5957 return retval;
5958 } else {
5959 /* enable wakeup by the MAC */
5960 ew32(WUFC, wufc);
5961 ew32(WUC, E1000_WUC_PME_EN);
5962 }
5963 } else {
5964 ew32(WUC, 0);
5965 ew32(WUFC, 0);
5966 }
5967
5968 *enable_wake = !!wufc;
5969
5970 /* make sure adapter isn't asleep if manageability is enabled */
5971 if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
5972 (hw->mac.ops.check_mng_mode(hw)))
5973 *enable_wake = true;
5974
5975 if (adapter->hw.phy.type == e1000_phy_igp_3)
5976 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5977
5978 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5979 * would have already happened in close and is redundant.
5980 */
5981 e1000e_release_hw_control(adapter);
5982
5983 pci_disable_device(pdev);
5984
5985 return 0;
5986 }
5987
5988 static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
5989 {
5990 if (sleep && wake) {
5991 pci_prepare_to_sleep(pdev);
5992 return;
5993 }
5994
5995 pci_wake_from_d3(pdev, wake);
5996 pci_set_power_state(pdev, PCI_D3hot);
5997 }
5998
5999 static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
6000 bool wake)
6001 {
6002 struct net_device *netdev = pci_get_drvdata(pdev);
6003 struct e1000_adapter *adapter = netdev_priv(netdev);
6004
6005 /* The pci-e switch on some quad port adapters will report a
6006 * correctable error when the MAC transitions from D0 to D3. To
6007 * prevent this we need to mask off the correctable errors on the
6008 * downstream port of the pci-e switch.
6009 */
6010 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6011 struct pci_dev *us_dev = pdev->bus->self;
6012 u16 devctl;
6013
6014 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6015 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6016 (devctl & ~PCI_EXP_DEVCTL_CERE));
6017
6018 e1000_power_off(pdev, sleep, wake);
6019
6020 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
6021 } else {
6022 e1000_power_off(pdev, sleep, wake);
6023 }
6024 }
6025
6026 #ifdef CONFIG_PCIEASPM
6027 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6028 {
6029 pci_disable_link_state_locked(pdev, state);
6030 }
6031 #else
6032 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6033 {
6034 u16 aspm_ctl = 0;
6035
6036 if (state & PCIE_LINK_STATE_L0S)
6037 aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L0S;
6038 if (state & PCIE_LINK_STATE_L1)
6039 aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L1;
6040
6041 /* Both device and parent should have the same ASPM setting.
6042 * Disable ASPM in downstream component first and then upstream.
6043 */
6044 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_ctl);
6045
6046 if (pdev->bus->self)
6047 pcie_capability_clear_word(pdev->bus->self, PCI_EXP_LNKCTL,
6048 aspm_ctl);
6049 }
6050 #endif
6051 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6052 {
6053 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6054 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
6055 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
6056
6057 __e1000e_disable_aspm(pdev, state);
6058 }
6059
6060 #ifdef CONFIG_PM
6061 static bool e1000e_pm_ready(struct e1000_adapter *adapter)
6062 {
6063 return !!adapter->tx_ring->buffer_info;
6064 }
6065
6066 static int __e1000_resume(struct pci_dev *pdev)
6067 {
6068 struct net_device *netdev = pci_get_drvdata(pdev);
6069 struct e1000_adapter *adapter = netdev_priv(netdev);
6070 struct e1000_hw *hw = &adapter->hw;
6071 u16 aspm_disable_flag = 0;
6072 u32 err;
6073
6074 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6075 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6076 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6077 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6078 if (aspm_disable_flag)
6079 e1000e_disable_aspm(pdev, aspm_disable_flag);
6080
6081 pci_set_power_state(pdev, PCI_D0);
6082 pci_restore_state(pdev);
6083 pci_save_state(pdev);
6084
6085 e1000e_set_interrupt_capability(adapter);
6086 if (netif_running(netdev)) {
6087 err = e1000_request_irq(adapter);
6088 if (err)
6089 return err;
6090 }
6091
6092 if (hw->mac.type >= e1000_pch2lan)
6093 e1000_resume_workarounds_pchlan(&adapter->hw);
6094
6095 e1000e_power_up_phy(adapter);
6096
6097 /* report the system wakeup cause from S3/S4 */
6098 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6099 u16 phy_data;
6100
6101 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6102 if (phy_data) {
6103 e_info("PHY Wakeup cause - %s\n",
6104 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6105 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6106 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6107 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6108 phy_data & E1000_WUS_LNKC ?
6109 "Link Status Change" : "other");
6110 }
6111 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6112 } else {
6113 u32 wus = er32(WUS);
6114 if (wus) {
6115 e_info("MAC Wakeup cause - %s\n",
6116 wus & E1000_WUS_EX ? "Unicast Packet" :
6117 wus & E1000_WUS_MC ? "Multicast Packet" :
6118 wus & E1000_WUS_BC ? "Broadcast Packet" :
6119 wus & E1000_WUS_MAG ? "Magic Packet" :
6120 wus & E1000_WUS_LNKC ? "Link Status Change" :
6121 "other");
6122 }
6123 ew32(WUS, ~0);
6124 }
6125
6126 e1000e_reset(adapter);
6127
6128 e1000_init_manageability_pt(adapter);
6129
6130 if (netif_running(netdev))
6131 e1000e_up(adapter);
6132
6133 netif_device_attach(netdev);
6134
6135 /* If the controller has AMT, do not set DRV_LOAD until the interface
6136 * is up. For all other cases, let the f/w know that the h/w is now
6137 * under the control of the driver.
6138 */
6139 if (!(adapter->flags & FLAG_HAS_AMT))
6140 e1000e_get_hw_control(adapter);
6141
6142 return 0;
6143 }
6144
6145 #ifdef CONFIG_PM_SLEEP
6146 static int e1000_suspend(struct device *dev)
6147 {
6148 struct pci_dev *pdev = to_pci_dev(dev);
6149 int retval;
6150 bool wake;
6151
6152 retval = __e1000_shutdown(pdev, &wake, false);
6153 if (!retval)
6154 e1000_complete_shutdown(pdev, true, wake);
6155
6156 return retval;
6157 }
6158
6159 static int e1000_resume(struct device *dev)
6160 {
6161 struct pci_dev *pdev = to_pci_dev(dev);
6162 struct net_device *netdev = pci_get_drvdata(pdev);
6163 struct e1000_adapter *adapter = netdev_priv(netdev);
6164
6165 if (e1000e_pm_ready(adapter))
6166 adapter->idle_check = true;
6167
6168 return __e1000_resume(pdev);
6169 }
6170 #endif /* CONFIG_PM_SLEEP */
6171
6172 #ifdef CONFIG_PM_RUNTIME
6173 static int e1000_runtime_suspend(struct device *dev)
6174 {
6175 struct pci_dev *pdev = to_pci_dev(dev);
6176 struct net_device *netdev = pci_get_drvdata(pdev);
6177 struct e1000_adapter *adapter = netdev_priv(netdev);
6178
6179 if (e1000e_pm_ready(adapter)) {
6180 bool wake;
6181
6182 __e1000_shutdown(pdev, &wake, true);
6183 }
6184
6185 return 0;
6186 }
6187
6188 static int e1000_idle(struct device *dev)
6189 {
6190 struct pci_dev *pdev = to_pci_dev(dev);
6191 struct net_device *netdev = pci_get_drvdata(pdev);
6192 struct e1000_adapter *adapter = netdev_priv(netdev);
6193
6194 if (!e1000e_pm_ready(adapter))
6195 return 0;
6196
6197 if (adapter->idle_check) {
6198 adapter->idle_check = false;
6199 if (!e1000e_has_link(adapter))
6200 pm_schedule_suspend(dev, MSEC_PER_SEC);
6201 }
6202
6203 return -EBUSY;
6204 }
6205
6206 static int e1000_runtime_resume(struct device *dev)
6207 {
6208 struct pci_dev *pdev = to_pci_dev(dev);
6209 struct net_device *netdev = pci_get_drvdata(pdev);
6210 struct e1000_adapter *adapter = netdev_priv(netdev);
6211
6212 if (!e1000e_pm_ready(adapter))
6213 return 0;
6214
6215 adapter->idle_check = !dev->power.runtime_auto;
6216 return __e1000_resume(pdev);
6217 }
6218 #endif /* CONFIG_PM_RUNTIME */
6219 #endif /* CONFIG_PM */
6220
6221 static void e1000_shutdown(struct pci_dev *pdev)
6222 {
6223 bool wake = false;
6224
6225 __e1000_shutdown(pdev, &wake, false);
6226
6227 if (system_state == SYSTEM_POWER_OFF)
6228 e1000_complete_shutdown(pdev, false, wake);
6229 }
6230
6231 #ifdef CONFIG_NET_POLL_CONTROLLER
6232
6233 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
6234 {
6235 struct net_device *netdev = data;
6236 struct e1000_adapter *adapter = netdev_priv(netdev);
6237
6238 if (adapter->msix_entries) {
6239 int vector, msix_irq;
6240
6241 vector = 0;
6242 msix_irq = adapter->msix_entries[vector].vector;
6243 disable_irq(msix_irq);
6244 e1000_intr_msix_rx(msix_irq, netdev);
6245 enable_irq(msix_irq);
6246
6247 vector++;
6248 msix_irq = adapter->msix_entries[vector].vector;
6249 disable_irq(msix_irq);
6250 e1000_intr_msix_tx(msix_irq, netdev);
6251 enable_irq(msix_irq);
6252
6253 vector++;
6254 msix_irq = adapter->msix_entries[vector].vector;
6255 disable_irq(msix_irq);
6256 e1000_msix_other(msix_irq, netdev);
6257 enable_irq(msix_irq);
6258 }
6259
6260 return IRQ_HANDLED;
6261 }
6262
6263 /**
6264 * e1000_netpoll
6265 * @netdev: network interface device structure
6266 *
6267 * Polling 'interrupt' - used by things like netconsole to send skbs
6268 * without having to re-enable interrupts. It's not called while
6269 * the interrupt routine is executing.
6270 */
6271 static void e1000_netpoll(struct net_device *netdev)
6272 {
6273 struct e1000_adapter *adapter = netdev_priv(netdev);
6274
6275 switch (adapter->int_mode) {
6276 case E1000E_INT_MODE_MSIX:
6277 e1000_intr_msix(adapter->pdev->irq, netdev);
6278 break;
6279 case E1000E_INT_MODE_MSI:
6280 disable_irq(adapter->pdev->irq);
6281 e1000_intr_msi(adapter->pdev->irq, netdev);
6282 enable_irq(adapter->pdev->irq);
6283 break;
6284 default: /* E1000E_INT_MODE_LEGACY */
6285 disable_irq(adapter->pdev->irq);
6286 e1000_intr(adapter->pdev->irq, netdev);
6287 enable_irq(adapter->pdev->irq);
6288 break;
6289 }
6290 }
6291 #endif
6292
6293 /**
6294 * e1000_io_error_detected - called when PCI error is detected
6295 * @pdev: Pointer to PCI device
6296 * @state: The current pci connection state
6297 *
6298 * This function is called after a PCI bus error affecting
6299 * this device has been detected.
6300 */
6301 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6302 pci_channel_state_t state)
6303 {
6304 struct net_device *netdev = pci_get_drvdata(pdev);
6305 struct e1000_adapter *adapter = netdev_priv(netdev);
6306
6307 netif_device_detach(netdev);
6308
6309 if (state == pci_channel_io_perm_failure)
6310 return PCI_ERS_RESULT_DISCONNECT;
6311
6312 if (netif_running(netdev))
6313 e1000e_down(adapter);
6314 pci_disable_device(pdev);
6315
6316 /* Request a slot slot reset. */
6317 return PCI_ERS_RESULT_NEED_RESET;
6318 }
6319
6320 /**
6321 * e1000_io_slot_reset - called after the pci bus has been reset.
6322 * @pdev: Pointer to PCI device
6323 *
6324 * Restart the card from scratch, as if from a cold-boot. Implementation
6325 * resembles the first-half of the e1000_resume routine.
6326 */
6327 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6328 {
6329 struct net_device *netdev = pci_get_drvdata(pdev);
6330 struct e1000_adapter *adapter = netdev_priv(netdev);
6331 struct e1000_hw *hw = &adapter->hw;
6332 u16 aspm_disable_flag = 0;
6333 int err;
6334 pci_ers_result_t result;
6335
6336 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6337 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6338 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6339 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6340 if (aspm_disable_flag)
6341 e1000e_disable_aspm(pdev, aspm_disable_flag);
6342
6343 err = pci_enable_device_mem(pdev);
6344 if (err) {
6345 dev_err(&pdev->dev,
6346 "Cannot re-enable PCI device after reset.\n");
6347 result = PCI_ERS_RESULT_DISCONNECT;
6348 } else {
6349 pci_set_master(pdev);
6350 pdev->state_saved = true;
6351 pci_restore_state(pdev);
6352
6353 pci_enable_wake(pdev, PCI_D3hot, 0);
6354 pci_enable_wake(pdev, PCI_D3cold, 0);
6355
6356 e1000e_reset(adapter);
6357 ew32(WUS, ~0);
6358 result = PCI_ERS_RESULT_RECOVERED;
6359 }
6360
6361 pci_cleanup_aer_uncorrect_error_status(pdev);
6362
6363 return result;
6364 }
6365
6366 /**
6367 * e1000_io_resume - called when traffic can start flowing again.
6368 * @pdev: Pointer to PCI device
6369 *
6370 * This callback is called when the error recovery driver tells us that
6371 * its OK to resume normal operation. Implementation resembles the
6372 * second-half of the e1000_resume routine.
6373 */
6374 static void e1000_io_resume(struct pci_dev *pdev)
6375 {
6376 struct net_device *netdev = pci_get_drvdata(pdev);
6377 struct e1000_adapter *adapter = netdev_priv(netdev);
6378
6379 e1000_init_manageability_pt(adapter);
6380
6381 if (netif_running(netdev)) {
6382 if (e1000e_up(adapter)) {
6383 dev_err(&pdev->dev,
6384 "can't bring device back up after reset\n");
6385 return;
6386 }
6387 }
6388
6389 netif_device_attach(netdev);
6390
6391 /* If the controller has AMT, do not set DRV_LOAD until the interface
6392 * is up. For all other cases, let the f/w know that the h/w is now
6393 * under the control of the driver.
6394 */
6395 if (!(adapter->flags & FLAG_HAS_AMT))
6396 e1000e_get_hw_control(adapter);
6397
6398 }
6399
6400 static void e1000_print_device_info(struct e1000_adapter *adapter)
6401 {
6402 struct e1000_hw *hw = &adapter->hw;
6403 struct net_device *netdev = adapter->netdev;
6404 u32 ret_val;
6405 u8 pba_str[E1000_PBANUM_LENGTH];
6406
6407 /* print bus type/speed/width info */
6408 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
6409 /* bus width */
6410 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
6411 "Width x1"),
6412 /* MAC address */
6413 netdev->dev_addr);
6414 e_info("Intel(R) PRO/%s Network Connection\n",
6415 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
6416 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6417 E1000_PBANUM_LENGTH);
6418 if (ret_val)
6419 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
6420 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6421 hw->mac.type, hw->phy.type, pba_str);
6422 }
6423
6424 static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6425 {
6426 struct e1000_hw *hw = &adapter->hw;
6427 int ret_val;
6428 u16 buf = 0;
6429
6430 if (hw->mac.type != e1000_82573)
6431 return;
6432
6433 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
6434 le16_to_cpus(&buf);
6435 if (!ret_val && (!(buf & (1 << 0)))) {
6436 /* Deep Smart Power Down (DSPD) */
6437 dev_warn(&adapter->pdev->dev,
6438 "Warning: detected DSPD enabled in EEPROM\n");
6439 }
6440 }
6441
6442 static int e1000_set_features(struct net_device *netdev,
6443 netdev_features_t features)
6444 {
6445 struct e1000_adapter *adapter = netdev_priv(netdev);
6446 netdev_features_t changed = features ^ netdev->features;
6447
6448 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6449 adapter->flags |= FLAG_TSO_FORCE;
6450
6451 if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX |
6452 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6453 NETIF_F_RXALL)))
6454 return 0;
6455
6456 if (changed & NETIF_F_RXFCS) {
6457 if (features & NETIF_F_RXFCS) {
6458 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6459 } else {
6460 /* We need to take it back to defaults, which might mean
6461 * stripping is still disabled at the adapter level.
6462 */
6463 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6464 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6465 else
6466 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6467 }
6468 }
6469
6470 netdev->features = features;
6471
6472 if (netif_running(netdev))
6473 e1000e_reinit_locked(adapter);
6474 else
6475 e1000e_reset(adapter);
6476
6477 return 0;
6478 }
6479
6480 static const struct net_device_ops e1000e_netdev_ops = {
6481 .ndo_open = e1000_open,
6482 .ndo_stop = e1000_close,
6483 .ndo_start_xmit = e1000_xmit_frame,
6484 .ndo_get_stats64 = e1000e_get_stats64,
6485 .ndo_set_rx_mode = e1000e_set_rx_mode,
6486 .ndo_set_mac_address = e1000_set_mac,
6487 .ndo_change_mtu = e1000_change_mtu,
6488 .ndo_do_ioctl = e1000_ioctl,
6489 .ndo_tx_timeout = e1000_tx_timeout,
6490 .ndo_validate_addr = eth_validate_addr,
6491
6492 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6493 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6494 #ifdef CONFIG_NET_POLL_CONTROLLER
6495 .ndo_poll_controller = e1000_netpoll,
6496 #endif
6497 .ndo_set_features = e1000_set_features,
6498 };
6499
6500 /**
6501 * e1000_probe - Device Initialization Routine
6502 * @pdev: PCI device information struct
6503 * @ent: entry in e1000_pci_tbl
6504 *
6505 * Returns 0 on success, negative on failure
6506 *
6507 * e1000_probe initializes an adapter identified by a pci_dev structure.
6508 * The OS initialization, configuring of the adapter private structure,
6509 * and a hardware reset occur.
6510 **/
6511 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
6512 {
6513 struct net_device *netdev;
6514 struct e1000_adapter *adapter;
6515 struct e1000_hw *hw;
6516 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
6517 resource_size_t mmio_start, mmio_len;
6518 resource_size_t flash_start, flash_len;
6519 static int cards_found;
6520 u16 aspm_disable_flag = 0;
6521 int i, err, pci_using_dac;
6522 u16 eeprom_data = 0;
6523 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6524
6525 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6526 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6527 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
6528 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6529 if (aspm_disable_flag)
6530 e1000e_disable_aspm(pdev, aspm_disable_flag);
6531
6532 err = pci_enable_device_mem(pdev);
6533 if (err)
6534 return err;
6535
6536 pci_using_dac = 0;
6537 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
6538 if (!err) {
6539 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
6540 if (!err)
6541 pci_using_dac = 1;
6542 } else {
6543 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6544 if (err) {
6545 err = dma_set_coherent_mask(&pdev->dev,
6546 DMA_BIT_MASK(32));
6547 if (err) {
6548 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
6549 goto err_dma;
6550 }
6551 }
6552 }
6553
6554 err = pci_request_selected_regions_exclusive(pdev,
6555 pci_select_bars(pdev, IORESOURCE_MEM),
6556 e1000e_driver_name);
6557 if (err)
6558 goto err_pci_reg;
6559
6560 /* AER (Advanced Error Reporting) hooks */
6561 pci_enable_pcie_error_reporting(pdev);
6562
6563 pci_set_master(pdev);
6564 /* PCI config space info */
6565 err = pci_save_state(pdev);
6566 if (err)
6567 goto err_alloc_etherdev;
6568
6569 err = -ENOMEM;
6570 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6571 if (!netdev)
6572 goto err_alloc_etherdev;
6573
6574 SET_NETDEV_DEV(netdev, &pdev->dev);
6575
6576 netdev->irq = pdev->irq;
6577
6578 pci_set_drvdata(pdev, netdev);
6579 adapter = netdev_priv(netdev);
6580 hw = &adapter->hw;
6581 adapter->netdev = netdev;
6582 adapter->pdev = pdev;
6583 adapter->ei = ei;
6584 adapter->pba = ei->pba;
6585 adapter->flags = ei->flags;
6586 adapter->flags2 = ei->flags2;
6587 adapter->hw.adapter = adapter;
6588 adapter->hw.mac.type = ei->mac;
6589 adapter->max_hw_frame_size = ei->max_hw_frame_size;
6590 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
6591
6592 mmio_start = pci_resource_start(pdev, 0);
6593 mmio_len = pci_resource_len(pdev, 0);
6594
6595 err = -EIO;
6596 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6597 if (!adapter->hw.hw_addr)
6598 goto err_ioremap;
6599
6600 if ((adapter->flags & FLAG_HAS_FLASH) &&
6601 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6602 flash_start = pci_resource_start(pdev, 1);
6603 flash_len = pci_resource_len(pdev, 1);
6604 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6605 if (!adapter->hw.flash_address)
6606 goto err_flashmap;
6607 }
6608
6609 /* construct the net_device struct */
6610 netdev->netdev_ops = &e1000e_netdev_ops;
6611 e1000e_set_ethtool_ops(netdev);
6612 netdev->watchdog_timeo = 5 * HZ;
6613 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
6614 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
6615
6616 netdev->mem_start = mmio_start;
6617 netdev->mem_end = mmio_start + mmio_len;
6618
6619 adapter->bd_number = cards_found++;
6620
6621 e1000e_check_options(adapter);
6622
6623 /* setup adapter struct */
6624 err = e1000_sw_init(adapter);
6625 if (err)
6626 goto err_sw_init;
6627
6628 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6629 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6630 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6631
6632 err = ei->get_variants(adapter);
6633 if (err)
6634 goto err_hw_init;
6635
6636 if ((adapter->flags & FLAG_IS_ICH) &&
6637 (adapter->flags & FLAG_READ_ONLY_NVM))
6638 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6639
6640 hw->mac.ops.get_bus_info(&adapter->hw);
6641
6642 adapter->hw.phy.autoneg_wait_to_complete = 0;
6643
6644 /* Copper options */
6645 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
6646 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6647 adapter->hw.phy.disable_polarity_correction = 0;
6648 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6649 }
6650
6651 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
6652 dev_info(&pdev->dev,
6653 "PHY reset is blocked due to SOL/IDER session.\n");
6654
6655 /* Set initial default active device features */
6656 netdev->features = (NETIF_F_SG |
6657 NETIF_F_HW_VLAN_RX |
6658 NETIF_F_HW_VLAN_TX |
6659 NETIF_F_TSO |
6660 NETIF_F_TSO6 |
6661 NETIF_F_RXHASH |
6662 NETIF_F_RXCSUM |
6663 NETIF_F_HW_CSUM);
6664
6665 /* Set user-changeable features (subset of all device features) */
6666 netdev->hw_features = netdev->features;
6667 netdev->hw_features |= NETIF_F_RXFCS;
6668 netdev->priv_flags |= IFF_SUPP_NOFCS;
6669 netdev->hw_features |= NETIF_F_RXALL;
6670
6671 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
6672 netdev->features |= NETIF_F_HW_VLAN_FILTER;
6673
6674 netdev->vlan_features |= (NETIF_F_SG |
6675 NETIF_F_TSO |
6676 NETIF_F_TSO6 |
6677 NETIF_F_HW_CSUM);
6678
6679 netdev->priv_flags |= IFF_UNICAST_FLT;
6680
6681 if (pci_using_dac) {
6682 netdev->features |= NETIF_F_HIGHDMA;
6683 netdev->vlan_features |= NETIF_F_HIGHDMA;
6684 }
6685
6686 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6687 adapter->flags |= FLAG_MNG_PT_ENABLED;
6688
6689 /* before reading the NVM, reset the controller to
6690 * put the device in a known good starting state
6691 */
6692 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6693
6694 /* systems with ASPM and others may see the checksum fail on the first
6695 * attempt. Let's give it a few tries
6696 */
6697 for (i = 0;; i++) {
6698 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6699 break;
6700 if (i == 2) {
6701 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
6702 err = -EIO;
6703 goto err_eeprom;
6704 }
6705 }
6706
6707 e1000_eeprom_checks(adapter);
6708
6709 /* copy the MAC address */
6710 if (e1000e_read_mac_addr(&adapter->hw))
6711 dev_err(&pdev->dev,
6712 "NVM Read Error while reading MAC address\n");
6713
6714 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
6715
6716 if (!is_valid_ether_addr(netdev->dev_addr)) {
6717 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
6718 netdev->dev_addr);
6719 err = -EIO;
6720 goto err_eeprom;
6721 }
6722
6723 init_timer(&adapter->watchdog_timer);
6724 adapter->watchdog_timer.function = e1000_watchdog;
6725 adapter->watchdog_timer.data = (unsigned long) adapter;
6726
6727 init_timer(&adapter->phy_info_timer);
6728 adapter->phy_info_timer.function = e1000_update_phy_info;
6729 adapter->phy_info_timer.data = (unsigned long) adapter;
6730
6731 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6732 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
6733 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6734 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
6735 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
6736
6737 /* Initialize link parameters. User can change them with ethtool */
6738 adapter->hw.mac.autoneg = 1;
6739 adapter->fc_autoneg = true;
6740 adapter->hw.fc.requested_mode = e1000_fc_default;
6741 adapter->hw.fc.current_mode = e1000_fc_default;
6742 adapter->hw.phy.autoneg_advertised = 0x2f;
6743
6744 /* ring size defaults */
6745 adapter->rx_ring->count = E1000_DEFAULT_RXD;
6746 adapter->tx_ring->count = E1000_DEFAULT_TXD;
6747
6748 /* Initial Wake on LAN setting - If APM wake is enabled in
6749 * the EEPROM, enable the ACPI Magic Packet filter
6750 */
6751 if (adapter->flags & FLAG_APME_IN_WUC) {
6752 /* APME bit in EEPROM is mapped to WUC.APME */
6753 eeprom_data = er32(WUC);
6754 eeprom_apme_mask = E1000_WUC_APME;
6755 if ((hw->mac.type > e1000_ich10lan) &&
6756 (eeprom_data & E1000_WUC_PHY_WAKE))
6757 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
6758 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6759 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6760 (adapter->hw.bus.func == 1))
6761 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
6762 1, &eeprom_data);
6763 else
6764 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
6765 1, &eeprom_data);
6766 }
6767
6768 /* fetch WoL from EEPROM */
6769 if (eeprom_data & eeprom_apme_mask)
6770 adapter->eeprom_wol |= E1000_WUFC_MAG;
6771
6772 /* now that we have the eeprom settings, apply the special cases
6773 * where the eeprom may be wrong or the board simply won't support
6774 * wake on lan on a particular port
6775 */
6776 if (!(adapter->flags & FLAG_HAS_WOL))
6777 adapter->eeprom_wol = 0;
6778
6779 /* initialize the wol settings based on the eeprom settings */
6780 adapter->wol = adapter->eeprom_wol;
6781 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6782
6783 /* save off EEPROM version number */
6784 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6785
6786 /* reset the hardware with the new settings */
6787 e1000e_reset(adapter);
6788
6789 /* If the controller has AMT, do not set DRV_LOAD until the interface
6790 * is up. For all other cases, let the f/w know that the h/w is now
6791 * under the control of the driver.
6792 */
6793 if (!(adapter->flags & FLAG_HAS_AMT))
6794 e1000e_get_hw_control(adapter);
6795
6796 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
6797 err = register_netdev(netdev);
6798 if (err)
6799 goto err_register;
6800
6801 /* carrier off reporting is important to ethtool even BEFORE open */
6802 netif_carrier_off(netdev);
6803
6804 /* init PTP hardware clock */
6805 e1000e_ptp_init(adapter);
6806
6807 e1000_print_device_info(adapter);
6808
6809 if (pci_dev_run_wake(pdev))
6810 pm_runtime_put_noidle(&pdev->dev);
6811
6812 return 0;
6813
6814 err_register:
6815 if (!(adapter->flags & FLAG_HAS_AMT))
6816 e1000e_release_hw_control(adapter);
6817 err_eeprom:
6818 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
6819 e1000_phy_hw_reset(&adapter->hw);
6820 err_hw_init:
6821 kfree(adapter->tx_ring);
6822 kfree(adapter->rx_ring);
6823 err_sw_init:
6824 if (adapter->hw.flash_address)
6825 iounmap(adapter->hw.flash_address);
6826 e1000e_reset_interrupt_capability(adapter);
6827 err_flashmap:
6828 iounmap(adapter->hw.hw_addr);
6829 err_ioremap:
6830 free_netdev(netdev);
6831 err_alloc_etherdev:
6832 pci_release_selected_regions(pdev,
6833 pci_select_bars(pdev, IORESOURCE_MEM));
6834 err_pci_reg:
6835 err_dma:
6836 pci_disable_device(pdev);
6837 return err;
6838 }
6839
6840 /**
6841 * e1000_remove - Device Removal Routine
6842 * @pdev: PCI device information struct
6843 *
6844 * e1000_remove is called by the PCI subsystem to alert the driver
6845 * that it should release a PCI device. The could be caused by a
6846 * Hot-Plug event, or because the driver is going to be removed from
6847 * memory.
6848 **/
6849 static void e1000_remove(struct pci_dev *pdev)
6850 {
6851 struct net_device *netdev = pci_get_drvdata(pdev);
6852 struct e1000_adapter *adapter = netdev_priv(netdev);
6853 bool down = test_bit(__E1000_DOWN, &adapter->state);
6854
6855 e1000e_ptp_remove(adapter);
6856
6857 /* The timers may be rescheduled, so explicitly disable them
6858 * from being rescheduled.
6859 */
6860 if (!down)
6861 set_bit(__E1000_DOWN, &adapter->state);
6862 del_timer_sync(&adapter->watchdog_timer);
6863 del_timer_sync(&adapter->phy_info_timer);
6864
6865 cancel_work_sync(&adapter->reset_task);
6866 cancel_work_sync(&adapter->watchdog_task);
6867 cancel_work_sync(&adapter->downshift_task);
6868 cancel_work_sync(&adapter->update_phy_task);
6869 cancel_work_sync(&adapter->print_hang_task);
6870
6871 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
6872 cancel_work_sync(&adapter->tx_hwtstamp_work);
6873 if (adapter->tx_hwtstamp_skb) {
6874 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
6875 adapter->tx_hwtstamp_skb = NULL;
6876 }
6877 }
6878
6879 if (!(netdev->flags & IFF_UP))
6880 e1000_power_down_phy(adapter);
6881
6882 /* Don't lie to e1000_close() down the road. */
6883 if (!down)
6884 clear_bit(__E1000_DOWN, &adapter->state);
6885 unregister_netdev(netdev);
6886
6887 if (pci_dev_run_wake(pdev))
6888 pm_runtime_get_noresume(&pdev->dev);
6889
6890 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6891 * would have already happened in close and is redundant.
6892 */
6893 e1000e_release_hw_control(adapter);
6894
6895 e1000e_reset_interrupt_capability(adapter);
6896 kfree(adapter->tx_ring);
6897 kfree(adapter->rx_ring);
6898
6899 iounmap(adapter->hw.hw_addr);
6900 if (adapter->hw.flash_address)
6901 iounmap(adapter->hw.flash_address);
6902 pci_release_selected_regions(pdev,
6903 pci_select_bars(pdev, IORESOURCE_MEM));
6904
6905 free_netdev(netdev);
6906
6907 /* AER disable */
6908 pci_disable_pcie_error_reporting(pdev);
6909
6910 pci_disable_device(pdev);
6911 }
6912
6913 /* PCI Error Recovery (ERS) */
6914 static const struct pci_error_handlers e1000_err_handler = {
6915 .error_detected = e1000_io_error_detected,
6916 .slot_reset = e1000_io_slot_reset,
6917 .resume = e1000_io_resume,
6918 };
6919
6920 static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
6921 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6922 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6923 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
6924 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
6925 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6926 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
6927 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6928 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6929 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
6930
6931 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6932 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6933 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6934 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
6935
6936 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6937 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6938 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
6939
6940 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
6941 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
6942 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
6943
6944 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6945 board_80003es2lan },
6946 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6947 board_80003es2lan },
6948 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6949 board_80003es2lan },
6950 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6951 board_80003es2lan },
6952
6953 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6954 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6955 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6956 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6957 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6958 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6959 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
6960 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
6961
6962 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6963 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6964 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6965 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6966 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
6967 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
6968 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6969 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6970 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6971
6972 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6973 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6974 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
6975
6976 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6977 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
6978 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
6979
6980 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6981 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6982 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
6983 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
6984
6985 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
6986 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
6987
6988 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
6989 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
6990 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
6991 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
6992
6993 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
6994 };
6995 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
6996
6997 #ifdef CONFIG_PM
6998 static const struct dev_pm_ops e1000_pm_ops = {
6999 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
7000 SET_RUNTIME_PM_OPS(e1000_runtime_suspend,
7001 e1000_runtime_resume, e1000_idle)
7002 };
7003 #endif
7004
7005 /* PCI Device API Driver */
7006 static struct pci_driver e1000_driver = {
7007 .name = e1000e_driver_name,
7008 .id_table = e1000_pci_tbl,
7009 .probe = e1000_probe,
7010 .remove = e1000_remove,
7011 #ifdef CONFIG_PM
7012 .driver = {
7013 .pm = &e1000_pm_ops,
7014 },
7015 #endif
7016 .shutdown = e1000_shutdown,
7017 .err_handler = &e1000_err_handler
7018 };
7019
7020 /**
7021 * e1000_init_module - Driver Registration Routine
7022 *
7023 * e1000_init_module is the first routine called when the driver is
7024 * loaded. All it does is register with the PCI subsystem.
7025 **/
7026 static int __init e1000_init_module(void)
7027 {
7028 int ret;
7029 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7030 e1000e_driver_version);
7031 pr_info("Copyright(c) 1999 - 2013 Intel Corporation.\n");
7032 ret = pci_register_driver(&e1000_driver);
7033
7034 return ret;
7035 }
7036 module_init(e1000_init_module);
7037
7038 /**
7039 * e1000_exit_module - Driver Exit Cleanup Routine
7040 *
7041 * e1000_exit_module is called just before the driver is removed
7042 * from memory.
7043 **/
7044 static void __exit e1000_exit_module(void)
7045 {
7046 pci_unregister_driver(&e1000_driver);
7047 }
7048 module_exit(e1000_exit_module);
7049
7050
7051 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7052 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7053 MODULE_LICENSE("GPL");
7054 MODULE_VERSION(DRV_VERSION);
7055
7056 /* netdev.c */
Linux kernel - Deliverables
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