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e1000e: Fix EEE in Sx implementation
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
1 /* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2015 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
21
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23
24 #include <linux/module.h>
25 #include <linux/types.h>
26 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/vmalloc.h>
29 #include <linux/pagemap.h>
30 #include <linux/delay.h>
31 #include <linux/netdevice.h>
32 #include <linux/interrupt.h>
33 #include <linux/tcp.h>
34 #include <linux/ipv6.h>
35 #include <linux/slab.h>
36 #include <net/checksum.h>
37 #include <net/ip6_checksum.h>
38 #include <linux/ethtool.h>
39 #include <linux/if_vlan.h>
40 #include <linux/cpu.h>
41 #include <linux/smp.h>
42 #include <linux/pm_qos.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/aer.h>
45 #include <linux/prefetch.h>
46
47 #include "e1000.h"
48
49 #define DRV_EXTRAVERSION "-k"
50
51 #define DRV_VERSION "3.2.5" DRV_EXTRAVERSION
52 char e1000e_driver_name[] = "e1000e";
53 const char e1000e_driver_version[] = DRV_VERSION;
54
55 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
56 static int debug = -1;
57 module_param(debug, int, 0);
58 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
59
60 static const struct e1000_info *e1000_info_tbl[] = {
61 [board_82571] = &e1000_82571_info,
62 [board_82572] = &e1000_82572_info,
63 [board_82573] = &e1000_82573_info,
64 [board_82574] = &e1000_82574_info,
65 [board_82583] = &e1000_82583_info,
66 [board_80003es2lan] = &e1000_es2_info,
67 [board_ich8lan] = &e1000_ich8_info,
68 [board_ich9lan] = &e1000_ich9_info,
69 [board_ich10lan] = &e1000_ich10_info,
70 [board_pchlan] = &e1000_pch_info,
71 [board_pch2lan] = &e1000_pch2_info,
72 [board_pch_lpt] = &e1000_pch_lpt_info,
73 [board_pch_spt] = &e1000_pch_spt_info,
74 };
75
76 struct e1000_reg_info {
77 u32 ofs;
78 char *name;
79 };
80
81 static const struct e1000_reg_info e1000_reg_info_tbl[] = {
82 /* General Registers */
83 {E1000_CTRL, "CTRL"},
84 {E1000_STATUS, "STATUS"},
85 {E1000_CTRL_EXT, "CTRL_EXT"},
86
87 /* Interrupt Registers */
88 {E1000_ICR, "ICR"},
89
90 /* Rx Registers */
91 {E1000_RCTL, "RCTL"},
92 {E1000_RDLEN(0), "RDLEN"},
93 {E1000_RDH(0), "RDH"},
94 {E1000_RDT(0), "RDT"},
95 {E1000_RDTR, "RDTR"},
96 {E1000_RXDCTL(0), "RXDCTL"},
97 {E1000_ERT, "ERT"},
98 {E1000_RDBAL(0), "RDBAL"},
99 {E1000_RDBAH(0), "RDBAH"},
100 {E1000_RDFH, "RDFH"},
101 {E1000_RDFT, "RDFT"},
102 {E1000_RDFHS, "RDFHS"},
103 {E1000_RDFTS, "RDFTS"},
104 {E1000_RDFPC, "RDFPC"},
105
106 /* Tx Registers */
107 {E1000_TCTL, "TCTL"},
108 {E1000_TDBAL(0), "TDBAL"},
109 {E1000_TDBAH(0), "TDBAH"},
110 {E1000_TDLEN(0), "TDLEN"},
111 {E1000_TDH(0), "TDH"},
112 {E1000_TDT(0), "TDT"},
113 {E1000_TIDV, "TIDV"},
114 {E1000_TXDCTL(0), "TXDCTL"},
115 {E1000_TADV, "TADV"},
116 {E1000_TARC(0), "TARC"},
117 {E1000_TDFH, "TDFH"},
118 {E1000_TDFT, "TDFT"},
119 {E1000_TDFHS, "TDFHS"},
120 {E1000_TDFTS, "TDFTS"},
121 {E1000_TDFPC, "TDFPC"},
122
123 /* List Terminator */
124 {0, NULL}
125 };
126
127 /**
128 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
129 * @hw: pointer to the HW structure
130 *
131 * When updating the MAC CSR registers, the Manageability Engine (ME) could
132 * be accessing the registers at the same time. Normally, this is handled in
133 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
134 * accesses later than it should which could result in the register to have
135 * an incorrect value. Workaround this by checking the FWSM register which
136 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
137 * and try again a number of times.
138 **/
139 s32 __ew32_prepare(struct e1000_hw *hw)
140 {
141 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
142
143 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
144 udelay(50);
145
146 return i;
147 }
148
149 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
150 {
151 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
152 __ew32_prepare(hw);
153
154 writel(val, hw->hw_addr + reg);
155 }
156
157 /**
158 * e1000_regdump - register printout routine
159 * @hw: pointer to the HW structure
160 * @reginfo: pointer to the register info table
161 **/
162 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
163 {
164 int n = 0;
165 char rname[16];
166 u32 regs[8];
167
168 switch (reginfo->ofs) {
169 case E1000_RXDCTL(0):
170 for (n = 0; n < 2; n++)
171 regs[n] = __er32(hw, E1000_RXDCTL(n));
172 break;
173 case E1000_TXDCTL(0):
174 for (n = 0; n < 2; n++)
175 regs[n] = __er32(hw, E1000_TXDCTL(n));
176 break;
177 case E1000_TARC(0):
178 for (n = 0; n < 2; n++)
179 regs[n] = __er32(hw, E1000_TARC(n));
180 break;
181 default:
182 pr_info("%-15s %08x\n",
183 reginfo->name, __er32(hw, reginfo->ofs));
184 return;
185 }
186
187 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
188 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
189 }
190
191 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
192 struct e1000_buffer *bi)
193 {
194 int i;
195 struct e1000_ps_page *ps_page;
196
197 for (i = 0; i < adapter->rx_ps_pages; i++) {
198 ps_page = &bi->ps_pages[i];
199
200 if (ps_page->page) {
201 pr_info("packet dump for ps_page %d:\n", i);
202 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
203 16, 1, page_address(ps_page->page),
204 PAGE_SIZE, true);
205 }
206 }
207 }
208
209 /**
210 * e1000e_dump - Print registers, Tx-ring and Rx-ring
211 * @adapter: board private structure
212 **/
213 static void e1000e_dump(struct e1000_adapter *adapter)
214 {
215 struct net_device *netdev = adapter->netdev;
216 struct e1000_hw *hw = &adapter->hw;
217 struct e1000_reg_info *reginfo;
218 struct e1000_ring *tx_ring = adapter->tx_ring;
219 struct e1000_tx_desc *tx_desc;
220 struct my_u0 {
221 __le64 a;
222 __le64 b;
223 } *u0;
224 struct e1000_buffer *buffer_info;
225 struct e1000_ring *rx_ring = adapter->rx_ring;
226 union e1000_rx_desc_packet_split *rx_desc_ps;
227 union e1000_rx_desc_extended *rx_desc;
228 struct my_u1 {
229 __le64 a;
230 __le64 b;
231 __le64 c;
232 __le64 d;
233 } *u1;
234 u32 staterr;
235 int i = 0;
236
237 if (!netif_msg_hw(adapter))
238 return;
239
240 /* Print netdevice Info */
241 if (netdev) {
242 dev_info(&adapter->pdev->dev, "Net device Info\n");
243 pr_info("Device Name state trans_start last_rx\n");
244 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
245 netdev->state, netdev->trans_start, netdev->last_rx);
246 }
247
248 /* Print Registers */
249 dev_info(&adapter->pdev->dev, "Register Dump\n");
250 pr_info(" Register Name Value\n");
251 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
252 reginfo->name; reginfo++) {
253 e1000_regdump(hw, reginfo);
254 }
255
256 /* Print Tx Ring Summary */
257 if (!netdev || !netif_running(netdev))
258 return;
259
260 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
261 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
262 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
263 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
264 0, tx_ring->next_to_use, tx_ring->next_to_clean,
265 (unsigned long long)buffer_info->dma,
266 buffer_info->length,
267 buffer_info->next_to_watch,
268 (unsigned long long)buffer_info->time_stamp);
269
270 /* Print Tx Ring */
271 if (!netif_msg_tx_done(adapter))
272 goto rx_ring_summary;
273
274 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
275
276 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
277 *
278 * Legacy Transmit Descriptor
279 * +--------------------------------------------------------------+
280 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
281 * +--------------------------------------------------------------+
282 * 8 | Special | CSS | Status | CMD | CSO | Length |
283 * +--------------------------------------------------------------+
284 * 63 48 47 36 35 32 31 24 23 16 15 0
285 *
286 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
287 * 63 48 47 40 39 32 31 16 15 8 7 0
288 * +----------------------------------------------------------------+
289 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
290 * +----------------------------------------------------------------+
291 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
292 * +----------------------------------------------------------------+
293 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
294 *
295 * Extended Data Descriptor (DTYP=0x1)
296 * +----------------------------------------------------------------+
297 * 0 | Buffer Address [63:0] |
298 * +----------------------------------------------------------------+
299 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
300 * +----------------------------------------------------------------+
301 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
302 */
303 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
304 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
305 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
306 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
307 const char *next_desc;
308 tx_desc = E1000_TX_DESC(*tx_ring, i);
309 buffer_info = &tx_ring->buffer_info[i];
310 u0 = (struct my_u0 *)tx_desc;
311 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
312 next_desc = " NTC/U";
313 else if (i == tx_ring->next_to_use)
314 next_desc = " NTU";
315 else if (i == tx_ring->next_to_clean)
316 next_desc = " NTC";
317 else
318 next_desc = "";
319 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
320 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
321 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
322 i,
323 (unsigned long long)le64_to_cpu(u0->a),
324 (unsigned long long)le64_to_cpu(u0->b),
325 (unsigned long long)buffer_info->dma,
326 buffer_info->length, buffer_info->next_to_watch,
327 (unsigned long long)buffer_info->time_stamp,
328 buffer_info->skb, next_desc);
329
330 if (netif_msg_pktdata(adapter) && buffer_info->skb)
331 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
332 16, 1, buffer_info->skb->data,
333 buffer_info->skb->len, true);
334 }
335
336 /* Print Rx Ring Summary */
337 rx_ring_summary:
338 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
339 pr_info("Queue [NTU] [NTC]\n");
340 pr_info(" %5d %5X %5X\n",
341 0, rx_ring->next_to_use, rx_ring->next_to_clean);
342
343 /* Print Rx Ring */
344 if (!netif_msg_rx_status(adapter))
345 return;
346
347 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
348 switch (adapter->rx_ps_pages) {
349 case 1:
350 case 2:
351 case 3:
352 /* [Extended] Packet Split Receive Descriptor Format
353 *
354 * +-----------------------------------------------------+
355 * 0 | Buffer Address 0 [63:0] |
356 * +-----------------------------------------------------+
357 * 8 | Buffer Address 1 [63:0] |
358 * +-----------------------------------------------------+
359 * 16 | Buffer Address 2 [63:0] |
360 * +-----------------------------------------------------+
361 * 24 | Buffer Address 3 [63:0] |
362 * +-----------------------------------------------------+
363 */
364 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
365 /* [Extended] Receive Descriptor (Write-Back) Format
366 *
367 * 63 48 47 32 31 13 12 8 7 4 3 0
368 * +------------------------------------------------------+
369 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
370 * | Checksum | Ident | | Queue | | Type |
371 * +------------------------------------------------------+
372 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
373 * +------------------------------------------------------+
374 * 63 48 47 32 31 20 19 0
375 */
376 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
377 for (i = 0; i < rx_ring->count; i++) {
378 const char *next_desc;
379 buffer_info = &rx_ring->buffer_info[i];
380 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
381 u1 = (struct my_u1 *)rx_desc_ps;
382 staterr =
383 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
384
385 if (i == rx_ring->next_to_use)
386 next_desc = " NTU";
387 else if (i == rx_ring->next_to_clean)
388 next_desc = " NTC";
389 else
390 next_desc = "";
391
392 if (staterr & E1000_RXD_STAT_DD) {
393 /* Descriptor Done */
394 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
395 "RWB", i,
396 (unsigned long long)le64_to_cpu(u1->a),
397 (unsigned long long)le64_to_cpu(u1->b),
398 (unsigned long long)le64_to_cpu(u1->c),
399 (unsigned long long)le64_to_cpu(u1->d),
400 buffer_info->skb, next_desc);
401 } else {
402 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
403 "R ", i,
404 (unsigned long long)le64_to_cpu(u1->a),
405 (unsigned long long)le64_to_cpu(u1->b),
406 (unsigned long long)le64_to_cpu(u1->c),
407 (unsigned long long)le64_to_cpu(u1->d),
408 (unsigned long long)buffer_info->dma,
409 buffer_info->skb, next_desc);
410
411 if (netif_msg_pktdata(adapter))
412 e1000e_dump_ps_pages(adapter,
413 buffer_info);
414 }
415 }
416 break;
417 default:
418 case 0:
419 /* Extended Receive Descriptor (Read) Format
420 *
421 * +-----------------------------------------------------+
422 * 0 | Buffer Address [63:0] |
423 * +-----------------------------------------------------+
424 * 8 | Reserved |
425 * +-----------------------------------------------------+
426 */
427 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
428 /* Extended Receive Descriptor (Write-Back) Format
429 *
430 * 63 48 47 32 31 24 23 4 3 0
431 * +------------------------------------------------------+
432 * | RSS Hash | | | |
433 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
434 * | Packet | IP | | | Type |
435 * | Checksum | Ident | | | |
436 * +------------------------------------------------------+
437 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
438 * +------------------------------------------------------+
439 * 63 48 47 32 31 20 19 0
440 */
441 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
442
443 for (i = 0; i < rx_ring->count; i++) {
444 const char *next_desc;
445
446 buffer_info = &rx_ring->buffer_info[i];
447 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
448 u1 = (struct my_u1 *)rx_desc;
449 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
450
451 if (i == rx_ring->next_to_use)
452 next_desc = " NTU";
453 else if (i == rx_ring->next_to_clean)
454 next_desc = " NTC";
455 else
456 next_desc = "";
457
458 if (staterr & E1000_RXD_STAT_DD) {
459 /* Descriptor Done */
460 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
461 "RWB", i,
462 (unsigned long long)le64_to_cpu(u1->a),
463 (unsigned long long)le64_to_cpu(u1->b),
464 buffer_info->skb, next_desc);
465 } else {
466 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
467 "R ", i,
468 (unsigned long long)le64_to_cpu(u1->a),
469 (unsigned long long)le64_to_cpu(u1->b),
470 (unsigned long long)buffer_info->dma,
471 buffer_info->skb, next_desc);
472
473 if (netif_msg_pktdata(adapter) &&
474 buffer_info->skb)
475 print_hex_dump(KERN_INFO, "",
476 DUMP_PREFIX_ADDRESS, 16,
477 1,
478 buffer_info->skb->data,
479 adapter->rx_buffer_len,
480 true);
481 }
482 }
483 }
484 }
485
486 /**
487 * e1000_desc_unused - calculate if we have unused descriptors
488 **/
489 static int e1000_desc_unused(struct e1000_ring *ring)
490 {
491 if (ring->next_to_clean > ring->next_to_use)
492 return ring->next_to_clean - ring->next_to_use - 1;
493
494 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
495 }
496
497 /**
498 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
499 * @adapter: board private structure
500 * @hwtstamps: time stamp structure to update
501 * @systim: unsigned 64bit system time value.
502 *
503 * Convert the system time value stored in the RX/TXSTMP registers into a
504 * hwtstamp which can be used by the upper level time stamping functions.
505 *
506 * The 'systim_lock' spinlock is used to protect the consistency of the
507 * system time value. This is needed because reading the 64 bit time
508 * value involves reading two 32 bit registers. The first read latches the
509 * value.
510 **/
511 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
512 struct skb_shared_hwtstamps *hwtstamps,
513 u64 systim)
514 {
515 u64 ns;
516 unsigned long flags;
517
518 spin_lock_irqsave(&adapter->systim_lock, flags);
519 ns = timecounter_cyc2time(&adapter->tc, systim);
520 spin_unlock_irqrestore(&adapter->systim_lock, flags);
521
522 memset(hwtstamps, 0, sizeof(*hwtstamps));
523 hwtstamps->hwtstamp = ns_to_ktime(ns);
524 }
525
526 /**
527 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
528 * @adapter: board private structure
529 * @status: descriptor extended error and status field
530 * @skb: particular skb to include time stamp
531 *
532 * If the time stamp is valid, convert it into the timecounter ns value
533 * and store that result into the shhwtstamps structure which is passed
534 * up the network stack.
535 **/
536 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
537 struct sk_buff *skb)
538 {
539 struct e1000_hw *hw = &adapter->hw;
540 u64 rxstmp;
541
542 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
543 !(status & E1000_RXDEXT_STATERR_TST) ||
544 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
545 return;
546
547 /* The Rx time stamp registers contain the time stamp. No other
548 * received packet will be time stamped until the Rx time stamp
549 * registers are read. Because only one packet can be time stamped
550 * at a time, the register values must belong to this packet and
551 * therefore none of the other additional attributes need to be
552 * compared.
553 */
554 rxstmp = (u64)er32(RXSTMPL);
555 rxstmp |= (u64)er32(RXSTMPH) << 32;
556 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
557
558 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
559 }
560
561 /**
562 * e1000_receive_skb - helper function to handle Rx indications
563 * @adapter: board private structure
564 * @staterr: descriptor extended error and status field as written by hardware
565 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
566 * @skb: pointer to sk_buff to be indicated to stack
567 **/
568 static void e1000_receive_skb(struct e1000_adapter *adapter,
569 struct net_device *netdev, struct sk_buff *skb,
570 u32 staterr, __le16 vlan)
571 {
572 u16 tag = le16_to_cpu(vlan);
573
574 e1000e_rx_hwtstamp(adapter, staterr, skb);
575
576 skb->protocol = eth_type_trans(skb, netdev);
577
578 if (staterr & E1000_RXD_STAT_VP)
579 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
580
581 napi_gro_receive(&adapter->napi, skb);
582 }
583
584 /**
585 * e1000_rx_checksum - Receive Checksum Offload
586 * @adapter: board private structure
587 * @status_err: receive descriptor status and error fields
588 * @csum: receive descriptor csum field
589 * @sk_buff: socket buffer with received data
590 **/
591 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
592 struct sk_buff *skb)
593 {
594 u16 status = (u16)status_err;
595 u8 errors = (u8)(status_err >> 24);
596
597 skb_checksum_none_assert(skb);
598
599 /* Rx checksum disabled */
600 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
601 return;
602
603 /* Ignore Checksum bit is set */
604 if (status & E1000_RXD_STAT_IXSM)
605 return;
606
607 /* TCP/UDP checksum error bit or IP checksum error bit is set */
608 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
609 /* let the stack verify checksum errors */
610 adapter->hw_csum_err++;
611 return;
612 }
613
614 /* TCP/UDP Checksum has not been calculated */
615 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
616 return;
617
618 /* It must be a TCP or UDP packet with a valid checksum */
619 skb->ip_summed = CHECKSUM_UNNECESSARY;
620 adapter->hw_csum_good++;
621 }
622
623 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
624 {
625 struct e1000_adapter *adapter = rx_ring->adapter;
626 struct e1000_hw *hw = &adapter->hw;
627 s32 ret_val = __ew32_prepare(hw);
628
629 writel(i, rx_ring->tail);
630
631 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
632 u32 rctl = er32(RCTL);
633
634 ew32(RCTL, rctl & ~E1000_RCTL_EN);
635 e_err("ME firmware caused invalid RDT - resetting\n");
636 schedule_work(&adapter->reset_task);
637 }
638 }
639
640 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
641 {
642 struct e1000_adapter *adapter = tx_ring->adapter;
643 struct e1000_hw *hw = &adapter->hw;
644 s32 ret_val = __ew32_prepare(hw);
645
646 writel(i, tx_ring->tail);
647
648 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
649 u32 tctl = er32(TCTL);
650
651 ew32(TCTL, tctl & ~E1000_TCTL_EN);
652 e_err("ME firmware caused invalid TDT - resetting\n");
653 schedule_work(&adapter->reset_task);
654 }
655 }
656
657 /**
658 * e1000_alloc_rx_buffers - Replace used receive buffers
659 * @rx_ring: Rx descriptor ring
660 **/
661 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
662 int cleaned_count, gfp_t gfp)
663 {
664 struct e1000_adapter *adapter = rx_ring->adapter;
665 struct net_device *netdev = adapter->netdev;
666 struct pci_dev *pdev = adapter->pdev;
667 union e1000_rx_desc_extended *rx_desc;
668 struct e1000_buffer *buffer_info;
669 struct sk_buff *skb;
670 unsigned int i;
671 unsigned int bufsz = adapter->rx_buffer_len;
672
673 i = rx_ring->next_to_use;
674 buffer_info = &rx_ring->buffer_info[i];
675
676 while (cleaned_count--) {
677 skb = buffer_info->skb;
678 if (skb) {
679 skb_trim(skb, 0);
680 goto map_skb;
681 }
682
683 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
684 if (!skb) {
685 /* Better luck next round */
686 adapter->alloc_rx_buff_failed++;
687 break;
688 }
689
690 buffer_info->skb = skb;
691 map_skb:
692 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
693 adapter->rx_buffer_len,
694 DMA_FROM_DEVICE);
695 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
696 dev_err(&pdev->dev, "Rx DMA map failed\n");
697 adapter->rx_dma_failed++;
698 break;
699 }
700
701 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
702 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
703
704 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
705 /* Force memory writes to complete before letting h/w
706 * know there are new descriptors to fetch. (Only
707 * applicable for weak-ordered memory model archs,
708 * such as IA-64).
709 */
710 wmb();
711 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
712 e1000e_update_rdt_wa(rx_ring, i);
713 else
714 writel(i, rx_ring->tail);
715 }
716 i++;
717 if (i == rx_ring->count)
718 i = 0;
719 buffer_info = &rx_ring->buffer_info[i];
720 }
721
722 rx_ring->next_to_use = i;
723 }
724
725 /**
726 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
727 * @rx_ring: Rx descriptor ring
728 **/
729 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
730 int cleaned_count, gfp_t gfp)
731 {
732 struct e1000_adapter *adapter = rx_ring->adapter;
733 struct net_device *netdev = adapter->netdev;
734 struct pci_dev *pdev = adapter->pdev;
735 union e1000_rx_desc_packet_split *rx_desc;
736 struct e1000_buffer *buffer_info;
737 struct e1000_ps_page *ps_page;
738 struct sk_buff *skb;
739 unsigned int i, j;
740
741 i = rx_ring->next_to_use;
742 buffer_info = &rx_ring->buffer_info[i];
743
744 while (cleaned_count--) {
745 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
746
747 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
748 ps_page = &buffer_info->ps_pages[j];
749 if (j >= adapter->rx_ps_pages) {
750 /* all unused desc entries get hw null ptr */
751 rx_desc->read.buffer_addr[j + 1] =
752 ~cpu_to_le64(0);
753 continue;
754 }
755 if (!ps_page->page) {
756 ps_page->page = alloc_page(gfp);
757 if (!ps_page->page) {
758 adapter->alloc_rx_buff_failed++;
759 goto no_buffers;
760 }
761 ps_page->dma = dma_map_page(&pdev->dev,
762 ps_page->page,
763 0, PAGE_SIZE,
764 DMA_FROM_DEVICE);
765 if (dma_mapping_error(&pdev->dev,
766 ps_page->dma)) {
767 dev_err(&adapter->pdev->dev,
768 "Rx DMA page map failed\n");
769 adapter->rx_dma_failed++;
770 goto no_buffers;
771 }
772 }
773 /* Refresh the desc even if buffer_addrs
774 * didn't change because each write-back
775 * erases this info.
776 */
777 rx_desc->read.buffer_addr[j + 1] =
778 cpu_to_le64(ps_page->dma);
779 }
780
781 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
782 gfp);
783
784 if (!skb) {
785 adapter->alloc_rx_buff_failed++;
786 break;
787 }
788
789 buffer_info->skb = skb;
790 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
791 adapter->rx_ps_bsize0,
792 DMA_FROM_DEVICE);
793 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
794 dev_err(&pdev->dev, "Rx DMA map failed\n");
795 adapter->rx_dma_failed++;
796 /* cleanup skb */
797 dev_kfree_skb_any(skb);
798 buffer_info->skb = NULL;
799 break;
800 }
801
802 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
803
804 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
805 /* Force memory writes to complete before letting h/w
806 * know there are new descriptors to fetch. (Only
807 * applicable for weak-ordered memory model archs,
808 * such as IA-64).
809 */
810 wmb();
811 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
812 e1000e_update_rdt_wa(rx_ring, i << 1);
813 else
814 writel(i << 1, rx_ring->tail);
815 }
816
817 i++;
818 if (i == rx_ring->count)
819 i = 0;
820 buffer_info = &rx_ring->buffer_info[i];
821 }
822
823 no_buffers:
824 rx_ring->next_to_use = i;
825 }
826
827 /**
828 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
829 * @rx_ring: Rx descriptor ring
830 * @cleaned_count: number of buffers to allocate this pass
831 **/
832
833 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
834 int cleaned_count, gfp_t gfp)
835 {
836 struct e1000_adapter *adapter = rx_ring->adapter;
837 struct net_device *netdev = adapter->netdev;
838 struct pci_dev *pdev = adapter->pdev;
839 union e1000_rx_desc_extended *rx_desc;
840 struct e1000_buffer *buffer_info;
841 struct sk_buff *skb;
842 unsigned int i;
843 unsigned int bufsz = 256 - 16; /* for skb_reserve */
844
845 i = rx_ring->next_to_use;
846 buffer_info = &rx_ring->buffer_info[i];
847
848 while (cleaned_count--) {
849 skb = buffer_info->skb;
850 if (skb) {
851 skb_trim(skb, 0);
852 goto check_page;
853 }
854
855 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
856 if (unlikely(!skb)) {
857 /* Better luck next round */
858 adapter->alloc_rx_buff_failed++;
859 break;
860 }
861
862 buffer_info->skb = skb;
863 check_page:
864 /* allocate a new page if necessary */
865 if (!buffer_info->page) {
866 buffer_info->page = alloc_page(gfp);
867 if (unlikely(!buffer_info->page)) {
868 adapter->alloc_rx_buff_failed++;
869 break;
870 }
871 }
872
873 if (!buffer_info->dma) {
874 buffer_info->dma = dma_map_page(&pdev->dev,
875 buffer_info->page, 0,
876 PAGE_SIZE,
877 DMA_FROM_DEVICE);
878 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
879 adapter->alloc_rx_buff_failed++;
880 break;
881 }
882 }
883
884 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
885 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
886
887 if (unlikely(++i == rx_ring->count))
888 i = 0;
889 buffer_info = &rx_ring->buffer_info[i];
890 }
891
892 if (likely(rx_ring->next_to_use != i)) {
893 rx_ring->next_to_use = i;
894 if (unlikely(i-- == 0))
895 i = (rx_ring->count - 1);
896
897 /* Force memory writes to complete before letting h/w
898 * know there are new descriptors to fetch. (Only
899 * applicable for weak-ordered memory model archs,
900 * such as IA-64).
901 */
902 wmb();
903 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
904 e1000e_update_rdt_wa(rx_ring, i);
905 else
906 writel(i, rx_ring->tail);
907 }
908 }
909
910 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
911 struct sk_buff *skb)
912 {
913 if (netdev->features & NETIF_F_RXHASH)
914 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
915 }
916
917 /**
918 * e1000_clean_rx_irq - Send received data up the network stack
919 * @rx_ring: Rx descriptor ring
920 *
921 * the return value indicates whether actual cleaning was done, there
922 * is no guarantee that everything was cleaned
923 **/
924 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
925 int work_to_do)
926 {
927 struct e1000_adapter *adapter = rx_ring->adapter;
928 struct net_device *netdev = adapter->netdev;
929 struct pci_dev *pdev = adapter->pdev;
930 struct e1000_hw *hw = &adapter->hw;
931 union e1000_rx_desc_extended *rx_desc, *next_rxd;
932 struct e1000_buffer *buffer_info, *next_buffer;
933 u32 length, staterr;
934 unsigned int i;
935 int cleaned_count = 0;
936 bool cleaned = false;
937 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
938
939 i = rx_ring->next_to_clean;
940 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
941 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
942 buffer_info = &rx_ring->buffer_info[i];
943
944 while (staterr & E1000_RXD_STAT_DD) {
945 struct sk_buff *skb;
946
947 if (*work_done >= work_to_do)
948 break;
949 (*work_done)++;
950 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
951
952 skb = buffer_info->skb;
953 buffer_info->skb = NULL;
954
955 prefetch(skb->data - NET_IP_ALIGN);
956
957 i++;
958 if (i == rx_ring->count)
959 i = 0;
960 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
961 prefetch(next_rxd);
962
963 next_buffer = &rx_ring->buffer_info[i];
964
965 cleaned = true;
966 cleaned_count++;
967 dma_unmap_single(&pdev->dev, buffer_info->dma,
968 adapter->rx_buffer_len, DMA_FROM_DEVICE);
969 buffer_info->dma = 0;
970
971 length = le16_to_cpu(rx_desc->wb.upper.length);
972
973 /* !EOP means multiple descriptors were used to store a single
974 * packet, if that's the case we need to toss it. In fact, we
975 * need to toss every packet with the EOP bit clear and the
976 * next frame that _does_ have the EOP bit set, as it is by
977 * definition only a frame fragment
978 */
979 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
980 adapter->flags2 |= FLAG2_IS_DISCARDING;
981
982 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
983 /* All receives must fit into a single buffer */
984 e_dbg("Receive packet consumed multiple buffers\n");
985 /* recycle */
986 buffer_info->skb = skb;
987 if (staterr & E1000_RXD_STAT_EOP)
988 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
989 goto next_desc;
990 }
991
992 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
993 !(netdev->features & NETIF_F_RXALL))) {
994 /* recycle */
995 buffer_info->skb = skb;
996 goto next_desc;
997 }
998
999 /* adjust length to remove Ethernet CRC */
1000 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1001 /* If configured to store CRC, don't subtract FCS,
1002 * but keep the FCS bytes out of the total_rx_bytes
1003 * counter
1004 */
1005 if (netdev->features & NETIF_F_RXFCS)
1006 total_rx_bytes -= 4;
1007 else
1008 length -= 4;
1009 }
1010
1011 total_rx_bytes += length;
1012 total_rx_packets++;
1013
1014 /* code added for copybreak, this should improve
1015 * performance for small packets with large amounts
1016 * of reassembly being done in the stack
1017 */
1018 if (length < copybreak) {
1019 struct sk_buff *new_skb =
1020 napi_alloc_skb(&adapter->napi, length);
1021 if (new_skb) {
1022 skb_copy_to_linear_data_offset(new_skb,
1023 -NET_IP_ALIGN,
1024 (skb->data -
1025 NET_IP_ALIGN),
1026 (length +
1027 NET_IP_ALIGN));
1028 /* save the skb in buffer_info as good */
1029 buffer_info->skb = skb;
1030 skb = new_skb;
1031 }
1032 /* else just continue with the old one */
1033 }
1034 /* end copybreak code */
1035 skb_put(skb, length);
1036
1037 /* Receive Checksum Offload */
1038 e1000_rx_checksum(adapter, staterr, skb);
1039
1040 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1041
1042 e1000_receive_skb(adapter, netdev, skb, staterr,
1043 rx_desc->wb.upper.vlan);
1044
1045 next_desc:
1046 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1047
1048 /* return some buffers to hardware, one at a time is too slow */
1049 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1050 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1051 GFP_ATOMIC);
1052 cleaned_count = 0;
1053 }
1054
1055 /* use prefetched values */
1056 rx_desc = next_rxd;
1057 buffer_info = next_buffer;
1058
1059 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1060 }
1061 rx_ring->next_to_clean = i;
1062
1063 cleaned_count = e1000_desc_unused(rx_ring);
1064 if (cleaned_count)
1065 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1066
1067 adapter->total_rx_bytes += total_rx_bytes;
1068 adapter->total_rx_packets += total_rx_packets;
1069 return cleaned;
1070 }
1071
1072 static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1073 struct e1000_buffer *buffer_info)
1074 {
1075 struct e1000_adapter *adapter = tx_ring->adapter;
1076
1077 if (buffer_info->dma) {
1078 if (buffer_info->mapped_as_page)
1079 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1080 buffer_info->length, DMA_TO_DEVICE);
1081 else
1082 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1083 buffer_info->length, DMA_TO_DEVICE);
1084 buffer_info->dma = 0;
1085 }
1086 if (buffer_info->skb) {
1087 dev_kfree_skb_any(buffer_info->skb);
1088 buffer_info->skb = NULL;
1089 }
1090 buffer_info->time_stamp = 0;
1091 }
1092
1093 static void e1000_print_hw_hang(struct work_struct *work)
1094 {
1095 struct e1000_adapter *adapter = container_of(work,
1096 struct e1000_adapter,
1097 print_hang_task);
1098 struct net_device *netdev = adapter->netdev;
1099 struct e1000_ring *tx_ring = adapter->tx_ring;
1100 unsigned int i = tx_ring->next_to_clean;
1101 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1102 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
1103 struct e1000_hw *hw = &adapter->hw;
1104 u16 phy_status, phy_1000t_status, phy_ext_status;
1105 u16 pci_status;
1106
1107 if (test_bit(__E1000_DOWN, &adapter->state))
1108 return;
1109
1110 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
1111 /* May be block on write-back, flush and detect again
1112 * flush pending descriptor writebacks to memory
1113 */
1114 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1115 /* execute the writes immediately */
1116 e1e_flush();
1117 /* Due to rare timing issues, write to TIDV again to ensure
1118 * the write is successful
1119 */
1120 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1121 /* execute the writes immediately */
1122 e1e_flush();
1123 adapter->tx_hang_recheck = true;
1124 return;
1125 }
1126 adapter->tx_hang_recheck = false;
1127
1128 if (er32(TDH(0)) == er32(TDT(0))) {
1129 e_dbg("false hang detected, ignoring\n");
1130 return;
1131 }
1132
1133 /* Real hang detected */
1134 netif_stop_queue(netdev);
1135
1136 e1e_rphy(hw, MII_BMSR, &phy_status);
1137 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1138 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
1139
1140 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1141
1142 /* detected Hardware unit hang */
1143 e_err("Detected Hardware Unit Hang:\n"
1144 " TDH <%x>\n"
1145 " TDT <%x>\n"
1146 " next_to_use <%x>\n"
1147 " next_to_clean <%x>\n"
1148 "buffer_info[next_to_clean]:\n"
1149 " time_stamp <%lx>\n"
1150 " next_to_watch <%x>\n"
1151 " jiffies <%lx>\n"
1152 " next_to_watch.status <%x>\n"
1153 "MAC Status <%x>\n"
1154 "PHY Status <%x>\n"
1155 "PHY 1000BASE-T Status <%x>\n"
1156 "PHY Extended Status <%x>\n"
1157 "PCI Status <%x>\n",
1158 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1159 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1160 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1161 phy_status, phy_1000t_status, phy_ext_status, pci_status);
1162
1163 e1000e_dump(adapter);
1164
1165 /* Suggest workaround for known h/w issue */
1166 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1167 e_err("Try turning off Tx pause (flow control) via ethtool\n");
1168 }
1169
1170 /**
1171 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1172 * @work: pointer to work struct
1173 *
1174 * This work function polls the TSYNCTXCTL valid bit to determine when a
1175 * timestamp has been taken for the current stored skb. The timestamp must
1176 * be for this skb because only one such packet is allowed in the queue.
1177 */
1178 static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1179 {
1180 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1181 tx_hwtstamp_work);
1182 struct e1000_hw *hw = &adapter->hw;
1183
1184 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1185 struct skb_shared_hwtstamps shhwtstamps;
1186 u64 txstmp;
1187
1188 txstmp = er32(TXSTMPL);
1189 txstmp |= (u64)er32(TXSTMPH) << 32;
1190
1191 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1192
1193 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps);
1194 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1195 adapter->tx_hwtstamp_skb = NULL;
1196 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1197 + adapter->tx_timeout_factor * HZ)) {
1198 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1199 adapter->tx_hwtstamp_skb = NULL;
1200 adapter->tx_hwtstamp_timeouts++;
1201 e_warn("clearing Tx timestamp hang\n");
1202 } else {
1203 /* reschedule to check later */
1204 schedule_work(&adapter->tx_hwtstamp_work);
1205 }
1206 }
1207
1208 /**
1209 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1210 * @tx_ring: Tx descriptor ring
1211 *
1212 * the return value indicates whether actual cleaning was done, there
1213 * is no guarantee that everything was cleaned
1214 **/
1215 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
1216 {
1217 struct e1000_adapter *adapter = tx_ring->adapter;
1218 struct net_device *netdev = adapter->netdev;
1219 struct e1000_hw *hw = &adapter->hw;
1220 struct e1000_tx_desc *tx_desc, *eop_desc;
1221 struct e1000_buffer *buffer_info;
1222 unsigned int i, eop;
1223 unsigned int count = 0;
1224 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
1225 unsigned int bytes_compl = 0, pkts_compl = 0;
1226
1227 i = tx_ring->next_to_clean;
1228 eop = tx_ring->buffer_info[i].next_to_watch;
1229 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1230
1231 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1232 (count < tx_ring->count)) {
1233 bool cleaned = false;
1234
1235 dma_rmb(); /* read buffer_info after eop_desc */
1236 for (; !cleaned; count++) {
1237 tx_desc = E1000_TX_DESC(*tx_ring, i);
1238 buffer_info = &tx_ring->buffer_info[i];
1239 cleaned = (i == eop);
1240
1241 if (cleaned) {
1242 total_tx_packets += buffer_info->segs;
1243 total_tx_bytes += buffer_info->bytecount;
1244 if (buffer_info->skb) {
1245 bytes_compl += buffer_info->skb->len;
1246 pkts_compl++;
1247 }
1248 }
1249
1250 e1000_put_txbuf(tx_ring, buffer_info);
1251 tx_desc->upper.data = 0;
1252
1253 i++;
1254 if (i == tx_ring->count)
1255 i = 0;
1256 }
1257
1258 if (i == tx_ring->next_to_use)
1259 break;
1260 eop = tx_ring->buffer_info[i].next_to_watch;
1261 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1262 }
1263
1264 tx_ring->next_to_clean = i;
1265
1266 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1267
1268 #define TX_WAKE_THRESHOLD 32
1269 if (count && netif_carrier_ok(netdev) &&
1270 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
1271 /* Make sure that anybody stopping the queue after this
1272 * sees the new next_to_clean.
1273 */
1274 smp_mb();
1275
1276 if (netif_queue_stopped(netdev) &&
1277 !(test_bit(__E1000_DOWN, &adapter->state))) {
1278 netif_wake_queue(netdev);
1279 ++adapter->restart_queue;
1280 }
1281 }
1282
1283 if (adapter->detect_tx_hung) {
1284 /* Detect a transmit hang in hardware, this serializes the
1285 * check with the clearing of time_stamp and movement of i
1286 */
1287 adapter->detect_tx_hung = false;
1288 if (tx_ring->buffer_info[i].time_stamp &&
1289 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
1290 + (adapter->tx_timeout_factor * HZ)) &&
1291 !(er32(STATUS) & E1000_STATUS_TXOFF))
1292 schedule_work(&adapter->print_hang_task);
1293 else
1294 adapter->tx_hang_recheck = false;
1295 }
1296 adapter->total_tx_bytes += total_tx_bytes;
1297 adapter->total_tx_packets += total_tx_packets;
1298 return count < tx_ring->count;
1299 }
1300
1301 /**
1302 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1303 * @rx_ring: Rx descriptor ring
1304 *
1305 * the return value indicates whether actual cleaning was done, there
1306 * is no guarantee that everything was cleaned
1307 **/
1308 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1309 int work_to_do)
1310 {
1311 struct e1000_adapter *adapter = rx_ring->adapter;
1312 struct e1000_hw *hw = &adapter->hw;
1313 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1314 struct net_device *netdev = adapter->netdev;
1315 struct pci_dev *pdev = adapter->pdev;
1316 struct e1000_buffer *buffer_info, *next_buffer;
1317 struct e1000_ps_page *ps_page;
1318 struct sk_buff *skb;
1319 unsigned int i, j;
1320 u32 length, staterr;
1321 int cleaned_count = 0;
1322 bool cleaned = false;
1323 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1324
1325 i = rx_ring->next_to_clean;
1326 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1327 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1328 buffer_info = &rx_ring->buffer_info[i];
1329
1330 while (staterr & E1000_RXD_STAT_DD) {
1331 if (*work_done >= work_to_do)
1332 break;
1333 (*work_done)++;
1334 skb = buffer_info->skb;
1335 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1336
1337 /* in the packet split case this is header only */
1338 prefetch(skb->data - NET_IP_ALIGN);
1339
1340 i++;
1341 if (i == rx_ring->count)
1342 i = 0;
1343 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1344 prefetch(next_rxd);
1345
1346 next_buffer = &rx_ring->buffer_info[i];
1347
1348 cleaned = true;
1349 cleaned_count++;
1350 dma_unmap_single(&pdev->dev, buffer_info->dma,
1351 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
1352 buffer_info->dma = 0;
1353
1354 /* see !EOP comment in other Rx routine */
1355 if (!(staterr & E1000_RXD_STAT_EOP))
1356 adapter->flags2 |= FLAG2_IS_DISCARDING;
1357
1358 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
1359 e_dbg("Packet Split buffers didn't pick up the full packet\n");
1360 dev_kfree_skb_irq(skb);
1361 if (staterr & E1000_RXD_STAT_EOP)
1362 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1363 goto next_desc;
1364 }
1365
1366 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1367 !(netdev->features & NETIF_F_RXALL))) {
1368 dev_kfree_skb_irq(skb);
1369 goto next_desc;
1370 }
1371
1372 length = le16_to_cpu(rx_desc->wb.middle.length0);
1373
1374 if (!length) {
1375 e_dbg("Last part of the packet spanning multiple descriptors\n");
1376 dev_kfree_skb_irq(skb);
1377 goto next_desc;
1378 }
1379
1380 /* Good Receive */
1381 skb_put(skb, length);
1382
1383 {
1384 /* this looks ugly, but it seems compiler issues make
1385 * it more efficient than reusing j
1386 */
1387 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1388
1389 /* page alloc/put takes too long and effects small
1390 * packet throughput, so unsplit small packets and
1391 * save the alloc/put only valid in softirq (napi)
1392 * context to call kmap_*
1393 */
1394 if (l1 && (l1 <= copybreak) &&
1395 ((length + l1) <= adapter->rx_ps_bsize0)) {
1396 u8 *vaddr;
1397
1398 ps_page = &buffer_info->ps_pages[0];
1399
1400 /* there is no documentation about how to call
1401 * kmap_atomic, so we can't hold the mapping
1402 * very long
1403 */
1404 dma_sync_single_for_cpu(&pdev->dev,
1405 ps_page->dma,
1406 PAGE_SIZE,
1407 DMA_FROM_DEVICE);
1408 vaddr = kmap_atomic(ps_page->page);
1409 memcpy(skb_tail_pointer(skb), vaddr, l1);
1410 kunmap_atomic(vaddr);
1411 dma_sync_single_for_device(&pdev->dev,
1412 ps_page->dma,
1413 PAGE_SIZE,
1414 DMA_FROM_DEVICE);
1415
1416 /* remove the CRC */
1417 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1418 if (!(netdev->features & NETIF_F_RXFCS))
1419 l1 -= 4;
1420 }
1421
1422 skb_put(skb, l1);
1423 goto copydone;
1424 } /* if */
1425 }
1426
1427 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1428 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1429 if (!length)
1430 break;
1431
1432 ps_page = &buffer_info->ps_pages[j];
1433 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1434 DMA_FROM_DEVICE);
1435 ps_page->dma = 0;
1436 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1437 ps_page->page = NULL;
1438 skb->len += length;
1439 skb->data_len += length;
1440 skb->truesize += PAGE_SIZE;
1441 }
1442
1443 /* strip the ethernet crc, problem is we're using pages now so
1444 * this whole operation can get a little cpu intensive
1445 */
1446 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1447 if (!(netdev->features & NETIF_F_RXFCS))
1448 pskb_trim(skb, skb->len - 4);
1449 }
1450
1451 copydone:
1452 total_rx_bytes += skb->len;
1453 total_rx_packets++;
1454
1455 e1000_rx_checksum(adapter, staterr, skb);
1456
1457 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1458
1459 if (rx_desc->wb.upper.header_status &
1460 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1461 adapter->rx_hdr_split++;
1462
1463 e1000_receive_skb(adapter, netdev, skb, staterr,
1464 rx_desc->wb.middle.vlan);
1465
1466 next_desc:
1467 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1468 buffer_info->skb = NULL;
1469
1470 /* return some buffers to hardware, one at a time is too slow */
1471 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1472 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1473 GFP_ATOMIC);
1474 cleaned_count = 0;
1475 }
1476
1477 /* use prefetched values */
1478 rx_desc = next_rxd;
1479 buffer_info = next_buffer;
1480
1481 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1482 }
1483 rx_ring->next_to_clean = i;
1484
1485 cleaned_count = e1000_desc_unused(rx_ring);
1486 if (cleaned_count)
1487 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1488
1489 adapter->total_rx_bytes += total_rx_bytes;
1490 adapter->total_rx_packets += total_rx_packets;
1491 return cleaned;
1492 }
1493
1494 /**
1495 * e1000_consume_page - helper function
1496 **/
1497 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1498 u16 length)
1499 {
1500 bi->page = NULL;
1501 skb->len += length;
1502 skb->data_len += length;
1503 skb->truesize += PAGE_SIZE;
1504 }
1505
1506 /**
1507 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1508 * @adapter: board private structure
1509 *
1510 * the return value indicates whether actual cleaning was done, there
1511 * is no guarantee that everything was cleaned
1512 **/
1513 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1514 int work_to_do)
1515 {
1516 struct e1000_adapter *adapter = rx_ring->adapter;
1517 struct net_device *netdev = adapter->netdev;
1518 struct pci_dev *pdev = adapter->pdev;
1519 union e1000_rx_desc_extended *rx_desc, *next_rxd;
1520 struct e1000_buffer *buffer_info, *next_buffer;
1521 u32 length, staterr;
1522 unsigned int i;
1523 int cleaned_count = 0;
1524 bool cleaned = false;
1525 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1526 struct skb_shared_info *shinfo;
1527
1528 i = rx_ring->next_to_clean;
1529 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1530 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1531 buffer_info = &rx_ring->buffer_info[i];
1532
1533 while (staterr & E1000_RXD_STAT_DD) {
1534 struct sk_buff *skb;
1535
1536 if (*work_done >= work_to_do)
1537 break;
1538 (*work_done)++;
1539 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1540
1541 skb = buffer_info->skb;
1542 buffer_info->skb = NULL;
1543
1544 ++i;
1545 if (i == rx_ring->count)
1546 i = 0;
1547 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
1548 prefetch(next_rxd);
1549
1550 next_buffer = &rx_ring->buffer_info[i];
1551
1552 cleaned = true;
1553 cleaned_count++;
1554 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1555 DMA_FROM_DEVICE);
1556 buffer_info->dma = 0;
1557
1558 length = le16_to_cpu(rx_desc->wb.upper.length);
1559
1560 /* errors is only valid for DD + EOP descriptors */
1561 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1562 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1563 !(netdev->features & NETIF_F_RXALL)))) {
1564 /* recycle both page and skb */
1565 buffer_info->skb = skb;
1566 /* an error means any chain goes out the window too */
1567 if (rx_ring->rx_skb_top)
1568 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1569 rx_ring->rx_skb_top = NULL;
1570 goto next_desc;
1571 }
1572 #define rxtop (rx_ring->rx_skb_top)
1573 if (!(staterr & E1000_RXD_STAT_EOP)) {
1574 /* this descriptor is only the beginning (or middle) */
1575 if (!rxtop) {
1576 /* this is the beginning of a chain */
1577 rxtop = skb;
1578 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1579 0, length);
1580 } else {
1581 /* this is the middle of a chain */
1582 shinfo = skb_shinfo(rxtop);
1583 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1584 buffer_info->page, 0,
1585 length);
1586 /* re-use the skb, only consumed the page */
1587 buffer_info->skb = skb;
1588 }
1589 e1000_consume_page(buffer_info, rxtop, length);
1590 goto next_desc;
1591 } else {
1592 if (rxtop) {
1593 /* end of the chain */
1594 shinfo = skb_shinfo(rxtop);
1595 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1596 buffer_info->page, 0,
1597 length);
1598 /* re-use the current skb, we only consumed the
1599 * page
1600 */
1601 buffer_info->skb = skb;
1602 skb = rxtop;
1603 rxtop = NULL;
1604 e1000_consume_page(buffer_info, skb, length);
1605 } else {
1606 /* no chain, got EOP, this buf is the packet
1607 * copybreak to save the put_page/alloc_page
1608 */
1609 if (length <= copybreak &&
1610 skb_tailroom(skb) >= length) {
1611 u8 *vaddr;
1612 vaddr = kmap_atomic(buffer_info->page);
1613 memcpy(skb_tail_pointer(skb), vaddr,
1614 length);
1615 kunmap_atomic(vaddr);
1616 /* re-use the page, so don't erase
1617 * buffer_info->page
1618 */
1619 skb_put(skb, length);
1620 } else {
1621 skb_fill_page_desc(skb, 0,
1622 buffer_info->page, 0,
1623 length);
1624 e1000_consume_page(buffer_info, skb,
1625 length);
1626 }
1627 }
1628 }
1629
1630 /* Receive Checksum Offload */
1631 e1000_rx_checksum(adapter, staterr, skb);
1632
1633 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1634
1635 /* probably a little skewed due to removing CRC */
1636 total_rx_bytes += skb->len;
1637 total_rx_packets++;
1638
1639 /* eth type trans needs skb->data to point to something */
1640 if (!pskb_may_pull(skb, ETH_HLEN)) {
1641 e_err("pskb_may_pull failed.\n");
1642 dev_kfree_skb_irq(skb);
1643 goto next_desc;
1644 }
1645
1646 e1000_receive_skb(adapter, netdev, skb, staterr,
1647 rx_desc->wb.upper.vlan);
1648
1649 next_desc:
1650 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1651
1652 /* return some buffers to hardware, one at a time is too slow */
1653 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
1654 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1655 GFP_ATOMIC);
1656 cleaned_count = 0;
1657 }
1658
1659 /* use prefetched values */
1660 rx_desc = next_rxd;
1661 buffer_info = next_buffer;
1662
1663 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1664 }
1665 rx_ring->next_to_clean = i;
1666
1667 cleaned_count = e1000_desc_unused(rx_ring);
1668 if (cleaned_count)
1669 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1670
1671 adapter->total_rx_bytes += total_rx_bytes;
1672 adapter->total_rx_packets += total_rx_packets;
1673 return cleaned;
1674 }
1675
1676 /**
1677 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1678 * @rx_ring: Rx descriptor ring
1679 **/
1680 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
1681 {
1682 struct e1000_adapter *adapter = rx_ring->adapter;
1683 struct e1000_buffer *buffer_info;
1684 struct e1000_ps_page *ps_page;
1685 struct pci_dev *pdev = adapter->pdev;
1686 unsigned int i, j;
1687
1688 /* Free all the Rx ring sk_buffs */
1689 for (i = 0; i < rx_ring->count; i++) {
1690 buffer_info = &rx_ring->buffer_info[i];
1691 if (buffer_info->dma) {
1692 if (adapter->clean_rx == e1000_clean_rx_irq)
1693 dma_unmap_single(&pdev->dev, buffer_info->dma,
1694 adapter->rx_buffer_len,
1695 DMA_FROM_DEVICE);
1696 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
1697 dma_unmap_page(&pdev->dev, buffer_info->dma,
1698 PAGE_SIZE, DMA_FROM_DEVICE);
1699 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
1700 dma_unmap_single(&pdev->dev, buffer_info->dma,
1701 adapter->rx_ps_bsize0,
1702 DMA_FROM_DEVICE);
1703 buffer_info->dma = 0;
1704 }
1705
1706 if (buffer_info->page) {
1707 put_page(buffer_info->page);
1708 buffer_info->page = NULL;
1709 }
1710
1711 if (buffer_info->skb) {
1712 dev_kfree_skb(buffer_info->skb);
1713 buffer_info->skb = NULL;
1714 }
1715
1716 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1717 ps_page = &buffer_info->ps_pages[j];
1718 if (!ps_page->page)
1719 break;
1720 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1721 DMA_FROM_DEVICE);
1722 ps_page->dma = 0;
1723 put_page(ps_page->page);
1724 ps_page->page = NULL;
1725 }
1726 }
1727
1728 /* there also may be some cached data from a chained receive */
1729 if (rx_ring->rx_skb_top) {
1730 dev_kfree_skb(rx_ring->rx_skb_top);
1731 rx_ring->rx_skb_top = NULL;
1732 }
1733
1734 /* Zero out the descriptor ring */
1735 memset(rx_ring->desc, 0, rx_ring->size);
1736
1737 rx_ring->next_to_clean = 0;
1738 rx_ring->next_to_use = 0;
1739 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1740
1741 writel(0, rx_ring->head);
1742 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
1743 e1000e_update_rdt_wa(rx_ring, 0);
1744 else
1745 writel(0, rx_ring->tail);
1746 }
1747
1748 static void e1000e_downshift_workaround(struct work_struct *work)
1749 {
1750 struct e1000_adapter *adapter = container_of(work,
1751 struct e1000_adapter,
1752 downshift_task);
1753
1754 if (test_bit(__E1000_DOWN, &adapter->state))
1755 return;
1756
1757 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1758 }
1759
1760 /**
1761 * e1000_intr_msi - Interrupt Handler
1762 * @irq: interrupt number
1763 * @data: pointer to a network interface device structure
1764 **/
1765 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
1766 {
1767 struct net_device *netdev = data;
1768 struct e1000_adapter *adapter = netdev_priv(netdev);
1769 struct e1000_hw *hw = &adapter->hw;
1770 u32 icr = er32(ICR);
1771
1772 /* read ICR disables interrupts using IAM */
1773 if (icr & E1000_ICR_LSC) {
1774 hw->mac.get_link_status = true;
1775 /* ICH8 workaround-- Call gig speed drop workaround on cable
1776 * disconnect (LSC) before accessing any PHY registers
1777 */
1778 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1779 (!(er32(STATUS) & E1000_STATUS_LU)))
1780 schedule_work(&adapter->downshift_task);
1781
1782 /* 80003ES2LAN workaround-- For packet buffer work-around on
1783 * link down event; disable receives here in the ISR and reset
1784 * adapter in watchdog
1785 */
1786 if (netif_carrier_ok(netdev) &&
1787 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1788 /* disable receives */
1789 u32 rctl = er32(RCTL);
1790
1791 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1792 adapter->flags |= FLAG_RESTART_NOW;
1793 }
1794 /* guard against interrupt when we're going down */
1795 if (!test_bit(__E1000_DOWN, &adapter->state))
1796 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1797 }
1798
1799 /* Reset on uncorrectable ECC error */
1800 if ((icr & E1000_ICR_ECCER) && ((hw->mac.type == e1000_pch_lpt) ||
1801 (hw->mac.type == e1000_pch_spt))) {
1802 u32 pbeccsts = er32(PBECCSTS);
1803
1804 adapter->corr_errors +=
1805 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1806 adapter->uncorr_errors +=
1807 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1808 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1809
1810 /* Do the reset outside of interrupt context */
1811 schedule_work(&adapter->reset_task);
1812
1813 /* return immediately since reset is imminent */
1814 return IRQ_HANDLED;
1815 }
1816
1817 if (napi_schedule_prep(&adapter->napi)) {
1818 adapter->total_tx_bytes = 0;
1819 adapter->total_tx_packets = 0;
1820 adapter->total_rx_bytes = 0;
1821 adapter->total_rx_packets = 0;
1822 __napi_schedule(&adapter->napi);
1823 }
1824
1825 return IRQ_HANDLED;
1826 }
1827
1828 /**
1829 * e1000_intr - Interrupt Handler
1830 * @irq: interrupt number
1831 * @data: pointer to a network interface device structure
1832 **/
1833 static irqreturn_t e1000_intr(int __always_unused irq, void *data)
1834 {
1835 struct net_device *netdev = data;
1836 struct e1000_adapter *adapter = netdev_priv(netdev);
1837 struct e1000_hw *hw = &adapter->hw;
1838 u32 rctl, icr = er32(ICR);
1839
1840 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
1841 return IRQ_NONE; /* Not our interrupt */
1842
1843 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1844 * not set, then the adapter didn't send an interrupt
1845 */
1846 if (!(icr & E1000_ICR_INT_ASSERTED))
1847 return IRQ_NONE;
1848
1849 /* Interrupt Auto-Mask...upon reading ICR,
1850 * interrupts are masked. No need for the
1851 * IMC write
1852 */
1853
1854 if (icr & E1000_ICR_LSC) {
1855 hw->mac.get_link_status = true;
1856 /* ICH8 workaround-- Call gig speed drop workaround on cable
1857 * disconnect (LSC) before accessing any PHY registers
1858 */
1859 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1860 (!(er32(STATUS) & E1000_STATUS_LU)))
1861 schedule_work(&adapter->downshift_task);
1862
1863 /* 80003ES2LAN workaround--
1864 * For packet buffer work-around on link down event;
1865 * disable receives here in the ISR and
1866 * reset adapter in watchdog
1867 */
1868 if (netif_carrier_ok(netdev) &&
1869 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1870 /* disable receives */
1871 rctl = er32(RCTL);
1872 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1873 adapter->flags |= FLAG_RESTART_NOW;
1874 }
1875 /* guard against interrupt when we're going down */
1876 if (!test_bit(__E1000_DOWN, &adapter->state))
1877 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1878 }
1879
1880 /* Reset on uncorrectable ECC error */
1881 if ((icr & E1000_ICR_ECCER) && ((hw->mac.type == e1000_pch_lpt) ||
1882 (hw->mac.type == e1000_pch_spt))) {
1883 u32 pbeccsts = er32(PBECCSTS);
1884
1885 adapter->corr_errors +=
1886 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1887 adapter->uncorr_errors +=
1888 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1889 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1890
1891 /* Do the reset outside of interrupt context */
1892 schedule_work(&adapter->reset_task);
1893
1894 /* return immediately since reset is imminent */
1895 return IRQ_HANDLED;
1896 }
1897
1898 if (napi_schedule_prep(&adapter->napi)) {
1899 adapter->total_tx_bytes = 0;
1900 adapter->total_tx_packets = 0;
1901 adapter->total_rx_bytes = 0;
1902 adapter->total_rx_packets = 0;
1903 __napi_schedule(&adapter->napi);
1904 }
1905
1906 return IRQ_HANDLED;
1907 }
1908
1909 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
1910 {
1911 struct net_device *netdev = data;
1912 struct e1000_adapter *adapter = netdev_priv(netdev);
1913 struct e1000_hw *hw = &adapter->hw;
1914 u32 icr = er32(ICR);
1915
1916 if (!(icr & E1000_ICR_INT_ASSERTED)) {
1917 if (!test_bit(__E1000_DOWN, &adapter->state))
1918 ew32(IMS, E1000_IMS_OTHER);
1919 return IRQ_NONE;
1920 }
1921
1922 if (icr & adapter->eiac_mask)
1923 ew32(ICS, (icr & adapter->eiac_mask));
1924
1925 if (icr & E1000_ICR_OTHER) {
1926 if (!(icr & E1000_ICR_LSC))
1927 goto no_link_interrupt;
1928 hw->mac.get_link_status = true;
1929 /* guard against interrupt when we're going down */
1930 if (!test_bit(__E1000_DOWN, &adapter->state))
1931 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1932 }
1933
1934 no_link_interrupt:
1935 if (!test_bit(__E1000_DOWN, &adapter->state))
1936 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
1937
1938 return IRQ_HANDLED;
1939 }
1940
1941 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
1942 {
1943 struct net_device *netdev = data;
1944 struct e1000_adapter *adapter = netdev_priv(netdev);
1945 struct e1000_hw *hw = &adapter->hw;
1946 struct e1000_ring *tx_ring = adapter->tx_ring;
1947
1948 adapter->total_tx_bytes = 0;
1949 adapter->total_tx_packets = 0;
1950
1951 if (!e1000_clean_tx_irq(tx_ring))
1952 /* Ring was not completely cleaned, so fire another interrupt */
1953 ew32(ICS, tx_ring->ims_val);
1954
1955 return IRQ_HANDLED;
1956 }
1957
1958 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
1959 {
1960 struct net_device *netdev = data;
1961 struct e1000_adapter *adapter = netdev_priv(netdev);
1962 struct e1000_ring *rx_ring = adapter->rx_ring;
1963
1964 /* Write the ITR value calculated at the end of the
1965 * previous interrupt.
1966 */
1967 if (rx_ring->set_itr) {
1968 writel(1000000000 / (rx_ring->itr_val * 256),
1969 rx_ring->itr_register);
1970 rx_ring->set_itr = 0;
1971 }
1972
1973 if (napi_schedule_prep(&adapter->napi)) {
1974 adapter->total_rx_bytes = 0;
1975 adapter->total_rx_packets = 0;
1976 __napi_schedule(&adapter->napi);
1977 }
1978 return IRQ_HANDLED;
1979 }
1980
1981 /**
1982 * e1000_configure_msix - Configure MSI-X hardware
1983 *
1984 * e1000_configure_msix sets up the hardware to properly
1985 * generate MSI-X interrupts.
1986 **/
1987 static void e1000_configure_msix(struct e1000_adapter *adapter)
1988 {
1989 struct e1000_hw *hw = &adapter->hw;
1990 struct e1000_ring *rx_ring = adapter->rx_ring;
1991 struct e1000_ring *tx_ring = adapter->tx_ring;
1992 int vector = 0;
1993 u32 ctrl_ext, ivar = 0;
1994
1995 adapter->eiac_mask = 0;
1996
1997 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1998 if (hw->mac.type == e1000_82574) {
1999 u32 rfctl = er32(RFCTL);
2000
2001 rfctl |= E1000_RFCTL_ACK_DIS;
2002 ew32(RFCTL, rfctl);
2003 }
2004
2005 /* Configure Rx vector */
2006 rx_ring->ims_val = E1000_IMS_RXQ0;
2007 adapter->eiac_mask |= rx_ring->ims_val;
2008 if (rx_ring->itr_val)
2009 writel(1000000000 / (rx_ring->itr_val * 256),
2010 rx_ring->itr_register);
2011 else
2012 writel(1, rx_ring->itr_register);
2013 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
2014
2015 /* Configure Tx vector */
2016 tx_ring->ims_val = E1000_IMS_TXQ0;
2017 vector++;
2018 if (tx_ring->itr_val)
2019 writel(1000000000 / (tx_ring->itr_val * 256),
2020 tx_ring->itr_register);
2021 else
2022 writel(1, tx_ring->itr_register);
2023 adapter->eiac_mask |= tx_ring->ims_val;
2024 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2025
2026 /* set vector for Other Causes, e.g. link changes */
2027 vector++;
2028 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2029 if (rx_ring->itr_val)
2030 writel(1000000000 / (rx_ring->itr_val * 256),
2031 hw->hw_addr + E1000_EITR_82574(vector));
2032 else
2033 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2034
2035 /* Cause Tx interrupts on every write back */
2036 ivar |= (1 << 31);
2037
2038 ew32(IVAR, ivar);
2039
2040 /* enable MSI-X PBA support */
2041 ctrl_ext = er32(CTRL_EXT);
2042 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
2043
2044 /* Auto-Mask Other interrupts upon ICR read */
2045 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
2046 ctrl_ext |= E1000_CTRL_EXT_EIAME;
2047 ew32(CTRL_EXT, ctrl_ext);
2048 e1e_flush();
2049 }
2050
2051 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2052 {
2053 if (adapter->msix_entries) {
2054 pci_disable_msix(adapter->pdev);
2055 kfree(adapter->msix_entries);
2056 adapter->msix_entries = NULL;
2057 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2058 pci_disable_msi(adapter->pdev);
2059 adapter->flags &= ~FLAG_MSI_ENABLED;
2060 }
2061 }
2062
2063 /**
2064 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2065 *
2066 * Attempt to configure interrupts using the best available
2067 * capabilities of the hardware and kernel.
2068 **/
2069 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2070 {
2071 int err;
2072 int i;
2073
2074 switch (adapter->int_mode) {
2075 case E1000E_INT_MODE_MSIX:
2076 if (adapter->flags & FLAG_HAS_MSIX) {
2077 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2078 adapter->msix_entries = kcalloc(adapter->num_vectors,
2079 sizeof(struct
2080 msix_entry),
2081 GFP_KERNEL);
2082 if (adapter->msix_entries) {
2083 struct e1000_adapter *a = adapter;
2084
2085 for (i = 0; i < adapter->num_vectors; i++)
2086 adapter->msix_entries[i].entry = i;
2087
2088 err = pci_enable_msix_range(a->pdev,
2089 a->msix_entries,
2090 a->num_vectors,
2091 a->num_vectors);
2092 if (err > 0)
2093 return;
2094 }
2095 /* MSI-X failed, so fall through and try MSI */
2096 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
2097 e1000e_reset_interrupt_capability(adapter);
2098 }
2099 adapter->int_mode = E1000E_INT_MODE_MSI;
2100 /* Fall through */
2101 case E1000E_INT_MODE_MSI:
2102 if (!pci_enable_msi(adapter->pdev)) {
2103 adapter->flags |= FLAG_MSI_ENABLED;
2104 } else {
2105 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2106 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
2107 }
2108 /* Fall through */
2109 case E1000E_INT_MODE_LEGACY:
2110 /* Don't do anything; this is the system default */
2111 break;
2112 }
2113
2114 /* store the number of vectors being used */
2115 adapter->num_vectors = 1;
2116 }
2117
2118 /**
2119 * e1000_request_msix - Initialize MSI-X interrupts
2120 *
2121 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2122 * kernel.
2123 **/
2124 static int e1000_request_msix(struct e1000_adapter *adapter)
2125 {
2126 struct net_device *netdev = adapter->netdev;
2127 int err = 0, vector = 0;
2128
2129 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2130 snprintf(adapter->rx_ring->name,
2131 sizeof(adapter->rx_ring->name) - 1,
2132 "%s-rx-0", netdev->name);
2133 else
2134 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2135 err = request_irq(adapter->msix_entries[vector].vector,
2136 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
2137 netdev);
2138 if (err)
2139 return err;
2140 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2141 E1000_EITR_82574(vector);
2142 adapter->rx_ring->itr_val = adapter->itr;
2143 vector++;
2144
2145 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2146 snprintf(adapter->tx_ring->name,
2147 sizeof(adapter->tx_ring->name) - 1,
2148 "%s-tx-0", netdev->name);
2149 else
2150 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2151 err = request_irq(adapter->msix_entries[vector].vector,
2152 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
2153 netdev);
2154 if (err)
2155 return err;
2156 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2157 E1000_EITR_82574(vector);
2158 adapter->tx_ring->itr_val = adapter->itr;
2159 vector++;
2160
2161 err = request_irq(adapter->msix_entries[vector].vector,
2162 e1000_msix_other, 0, netdev->name, netdev);
2163 if (err)
2164 return err;
2165
2166 e1000_configure_msix(adapter);
2167
2168 return 0;
2169 }
2170
2171 /**
2172 * e1000_request_irq - initialize interrupts
2173 *
2174 * Attempts to configure interrupts using the best available
2175 * capabilities of the hardware and kernel.
2176 **/
2177 static int e1000_request_irq(struct e1000_adapter *adapter)
2178 {
2179 struct net_device *netdev = adapter->netdev;
2180 int err;
2181
2182 if (adapter->msix_entries) {
2183 err = e1000_request_msix(adapter);
2184 if (!err)
2185 return err;
2186 /* fall back to MSI */
2187 e1000e_reset_interrupt_capability(adapter);
2188 adapter->int_mode = E1000E_INT_MODE_MSI;
2189 e1000e_set_interrupt_capability(adapter);
2190 }
2191 if (adapter->flags & FLAG_MSI_ENABLED) {
2192 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
2193 netdev->name, netdev);
2194 if (!err)
2195 return err;
2196
2197 /* fall back to legacy interrupt */
2198 e1000e_reset_interrupt_capability(adapter);
2199 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2200 }
2201
2202 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
2203 netdev->name, netdev);
2204 if (err)
2205 e_err("Unable to allocate interrupt, Error: %d\n", err);
2206
2207 return err;
2208 }
2209
2210 static void e1000_free_irq(struct e1000_adapter *adapter)
2211 {
2212 struct net_device *netdev = adapter->netdev;
2213
2214 if (adapter->msix_entries) {
2215 int vector = 0;
2216
2217 free_irq(adapter->msix_entries[vector].vector, netdev);
2218 vector++;
2219
2220 free_irq(adapter->msix_entries[vector].vector, netdev);
2221 vector++;
2222
2223 /* Other Causes interrupt vector */
2224 free_irq(adapter->msix_entries[vector].vector, netdev);
2225 return;
2226 }
2227
2228 free_irq(adapter->pdev->irq, netdev);
2229 }
2230
2231 /**
2232 * e1000_irq_disable - Mask off interrupt generation on the NIC
2233 **/
2234 static void e1000_irq_disable(struct e1000_adapter *adapter)
2235 {
2236 struct e1000_hw *hw = &adapter->hw;
2237
2238 ew32(IMC, ~0);
2239 if (adapter->msix_entries)
2240 ew32(EIAC_82574, 0);
2241 e1e_flush();
2242
2243 if (adapter->msix_entries) {
2244 int i;
2245
2246 for (i = 0; i < adapter->num_vectors; i++)
2247 synchronize_irq(adapter->msix_entries[i].vector);
2248 } else {
2249 synchronize_irq(adapter->pdev->irq);
2250 }
2251 }
2252
2253 /**
2254 * e1000_irq_enable - Enable default interrupt generation settings
2255 **/
2256 static void e1000_irq_enable(struct e1000_adapter *adapter)
2257 {
2258 struct e1000_hw *hw = &adapter->hw;
2259
2260 if (adapter->msix_entries) {
2261 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2262 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
2263 } else if ((hw->mac.type == e1000_pch_lpt) ||
2264 (hw->mac.type == e1000_pch_spt)) {
2265 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
2266 } else {
2267 ew32(IMS, IMS_ENABLE_MASK);
2268 }
2269 e1e_flush();
2270 }
2271
2272 /**
2273 * e1000e_get_hw_control - get control of the h/w from f/w
2274 * @adapter: address of board private structure
2275 *
2276 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2277 * For ASF and Pass Through versions of f/w this means that
2278 * the driver is loaded. For AMT version (only with 82573)
2279 * of the f/w this means that the network i/f is open.
2280 **/
2281 void e1000e_get_hw_control(struct e1000_adapter *adapter)
2282 {
2283 struct e1000_hw *hw = &adapter->hw;
2284 u32 ctrl_ext;
2285 u32 swsm;
2286
2287 /* Let firmware know the driver has taken over */
2288 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2289 swsm = er32(SWSM);
2290 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2291 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2292 ctrl_ext = er32(CTRL_EXT);
2293 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2294 }
2295 }
2296
2297 /**
2298 * e1000e_release_hw_control - release control of the h/w to f/w
2299 * @adapter: address of board private structure
2300 *
2301 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2302 * For ASF and Pass Through versions of f/w this means that the
2303 * driver is no longer loaded. For AMT version (only with 82573) i
2304 * of the f/w this means that the network i/f is closed.
2305 *
2306 **/
2307 void e1000e_release_hw_control(struct e1000_adapter *adapter)
2308 {
2309 struct e1000_hw *hw = &adapter->hw;
2310 u32 ctrl_ext;
2311 u32 swsm;
2312
2313 /* Let firmware taken over control of h/w */
2314 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2315 swsm = er32(SWSM);
2316 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2317 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2318 ctrl_ext = er32(CTRL_EXT);
2319 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2320 }
2321 }
2322
2323 /**
2324 * e1000_alloc_ring_dma - allocate memory for a ring structure
2325 **/
2326 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2327 struct e1000_ring *ring)
2328 {
2329 struct pci_dev *pdev = adapter->pdev;
2330
2331 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2332 GFP_KERNEL);
2333 if (!ring->desc)
2334 return -ENOMEM;
2335
2336 return 0;
2337 }
2338
2339 /**
2340 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2341 * @tx_ring: Tx descriptor ring
2342 *
2343 * Return 0 on success, negative on failure
2344 **/
2345 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
2346 {
2347 struct e1000_adapter *adapter = tx_ring->adapter;
2348 int err = -ENOMEM, size;
2349
2350 size = sizeof(struct e1000_buffer) * tx_ring->count;
2351 tx_ring->buffer_info = vzalloc(size);
2352 if (!tx_ring->buffer_info)
2353 goto err;
2354
2355 /* round up to nearest 4K */
2356 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2357 tx_ring->size = ALIGN(tx_ring->size, 4096);
2358
2359 err = e1000_alloc_ring_dma(adapter, tx_ring);
2360 if (err)
2361 goto err;
2362
2363 tx_ring->next_to_use = 0;
2364 tx_ring->next_to_clean = 0;
2365
2366 return 0;
2367 err:
2368 vfree(tx_ring->buffer_info);
2369 e_err("Unable to allocate memory for the transmit descriptor ring\n");
2370 return err;
2371 }
2372
2373 /**
2374 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2375 * @rx_ring: Rx descriptor ring
2376 *
2377 * Returns 0 on success, negative on failure
2378 **/
2379 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
2380 {
2381 struct e1000_adapter *adapter = rx_ring->adapter;
2382 struct e1000_buffer *buffer_info;
2383 int i, size, desc_len, err = -ENOMEM;
2384
2385 size = sizeof(struct e1000_buffer) * rx_ring->count;
2386 rx_ring->buffer_info = vzalloc(size);
2387 if (!rx_ring->buffer_info)
2388 goto err;
2389
2390 for (i = 0; i < rx_ring->count; i++) {
2391 buffer_info = &rx_ring->buffer_info[i];
2392 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2393 sizeof(struct e1000_ps_page),
2394 GFP_KERNEL);
2395 if (!buffer_info->ps_pages)
2396 goto err_pages;
2397 }
2398
2399 desc_len = sizeof(union e1000_rx_desc_packet_split);
2400
2401 /* Round up to nearest 4K */
2402 rx_ring->size = rx_ring->count * desc_len;
2403 rx_ring->size = ALIGN(rx_ring->size, 4096);
2404
2405 err = e1000_alloc_ring_dma(adapter, rx_ring);
2406 if (err)
2407 goto err_pages;
2408
2409 rx_ring->next_to_clean = 0;
2410 rx_ring->next_to_use = 0;
2411 rx_ring->rx_skb_top = NULL;
2412
2413 return 0;
2414
2415 err_pages:
2416 for (i = 0; i < rx_ring->count; i++) {
2417 buffer_info = &rx_ring->buffer_info[i];
2418 kfree(buffer_info->ps_pages);
2419 }
2420 err:
2421 vfree(rx_ring->buffer_info);
2422 e_err("Unable to allocate memory for the receive descriptor ring\n");
2423 return err;
2424 }
2425
2426 /**
2427 * e1000_clean_tx_ring - Free Tx Buffers
2428 * @tx_ring: Tx descriptor ring
2429 **/
2430 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
2431 {
2432 struct e1000_adapter *adapter = tx_ring->adapter;
2433 struct e1000_buffer *buffer_info;
2434 unsigned long size;
2435 unsigned int i;
2436
2437 for (i = 0; i < tx_ring->count; i++) {
2438 buffer_info = &tx_ring->buffer_info[i];
2439 e1000_put_txbuf(tx_ring, buffer_info);
2440 }
2441
2442 netdev_reset_queue(adapter->netdev);
2443 size = sizeof(struct e1000_buffer) * tx_ring->count;
2444 memset(tx_ring->buffer_info, 0, size);
2445
2446 memset(tx_ring->desc, 0, tx_ring->size);
2447
2448 tx_ring->next_to_use = 0;
2449 tx_ring->next_to_clean = 0;
2450
2451 writel(0, tx_ring->head);
2452 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2453 e1000e_update_tdt_wa(tx_ring, 0);
2454 else
2455 writel(0, tx_ring->tail);
2456 }
2457
2458 /**
2459 * e1000e_free_tx_resources - Free Tx Resources per Queue
2460 * @tx_ring: Tx descriptor ring
2461 *
2462 * Free all transmit software resources
2463 **/
2464 void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
2465 {
2466 struct e1000_adapter *adapter = tx_ring->adapter;
2467 struct pci_dev *pdev = adapter->pdev;
2468
2469 e1000_clean_tx_ring(tx_ring);
2470
2471 vfree(tx_ring->buffer_info);
2472 tx_ring->buffer_info = NULL;
2473
2474 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2475 tx_ring->dma);
2476 tx_ring->desc = NULL;
2477 }
2478
2479 /**
2480 * e1000e_free_rx_resources - Free Rx Resources
2481 * @rx_ring: Rx descriptor ring
2482 *
2483 * Free all receive software resources
2484 **/
2485 void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
2486 {
2487 struct e1000_adapter *adapter = rx_ring->adapter;
2488 struct pci_dev *pdev = adapter->pdev;
2489 int i;
2490
2491 e1000_clean_rx_ring(rx_ring);
2492
2493 for (i = 0; i < rx_ring->count; i++)
2494 kfree(rx_ring->buffer_info[i].ps_pages);
2495
2496 vfree(rx_ring->buffer_info);
2497 rx_ring->buffer_info = NULL;
2498
2499 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2500 rx_ring->dma);
2501 rx_ring->desc = NULL;
2502 }
2503
2504 /**
2505 * e1000_update_itr - update the dynamic ITR value based on statistics
2506 * @adapter: pointer to adapter
2507 * @itr_setting: current adapter->itr
2508 * @packets: the number of packets during this measurement interval
2509 * @bytes: the number of bytes during this measurement interval
2510 *
2511 * Stores a new ITR value based on packets and byte
2512 * counts during the last interrupt. The advantage of per interrupt
2513 * computation is faster updates and more accurate ITR for the current
2514 * traffic pattern. Constants in this function were computed
2515 * based on theoretical maximum wire speed and thresholds were set based
2516 * on testing data as well as attempting to minimize response time
2517 * while increasing bulk throughput. This functionality is controlled
2518 * by the InterruptThrottleRate module parameter.
2519 **/
2520 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
2521 {
2522 unsigned int retval = itr_setting;
2523
2524 if (packets == 0)
2525 return itr_setting;
2526
2527 switch (itr_setting) {
2528 case lowest_latency:
2529 /* handle TSO and jumbo frames */
2530 if (bytes / packets > 8000)
2531 retval = bulk_latency;
2532 else if ((packets < 5) && (bytes > 512))
2533 retval = low_latency;
2534 break;
2535 case low_latency: /* 50 usec aka 20000 ints/s */
2536 if (bytes > 10000) {
2537 /* this if handles the TSO accounting */
2538 if (bytes / packets > 8000)
2539 retval = bulk_latency;
2540 else if ((packets < 10) || ((bytes / packets) > 1200))
2541 retval = bulk_latency;
2542 else if ((packets > 35))
2543 retval = lowest_latency;
2544 } else if (bytes / packets > 2000) {
2545 retval = bulk_latency;
2546 } else if (packets <= 2 && bytes < 512) {
2547 retval = lowest_latency;
2548 }
2549 break;
2550 case bulk_latency: /* 250 usec aka 4000 ints/s */
2551 if (bytes > 25000) {
2552 if (packets > 35)
2553 retval = low_latency;
2554 } else if (bytes < 6000) {
2555 retval = low_latency;
2556 }
2557 break;
2558 }
2559
2560 return retval;
2561 }
2562
2563 static void e1000_set_itr(struct e1000_adapter *adapter)
2564 {
2565 u16 current_itr;
2566 u32 new_itr = adapter->itr;
2567
2568 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2569 if (adapter->link_speed != SPEED_1000) {
2570 current_itr = 0;
2571 new_itr = 4000;
2572 goto set_itr_now;
2573 }
2574
2575 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2576 new_itr = 0;
2577 goto set_itr_now;
2578 }
2579
2580 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2581 adapter->total_tx_packets,
2582 adapter->total_tx_bytes);
2583 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2584 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2585 adapter->tx_itr = low_latency;
2586
2587 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2588 adapter->total_rx_packets,
2589 adapter->total_rx_bytes);
2590 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2591 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2592 adapter->rx_itr = low_latency;
2593
2594 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2595
2596 /* counts and packets in update_itr are dependent on these numbers */
2597 switch (current_itr) {
2598 case lowest_latency:
2599 new_itr = 70000;
2600 break;
2601 case low_latency:
2602 new_itr = 20000; /* aka hwitr = ~200 */
2603 break;
2604 case bulk_latency:
2605 new_itr = 4000;
2606 break;
2607 default:
2608 break;
2609 }
2610
2611 set_itr_now:
2612 if (new_itr != adapter->itr) {
2613 /* this attempts to bias the interrupt rate towards Bulk
2614 * by adding intermediate steps when interrupt rate is
2615 * increasing
2616 */
2617 new_itr = new_itr > adapter->itr ?
2618 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
2619 adapter->itr = new_itr;
2620 adapter->rx_ring->itr_val = new_itr;
2621 if (adapter->msix_entries)
2622 adapter->rx_ring->set_itr = 1;
2623 else
2624 e1000e_write_itr(adapter, new_itr);
2625 }
2626 }
2627
2628 /**
2629 * e1000e_write_itr - write the ITR value to the appropriate registers
2630 * @adapter: address of board private structure
2631 * @itr: new ITR value to program
2632 *
2633 * e1000e_write_itr determines if the adapter is in MSI-X mode
2634 * and, if so, writes the EITR registers with the ITR value.
2635 * Otherwise, it writes the ITR value into the ITR register.
2636 **/
2637 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2638 {
2639 struct e1000_hw *hw = &adapter->hw;
2640 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2641
2642 if (adapter->msix_entries) {
2643 int vector;
2644
2645 for (vector = 0; vector < adapter->num_vectors; vector++)
2646 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2647 } else {
2648 ew32(ITR, new_itr);
2649 }
2650 }
2651
2652 /**
2653 * e1000_alloc_queues - Allocate memory for all rings
2654 * @adapter: board private structure to initialize
2655 **/
2656 static int e1000_alloc_queues(struct e1000_adapter *adapter)
2657 {
2658 int size = sizeof(struct e1000_ring);
2659
2660 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
2661 if (!adapter->tx_ring)
2662 goto err;
2663 adapter->tx_ring->count = adapter->tx_ring_count;
2664 adapter->tx_ring->adapter = adapter;
2665
2666 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
2667 if (!adapter->rx_ring)
2668 goto err;
2669 adapter->rx_ring->count = adapter->rx_ring_count;
2670 adapter->rx_ring->adapter = adapter;
2671
2672 return 0;
2673 err:
2674 e_err("Unable to allocate memory for queues\n");
2675 kfree(adapter->rx_ring);
2676 kfree(adapter->tx_ring);
2677 return -ENOMEM;
2678 }
2679
2680 /**
2681 * e1000e_poll - NAPI Rx polling callback
2682 * @napi: struct associated with this polling callback
2683 * @weight: number of packets driver is allowed to process this poll
2684 **/
2685 static int e1000e_poll(struct napi_struct *napi, int weight)
2686 {
2687 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2688 napi);
2689 struct e1000_hw *hw = &adapter->hw;
2690 struct net_device *poll_dev = adapter->netdev;
2691 int tx_cleaned = 1, work_done = 0;
2692
2693 adapter = netdev_priv(poll_dev);
2694
2695 if (!adapter->msix_entries ||
2696 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2697 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
2698
2699 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
2700
2701 if (!tx_cleaned)
2702 work_done = weight;
2703
2704 /* If weight not fully consumed, exit the polling mode */
2705 if (work_done < weight) {
2706 if (adapter->itr_setting & 3)
2707 e1000_set_itr(adapter);
2708 napi_complete(napi);
2709 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2710 if (adapter->msix_entries)
2711 ew32(IMS, adapter->rx_ring->ims_val);
2712 else
2713 e1000_irq_enable(adapter);
2714 }
2715 }
2716
2717 return work_done;
2718 }
2719
2720 static int e1000_vlan_rx_add_vid(struct net_device *netdev,
2721 __always_unused __be16 proto, u16 vid)
2722 {
2723 struct e1000_adapter *adapter = netdev_priv(netdev);
2724 struct e1000_hw *hw = &adapter->hw;
2725 u32 vfta, index;
2726
2727 /* don't update vlan cookie if already programmed */
2728 if ((adapter->hw.mng_cookie.status &
2729 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2730 (vid == adapter->mng_vlan_id))
2731 return 0;
2732
2733 /* add VID to filter table */
2734 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2735 index = (vid >> 5) & 0x7F;
2736 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2737 vfta |= (1 << (vid & 0x1F));
2738 hw->mac.ops.write_vfta(hw, index, vfta);
2739 }
2740
2741 set_bit(vid, adapter->active_vlans);
2742
2743 return 0;
2744 }
2745
2746 static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
2747 __always_unused __be16 proto, u16 vid)
2748 {
2749 struct e1000_adapter *adapter = netdev_priv(netdev);
2750 struct e1000_hw *hw = &adapter->hw;
2751 u32 vfta, index;
2752
2753 if ((adapter->hw.mng_cookie.status &
2754 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2755 (vid == adapter->mng_vlan_id)) {
2756 /* release control to f/w */
2757 e1000e_release_hw_control(adapter);
2758 return 0;
2759 }
2760
2761 /* remove VID from filter table */
2762 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2763 index = (vid >> 5) & 0x7F;
2764 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2765 vfta &= ~(1 << (vid & 0x1F));
2766 hw->mac.ops.write_vfta(hw, index, vfta);
2767 }
2768
2769 clear_bit(vid, adapter->active_vlans);
2770
2771 return 0;
2772 }
2773
2774 /**
2775 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2776 * @adapter: board private structure to initialize
2777 **/
2778 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
2779 {
2780 struct net_device *netdev = adapter->netdev;
2781 struct e1000_hw *hw = &adapter->hw;
2782 u32 rctl;
2783
2784 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2785 /* disable VLAN receive filtering */
2786 rctl = er32(RCTL);
2787 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2788 ew32(RCTL, rctl);
2789
2790 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2791 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2792 adapter->mng_vlan_id);
2793 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
2794 }
2795 }
2796 }
2797
2798 /**
2799 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2800 * @adapter: board private structure to initialize
2801 **/
2802 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2803 {
2804 struct e1000_hw *hw = &adapter->hw;
2805 u32 rctl;
2806
2807 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2808 /* enable VLAN receive filtering */
2809 rctl = er32(RCTL);
2810 rctl |= E1000_RCTL_VFE;
2811 rctl &= ~E1000_RCTL_CFIEN;
2812 ew32(RCTL, rctl);
2813 }
2814 }
2815
2816 /**
2817 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2818 * @adapter: board private structure to initialize
2819 **/
2820 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
2821 {
2822 struct e1000_hw *hw = &adapter->hw;
2823 u32 ctrl;
2824
2825 /* disable VLAN tag insert/strip */
2826 ctrl = er32(CTRL);
2827 ctrl &= ~E1000_CTRL_VME;
2828 ew32(CTRL, ctrl);
2829 }
2830
2831 /**
2832 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2833 * @adapter: board private structure to initialize
2834 **/
2835 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2836 {
2837 struct e1000_hw *hw = &adapter->hw;
2838 u32 ctrl;
2839
2840 /* enable VLAN tag insert/strip */
2841 ctrl = er32(CTRL);
2842 ctrl |= E1000_CTRL_VME;
2843 ew32(CTRL, ctrl);
2844 }
2845
2846 static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2847 {
2848 struct net_device *netdev = adapter->netdev;
2849 u16 vid = adapter->hw.mng_cookie.vlan_id;
2850 u16 old_vid = adapter->mng_vlan_id;
2851
2852 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2853 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
2854 adapter->mng_vlan_id = vid;
2855 }
2856
2857 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2858 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
2859 }
2860
2861 static void e1000_restore_vlan(struct e1000_adapter *adapter)
2862 {
2863 u16 vid;
2864
2865 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
2866
2867 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2868 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
2869 }
2870
2871 static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2872 {
2873 struct e1000_hw *hw = &adapter->hw;
2874 u32 manc, manc2h, mdef, i, j;
2875
2876 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2877 return;
2878
2879 manc = er32(MANC);
2880
2881 /* enable receiving management packets to the host. this will probably
2882 * generate destination unreachable messages from the host OS, but
2883 * the packets will be handled on SMBUS
2884 */
2885 manc |= E1000_MANC_EN_MNG2HOST;
2886 manc2h = er32(MANC2H);
2887
2888 switch (hw->mac.type) {
2889 default:
2890 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2891 break;
2892 case e1000_82574:
2893 case e1000_82583:
2894 /* Check if IPMI pass-through decision filter already exists;
2895 * if so, enable it.
2896 */
2897 for (i = 0, j = 0; i < 8; i++) {
2898 mdef = er32(MDEF(i));
2899
2900 /* Ignore filters with anything other than IPMI ports */
2901 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2902 continue;
2903
2904 /* Enable this decision filter in MANC2H */
2905 if (mdef)
2906 manc2h |= (1 << i);
2907
2908 j |= mdef;
2909 }
2910
2911 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2912 break;
2913
2914 /* Create new decision filter in an empty filter */
2915 for (i = 0, j = 0; i < 8; i++)
2916 if (er32(MDEF(i)) == 0) {
2917 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2918 E1000_MDEF_PORT_664));
2919 manc2h |= (1 << 1);
2920 j++;
2921 break;
2922 }
2923
2924 if (!j)
2925 e_warn("Unable to create IPMI pass-through filter\n");
2926 break;
2927 }
2928
2929 ew32(MANC2H, manc2h);
2930 ew32(MANC, manc);
2931 }
2932
2933 /**
2934 * e1000_configure_tx - Configure Transmit Unit after Reset
2935 * @adapter: board private structure
2936 *
2937 * Configure the Tx unit of the MAC after a reset.
2938 **/
2939 static void e1000_configure_tx(struct e1000_adapter *adapter)
2940 {
2941 struct e1000_hw *hw = &adapter->hw;
2942 struct e1000_ring *tx_ring = adapter->tx_ring;
2943 u64 tdba;
2944 u32 tdlen, tctl, tarc;
2945
2946 /* Setup the HW Tx Head and Tail descriptor pointers */
2947 tdba = tx_ring->dma;
2948 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
2949 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2950 ew32(TDBAH(0), (tdba >> 32));
2951 ew32(TDLEN(0), tdlen);
2952 ew32(TDH(0), 0);
2953 ew32(TDT(0), 0);
2954 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2955 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
2956
2957 /* Set the Tx Interrupt Delay register */
2958 ew32(TIDV, adapter->tx_int_delay);
2959 /* Tx irq moderation */
2960 ew32(TADV, adapter->tx_abs_int_delay);
2961
2962 if (adapter->flags2 & FLAG2_DMA_BURST) {
2963 u32 txdctl = er32(TXDCTL(0));
2964
2965 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2966 E1000_TXDCTL_WTHRESH);
2967 /* set up some performance related parameters to encourage the
2968 * hardware to use the bus more efficiently in bursts, depends
2969 * on the tx_int_delay to be enabled,
2970 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2971 * hthresh = 1 ==> prefetch when one or more available
2972 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2973 * BEWARE: this seems to work but should be considered first if
2974 * there are Tx hangs or other Tx related bugs
2975 */
2976 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2977 ew32(TXDCTL(0), txdctl);
2978 }
2979 /* erratum work around: set txdctl the same for both queues */
2980 ew32(TXDCTL(1), er32(TXDCTL(0)));
2981
2982 /* Program the Transmit Control Register */
2983 tctl = er32(TCTL);
2984 tctl &= ~E1000_TCTL_CT;
2985 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2986 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2987
2988 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
2989 tarc = er32(TARC(0));
2990 /* set the speed mode bit, we'll clear it if we're not at
2991 * gigabit link later
2992 */
2993 #define SPEED_MODE_BIT (1 << 21)
2994 tarc |= SPEED_MODE_BIT;
2995 ew32(TARC(0), tarc);
2996 }
2997
2998 /* errata: program both queues to unweighted RR */
2999 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
3000 tarc = er32(TARC(0));
3001 tarc |= 1;
3002 ew32(TARC(0), tarc);
3003 tarc = er32(TARC(1));
3004 tarc |= 1;
3005 ew32(TARC(1), tarc);
3006 }
3007
3008 /* Setup Transmit Descriptor Settings for eop descriptor */
3009 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
3010
3011 /* only set IDE if we are delaying interrupts using the timers */
3012 if (adapter->tx_int_delay)
3013 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3014
3015 /* enable Report Status bit */
3016 adapter->txd_cmd |= E1000_TXD_CMD_RS;
3017
3018 ew32(TCTL, tctl);
3019
3020 hw->mac.ops.config_collision_dist(hw);
3021
3022 /* SPT Si errata workaround to avoid data corruption */
3023 if (hw->mac.type == e1000_pch_spt) {
3024 u32 reg_val;
3025
3026 reg_val = er32(IOSFPC);
3027 reg_val |= E1000_RCTL_RDMTS_HEX;
3028 ew32(IOSFPC, reg_val);
3029
3030 reg_val = er32(TARC(0));
3031 reg_val |= E1000_TARC0_CB_MULTIQ_3_REQ;
3032 ew32(TARC(0), reg_val);
3033 }
3034 }
3035
3036 /**
3037 * e1000_setup_rctl - configure the receive control registers
3038 * @adapter: Board private structure
3039 **/
3040 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3041 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3042 static void e1000_setup_rctl(struct e1000_adapter *adapter)
3043 {
3044 struct e1000_hw *hw = &adapter->hw;
3045 u32 rctl, rfctl;
3046 u32 pages = 0;
3047
3048 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3049 * If jumbo frames not set, program related MAC/PHY registers
3050 * to h/w defaults
3051 */
3052 if (hw->mac.type >= e1000_pch2lan) {
3053 s32 ret_val;
3054
3055 if (adapter->netdev->mtu > ETH_DATA_LEN)
3056 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3057 else
3058 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3059
3060 if (ret_val)
3061 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3062 }
3063
3064 /* Program MC offset vector base */
3065 rctl = er32(RCTL);
3066 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3067 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3068 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3069 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3070
3071 /* Do not Store bad packets */
3072 rctl &= ~E1000_RCTL_SBP;
3073
3074 /* Enable Long Packet receive */
3075 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3076 rctl &= ~E1000_RCTL_LPE;
3077 else
3078 rctl |= E1000_RCTL_LPE;
3079
3080 /* Some systems expect that the CRC is included in SMBUS traffic. The
3081 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3082 * host memory when this is enabled
3083 */
3084 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3085 rctl |= E1000_RCTL_SECRC;
3086
3087 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3088 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3089 u16 phy_data;
3090
3091 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3092 phy_data &= 0xfff8;
3093 phy_data |= (1 << 2);
3094 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3095
3096 e1e_rphy(hw, 22, &phy_data);
3097 phy_data &= 0x0fff;
3098 phy_data |= (1 << 14);
3099 e1e_wphy(hw, 0x10, 0x2823);
3100 e1e_wphy(hw, 0x11, 0x0003);
3101 e1e_wphy(hw, 22, phy_data);
3102 }
3103
3104 /* Setup buffer sizes */
3105 rctl &= ~E1000_RCTL_SZ_4096;
3106 rctl |= E1000_RCTL_BSEX;
3107 switch (adapter->rx_buffer_len) {
3108 case 2048:
3109 default:
3110 rctl |= E1000_RCTL_SZ_2048;
3111 rctl &= ~E1000_RCTL_BSEX;
3112 break;
3113 case 4096:
3114 rctl |= E1000_RCTL_SZ_4096;
3115 break;
3116 case 8192:
3117 rctl |= E1000_RCTL_SZ_8192;
3118 break;
3119 case 16384:
3120 rctl |= E1000_RCTL_SZ_16384;
3121 break;
3122 }
3123
3124 /* Enable Extended Status in all Receive Descriptors */
3125 rfctl = er32(RFCTL);
3126 rfctl |= E1000_RFCTL_EXTEN;
3127 ew32(RFCTL, rfctl);
3128
3129 /* 82571 and greater support packet-split where the protocol
3130 * header is placed in skb->data and the packet data is
3131 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3132 * In the case of a non-split, skb->data is linearly filled,
3133 * followed by the page buffers. Therefore, skb->data is
3134 * sized to hold the largest protocol header.
3135 *
3136 * allocations using alloc_page take too long for regular MTU
3137 * so only enable packet split for jumbo frames
3138 *
3139 * Using pages when the page size is greater than 16k wastes
3140 * a lot of memory, since we allocate 3 pages at all times
3141 * per packet.
3142 */
3143 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
3144 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
3145 adapter->rx_ps_pages = pages;
3146 else
3147 adapter->rx_ps_pages = 0;
3148
3149 if (adapter->rx_ps_pages) {
3150 u32 psrctl = 0;
3151
3152 /* Enable Packet split descriptors */
3153 rctl |= E1000_RCTL_DTYP_PS;
3154
3155 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
3156
3157 switch (adapter->rx_ps_pages) {
3158 case 3:
3159 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3160 /* fall-through */
3161 case 2:
3162 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3163 /* fall-through */
3164 case 1:
3165 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
3166 break;
3167 }
3168
3169 ew32(PSRCTL, psrctl);
3170 }
3171
3172 /* This is useful for sniffing bad packets. */
3173 if (adapter->netdev->features & NETIF_F_RXALL) {
3174 /* UPE and MPE will be handled by normal PROMISC logic
3175 * in e1000e_set_rx_mode
3176 */
3177 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3178 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3179 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3180
3181 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3182 E1000_RCTL_DPF | /* Allow filtered pause */
3183 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3184 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3185 * and that breaks VLANs.
3186 */
3187 }
3188
3189 ew32(RCTL, rctl);
3190 /* just started the receive unit, no need to restart */
3191 adapter->flags &= ~FLAG_RESTART_NOW;
3192 }
3193
3194 /**
3195 * e1000_configure_rx - Configure Receive Unit after Reset
3196 * @adapter: board private structure
3197 *
3198 * Configure the Rx unit of the MAC after a reset.
3199 **/
3200 static void e1000_configure_rx(struct e1000_adapter *adapter)
3201 {
3202 struct e1000_hw *hw = &adapter->hw;
3203 struct e1000_ring *rx_ring = adapter->rx_ring;
3204 u64 rdba;
3205 u32 rdlen, rctl, rxcsum, ctrl_ext;
3206
3207 if (adapter->rx_ps_pages) {
3208 /* this is a 32 byte descriptor */
3209 rdlen = rx_ring->count *
3210 sizeof(union e1000_rx_desc_packet_split);
3211 adapter->clean_rx = e1000_clean_rx_irq_ps;
3212 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
3213 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
3214 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3215 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3216 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
3217 } else {
3218 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3219 adapter->clean_rx = e1000_clean_rx_irq;
3220 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3221 }
3222
3223 /* disable receives while setting up the descriptors */
3224 rctl = er32(RCTL);
3225 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3226 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3227 e1e_flush();
3228 usleep_range(10000, 20000);
3229
3230 if (adapter->flags2 & FLAG2_DMA_BURST) {
3231 /* set the writeback threshold (only takes effect if the RDTR
3232 * is set). set GRAN=1 and write back up to 0x4 worth, and
3233 * enable prefetching of 0x20 Rx descriptors
3234 * granularity = 01
3235 * wthresh = 04,
3236 * hthresh = 04,
3237 * pthresh = 0x20
3238 */
3239 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3240 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3241
3242 /* override the delay timers for enabling bursting, only if
3243 * the value was not set by the user via module options
3244 */
3245 if (adapter->rx_int_delay == DEFAULT_RDTR)
3246 adapter->rx_int_delay = BURST_RDTR;
3247 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3248 adapter->rx_abs_int_delay = BURST_RADV;
3249 }
3250
3251 /* set the Receive Delay Timer Register */
3252 ew32(RDTR, adapter->rx_int_delay);
3253
3254 /* irq moderation */
3255 ew32(RADV, adapter->rx_abs_int_delay);
3256 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
3257 e1000e_write_itr(adapter, adapter->itr);
3258
3259 ctrl_ext = er32(CTRL_EXT);
3260 /* Auto-Mask interrupts upon ICR access */
3261 ctrl_ext |= E1000_CTRL_EXT_IAME;
3262 ew32(IAM, 0xffffffff);
3263 ew32(CTRL_EXT, ctrl_ext);
3264 e1e_flush();
3265
3266 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3267 * the Base and Length of the Rx Descriptor Ring
3268 */
3269 rdba = rx_ring->dma;
3270 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3271 ew32(RDBAH(0), (rdba >> 32));
3272 ew32(RDLEN(0), rdlen);
3273 ew32(RDH(0), 0);
3274 ew32(RDT(0), 0);
3275 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3276 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
3277
3278 /* Enable Receive Checksum Offload for TCP and UDP */
3279 rxcsum = er32(RXCSUM);
3280 if (adapter->netdev->features & NETIF_F_RXCSUM)
3281 rxcsum |= E1000_RXCSUM_TUOFL;
3282 else
3283 rxcsum &= ~E1000_RXCSUM_TUOFL;
3284 ew32(RXCSUM, rxcsum);
3285
3286 /* With jumbo frames, excessive C-state transition latencies result
3287 * in dropped transactions.
3288 */
3289 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3290 u32 lat =
3291 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3292 adapter->max_frame_size) * 8 / 1000;
3293
3294 if (adapter->flags & FLAG_IS_ICH) {
3295 u32 rxdctl = er32(RXDCTL(0));
3296
3297 ew32(RXDCTL(0), rxdctl | 0x3);
3298 }
3299
3300 pm_qos_update_request(&adapter->pm_qos_req, lat);
3301 } else {
3302 pm_qos_update_request(&adapter->pm_qos_req,
3303 PM_QOS_DEFAULT_VALUE);
3304 }
3305
3306 /* Enable Receives */
3307 ew32(RCTL, rctl);
3308 }
3309
3310 /**
3311 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3312 * @netdev: network interface device structure
3313 *
3314 * Writes multicast address list to the MTA hash table.
3315 * Returns: -ENOMEM on failure
3316 * 0 on no addresses written
3317 * X on writing X addresses to MTA
3318 */
3319 static int e1000e_write_mc_addr_list(struct net_device *netdev)
3320 {
3321 struct e1000_adapter *adapter = netdev_priv(netdev);
3322 struct e1000_hw *hw = &adapter->hw;
3323 struct netdev_hw_addr *ha;
3324 u8 *mta_list;
3325 int i;
3326
3327 if (netdev_mc_empty(netdev)) {
3328 /* nothing to program, so clear mc list */
3329 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3330 return 0;
3331 }
3332
3333 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3334 if (!mta_list)
3335 return -ENOMEM;
3336
3337 /* update_mc_addr_list expects a packed array of only addresses. */
3338 i = 0;
3339 netdev_for_each_mc_addr(ha, netdev)
3340 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3341
3342 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3343 kfree(mta_list);
3344
3345 return netdev_mc_count(netdev);
3346 }
3347
3348 /**
3349 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3350 * @netdev: network interface device structure
3351 *
3352 * Writes unicast address list to the RAR table.
3353 * Returns: -ENOMEM on failure/insufficient address space
3354 * 0 on no addresses written
3355 * X on writing X addresses to the RAR table
3356 **/
3357 static int e1000e_write_uc_addr_list(struct net_device *netdev)
3358 {
3359 struct e1000_adapter *adapter = netdev_priv(netdev);
3360 struct e1000_hw *hw = &adapter->hw;
3361 unsigned int rar_entries;
3362 int count = 0;
3363
3364 rar_entries = hw->mac.ops.rar_get_count(hw);
3365
3366 /* save a rar entry for our hardware address */
3367 rar_entries--;
3368
3369 /* save a rar entry for the LAA workaround */
3370 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3371 rar_entries--;
3372
3373 /* return ENOMEM indicating insufficient memory for addresses */
3374 if (netdev_uc_count(netdev) > rar_entries)
3375 return -ENOMEM;
3376
3377 if (!netdev_uc_empty(netdev) && rar_entries) {
3378 struct netdev_hw_addr *ha;
3379
3380 /* write the addresses in reverse order to avoid write
3381 * combining
3382 */
3383 netdev_for_each_uc_addr(ha, netdev) {
3384 int rval;
3385
3386 if (!rar_entries)
3387 break;
3388 rval = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3389 if (rval < 0)
3390 return -ENOMEM;
3391 count++;
3392 }
3393 }
3394
3395 /* zero out the remaining RAR entries not used above */
3396 for (; rar_entries > 0; rar_entries--) {
3397 ew32(RAH(rar_entries), 0);
3398 ew32(RAL(rar_entries), 0);
3399 }
3400 e1e_flush();
3401
3402 return count;
3403 }
3404
3405 /**
3406 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3407 * @netdev: network interface device structure
3408 *
3409 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3410 * address list or the network interface flags are updated. This routine is
3411 * responsible for configuring the hardware for proper unicast, multicast,
3412 * promiscuous mode, and all-multi behavior.
3413 **/
3414 static void e1000e_set_rx_mode(struct net_device *netdev)
3415 {
3416 struct e1000_adapter *adapter = netdev_priv(netdev);
3417 struct e1000_hw *hw = &adapter->hw;
3418 u32 rctl;
3419
3420 if (pm_runtime_suspended(netdev->dev.parent))
3421 return;
3422
3423 /* Check for Promiscuous and All Multicast modes */
3424 rctl = er32(RCTL);
3425
3426 /* clear the affected bits */
3427 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3428
3429 if (netdev->flags & IFF_PROMISC) {
3430 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3431 /* Do not hardware filter VLANs in promisc mode */
3432 e1000e_vlan_filter_disable(adapter);
3433 } else {
3434 int count;
3435
3436 if (netdev->flags & IFF_ALLMULTI) {
3437 rctl |= E1000_RCTL_MPE;
3438 } else {
3439 /* Write addresses to the MTA, if the attempt fails
3440 * then we should just turn on promiscuous mode so
3441 * that we can at least receive multicast traffic
3442 */
3443 count = e1000e_write_mc_addr_list(netdev);
3444 if (count < 0)
3445 rctl |= E1000_RCTL_MPE;
3446 }
3447 e1000e_vlan_filter_enable(adapter);
3448 /* Write addresses to available RAR registers, if there is not
3449 * sufficient space to store all the addresses then enable
3450 * unicast promiscuous mode
3451 */
3452 count = e1000e_write_uc_addr_list(netdev);
3453 if (count < 0)
3454 rctl |= E1000_RCTL_UPE;
3455 }
3456
3457 ew32(RCTL, rctl);
3458
3459 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3460 e1000e_vlan_strip_enable(adapter);
3461 else
3462 e1000e_vlan_strip_disable(adapter);
3463 }
3464
3465 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3466 {
3467 struct e1000_hw *hw = &adapter->hw;
3468 u32 mrqc, rxcsum;
3469 u32 rss_key[10];
3470 int i;
3471
3472 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3473 for (i = 0; i < 10; i++)
3474 ew32(RSSRK(i), rss_key[i]);
3475
3476 /* Direct all traffic to queue 0 */
3477 for (i = 0; i < 32; i++)
3478 ew32(RETA(i), 0);
3479
3480 /* Disable raw packet checksumming so that RSS hash is placed in
3481 * descriptor on writeback.
3482 */
3483 rxcsum = er32(RXCSUM);
3484 rxcsum |= E1000_RXCSUM_PCSD;
3485
3486 ew32(RXCSUM, rxcsum);
3487
3488 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3489 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3490 E1000_MRQC_RSS_FIELD_IPV6 |
3491 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3492 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3493
3494 ew32(MRQC, mrqc);
3495 }
3496
3497 /**
3498 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3499 * @adapter: board private structure
3500 * @timinca: pointer to returned time increment attributes
3501 *
3502 * Get attributes for incrementing the System Time Register SYSTIML/H at
3503 * the default base frequency, and set the cyclecounter shift value.
3504 **/
3505 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3506 {
3507 struct e1000_hw *hw = &adapter->hw;
3508 u32 incvalue, incperiod, shift;
3509
3510 /* Make sure clock is enabled on I217/I218/I219 before checking
3511 * the frequency
3512 */
3513 if (((hw->mac.type == e1000_pch_lpt) ||
3514 (hw->mac.type == e1000_pch_spt)) &&
3515 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3516 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3517 u32 fextnvm7 = er32(FEXTNVM7);
3518
3519 if (!(fextnvm7 & (1 << 0))) {
3520 ew32(FEXTNVM7, fextnvm7 | (1 << 0));
3521 e1e_flush();
3522 }
3523 }
3524
3525 switch (hw->mac.type) {
3526 case e1000_pch2lan:
3527 case e1000_pch_lpt:
3528 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3529 /* Stable 96MHz frequency */
3530 incperiod = INCPERIOD_96MHz;
3531 incvalue = INCVALUE_96MHz;
3532 shift = INCVALUE_SHIFT_96MHz;
3533 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz;
3534 } else {
3535 /* Stable 25MHz frequency */
3536 incperiod = INCPERIOD_25MHz;
3537 incvalue = INCVALUE_25MHz;
3538 shift = INCVALUE_SHIFT_25MHz;
3539 adapter->cc.shift = shift;
3540 }
3541 break;
3542 case e1000_pch_spt:
3543 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3544 /* Stable 24MHz frequency */
3545 incperiod = INCPERIOD_24MHz;
3546 incvalue = INCVALUE_24MHz;
3547 shift = INCVALUE_SHIFT_24MHz;
3548 adapter->cc.shift = shift;
3549 break;
3550 }
3551 return -EINVAL;
3552 case e1000_82574:
3553 case e1000_82583:
3554 /* Stable 25MHz frequency */
3555 incperiod = INCPERIOD_25MHz;
3556 incvalue = INCVALUE_25MHz;
3557 shift = INCVALUE_SHIFT_25MHz;
3558 adapter->cc.shift = shift;
3559 break;
3560 default:
3561 return -EINVAL;
3562 }
3563
3564 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3565 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3566
3567 return 0;
3568 }
3569
3570 /**
3571 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3572 * @adapter: board private structure
3573 *
3574 * Outgoing time stamping can be enabled and disabled. Play nice and
3575 * disable it when requested, although it shouldn't cause any overhead
3576 * when no packet needs it. At most one packet in the queue may be
3577 * marked for time stamping, otherwise it would be impossible to tell
3578 * for sure to which packet the hardware time stamp belongs.
3579 *
3580 * Incoming time stamping has to be configured via the hardware filters.
3581 * Not all combinations are supported, in particular event type has to be
3582 * specified. Matching the kind of event packet is not supported, with the
3583 * exception of "all V2 events regardless of level 2 or 4".
3584 **/
3585 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3586 struct hwtstamp_config *config)
3587 {
3588 struct e1000_hw *hw = &adapter->hw;
3589 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3590 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
3591 u32 rxmtrl = 0;
3592 u16 rxudp = 0;
3593 bool is_l4 = false;
3594 bool is_l2 = false;
3595 u32 regval;
3596 s32 ret_val;
3597
3598 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3599 return -EINVAL;
3600
3601 /* flags reserved for future extensions - must be zero */
3602 if (config->flags)
3603 return -EINVAL;
3604
3605 switch (config->tx_type) {
3606 case HWTSTAMP_TX_OFF:
3607 tsync_tx_ctl = 0;
3608 break;
3609 case HWTSTAMP_TX_ON:
3610 break;
3611 default:
3612 return -ERANGE;
3613 }
3614
3615 switch (config->rx_filter) {
3616 case HWTSTAMP_FILTER_NONE:
3617 tsync_rx_ctl = 0;
3618 break;
3619 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3620 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3621 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3622 is_l4 = true;
3623 break;
3624 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3625 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3626 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3627 is_l4 = true;
3628 break;
3629 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3630 /* Also time stamps V2 L2 Path Delay Request/Response */
3631 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3632 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3633 is_l2 = true;
3634 break;
3635 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3636 /* Also time stamps V2 L2 Path Delay Request/Response. */
3637 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3638 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3639 is_l2 = true;
3640 break;
3641 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3642 /* Hardware cannot filter just V2 L4 Sync messages;
3643 * fall-through to V2 (both L2 and L4) Sync.
3644 */
3645 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3646 /* Also time stamps V2 Path Delay Request/Response. */
3647 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3648 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3649 is_l2 = true;
3650 is_l4 = true;
3651 break;
3652 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3653 /* Hardware cannot filter just V2 L4 Delay Request messages;
3654 * fall-through to V2 (both L2 and L4) Delay Request.
3655 */
3656 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3657 /* Also time stamps V2 Path Delay Request/Response. */
3658 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3659 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3660 is_l2 = true;
3661 is_l4 = true;
3662 break;
3663 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3664 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3665 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3666 * fall-through to all V2 (both L2 and L4) Events.
3667 */
3668 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3669 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3670 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3671 is_l2 = true;
3672 is_l4 = true;
3673 break;
3674 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3675 /* For V1, the hardware can only filter Sync messages or
3676 * Delay Request messages but not both so fall-through to
3677 * time stamp all packets.
3678 */
3679 case HWTSTAMP_FILTER_ALL:
3680 is_l2 = true;
3681 is_l4 = true;
3682 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3683 config->rx_filter = HWTSTAMP_FILTER_ALL;
3684 break;
3685 default:
3686 return -ERANGE;
3687 }
3688
3689 adapter->hwtstamp_config = *config;
3690
3691 /* enable/disable Tx h/w time stamping */
3692 regval = er32(TSYNCTXCTL);
3693 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3694 regval |= tsync_tx_ctl;
3695 ew32(TSYNCTXCTL, regval);
3696 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3697 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3698 e_err("Timesync Tx Control register not set as expected\n");
3699 return -EAGAIN;
3700 }
3701
3702 /* enable/disable Rx h/w time stamping */
3703 regval = er32(TSYNCRXCTL);
3704 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3705 regval |= tsync_rx_ctl;
3706 ew32(TSYNCRXCTL, regval);
3707 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3708 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3709 (regval & (E1000_TSYNCRXCTL_ENABLED |
3710 E1000_TSYNCRXCTL_TYPE_MASK))) {
3711 e_err("Timesync Rx Control register not set as expected\n");
3712 return -EAGAIN;
3713 }
3714
3715 /* L2: define ethertype filter for time stamped packets */
3716 if (is_l2)
3717 rxmtrl |= ETH_P_1588;
3718
3719 /* define which PTP packets get time stamped */
3720 ew32(RXMTRL, rxmtrl);
3721
3722 /* Filter by destination port */
3723 if (is_l4) {
3724 rxudp = PTP_EV_PORT;
3725 cpu_to_be16s(&rxudp);
3726 }
3727 ew32(RXUDP, rxudp);
3728
3729 e1e_flush();
3730
3731 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3732 er32(RXSTMPH);
3733 er32(TXSTMPH);
3734
3735 /* Get and set the System Time Register SYSTIM base frequency */
3736 ret_val = e1000e_get_base_timinca(adapter, &regval);
3737 if (ret_val)
3738 return ret_val;
3739 ew32(TIMINCA, regval);
3740
3741 /* reset the ns time counter */
3742 timecounter_init(&adapter->tc, &adapter->cc,
3743 ktime_to_ns(ktime_get_real()));
3744
3745 return 0;
3746 }
3747
3748 /**
3749 * e1000_configure - configure the hardware for Rx and Tx
3750 * @adapter: private board structure
3751 **/
3752 static void e1000_configure(struct e1000_adapter *adapter)
3753 {
3754 struct e1000_ring *rx_ring = adapter->rx_ring;
3755
3756 e1000e_set_rx_mode(adapter->netdev);
3757
3758 e1000_restore_vlan(adapter);
3759 e1000_init_manageability_pt(adapter);
3760
3761 e1000_configure_tx(adapter);
3762
3763 if (adapter->netdev->features & NETIF_F_RXHASH)
3764 e1000e_setup_rss_hash(adapter);
3765 e1000_setup_rctl(adapter);
3766 e1000_configure_rx(adapter);
3767 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
3768 }
3769
3770 /**
3771 * e1000e_power_up_phy - restore link in case the phy was powered down
3772 * @adapter: address of board private structure
3773 *
3774 * The phy may be powered down to save power and turn off link when the
3775 * driver is unloaded and wake on lan is not enabled (among others)
3776 * *** this routine MUST be followed by a call to e1000e_reset ***
3777 **/
3778 void e1000e_power_up_phy(struct e1000_adapter *adapter)
3779 {
3780 if (adapter->hw.phy.ops.power_up)
3781 adapter->hw.phy.ops.power_up(&adapter->hw);
3782
3783 adapter->hw.mac.ops.setup_link(&adapter->hw);
3784 }
3785
3786 /**
3787 * e1000_power_down_phy - Power down the PHY
3788 *
3789 * Power down the PHY so no link is implied when interface is down.
3790 * The PHY cannot be powered down if management or WoL is active.
3791 */
3792 static void e1000_power_down_phy(struct e1000_adapter *adapter)
3793 {
3794 if (adapter->hw.phy.ops.power_down)
3795 adapter->hw.phy.ops.power_down(&adapter->hw);
3796 }
3797
3798 /**
3799 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3800 *
3801 * We want to clear all pending descriptors from the TX ring.
3802 * zeroing happens when the HW reads the regs. We assign the ring itself as
3803 * the data of the next descriptor. We don't care about the data we are about
3804 * to reset the HW.
3805 */
3806 static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3807 {
3808 struct e1000_hw *hw = &adapter->hw;
3809 struct e1000_ring *tx_ring = adapter->tx_ring;
3810 struct e1000_tx_desc *tx_desc = NULL;
3811 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3812 u16 size = 512;
3813
3814 tctl = er32(TCTL);
3815 ew32(TCTL, tctl | E1000_TCTL_EN);
3816 tdt = er32(TDT(0));
3817 BUG_ON(tdt != tx_ring->next_to_use);
3818 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
3819 tx_desc->buffer_addr = tx_ring->dma;
3820
3821 tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3822 tx_desc->upper.data = 0;
3823 /* flush descriptors to memory before notifying the HW */
3824 wmb();
3825 tx_ring->next_to_use++;
3826 if (tx_ring->next_to_use == tx_ring->count)
3827 tx_ring->next_to_use = 0;
3828 ew32(TDT(0), tx_ring->next_to_use);
3829 mmiowb();
3830 usleep_range(200, 250);
3831 }
3832
3833 /**
3834 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3835 *
3836 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3837 */
3838 static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3839 {
3840 u32 rctl, rxdctl;
3841 struct e1000_hw *hw = &adapter->hw;
3842
3843 rctl = er32(RCTL);
3844 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3845 e1e_flush();
3846 usleep_range(100, 150);
3847
3848 rxdctl = er32(RXDCTL(0));
3849 /* zero the lower 14 bits (prefetch and host thresholds) */
3850 rxdctl &= 0xffffc000;
3851
3852 /* update thresholds: prefetch threshold to 31, host threshold to 1
3853 * and make sure the granularity is "descriptors" and not "cache lines"
3854 */
3855 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC);
3856
3857 ew32(RXDCTL(0), rxdctl);
3858 /* momentarily enable the RX ring for the changes to take effect */
3859 ew32(RCTL, rctl | E1000_RCTL_EN);
3860 e1e_flush();
3861 usleep_range(100, 150);
3862 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3863 }
3864
3865 /**
3866 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3867 *
3868 * In i219, the descriptor rings must be emptied before resetting the HW
3869 * or before changing the device state to D3 during runtime (runtime PM).
3870 *
3871 * Failure to do this will cause the HW to enter a unit hang state which can
3872 * only be released by PCI reset on the device
3873 *
3874 */
3875
3876 static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3877 {
3878 u16 hang_state;
3879 u32 fext_nvm11, tdlen;
3880 struct e1000_hw *hw = &adapter->hw;
3881
3882 /* First, disable MULR fix in FEXTNVM11 */
3883 fext_nvm11 = er32(FEXTNVM11);
3884 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3885 ew32(FEXTNVM11, fext_nvm11);
3886 /* do nothing if we're not in faulty state, or if the queue is empty */
3887 tdlen = er32(TDLEN(0));
3888 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3889 &hang_state);
3890 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
3891 return;
3892 e1000_flush_tx_ring(adapter);
3893 /* recheck, maybe the fault is caused by the rx ring */
3894 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3895 &hang_state);
3896 if (hang_state & FLUSH_DESC_REQUIRED)
3897 e1000_flush_rx_ring(adapter);
3898 }
3899
3900 /**
3901 * e1000e_reset - bring the hardware into a known good state
3902 *
3903 * This function boots the hardware and enables some settings that
3904 * require a configuration cycle of the hardware - those cannot be
3905 * set/changed during runtime. After reset the device needs to be
3906 * properly configured for Rx, Tx etc.
3907 */
3908 void e1000e_reset(struct e1000_adapter *adapter)
3909 {
3910 struct e1000_mac_info *mac = &adapter->hw.mac;
3911 struct e1000_fc_info *fc = &adapter->hw.fc;
3912 struct e1000_hw *hw = &adapter->hw;
3913 u32 tx_space, min_tx_space, min_rx_space;
3914 u32 pba = adapter->pba;
3915 u16 hwm;
3916
3917 /* reset Packet Buffer Allocation to default */
3918 ew32(PBA, pba);
3919
3920 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
3921 /* To maintain wire speed transmits, the Tx FIFO should be
3922 * large enough to accommodate two full transmit packets,
3923 * rounded up to the next 1KB and expressed in KB. Likewise,
3924 * the Rx FIFO should be large enough to accommodate at least
3925 * one full receive packet and is similarly rounded up and
3926 * expressed in KB.
3927 */
3928 pba = er32(PBA);
3929 /* upper 16 bits has Tx packet buffer allocation size in KB */
3930 tx_space = pba >> 16;
3931 /* lower 16 bits has Rx packet buffer allocation size in KB */
3932 pba &= 0xffff;
3933 /* the Tx fifo also stores 16 bytes of information about the Tx
3934 * but don't include ethernet FCS because hardware appends it
3935 */
3936 min_tx_space = (adapter->max_frame_size +
3937 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
3938 min_tx_space = ALIGN(min_tx_space, 1024);
3939 min_tx_space >>= 10;
3940 /* software strips receive CRC, so leave room for it */
3941 min_rx_space = adapter->max_frame_size;
3942 min_rx_space = ALIGN(min_rx_space, 1024);
3943 min_rx_space >>= 10;
3944
3945 /* If current Tx allocation is less than the min Tx FIFO size,
3946 * and the min Tx FIFO size is less than the current Rx FIFO
3947 * allocation, take space away from current Rx allocation
3948 */
3949 if ((tx_space < min_tx_space) &&
3950 ((min_tx_space - tx_space) < pba)) {
3951 pba -= min_tx_space - tx_space;
3952
3953 /* if short on Rx space, Rx wins and must trump Tx
3954 * adjustment
3955 */
3956 if (pba < min_rx_space)
3957 pba = min_rx_space;
3958 }
3959
3960 ew32(PBA, pba);
3961 }
3962
3963 /* flow control settings
3964 *
3965 * The high water mark must be low enough to fit one full frame
3966 * (or the size used for early receive) above it in the Rx FIFO.
3967 * Set it to the lower of:
3968 * - 90% of the Rx FIFO size, and
3969 * - the full Rx FIFO size minus one full frame
3970 */
3971 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3972 fc->pause_time = 0xFFFF;
3973 else
3974 fc->pause_time = E1000_FC_PAUSE_TIME;
3975 fc->send_xon = true;
3976 fc->current_mode = fc->requested_mode;
3977
3978 switch (hw->mac.type) {
3979 case e1000_ich9lan:
3980 case e1000_ich10lan:
3981 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3982 pba = 14;
3983 ew32(PBA, pba);
3984 fc->high_water = 0x2800;
3985 fc->low_water = fc->high_water - 8;
3986 break;
3987 }
3988 /* fall-through */
3989 default:
3990 hwm = min(((pba << 10) * 9 / 10),
3991 ((pba << 10) - adapter->max_frame_size));
3992
3993 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3994 fc->low_water = fc->high_water - 8;
3995 break;
3996 case e1000_pchlan:
3997 /* Workaround PCH LOM adapter hangs with certain network
3998 * loads. If hangs persist, try disabling Tx flow control.
3999 */
4000 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4001 fc->high_water = 0x3500;
4002 fc->low_water = 0x1500;
4003 } else {
4004 fc->high_water = 0x5000;
4005 fc->low_water = 0x3000;
4006 }
4007 fc->refresh_time = 0x1000;
4008 break;
4009 case e1000_pch2lan:
4010 case e1000_pch_lpt:
4011 case e1000_pch_spt:
4012 fc->refresh_time = 0x0400;
4013
4014 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4015 fc->high_water = 0x05C20;
4016 fc->low_water = 0x05048;
4017 fc->pause_time = 0x0650;
4018 break;
4019 }
4020
4021 pba = 14;
4022 ew32(PBA, pba);
4023 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4024 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
4025 break;
4026 }
4027
4028 /* Alignment of Tx data is on an arbitrary byte boundary with the
4029 * maximum size per Tx descriptor limited only to the transmit
4030 * allocation of the packet buffer minus 96 bytes with an upper
4031 * limit of 24KB due to receive synchronization limitations.
4032 */
4033 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4034 24 << 10);
4035
4036 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4037 * fit in receive buffer.
4038 */
4039 if (adapter->itr_setting & 0x3) {
4040 if ((adapter->max_frame_size * 2) > (pba << 10)) {
4041 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4042 dev_info(&adapter->pdev->dev,
4043 "Interrupt Throttle Rate off\n");
4044 adapter->flags2 |= FLAG2_DISABLE_AIM;
4045 e1000e_write_itr(adapter, 0);
4046 }
4047 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4048 dev_info(&adapter->pdev->dev,
4049 "Interrupt Throttle Rate on\n");
4050 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4051 adapter->itr = 20000;
4052 e1000e_write_itr(adapter, adapter->itr);
4053 }
4054 }
4055
4056 if (hw->mac.type == e1000_pch_spt)
4057 e1000_flush_desc_rings(adapter);
4058 /* Allow time for pending master requests to run */
4059 mac->ops.reset_hw(hw);
4060
4061 /* For parts with AMT enabled, let the firmware know
4062 * that the network interface is in control
4063 */
4064 if (adapter->flags & FLAG_HAS_AMT)
4065 e1000e_get_hw_control(adapter);
4066
4067 ew32(WUC, 0);
4068
4069 if (mac->ops.init_hw(hw))
4070 e_err("Hardware Error\n");
4071
4072 e1000_update_mng_vlan(adapter);
4073
4074 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4075 ew32(VET, ETH_P_8021Q);
4076
4077 e1000e_reset_adaptive(hw);
4078
4079 /* initialize systim and reset the ns time counter */
4080 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
4081
4082 /* Set EEE advertisement as appropriate */
4083 if (adapter->flags2 & FLAG2_HAS_EEE) {
4084 s32 ret_val;
4085 u16 adv_addr;
4086
4087 switch (hw->phy.type) {
4088 case e1000_phy_82579:
4089 adv_addr = I82579_EEE_ADVERTISEMENT;
4090 break;
4091 case e1000_phy_i217:
4092 adv_addr = I217_EEE_ADVERTISEMENT;
4093 break;
4094 default:
4095 dev_err(&adapter->pdev->dev,
4096 "Invalid PHY type setting EEE advertisement\n");
4097 return;
4098 }
4099
4100 ret_val = hw->phy.ops.acquire(hw);
4101 if (ret_val) {
4102 dev_err(&adapter->pdev->dev,
4103 "EEE advertisement - unable to acquire PHY\n");
4104 return;
4105 }
4106
4107 e1000_write_emi_reg_locked(hw, adv_addr,
4108 hw->dev_spec.ich8lan.eee_disable ?
4109 0 : adapter->eee_advert);
4110
4111 hw->phy.ops.release(hw);
4112 }
4113
4114 if (!netif_running(adapter->netdev) &&
4115 !test_bit(__E1000_TESTING, &adapter->state))
4116 e1000_power_down_phy(adapter);
4117
4118 e1000_get_phy_info(hw);
4119
4120 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4121 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
4122 u16 phy_data = 0;
4123 /* speed up time to link by disabling smart power down, ignore
4124 * the return value of this function because there is nothing
4125 * different we would do if it failed
4126 */
4127 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
4128 phy_data &= ~IGP02E1000_PM_SPD;
4129 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
4130 }
4131 if (hw->mac.type == e1000_pch_spt && adapter->int_mode == 0) {
4132 u32 reg;
4133
4134 /* Fextnvm7 @ 0xe4[2] = 1 */
4135 reg = er32(FEXTNVM7);
4136 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4137 ew32(FEXTNVM7, reg);
4138 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4139 reg = er32(FEXTNVM9);
4140 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4141 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4142 ew32(FEXTNVM9, reg);
4143 }
4144
4145 }
4146
4147 int e1000e_up(struct e1000_adapter *adapter)
4148 {
4149 struct e1000_hw *hw = &adapter->hw;
4150
4151 /* hardware has been reset, we need to reload some things */
4152 e1000_configure(adapter);
4153
4154 clear_bit(__E1000_DOWN, &adapter->state);
4155
4156 if (adapter->msix_entries)
4157 e1000_configure_msix(adapter);
4158 e1000_irq_enable(adapter);
4159
4160 netif_start_queue(adapter->netdev);
4161
4162 /* fire a link change interrupt to start the watchdog */
4163 if (adapter->msix_entries)
4164 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
4165 else
4166 ew32(ICS, E1000_ICS_LSC);
4167
4168 return 0;
4169 }
4170
4171 static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4172 {
4173 struct e1000_hw *hw = &adapter->hw;
4174
4175 if (!(adapter->flags2 & FLAG2_DMA_BURST))
4176 return;
4177
4178 /* flush pending descriptor writebacks to memory */
4179 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4180 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4181
4182 /* execute the writes immediately */
4183 e1e_flush();
4184
4185 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
4186 * write is successful
4187 */
4188 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4189 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4190
4191 /* execute the writes immediately */
4192 e1e_flush();
4193 }
4194
4195 static void e1000e_update_stats(struct e1000_adapter *adapter);
4196
4197 /**
4198 * e1000e_down - quiesce the device and optionally reset the hardware
4199 * @adapter: board private structure
4200 * @reset: boolean flag to reset the hardware or not
4201 */
4202 void e1000e_down(struct e1000_adapter *adapter, bool reset)
4203 {
4204 struct net_device *netdev = adapter->netdev;
4205 struct e1000_hw *hw = &adapter->hw;
4206 u32 tctl, rctl;
4207
4208 /* signal that we're down so the interrupt handler does not
4209 * reschedule our watchdog timer
4210 */
4211 set_bit(__E1000_DOWN, &adapter->state);
4212
4213 netif_carrier_off(netdev);
4214
4215 /* disable receives in the hardware */
4216 rctl = er32(RCTL);
4217 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4218 ew32(RCTL, rctl & ~E1000_RCTL_EN);
4219 /* flush and sleep below */
4220
4221 netif_stop_queue(netdev);
4222
4223 /* disable transmits in the hardware */
4224 tctl = er32(TCTL);
4225 tctl &= ~E1000_TCTL_EN;
4226 ew32(TCTL, tctl);
4227
4228 /* flush both disables and wait for them to finish */
4229 e1e_flush();
4230 usleep_range(10000, 20000);
4231
4232 e1000_irq_disable(adapter);
4233
4234 napi_synchronize(&adapter->napi);
4235
4236 del_timer_sync(&adapter->watchdog_timer);
4237 del_timer_sync(&adapter->phy_info_timer);
4238
4239 spin_lock(&adapter->stats64_lock);
4240 e1000e_update_stats(adapter);
4241 spin_unlock(&adapter->stats64_lock);
4242
4243 e1000e_flush_descriptors(adapter);
4244
4245 adapter->link_speed = 0;
4246 adapter->link_duplex = 0;
4247
4248 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4249 if ((hw->mac.type >= e1000_pch2lan) &&
4250 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4251 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4252 e_dbg("failed to disable jumbo frame workaround mode\n");
4253
4254 if (!pci_channel_offline(adapter->pdev)) {
4255 if (reset)
4256 e1000e_reset(adapter);
4257 else if (hw->mac.type == e1000_pch_spt)
4258 e1000_flush_desc_rings(adapter);
4259 }
4260 e1000_clean_tx_ring(adapter->tx_ring);
4261 e1000_clean_rx_ring(adapter->rx_ring);
4262 }
4263
4264 void e1000e_reinit_locked(struct e1000_adapter *adapter)
4265 {
4266 might_sleep();
4267 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4268 usleep_range(1000, 2000);
4269 e1000e_down(adapter, true);
4270 e1000e_up(adapter);
4271 clear_bit(__E1000_RESETTING, &adapter->state);
4272 }
4273
4274 /**
4275 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4276 * @cc: cyclecounter structure
4277 **/
4278 static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
4279 {
4280 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4281 cc);
4282 struct e1000_hw *hw = &adapter->hw;
4283 cycle_t systim, systim_next;
4284 /* SYSTIMH latching upon SYSTIML read does not work well. To fix that
4285 * we don't want to allow overflow of SYSTIML and a change to SYSTIMH
4286 * to occur between reads, so if we read a vale close to overflow, we
4287 * wait for overflow to occur and read both registers when its safe.
4288 */
4289 u32 systim_overflow_latch_fix = 0x3FFFFFFF;
4290
4291 do {
4292 systim = (cycle_t)er32(SYSTIML);
4293 } while (systim > systim_overflow_latch_fix);
4294 systim |= (cycle_t)er32(SYSTIMH) << 32;
4295
4296 if ((hw->mac.type == e1000_82574) || (hw->mac.type == e1000_82583)) {
4297 u64 incvalue, time_delta, rem, temp;
4298 int i;
4299
4300 /* errata for 82574/82583 possible bad bits read from SYSTIMH/L
4301 * check to see that the time is incrementing at a reasonable
4302 * rate and is a multiple of incvalue
4303 */
4304 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4305 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4306 /* latch SYSTIMH on read of SYSTIML */
4307 systim_next = (cycle_t)er32(SYSTIML);
4308 systim_next |= (cycle_t)er32(SYSTIMH) << 32;
4309
4310 time_delta = systim_next - systim;
4311 temp = time_delta;
4312 rem = do_div(temp, incvalue);
4313
4314 systim = systim_next;
4315
4316 if ((time_delta < E1000_82574_SYSTIM_EPSILON) &&
4317 (rem == 0))
4318 break;
4319 }
4320 }
4321 return systim;
4322 }
4323
4324 /**
4325 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4326 * @adapter: board private structure to initialize
4327 *
4328 * e1000_sw_init initializes the Adapter private data structure.
4329 * Fields are initialized based on PCI device information and
4330 * OS network device settings (MTU size).
4331 **/
4332 static int e1000_sw_init(struct e1000_adapter *adapter)
4333 {
4334 struct net_device *netdev = adapter->netdev;
4335
4336 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
4337 adapter->rx_ps_bsize0 = 128;
4338 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4339 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4340 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4341 adapter->rx_ring_count = E1000_DEFAULT_RXD;
4342
4343 spin_lock_init(&adapter->stats64_lock);
4344
4345 e1000e_set_interrupt_capability(adapter);
4346
4347 if (e1000_alloc_queues(adapter))
4348 return -ENOMEM;
4349
4350 /* Setup hardware time stamping cyclecounter */
4351 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4352 adapter->cc.read = e1000e_cyclecounter_read;
4353 adapter->cc.mask = CYCLECOUNTER_MASK(64);
4354 adapter->cc.mult = 1;
4355 /* cc.shift set in e1000e_get_base_tininca() */
4356
4357 spin_lock_init(&adapter->systim_lock);
4358 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4359 }
4360
4361 /* Explicitly disable IRQ since the NIC can be in any state. */
4362 e1000_irq_disable(adapter);
4363
4364 set_bit(__E1000_DOWN, &adapter->state);
4365 return 0;
4366 }
4367
4368 /**
4369 * e1000_intr_msi_test - Interrupt Handler
4370 * @irq: interrupt number
4371 * @data: pointer to a network interface device structure
4372 **/
4373 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
4374 {
4375 struct net_device *netdev = data;
4376 struct e1000_adapter *adapter = netdev_priv(netdev);
4377 struct e1000_hw *hw = &adapter->hw;
4378 u32 icr = er32(ICR);
4379
4380 e_dbg("icr is %08X\n", icr);
4381 if (icr & E1000_ICR_RXSEQ) {
4382 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
4383 /* Force memory writes to complete before acknowledging the
4384 * interrupt is handled.
4385 */
4386 wmb();
4387 }
4388
4389 return IRQ_HANDLED;
4390 }
4391
4392 /**
4393 * e1000_test_msi_interrupt - Returns 0 for successful test
4394 * @adapter: board private struct
4395 *
4396 * code flow taken from tg3.c
4397 **/
4398 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4399 {
4400 struct net_device *netdev = adapter->netdev;
4401 struct e1000_hw *hw = &adapter->hw;
4402 int err;
4403
4404 /* poll_enable hasn't been called yet, so don't need disable */
4405 /* clear any pending events */
4406 er32(ICR);
4407
4408 /* free the real vector and request a test handler */
4409 e1000_free_irq(adapter);
4410 e1000e_reset_interrupt_capability(adapter);
4411
4412 /* Assume that the test fails, if it succeeds then the test
4413 * MSI irq handler will unset this flag
4414 */
4415 adapter->flags |= FLAG_MSI_TEST_FAILED;
4416
4417 err = pci_enable_msi(adapter->pdev);
4418 if (err)
4419 goto msi_test_failed;
4420
4421 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
4422 netdev->name, netdev);
4423 if (err) {
4424 pci_disable_msi(adapter->pdev);
4425 goto msi_test_failed;
4426 }
4427
4428 /* Force memory writes to complete before enabling and firing an
4429 * interrupt.
4430 */
4431 wmb();
4432
4433 e1000_irq_enable(adapter);
4434
4435 /* fire an unusual interrupt on the test handler */
4436 ew32(ICS, E1000_ICS_RXSEQ);
4437 e1e_flush();
4438 msleep(100);
4439
4440 e1000_irq_disable(adapter);
4441
4442 rmb(); /* read flags after interrupt has been fired */
4443
4444 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4445 adapter->int_mode = E1000E_INT_MODE_LEGACY;
4446 e_info("MSI interrupt test failed, using legacy interrupt.\n");
4447 } else {
4448 e_dbg("MSI interrupt test succeeded!\n");
4449 }
4450
4451 free_irq(adapter->pdev->irq, netdev);
4452 pci_disable_msi(adapter->pdev);
4453
4454 msi_test_failed:
4455 e1000e_set_interrupt_capability(adapter);
4456 return e1000_request_irq(adapter);
4457 }
4458
4459 /**
4460 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4461 * @adapter: board private struct
4462 *
4463 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4464 **/
4465 static int e1000_test_msi(struct e1000_adapter *adapter)
4466 {
4467 int err;
4468 u16 pci_cmd;
4469
4470 if (!(adapter->flags & FLAG_MSI_ENABLED))
4471 return 0;
4472
4473 /* disable SERR in case the MSI write causes a master abort */
4474 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4475 if (pci_cmd & PCI_COMMAND_SERR)
4476 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4477 pci_cmd & ~PCI_COMMAND_SERR);
4478
4479 err = e1000_test_msi_interrupt(adapter);
4480
4481 /* re-enable SERR */
4482 if (pci_cmd & PCI_COMMAND_SERR) {
4483 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4484 pci_cmd |= PCI_COMMAND_SERR;
4485 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4486 }
4487
4488 return err;
4489 }
4490
4491 /**
4492 * e1000_open - Called when a network interface is made active
4493 * @netdev: network interface device structure
4494 *
4495 * Returns 0 on success, negative value on failure
4496 *
4497 * The open entry point is called when a network interface is made
4498 * active by the system (IFF_UP). At this point all resources needed
4499 * for transmit and receive operations are allocated, the interrupt
4500 * handler is registered with the OS, the watchdog timer is started,
4501 * and the stack is notified that the interface is ready.
4502 **/
4503 static int e1000_open(struct net_device *netdev)
4504 {
4505 struct e1000_adapter *adapter = netdev_priv(netdev);
4506 struct e1000_hw *hw = &adapter->hw;
4507 struct pci_dev *pdev = adapter->pdev;
4508 int err;
4509
4510 /* disallow open during test */
4511 if (test_bit(__E1000_TESTING, &adapter->state))
4512 return -EBUSY;
4513
4514 pm_runtime_get_sync(&pdev->dev);
4515
4516 netif_carrier_off(netdev);
4517
4518 /* allocate transmit descriptors */
4519 err = e1000e_setup_tx_resources(adapter->tx_ring);
4520 if (err)
4521 goto err_setup_tx;
4522
4523 /* allocate receive descriptors */
4524 err = e1000e_setup_rx_resources(adapter->rx_ring);
4525 if (err)
4526 goto err_setup_rx;
4527
4528 /* If AMT is enabled, let the firmware know that the network
4529 * interface is now open and reset the part to a known state.
4530 */
4531 if (adapter->flags & FLAG_HAS_AMT) {
4532 e1000e_get_hw_control(adapter);
4533 e1000e_reset(adapter);
4534 }
4535
4536 e1000e_power_up_phy(adapter);
4537
4538 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4539 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4540 e1000_update_mng_vlan(adapter);
4541
4542 /* DMA latency requirement to workaround jumbo issue */
4543 pm_qos_add_request(&adapter->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
4544 PM_QOS_DEFAULT_VALUE);
4545
4546 /* before we allocate an interrupt, we must be ready to handle it.
4547 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4548 * as soon as we call pci_request_irq, so we have to setup our
4549 * clean_rx handler before we do so.
4550 */
4551 e1000_configure(adapter);
4552
4553 err = e1000_request_irq(adapter);
4554 if (err)
4555 goto err_req_irq;
4556
4557 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4558 * ignore e1000e MSI messages, which means we need to test our MSI
4559 * interrupt now
4560 */
4561 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
4562 err = e1000_test_msi(adapter);
4563 if (err) {
4564 e_err("Interrupt allocation failed\n");
4565 goto err_req_irq;
4566 }
4567 }
4568
4569 /* From here on the code is the same as e1000e_up() */
4570 clear_bit(__E1000_DOWN, &adapter->state);
4571
4572 napi_enable(&adapter->napi);
4573
4574 e1000_irq_enable(adapter);
4575
4576 adapter->tx_hang_recheck = false;
4577 netif_start_queue(netdev);
4578
4579 hw->mac.get_link_status = true;
4580 pm_runtime_put(&pdev->dev);
4581
4582 /* fire a link status change interrupt to start the watchdog */
4583 if (adapter->msix_entries)
4584 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
4585 else
4586 ew32(ICS, E1000_ICS_LSC);
4587
4588 return 0;
4589
4590 err_req_irq:
4591 pm_qos_remove_request(&adapter->pm_qos_req);
4592 e1000e_release_hw_control(adapter);
4593 e1000_power_down_phy(adapter);
4594 e1000e_free_rx_resources(adapter->rx_ring);
4595 err_setup_rx:
4596 e1000e_free_tx_resources(adapter->tx_ring);
4597 err_setup_tx:
4598 e1000e_reset(adapter);
4599 pm_runtime_put_sync(&pdev->dev);
4600
4601 return err;
4602 }
4603
4604 /**
4605 * e1000_close - Disables a network interface
4606 * @netdev: network interface device structure
4607 *
4608 * Returns 0, this is not allowed to fail
4609 *
4610 * The close entry point is called when an interface is de-activated
4611 * by the OS. The hardware is still under the drivers control, but
4612 * needs to be disabled. A global MAC reset is issued to stop the
4613 * hardware, and all transmit and receive resources are freed.
4614 **/
4615 static int e1000_close(struct net_device *netdev)
4616 {
4617 struct e1000_adapter *adapter = netdev_priv(netdev);
4618 struct pci_dev *pdev = adapter->pdev;
4619 int count = E1000_CHECK_RESET_COUNT;
4620
4621 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4622 usleep_range(10000, 20000);
4623
4624 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
4625
4626 pm_runtime_get_sync(&pdev->dev);
4627
4628 if (!test_bit(__E1000_DOWN, &adapter->state)) {
4629 e1000e_down(adapter, true);
4630 e1000_free_irq(adapter);
4631
4632 /* Link status message must follow this format */
4633 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
4634 }
4635
4636 napi_disable(&adapter->napi);
4637
4638 e1000e_free_tx_resources(adapter->tx_ring);
4639 e1000e_free_rx_resources(adapter->rx_ring);
4640
4641 /* kill manageability vlan ID if supported, but not if a vlan with
4642 * the same ID is registered on the host OS (let 8021q kill it)
4643 */
4644 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4645 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4646 adapter->mng_vlan_id);
4647
4648 /* If AMT is enabled, let the firmware know that the network
4649 * interface is now closed
4650 */
4651 if ((adapter->flags & FLAG_HAS_AMT) &&
4652 !test_bit(__E1000_TESTING, &adapter->state))
4653 e1000e_release_hw_control(adapter);
4654
4655 pm_qos_remove_request(&adapter->pm_qos_req);
4656
4657 pm_runtime_put_sync(&pdev->dev);
4658
4659 return 0;
4660 }
4661
4662 /**
4663 * e1000_set_mac - Change the Ethernet Address of the NIC
4664 * @netdev: network interface device structure
4665 * @p: pointer to an address structure
4666 *
4667 * Returns 0 on success, negative on failure
4668 **/
4669 static int e1000_set_mac(struct net_device *netdev, void *p)
4670 {
4671 struct e1000_adapter *adapter = netdev_priv(netdev);
4672 struct e1000_hw *hw = &adapter->hw;
4673 struct sockaddr *addr = p;
4674
4675 if (!is_valid_ether_addr(addr->sa_data))
4676 return -EADDRNOTAVAIL;
4677
4678 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4679 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4680
4681 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4682
4683 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4684 /* activate the work around */
4685 e1000e_set_laa_state_82571(&adapter->hw, 1);
4686
4687 /* Hold a copy of the LAA in RAR[14] This is done so that
4688 * between the time RAR[0] gets clobbered and the time it
4689 * gets fixed (in e1000_watchdog), the actual LAA is in one
4690 * of the RARs and no incoming packets directed to this port
4691 * are dropped. Eventually the LAA will be in RAR[0] and
4692 * RAR[14]
4693 */
4694 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4695 adapter->hw.mac.rar_entry_count - 1);
4696 }
4697
4698 return 0;
4699 }
4700
4701 /**
4702 * e1000e_update_phy_task - work thread to update phy
4703 * @work: pointer to our work struct
4704 *
4705 * this worker thread exists because we must acquire a
4706 * semaphore to read the phy, which we could msleep while
4707 * waiting for it, and we can't msleep in a timer.
4708 **/
4709 static void e1000e_update_phy_task(struct work_struct *work)
4710 {
4711 struct e1000_adapter *adapter = container_of(work,
4712 struct e1000_adapter,
4713 update_phy_task);
4714 struct e1000_hw *hw = &adapter->hw;
4715
4716 if (test_bit(__E1000_DOWN, &adapter->state))
4717 return;
4718
4719 e1000_get_phy_info(hw);
4720
4721 /* Enable EEE on 82579 after link up */
4722 if (hw->phy.type >= e1000_phy_82579)
4723 e1000_set_eee_pchlan(hw);
4724 }
4725
4726 /**
4727 * e1000_update_phy_info - timre call-back to update PHY info
4728 * @data: pointer to adapter cast into an unsigned long
4729 *
4730 * Need to wait a few seconds after link up to get diagnostic information from
4731 * the phy
4732 **/
4733 static void e1000_update_phy_info(unsigned long data)
4734 {
4735 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
4736
4737 if (test_bit(__E1000_DOWN, &adapter->state))
4738 return;
4739
4740 schedule_work(&adapter->update_phy_task);
4741 }
4742
4743 /**
4744 * e1000e_update_phy_stats - Update the PHY statistics counters
4745 * @adapter: board private structure
4746 *
4747 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4748 **/
4749 static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4750 {
4751 struct e1000_hw *hw = &adapter->hw;
4752 s32 ret_val;
4753 u16 phy_data;
4754
4755 ret_val = hw->phy.ops.acquire(hw);
4756 if (ret_val)
4757 return;
4758
4759 /* A page set is expensive so check if already on desired page.
4760 * If not, set to the page with the PHY status registers.
4761 */
4762 hw->phy.addr = 1;
4763 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4764 &phy_data);
4765 if (ret_val)
4766 goto release;
4767 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4768 ret_val = hw->phy.ops.set_page(hw,
4769 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4770 if (ret_val)
4771 goto release;
4772 }
4773
4774 /* Single Collision Count */
4775 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4776 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4777 if (!ret_val)
4778 adapter->stats.scc += phy_data;
4779
4780 /* Excessive Collision Count */
4781 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4782 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4783 if (!ret_val)
4784 adapter->stats.ecol += phy_data;
4785
4786 /* Multiple Collision Count */
4787 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4788 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4789 if (!ret_val)
4790 adapter->stats.mcc += phy_data;
4791
4792 /* Late Collision Count */
4793 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4794 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4795 if (!ret_val)
4796 adapter->stats.latecol += phy_data;
4797
4798 /* Collision Count - also used for adaptive IFS */
4799 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4800 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4801 if (!ret_val)
4802 hw->mac.collision_delta = phy_data;
4803
4804 /* Defer Count */
4805 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4806 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4807 if (!ret_val)
4808 adapter->stats.dc += phy_data;
4809
4810 /* Transmit with no CRS */
4811 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4812 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4813 if (!ret_val)
4814 adapter->stats.tncrs += phy_data;
4815
4816 release:
4817 hw->phy.ops.release(hw);
4818 }
4819
4820 /**
4821 * e1000e_update_stats - Update the board statistics counters
4822 * @adapter: board private structure
4823 **/
4824 static void e1000e_update_stats(struct e1000_adapter *adapter)
4825 {
4826 struct net_device *netdev = adapter->netdev;
4827 struct e1000_hw *hw = &adapter->hw;
4828 struct pci_dev *pdev = adapter->pdev;
4829
4830 /* Prevent stats update while adapter is being reset, or if the pci
4831 * connection is down.
4832 */
4833 if (adapter->link_speed == 0)
4834 return;
4835 if (pci_channel_offline(pdev))
4836 return;
4837
4838 adapter->stats.crcerrs += er32(CRCERRS);
4839 adapter->stats.gprc += er32(GPRC);
4840 adapter->stats.gorc += er32(GORCL);
4841 er32(GORCH); /* Clear gorc */
4842 adapter->stats.bprc += er32(BPRC);
4843 adapter->stats.mprc += er32(MPRC);
4844 adapter->stats.roc += er32(ROC);
4845
4846 adapter->stats.mpc += er32(MPC);
4847
4848 /* Half-duplex statistics */
4849 if (adapter->link_duplex == HALF_DUPLEX) {
4850 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4851 e1000e_update_phy_stats(adapter);
4852 } else {
4853 adapter->stats.scc += er32(SCC);
4854 adapter->stats.ecol += er32(ECOL);
4855 adapter->stats.mcc += er32(MCC);
4856 adapter->stats.latecol += er32(LATECOL);
4857 adapter->stats.dc += er32(DC);
4858
4859 hw->mac.collision_delta = er32(COLC);
4860
4861 if ((hw->mac.type != e1000_82574) &&
4862 (hw->mac.type != e1000_82583))
4863 adapter->stats.tncrs += er32(TNCRS);
4864 }
4865 adapter->stats.colc += hw->mac.collision_delta;
4866 }
4867
4868 adapter->stats.xonrxc += er32(XONRXC);
4869 adapter->stats.xontxc += er32(XONTXC);
4870 adapter->stats.xoffrxc += er32(XOFFRXC);
4871 adapter->stats.xofftxc += er32(XOFFTXC);
4872 adapter->stats.gptc += er32(GPTC);
4873 adapter->stats.gotc += er32(GOTCL);
4874 er32(GOTCH); /* Clear gotc */
4875 adapter->stats.rnbc += er32(RNBC);
4876 adapter->stats.ruc += er32(RUC);
4877
4878 adapter->stats.mptc += er32(MPTC);
4879 adapter->stats.bptc += er32(BPTC);
4880
4881 /* used for adaptive IFS */
4882
4883 hw->mac.tx_packet_delta = er32(TPT);
4884 adapter->stats.tpt += hw->mac.tx_packet_delta;
4885
4886 adapter->stats.algnerrc += er32(ALGNERRC);
4887 adapter->stats.rxerrc += er32(RXERRC);
4888 adapter->stats.cexterr += er32(CEXTERR);
4889 adapter->stats.tsctc += er32(TSCTC);
4890 adapter->stats.tsctfc += er32(TSCTFC);
4891
4892 /* Fill out the OS statistics structure */
4893 netdev->stats.multicast = adapter->stats.mprc;
4894 netdev->stats.collisions = adapter->stats.colc;
4895
4896 /* Rx Errors */
4897
4898 /* RLEC on some newer hardware can be incorrect so build
4899 * our own version based on RUC and ROC
4900 */
4901 netdev->stats.rx_errors = adapter->stats.rxerrc +
4902 adapter->stats.crcerrs + adapter->stats.algnerrc +
4903 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
4904 netdev->stats.rx_length_errors = adapter->stats.ruc +
4905 adapter->stats.roc;
4906 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4907 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4908 netdev->stats.rx_missed_errors = adapter->stats.mpc;
4909
4910 /* Tx Errors */
4911 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
4912 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4913 netdev->stats.tx_window_errors = adapter->stats.latecol;
4914 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
4915
4916 /* Tx Dropped needs to be maintained elsewhere */
4917
4918 /* Management Stats */
4919 adapter->stats.mgptc += er32(MGTPTC);
4920 adapter->stats.mgprc += er32(MGTPRC);
4921 adapter->stats.mgpdc += er32(MGTPDC);
4922
4923 /* Correctable ECC Errors */
4924 if ((hw->mac.type == e1000_pch_lpt) ||
4925 (hw->mac.type == e1000_pch_spt)) {
4926 u32 pbeccsts = er32(PBECCSTS);
4927
4928 adapter->corr_errors +=
4929 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
4930 adapter->uncorr_errors +=
4931 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
4932 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4933 }
4934 }
4935
4936 /**
4937 * e1000_phy_read_status - Update the PHY register status snapshot
4938 * @adapter: board private structure
4939 **/
4940 static void e1000_phy_read_status(struct e1000_adapter *adapter)
4941 {
4942 struct e1000_hw *hw = &adapter->hw;
4943 struct e1000_phy_regs *phy = &adapter->phy_regs;
4944
4945 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
4946 (er32(STATUS) & E1000_STATUS_LU) &&
4947 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
4948 int ret_val;
4949
4950 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
4951 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
4952 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
4953 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
4954 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
4955 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
4956 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
4957 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
4958 if (ret_val)
4959 e_warn("Error reading PHY register\n");
4960 } else {
4961 /* Do not read PHY registers if link is not up
4962 * Set values to typical power-on defaults
4963 */
4964 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4965 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4966 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4967 BMSR_ERCAP);
4968 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4969 ADVERTISE_ALL | ADVERTISE_CSMA);
4970 phy->lpa = 0;
4971 phy->expansion = EXPANSION_ENABLENPAGE;
4972 phy->ctrl1000 = ADVERTISE_1000FULL;
4973 phy->stat1000 = 0;
4974 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4975 }
4976 }
4977
4978 static void e1000_print_link_info(struct e1000_adapter *adapter)
4979 {
4980 struct e1000_hw *hw = &adapter->hw;
4981 u32 ctrl = er32(CTRL);
4982
4983 /* Link status message must follow this format for user tools */
4984 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4985 adapter->netdev->name, adapter->link_speed,
4986 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4987 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4988 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4989 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
4990 }
4991
4992 static bool e1000e_has_link(struct e1000_adapter *adapter)
4993 {
4994 struct e1000_hw *hw = &adapter->hw;
4995 bool link_active = false;
4996 s32 ret_val = 0;
4997
4998 /* get_link_status is set on LSC (link status) interrupt or
4999 * Rx sequence error interrupt. get_link_status will stay
5000 * false until the check_for_link establishes link
5001 * for copper adapters ONLY
5002 */
5003 switch (hw->phy.media_type) {
5004 case e1000_media_type_copper:
5005 if (hw->mac.get_link_status) {
5006 ret_val = hw->mac.ops.check_for_link(hw);
5007 link_active = !hw->mac.get_link_status;
5008 } else {
5009 link_active = true;
5010 }
5011 break;
5012 case e1000_media_type_fiber:
5013 ret_val = hw->mac.ops.check_for_link(hw);
5014 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5015 break;
5016 case e1000_media_type_internal_serdes:
5017 ret_val = hw->mac.ops.check_for_link(hw);
5018 link_active = adapter->hw.mac.serdes_has_link;
5019 break;
5020 default:
5021 case e1000_media_type_unknown:
5022 break;
5023 }
5024
5025 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
5026 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5027 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5028 e_info("Gigabit has been disabled, downgrading speed\n");
5029 }
5030
5031 return link_active;
5032 }
5033
5034 static void e1000e_enable_receives(struct e1000_adapter *adapter)
5035 {
5036 /* make sure the receive unit is started */
5037 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5038 (adapter->flags & FLAG_RESTART_NOW)) {
5039 struct e1000_hw *hw = &adapter->hw;
5040 u32 rctl = er32(RCTL);
5041
5042 ew32(RCTL, rctl | E1000_RCTL_EN);
5043 adapter->flags &= ~FLAG_RESTART_NOW;
5044 }
5045 }
5046
5047 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5048 {
5049 struct e1000_hw *hw = &adapter->hw;
5050
5051 /* With 82574 controllers, PHY needs to be checked periodically
5052 * for hung state and reset, if two calls return true
5053 */
5054 if (e1000_check_phy_82574(hw))
5055 adapter->phy_hang_count++;
5056 else
5057 adapter->phy_hang_count = 0;
5058
5059 if (adapter->phy_hang_count > 1) {
5060 adapter->phy_hang_count = 0;
5061 e_dbg("PHY appears hung - resetting\n");
5062 schedule_work(&adapter->reset_task);
5063 }
5064 }
5065
5066 /**
5067 * e1000_watchdog - Timer Call-back
5068 * @data: pointer to adapter cast into an unsigned long
5069 **/
5070 static void e1000_watchdog(unsigned long data)
5071 {
5072 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
5073
5074 /* Do the rest outside of interrupt context */
5075 schedule_work(&adapter->watchdog_task);
5076
5077 /* TODO: make this use queue_delayed_work() */
5078 }
5079
5080 static void e1000_watchdog_task(struct work_struct *work)
5081 {
5082 struct e1000_adapter *adapter = container_of(work,
5083 struct e1000_adapter,
5084 watchdog_task);
5085 struct net_device *netdev = adapter->netdev;
5086 struct e1000_mac_info *mac = &adapter->hw.mac;
5087 struct e1000_phy_info *phy = &adapter->hw.phy;
5088 struct e1000_ring *tx_ring = adapter->tx_ring;
5089 struct e1000_hw *hw = &adapter->hw;
5090 u32 link, tctl;
5091
5092 if (test_bit(__E1000_DOWN, &adapter->state))
5093 return;
5094
5095 link = e1000e_has_link(adapter);
5096 if ((netif_carrier_ok(netdev)) && link) {
5097 /* Cancel scheduled suspend requests. */
5098 pm_runtime_resume(netdev->dev.parent);
5099
5100 e1000e_enable_receives(adapter);
5101 goto link_up;
5102 }
5103
5104 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5105 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5106 e1000_update_mng_vlan(adapter);
5107
5108 if (link) {
5109 if (!netif_carrier_ok(netdev)) {
5110 bool txb2b = true;
5111
5112 /* Cancel scheduled suspend requests. */
5113 pm_runtime_resume(netdev->dev.parent);
5114
5115 /* update snapshot of PHY registers on LSC */
5116 e1000_phy_read_status(adapter);
5117 mac->ops.get_link_up_info(&adapter->hw,
5118 &adapter->link_speed,
5119 &adapter->link_duplex);
5120 e1000_print_link_info(adapter);
5121
5122 /* check if SmartSpeed worked */
5123 e1000e_check_downshift(hw);
5124 if (phy->speed_downgraded)
5125 netdev_warn(netdev,
5126 "Link Speed was downgraded by SmartSpeed\n");
5127
5128 /* On supported PHYs, check for duplex mismatch only
5129 * if link has autonegotiated at 10/100 half
5130 */
5131 if ((hw->phy.type == e1000_phy_igp_3 ||
5132 hw->phy.type == e1000_phy_bm) &&
5133 hw->mac.autoneg &&
5134 (adapter->link_speed == SPEED_10 ||
5135 adapter->link_speed == SPEED_100) &&
5136 (adapter->link_duplex == HALF_DUPLEX)) {
5137 u16 autoneg_exp;
5138
5139 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
5140
5141 if (!(autoneg_exp & EXPANSION_NWAY))
5142 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5143 }
5144
5145 /* adjust timeout factor according to speed/duplex */
5146 adapter->tx_timeout_factor = 1;
5147 switch (adapter->link_speed) {
5148 case SPEED_10:
5149 txb2b = false;
5150 adapter->tx_timeout_factor = 16;
5151 break;
5152 case SPEED_100:
5153 txb2b = false;
5154 adapter->tx_timeout_factor = 10;
5155 break;
5156 }
5157
5158 /* workaround: re-program speed mode bit after
5159 * link-up event
5160 */
5161 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5162 !txb2b) {
5163 u32 tarc0;
5164
5165 tarc0 = er32(TARC(0));
5166 tarc0 &= ~SPEED_MODE_BIT;
5167 ew32(TARC(0), tarc0);
5168 }
5169
5170 /* disable TSO for pcie and 10/100 speeds, to avoid
5171 * some hardware issues
5172 */
5173 if (!(adapter->flags & FLAG_TSO_FORCE)) {
5174 switch (adapter->link_speed) {
5175 case SPEED_10:
5176 case SPEED_100:
5177 e_info("10/100 speed: disabling TSO\n");
5178 netdev->features &= ~NETIF_F_TSO;
5179 netdev->features &= ~NETIF_F_TSO6;
5180 break;
5181 case SPEED_1000:
5182 netdev->features |= NETIF_F_TSO;
5183 netdev->features |= NETIF_F_TSO6;
5184 break;
5185 default:
5186 /* oops */
5187 break;
5188 }
5189 }
5190
5191 /* enable transmits in the hardware, need to do this
5192 * after setting TARC(0)
5193 */
5194 tctl = er32(TCTL);
5195 tctl |= E1000_TCTL_EN;
5196 ew32(TCTL, tctl);
5197
5198 /* Perform any post-link-up configuration before
5199 * reporting link up.
5200 */
5201 if (phy->ops.cfg_on_link_up)
5202 phy->ops.cfg_on_link_up(hw);
5203
5204 netif_carrier_on(netdev);
5205
5206 if (!test_bit(__E1000_DOWN, &adapter->state))
5207 mod_timer(&adapter->phy_info_timer,
5208 round_jiffies(jiffies + 2 * HZ));
5209 }
5210 } else {
5211 if (netif_carrier_ok(netdev)) {
5212 adapter->link_speed = 0;
5213 adapter->link_duplex = 0;
5214 /* Link status message must follow this format */
5215 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
5216 netif_carrier_off(netdev);
5217 if (!test_bit(__E1000_DOWN, &adapter->state))
5218 mod_timer(&adapter->phy_info_timer,
5219 round_jiffies(jiffies + 2 * HZ));
5220
5221 /* 8000ES2LAN requires a Rx packet buffer work-around
5222 * on link down event; reset the controller to flush
5223 * the Rx packet buffer.
5224 */
5225 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
5226 adapter->flags |= FLAG_RESTART_NOW;
5227 else
5228 pm_schedule_suspend(netdev->dev.parent,
5229 LINK_TIMEOUT);
5230 }
5231 }
5232
5233 link_up:
5234 spin_lock(&adapter->stats64_lock);
5235 e1000e_update_stats(adapter);
5236
5237 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5238 adapter->tpt_old = adapter->stats.tpt;
5239 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5240 adapter->colc_old = adapter->stats.colc;
5241
5242 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5243 adapter->gorc_old = adapter->stats.gorc;
5244 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5245 adapter->gotc_old = adapter->stats.gotc;
5246 spin_unlock(&adapter->stats64_lock);
5247
5248 /* If the link is lost the controller stops DMA, but
5249 * if there is queued Tx work it cannot be done. So
5250 * reset the controller to flush the Tx packet buffers.
5251 */
5252 if (!netif_carrier_ok(netdev) &&
5253 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5254 adapter->flags |= FLAG_RESTART_NOW;
5255
5256 /* If reset is necessary, do it outside of interrupt context. */
5257 if (adapter->flags & FLAG_RESTART_NOW) {
5258 schedule_work(&adapter->reset_task);
5259 /* return immediately since reset is imminent */
5260 return;
5261 }
5262
5263 e1000e_update_adaptive(&adapter->hw);
5264
5265 /* Simple mode for Interrupt Throttle Rate (ITR) */
5266 if (adapter->itr_setting == 4) {
5267 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5268 * Total asymmetrical Tx or Rx gets ITR=8000;
5269 * everyone else is between 2000-8000.
5270 */
5271 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5272 u32 dif = (adapter->gotc > adapter->gorc ?
5273 adapter->gotc - adapter->gorc :
5274 adapter->gorc - adapter->gotc) / 10000;
5275 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5276
5277 e1000e_write_itr(adapter, itr);
5278 }
5279
5280 /* Cause software interrupt to ensure Rx ring is cleaned */
5281 if (adapter->msix_entries)
5282 ew32(ICS, adapter->rx_ring->ims_val);
5283 else
5284 ew32(ICS, E1000_ICS_RXDMT0);
5285
5286 /* flush pending descriptors to memory before detecting Tx hang */
5287 e1000e_flush_descriptors(adapter);
5288
5289 /* Force detection of hung controller every watchdog period */
5290 adapter->detect_tx_hung = true;
5291
5292 /* With 82571 controllers, LAA may be overwritten due to controller
5293 * reset from the other port. Set the appropriate LAA in RAR[0]
5294 */
5295 if (e1000e_get_laa_state_82571(hw))
5296 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
5297
5298 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5299 e1000e_check_82574_phy_workaround(adapter);
5300
5301 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5302 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5303 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5304 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5305 er32(RXSTMPH);
5306 adapter->rx_hwtstamp_cleared++;
5307 } else {
5308 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5309 }
5310 }
5311
5312 /* Reset the timer */
5313 if (!test_bit(__E1000_DOWN, &adapter->state))
5314 mod_timer(&adapter->watchdog_timer,
5315 round_jiffies(jiffies + 2 * HZ));
5316 }
5317
5318 #define E1000_TX_FLAGS_CSUM 0x00000001
5319 #define E1000_TX_FLAGS_VLAN 0x00000002
5320 #define E1000_TX_FLAGS_TSO 0x00000004
5321 #define E1000_TX_FLAGS_IPV4 0x00000008
5322 #define E1000_TX_FLAGS_NO_FCS 0x00000010
5323 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5324 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5325 #define E1000_TX_FLAGS_VLAN_SHIFT 16
5326
5327 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5328 __be16 protocol)
5329 {
5330 struct e1000_context_desc *context_desc;
5331 struct e1000_buffer *buffer_info;
5332 unsigned int i;
5333 u32 cmd_length = 0;
5334 u16 ipcse = 0, mss;
5335 u8 ipcss, ipcso, tucss, tucso, hdr_len;
5336 int err;
5337
5338 if (!skb_is_gso(skb))
5339 return 0;
5340
5341 err = skb_cow_head(skb, 0);
5342 if (err < 0)
5343 return err;
5344
5345 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5346 mss = skb_shinfo(skb)->gso_size;
5347 if (protocol == htons(ETH_P_IP)) {
5348 struct iphdr *iph = ip_hdr(skb);
5349 iph->tot_len = 0;
5350 iph->check = 0;
5351 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
5352 0, IPPROTO_TCP, 0);
5353 cmd_length = E1000_TXD_CMD_IP;
5354 ipcse = skb_transport_offset(skb) - 1;
5355 } else if (skb_is_gso_v6(skb)) {
5356 ipv6_hdr(skb)->payload_len = 0;
5357 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5358 &ipv6_hdr(skb)->daddr,
5359 0, IPPROTO_TCP, 0);
5360 ipcse = 0;
5361 }
5362 ipcss = skb_network_offset(skb);
5363 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5364 tucss = skb_transport_offset(skb);
5365 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
5366
5367 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5368 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5369
5370 i = tx_ring->next_to_use;
5371 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5372 buffer_info = &tx_ring->buffer_info[i];
5373
5374 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5375 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5376 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5377 context_desc->upper_setup.tcp_fields.tucss = tucss;
5378 context_desc->upper_setup.tcp_fields.tucso = tucso;
5379 context_desc->upper_setup.tcp_fields.tucse = 0;
5380 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5381 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5382 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5383
5384 buffer_info->time_stamp = jiffies;
5385 buffer_info->next_to_watch = i;
5386
5387 i++;
5388 if (i == tx_ring->count)
5389 i = 0;
5390 tx_ring->next_to_use = i;
5391
5392 return 1;
5393 }
5394
5395 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5396 __be16 protocol)
5397 {
5398 struct e1000_adapter *adapter = tx_ring->adapter;
5399 struct e1000_context_desc *context_desc;
5400 struct e1000_buffer *buffer_info;
5401 unsigned int i;
5402 u8 css;
5403 u32 cmd_len = E1000_TXD_CMD_DEXT;
5404
5405 if (skb->ip_summed != CHECKSUM_PARTIAL)
5406 return false;
5407
5408 switch (protocol) {
5409 case cpu_to_be16(ETH_P_IP):
5410 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5411 cmd_len |= E1000_TXD_CMD_TCP;
5412 break;
5413 case cpu_to_be16(ETH_P_IPV6):
5414 /* XXX not handling all IPV6 headers */
5415 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5416 cmd_len |= E1000_TXD_CMD_TCP;
5417 break;
5418 default:
5419 if (unlikely(net_ratelimit()))
5420 e_warn("checksum_partial proto=%x!\n",
5421 be16_to_cpu(protocol));
5422 break;
5423 }
5424
5425 css = skb_checksum_start_offset(skb);
5426
5427 i = tx_ring->next_to_use;
5428 buffer_info = &tx_ring->buffer_info[i];
5429 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5430
5431 context_desc->lower_setup.ip_config = 0;
5432 context_desc->upper_setup.tcp_fields.tucss = css;
5433 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
5434 context_desc->upper_setup.tcp_fields.tucse = 0;
5435 context_desc->tcp_seg_setup.data = 0;
5436 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5437
5438 buffer_info->time_stamp = jiffies;
5439 buffer_info->next_to_watch = i;
5440
5441 i++;
5442 if (i == tx_ring->count)
5443 i = 0;
5444 tx_ring->next_to_use = i;
5445
5446 return true;
5447 }
5448
5449 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5450 unsigned int first, unsigned int max_per_txd,
5451 unsigned int nr_frags)
5452 {
5453 struct e1000_adapter *adapter = tx_ring->adapter;
5454 struct pci_dev *pdev = adapter->pdev;
5455 struct e1000_buffer *buffer_info;
5456 unsigned int len = skb_headlen(skb);
5457 unsigned int offset = 0, size, count = 0, i;
5458 unsigned int f, bytecount, segs;
5459
5460 i = tx_ring->next_to_use;
5461
5462 while (len) {
5463 buffer_info = &tx_ring->buffer_info[i];
5464 size = min(len, max_per_txd);
5465
5466 buffer_info->length = size;
5467 buffer_info->time_stamp = jiffies;
5468 buffer_info->next_to_watch = i;
5469 buffer_info->dma = dma_map_single(&pdev->dev,
5470 skb->data + offset,
5471 size, DMA_TO_DEVICE);
5472 buffer_info->mapped_as_page = false;
5473 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5474 goto dma_error;
5475
5476 len -= size;
5477 offset += size;
5478 count++;
5479
5480 if (len) {
5481 i++;
5482 if (i == tx_ring->count)
5483 i = 0;
5484 }
5485 }
5486
5487 for (f = 0; f < nr_frags; f++) {
5488 const struct skb_frag_struct *frag;
5489
5490 frag = &skb_shinfo(skb)->frags[f];
5491 len = skb_frag_size(frag);
5492 offset = 0;
5493
5494 while (len) {
5495 i++;
5496 if (i == tx_ring->count)
5497 i = 0;
5498
5499 buffer_info = &tx_ring->buffer_info[i];
5500 size = min(len, max_per_txd);
5501
5502 buffer_info->length = size;
5503 buffer_info->time_stamp = jiffies;
5504 buffer_info->next_to_watch = i;
5505 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5506 offset, size,
5507 DMA_TO_DEVICE);
5508 buffer_info->mapped_as_page = true;
5509 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5510 goto dma_error;
5511
5512 len -= size;
5513 offset += size;
5514 count++;
5515 }
5516 }
5517
5518 segs = skb_shinfo(skb)->gso_segs ? : 1;
5519 /* multiply data chunks by size of headers */
5520 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5521
5522 tx_ring->buffer_info[i].skb = skb;
5523 tx_ring->buffer_info[i].segs = segs;
5524 tx_ring->buffer_info[i].bytecount = bytecount;
5525 tx_ring->buffer_info[first].next_to_watch = i;
5526
5527 return count;
5528
5529 dma_error:
5530 dev_err(&pdev->dev, "Tx DMA map failed\n");
5531 buffer_info->dma = 0;
5532 if (count)
5533 count--;
5534
5535 while (count--) {
5536 if (i == 0)
5537 i += tx_ring->count;
5538 i--;
5539 buffer_info = &tx_ring->buffer_info[i];
5540 e1000_put_txbuf(tx_ring, buffer_info);
5541 }
5542
5543 return 0;
5544 }
5545
5546 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
5547 {
5548 struct e1000_adapter *adapter = tx_ring->adapter;
5549 struct e1000_tx_desc *tx_desc = NULL;
5550 struct e1000_buffer *buffer_info;
5551 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5552 unsigned int i;
5553
5554 if (tx_flags & E1000_TX_FLAGS_TSO) {
5555 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5556 E1000_TXD_CMD_TSE;
5557 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5558
5559 if (tx_flags & E1000_TX_FLAGS_IPV4)
5560 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5561 }
5562
5563 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5564 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5565 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5566 }
5567
5568 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5569 txd_lower |= E1000_TXD_CMD_VLE;
5570 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5571 }
5572
5573 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5574 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5575
5576 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5577 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5578 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5579 }
5580
5581 i = tx_ring->next_to_use;
5582
5583 do {
5584 buffer_info = &tx_ring->buffer_info[i];
5585 tx_desc = E1000_TX_DESC(*tx_ring, i);
5586 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5587 tx_desc->lower.data = cpu_to_le32(txd_lower |
5588 buffer_info->length);
5589 tx_desc->upper.data = cpu_to_le32(txd_upper);
5590
5591 i++;
5592 if (i == tx_ring->count)
5593 i = 0;
5594 } while (--count > 0);
5595
5596 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5597
5598 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5599 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5600 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5601
5602 /* Force memory writes to complete before letting h/w
5603 * know there are new descriptors to fetch. (Only
5604 * applicable for weak-ordered memory model archs,
5605 * such as IA-64).
5606 */
5607 wmb();
5608
5609 tx_ring->next_to_use = i;
5610 }
5611
5612 #define MINIMUM_DHCP_PACKET_SIZE 282
5613 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5614 struct sk_buff *skb)
5615 {
5616 struct e1000_hw *hw = &adapter->hw;
5617 u16 length, offset;
5618
5619 if (skb_vlan_tag_present(skb) &&
5620 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5621 (adapter->hw.mng_cookie.status &
5622 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5623 return 0;
5624
5625 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5626 return 0;
5627
5628 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
5629 return 0;
5630
5631 {
5632 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
5633 struct udphdr *udp;
5634
5635 if (ip->protocol != IPPROTO_UDP)
5636 return 0;
5637
5638 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5639 if (ntohs(udp->dest) != 67)
5640 return 0;
5641
5642 offset = (u8 *)udp + 8 - skb->data;
5643 length = skb->len - offset;
5644 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5645 }
5646
5647 return 0;
5648 }
5649
5650 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5651 {
5652 struct e1000_adapter *adapter = tx_ring->adapter;
5653
5654 netif_stop_queue(adapter->netdev);
5655 /* Herbert's original patch had:
5656 * smp_mb__after_netif_stop_queue();
5657 * but since that doesn't exist yet, just open code it.
5658 */
5659 smp_mb();
5660
5661 /* We need to check again in a case another CPU has just
5662 * made room available.
5663 */
5664 if (e1000_desc_unused(tx_ring) < size)
5665 return -EBUSY;
5666
5667 /* A reprieve! */
5668 netif_start_queue(adapter->netdev);
5669 ++adapter->restart_queue;
5670 return 0;
5671 }
5672
5673 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5674 {
5675 BUG_ON(size > tx_ring->count);
5676
5677 if (e1000_desc_unused(tx_ring) >= size)
5678 return 0;
5679 return __e1000_maybe_stop_tx(tx_ring, size);
5680 }
5681
5682 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5683 struct net_device *netdev)
5684 {
5685 struct e1000_adapter *adapter = netdev_priv(netdev);
5686 struct e1000_ring *tx_ring = adapter->tx_ring;
5687 unsigned int first;
5688 unsigned int tx_flags = 0;
5689 unsigned int len = skb_headlen(skb);
5690 unsigned int nr_frags;
5691 unsigned int mss;
5692 int count = 0;
5693 int tso;
5694 unsigned int f;
5695 __be16 protocol = vlan_get_protocol(skb);
5696
5697 if (test_bit(__E1000_DOWN, &adapter->state)) {
5698 dev_kfree_skb_any(skb);
5699 return NETDEV_TX_OK;
5700 }
5701
5702 if (skb->len <= 0) {
5703 dev_kfree_skb_any(skb);
5704 return NETDEV_TX_OK;
5705 }
5706
5707 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5708 * pad skb in order to meet this minimum size requirement
5709 */
5710 if (skb_put_padto(skb, 17))
5711 return NETDEV_TX_OK;
5712
5713 mss = skb_shinfo(skb)->gso_size;
5714 if (mss) {
5715 u8 hdr_len;
5716
5717 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5718 * points to just header, pull a few bytes of payload from
5719 * frags into skb->data
5720 */
5721 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5722 /* we do this workaround for ES2LAN, but it is un-necessary,
5723 * avoiding it could save a lot of cycles
5724 */
5725 if (skb->data_len && (hdr_len == len)) {
5726 unsigned int pull_size;
5727
5728 pull_size = min_t(unsigned int, 4, skb->data_len);
5729 if (!__pskb_pull_tail(skb, pull_size)) {
5730 e_err("__pskb_pull_tail failed.\n");
5731 dev_kfree_skb_any(skb);
5732 return NETDEV_TX_OK;
5733 }
5734 len = skb_headlen(skb);
5735 }
5736 }
5737
5738 /* reserve a descriptor for the offload context */
5739 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5740 count++;
5741 count++;
5742
5743 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
5744
5745 nr_frags = skb_shinfo(skb)->nr_frags;
5746 for (f = 0; f < nr_frags; f++)
5747 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5748 adapter->tx_fifo_limit);
5749
5750 if (adapter->hw.mac.tx_pkt_filtering)
5751 e1000_transfer_dhcp_info(adapter, skb);
5752
5753 /* need: count + 2 desc gap to keep tail from touching
5754 * head, otherwise try next time
5755 */
5756 if (e1000_maybe_stop_tx(tx_ring, count + 2))
5757 return NETDEV_TX_BUSY;
5758
5759 if (skb_vlan_tag_present(skb)) {
5760 tx_flags |= E1000_TX_FLAGS_VLAN;
5761 tx_flags |= (skb_vlan_tag_get(skb) <<
5762 E1000_TX_FLAGS_VLAN_SHIFT);
5763 }
5764
5765 first = tx_ring->next_to_use;
5766
5767 tso = e1000_tso(tx_ring, skb, protocol);
5768 if (tso < 0) {
5769 dev_kfree_skb_any(skb);
5770 return NETDEV_TX_OK;
5771 }
5772
5773 if (tso)
5774 tx_flags |= E1000_TX_FLAGS_TSO;
5775 else if (e1000_tx_csum(tx_ring, skb, protocol))
5776 tx_flags |= E1000_TX_FLAGS_CSUM;
5777
5778 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5779 * 82571 hardware supports TSO capabilities for IPv6 as well...
5780 * no longer assume, we must.
5781 */
5782 if (protocol == htons(ETH_P_IP))
5783 tx_flags |= E1000_TX_FLAGS_IPV4;
5784
5785 if (unlikely(skb->no_fcs))
5786 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5787
5788 /* if count is 0 then mapping error has occurred */
5789 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5790 nr_frags);
5791 if (count) {
5792 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5793 (adapter->flags & FLAG_HAS_HW_TIMESTAMP) &&
5794 !adapter->tx_hwtstamp_skb) {
5795 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5796 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5797 adapter->tx_hwtstamp_skb = skb_get(skb);
5798 adapter->tx_hwtstamp_start = jiffies;
5799 schedule_work(&adapter->tx_hwtstamp_work);
5800 } else {
5801 skb_tx_timestamp(skb);
5802 }
5803
5804 netdev_sent_queue(netdev, skb->len);
5805 e1000_tx_queue(tx_ring, tx_flags, count);
5806 /* Make sure there is space in the ring for the next send. */
5807 e1000_maybe_stop_tx(tx_ring,
5808 (MAX_SKB_FRAGS *
5809 DIV_ROUND_UP(PAGE_SIZE,
5810 adapter->tx_fifo_limit) + 2));
5811
5812 if (!skb->xmit_more ||
5813 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) {
5814 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5815 e1000e_update_tdt_wa(tx_ring,
5816 tx_ring->next_to_use);
5817 else
5818 writel(tx_ring->next_to_use, tx_ring->tail);
5819
5820 /* we need this if more than one processor can write
5821 * to our tail at a time, it synchronizes IO on
5822 *IA64/Altix systems
5823 */
5824 mmiowb();
5825 }
5826 } else {
5827 dev_kfree_skb_any(skb);
5828 tx_ring->buffer_info[first].time_stamp = 0;
5829 tx_ring->next_to_use = first;
5830 }
5831
5832 return NETDEV_TX_OK;
5833 }
5834
5835 /**
5836 * e1000_tx_timeout - Respond to a Tx Hang
5837 * @netdev: network interface device structure
5838 **/
5839 static void e1000_tx_timeout(struct net_device *netdev)
5840 {
5841 struct e1000_adapter *adapter = netdev_priv(netdev);
5842
5843 /* Do the reset outside of interrupt context */
5844 adapter->tx_timeout_count++;
5845 schedule_work(&adapter->reset_task);
5846 }
5847
5848 static void e1000_reset_task(struct work_struct *work)
5849 {
5850 struct e1000_adapter *adapter;
5851 adapter = container_of(work, struct e1000_adapter, reset_task);
5852
5853 /* don't run the task if already down */
5854 if (test_bit(__E1000_DOWN, &adapter->state))
5855 return;
5856
5857 if (!(adapter->flags & FLAG_RESTART_NOW)) {
5858 e1000e_dump(adapter);
5859 e_err("Reset adapter unexpectedly\n");
5860 }
5861 e1000e_reinit_locked(adapter);
5862 }
5863
5864 /**
5865 * e1000_get_stats64 - Get System Network Statistics
5866 * @netdev: network interface device structure
5867 * @stats: rtnl_link_stats64 pointer
5868 *
5869 * Returns the address of the device statistics structure.
5870 **/
5871 struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5872 struct rtnl_link_stats64 *stats)
5873 {
5874 struct e1000_adapter *adapter = netdev_priv(netdev);
5875
5876 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5877 spin_lock(&adapter->stats64_lock);
5878 e1000e_update_stats(adapter);
5879 /* Fill out the OS statistics structure */
5880 stats->rx_bytes = adapter->stats.gorc;
5881 stats->rx_packets = adapter->stats.gprc;
5882 stats->tx_bytes = adapter->stats.gotc;
5883 stats->tx_packets = adapter->stats.gptc;
5884 stats->multicast = adapter->stats.mprc;
5885 stats->collisions = adapter->stats.colc;
5886
5887 /* Rx Errors */
5888
5889 /* RLEC on some newer hardware can be incorrect so build
5890 * our own version based on RUC and ROC
5891 */
5892 stats->rx_errors = adapter->stats.rxerrc +
5893 adapter->stats.crcerrs + adapter->stats.algnerrc +
5894 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5895 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
5896 stats->rx_crc_errors = adapter->stats.crcerrs;
5897 stats->rx_frame_errors = adapter->stats.algnerrc;
5898 stats->rx_missed_errors = adapter->stats.mpc;
5899
5900 /* Tx Errors */
5901 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5902 stats->tx_aborted_errors = adapter->stats.ecol;
5903 stats->tx_window_errors = adapter->stats.latecol;
5904 stats->tx_carrier_errors = adapter->stats.tncrs;
5905
5906 /* Tx Dropped needs to be maintained elsewhere */
5907
5908 spin_unlock(&adapter->stats64_lock);
5909 return stats;
5910 }
5911
5912 /**
5913 * e1000_change_mtu - Change the Maximum Transfer Unit
5914 * @netdev: network interface device structure
5915 * @new_mtu: new value for maximum frame size
5916 *
5917 * Returns 0 on success, negative on failure
5918 **/
5919 static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5920 {
5921 struct e1000_adapter *adapter = netdev_priv(netdev);
5922 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
5923
5924 /* Jumbo frame support */
5925 if ((max_frame > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) &&
5926 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5927 e_err("Jumbo Frames not supported.\n");
5928 return -EINVAL;
5929 }
5930
5931 /* Supported frame sizes */
5932 if ((new_mtu < (VLAN_ETH_ZLEN + ETH_FCS_LEN)) ||
5933 (max_frame > adapter->max_hw_frame_size)) {
5934 e_err("Unsupported MTU setting\n");
5935 return -EINVAL;
5936 }
5937
5938 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5939 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
5940 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5941 (new_mtu > ETH_DATA_LEN)) {
5942 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
5943 return -EINVAL;
5944 }
5945
5946 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
5947 usleep_range(1000, 2000);
5948 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
5949 adapter->max_frame_size = max_frame;
5950 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5951 netdev->mtu = new_mtu;
5952
5953 pm_runtime_get_sync(netdev->dev.parent);
5954
5955 if (netif_running(netdev))
5956 e1000e_down(adapter, true);
5957
5958 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
5959 * means we reserve 2 more, this pushes us to allocate from the next
5960 * larger slab size.
5961 * i.e. RXBUFFER_2048 --> size-4096 slab
5962 * However with the new *_jumbo_rx* routines, jumbo receives will use
5963 * fragmented skbs
5964 */
5965
5966 if (max_frame <= 2048)
5967 adapter->rx_buffer_len = 2048;
5968 else
5969 adapter->rx_buffer_len = 4096;
5970
5971 /* adjust allocation if LPE protects us, and we aren't using SBP */
5972 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
5973 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
5974
5975 if (netif_running(netdev))
5976 e1000e_up(adapter);
5977 else
5978 e1000e_reset(adapter);
5979
5980 pm_runtime_put_sync(netdev->dev.parent);
5981
5982 clear_bit(__E1000_RESETTING, &adapter->state);
5983
5984 return 0;
5985 }
5986
5987 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5988 int cmd)
5989 {
5990 struct e1000_adapter *adapter = netdev_priv(netdev);
5991 struct mii_ioctl_data *data = if_mii(ifr);
5992
5993 if (adapter->hw.phy.media_type != e1000_media_type_copper)
5994 return -EOPNOTSUPP;
5995
5996 switch (cmd) {
5997 case SIOCGMIIPHY:
5998 data->phy_id = adapter->hw.phy.addr;
5999 break;
6000 case SIOCGMIIREG:
6001 e1000_phy_read_status(adapter);
6002
6003 switch (data->reg_num & 0x1F) {
6004 case MII_BMCR:
6005 data->val_out = adapter->phy_regs.bmcr;
6006 break;
6007 case MII_BMSR:
6008 data->val_out = adapter->phy_regs.bmsr;
6009 break;
6010 case MII_PHYSID1:
6011 data->val_out = (adapter->hw.phy.id >> 16);
6012 break;
6013 case MII_PHYSID2:
6014 data->val_out = (adapter->hw.phy.id & 0xFFFF);
6015 break;
6016 case MII_ADVERTISE:
6017 data->val_out = adapter->phy_regs.advertise;
6018 break;
6019 case MII_LPA:
6020 data->val_out = adapter->phy_regs.lpa;
6021 break;
6022 case MII_EXPANSION:
6023 data->val_out = adapter->phy_regs.expansion;
6024 break;
6025 case MII_CTRL1000:
6026 data->val_out = adapter->phy_regs.ctrl1000;
6027 break;
6028 case MII_STAT1000:
6029 data->val_out = adapter->phy_regs.stat1000;
6030 break;
6031 case MII_ESTATUS:
6032 data->val_out = adapter->phy_regs.estatus;
6033 break;
6034 default:
6035 return -EIO;
6036 }
6037 break;
6038 case SIOCSMIIREG:
6039 default:
6040 return -EOPNOTSUPP;
6041 }
6042 return 0;
6043 }
6044
6045 /**
6046 * e1000e_hwtstamp_ioctl - control hardware time stamping
6047 * @netdev: network interface device structure
6048 * @ifreq: interface request
6049 *
6050 * Outgoing time stamping can be enabled and disabled. Play nice and
6051 * disable it when requested, although it shouldn't cause any overhead
6052 * when no packet needs it. At most one packet in the queue may be
6053 * marked for time stamping, otherwise it would be impossible to tell
6054 * for sure to which packet the hardware time stamp belongs.
6055 *
6056 * Incoming time stamping has to be configured via the hardware filters.
6057 * Not all combinations are supported, in particular event type has to be
6058 * specified. Matching the kind of event packet is not supported, with the
6059 * exception of "all V2 events regardless of level 2 or 4".
6060 **/
6061 static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
6062 {
6063 struct e1000_adapter *adapter = netdev_priv(netdev);
6064 struct hwtstamp_config config;
6065 int ret_val;
6066
6067 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6068 return -EFAULT;
6069
6070 ret_val = e1000e_config_hwtstamp(adapter, &config);
6071 if (ret_val)
6072 return ret_val;
6073
6074 switch (config.rx_filter) {
6075 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6076 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6077 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6078 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6079 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6080 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6081 /* With V2 type filters which specify a Sync or Delay Request,
6082 * Path Delay Request/Response messages are also time stamped
6083 * by hardware so notify the caller the requested packets plus
6084 * some others are time stamped.
6085 */
6086 config.rx_filter = HWTSTAMP_FILTER_SOME;
6087 break;
6088 default:
6089 break;
6090 }
6091
6092 return copy_to_user(ifr->ifr_data, &config,
6093 sizeof(config)) ? -EFAULT : 0;
6094 }
6095
6096 static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
6097 {
6098 struct e1000_adapter *adapter = netdev_priv(netdev);
6099
6100 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
6101 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
6102 }
6103
6104 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6105 {
6106 switch (cmd) {
6107 case SIOCGMIIPHY:
6108 case SIOCGMIIREG:
6109 case SIOCSMIIREG:
6110 return e1000_mii_ioctl(netdev, ifr, cmd);
6111 case SIOCSHWTSTAMP:
6112 return e1000e_hwtstamp_set(netdev, ifr);
6113 case SIOCGHWTSTAMP:
6114 return e1000e_hwtstamp_get(netdev, ifr);
6115 default:
6116 return -EOPNOTSUPP;
6117 }
6118 }
6119
6120 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6121 {
6122 struct e1000_hw *hw = &adapter->hw;
6123 u32 i, mac_reg, wuc;
6124 u16 phy_reg, wuc_enable;
6125 int retval;
6126
6127 /* copy MAC RARs to PHY RARs */
6128 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
6129
6130 retval = hw->phy.ops.acquire(hw);
6131 if (retval) {
6132 e_err("Could not acquire PHY\n");
6133 return retval;
6134 }
6135
6136 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6137 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6138 if (retval)
6139 goto release;
6140
6141 /* copy MAC MTA to PHY MTA - only needed for pchlan */
6142 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6143 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
6144 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6145 (u16)(mac_reg & 0xFFFF));
6146 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6147 (u16)((mac_reg >> 16) & 0xFFFF));
6148 }
6149
6150 /* configure PHY Rx Control register */
6151 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
6152 mac_reg = er32(RCTL);
6153 if (mac_reg & E1000_RCTL_UPE)
6154 phy_reg |= BM_RCTL_UPE;
6155 if (mac_reg & E1000_RCTL_MPE)
6156 phy_reg |= BM_RCTL_MPE;
6157 phy_reg &= ~(BM_RCTL_MO_MASK);
6158 if (mac_reg & E1000_RCTL_MO_3)
6159 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
6160 << BM_RCTL_MO_SHIFT);
6161 if (mac_reg & E1000_RCTL_BAM)
6162 phy_reg |= BM_RCTL_BAM;
6163 if (mac_reg & E1000_RCTL_PMCF)
6164 phy_reg |= BM_RCTL_PMCF;
6165 mac_reg = er32(CTRL);
6166 if (mac_reg & E1000_CTRL_RFCE)
6167 phy_reg |= BM_RCTL_RFCE;
6168 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
6169
6170 wuc = E1000_WUC_PME_EN;
6171 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6172 wuc |= E1000_WUC_APME;
6173
6174 /* enable PHY wakeup in MAC register */
6175 ew32(WUFC, wufc);
6176 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6177 E1000_WUC_PME_STATUS | wuc));
6178
6179 /* configure and enable PHY wakeup in PHY registers */
6180 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
6181 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
6182
6183 /* activate PHY wakeup */
6184 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6185 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6186 if (retval)
6187 e_err("Could not set PHY Host Wakeup bit\n");
6188 release:
6189 hw->phy.ops.release(hw);
6190
6191 return retval;
6192 }
6193
6194 static void e1000e_flush_lpic(struct pci_dev *pdev)
6195 {
6196 struct net_device *netdev = pci_get_drvdata(pdev);
6197 struct e1000_adapter *adapter = netdev_priv(netdev);
6198 struct e1000_hw *hw = &adapter->hw;
6199 u32 ret_val;
6200
6201 pm_runtime_get_sync(netdev->dev.parent);
6202
6203 ret_val = hw->phy.ops.acquire(hw);
6204 if (ret_val)
6205 goto fl_out;
6206
6207 pr_info("EEE TX LPI TIMER: %08X\n",
6208 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6209
6210 hw->phy.ops.release(hw);
6211
6212 fl_out:
6213 pm_runtime_put_sync(netdev->dev.parent);
6214 }
6215
6216 static int e1000e_pm_freeze(struct device *dev)
6217 {
6218 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6219 struct e1000_adapter *adapter = netdev_priv(netdev);
6220
6221 netif_device_detach(netdev);
6222
6223 if (netif_running(netdev)) {
6224 int count = E1000_CHECK_RESET_COUNT;
6225
6226 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6227 usleep_range(10000, 20000);
6228
6229 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6230
6231 /* Quiesce the device without resetting the hardware */
6232 e1000e_down(adapter, false);
6233 e1000_free_irq(adapter);
6234 }
6235 e1000e_reset_interrupt_capability(adapter);
6236
6237 /* Allow time for pending master requests to run */
6238 e1000e_disable_pcie_master(&adapter->hw);
6239
6240 return 0;
6241 }
6242
6243 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6244 {
6245 struct net_device *netdev = pci_get_drvdata(pdev);
6246 struct e1000_adapter *adapter = netdev_priv(netdev);
6247 struct e1000_hw *hw = &adapter->hw;
6248 u32 ctrl, ctrl_ext, rctl, status;
6249 /* Runtime suspend should only enable wakeup for link changes */
6250 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
6251 int retval = 0;
6252
6253 status = er32(STATUS);
6254 if (status & E1000_STATUS_LU)
6255 wufc &= ~E1000_WUFC_LNKC;
6256
6257 if (wufc) {
6258 e1000_setup_rctl(adapter);
6259 e1000e_set_rx_mode(netdev);
6260
6261 /* turn on all-multi mode if wake on multicast is enabled */
6262 if (wufc & E1000_WUFC_MC) {
6263 rctl = er32(RCTL);
6264 rctl |= E1000_RCTL_MPE;
6265 ew32(RCTL, rctl);
6266 }
6267
6268 ctrl = er32(CTRL);
6269 ctrl |= E1000_CTRL_ADVD3WUC;
6270 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6271 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
6272 ew32(CTRL, ctrl);
6273
6274 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6275 adapter->hw.phy.media_type ==
6276 e1000_media_type_internal_serdes) {
6277 /* keep the laser running in D3 */
6278 ctrl_ext = er32(CTRL_EXT);
6279 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
6280 ew32(CTRL_EXT, ctrl_ext);
6281 }
6282
6283 if (!runtime)
6284 e1000e_power_up_phy(adapter);
6285
6286 if (adapter->flags & FLAG_IS_ICH)
6287 e1000_suspend_workarounds_ich8lan(&adapter->hw);
6288
6289 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6290 /* enable wakeup by the PHY */
6291 retval = e1000_init_phy_wakeup(adapter, wufc);
6292 if (retval)
6293 return retval;
6294 } else {
6295 /* enable wakeup by the MAC */
6296 ew32(WUFC, wufc);
6297 ew32(WUC, E1000_WUC_PME_EN);
6298 }
6299 } else {
6300 ew32(WUC, 0);
6301 ew32(WUFC, 0);
6302
6303 e1000_power_down_phy(adapter);
6304 }
6305
6306 if (adapter->hw.phy.type == e1000_phy_igp_3) {
6307 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
6308 } else if ((hw->mac.type == e1000_pch_lpt) ||
6309 (hw->mac.type == e1000_pch_spt)) {
6310 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
6311 /* ULP does not support wake from unicast, multicast
6312 * or broadcast.
6313 */
6314 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6315
6316 if (retval)
6317 return retval;
6318 }
6319
6320 /* Ensure that the appropriate bits are set in LPI_CTRL
6321 * for EEE in Sx
6322 */
6323 if ((hw->phy.type >= e1000_phy_i217) &&
6324 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6325 u16 lpi_ctrl = 0;
6326
6327 retval = hw->phy.ops.acquire(hw);
6328 if (!retval) {
6329 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6330 &lpi_ctrl);
6331 if (!retval) {
6332 if (adapter->eee_advert &
6333 hw->dev_spec.ich8lan.eee_lp_ability &
6334 I82579_EEE_100_SUPPORTED)
6335 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6336 if (adapter->eee_advert &
6337 hw->dev_spec.ich8lan.eee_lp_ability &
6338 I82579_EEE_1000_SUPPORTED)
6339 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6340
6341 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6342 lpi_ctrl);
6343 }
6344 }
6345 hw->phy.ops.release(hw);
6346 }
6347
6348 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6349 * would have already happened in close and is redundant.
6350 */
6351 e1000e_release_hw_control(adapter);
6352
6353 pci_clear_master(pdev);
6354
6355 /* The pci-e switch on some quad port adapters will report a
6356 * correctable error when the MAC transitions from D0 to D3. To
6357 * prevent this we need to mask off the correctable errors on the
6358 * downstream port of the pci-e switch.
6359 *
6360 * We don't have the associated upstream bridge while assigning
6361 * the PCI device into guest. For example, the KVM on power is
6362 * one of the cases.
6363 */
6364 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6365 struct pci_dev *us_dev = pdev->bus->self;
6366 u16 devctl;
6367
6368 if (!us_dev)
6369 return 0;
6370
6371 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6372 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6373 (devctl & ~PCI_EXP_DEVCTL_CERE));
6374
6375 pci_save_state(pdev);
6376 pci_prepare_to_sleep(pdev);
6377
6378 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
6379 }
6380
6381 return 0;
6382 }
6383
6384 /**
6385 * __e1000e_disable_aspm - Disable ASPM states
6386 * @pdev: pointer to PCI device struct
6387 * @state: bit-mask of ASPM states to disable
6388 * @locked: indication if this context holds pci_bus_sem locked.
6389 *
6390 * Some devices *must* have certain ASPM states disabled per hardware errata.
6391 **/
6392 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6393 {
6394 struct pci_dev *parent = pdev->bus->self;
6395 u16 aspm_dis_mask = 0;
6396 u16 pdev_aspmc, parent_aspmc;
6397
6398 switch (state) {
6399 case PCIE_LINK_STATE_L0S:
6400 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6401 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6402 /* fall-through - can't have L1 without L0s */
6403 case PCIE_LINK_STATE_L1:
6404 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6405 break;
6406 default:
6407 return;
6408 }
6409
6410 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6411 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6412
6413 if (parent) {
6414 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6415 &parent_aspmc);
6416 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6417 }
6418
6419 /* Nothing to do if the ASPM states to be disabled already are */
6420 if (!(pdev_aspmc & aspm_dis_mask) &&
6421 (!parent || !(parent_aspmc & aspm_dis_mask)))
6422 return;
6423
6424 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6425 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6426 "L0s" : "",
6427 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6428 "L1" : "");
6429
6430 #ifdef CONFIG_PCIEASPM
6431 if (locked)
6432 pci_disable_link_state_locked(pdev, state);
6433 else
6434 pci_disable_link_state(pdev, state);
6435
6436 /* Double-check ASPM control. If not disabled by the above, the
6437 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6438 * not enabled); override by writing PCI config space directly.
6439 */
6440 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6441 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6442
6443 if (!(aspm_dis_mask & pdev_aspmc))
6444 return;
6445 #endif
6446
6447 /* Both device and parent should have the same ASPM setting.
6448 * Disable ASPM in downstream component first and then upstream.
6449 */
6450 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6451
6452 if (parent)
6453 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6454 aspm_dis_mask);
6455 }
6456
6457 /**
6458 * e1000e_disable_aspm - Disable ASPM states.
6459 * @pdev: pointer to PCI device struct
6460 * @state: bit-mask of ASPM states to disable
6461 *
6462 * This function acquires the pci_bus_sem!
6463 * Some devices *must* have certain ASPM states disabled per hardware errata.
6464 **/
6465 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6466 {
6467 __e1000e_disable_aspm(pdev, state, 0);
6468 }
6469
6470 /**
6471 * e1000e_disable_aspm_locked Disable ASPM states.
6472 * @pdev: pointer to PCI device struct
6473 * @state: bit-mask of ASPM states to disable
6474 *
6475 * This function must be called with pci_bus_sem acquired!
6476 * Some devices *must* have certain ASPM states disabled per hardware errata.
6477 **/
6478 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6479 {
6480 __e1000e_disable_aspm(pdev, state, 1);
6481 }
6482
6483 #ifdef CONFIG_PM
6484 static int __e1000_resume(struct pci_dev *pdev)
6485 {
6486 struct net_device *netdev = pci_get_drvdata(pdev);
6487 struct e1000_adapter *adapter = netdev_priv(netdev);
6488 struct e1000_hw *hw = &adapter->hw;
6489 u16 aspm_disable_flag = 0;
6490
6491 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6492 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6493 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6494 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6495 if (aspm_disable_flag)
6496 e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
6497
6498 pci_set_master(pdev);
6499
6500 if (hw->mac.type >= e1000_pch2lan)
6501 e1000_resume_workarounds_pchlan(&adapter->hw);
6502
6503 e1000e_power_up_phy(adapter);
6504
6505 /* report the system wakeup cause from S3/S4 */
6506 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6507 u16 phy_data;
6508
6509 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6510 if (phy_data) {
6511 e_info("PHY Wakeup cause - %s\n",
6512 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6513 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6514 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6515 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6516 phy_data & E1000_WUS_LNKC ?
6517 "Link Status Change" : "other");
6518 }
6519 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6520 } else {
6521 u32 wus = er32(WUS);
6522
6523 if (wus) {
6524 e_info("MAC Wakeup cause - %s\n",
6525 wus & E1000_WUS_EX ? "Unicast Packet" :
6526 wus & E1000_WUS_MC ? "Multicast Packet" :
6527 wus & E1000_WUS_BC ? "Broadcast Packet" :
6528 wus & E1000_WUS_MAG ? "Magic Packet" :
6529 wus & E1000_WUS_LNKC ? "Link Status Change" :
6530 "other");
6531 }
6532 ew32(WUS, ~0);
6533 }
6534
6535 e1000e_reset(adapter);
6536
6537 e1000_init_manageability_pt(adapter);
6538
6539 /* If the controller has AMT, do not set DRV_LOAD until the interface
6540 * is up. For all other cases, let the f/w know that the h/w is now
6541 * under the control of the driver.
6542 */
6543 if (!(adapter->flags & FLAG_HAS_AMT))
6544 e1000e_get_hw_control(adapter);
6545
6546 return 0;
6547 }
6548
6549 #ifdef CONFIG_PM_SLEEP
6550 static int e1000e_pm_thaw(struct device *dev)
6551 {
6552 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6553 struct e1000_adapter *adapter = netdev_priv(netdev);
6554
6555 e1000e_set_interrupt_capability(adapter);
6556 if (netif_running(netdev)) {
6557 u32 err = e1000_request_irq(adapter);
6558
6559 if (err)
6560 return err;
6561
6562 e1000e_up(adapter);
6563 }
6564
6565 netif_device_attach(netdev);
6566
6567 return 0;
6568 }
6569
6570 static int e1000e_pm_suspend(struct device *dev)
6571 {
6572 struct pci_dev *pdev = to_pci_dev(dev);
6573
6574 e1000e_flush_lpic(pdev);
6575
6576 e1000e_pm_freeze(dev);
6577
6578 return __e1000_shutdown(pdev, false);
6579 }
6580
6581 static int e1000e_pm_resume(struct device *dev)
6582 {
6583 struct pci_dev *pdev = to_pci_dev(dev);
6584 int rc;
6585
6586 rc = __e1000_resume(pdev);
6587 if (rc)
6588 return rc;
6589
6590 return e1000e_pm_thaw(dev);
6591 }
6592 #endif /* CONFIG_PM_SLEEP */
6593
6594 static int e1000e_pm_runtime_idle(struct device *dev)
6595 {
6596 struct pci_dev *pdev = to_pci_dev(dev);
6597 struct net_device *netdev = pci_get_drvdata(pdev);
6598 struct e1000_adapter *adapter = netdev_priv(netdev);
6599 u16 eee_lp;
6600
6601 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
6602
6603 if (!e1000e_has_link(adapter)) {
6604 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
6605 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
6606 }
6607
6608 return -EBUSY;
6609 }
6610
6611 static int e1000e_pm_runtime_resume(struct device *dev)
6612 {
6613 struct pci_dev *pdev = to_pci_dev(dev);
6614 struct net_device *netdev = pci_get_drvdata(pdev);
6615 struct e1000_adapter *adapter = netdev_priv(netdev);
6616 int rc;
6617
6618 rc = __e1000_resume(pdev);
6619 if (rc)
6620 return rc;
6621
6622 if (netdev->flags & IFF_UP)
6623 rc = e1000e_up(adapter);
6624
6625 return rc;
6626 }
6627
6628 static int e1000e_pm_runtime_suspend(struct device *dev)
6629 {
6630 struct pci_dev *pdev = to_pci_dev(dev);
6631 struct net_device *netdev = pci_get_drvdata(pdev);
6632 struct e1000_adapter *adapter = netdev_priv(netdev);
6633
6634 if (netdev->flags & IFF_UP) {
6635 int count = E1000_CHECK_RESET_COUNT;
6636
6637 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6638 usleep_range(10000, 20000);
6639
6640 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6641
6642 /* Down the device without resetting the hardware */
6643 e1000e_down(adapter, false);
6644 }
6645
6646 if (__e1000_shutdown(pdev, true)) {
6647 e1000e_pm_runtime_resume(dev);
6648 return -EBUSY;
6649 }
6650
6651 return 0;
6652 }
6653 #endif /* CONFIG_PM */
6654
6655 static void e1000_shutdown(struct pci_dev *pdev)
6656 {
6657 e1000e_flush_lpic(pdev);
6658
6659 e1000e_pm_freeze(&pdev->dev);
6660
6661 __e1000_shutdown(pdev, false);
6662 }
6663
6664 #ifdef CONFIG_NET_POLL_CONTROLLER
6665
6666 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
6667 {
6668 struct net_device *netdev = data;
6669 struct e1000_adapter *adapter = netdev_priv(netdev);
6670
6671 if (adapter->msix_entries) {
6672 int vector, msix_irq;
6673
6674 vector = 0;
6675 msix_irq = adapter->msix_entries[vector].vector;
6676 disable_irq(msix_irq);
6677 e1000_intr_msix_rx(msix_irq, netdev);
6678 enable_irq(msix_irq);
6679
6680 vector++;
6681 msix_irq = adapter->msix_entries[vector].vector;
6682 disable_irq(msix_irq);
6683 e1000_intr_msix_tx(msix_irq, netdev);
6684 enable_irq(msix_irq);
6685
6686 vector++;
6687 msix_irq = adapter->msix_entries[vector].vector;
6688 disable_irq(msix_irq);
6689 e1000_msix_other(msix_irq, netdev);
6690 enable_irq(msix_irq);
6691 }
6692
6693 return IRQ_HANDLED;
6694 }
6695
6696 /**
6697 * e1000_netpoll
6698 * @netdev: network interface device structure
6699 *
6700 * Polling 'interrupt' - used by things like netconsole to send skbs
6701 * without having to re-enable interrupts. It's not called while
6702 * the interrupt routine is executing.
6703 */
6704 static void e1000_netpoll(struct net_device *netdev)
6705 {
6706 struct e1000_adapter *adapter = netdev_priv(netdev);
6707
6708 switch (adapter->int_mode) {
6709 case E1000E_INT_MODE_MSIX:
6710 e1000_intr_msix(adapter->pdev->irq, netdev);
6711 break;
6712 case E1000E_INT_MODE_MSI:
6713 disable_irq(adapter->pdev->irq);
6714 e1000_intr_msi(adapter->pdev->irq, netdev);
6715 enable_irq(adapter->pdev->irq);
6716 break;
6717 default: /* E1000E_INT_MODE_LEGACY */
6718 disable_irq(adapter->pdev->irq);
6719 e1000_intr(adapter->pdev->irq, netdev);
6720 enable_irq(adapter->pdev->irq);
6721 break;
6722 }
6723 }
6724 #endif
6725
6726 /**
6727 * e1000_io_error_detected - called when PCI error is detected
6728 * @pdev: Pointer to PCI device
6729 * @state: The current pci connection state
6730 *
6731 * This function is called after a PCI bus error affecting
6732 * this device has been detected.
6733 */
6734 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6735 pci_channel_state_t state)
6736 {
6737 struct net_device *netdev = pci_get_drvdata(pdev);
6738 struct e1000_adapter *adapter = netdev_priv(netdev);
6739
6740 netif_device_detach(netdev);
6741
6742 if (state == pci_channel_io_perm_failure)
6743 return PCI_ERS_RESULT_DISCONNECT;
6744
6745 if (netif_running(netdev))
6746 e1000e_down(adapter, true);
6747 pci_disable_device(pdev);
6748
6749 /* Request a slot slot reset. */
6750 return PCI_ERS_RESULT_NEED_RESET;
6751 }
6752
6753 /**
6754 * e1000_io_slot_reset - called after the pci bus has been reset.
6755 * @pdev: Pointer to PCI device
6756 *
6757 * Restart the card from scratch, as if from a cold-boot. Implementation
6758 * resembles the first-half of the e1000e_pm_resume routine.
6759 */
6760 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6761 {
6762 struct net_device *netdev = pci_get_drvdata(pdev);
6763 struct e1000_adapter *adapter = netdev_priv(netdev);
6764 struct e1000_hw *hw = &adapter->hw;
6765 u16 aspm_disable_flag = 0;
6766 int err;
6767 pci_ers_result_t result;
6768
6769 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6770 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6771 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6772 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6773 if (aspm_disable_flag)
6774 e1000e_disable_aspm(pdev, aspm_disable_flag);
6775
6776 err = pci_enable_device_mem(pdev);
6777 if (err) {
6778 dev_err(&pdev->dev,
6779 "Cannot re-enable PCI device after reset.\n");
6780 result = PCI_ERS_RESULT_DISCONNECT;
6781 } else {
6782 pdev->state_saved = true;
6783 pci_restore_state(pdev);
6784 pci_set_master(pdev);
6785
6786 pci_enable_wake(pdev, PCI_D3hot, 0);
6787 pci_enable_wake(pdev, PCI_D3cold, 0);
6788
6789 e1000e_reset(adapter);
6790 ew32(WUS, ~0);
6791 result = PCI_ERS_RESULT_RECOVERED;
6792 }
6793
6794 pci_cleanup_aer_uncorrect_error_status(pdev);
6795
6796 return result;
6797 }
6798
6799 /**
6800 * e1000_io_resume - called when traffic can start flowing again.
6801 * @pdev: Pointer to PCI device
6802 *
6803 * This callback is called when the error recovery driver tells us that
6804 * its OK to resume normal operation. Implementation resembles the
6805 * second-half of the e1000e_pm_resume routine.
6806 */
6807 static void e1000_io_resume(struct pci_dev *pdev)
6808 {
6809 struct net_device *netdev = pci_get_drvdata(pdev);
6810 struct e1000_adapter *adapter = netdev_priv(netdev);
6811
6812 e1000_init_manageability_pt(adapter);
6813
6814 if (netif_running(netdev)) {
6815 if (e1000e_up(adapter)) {
6816 dev_err(&pdev->dev,
6817 "can't bring device back up after reset\n");
6818 return;
6819 }
6820 }
6821
6822 netif_device_attach(netdev);
6823
6824 /* If the controller has AMT, do not set DRV_LOAD until the interface
6825 * is up. For all other cases, let the f/w know that the h/w is now
6826 * under the control of the driver.
6827 */
6828 if (!(adapter->flags & FLAG_HAS_AMT))
6829 e1000e_get_hw_control(adapter);
6830 }
6831
6832 static void e1000_print_device_info(struct e1000_adapter *adapter)
6833 {
6834 struct e1000_hw *hw = &adapter->hw;
6835 struct net_device *netdev = adapter->netdev;
6836 u32 ret_val;
6837 u8 pba_str[E1000_PBANUM_LENGTH];
6838
6839 /* print bus type/speed/width info */
6840 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
6841 /* bus width */
6842 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
6843 "Width x1"),
6844 /* MAC address */
6845 netdev->dev_addr);
6846 e_info("Intel(R) PRO/%s Network Connection\n",
6847 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
6848 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6849 E1000_PBANUM_LENGTH);
6850 if (ret_val)
6851 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
6852 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6853 hw->mac.type, hw->phy.type, pba_str);
6854 }
6855
6856 static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6857 {
6858 struct e1000_hw *hw = &adapter->hw;
6859 int ret_val;
6860 u16 buf = 0;
6861
6862 if (hw->mac.type != e1000_82573)
6863 return;
6864
6865 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
6866 le16_to_cpus(&buf);
6867 if (!ret_val && (!(buf & (1 << 0)))) {
6868 /* Deep Smart Power Down (DSPD) */
6869 dev_warn(&adapter->pdev->dev,
6870 "Warning: detected DSPD enabled in EEPROM\n");
6871 }
6872 }
6873
6874 static netdev_features_t e1000_fix_features(struct net_device *netdev,
6875 netdev_features_t features)
6876 {
6877 struct e1000_adapter *adapter = netdev_priv(netdev);
6878 struct e1000_hw *hw = &adapter->hw;
6879
6880 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6881 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
6882 features &= ~NETIF_F_RXFCS;
6883
6884 return features;
6885 }
6886
6887 static int e1000_set_features(struct net_device *netdev,
6888 netdev_features_t features)
6889 {
6890 struct e1000_adapter *adapter = netdev_priv(netdev);
6891 netdev_features_t changed = features ^ netdev->features;
6892
6893 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6894 adapter->flags |= FLAG_TSO_FORCE;
6895
6896 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
6897 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6898 NETIF_F_RXALL)))
6899 return 0;
6900
6901 if (changed & NETIF_F_RXFCS) {
6902 if (features & NETIF_F_RXFCS) {
6903 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6904 } else {
6905 /* We need to take it back to defaults, which might mean
6906 * stripping is still disabled at the adapter level.
6907 */
6908 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6909 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6910 else
6911 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6912 }
6913 }
6914
6915 netdev->features = features;
6916
6917 if (netif_running(netdev))
6918 e1000e_reinit_locked(adapter);
6919 else
6920 e1000e_reset(adapter);
6921
6922 return 0;
6923 }
6924
6925 static const struct net_device_ops e1000e_netdev_ops = {
6926 .ndo_open = e1000_open,
6927 .ndo_stop = e1000_close,
6928 .ndo_start_xmit = e1000_xmit_frame,
6929 .ndo_get_stats64 = e1000e_get_stats64,
6930 .ndo_set_rx_mode = e1000e_set_rx_mode,
6931 .ndo_set_mac_address = e1000_set_mac,
6932 .ndo_change_mtu = e1000_change_mtu,
6933 .ndo_do_ioctl = e1000_ioctl,
6934 .ndo_tx_timeout = e1000_tx_timeout,
6935 .ndo_validate_addr = eth_validate_addr,
6936
6937 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6938 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6939 #ifdef CONFIG_NET_POLL_CONTROLLER
6940 .ndo_poll_controller = e1000_netpoll,
6941 #endif
6942 .ndo_set_features = e1000_set_features,
6943 .ndo_fix_features = e1000_fix_features,
6944 };
6945
6946 /**
6947 * e1000_probe - Device Initialization Routine
6948 * @pdev: PCI device information struct
6949 * @ent: entry in e1000_pci_tbl
6950 *
6951 * Returns 0 on success, negative on failure
6952 *
6953 * e1000_probe initializes an adapter identified by a pci_dev structure.
6954 * The OS initialization, configuring of the adapter private structure,
6955 * and a hardware reset occur.
6956 **/
6957 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
6958 {
6959 struct net_device *netdev;
6960 struct e1000_adapter *adapter;
6961 struct e1000_hw *hw;
6962 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
6963 resource_size_t mmio_start, mmio_len;
6964 resource_size_t flash_start, flash_len;
6965 static int cards_found;
6966 u16 aspm_disable_flag = 0;
6967 int bars, i, err, pci_using_dac;
6968 u16 eeprom_data = 0;
6969 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6970 s32 rval = 0;
6971
6972 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6973 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6974 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
6975 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6976 if (aspm_disable_flag)
6977 e1000e_disable_aspm(pdev, aspm_disable_flag);
6978
6979 err = pci_enable_device_mem(pdev);
6980 if (err)
6981 return err;
6982
6983 pci_using_dac = 0;
6984 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6985 if (!err) {
6986 pci_using_dac = 1;
6987 } else {
6988 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
6989 if (err) {
6990 dev_err(&pdev->dev,
6991 "No usable DMA configuration, aborting\n");
6992 goto err_dma;
6993 }
6994 }
6995
6996 bars = pci_select_bars(pdev, IORESOURCE_MEM);
6997 err = pci_request_selected_regions_exclusive(pdev, bars,
6998 e1000e_driver_name);
6999 if (err)
7000 goto err_pci_reg;
7001
7002 /* AER (Advanced Error Reporting) hooks */
7003 pci_enable_pcie_error_reporting(pdev);
7004
7005 pci_set_master(pdev);
7006 /* PCI config space info */
7007 err = pci_save_state(pdev);
7008 if (err)
7009 goto err_alloc_etherdev;
7010
7011 err = -ENOMEM;
7012 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7013 if (!netdev)
7014 goto err_alloc_etherdev;
7015
7016 SET_NETDEV_DEV(netdev, &pdev->dev);
7017
7018 netdev->irq = pdev->irq;
7019
7020 pci_set_drvdata(pdev, netdev);
7021 adapter = netdev_priv(netdev);
7022 hw = &adapter->hw;
7023 adapter->netdev = netdev;
7024 adapter->pdev = pdev;
7025 adapter->ei = ei;
7026 adapter->pba = ei->pba;
7027 adapter->flags = ei->flags;
7028 adapter->flags2 = ei->flags2;
7029 adapter->hw.adapter = adapter;
7030 adapter->hw.mac.type = ei->mac;
7031 adapter->max_hw_frame_size = ei->max_hw_frame_size;
7032 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7033
7034 mmio_start = pci_resource_start(pdev, 0);
7035 mmio_len = pci_resource_len(pdev, 0);
7036
7037 err = -EIO;
7038 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
7039 if (!adapter->hw.hw_addr)
7040 goto err_ioremap;
7041
7042 if ((adapter->flags & FLAG_HAS_FLASH) &&
7043 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7044 (hw->mac.type < e1000_pch_spt)) {
7045 flash_start = pci_resource_start(pdev, 1);
7046 flash_len = pci_resource_len(pdev, 1);
7047 adapter->hw.flash_address = ioremap(flash_start, flash_len);
7048 if (!adapter->hw.flash_address)
7049 goto err_flashmap;
7050 }
7051
7052 /* Set default EEE advertisement */
7053 if (adapter->flags2 & FLAG2_HAS_EEE)
7054 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7055
7056 /* construct the net_device struct */
7057 netdev->netdev_ops = &e1000e_netdev_ops;
7058 e1000e_set_ethtool_ops(netdev);
7059 netdev->watchdog_timeo = 5 * HZ;
7060 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
7061 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
7062
7063 netdev->mem_start = mmio_start;
7064 netdev->mem_end = mmio_start + mmio_len;
7065
7066 adapter->bd_number = cards_found++;
7067
7068 e1000e_check_options(adapter);
7069
7070 /* setup adapter struct */
7071 err = e1000_sw_init(adapter);
7072 if (err)
7073 goto err_sw_init;
7074
7075 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7076 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7077 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7078
7079 err = ei->get_variants(adapter);
7080 if (err)
7081 goto err_hw_init;
7082
7083 if ((adapter->flags & FLAG_IS_ICH) &&
7084 (adapter->flags & FLAG_READ_ONLY_NVM) &&
7085 (hw->mac.type < e1000_pch_spt))
7086 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
7087
7088 hw->mac.ops.get_bus_info(&adapter->hw);
7089
7090 adapter->hw.phy.autoneg_wait_to_complete = 0;
7091
7092 /* Copper options */
7093 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
7094 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7095 adapter->hw.phy.disable_polarity_correction = 0;
7096 adapter->hw.phy.ms_type = e1000_ms_hw_default;
7097 }
7098
7099 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
7100 dev_info(&pdev->dev,
7101 "PHY reset is blocked due to SOL/IDER session.\n");
7102
7103 /* Set initial default active device features */
7104 netdev->features = (NETIF_F_SG |
7105 NETIF_F_HW_VLAN_CTAG_RX |
7106 NETIF_F_HW_VLAN_CTAG_TX |
7107 NETIF_F_TSO |
7108 NETIF_F_TSO6 |
7109 NETIF_F_RXHASH |
7110 NETIF_F_RXCSUM |
7111 NETIF_F_HW_CSUM);
7112
7113 /* Set user-changeable features (subset of all device features) */
7114 netdev->hw_features = netdev->features;
7115 netdev->hw_features |= NETIF_F_RXFCS;
7116 netdev->priv_flags |= IFF_SUPP_NOFCS;
7117 netdev->hw_features |= NETIF_F_RXALL;
7118
7119 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
7120 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7121
7122 netdev->vlan_features |= (NETIF_F_SG |
7123 NETIF_F_TSO |
7124 NETIF_F_TSO6 |
7125 NETIF_F_HW_CSUM);
7126
7127 netdev->priv_flags |= IFF_UNICAST_FLT;
7128
7129 if (pci_using_dac) {
7130 netdev->features |= NETIF_F_HIGHDMA;
7131 netdev->vlan_features |= NETIF_F_HIGHDMA;
7132 }
7133
7134 if (e1000e_enable_mng_pass_thru(&adapter->hw))
7135 adapter->flags |= FLAG_MNG_PT_ENABLED;
7136
7137 /* before reading the NVM, reset the controller to
7138 * put the device in a known good starting state
7139 */
7140 adapter->hw.mac.ops.reset_hw(&adapter->hw);
7141
7142 /* systems with ASPM and others may see the checksum fail on the first
7143 * attempt. Let's give it a few tries
7144 */
7145 for (i = 0;; i++) {
7146 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
7147 break;
7148 if (i == 2) {
7149 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
7150 err = -EIO;
7151 goto err_eeprom;
7152 }
7153 }
7154
7155 e1000_eeprom_checks(adapter);
7156
7157 /* copy the MAC address */
7158 if (e1000e_read_mac_addr(&adapter->hw))
7159 dev_err(&pdev->dev,
7160 "NVM Read Error while reading MAC address\n");
7161
7162 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
7163
7164 if (!is_valid_ether_addr(netdev->dev_addr)) {
7165 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
7166 netdev->dev_addr);
7167 err = -EIO;
7168 goto err_eeprom;
7169 }
7170
7171 init_timer(&adapter->watchdog_timer);
7172 adapter->watchdog_timer.function = e1000_watchdog;
7173 adapter->watchdog_timer.data = (unsigned long)adapter;
7174
7175 init_timer(&adapter->phy_info_timer);
7176 adapter->phy_info_timer.function = e1000_update_phy_info;
7177 adapter->phy_info_timer.data = (unsigned long)adapter;
7178
7179 INIT_WORK(&adapter->reset_task, e1000_reset_task);
7180 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
7181 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7182 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
7183 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
7184
7185 /* Initialize link parameters. User can change them with ethtool */
7186 adapter->hw.mac.autoneg = 1;
7187 adapter->fc_autoneg = true;
7188 adapter->hw.fc.requested_mode = e1000_fc_default;
7189 adapter->hw.fc.current_mode = e1000_fc_default;
7190 adapter->hw.phy.autoneg_advertised = 0x2f;
7191
7192 /* Initial Wake on LAN setting - If APM wake is enabled in
7193 * the EEPROM, enable the ACPI Magic Packet filter
7194 */
7195 if (adapter->flags & FLAG_APME_IN_WUC) {
7196 /* APME bit in EEPROM is mapped to WUC.APME */
7197 eeprom_data = er32(WUC);
7198 eeprom_apme_mask = E1000_WUC_APME;
7199 if ((hw->mac.type > e1000_ich10lan) &&
7200 (eeprom_data & E1000_WUC_PHY_WAKE))
7201 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
7202 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7203 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7204 (adapter->hw.bus.func == 1))
7205 rval = e1000_read_nvm(&adapter->hw,
7206 NVM_INIT_CONTROL3_PORT_B,
7207 1, &eeprom_data);
7208 else
7209 rval = e1000_read_nvm(&adapter->hw,
7210 NVM_INIT_CONTROL3_PORT_A,
7211 1, &eeprom_data);
7212 }
7213
7214 /* fetch WoL from EEPROM */
7215 if (rval)
7216 e_dbg("NVM read error getting WoL initial values: %d\n", rval);
7217 else if (eeprom_data & eeprom_apme_mask)
7218 adapter->eeprom_wol |= E1000_WUFC_MAG;
7219
7220 /* now that we have the eeprom settings, apply the special cases
7221 * where the eeprom may be wrong or the board simply won't support
7222 * wake on lan on a particular port
7223 */
7224 if (!(adapter->flags & FLAG_HAS_WOL))
7225 adapter->eeprom_wol = 0;
7226
7227 /* initialize the wol settings based on the eeprom settings */
7228 adapter->wol = adapter->eeprom_wol;
7229
7230 /* make sure adapter isn't asleep if manageability is enabled */
7231 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7232 (hw->mac.ops.check_mng_mode(hw)))
7233 device_wakeup_enable(&pdev->dev);
7234
7235 /* save off EEPROM version number */
7236 rval = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
7237
7238 if (rval) {
7239 e_dbg("NVM read error getting EEPROM version: %d\n", rval);
7240 adapter->eeprom_vers = 0;
7241 }
7242
7243 /* reset the hardware with the new settings */
7244 e1000e_reset(adapter);
7245
7246 /* If the controller has AMT, do not set DRV_LOAD until the interface
7247 * is up. For all other cases, let the f/w know that the h/w is now
7248 * under the control of the driver.
7249 */
7250 if (!(adapter->flags & FLAG_HAS_AMT))
7251 e1000e_get_hw_control(adapter);
7252
7253 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
7254 err = register_netdev(netdev);
7255 if (err)
7256 goto err_register;
7257
7258 /* carrier off reporting is important to ethtool even BEFORE open */
7259 netif_carrier_off(netdev);
7260
7261 /* init PTP hardware clock */
7262 e1000e_ptp_init(adapter);
7263
7264 e1000_print_device_info(adapter);
7265
7266 if (pci_dev_run_wake(pdev))
7267 pm_runtime_put_noidle(&pdev->dev);
7268
7269 return 0;
7270
7271 err_register:
7272 if (!(adapter->flags & FLAG_HAS_AMT))
7273 e1000e_release_hw_control(adapter);
7274 err_eeprom:
7275 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
7276 e1000_phy_hw_reset(&adapter->hw);
7277 err_hw_init:
7278 kfree(adapter->tx_ring);
7279 kfree(adapter->rx_ring);
7280 err_sw_init:
7281 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
7282 iounmap(adapter->hw.flash_address);
7283 e1000e_reset_interrupt_capability(adapter);
7284 err_flashmap:
7285 iounmap(adapter->hw.hw_addr);
7286 err_ioremap:
7287 free_netdev(netdev);
7288 err_alloc_etherdev:
7289 pci_release_selected_regions(pdev,
7290 pci_select_bars(pdev, IORESOURCE_MEM));
7291 err_pci_reg:
7292 err_dma:
7293 pci_disable_device(pdev);
7294 return err;
7295 }
7296
7297 /**
7298 * e1000_remove - Device Removal Routine
7299 * @pdev: PCI device information struct
7300 *
7301 * e1000_remove is called by the PCI subsystem to alert the driver
7302 * that it should release a PCI device. The could be caused by a
7303 * Hot-Plug event, or because the driver is going to be removed from
7304 * memory.
7305 **/
7306 static void e1000_remove(struct pci_dev *pdev)
7307 {
7308 struct net_device *netdev = pci_get_drvdata(pdev);
7309 struct e1000_adapter *adapter = netdev_priv(netdev);
7310 bool down = test_bit(__E1000_DOWN, &adapter->state);
7311
7312 e1000e_ptp_remove(adapter);
7313
7314 /* The timers may be rescheduled, so explicitly disable them
7315 * from being rescheduled.
7316 */
7317 if (!down)
7318 set_bit(__E1000_DOWN, &adapter->state);
7319 del_timer_sync(&adapter->watchdog_timer);
7320 del_timer_sync(&adapter->phy_info_timer);
7321
7322 cancel_work_sync(&adapter->reset_task);
7323 cancel_work_sync(&adapter->watchdog_task);
7324 cancel_work_sync(&adapter->downshift_task);
7325 cancel_work_sync(&adapter->update_phy_task);
7326 cancel_work_sync(&adapter->print_hang_task);
7327
7328 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7329 cancel_work_sync(&adapter->tx_hwtstamp_work);
7330 if (adapter->tx_hwtstamp_skb) {
7331 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
7332 adapter->tx_hwtstamp_skb = NULL;
7333 }
7334 }
7335
7336 /* Don't lie to e1000_close() down the road. */
7337 if (!down)
7338 clear_bit(__E1000_DOWN, &adapter->state);
7339 unregister_netdev(netdev);
7340
7341 if (pci_dev_run_wake(pdev))
7342 pm_runtime_get_noresume(&pdev->dev);
7343
7344 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7345 * would have already happened in close and is redundant.
7346 */
7347 e1000e_release_hw_control(adapter);
7348
7349 e1000e_reset_interrupt_capability(adapter);
7350 kfree(adapter->tx_ring);
7351 kfree(adapter->rx_ring);
7352
7353 iounmap(adapter->hw.hw_addr);
7354 if ((adapter->hw.flash_address) &&
7355 (adapter->hw.mac.type < e1000_pch_spt))
7356 iounmap(adapter->hw.flash_address);
7357 pci_release_selected_regions(pdev,
7358 pci_select_bars(pdev, IORESOURCE_MEM));
7359
7360 free_netdev(netdev);
7361
7362 /* AER disable */
7363 pci_disable_pcie_error_reporting(pdev);
7364
7365 pci_disable_device(pdev);
7366 }
7367
7368 /* PCI Error Recovery (ERS) */
7369 static const struct pci_error_handlers e1000_err_handler = {
7370 .error_detected = e1000_io_error_detected,
7371 .slot_reset = e1000_io_slot_reset,
7372 .resume = e1000_io_resume,
7373 };
7374
7375 static const struct pci_device_id e1000_pci_tbl[] = {
7376 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7377 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7378 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
7379 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7380 board_82571 },
7381 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7382 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
7383 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7384 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7385 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
7386
7387 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7388 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7389 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7390 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
7391
7392 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7393 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7394 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
7395
7396 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
7397 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
7398 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
7399
7400 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7401 board_80003es2lan },
7402 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7403 board_80003es2lan },
7404 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7405 board_80003es2lan },
7406 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7407 board_80003es2lan },
7408
7409 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7410 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7411 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7412 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7413 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7414 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7415 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
7416 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
7417
7418 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7419 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7420 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7421 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7422 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
7423 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
7424 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7425 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7426 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7427
7428 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7429 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7430 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
7431
7432 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7433 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
7434 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
7435
7436 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7437 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7438 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7439 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7440
7441 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7442 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7443
7444 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7445 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
7446 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7447 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
7448 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7449 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7450 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7451 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
7452 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
7453 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
7454 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
7455 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
7456
7457 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
7458 };
7459 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7460
7461 static const struct dev_pm_ops e1000_pm_ops = {
7462 #ifdef CONFIG_PM_SLEEP
7463 .suspend = e1000e_pm_suspend,
7464 .resume = e1000e_pm_resume,
7465 .freeze = e1000e_pm_freeze,
7466 .thaw = e1000e_pm_thaw,
7467 .poweroff = e1000e_pm_suspend,
7468 .restore = e1000e_pm_resume,
7469 #endif
7470 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7471 e1000e_pm_runtime_idle)
7472 };
7473
7474 /* PCI Device API Driver */
7475 static struct pci_driver e1000_driver = {
7476 .name = e1000e_driver_name,
7477 .id_table = e1000_pci_tbl,
7478 .probe = e1000_probe,
7479 .remove = e1000_remove,
7480 .driver = {
7481 .pm = &e1000_pm_ops,
7482 },
7483 .shutdown = e1000_shutdown,
7484 .err_handler = &e1000_err_handler
7485 };
7486
7487 /**
7488 * e1000_init_module - Driver Registration Routine
7489 *
7490 * e1000_init_module is the first routine called when the driver is
7491 * loaded. All it does is register with the PCI subsystem.
7492 **/
7493 static int __init e1000_init_module(void)
7494 {
7495 int ret;
7496
7497 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7498 e1000e_driver_version);
7499 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
7500 ret = pci_register_driver(&e1000_driver);
7501
7502 return ret;
7503 }
7504 module_init(e1000_init_module);
7505
7506 /**
7507 * e1000_exit_module - Driver Exit Cleanup Routine
7508 *
7509 * e1000_exit_module is called just before the driver is removed
7510 * from memory.
7511 **/
7512 static void __exit e1000_exit_module(void)
7513 {
7514 pci_unregister_driver(&e1000_driver);
7515 }
7516 module_exit(e1000_exit_module);
7517
7518 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7519 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7520 MODULE_LICENSE("GPL");
7521 MODULE_VERSION(DRV_VERSION);
7522
7523 /* netdev.c */
Linux kernel - Deliverables
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