1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
31 static s32
e1000_wait_autoneg(struct e1000_hw
*hw
);
32 static s32
e1000_access_phy_wakeup_reg_bm(struct e1000_hw
*hw
, u32 offset
,
33 u16
*data
, bool read
, bool page_set
);
34 static u32
e1000_get_phy_addr_for_hv_page(u32 page
);
35 static s32
e1000_access_phy_debug_regs_hv(struct e1000_hw
*hw
, u32 offset
,
36 u16
*data
, bool read
);
38 /* Cable length tables */
39 static const u16 e1000_m88_cable_length_table
[] = {
40 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
};
42 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
43 ARRAY_SIZE(e1000_m88_cable_length_table)
45 static const u16 e1000_igp_2_cable_length_table
[] = {
46 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
47 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
48 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
49 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
50 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
51 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
52 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
55 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
56 ARRAY_SIZE(e1000_igp_2_cable_length_table)
59 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
60 * @hw: pointer to the HW structure
62 * Read the PHY management control register and check whether a PHY reset
63 * is blocked. If a reset is not blocked return 0, otherwise
64 * return E1000_BLK_PHY_RESET (12).
66 s32
e1000e_check_reset_block_generic(struct e1000_hw
*hw
)
72 return (manc
& E1000_MANC_BLK_PHY_RST_ON_IDE
) ?
73 E1000_BLK_PHY_RESET
: 0;
77 * e1000e_get_phy_id - Retrieve the PHY ID and revision
78 * @hw: pointer to the HW structure
80 * Reads the PHY registers and stores the PHY ID and possibly the PHY
81 * revision in the hardware structure.
83 s32
e1000e_get_phy_id(struct e1000_hw
*hw
)
85 struct e1000_phy_info
*phy
= &hw
->phy
;
90 if (!phy
->ops
.read_reg
)
93 while (retry_count
< 2) {
94 ret_val
= e1e_rphy(hw
, MII_PHYSID1
, &phy_id
);
98 phy
->id
= (u32
)(phy_id
<< 16);
100 ret_val
= e1e_rphy(hw
, MII_PHYSID2
, &phy_id
);
104 phy
->id
|= (u32
)(phy_id
& PHY_REVISION_MASK
);
105 phy
->revision
= (u32
)(phy_id
& ~PHY_REVISION_MASK
);
107 if (phy
->id
!= 0 && phy
->id
!= PHY_REVISION_MASK
)
117 * e1000e_phy_reset_dsp - Reset PHY DSP
118 * @hw: pointer to the HW structure
120 * Reset the digital signal processor.
122 s32
e1000e_phy_reset_dsp(struct e1000_hw
*hw
)
126 ret_val
= e1e_wphy(hw
, M88E1000_PHY_GEN_CONTROL
, 0xC1);
130 return e1e_wphy(hw
, M88E1000_PHY_GEN_CONTROL
, 0);
134 * e1000e_read_phy_reg_mdic - Read MDI control register
135 * @hw: pointer to the HW structure
136 * @offset: register offset to be read
137 * @data: pointer to the read data
139 * Reads the MDI control register in the PHY at offset and stores the
140 * information read to data.
142 s32
e1000e_read_phy_reg_mdic(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
144 struct e1000_phy_info
*phy
= &hw
->phy
;
147 if (offset
> MAX_PHY_REG_ADDRESS
) {
148 e_dbg("PHY Address %d is out of range\n", offset
);
149 return -E1000_ERR_PARAM
;
152 /* Set up Op-code, Phy Address, and register offset in the MDI
153 * Control register. The MAC will take care of interfacing with the
154 * PHY to retrieve the desired data.
156 mdic
= ((offset
<< E1000_MDIC_REG_SHIFT
) |
157 (phy
->addr
<< E1000_MDIC_PHY_SHIFT
) |
158 (E1000_MDIC_OP_READ
));
162 /* Poll the ready bit to see if the MDI read completed
163 * Increasing the time out as testing showed failures with
166 for (i
= 0; i
< (E1000_GEN_POLL_TIMEOUT
* 3); i
++) {
169 if (mdic
& E1000_MDIC_READY
)
172 if (!(mdic
& E1000_MDIC_READY
)) {
173 e_dbg("MDI Read did not complete\n");
174 return -E1000_ERR_PHY
;
176 if (mdic
& E1000_MDIC_ERROR
) {
177 e_dbg("MDI Error\n");
178 return -E1000_ERR_PHY
;
182 /* Allow some time after each MDIC transaction to avoid
183 * reading duplicate data in the next MDIC transaction.
185 if (hw
->mac
.type
== e1000_pch2lan
)
192 * e1000e_write_phy_reg_mdic - Write MDI control register
193 * @hw: pointer to the HW structure
194 * @offset: register offset to write to
195 * @data: data to write to register at offset
197 * Writes data to MDI control register in the PHY at offset.
199 s32
e1000e_write_phy_reg_mdic(struct e1000_hw
*hw
, u32 offset
, u16 data
)
201 struct e1000_phy_info
*phy
= &hw
->phy
;
204 if (offset
> MAX_PHY_REG_ADDRESS
) {
205 e_dbg("PHY Address %d is out of range\n", offset
);
206 return -E1000_ERR_PARAM
;
209 /* Set up Op-code, Phy Address, and register offset in the MDI
210 * Control register. The MAC will take care of interfacing with the
211 * PHY to retrieve the desired data.
213 mdic
= (((u32
)data
) |
214 (offset
<< E1000_MDIC_REG_SHIFT
) |
215 (phy
->addr
<< E1000_MDIC_PHY_SHIFT
) |
216 (E1000_MDIC_OP_WRITE
));
220 /* Poll the ready bit to see if the MDI read completed
221 * Increasing the time out as testing showed failures with
224 for (i
= 0; i
< (E1000_GEN_POLL_TIMEOUT
* 3); i
++) {
227 if (mdic
& E1000_MDIC_READY
)
230 if (!(mdic
& E1000_MDIC_READY
)) {
231 e_dbg("MDI Write did not complete\n");
232 return -E1000_ERR_PHY
;
234 if (mdic
& E1000_MDIC_ERROR
) {
235 e_dbg("MDI Error\n");
236 return -E1000_ERR_PHY
;
239 /* Allow some time after each MDIC transaction to avoid
240 * reading duplicate data in the next MDIC transaction.
242 if (hw
->mac
.type
== e1000_pch2lan
)
249 * e1000e_read_phy_reg_m88 - Read m88 PHY register
250 * @hw: pointer to the HW structure
251 * @offset: register offset to be read
252 * @data: pointer to the read data
254 * Acquires semaphore, if necessary, then reads the PHY register at offset
255 * and storing the retrieved information in data. Release any acquired
256 * semaphores before exiting.
258 s32
e1000e_read_phy_reg_m88(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
262 ret_val
= hw
->phy
.ops
.acquire(hw
);
266 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
269 hw
->phy
.ops
.release(hw
);
275 * e1000e_write_phy_reg_m88 - Write m88 PHY register
276 * @hw: pointer to the HW structure
277 * @offset: register offset to write to
278 * @data: data to write at register offset
280 * Acquires semaphore, if necessary, then writes the data to PHY register
281 * at the offset. Release any acquired semaphores before exiting.
283 s32
e1000e_write_phy_reg_m88(struct e1000_hw
*hw
, u32 offset
, u16 data
)
287 ret_val
= hw
->phy
.ops
.acquire(hw
);
291 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
294 hw
->phy
.ops
.release(hw
);
300 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
301 * @hw: pointer to the HW structure
302 * @page: page to set (shifted left when necessary)
304 * Sets PHY page required for PHY register access. Assumes semaphore is
305 * already acquired. Note, this function sets phy.addr to 1 so the caller
306 * must set it appropriately (if necessary) after this function returns.
308 s32
e1000_set_page_igp(struct e1000_hw
*hw
, u16 page
)
310 e_dbg("Setting page 0x%x\n", page
);
314 return e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
, page
);
318 * __e1000e_read_phy_reg_igp - Read igp PHY register
319 * @hw: pointer to the HW structure
320 * @offset: register offset to be read
321 * @data: pointer to the read data
322 * @locked: semaphore has already been acquired or not
324 * Acquires semaphore, if necessary, then reads the PHY register at offset
325 * and stores the retrieved information in data. Release any acquired
326 * semaphores before exiting.
328 static s32
__e1000e_read_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16
*data
,
334 if (!hw
->phy
.ops
.acquire
)
337 ret_val
= hw
->phy
.ops
.acquire(hw
);
342 if (offset
> MAX_PHY_MULTI_PAGE_REG
)
343 ret_val
= e1000e_write_phy_reg_mdic(hw
,
344 IGP01E1000_PHY_PAGE_SELECT
,
347 ret_val
= e1000e_read_phy_reg_mdic(hw
,
348 MAX_PHY_REG_ADDRESS
& offset
,
351 hw
->phy
.ops
.release(hw
);
357 * e1000e_read_phy_reg_igp - Read igp PHY register
358 * @hw: pointer to the HW structure
359 * @offset: register offset to be read
360 * @data: pointer to the read data
362 * Acquires semaphore then reads the PHY register at offset and stores the
363 * retrieved information in data.
364 * Release the acquired semaphore before exiting.
366 s32
e1000e_read_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
368 return __e1000e_read_phy_reg_igp(hw
, offset
, data
, false);
372 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
373 * @hw: pointer to the HW structure
374 * @offset: register offset to be read
375 * @data: pointer to the read data
377 * Reads the PHY register at offset and stores the retrieved information
378 * in data. Assumes semaphore already acquired.
380 s32
e1000e_read_phy_reg_igp_locked(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
382 return __e1000e_read_phy_reg_igp(hw
, offset
, data
, true);
386 * e1000e_write_phy_reg_igp - Write igp PHY register
387 * @hw: pointer to the HW structure
388 * @offset: register offset to write to
389 * @data: data to write at register offset
390 * @locked: semaphore has already been acquired or not
392 * Acquires semaphore, if necessary, then writes the data to PHY register
393 * at the offset. Release any acquired semaphores before exiting.
395 static s32
__e1000e_write_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16 data
,
401 if (!hw
->phy
.ops
.acquire
)
404 ret_val
= hw
->phy
.ops
.acquire(hw
);
409 if (offset
> MAX_PHY_MULTI_PAGE_REG
)
410 ret_val
= e1000e_write_phy_reg_mdic(hw
,
411 IGP01E1000_PHY_PAGE_SELECT
,
414 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
&
417 hw
->phy
.ops
.release(hw
);
423 * e1000e_write_phy_reg_igp - Write igp PHY register
424 * @hw: pointer to the HW structure
425 * @offset: register offset to write to
426 * @data: data to write at register offset
428 * Acquires semaphore then writes the data to PHY register
429 * at the offset. Release any acquired semaphores before exiting.
431 s32
e1000e_write_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16 data
)
433 return __e1000e_write_phy_reg_igp(hw
, offset
, data
, false);
437 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
438 * @hw: pointer to the HW structure
439 * @offset: register offset to write to
440 * @data: data to write at register offset
442 * Writes the data to PHY register at the offset.
443 * Assumes semaphore already acquired.
445 s32
e1000e_write_phy_reg_igp_locked(struct e1000_hw
*hw
, u32 offset
, u16 data
)
447 return __e1000e_write_phy_reg_igp(hw
, offset
, data
, true);
451 * __e1000_read_kmrn_reg - Read kumeran register
452 * @hw: pointer to the HW structure
453 * @offset: register offset to be read
454 * @data: pointer to the read data
455 * @locked: semaphore has already been acquired or not
457 * Acquires semaphore, if necessary. Then reads the PHY register at offset
458 * using the kumeran interface. The information retrieved is stored in data.
459 * Release any acquired semaphores before exiting.
461 static s32
__e1000_read_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16
*data
,
469 if (!hw
->phy
.ops
.acquire
)
472 ret_val
= hw
->phy
.ops
.acquire(hw
);
477 kmrnctrlsta
= ((offset
<< E1000_KMRNCTRLSTA_OFFSET_SHIFT
) &
478 E1000_KMRNCTRLSTA_OFFSET
) | E1000_KMRNCTRLSTA_REN
;
479 ew32(KMRNCTRLSTA
, kmrnctrlsta
);
484 kmrnctrlsta
= er32(KMRNCTRLSTA
);
485 *data
= (u16
)kmrnctrlsta
;
488 hw
->phy
.ops
.release(hw
);
494 * e1000e_read_kmrn_reg - Read kumeran register
495 * @hw: pointer to the HW structure
496 * @offset: register offset to be read
497 * @data: pointer to the read data
499 * Acquires semaphore then reads the PHY register at offset using the
500 * kumeran interface. The information retrieved is stored in data.
501 * Release the acquired semaphore before exiting.
503 s32
e1000e_read_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
505 return __e1000_read_kmrn_reg(hw
, offset
, data
, false);
509 * e1000e_read_kmrn_reg_locked - Read kumeran register
510 * @hw: pointer to the HW structure
511 * @offset: register offset to be read
512 * @data: pointer to the read data
514 * Reads the PHY register at offset using the kumeran interface. The
515 * information retrieved is stored in data.
516 * Assumes semaphore already acquired.
518 s32
e1000e_read_kmrn_reg_locked(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
520 return __e1000_read_kmrn_reg(hw
, offset
, data
, true);
524 * __e1000_write_kmrn_reg - Write kumeran register
525 * @hw: pointer to the HW structure
526 * @offset: register offset to write to
527 * @data: data to write at register offset
528 * @locked: semaphore has already been acquired or not
530 * Acquires semaphore, if necessary. Then write the data to PHY register
531 * at the offset using the kumeran interface. Release any acquired semaphores
534 static s32
__e1000_write_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16 data
,
542 if (!hw
->phy
.ops
.acquire
)
545 ret_val
= hw
->phy
.ops
.acquire(hw
);
550 kmrnctrlsta
= ((offset
<< E1000_KMRNCTRLSTA_OFFSET_SHIFT
) &
551 E1000_KMRNCTRLSTA_OFFSET
) | data
;
552 ew32(KMRNCTRLSTA
, kmrnctrlsta
);
558 hw
->phy
.ops
.release(hw
);
564 * e1000e_write_kmrn_reg - Write kumeran register
565 * @hw: pointer to the HW structure
566 * @offset: register offset to write to
567 * @data: data to write at register offset
569 * Acquires semaphore then writes the data to the PHY register at the offset
570 * using the kumeran interface. Release the acquired semaphore before exiting.
572 s32
e1000e_write_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16 data
)
574 return __e1000_write_kmrn_reg(hw
, offset
, data
, false);
578 * e1000e_write_kmrn_reg_locked - Write kumeran register
579 * @hw: pointer to the HW structure
580 * @offset: register offset to write to
581 * @data: data to write at register offset
583 * Write the data to PHY register at the offset using the kumeran interface.
584 * Assumes semaphore already acquired.
586 s32
e1000e_write_kmrn_reg_locked(struct e1000_hw
*hw
, u32 offset
, u16 data
)
588 return __e1000_write_kmrn_reg(hw
, offset
, data
, true);
592 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
593 * @hw: pointer to the HW structure
595 * Sets up Master/slave mode
597 static s32
e1000_set_master_slave_mode(struct e1000_hw
*hw
)
602 /* Resolve Master/Slave mode */
603 ret_val
= e1e_rphy(hw
, MII_CTRL1000
, &phy_data
);
607 /* load defaults for future use */
608 hw
->phy
.original_ms_type
= (phy_data
& CTL1000_ENABLE_MASTER
) ?
609 ((phy_data
& CTL1000_AS_MASTER
) ?
610 e1000_ms_force_master
: e1000_ms_force_slave
) : e1000_ms_auto
;
612 switch (hw
->phy
.ms_type
) {
613 case e1000_ms_force_master
:
614 phy_data
|= (CTL1000_ENABLE_MASTER
| CTL1000_AS_MASTER
);
616 case e1000_ms_force_slave
:
617 phy_data
|= CTL1000_ENABLE_MASTER
;
618 phy_data
&= ~(CTL1000_AS_MASTER
);
621 phy_data
&= ~CTL1000_ENABLE_MASTER
;
627 return e1e_wphy(hw
, MII_CTRL1000
, phy_data
);
631 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
632 * @hw: pointer to the HW structure
634 * Sets up Carrier-sense on Transmit and downshift values.
636 s32
e1000_copper_link_setup_82577(struct e1000_hw
*hw
)
641 /* Enable CRS on Tx. This must be set for half-duplex operation. */
642 ret_val
= e1e_rphy(hw
, I82577_CFG_REG
, &phy_data
);
646 phy_data
|= I82577_CFG_ASSERT_CRS_ON_TX
;
648 /* Enable downshift */
649 phy_data
|= I82577_CFG_ENABLE_DOWNSHIFT
;
651 ret_val
= e1e_wphy(hw
, I82577_CFG_REG
, phy_data
);
655 /* Set MDI/MDIX mode */
656 ret_val
= e1e_rphy(hw
, I82577_PHY_CTRL_2
, &phy_data
);
659 phy_data
&= ~I82577_PHY_CTRL2_MDIX_CFG_MASK
;
665 switch (hw
->phy
.mdix
) {
669 phy_data
|= I82577_PHY_CTRL2_MANUAL_MDIX
;
673 phy_data
|= I82577_PHY_CTRL2_AUTO_MDI_MDIX
;
676 ret_val
= e1e_wphy(hw
, I82577_PHY_CTRL_2
, phy_data
);
680 return e1000_set_master_slave_mode(hw
);
684 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
685 * @hw: pointer to the HW structure
687 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
688 * and downshift values are set also.
690 s32
e1000e_copper_link_setup_m88(struct e1000_hw
*hw
)
692 struct e1000_phy_info
*phy
= &hw
->phy
;
696 /* Enable CRS on Tx. This must be set for half-duplex operation. */
697 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
701 /* For BM PHY this bit is downshift enable */
702 if (phy
->type
!= e1000_phy_bm
)
703 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
706 * MDI/MDI-X = 0 (default)
707 * 0 - Auto for all speeds
710 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
712 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
716 phy_data
|= M88E1000_PSCR_MDI_MANUAL_MODE
;
719 phy_data
|= M88E1000_PSCR_MDIX_MANUAL_MODE
;
722 phy_data
|= M88E1000_PSCR_AUTO_X_1000T
;
726 phy_data
|= M88E1000_PSCR_AUTO_X_MODE
;
731 * disable_polarity_correction = 0 (default)
732 * Automatic Correction for Reversed Cable Polarity
736 phy_data
&= ~M88E1000_PSCR_POLARITY_REVERSAL
;
737 if (phy
->disable_polarity_correction
)
738 phy_data
|= M88E1000_PSCR_POLARITY_REVERSAL
;
740 /* Enable downshift on BM (disabled by default) */
741 if (phy
->type
== e1000_phy_bm
) {
742 /* For 82574/82583, first disable then enable downshift */
743 if (phy
->id
== BME1000_E_PHY_ID_R2
) {
744 phy_data
&= ~BME1000_PSCR_ENABLE_DOWNSHIFT
;
745 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
,
749 /* Commit the changes. */
750 ret_val
= phy
->ops
.commit(hw
);
752 e_dbg("Error committing the PHY changes\n");
757 phy_data
|= BME1000_PSCR_ENABLE_DOWNSHIFT
;
760 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
764 if ((phy
->type
== e1000_phy_m88
) &&
765 (phy
->revision
< E1000_REVISION_4
) &&
766 (phy
->id
!= BME1000_E_PHY_ID_R2
)) {
767 /* Force TX_CLK in the Extended PHY Specific Control Register
770 ret_val
= e1e_rphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
774 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
776 if ((phy
->revision
== 2) &&
777 (phy
->id
== M88E1111_I_PHY_ID
)) {
778 /* 82573L PHY - set the downshift counter to 5x. */
779 phy_data
&= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK
;
780 phy_data
|= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X
;
782 /* Configure Master and Slave downshift values */
783 phy_data
&= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
|
784 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK
);
785 phy_data
|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
|
786 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X
);
788 ret_val
= e1e_wphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
793 if ((phy
->type
== e1000_phy_bm
) && (phy
->id
== BME1000_E_PHY_ID_R2
)) {
794 /* Set PHY page 0, register 29 to 0x0003 */
795 ret_val
= e1e_wphy(hw
, 29, 0x0003);
799 /* Set PHY page 0, register 30 to 0x0000 */
800 ret_val
= e1e_wphy(hw
, 30, 0x0000);
805 /* Commit the changes. */
806 if (phy
->ops
.commit
) {
807 ret_val
= phy
->ops
.commit(hw
);
809 e_dbg("Error committing the PHY changes\n");
814 if (phy
->type
== e1000_phy_82578
) {
815 ret_val
= e1e_rphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
819 /* 82578 PHY - set the downshift count to 1x. */
820 phy_data
|= I82578_EPSCR_DOWNSHIFT_ENABLE
;
821 phy_data
&= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK
;
822 ret_val
= e1e_wphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
831 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
832 * @hw: pointer to the HW structure
834 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
837 s32
e1000e_copper_link_setup_igp(struct e1000_hw
*hw
)
839 struct e1000_phy_info
*phy
= &hw
->phy
;
843 ret_val
= e1000_phy_hw_reset(hw
);
845 e_dbg("Error resetting the PHY.\n");
849 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
850 * timeout issues when LFS is enabled.
854 /* disable lplu d0 during driver init */
855 if (hw
->phy
.ops
.set_d0_lplu_state
) {
856 ret_val
= hw
->phy
.ops
.set_d0_lplu_state(hw
, false);
858 e_dbg("Error Disabling LPLU D0\n");
862 /* Configure mdi-mdix settings */
863 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CTRL
, &data
);
867 data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
871 data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
874 data
|= IGP01E1000_PSCR_FORCE_MDI_MDIX
;
878 data
|= IGP01E1000_PSCR_AUTO_MDIX
;
881 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CTRL
, data
);
885 /* set auto-master slave resolution settings */
886 if (hw
->mac
.autoneg
) {
887 /* when autonegotiation advertisement is only 1000Mbps then we
888 * should disable SmartSpeed and enable Auto MasterSlave
889 * resolution as hardware default.
891 if (phy
->autoneg_advertised
== ADVERTISE_1000_FULL
) {
892 /* Disable SmartSpeed */
893 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
898 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
899 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
904 /* Set auto Master/Slave resolution process */
905 ret_val
= e1e_rphy(hw
, MII_CTRL1000
, &data
);
909 data
&= ~CTL1000_ENABLE_MASTER
;
910 ret_val
= e1e_wphy(hw
, MII_CTRL1000
, data
);
915 ret_val
= e1000_set_master_slave_mode(hw
);
922 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
923 * @hw: pointer to the HW structure
925 * Reads the MII auto-neg advertisement register and/or the 1000T control
926 * register and if the PHY is already setup for auto-negotiation, then
927 * return successful. Otherwise, setup advertisement and flow control to
928 * the appropriate values for the wanted auto-negotiation.
930 static s32
e1000_phy_setup_autoneg(struct e1000_hw
*hw
)
932 struct e1000_phy_info
*phy
= &hw
->phy
;
934 u16 mii_autoneg_adv_reg
;
935 u16 mii_1000t_ctrl_reg
= 0;
937 phy
->autoneg_advertised
&= phy
->autoneg_mask
;
939 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
940 ret_val
= e1e_rphy(hw
, MII_ADVERTISE
, &mii_autoneg_adv_reg
);
944 if (phy
->autoneg_mask
& ADVERTISE_1000_FULL
) {
945 /* Read the MII 1000Base-T Control Register (Address 9). */
946 ret_val
= e1e_rphy(hw
, MII_CTRL1000
, &mii_1000t_ctrl_reg
);
951 /* Need to parse both autoneg_advertised and fc and set up
952 * the appropriate PHY registers. First we will parse for
953 * autoneg_advertised software override. Since we can advertise
954 * a plethora of combinations, we need to check each bit
958 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
959 * Advertisement Register (Address 4) and the 1000 mb speed bits in
960 * the 1000Base-T Control Register (Address 9).
962 mii_autoneg_adv_reg
&= ~(ADVERTISE_100FULL
|
964 ADVERTISE_10FULL
| ADVERTISE_10HALF
);
965 mii_1000t_ctrl_reg
&= ~(ADVERTISE_1000HALF
| ADVERTISE_1000FULL
);
967 e_dbg("autoneg_advertised %x\n", phy
->autoneg_advertised
);
969 /* Do we want to advertise 10 Mb Half Duplex? */
970 if (phy
->autoneg_advertised
& ADVERTISE_10_HALF
) {
971 e_dbg("Advertise 10mb Half duplex\n");
972 mii_autoneg_adv_reg
|= ADVERTISE_10HALF
;
975 /* Do we want to advertise 10 Mb Full Duplex? */
976 if (phy
->autoneg_advertised
& ADVERTISE_10_FULL
) {
977 e_dbg("Advertise 10mb Full duplex\n");
978 mii_autoneg_adv_reg
|= ADVERTISE_10FULL
;
981 /* Do we want to advertise 100 Mb Half Duplex? */
982 if (phy
->autoneg_advertised
& ADVERTISE_100_HALF
) {
983 e_dbg("Advertise 100mb Half duplex\n");
984 mii_autoneg_adv_reg
|= ADVERTISE_100HALF
;
987 /* Do we want to advertise 100 Mb Full Duplex? */
988 if (phy
->autoneg_advertised
& ADVERTISE_100_FULL
) {
989 e_dbg("Advertise 100mb Full duplex\n");
990 mii_autoneg_adv_reg
|= ADVERTISE_100FULL
;
993 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
994 if (phy
->autoneg_advertised
& ADVERTISE_1000_HALF
)
995 e_dbg("Advertise 1000mb Half duplex request denied!\n");
997 /* Do we want to advertise 1000 Mb Full Duplex? */
998 if (phy
->autoneg_advertised
& ADVERTISE_1000_FULL
) {
999 e_dbg("Advertise 1000mb Full duplex\n");
1000 mii_1000t_ctrl_reg
|= ADVERTISE_1000FULL
;
1003 /* Check for a software override of the flow control settings, and
1004 * setup the PHY advertisement registers accordingly. If
1005 * auto-negotiation is enabled, then software will have to set the
1006 * "PAUSE" bits to the correct value in the Auto-Negotiation
1007 * Advertisement Register (MII_ADVERTISE) and re-start auto-
1010 * The possible values of the "fc" parameter are:
1011 * 0: Flow control is completely disabled
1012 * 1: Rx flow control is enabled (we can receive pause frames
1013 * but not send pause frames).
1014 * 2: Tx flow control is enabled (we can send pause frames
1015 * but we do not support receiving pause frames).
1016 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1017 * other: No software override. The flow control configuration
1018 * in the EEPROM is used.
1020 switch (hw
->fc
.current_mode
) {
1022 /* Flow control (Rx & Tx) is completely disabled by a
1023 * software over-ride.
1025 mii_autoneg_adv_reg
&=
1026 ~(ADVERTISE_PAUSE_ASYM
| ADVERTISE_PAUSE_CAP
);
1028 case e1000_fc_rx_pause
:
1029 /* Rx Flow control is enabled, and Tx Flow control is
1030 * disabled, by a software over-ride.
1032 * Since there really isn't a way to advertise that we are
1033 * capable of Rx Pause ONLY, we will advertise that we
1034 * support both symmetric and asymmetric Rx PAUSE. Later
1035 * (in e1000e_config_fc_after_link_up) we will disable the
1036 * hw's ability to send PAUSE frames.
1038 mii_autoneg_adv_reg
|=
1039 (ADVERTISE_PAUSE_ASYM
| ADVERTISE_PAUSE_CAP
);
1041 case e1000_fc_tx_pause
:
1042 /* Tx Flow control is enabled, and Rx Flow control is
1043 * disabled, by a software over-ride.
1045 mii_autoneg_adv_reg
|= ADVERTISE_PAUSE_ASYM
;
1046 mii_autoneg_adv_reg
&= ~ADVERTISE_PAUSE_CAP
;
1049 /* Flow control (both Rx and Tx) is enabled by a software
1052 mii_autoneg_adv_reg
|=
1053 (ADVERTISE_PAUSE_ASYM
| ADVERTISE_PAUSE_CAP
);
1056 e_dbg("Flow control param set incorrectly\n");
1057 return -E1000_ERR_CONFIG
;
1060 ret_val
= e1e_wphy(hw
, MII_ADVERTISE
, mii_autoneg_adv_reg
);
1064 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg
);
1066 if (phy
->autoneg_mask
& ADVERTISE_1000_FULL
)
1067 ret_val
= e1e_wphy(hw
, MII_CTRL1000
, mii_1000t_ctrl_reg
);
1073 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1074 * @hw: pointer to the HW structure
1076 * Performs initial bounds checking on autoneg advertisement parameter, then
1077 * configure to advertise the full capability. Setup the PHY to autoneg
1078 * and restart the negotiation process between the link partner. If
1079 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1081 static s32
e1000_copper_link_autoneg(struct e1000_hw
*hw
)
1083 struct e1000_phy_info
*phy
= &hw
->phy
;
1087 /* Perform some bounds checking on the autoneg advertisement
1090 phy
->autoneg_advertised
&= phy
->autoneg_mask
;
1092 /* If autoneg_advertised is zero, we assume it was not defaulted
1093 * by the calling code so we set to advertise full capability.
1095 if (!phy
->autoneg_advertised
)
1096 phy
->autoneg_advertised
= phy
->autoneg_mask
;
1098 e_dbg("Reconfiguring auto-neg advertisement params\n");
1099 ret_val
= e1000_phy_setup_autoneg(hw
);
1101 e_dbg("Error Setting up Auto-Negotiation\n");
1104 e_dbg("Restarting Auto-Neg\n");
1106 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1107 * the Auto Neg Restart bit in the PHY control register.
1109 ret_val
= e1e_rphy(hw
, MII_BMCR
, &phy_ctrl
);
1113 phy_ctrl
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
1114 ret_val
= e1e_wphy(hw
, MII_BMCR
, phy_ctrl
);
1118 /* Does the user want to wait for Auto-Neg to complete here, or
1119 * check at a later time (for example, callback routine).
1121 if (phy
->autoneg_wait_to_complete
) {
1122 ret_val
= e1000_wait_autoneg(hw
);
1124 e_dbg("Error while waiting for autoneg to complete\n");
1129 hw
->mac
.get_link_status
= true;
1135 * e1000e_setup_copper_link - Configure copper link settings
1136 * @hw: pointer to the HW structure
1138 * Calls the appropriate function to configure the link for auto-neg or forced
1139 * speed and duplex. Then we check for link, once link is established calls
1140 * to configure collision distance and flow control are called. If link is
1141 * not established, we return -E1000_ERR_PHY (-2).
1143 s32
e1000e_setup_copper_link(struct e1000_hw
*hw
)
1148 if (hw
->mac
.autoneg
) {
1149 /* Setup autoneg and flow control advertisement and perform
1152 ret_val
= e1000_copper_link_autoneg(hw
);
1156 /* PHY will be set to 10H, 10F, 100H or 100F
1157 * depending on user settings.
1159 e_dbg("Forcing Speed and Duplex\n");
1160 ret_val
= hw
->phy
.ops
.force_speed_duplex(hw
);
1162 e_dbg("Error Forcing Speed and Duplex\n");
1167 /* Check link status. Wait up to 100 microseconds for link to become
1170 ret_val
= e1000e_phy_has_link_generic(hw
, COPPER_LINK_UP_LIMIT
, 10,
1176 e_dbg("Valid link established!!!\n");
1177 hw
->mac
.ops
.config_collision_dist(hw
);
1178 ret_val
= e1000e_config_fc_after_link_up(hw
);
1180 e_dbg("Unable to establish link!!!\n");
1187 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1188 * @hw: pointer to the HW structure
1190 * Calls the PHY setup function to force speed and duplex. Clears the
1191 * auto-crossover to force MDI manually. Waits for link and returns
1192 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1194 s32
e1000e_phy_force_speed_duplex_igp(struct e1000_hw
*hw
)
1196 struct e1000_phy_info
*phy
= &hw
->phy
;
1201 ret_val
= e1e_rphy(hw
, MII_BMCR
, &phy_data
);
1205 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
1207 ret_val
= e1e_wphy(hw
, MII_BMCR
, phy_data
);
1211 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1212 * forced whenever speed and duplex are forced.
1214 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CTRL
, &phy_data
);
1218 phy_data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
1219 phy_data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1221 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CTRL
, phy_data
);
1225 e_dbg("IGP PSCR: %X\n", phy_data
);
1229 if (phy
->autoneg_wait_to_complete
) {
1230 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1232 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1238 e_dbg("Link taking longer than expected.\n");
1241 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1249 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1250 * @hw: pointer to the HW structure
1252 * Calls the PHY setup function to force speed and duplex. Clears the
1253 * auto-crossover to force MDI manually. Resets the PHY to commit the
1254 * changes. If time expires while waiting for link up, we reset the DSP.
1255 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1256 * successful completion, else return corresponding error code.
1258 s32
e1000e_phy_force_speed_duplex_m88(struct e1000_hw
*hw
)
1260 struct e1000_phy_info
*phy
= &hw
->phy
;
1265 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1266 * forced whenever speed and duplex are forced.
1268 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1272 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
1273 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1277 e_dbg("M88E1000 PSCR: %X\n", phy_data
);
1279 ret_val
= e1e_rphy(hw
, MII_BMCR
, &phy_data
);
1283 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
1285 ret_val
= e1e_wphy(hw
, MII_BMCR
, phy_data
);
1289 /* Reset the phy to commit changes. */
1290 if (hw
->phy
.ops
.commit
) {
1291 ret_val
= hw
->phy
.ops
.commit(hw
);
1296 if (phy
->autoneg_wait_to_complete
) {
1297 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1299 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1305 if (hw
->phy
.type
!= e1000_phy_m88
) {
1306 e_dbg("Link taking longer than expected.\n");
1308 /* We didn't get link.
1309 * Reset the DSP and cross our fingers.
1311 ret_val
= e1e_wphy(hw
, M88E1000_PHY_PAGE_SELECT
,
1315 ret_val
= e1000e_phy_reset_dsp(hw
);
1322 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1328 if (hw
->phy
.type
!= e1000_phy_m88
)
1331 ret_val
= e1e_rphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
1335 /* Resetting the phy means we need to re-force TX_CLK in the
1336 * Extended PHY Specific Control Register to 25MHz clock from
1337 * the reset value of 2.5MHz.
1339 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
1340 ret_val
= e1e_wphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
1344 /* In addition, we must re-enable CRS on Tx for both half and full
1347 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1351 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
1352 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1358 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1359 * @hw: pointer to the HW structure
1361 * Forces the speed and duplex settings of the PHY.
1362 * This is a function pointer entry point only called by
1363 * PHY setup routines.
1365 s32
e1000_phy_force_speed_duplex_ife(struct e1000_hw
*hw
)
1367 struct e1000_phy_info
*phy
= &hw
->phy
;
1372 ret_val
= e1e_rphy(hw
, MII_BMCR
, &data
);
1376 e1000e_phy_force_speed_duplex_setup(hw
, &data
);
1378 ret_val
= e1e_wphy(hw
, MII_BMCR
, data
);
1382 /* Disable MDI-X support for 10/100 */
1383 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, &data
);
1387 data
&= ~IFE_PMC_AUTO_MDIX
;
1388 data
&= ~IFE_PMC_FORCE_MDIX
;
1390 ret_val
= e1e_wphy(hw
, IFE_PHY_MDIX_CONTROL
, data
);
1394 e_dbg("IFE PMC: %X\n", data
);
1398 if (phy
->autoneg_wait_to_complete
) {
1399 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1401 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1407 e_dbg("Link taking longer than expected.\n");
1410 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1420 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1421 * @hw: pointer to the HW structure
1422 * @phy_ctrl: pointer to current value of MII_BMCR
1424 * Forces speed and duplex on the PHY by doing the following: disable flow
1425 * control, force speed/duplex on the MAC, disable auto speed detection,
1426 * disable auto-negotiation, configure duplex, configure speed, configure
1427 * the collision distance, write configuration to CTRL register. The
1428 * caller must write to the MII_BMCR register for these settings to
1431 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw
*hw
, u16
*phy_ctrl
)
1433 struct e1000_mac_info
*mac
= &hw
->mac
;
1436 /* Turn off flow control when forcing speed/duplex */
1437 hw
->fc
.current_mode
= e1000_fc_none
;
1439 /* Force speed/duplex on the mac */
1441 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1442 ctrl
&= ~E1000_CTRL_SPD_SEL
;
1444 /* Disable Auto Speed Detection */
1445 ctrl
&= ~E1000_CTRL_ASDE
;
1447 /* Disable autoneg on the phy */
1448 *phy_ctrl
&= ~BMCR_ANENABLE
;
1450 /* Forcing Full or Half Duplex? */
1451 if (mac
->forced_speed_duplex
& E1000_ALL_HALF_DUPLEX
) {
1452 ctrl
&= ~E1000_CTRL_FD
;
1453 *phy_ctrl
&= ~BMCR_FULLDPLX
;
1454 e_dbg("Half Duplex\n");
1456 ctrl
|= E1000_CTRL_FD
;
1457 *phy_ctrl
|= BMCR_FULLDPLX
;
1458 e_dbg("Full Duplex\n");
1461 /* Forcing 10mb or 100mb? */
1462 if (mac
->forced_speed_duplex
& E1000_ALL_100_SPEED
) {
1463 ctrl
|= E1000_CTRL_SPD_100
;
1464 *phy_ctrl
|= BMCR_SPEED100
;
1465 *phy_ctrl
&= ~BMCR_SPEED1000
;
1466 e_dbg("Forcing 100mb\n");
1468 ctrl
&= ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
1469 *phy_ctrl
&= ~(BMCR_SPEED1000
| BMCR_SPEED100
);
1470 e_dbg("Forcing 10mb\n");
1473 hw
->mac
.ops
.config_collision_dist(hw
);
1479 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1480 * @hw: pointer to the HW structure
1481 * @active: boolean used to enable/disable lplu
1483 * Success returns 0, Failure returns 1
1485 * The low power link up (lplu) state is set to the power management level D3
1486 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1487 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1488 * is used during Dx states where the power conservation is most important.
1489 * During driver activity, SmartSpeed should be enabled so performance is
1492 s32
e1000e_set_d3_lplu_state(struct e1000_hw
*hw
, bool active
)
1494 struct e1000_phy_info
*phy
= &hw
->phy
;
1498 ret_val
= e1e_rphy(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
1503 data
&= ~IGP02E1000_PM_D3_LPLU
;
1504 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
1507 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1508 * during Dx states where the power conservation is most
1509 * important. During driver activity we should enable
1510 * SmartSpeed, so performance is maintained.
1512 if (phy
->smart_speed
== e1000_smart_speed_on
) {
1513 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1518 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
1519 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1523 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
1524 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1529 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1530 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1535 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
1536 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
1537 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
1538 data
|= IGP02E1000_PM_D3_LPLU
;
1539 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
1543 /* When LPLU is enabled, we should disable SmartSpeed */
1544 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
1548 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1549 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
1556 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1557 * @hw: pointer to the HW structure
1559 * Success returns 0, Failure returns 1
1561 * A downshift is detected by querying the PHY link health.
1563 s32
e1000e_check_downshift(struct e1000_hw
*hw
)
1565 struct e1000_phy_info
*phy
= &hw
->phy
;
1567 u16 phy_data
, offset
, mask
;
1569 switch (phy
->type
) {
1571 case e1000_phy_gg82563
:
1573 case e1000_phy_82578
:
1574 offset
= M88E1000_PHY_SPEC_STATUS
;
1575 mask
= M88E1000_PSSR_DOWNSHIFT
;
1577 case e1000_phy_igp_2
:
1578 case e1000_phy_igp_3
:
1579 offset
= IGP01E1000_PHY_LINK_HEALTH
;
1580 mask
= IGP01E1000_PLHR_SS_DOWNGRADE
;
1583 /* speed downshift not supported */
1584 phy
->speed_downgraded
= false;
1588 ret_val
= e1e_rphy(hw
, offset
, &phy_data
);
1591 phy
->speed_downgraded
= !!(phy_data
& mask
);
1597 * e1000_check_polarity_m88 - Checks the polarity.
1598 * @hw: pointer to the HW structure
1600 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1602 * Polarity is determined based on the PHY specific status register.
1604 s32
e1000_check_polarity_m88(struct e1000_hw
*hw
)
1606 struct e1000_phy_info
*phy
= &hw
->phy
;
1610 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_STATUS
, &data
);
1613 phy
->cable_polarity
= ((data
& M88E1000_PSSR_REV_POLARITY
)
1614 ? e1000_rev_polarity_reversed
1615 : e1000_rev_polarity_normal
);
1621 * e1000_check_polarity_igp - Checks the polarity.
1622 * @hw: pointer to the HW structure
1624 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1626 * Polarity is determined based on the PHY port status register, and the
1627 * current speed (since there is no polarity at 100Mbps).
1629 s32
e1000_check_polarity_igp(struct e1000_hw
*hw
)
1631 struct e1000_phy_info
*phy
= &hw
->phy
;
1633 u16 data
, offset
, mask
;
1635 /* Polarity is determined based on the speed of
1638 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_STATUS
, &data
);
1642 if ((data
& IGP01E1000_PSSR_SPEED_MASK
) ==
1643 IGP01E1000_PSSR_SPEED_1000MBPS
) {
1644 offset
= IGP01E1000_PHY_PCS_INIT_REG
;
1645 mask
= IGP01E1000_PHY_POLARITY_MASK
;
1647 /* This really only applies to 10Mbps since
1648 * there is no polarity for 100Mbps (always 0).
1650 offset
= IGP01E1000_PHY_PORT_STATUS
;
1651 mask
= IGP01E1000_PSSR_POLARITY_REVERSED
;
1654 ret_val
= e1e_rphy(hw
, offset
, &data
);
1657 phy
->cable_polarity
= ((data
& mask
)
1658 ? e1000_rev_polarity_reversed
1659 : e1000_rev_polarity_normal
);
1665 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1666 * @hw: pointer to the HW structure
1668 * Polarity is determined on the polarity reversal feature being enabled.
1670 s32
e1000_check_polarity_ife(struct e1000_hw
*hw
)
1672 struct e1000_phy_info
*phy
= &hw
->phy
;
1674 u16 phy_data
, offset
, mask
;
1676 /* Polarity is determined based on the reversal feature being enabled.
1678 if (phy
->polarity_correction
) {
1679 offset
= IFE_PHY_EXTENDED_STATUS_CONTROL
;
1680 mask
= IFE_PESC_POLARITY_REVERSED
;
1682 offset
= IFE_PHY_SPECIAL_CONTROL
;
1683 mask
= IFE_PSC_FORCE_POLARITY
;
1686 ret_val
= e1e_rphy(hw
, offset
, &phy_data
);
1689 phy
->cable_polarity
= ((phy_data
& mask
)
1690 ? e1000_rev_polarity_reversed
1691 : e1000_rev_polarity_normal
);
1697 * e1000_wait_autoneg - Wait for auto-neg completion
1698 * @hw: pointer to the HW structure
1700 * Waits for auto-negotiation to complete or for the auto-negotiation time
1701 * limit to expire, which ever happens first.
1703 static s32
e1000_wait_autoneg(struct e1000_hw
*hw
)
1708 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1709 for (i
= PHY_AUTO_NEG_LIMIT
; i
> 0; i
--) {
1710 ret_val
= e1e_rphy(hw
, MII_BMSR
, &phy_status
);
1713 ret_val
= e1e_rphy(hw
, MII_BMSR
, &phy_status
);
1716 if (phy_status
& BMSR_ANEGCOMPLETE
)
1721 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1728 * e1000e_phy_has_link_generic - Polls PHY for link
1729 * @hw: pointer to the HW structure
1730 * @iterations: number of times to poll for link
1731 * @usec_interval: delay between polling attempts
1732 * @success: pointer to whether polling was successful or not
1734 * Polls the PHY status register for link, 'iterations' number of times.
1736 s32
e1000e_phy_has_link_generic(struct e1000_hw
*hw
, u32 iterations
,
1737 u32 usec_interval
, bool *success
)
1742 for (i
= 0; i
< iterations
; i
++) {
1743 /* Some PHYs require the MII_BMSR register to be read
1744 * twice due to the link bit being sticky. No harm doing
1745 * it across the board.
1747 ret_val
= e1e_rphy(hw
, MII_BMSR
, &phy_status
);
1749 /* If the first read fails, another entity may have
1750 * ownership of the resources, wait and try again to
1751 * see if they have relinquished the resources yet.
1753 udelay(usec_interval
);
1754 ret_val
= e1e_rphy(hw
, MII_BMSR
, &phy_status
);
1757 if (phy_status
& BMSR_LSTATUS
)
1759 if (usec_interval
>= 1000)
1760 mdelay(usec_interval
/ 1000);
1762 udelay(usec_interval
);
1765 *success
= (i
< iterations
);
1771 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1772 * @hw: pointer to the HW structure
1774 * Reads the PHY specific status register to retrieve the cable length
1775 * information. The cable length is determined by averaging the minimum and
1776 * maximum values to get the "average" cable length. The m88 PHY has four
1777 * possible cable length values, which are:
1778 * Register Value Cable Length
1782 * 3 110 - 140 meters
1785 s32
e1000e_get_cable_length_m88(struct e1000_hw
*hw
)
1787 struct e1000_phy_info
*phy
= &hw
->phy
;
1789 u16 phy_data
, index
;
1791 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
1795 index
= ((phy_data
& M88E1000_PSSR_CABLE_LENGTH
) >>
1796 M88E1000_PSSR_CABLE_LENGTH_SHIFT
);
1798 if (index
>= M88E1000_CABLE_LENGTH_TABLE_SIZE
- 1)
1799 return -E1000_ERR_PHY
;
1801 phy
->min_cable_length
= e1000_m88_cable_length_table
[index
];
1802 phy
->max_cable_length
= e1000_m88_cable_length_table
[index
+ 1];
1804 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
1810 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1811 * @hw: pointer to the HW structure
1813 * The automatic gain control (agc) normalizes the amplitude of the
1814 * received signal, adjusting for the attenuation produced by the
1815 * cable. By reading the AGC registers, which represent the
1816 * combination of coarse and fine gain value, the value can be put
1817 * into a lookup table to obtain the approximate cable length
1820 s32
e1000e_get_cable_length_igp_2(struct e1000_hw
*hw
)
1822 struct e1000_phy_info
*phy
= &hw
->phy
;
1824 u16 phy_data
, i
, agc_value
= 0;
1825 u16 cur_agc_index
, max_agc_index
= 0;
1826 u16 min_agc_index
= IGP02E1000_CABLE_LENGTH_TABLE_SIZE
- 1;
1827 static const u16 agc_reg_array
[IGP02E1000_PHY_CHANNEL_NUM
] = {
1828 IGP02E1000_PHY_AGC_A
,
1829 IGP02E1000_PHY_AGC_B
,
1830 IGP02E1000_PHY_AGC_C
,
1831 IGP02E1000_PHY_AGC_D
1834 /* Read the AGC registers for all channels */
1835 for (i
= 0; i
< IGP02E1000_PHY_CHANNEL_NUM
; i
++) {
1836 ret_val
= e1e_rphy(hw
, agc_reg_array
[i
], &phy_data
);
1840 /* Getting bits 15:9, which represent the combination of
1841 * coarse and fine gain values. The result is a number
1842 * that can be put into the lookup table to obtain the
1843 * approximate cable length.
1845 cur_agc_index
= ((phy_data
>> IGP02E1000_AGC_LENGTH_SHIFT
) &
1846 IGP02E1000_AGC_LENGTH_MASK
);
1848 /* Array index bound check. */
1849 if ((cur_agc_index
>= IGP02E1000_CABLE_LENGTH_TABLE_SIZE
) ||
1850 (cur_agc_index
== 0))
1851 return -E1000_ERR_PHY
;
1853 /* Remove min & max AGC values from calculation. */
1854 if (e1000_igp_2_cable_length_table
[min_agc_index
] >
1855 e1000_igp_2_cable_length_table
[cur_agc_index
])
1856 min_agc_index
= cur_agc_index
;
1857 if (e1000_igp_2_cable_length_table
[max_agc_index
] <
1858 e1000_igp_2_cable_length_table
[cur_agc_index
])
1859 max_agc_index
= cur_agc_index
;
1861 agc_value
+= e1000_igp_2_cable_length_table
[cur_agc_index
];
1864 agc_value
-= (e1000_igp_2_cable_length_table
[min_agc_index
] +
1865 e1000_igp_2_cable_length_table
[max_agc_index
]);
1866 agc_value
/= (IGP02E1000_PHY_CHANNEL_NUM
- 2);
1868 /* Calculate cable length with the error range of +/- 10 meters. */
1869 phy
->min_cable_length
= (((agc_value
- IGP02E1000_AGC_RANGE
) > 0) ?
1870 (agc_value
- IGP02E1000_AGC_RANGE
) : 0);
1871 phy
->max_cable_length
= agc_value
+ IGP02E1000_AGC_RANGE
;
1873 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
1879 * e1000e_get_phy_info_m88 - Retrieve PHY information
1880 * @hw: pointer to the HW structure
1882 * Valid for only copper links. Read the PHY status register (sticky read)
1883 * to verify that link is up. Read the PHY special control register to
1884 * determine the polarity and 10base-T extended distance. Read the PHY
1885 * special status register to determine MDI/MDIx and current speed. If
1886 * speed is 1000, then determine cable length, local and remote receiver.
1888 s32
e1000e_get_phy_info_m88(struct e1000_hw
*hw
)
1890 struct e1000_phy_info
*phy
= &hw
->phy
;
1895 if (phy
->media_type
!= e1000_media_type_copper
) {
1896 e_dbg("Phy info is only valid for copper media\n");
1897 return -E1000_ERR_CONFIG
;
1900 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
1905 e_dbg("Phy info is only valid if link is up\n");
1906 return -E1000_ERR_CONFIG
;
1909 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1913 phy
->polarity_correction
= !!(phy_data
&
1914 M88E1000_PSCR_POLARITY_REVERSAL
);
1916 ret_val
= e1000_check_polarity_m88(hw
);
1920 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
1924 phy
->is_mdix
= !!(phy_data
& M88E1000_PSSR_MDIX
);
1926 if ((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
) {
1927 ret_val
= hw
->phy
.ops
.get_cable_length(hw
);
1931 ret_val
= e1e_rphy(hw
, MII_STAT1000
, &phy_data
);
1935 phy
->local_rx
= (phy_data
& LPA_1000LOCALRXOK
)
1936 ? e1000_1000t_rx_status_ok
: e1000_1000t_rx_status_not_ok
;
1938 phy
->remote_rx
= (phy_data
& LPA_1000REMRXOK
)
1939 ? e1000_1000t_rx_status_ok
: e1000_1000t_rx_status_not_ok
;
1941 /* Set values to "undefined" */
1942 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
1943 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
1944 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
1951 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1952 * @hw: pointer to the HW structure
1954 * Read PHY status to determine if link is up. If link is up, then
1955 * set/determine 10base-T extended distance and polarity correction. Read
1956 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1957 * determine on the cable length, local and remote receiver.
1959 s32
e1000e_get_phy_info_igp(struct e1000_hw
*hw
)
1961 struct e1000_phy_info
*phy
= &hw
->phy
;
1966 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
1971 e_dbg("Phy info is only valid if link is up\n");
1972 return -E1000_ERR_CONFIG
;
1975 phy
->polarity_correction
= true;
1977 ret_val
= e1000_check_polarity_igp(hw
);
1981 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_STATUS
, &data
);
1985 phy
->is_mdix
= !!(data
& IGP01E1000_PSSR_MDIX
);
1987 if ((data
& IGP01E1000_PSSR_SPEED_MASK
) ==
1988 IGP01E1000_PSSR_SPEED_1000MBPS
) {
1989 ret_val
= phy
->ops
.get_cable_length(hw
);
1993 ret_val
= e1e_rphy(hw
, MII_STAT1000
, &data
);
1997 phy
->local_rx
= (data
& LPA_1000LOCALRXOK
)
1998 ? e1000_1000t_rx_status_ok
: e1000_1000t_rx_status_not_ok
;
2000 phy
->remote_rx
= (data
& LPA_1000REMRXOK
)
2001 ? e1000_1000t_rx_status_ok
: e1000_1000t_rx_status_not_ok
;
2003 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
2004 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
2005 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
2012 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2013 * @hw: pointer to the HW structure
2015 * Populates "phy" structure with various feature states.
2017 s32
e1000_get_phy_info_ife(struct e1000_hw
*hw
)
2019 struct e1000_phy_info
*phy
= &hw
->phy
;
2024 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
2029 e_dbg("Phy info is only valid if link is up\n");
2030 return -E1000_ERR_CONFIG
;
2033 ret_val
= e1e_rphy(hw
, IFE_PHY_SPECIAL_CONTROL
, &data
);
2036 phy
->polarity_correction
= !(data
& IFE_PSC_AUTO_POLARITY_DISABLE
);
2038 if (phy
->polarity_correction
) {
2039 ret_val
= e1000_check_polarity_ife(hw
);
2043 /* Polarity is forced */
2044 phy
->cable_polarity
= ((data
& IFE_PSC_FORCE_POLARITY
)
2045 ? e1000_rev_polarity_reversed
2046 : e1000_rev_polarity_normal
);
2049 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, &data
);
2053 phy
->is_mdix
= !!(data
& IFE_PMC_MDIX_STATUS
);
2055 /* The following parameters are undefined for 10/100 operation. */
2056 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
2057 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
2058 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
2064 * e1000e_phy_sw_reset - PHY software reset
2065 * @hw: pointer to the HW structure
2067 * Does a software reset of the PHY by reading the PHY control register and
2068 * setting/write the control register reset bit to the PHY.
2070 s32
e1000e_phy_sw_reset(struct e1000_hw
*hw
)
2075 ret_val
= e1e_rphy(hw
, MII_BMCR
, &phy_ctrl
);
2079 phy_ctrl
|= BMCR_RESET
;
2080 ret_val
= e1e_wphy(hw
, MII_BMCR
, phy_ctrl
);
2090 * e1000e_phy_hw_reset_generic - PHY hardware reset
2091 * @hw: pointer to the HW structure
2093 * Verify the reset block is not blocking us from resetting. Acquire
2094 * semaphore (if necessary) and read/set/write the device control reset
2095 * bit in the PHY. Wait the appropriate delay time for the device to
2096 * reset and release the semaphore (if necessary).
2098 s32
e1000e_phy_hw_reset_generic(struct e1000_hw
*hw
)
2100 struct e1000_phy_info
*phy
= &hw
->phy
;
2104 if (phy
->ops
.check_reset_block
) {
2105 ret_val
= phy
->ops
.check_reset_block(hw
);
2110 ret_val
= phy
->ops
.acquire(hw
);
2115 ew32(CTRL
, ctrl
| E1000_CTRL_PHY_RST
);
2118 udelay(phy
->reset_delay_us
);
2125 phy
->ops
.release(hw
);
2127 return phy
->ops
.get_cfg_done(hw
);
2131 * e1000e_get_cfg_done_generic - Generic configuration done
2132 * @hw: pointer to the HW structure
2134 * Generic function to wait 10 milli-seconds for configuration to complete
2135 * and return success.
2137 s32
e1000e_get_cfg_done_generic(struct e1000_hw __always_unused
*hw
)
2145 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2146 * @hw: pointer to the HW structure
2148 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2150 s32
e1000e_phy_init_script_igp3(struct e1000_hw
*hw
)
2152 e_dbg("Running IGP 3 PHY init script\n");
2154 /* PHY init IGP 3 */
2155 /* Enable rise/fall, 10-mode work in class-A */
2156 e1e_wphy(hw
, 0x2F5B, 0x9018);
2157 /* Remove all caps from Replica path filter */
2158 e1e_wphy(hw
, 0x2F52, 0x0000);
2159 /* Bias trimming for ADC, AFE and Driver (Default) */
2160 e1e_wphy(hw
, 0x2FB1, 0x8B24);
2161 /* Increase Hybrid poly bias */
2162 e1e_wphy(hw
, 0x2FB2, 0xF8F0);
2163 /* Add 4% to Tx amplitude in Gig mode */
2164 e1e_wphy(hw
, 0x2010, 0x10B0);
2165 /* Disable trimming (TTT) */
2166 e1e_wphy(hw
, 0x2011, 0x0000);
2167 /* Poly DC correction to 94.6% + 2% for all channels */
2168 e1e_wphy(hw
, 0x20DD, 0x249A);
2169 /* ABS DC correction to 95.9% */
2170 e1e_wphy(hw
, 0x20DE, 0x00D3);
2171 /* BG temp curve trim */
2172 e1e_wphy(hw
, 0x28B4, 0x04CE);
2173 /* Increasing ADC OPAMP stage 1 currents to max */
2174 e1e_wphy(hw
, 0x2F70, 0x29E4);
2175 /* Force 1000 ( required for enabling PHY regs configuration) */
2176 e1e_wphy(hw
, 0x0000, 0x0140);
2177 /* Set upd_freq to 6 */
2178 e1e_wphy(hw
, 0x1F30, 0x1606);
2180 e1e_wphy(hw
, 0x1F31, 0xB814);
2181 /* Disable adaptive fixed FFE (Default) */
2182 e1e_wphy(hw
, 0x1F35, 0x002A);
2183 /* Enable FFE hysteresis */
2184 e1e_wphy(hw
, 0x1F3E, 0x0067);
2185 /* Fixed FFE for short cable lengths */
2186 e1e_wphy(hw
, 0x1F54, 0x0065);
2187 /* Fixed FFE for medium cable lengths */
2188 e1e_wphy(hw
, 0x1F55, 0x002A);
2189 /* Fixed FFE for long cable lengths */
2190 e1e_wphy(hw
, 0x1F56, 0x002A);
2191 /* Enable Adaptive Clip Threshold */
2192 e1e_wphy(hw
, 0x1F72, 0x3FB0);
2193 /* AHT reset limit to 1 */
2194 e1e_wphy(hw
, 0x1F76, 0xC0FF);
2195 /* Set AHT master delay to 127 msec */
2196 e1e_wphy(hw
, 0x1F77, 0x1DEC);
2197 /* Set scan bits for AHT */
2198 e1e_wphy(hw
, 0x1F78, 0xF9EF);
2199 /* Set AHT Preset bits */
2200 e1e_wphy(hw
, 0x1F79, 0x0210);
2201 /* Change integ_factor of channel A to 3 */
2202 e1e_wphy(hw
, 0x1895, 0x0003);
2203 /* Change prop_factor of channels BCD to 8 */
2204 e1e_wphy(hw
, 0x1796, 0x0008);
2205 /* Change cg_icount + enable integbp for channels BCD */
2206 e1e_wphy(hw
, 0x1798, 0xD008);
2207 /* Change cg_icount + enable integbp + change prop_factor_master
2208 * to 8 for channel A
2210 e1e_wphy(hw
, 0x1898, 0xD918);
2211 /* Disable AHT in Slave mode on channel A */
2212 e1e_wphy(hw
, 0x187A, 0x0800);
2213 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2216 e1e_wphy(hw
, 0x0019, 0x008D);
2217 /* Enable restart AN on an1000_dis change */
2218 e1e_wphy(hw
, 0x001B, 0x2080);
2219 /* Enable wh_fifo read clock in 10/100 modes */
2220 e1e_wphy(hw
, 0x0014, 0x0045);
2221 /* Restart AN, Speed selection is 1000 */
2222 e1e_wphy(hw
, 0x0000, 0x1340);
2228 * e1000e_get_phy_type_from_id - Get PHY type from id
2229 * @phy_id: phy_id read from the phy
2231 * Returns the phy type from the id.
2233 enum e1000_phy_type
e1000e_get_phy_type_from_id(u32 phy_id
)
2235 enum e1000_phy_type phy_type
= e1000_phy_unknown
;
2238 case M88E1000_I_PHY_ID
:
2239 case M88E1000_E_PHY_ID
:
2240 case M88E1111_I_PHY_ID
:
2241 case M88E1011_I_PHY_ID
:
2242 phy_type
= e1000_phy_m88
;
2244 case IGP01E1000_I_PHY_ID
: /* IGP 1 & 2 share this */
2245 phy_type
= e1000_phy_igp_2
;
2247 case GG82563_E_PHY_ID
:
2248 phy_type
= e1000_phy_gg82563
;
2250 case IGP03E1000_E_PHY_ID
:
2251 phy_type
= e1000_phy_igp_3
;
2254 case IFE_PLUS_E_PHY_ID
:
2255 case IFE_C_E_PHY_ID
:
2256 phy_type
= e1000_phy_ife
;
2258 case BME1000_E_PHY_ID
:
2259 case BME1000_E_PHY_ID_R2
:
2260 phy_type
= e1000_phy_bm
;
2262 case I82578_E_PHY_ID
:
2263 phy_type
= e1000_phy_82578
;
2265 case I82577_E_PHY_ID
:
2266 phy_type
= e1000_phy_82577
;
2268 case I82579_E_PHY_ID
:
2269 phy_type
= e1000_phy_82579
;
2272 phy_type
= e1000_phy_i217
;
2275 phy_type
= e1000_phy_unknown
;
2282 * e1000e_determine_phy_address - Determines PHY address.
2283 * @hw: pointer to the HW structure
2285 * This uses a trial and error method to loop through possible PHY
2286 * addresses. It tests each by reading the PHY ID registers and
2287 * checking for a match.
2289 s32
e1000e_determine_phy_address(struct e1000_hw
*hw
)
2293 enum e1000_phy_type phy_type
= e1000_phy_unknown
;
2295 hw
->phy
.id
= phy_type
;
2297 for (phy_addr
= 0; phy_addr
< E1000_MAX_PHY_ADDR
; phy_addr
++) {
2298 hw
->phy
.addr
= phy_addr
;
2302 e1000e_get_phy_id(hw
);
2303 phy_type
= e1000e_get_phy_type_from_id(hw
->phy
.id
);
2305 /* If phy_type is valid, break - we found our
2308 if (phy_type
!= e1000_phy_unknown
)
2311 usleep_range(1000, 2000);
2316 return -E1000_ERR_PHY_TYPE
;
2320 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2321 * @page: page to access
2323 * Returns the phy address for the page requested.
2325 static u32
e1000_get_phy_addr_for_bm_page(u32 page
, u32 reg
)
2329 if ((page
>= 768) || (page
== 0 && reg
== 25) || (reg
== 31))
2336 * e1000e_write_phy_reg_bm - Write BM PHY register
2337 * @hw: pointer to the HW structure
2338 * @offset: register offset to write to
2339 * @data: data to write at register offset
2341 * Acquires semaphore, if necessary, then writes the data to PHY register
2342 * at the offset. Release any acquired semaphores before exiting.
2344 s32
e1000e_write_phy_reg_bm(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2347 u32 page
= offset
>> IGP_PAGE_SHIFT
;
2349 ret_val
= hw
->phy
.ops
.acquire(hw
);
2353 /* Page 800 works differently than the rest so it has its own func */
2354 if (page
== BM_WUC_PAGE
) {
2355 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, &data
,
2360 hw
->phy
.addr
= e1000_get_phy_addr_for_bm_page(page
, offset
);
2362 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2363 u32 page_shift
, page_select
;
2365 /* Page select is register 31 for phy address 1 and 22 for
2366 * phy address 2 and 3. Page select is shifted only for
2369 if (hw
->phy
.addr
== 1) {
2370 page_shift
= IGP_PAGE_SHIFT
;
2371 page_select
= IGP01E1000_PHY_PAGE_SELECT
;
2374 page_select
= BM_PHY_PAGE_SELECT
;
2377 /* Page is shifted left, PHY expects (page x 32) */
2378 ret_val
= e1000e_write_phy_reg_mdic(hw
, page_select
,
2379 (page
<< page_shift
));
2384 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2388 hw
->phy
.ops
.release(hw
);
2393 * e1000e_read_phy_reg_bm - Read BM PHY register
2394 * @hw: pointer to the HW structure
2395 * @offset: register offset to be read
2396 * @data: pointer to the read data
2398 * Acquires semaphore, if necessary, then reads the PHY register at offset
2399 * and storing the retrieved information in data. Release any acquired
2400 * semaphores before exiting.
2402 s32
e1000e_read_phy_reg_bm(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2405 u32 page
= offset
>> IGP_PAGE_SHIFT
;
2407 ret_val
= hw
->phy
.ops
.acquire(hw
);
2411 /* Page 800 works differently than the rest so it has its own func */
2412 if (page
== BM_WUC_PAGE
) {
2413 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, data
,
2418 hw
->phy
.addr
= e1000_get_phy_addr_for_bm_page(page
, offset
);
2420 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2421 u32 page_shift
, page_select
;
2423 /* Page select is register 31 for phy address 1 and 22 for
2424 * phy address 2 and 3. Page select is shifted only for
2427 if (hw
->phy
.addr
== 1) {
2428 page_shift
= IGP_PAGE_SHIFT
;
2429 page_select
= IGP01E1000_PHY_PAGE_SELECT
;
2432 page_select
= BM_PHY_PAGE_SELECT
;
2435 /* Page is shifted left, PHY expects (page x 32) */
2436 ret_val
= e1000e_write_phy_reg_mdic(hw
, page_select
,
2437 (page
<< page_shift
));
2442 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2445 hw
->phy
.ops
.release(hw
);
2450 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2451 * @hw: pointer to the HW structure
2452 * @offset: register offset to be read
2453 * @data: pointer to the read data
2455 * Acquires semaphore, if necessary, then reads the PHY register at offset
2456 * and storing the retrieved information in data. Release any acquired
2457 * semaphores before exiting.
2459 s32
e1000e_read_phy_reg_bm2(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2462 u16 page
= (u16
)(offset
>> IGP_PAGE_SHIFT
);
2464 ret_val
= hw
->phy
.ops
.acquire(hw
);
2468 /* Page 800 works differently than the rest so it has its own func */
2469 if (page
== BM_WUC_PAGE
) {
2470 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, data
,
2477 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2478 /* Page is shifted left, PHY expects (page x 32) */
2479 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_PHY_PAGE_SELECT
,
2486 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2489 hw
->phy
.ops
.release(hw
);
2494 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2495 * @hw: pointer to the HW structure
2496 * @offset: register offset to write to
2497 * @data: data to write at register offset
2499 * Acquires semaphore, if necessary, then writes the data to PHY register
2500 * at the offset. Release any acquired semaphores before exiting.
2502 s32
e1000e_write_phy_reg_bm2(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2505 u16 page
= (u16
)(offset
>> IGP_PAGE_SHIFT
);
2507 ret_val
= hw
->phy
.ops
.acquire(hw
);
2511 /* Page 800 works differently than the rest so it has its own func */
2512 if (page
== BM_WUC_PAGE
) {
2513 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, &data
,
2520 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2521 /* Page is shifted left, PHY expects (page x 32) */
2522 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_PHY_PAGE_SELECT
,
2529 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2533 hw
->phy
.ops
.release(hw
);
2538 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2539 * @hw: pointer to the HW structure
2540 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2542 * Assumes semaphore already acquired and phy_reg points to a valid memory
2543 * address to store contents of the BM_WUC_ENABLE_REG register.
2545 s32
e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw
*hw
, u16
*phy_reg
)
2550 /* All page select, port ctrl and wakeup registers use phy address 1 */
2553 /* Select Port Control Registers page */
2554 ret_val
= e1000_set_page_igp(hw
, (BM_PORT_CTRL_PAGE
<< IGP_PAGE_SHIFT
));
2556 e_dbg("Could not set Port Control page\n");
2560 ret_val
= e1000e_read_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
, phy_reg
);
2562 e_dbg("Could not read PHY register %d.%d\n",
2563 BM_PORT_CTRL_PAGE
, BM_WUC_ENABLE_REG
);
2567 /* Enable both PHY wakeup mode and Wakeup register page writes.
2568 * Prevent a power state change by disabling ME and Host PHY wakeup.
2571 temp
|= BM_WUC_ENABLE_BIT
;
2572 temp
&= ~(BM_WUC_ME_WU_BIT
| BM_WUC_HOST_WU_BIT
);
2574 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
, temp
);
2576 e_dbg("Could not write PHY register %d.%d\n",
2577 BM_PORT_CTRL_PAGE
, BM_WUC_ENABLE_REG
);
2581 /* Select Host Wakeup Registers page - caller now able to write
2582 * registers on the Wakeup registers page
2584 return e1000_set_page_igp(hw
, (BM_WUC_PAGE
<< IGP_PAGE_SHIFT
));
2588 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2589 * @hw: pointer to the HW structure
2590 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2592 * Restore BM_WUC_ENABLE_REG to its original value.
2594 * Assumes semaphore already acquired and *phy_reg is the contents of the
2595 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2598 s32
e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw
*hw
, u16
*phy_reg
)
2602 /* Select Port Control Registers page */
2603 ret_val
= e1000_set_page_igp(hw
, (BM_PORT_CTRL_PAGE
<< IGP_PAGE_SHIFT
));
2605 e_dbg("Could not set Port Control page\n");
2609 /* Restore 769.17 to its original value */
2610 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
, *phy_reg
);
2612 e_dbg("Could not restore PHY register %d.%d\n",
2613 BM_PORT_CTRL_PAGE
, BM_WUC_ENABLE_REG
);
2619 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2620 * @hw: pointer to the HW structure
2621 * @offset: register offset to be read or written
2622 * @data: pointer to the data to read or write
2623 * @read: determines if operation is read or write
2624 * @page_set: BM_WUC_PAGE already set and access enabled
2626 * Read the PHY register at offset and store the retrieved information in
2627 * data, or write data to PHY register at offset. Note the procedure to
2628 * access the PHY wakeup registers is different than reading the other PHY
2629 * registers. It works as such:
2630 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2631 * 2) Set page to 800 for host (801 if we were manageability)
2632 * 3) Write the address using the address opcode (0x11)
2633 * 4) Read or write the data using the data opcode (0x12)
2634 * 5) Restore 769.17.2 to its original value
2636 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2637 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2639 * Assumes semaphore is already acquired. When page_set==true, assumes
2640 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2641 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2643 static s32
e1000_access_phy_wakeup_reg_bm(struct e1000_hw
*hw
, u32 offset
,
2644 u16
*data
, bool read
, bool page_set
)
2647 u16 reg
= BM_PHY_REG_NUM(offset
);
2648 u16 page
= BM_PHY_REG_PAGE(offset
);
2651 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2652 if ((hw
->mac
.type
== e1000_pchlan
) &&
2653 (!(er32(PHY_CTRL
) & E1000_PHY_CTRL_GBE_DISABLE
)))
2654 e_dbg("Attempting to access page %d while gig enabled.\n",
2658 /* Enable access to PHY wakeup registers */
2659 ret_val
= e1000_enable_phy_wakeup_reg_access_bm(hw
, &phy_reg
);
2661 e_dbg("Could not enable PHY wakeup reg access\n");
2666 e_dbg("Accessing PHY page %d reg 0x%x\n", page
, reg
);
2668 /* Write the Wakeup register page offset value using opcode 0x11 */
2669 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_ADDRESS_OPCODE
, reg
);
2671 e_dbg("Could not write address opcode to page %d\n", page
);
2676 /* Read the Wakeup register page value using opcode 0x12 */
2677 ret_val
= e1000e_read_phy_reg_mdic(hw
, BM_WUC_DATA_OPCODE
,
2680 /* Write the Wakeup register page value using opcode 0x12 */
2681 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_DATA_OPCODE
,
2686 e_dbg("Could not access PHY reg %d.%d\n", page
, reg
);
2691 ret_val
= e1000_disable_phy_wakeup_reg_access_bm(hw
, &phy_reg
);
2697 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2698 * @hw: pointer to the HW structure
2700 * In the case of a PHY power down to save power, or to turn off link during a
2701 * driver unload, or wake on lan is not enabled, restore the link to previous
2704 void e1000_power_up_phy_copper(struct e1000_hw
*hw
)
2708 /* The PHY will retain its settings across a power down/up cycle */
2709 e1e_rphy(hw
, MII_BMCR
, &mii_reg
);
2710 mii_reg
&= ~BMCR_PDOWN
;
2711 e1e_wphy(hw
, MII_BMCR
, mii_reg
);
2715 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2716 * @hw: pointer to the HW structure
2718 * In the case of a PHY power down to save power, or to turn off link during a
2719 * driver unload, or wake on lan is not enabled, restore the link to previous
2722 void e1000_power_down_phy_copper(struct e1000_hw
*hw
)
2726 /* The PHY will retain its settings across a power down/up cycle */
2727 e1e_rphy(hw
, MII_BMCR
, &mii_reg
);
2728 mii_reg
|= BMCR_PDOWN
;
2729 e1e_wphy(hw
, MII_BMCR
, mii_reg
);
2730 usleep_range(1000, 2000);
2734 * __e1000_read_phy_reg_hv - Read HV PHY register
2735 * @hw: pointer to the HW structure
2736 * @offset: register offset to be read
2737 * @data: pointer to the read data
2738 * @locked: semaphore has already been acquired or not
2740 * Acquires semaphore, if necessary, then reads the PHY register at offset
2741 * and stores the retrieved information in data. Release any acquired
2742 * semaphore before exiting.
2744 static s32
__e1000_read_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16
*data
,
2745 bool locked
, bool page_set
)
2748 u16 page
= BM_PHY_REG_PAGE(offset
);
2749 u16 reg
= BM_PHY_REG_NUM(offset
);
2750 u32 phy_addr
= hw
->phy
.addr
= e1000_get_phy_addr_for_hv_page(page
);
2753 ret_val
= hw
->phy
.ops
.acquire(hw
);
2758 /* Page 800 works differently than the rest so it has its own func */
2759 if (page
== BM_WUC_PAGE
) {
2760 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, data
,
2765 if (page
> 0 && page
< HV_INTC_FC_PAGE_START
) {
2766 ret_val
= e1000_access_phy_debug_regs_hv(hw
, offset
,
2772 if (page
== HV_INTC_FC_PAGE_START
)
2775 if (reg
> MAX_PHY_MULTI_PAGE_REG
) {
2776 /* Page is shifted left, PHY expects (page x 32) */
2777 ret_val
= e1000_set_page_igp(hw
,
2778 (page
<< IGP_PAGE_SHIFT
));
2780 hw
->phy
.addr
= phy_addr
;
2787 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page
,
2788 page
<< IGP_PAGE_SHIFT
, reg
);
2790 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& reg
, data
);
2793 hw
->phy
.ops
.release(hw
);
2799 * e1000_read_phy_reg_hv - Read HV PHY register
2800 * @hw: pointer to the HW structure
2801 * @offset: register offset to be read
2802 * @data: pointer to the read data
2804 * Acquires semaphore then reads the PHY register at offset and stores
2805 * the retrieved information in data. Release the acquired semaphore
2808 s32
e1000_read_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2810 return __e1000_read_phy_reg_hv(hw
, offset
, data
, false, false);
2814 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2815 * @hw: pointer to the HW structure
2816 * @offset: register offset to be read
2817 * @data: pointer to the read data
2819 * Reads the PHY register at offset and stores the retrieved information
2820 * in data. Assumes semaphore already acquired.
2822 s32
e1000_read_phy_reg_hv_locked(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2824 return __e1000_read_phy_reg_hv(hw
, offset
, data
, true, false);
2828 * e1000_read_phy_reg_page_hv - Read HV PHY register
2829 * @hw: pointer to the HW structure
2830 * @offset: register offset to write to
2831 * @data: data to write at register offset
2833 * Reads the PHY register at offset and stores the retrieved information
2834 * in data. Assumes semaphore already acquired and page already set.
2836 s32
e1000_read_phy_reg_page_hv(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2838 return __e1000_read_phy_reg_hv(hw
, offset
, data
, true, true);
2842 * __e1000_write_phy_reg_hv - Write HV PHY register
2843 * @hw: pointer to the HW structure
2844 * @offset: register offset to write to
2845 * @data: data to write at register offset
2846 * @locked: semaphore has already been acquired or not
2848 * Acquires semaphore, if necessary, then writes the data to PHY register
2849 * at the offset. Release any acquired semaphores before exiting.
2851 static s32
__e1000_write_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16 data
,
2852 bool locked
, bool page_set
)
2855 u16 page
= BM_PHY_REG_PAGE(offset
);
2856 u16 reg
= BM_PHY_REG_NUM(offset
);
2857 u32 phy_addr
= hw
->phy
.addr
= e1000_get_phy_addr_for_hv_page(page
);
2860 ret_val
= hw
->phy
.ops
.acquire(hw
);
2865 /* Page 800 works differently than the rest so it has its own func */
2866 if (page
== BM_WUC_PAGE
) {
2867 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, &data
,
2872 if (page
> 0 && page
< HV_INTC_FC_PAGE_START
) {
2873 ret_val
= e1000_access_phy_debug_regs_hv(hw
, offset
,
2879 if (page
== HV_INTC_FC_PAGE_START
)
2882 /* Workaround MDIO accesses being disabled after entering IEEE
2883 * Power Down (when bit 11 of the PHY Control register is set)
2885 if ((hw
->phy
.type
== e1000_phy_82578
) &&
2886 (hw
->phy
.revision
>= 1) &&
2887 (hw
->phy
.addr
== 2) &&
2888 !(MAX_PHY_REG_ADDRESS
& reg
) && (data
& (1 << 11))) {
2890 ret_val
= e1000_access_phy_debug_regs_hv(hw
,
2897 if (reg
> MAX_PHY_MULTI_PAGE_REG
) {
2898 /* Page is shifted left, PHY expects (page x 32) */
2899 ret_val
= e1000_set_page_igp(hw
,
2900 (page
<< IGP_PAGE_SHIFT
));
2902 hw
->phy
.addr
= phy_addr
;
2909 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page
,
2910 page
<< IGP_PAGE_SHIFT
, reg
);
2912 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& reg
,
2917 hw
->phy
.ops
.release(hw
);
2923 * e1000_write_phy_reg_hv - Write HV PHY register
2924 * @hw: pointer to the HW structure
2925 * @offset: register offset to write to
2926 * @data: data to write at register offset
2928 * Acquires semaphore then writes the data to PHY register at the offset.
2929 * Release the acquired semaphores before exiting.
2931 s32
e1000_write_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2933 return __e1000_write_phy_reg_hv(hw
, offset
, data
, false, false);
2937 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2938 * @hw: pointer to the HW structure
2939 * @offset: register offset to write to
2940 * @data: data to write at register offset
2942 * Writes the data to PHY register at the offset. Assumes semaphore
2945 s32
e1000_write_phy_reg_hv_locked(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2947 return __e1000_write_phy_reg_hv(hw
, offset
, data
, true, false);
2951 * e1000_write_phy_reg_page_hv - Write HV PHY register
2952 * @hw: pointer to the HW structure
2953 * @offset: register offset to write to
2954 * @data: data to write at register offset
2956 * Writes the data to PHY register at the offset. Assumes semaphore
2957 * already acquired and page already set.
2959 s32
e1000_write_phy_reg_page_hv(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2961 return __e1000_write_phy_reg_hv(hw
, offset
, data
, true, true);
2965 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
2966 * @page: page to be accessed
2968 static u32
e1000_get_phy_addr_for_hv_page(u32 page
)
2972 if (page
>= HV_INTC_FC_PAGE_START
)
2979 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
2980 * @hw: pointer to the HW structure
2981 * @offset: register offset to be read or written
2982 * @data: pointer to the data to be read or written
2983 * @read: determines if operation is read or write
2985 * Reads the PHY register at offset and stores the retreived information
2986 * in data. Assumes semaphore already acquired. Note that the procedure
2987 * to access these regs uses the address port and data port to read/write.
2988 * These accesses done with PHY address 2 and without using pages.
2990 static s32
e1000_access_phy_debug_regs_hv(struct e1000_hw
*hw
, u32 offset
,
2991 u16
*data
, bool read
)
2997 /* This takes care of the difference with desktop vs mobile phy */
2998 addr_reg
= ((hw
->phy
.type
== e1000_phy_82578
) ?
2999 I82578_ADDR_REG
: I82577_ADDR_REG
);
3000 data_reg
= addr_reg
+ 1;
3002 /* All operations in this function are phy address 2 */
3005 /* masking with 0x3F to remove the page from offset */
3006 ret_val
= e1000e_write_phy_reg_mdic(hw
, addr_reg
, (u16
)offset
& 0x3F);
3008 e_dbg("Could not write the Address Offset port register\n");
3012 /* Read or write the data value next */
3014 ret_val
= e1000e_read_phy_reg_mdic(hw
, data_reg
, data
);
3016 ret_val
= e1000e_write_phy_reg_mdic(hw
, data_reg
, *data
);
3019 e_dbg("Could not access the Data port register\n");
3025 * e1000_link_stall_workaround_hv - Si workaround
3026 * @hw: pointer to the HW structure
3028 * This function works around a Si bug where the link partner can get
3029 * a link up indication before the PHY does. If small packets are sent
3030 * by the link partner they can be placed in the packet buffer without
3031 * being properly accounted for by the PHY and will stall preventing
3032 * further packets from being received. The workaround is to clear the
3033 * packet buffer after the PHY detects link up.
3035 s32
e1000_link_stall_workaround_hv(struct e1000_hw
*hw
)
3040 if (hw
->phy
.type
!= e1000_phy_82578
)
3043 /* Do not apply workaround if in PHY loopback bit 14 set */
3044 e1e_rphy(hw
, MII_BMCR
, &data
);
3045 if (data
& BMCR_LOOPBACK
)
3048 /* check if link is up and at 1Gbps */
3049 ret_val
= e1e_rphy(hw
, BM_CS_STATUS
, &data
);
3053 data
&= (BM_CS_STATUS_LINK_UP
| BM_CS_STATUS_RESOLVED
|
3054 BM_CS_STATUS_SPEED_MASK
);
3056 if (data
!= (BM_CS_STATUS_LINK_UP
| BM_CS_STATUS_RESOLVED
|
3057 BM_CS_STATUS_SPEED_1000
))
3062 /* flush the packets in the fifo buffer */
3063 ret_val
= e1e_wphy(hw
, HV_MUX_DATA_CTRL
,
3064 (HV_MUX_DATA_CTRL_GEN_TO_MAC
|
3065 HV_MUX_DATA_CTRL_FORCE_SPEED
));
3069 return e1e_wphy(hw
, HV_MUX_DATA_CTRL
, HV_MUX_DATA_CTRL_GEN_TO_MAC
);
3073 * e1000_check_polarity_82577 - Checks the polarity.
3074 * @hw: pointer to the HW structure
3076 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3078 * Polarity is determined based on the PHY specific status register.
3080 s32
e1000_check_polarity_82577(struct e1000_hw
*hw
)
3082 struct e1000_phy_info
*phy
= &hw
->phy
;
3086 ret_val
= e1e_rphy(hw
, I82577_PHY_STATUS_2
, &data
);
3089 phy
->cable_polarity
= ((data
& I82577_PHY_STATUS2_REV_POLARITY
)
3090 ? e1000_rev_polarity_reversed
3091 : e1000_rev_polarity_normal
);
3097 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3098 * @hw: pointer to the HW structure
3100 * Calls the PHY setup function to force speed and duplex.
3102 s32
e1000_phy_force_speed_duplex_82577(struct e1000_hw
*hw
)
3104 struct e1000_phy_info
*phy
= &hw
->phy
;
3109 ret_val
= e1e_rphy(hw
, MII_BMCR
, &phy_data
);
3113 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
3115 ret_val
= e1e_wphy(hw
, MII_BMCR
, phy_data
);
3121 if (phy
->autoneg_wait_to_complete
) {
3122 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3124 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
3130 e_dbg("Link taking longer than expected.\n");
3133 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
3141 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3142 * @hw: pointer to the HW structure
3144 * Read PHY status to determine if link is up. If link is up, then
3145 * set/determine 10base-T extended distance and polarity correction. Read
3146 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3147 * determine on the cable length, local and remote receiver.
3149 s32
e1000_get_phy_info_82577(struct e1000_hw
*hw
)
3151 struct e1000_phy_info
*phy
= &hw
->phy
;
3156 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
3161 e_dbg("Phy info is only valid if link is up\n");
3162 return -E1000_ERR_CONFIG
;
3165 phy
->polarity_correction
= true;
3167 ret_val
= e1000_check_polarity_82577(hw
);
3171 ret_val
= e1e_rphy(hw
, I82577_PHY_STATUS_2
, &data
);
3175 phy
->is_mdix
= !!(data
& I82577_PHY_STATUS2_MDIX
);
3177 if ((data
& I82577_PHY_STATUS2_SPEED_MASK
) ==
3178 I82577_PHY_STATUS2_SPEED_1000MBPS
) {
3179 ret_val
= hw
->phy
.ops
.get_cable_length(hw
);
3183 ret_val
= e1e_rphy(hw
, MII_STAT1000
, &data
);
3187 phy
->local_rx
= (data
& LPA_1000LOCALRXOK
)
3188 ? e1000_1000t_rx_status_ok
: e1000_1000t_rx_status_not_ok
;
3190 phy
->remote_rx
= (data
& LPA_1000REMRXOK
)
3191 ? e1000_1000t_rx_status_ok
: e1000_1000t_rx_status_not_ok
;
3193 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
3194 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
3195 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
3202 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3203 * @hw: pointer to the HW structure
3205 * Reads the diagnostic status register and verifies result is valid before
3206 * placing it in the phy_cable_length field.
3208 s32
e1000_get_cable_length_82577(struct e1000_hw
*hw
)
3210 struct e1000_phy_info
*phy
= &hw
->phy
;
3212 u16 phy_data
, length
;
3214 ret_val
= e1e_rphy(hw
, I82577_PHY_DIAG_STATUS
, &phy_data
);
3218 length
= ((phy_data
& I82577_DSTATUS_CABLE_LENGTH
) >>
3219 I82577_DSTATUS_CABLE_LENGTH_SHIFT
);
3221 if (length
== E1000_CABLE_LENGTH_UNDEFINED
)
3222 return -E1000_ERR_PHY
;
3224 phy
->cable_length
= length
;