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[deliverable/linux.git] / drivers / net / ethernet / intel / fm10k / fm10k_type.h
1 /* Intel Ethernet Switch Host Interface Driver
2 * Copyright(c) 2013 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
18 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
19 */
20
21 #ifndef _FM10K_TYPE_H_
22 #define _FM10K_TYPE_H_
23
24 /* forward declaration */
25 struct fm10k_hw;
26
27 #include <linux/types.h>
28 #include <asm/byteorder.h>
29 #include <linux/etherdevice.h>
30
31 #include "fm10k_mbx.h"
32
33 #define FM10K_DEV_ID_PF 0x15A4
34 #define FM10K_DEV_ID_VF 0x15A5
35
36 #define FM10K_MAX_QUEUES 256
37 #define FM10K_MAX_QUEUES_PF 128
38 #define FM10K_MAX_QUEUES_POOL 16
39
40 #define FM10K_48_BIT_MASK 0x0000FFFFFFFFFFFFull
41 #define FM10K_STAT_VALID 0x80000000
42
43 /* PCI Bus Info */
44 #define FM10K_PCIE_LINK_CAP 0x7C
45 #define FM10K_PCIE_LINK_STATUS 0x82
46 #define FM10K_PCIE_LINK_WIDTH 0x3F0
47 #define FM10K_PCIE_LINK_WIDTH_1 0x10
48 #define FM10K_PCIE_LINK_WIDTH_2 0x20
49 #define FM10K_PCIE_LINK_WIDTH_4 0x40
50 #define FM10K_PCIE_LINK_WIDTH_8 0x80
51 #define FM10K_PCIE_LINK_SPEED 0xF
52 #define FM10K_PCIE_LINK_SPEED_2500 0x1
53 #define FM10K_PCIE_LINK_SPEED_5000 0x2
54 #define FM10K_PCIE_LINK_SPEED_8000 0x3
55
56 /* PCIe payload size */
57 #define FM10K_PCIE_DEV_CAP 0x74
58 #define FM10K_PCIE_DEV_CAP_PAYLOAD 0x07
59 #define FM10K_PCIE_DEV_CAP_PAYLOAD_128 0x00
60 #define FM10K_PCIE_DEV_CAP_PAYLOAD_256 0x01
61 #define FM10K_PCIE_DEV_CAP_PAYLOAD_512 0x02
62 #define FM10K_PCIE_DEV_CTRL 0x78
63 #define FM10K_PCIE_DEV_CTRL_PAYLOAD 0xE0
64 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_128 0x00
65 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_256 0x20
66 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_512 0x40
67
68 /* PCIe MSI-X Capability info */
69 #define FM10K_PCI_MSIX_MSG_CTRL 0xB2
70 #define FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK 0x7FF
71 #define FM10K_MAX_MSIX_VECTORS 256
72 #define FM10K_MAX_VECTORS_PF 256
73 #define FM10K_MAX_VECTORS_POOL 32
74
75 /* PCIe SR-IOV Info */
76 #define FM10K_PCIE_SRIOV_CTRL 0x190
77 #define FM10K_PCIE_SRIOV_CTRL_VFARI 0x10
78
79 #define FM10K_ERR_PARAM -2
80 #define FM10K_ERR_REQUESTS_PENDING -4
81 #define FM10K_ERR_RESET_REQUESTED -5
82 #define FM10K_ERR_DMA_PENDING -6
83 #define FM10K_ERR_RESET_FAILED -7
84 #define FM10K_ERR_INVALID_MAC_ADDR -8
85 #define FM10K_ERR_INVALID_VALUE -9
86 #define FM10K_NOT_IMPLEMENTED 0x7FFFFFFF
87
88 /* Start of PF registers */
89 #define FM10K_CTRL 0x0000
90 #define FM10K_CTRL_BAR4_ALLOWED 0x00000004
91
92 #define FM10K_CTRL_EXT 0x0001
93 #define FM10K_GCR 0x0003
94 #define FM10K_GCR_EXT 0x0005
95
96 /* Interrupt control registers */
97 #define FM10K_EICR 0x0006
98 #define FM10K_EICR_FAULT_MASK 0x0000003F
99 #define FM10K_EICR_MAILBOX 0x00000040
100 #define FM10K_EICR_SWITCHREADY 0x00000080
101 #define FM10K_EICR_SWITCHNOTREADY 0x00000100
102 #define FM10K_EICR_SWITCHINTERRUPT 0x00000200
103 #define FM10K_EICR_VFLR 0x00000800
104 #define FM10K_EICR_MAXHOLDTIME 0x00001000
105 #define FM10K_EIMR 0x0007
106 #define FM10K_EIMR_PCA_FAULT 0x00000001
107 #define FM10K_EIMR_THI_FAULT 0x00000010
108 #define FM10K_EIMR_FUM_FAULT 0x00000400
109 #define FM10K_EIMR_MAILBOX 0x00001000
110 #define FM10K_EIMR_SWITCHREADY 0x00004000
111 #define FM10K_EIMR_SWITCHNOTREADY 0x00010000
112 #define FM10K_EIMR_SWITCHINTERRUPT 0x00040000
113 #define FM10K_EIMR_SRAMERROR 0x00100000
114 #define FM10K_EIMR_VFLR 0x00400000
115 #define FM10K_EIMR_MAXHOLDTIME 0x01000000
116 #define FM10K_EIMR_ALL 0x55555555
117 #define FM10K_EIMR_DISABLE(NAME) ((FM10K_EIMR_ ## NAME) << 0)
118 #define FM10K_EIMR_ENABLE(NAME) ((FM10K_EIMR_ ## NAME) << 1)
119 #define FM10K_FAULT_ADDR_LO 0x0
120 #define FM10K_FAULT_ADDR_HI 0x1
121 #define FM10K_FAULT_SPECINFO 0x2
122 #define FM10K_FAULT_FUNC 0x3
123 #define FM10K_FAULT_SIZE 0x4
124 #define FM10K_FAULT_FUNC_VALID 0x00008000
125 #define FM10K_FAULT_FUNC_PF 0x00004000
126 #define FM10K_FAULT_FUNC_VF_MASK 0x00003F00
127 #define FM10K_FAULT_FUNC_VF_SHIFT 8
128 #define FM10K_FAULT_FUNC_TYPE_MASK 0x000000FF
129
130 #define FM10K_PCA_FAULT 0x0008
131 #define FM10K_THI_FAULT 0x0010
132 #define FM10K_FUM_FAULT 0x001C
133
134 /* Rx queue timeout indicator */
135 #define FM10K_MAXHOLDQ(_n) ((_n) + 0x0020)
136
137 /* Switch Manager info */
138 #define FM10K_SM_AREA(_n) ((_n) + 0x0028)
139
140 /* GLORT mapping registers */
141 #define FM10K_DGLORTMAP(_n) ((_n) + 0x0030)
142 #define FM10K_DGLORT_COUNT 8
143 #define FM10K_DGLORTMAP_MASK_SHIFT 16
144 #define FM10K_DGLORTMAP_ANY 0x00000000
145 #define FM10K_DGLORTMAP_NONE 0x0000FFFF
146 #define FM10K_DGLORTMAP_ZERO 0xFFFF0000
147 #define FM10K_DGLORTDEC(_n) ((_n) + 0x0038)
148 #define FM10K_DGLORTDEC_VSILENGTH_SHIFT 4
149 #define FM10K_DGLORTDEC_VSIBASE_SHIFT 7
150 #define FM10K_DGLORTDEC_PCLENGTH_SHIFT 14
151 #define FM10K_DGLORTDEC_QBASE_SHIFT 16
152 #define FM10K_DGLORTDEC_RSSLENGTH_SHIFT 24
153 #define FM10K_DGLORTDEC_INNERRSS_ENABLE 0x08000000
154 #define FM10K_TUNNEL_CFG 0x0040
155 #define FM10K_TUNNEL_CFG_NVGRE_SHIFT 16
156 #define FM10K_SWPRI_MAP(_n) ((_n) + 0x0050)
157 #define FM10K_SWPRI_MAX 16
158 #define FM10K_RSSRK(_n, _m) (((_n) * 0x10) + (_m) + 0x0800)
159 #define FM10K_RSSRK_SIZE 10
160 #define FM10K_RSSRK_ENTRIES_PER_REG 4
161 #define FM10K_RETA(_n, _m) (((_n) * 0x20) + (_m) + 0x1000)
162 #define FM10K_RETA_SIZE 32
163 #define FM10K_RETA_ENTRIES_PER_REG 4
164 #define FM10K_MAX_RSS_INDICES 128
165
166 /* Rate limiting registers */
167 #define FM10K_TC_CREDIT(_n) ((_n) + 0x2000)
168 #define FM10K_TC_CREDIT_CREDIT_MASK 0x001FFFFF
169 #define FM10K_TC_MAXCREDIT(_n) ((_n) + 0x2040)
170 #define FM10K_TC_MAXCREDIT_64K 0x00010000
171 #define FM10K_TC_RATE(_n) ((_n) + 0x2080)
172 #define FM10K_TC_RATE_QUANTA_MASK 0x0000FFFF
173 #define FM10K_TC_RATE_INTERVAL_4US_GEN1 0x00020000
174 #define FM10K_TC_RATE_INTERVAL_4US_GEN2 0x00040000
175 #define FM10K_TC_RATE_INTERVAL_4US_GEN3 0x00080000
176
177 /* DMA control registers */
178 #define FM10K_DMA_CTRL 0x20C3
179 #define FM10K_DMA_CTRL_TX_ENABLE 0x00000001
180 #define FM10K_DMA_CTRL_TX_ACTIVE 0x00000008
181 #define FM10K_DMA_CTRL_RX_ENABLE 0x00000010
182 #define FM10K_DMA_CTRL_RX_ACTIVE 0x00000080
183 #define FM10K_DMA_CTRL_RX_DESC_SIZE 0x00000100
184 #define FM10K_DMA_CTRL_MINMSS_64 0x00008000
185 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3 0x04800000
186 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2 0x04000000
187 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1 0x03800000
188 #define FM10K_DMA_CTRL_DATAPATH_RESET 0x20000000
189 #define FM10K_DMA_CTRL_32_DESC 0x00000000
190
191 #define FM10K_DMA_CTRL2 0x20C4
192 #define FM10K_DMA_CTRL2_SWITCH_READY 0x00002000
193
194 /* TSO flags configuration
195 * First packet contains all flags except for fin and psh
196 * Middle packet contains only urg and ack
197 * Last packet contains urg, ack, fin, and psh
198 */
199 #define FM10K_TSO_FLAGS_LOW 0x00300FF6
200 #define FM10K_TSO_FLAGS_HI 0x00000039
201 #define FM10K_DTXTCPFLGL 0x20C5
202 #define FM10K_DTXTCPFLGH 0x20C6
203
204 #define FM10K_TPH_CTRL 0x20C7
205 #define FM10K_MRQC(_n) ((_n) + 0x2100)
206 #define FM10K_MRQC_TCP_IPV4 0x00000001
207 #define FM10K_MRQC_IPV4 0x00000002
208 #define FM10K_MRQC_IPV6 0x00000010
209 #define FM10K_MRQC_TCP_IPV6 0x00000020
210 #define FM10K_MRQC_UDP_IPV4 0x00000040
211 #define FM10K_MRQC_UDP_IPV6 0x00000080
212
213 #define FM10K_TQMAP(_n) ((_n) + 0x2800)
214 #define FM10K_TQMAP_TABLE_SIZE 2048
215 #define FM10K_RQMAP(_n) ((_n) + 0x3000)
216
217 /* Hardware Statistics */
218 #define FM10K_STATS_TIMEOUT 0x3800
219 #define FM10K_STATS_UR 0x3801
220 #define FM10K_STATS_CA 0x3802
221 #define FM10K_STATS_UM 0x3803
222 #define FM10K_STATS_XEC 0x3804
223 #define FM10K_STATS_VLAN_DROP 0x3805
224 #define FM10K_STATS_LOOPBACK_DROP 0x3806
225 #define FM10K_STATS_NODESC_DROP 0x3807
226
227 /* PCIe state registers */
228 #define FM10K_PHYADDR 0x381C
229
230 /* Rx ring registers */
231 #define FM10K_RDBAL(_n) ((0x40 * (_n)) + 0x4000)
232 #define FM10K_RDBAH(_n) ((0x40 * (_n)) + 0x4001)
233 #define FM10K_RDLEN(_n) ((0x40 * (_n)) + 0x4002)
234 #define FM10K_TPH_RXCTRL(_n) ((0x40 * (_n)) + 0x4003)
235 #define FM10K_TPH_RXCTRL_DESC_TPHEN 0x00000020
236 #define FM10K_TPH_RXCTRL_DESC_RROEN 0x00000200
237 #define FM10K_TPH_RXCTRL_DATA_WROEN 0x00002000
238 #define FM10K_TPH_RXCTRL_HDR_WROEN 0x00008000
239 #define FM10K_RDH(_n) ((0x40 * (_n)) + 0x4004)
240 #define FM10K_RDT(_n) ((0x40 * (_n)) + 0x4005)
241 #define FM10K_RXQCTL(_n) ((0x40 * (_n)) + 0x4006)
242 #define FM10K_RXQCTL_ENABLE 0x00000001
243 #define FM10K_RXQCTL_PF 0x000000FC
244 #define FM10K_RXQCTL_VF_SHIFT 2
245 #define FM10K_RXQCTL_VF 0x00000100
246 #define FM10K_RXQCTL_ID_MASK (FM10K_RXQCTL_PF | FM10K_RXQCTL_VF)
247 #define FM10K_RXDCTL(_n) ((0x40 * (_n)) + 0x4007)
248 #define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY 0x00000001
249 #define FM10K_RXDCTL_DROP_ON_EMPTY 0x00000200
250 #define FM10K_RXINT(_n) ((0x40 * (_n)) + 0x4008)
251 #define FM10K_SRRCTL(_n) ((0x40 * (_n)) + 0x4009)
252 #define FM10K_SRRCTL_BSIZEPKT_SHIFT 8 /* shift _right_ */
253 #define FM10K_SRRCTL_LOOPBACK_SUPPRESS 0x40000000
254 #define FM10K_SRRCTL_BUFFER_CHAINING_EN 0x80000000
255
256 /* Rx Statistics */
257 #define FM10K_QPRC(_n) ((0x40 * (_n)) + 0x400A)
258 #define FM10K_QPRDC(_n) ((0x40 * (_n)) + 0x400B)
259 #define FM10K_QBRC_L(_n) ((0x40 * (_n)) + 0x400C)
260 #define FM10K_QBRC_H(_n) ((0x40 * (_n)) + 0x400D)
261
262 /* Rx GLORT register */
263 #define FM10K_RX_SGLORT(_n) ((0x40 * (_n)) + 0x400E)
264
265 /* Tx ring registers */
266 #define FM10K_TDBAL(_n) ((0x40 * (_n)) + 0x8000)
267 #define FM10K_TDBAH(_n) ((0x40 * (_n)) + 0x8001)
268 #define FM10K_TDLEN(_n) ((0x40 * (_n)) + 0x8002)
269 #define FM10K_TPH_TXCTRL(_n) ((0x40 * (_n)) + 0x8003)
270 #define FM10K_TPH_TXCTRL_DESC_TPHEN 0x00000020
271 #define FM10K_TPH_TXCTRL_DESC_RROEN 0x00000200
272 #define FM10K_TPH_TXCTRL_DESC_WROEN 0x00000800
273 #define FM10K_TPH_TXCTRL_DATA_RROEN 0x00002000
274 #define FM10K_TDH(_n) ((0x40 * (_n)) + 0x8004)
275 #define FM10K_TDT(_n) ((0x40 * (_n)) + 0x8005)
276 #define FM10K_TXDCTL(_n) ((0x40 * (_n)) + 0x8006)
277 #define FM10K_TXDCTL_ENABLE 0x00004000
278 #define FM10K_TXDCTL_MAX_TIME_SHIFT 16
279 #define FM10K_TXQCTL(_n) ((0x40 * (_n)) + 0x8007)
280 #define FM10K_TXQCTL_PF 0x0000003F
281 #define FM10K_TXQCTL_VF 0x00000040
282 #define FM10K_TXQCTL_ID_MASK (FM10K_TXQCTL_PF | FM10K_TXQCTL_VF)
283 #define FM10K_TXQCTL_PC_SHIFT 7
284 #define FM10K_TXQCTL_PC_MASK 0x00000380
285 #define FM10K_TXQCTL_TC_SHIFT 10
286 #define FM10K_TXQCTL_VID_SHIFT 16
287 #define FM10K_TXQCTL_VID_MASK 0x0FFF0000
288 #define FM10K_TXQCTL_UNLIMITED_BW 0x10000000
289 #define FM10K_TXINT(_n) ((0x40 * (_n)) + 0x8008)
290
291 /* Tx Statistics */
292 #define FM10K_QPTC(_n) ((0x40 * (_n)) + 0x8009)
293 #define FM10K_QBTC_L(_n) ((0x40 * (_n)) + 0x800A)
294 #define FM10K_QBTC_H(_n) ((0x40 * (_n)) + 0x800B)
295
296 /* Tx Push registers */
297 #define FM10K_TQDLOC(_n) ((0x40 * (_n)) + 0x800C)
298 #define FM10K_TQDLOC_BASE_32_DESC 0x08
299 #define FM10K_TQDLOC_SIZE_32_DESC 0x00050000
300
301 /* Tx GLORT registers */
302 #define FM10K_TX_SGLORT(_n) ((0x40 * (_n)) + 0x800D)
303 #define FM10K_PFVTCTL(_n) ((0x40 * (_n)) + 0x800E)
304 #define FM10K_PFVTCTL_FTAG_DESC_ENABLE 0x00000001
305
306 /* Interrupt moderation and control registers */
307 #define FM10K_INT_MAP(_n) ((_n) + 0x10080)
308 #define FM10K_INT_MAP_TIMER0 0x00000000
309 #define FM10K_INT_MAP_TIMER1 0x00000100
310 #define FM10K_INT_MAP_IMMEDIATE 0x00000200
311 #define FM10K_INT_MAP_DISABLE 0x00000300
312 #define FM10K_MSIX_VECTOR_MASK(_n) ((0x4 * (_n)) + 0x11003)
313 #define FM10K_INT_CTRL 0x12000
314 #define FM10K_INT_CTRL_ENABLEMODERATOR 0x00000400
315 #define FM10K_ITR(_n) ((_n) + 0x12400)
316 #define FM10K_ITR_INTERVAL1_SHIFT 12
317 #define FM10K_ITR_PENDING2 0x10000000
318 #define FM10K_ITR_AUTOMASK 0x20000000
319 #define FM10K_ITR_MASK_SET 0x40000000
320 #define FM10K_ITR_MASK_CLEAR 0x80000000
321 #define FM10K_ITR2(_n) ((0x2 * (_n)) + 0x12800)
322 #define FM10K_ITR_REG_COUNT 768
323 #define FM10K_ITR_REG_COUNT_PF 256
324
325 /* Switch manager interrupt registers */
326 #define FM10K_IP 0x13000
327 #define FM10K_IP_NOTINRESET 0x00000100
328
329 /* VLAN registers */
330 #define FM10K_VLAN_TABLE(_n, _m) ((0x80 * (_n)) + (_m) + 0x14000)
331 #define FM10K_VLAN_TABLE_SIZE 128
332
333 /* VLAN specific message offsets */
334 #define FM10K_VLAN_TABLE_VID_MAX 4096
335 #define FM10K_VLAN_TABLE_VSI_MAX 64
336 #define FM10K_VLAN_LENGTH_SHIFT 16
337 #define FM10K_VLAN_CLEAR (1 << 15)
338 #define FM10K_VLAN_ALL \
339 ((FM10K_VLAN_TABLE_VID_MAX - 1) << FM10K_VLAN_LENGTH_SHIFT)
340
341 /* VF FLR event notification registers */
342 #define FM10K_PFVFLRE(_n) ((0x1 * (_n)) + 0x18844)
343 #define FM10K_PFVFLREC(_n) ((0x1 * (_n)) + 0x18846)
344
345 /* Defines for size of uncacheable memories */
346 #define FM10K_UC_ADDR_START 0x000000 /* start of standard regs */
347 #define FM10K_UC_ADDR_END 0x100000 /* end of standard regs */
348 #define FM10K_UC_ADDR_SIZE (FM10K_UC_ADDR_END - FM10K_UC_ADDR_START)
349
350 /* Define timeouts for resets and disables */
351 #define FM10K_QUEUE_DISABLE_TIMEOUT 100
352 #define FM10K_RESET_TIMEOUT 100
353
354 /* VF registers */
355 #define FM10K_VFCTRL 0x00000
356 #define FM10K_VFCTRL_RST 0x00000008
357 #define FM10K_VFINT_MAP 0x00030
358 #define FM10K_VFSYSTIME 0x00040
359 #define FM10K_VFITR(_n) ((_n) + 0x00060)
360
361 enum fm10k_int_source {
362 fm10k_int_Mailbox = 0,
363 fm10k_int_PCIeFault = 1,
364 fm10k_int_SwitchUpDown = 2,
365 fm10k_int_SwitchEvent = 3,
366 fm10k_int_SRAM = 4,
367 fm10k_int_VFLR = 5,
368 fm10k_int_MaxHoldTime = 6,
369 fm10k_int_sources_max_pf
370 };
371
372 /* PCIe bus speeds */
373 enum fm10k_bus_speed {
374 fm10k_bus_speed_unknown = 0,
375 fm10k_bus_speed_2500 = 2500,
376 fm10k_bus_speed_5000 = 5000,
377 fm10k_bus_speed_8000 = 8000,
378 fm10k_bus_speed_reserved
379 };
380
381 /* PCIe bus widths */
382 enum fm10k_bus_width {
383 fm10k_bus_width_unknown = 0,
384 fm10k_bus_width_pcie_x1 = 1,
385 fm10k_bus_width_pcie_x2 = 2,
386 fm10k_bus_width_pcie_x4 = 4,
387 fm10k_bus_width_pcie_x8 = 8,
388 fm10k_bus_width_reserved
389 };
390
391 /* PCIe payload sizes */
392 enum fm10k_bus_payload {
393 fm10k_bus_payload_unknown = 0,
394 fm10k_bus_payload_128 = 1,
395 fm10k_bus_payload_256 = 2,
396 fm10k_bus_payload_512 = 3,
397 fm10k_bus_payload_reserved
398 };
399
400 /* Bus parameters */
401 struct fm10k_bus_info {
402 enum fm10k_bus_speed speed;
403 enum fm10k_bus_width width;
404 enum fm10k_bus_payload payload;
405 };
406
407 /* Statistics related declarations */
408 struct fm10k_hw_stat {
409 u64 count;
410 u32 base_l;
411 u32 base_h;
412 };
413
414 struct fm10k_hw_stats_q {
415 struct fm10k_hw_stat tx_bytes;
416 struct fm10k_hw_stat tx_packets;
417 #define tx_stats_idx tx_packets.base_h
418 struct fm10k_hw_stat rx_bytes;
419 struct fm10k_hw_stat rx_packets;
420 #define rx_stats_idx rx_packets.base_h
421 struct fm10k_hw_stat rx_drops;
422 };
423
424 struct fm10k_hw_stats {
425 struct fm10k_hw_stat timeout;
426 #define stats_idx timeout.base_h
427 struct fm10k_hw_stat ur;
428 struct fm10k_hw_stat ca;
429 struct fm10k_hw_stat um;
430 struct fm10k_hw_stat xec;
431 struct fm10k_hw_stat vlan_drop;
432 struct fm10k_hw_stat loopback_drop;
433 struct fm10k_hw_stat nodesc_drop;
434 struct fm10k_hw_stats_q q[FM10K_MAX_QUEUES_PF];
435 };
436
437 /* Establish DGLORT feature priority */
438 enum fm10k_dglortdec_idx {
439 fm10k_dglort_default = 0,
440 fm10k_dglort_vf_rsvd0 = 1,
441 fm10k_dglort_vf_rss = 2,
442 fm10k_dglort_pf_rsvd0 = 3,
443 fm10k_dglort_pf_queue = 4,
444 fm10k_dglort_pf_vsi = 5,
445 fm10k_dglort_pf_rsvd1 = 6,
446 fm10k_dglort_pf_rss = 7
447 };
448
449 struct fm10k_dglort_cfg {
450 u16 glort; /* GLORT base */
451 u16 queue_b; /* Base value for queue */
452 u8 vsi_b; /* Base value for VSI */
453 u8 idx; /* index of DGLORTDEC entry */
454 u8 rss_l; /* RSS indices */
455 u8 pc_l; /* Priority Class indices */
456 u8 vsi_l; /* Number of bits from GLORT used to determine VSI */
457 u8 queue_l; /* Number of bits from GLORT used to determine queue */
458 u8 shared_l; /* Ignored bits from GLORT resulting in shared VSI */
459 u8 inner_rss; /* Boolean value if inner header is used for RSS */
460 };
461
462 enum fm10k_pca_fault {
463 PCA_NO_FAULT,
464 PCA_UNMAPPED_ADDR,
465 PCA_BAD_QACCESS_PF,
466 PCA_BAD_QACCESS_VF,
467 PCA_MALICIOUS_REQ,
468 PCA_POISONED_TLP,
469 PCA_TLP_ABORT,
470 __PCA_MAX
471 };
472
473 enum fm10k_thi_fault {
474 THI_NO_FAULT,
475 THI_MAL_DIS_Q_FAULT,
476 __THI_MAX
477 };
478
479 enum fm10k_fum_fault {
480 FUM_NO_FAULT,
481 FUM_UNMAPPED_ADDR,
482 FUM_POISONED_TLP,
483 FUM_BAD_VF_QACCESS,
484 FUM_ADD_DECODE_ERR,
485 FUM_RO_ERROR,
486 FUM_QPRC_CRC_ERROR,
487 FUM_CSR_TIMEOUT,
488 FUM_INVALID_TYPE,
489 FUM_INVALID_LENGTH,
490 FUM_INVALID_BE,
491 FUM_INVALID_ALIGN,
492 __FUM_MAX
493 };
494
495 struct fm10k_fault {
496 u64 address; /* Address at the time fault was detected */
497 u32 specinfo; /* Extra info on this fault (fault dependent) */
498 u8 type; /* Fault value dependent on subunit */
499 u8 func; /* Function number of the fault */
500 };
501
502 struct fm10k_mac_ops {
503 /* basic bring-up and tear-down */
504 s32 (*reset_hw)(struct fm10k_hw *);
505 s32 (*init_hw)(struct fm10k_hw *);
506 s32 (*start_hw)(struct fm10k_hw *);
507 s32 (*stop_hw)(struct fm10k_hw *);
508 s32 (*get_bus_info)(struct fm10k_hw *);
509 s32 (*get_host_state)(struct fm10k_hw *, bool *);
510 bool (*is_slot_appropriate)(struct fm10k_hw *);
511 s32 (*update_vlan)(struct fm10k_hw *, u32, u8, bool);
512 s32 (*read_mac_addr)(struct fm10k_hw *);
513 s32 (*update_uc_addr)(struct fm10k_hw *, u16, const u8 *,
514 u16, bool, u8);
515 s32 (*update_mc_addr)(struct fm10k_hw *, u16, const u8 *, u16, bool);
516 s32 (*update_xcast_mode)(struct fm10k_hw *, u16, u8);
517 void (*update_int_moderator)(struct fm10k_hw *);
518 s32 (*update_lport_state)(struct fm10k_hw *, u16, u16, bool);
519 void (*update_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *);
520 void (*rebind_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *);
521 s32 (*configure_dglort_map)(struct fm10k_hw *,
522 struct fm10k_dglort_cfg *);
523 void (*set_dma_mask)(struct fm10k_hw *, u64);
524 s32 (*get_fault)(struct fm10k_hw *, int, struct fm10k_fault *);
525 void (*request_lport_map)(struct fm10k_hw *);
526 s32 (*adjust_systime)(struct fm10k_hw *, s32 ppb);
527 };
528
529 enum fm10k_mac_type {
530 fm10k_mac_unknown = 0,
531 fm10k_mac_pf,
532 fm10k_mac_vf,
533 fm10k_num_macs
534 };
535
536 struct fm10k_mac_info {
537 struct fm10k_mac_ops ops;
538 enum fm10k_mac_type type;
539 u8 addr[ETH_ALEN];
540 u8 perm_addr[ETH_ALEN];
541 u16 default_vid;
542 u16 max_msix_vectors;
543 u16 max_queues;
544 bool vlan_override;
545 bool get_host_state;
546 bool tx_ready;
547 u32 dglort_map;
548 };
549
550 struct fm10k_swapi_table_info {
551 u32 used;
552 u32 avail;
553 };
554
555 struct fm10k_swapi_info {
556 u32 status;
557 struct fm10k_swapi_table_info mac;
558 struct fm10k_swapi_table_info nexthop;
559 struct fm10k_swapi_table_info ffu;
560 };
561
562 enum fm10k_xcast_modes {
563 FM10K_XCAST_MODE_ALLMULTI = 0,
564 FM10K_XCAST_MODE_MULTI = 1,
565 FM10K_XCAST_MODE_PROMISC = 2,
566 FM10K_XCAST_MODE_NONE = 3,
567 FM10K_XCAST_MODE_DISABLE = 4
568 };
569
570 enum fm10k_devices {
571 fm10k_device_pf,
572 fm10k_device_vf,
573 };
574
575 struct fm10k_info {
576 enum fm10k_mac_type mac;
577 s32 (*get_invariants)(struct fm10k_hw *);
578 struct fm10k_mac_ops *mac_ops;
579 };
580
581 struct fm10k_hw {
582 u32 __iomem *hw_addr;
583 void *back;
584 struct fm10k_mac_info mac;
585 struct fm10k_bus_info bus;
586 struct fm10k_bus_info bus_caps;
587 struct fm10k_mbx_info mbx;
588 struct fm10k_swapi_info swapi;
589 u16 device_id;
590 u16 vendor_id;
591 u16 subsystem_device_id;
592 u16 subsystem_vendor_id;
593 u8 revision_id;
594 };
595
596 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
597 #define FM10K_REQ_TX_DESCRIPTOR_MULTIPLE 8
598 #define FM10K_REQ_RX_DESCRIPTOR_MULTIPLE 8
599
600 /* Transmit Descriptor */
601 struct fm10k_tx_desc {
602 __le64 buffer_addr; /* Address of the descriptor's data buffer */
603 __le16 buflen; /* Length of data to be DMAed */
604 __le16 vlan; /* VLAN_ID and VPRI to be inserted in FTAG */
605 __le16 mss; /* MSS for segmentation offload */
606 u8 hdrlen; /* Header size for segmentation offload */
607 u8 flags; /* Status and offload request flags */
608 };
609
610 /* Transmit Descriptor Cache Structure */
611 struct fm10k_tx_desc_cache {
612 struct fm10k_tx_desc tx_desc[256];
613 };
614
615 #define FM10K_TXD_FLAG_INT 0x01
616 #define FM10K_TXD_FLAG_TIME 0x02
617 #define FM10K_TXD_FLAG_CSUM 0x04
618 #define FM10K_TXD_FLAG_FTAG 0x10
619 #define FM10K_TXD_FLAG_RS 0x20
620 #define FM10K_TXD_FLAG_LAST 0x40
621 #define FM10K_TXD_FLAG_DONE 0x80
622
623 /* These macros are meant to enable optimal placement of the RS and INT
624 * bits. It will point us to the last descriptor in the cache for either the
625 * start of the packet, or the end of the packet. If the index is actually
626 * at the start of the FIFO it will point to the offset for the last index
627 * in the FIFO to prevent an unnecessary write.
628 */
629 #define FM10K_TXD_WB_FIFO_SIZE 4
630
631 /* Receive Descriptor - 32B */
632 union fm10k_rx_desc {
633 struct {
634 __le64 pkt_addr; /* Packet buffer address */
635 __le64 hdr_addr; /* Header buffer address */
636 __le64 reserved; /* Empty space, RSS hash */
637 __le64 timestamp;
638 } q; /* Read, Writeback, 64b quad-words */
639 struct {
640 __le32 data; /* RSS and header data */
641 __le32 rss; /* RSS Hash */
642 __le32 staterr;
643 __le32 vlan_len;
644 __le32 glort; /* sglort/dglort */
645 } d; /* Writeback, 32b double-words */
646 struct {
647 __le16 pkt_info; /* RSS, Pkt type */
648 __le16 hdr_info; /* Splithdr, hdrlen, xC */
649 __le16 rss_lower;
650 __le16 rss_upper;
651 __le16 status; /* status/error */
652 __le16 csum_err; /* checksum or extended error value */
653 __le16 length; /* Packet length */
654 __le16 vlan; /* VLAN tag */
655 __le16 dglort;
656 __le16 sglort;
657 } w; /* Writeback, 16b words */
658 };
659
660 #define FM10K_RXD_RSSTYPE_MASK 0x000F
661 enum fm10k_rdesc_rss_type {
662 FM10K_RSSTYPE_NONE = 0x0,
663 FM10K_RSSTYPE_IPV4_TCP = 0x1,
664 FM10K_RSSTYPE_IPV4 = 0x2,
665 FM10K_RSSTYPE_IPV6_TCP = 0x3,
666 /* Reserved 0x4 */
667 FM10K_RSSTYPE_IPV6 = 0x5,
668 /* Reserved 0x6 */
669 FM10K_RSSTYPE_IPV4_UDP = 0x7,
670 FM10K_RSSTYPE_IPV6_UDP = 0x8
671 /* Reserved 0x9 - 0xF */
672 };
673
674 #define FM10K_RXD_HDR_INFO_XC_MASK 0x0006
675 enum fm10k_rxdesc_xc {
676 FM10K_XC_UNICAST = 0x0,
677 FM10K_XC_MULTICAST = 0x4,
678 FM10K_XC_BROADCAST = 0x6
679 };
680
681 #define FM10K_RXD_STATUS_DD 0x0001 /* Descriptor done */
682 #define FM10K_RXD_STATUS_EOP 0x0002 /* End of packet */
683 #define FM10K_RXD_STATUS_L4CS 0x0010 /* Indicates an L4 csum */
684 #define FM10K_RXD_STATUS_L4CS2 0x0040 /* Inner header L4 csum */
685 #define FM10K_RXD_STATUS_L4E2 0x0800 /* Inner header L4 csum err */
686 #define FM10K_RXD_STATUS_IPE2 0x1000 /* Inner header IPv4 csum err */
687 #define FM10K_RXD_STATUS_RXE 0x2000 /* Generic Rx error */
688 #define FM10K_RXD_STATUS_L4E 0x4000 /* L4 csum error */
689 #define FM10K_RXD_STATUS_IPE 0x8000 /* IPv4 csum error */
690
691 struct fm10k_ftag {
692 __be16 swpri_type_user;
693 __be16 vlan;
694 __be16 sglort;
695 __be16 dglort;
696 };
697
698 #endif /* _FM10K_TYPE_H */
Linux kernel - Deliverables
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