projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
i40e: define function capabilities in only one place
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_adminq_cmd.h
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_ADMINQ_CMD_H_
28 #define _I40E_ADMINQ_CMD_H_
29
30 /* This header file defines the i40e Admin Queue commands and is shared between
31 * i40e Firmware and Software.
32 *
33 * This file needs to comply with the Linux Kernel coding style.
34 */
35
36 #define I40E_FW_API_VERSION_MAJOR 0x0001
37 #define I40E_FW_API_VERSION_MINOR 0x0004
38
39 struct i40e_aq_desc {
40 __le16 flags;
41 __le16 opcode;
42 __le16 datalen;
43 __le16 retval;
44 __le32 cookie_high;
45 __le32 cookie_low;
46 union {
47 struct {
48 __le32 param0;
49 __le32 param1;
50 __le32 param2;
51 __le32 param3;
52 } internal;
53 struct {
54 __le32 param0;
55 __le32 param1;
56 __le32 addr_high;
57 __le32 addr_low;
58 } external;
59 u8 raw[16];
60 } params;
61 };
62
63 /* Flags sub-structure
64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
66 */
67
68 /* command flags and offsets*/
69 #define I40E_AQ_FLAG_DD_SHIFT 0
70 #define I40E_AQ_FLAG_CMP_SHIFT 1
71 #define I40E_AQ_FLAG_ERR_SHIFT 2
72 #define I40E_AQ_FLAG_VFE_SHIFT 3
73 #define I40E_AQ_FLAG_LB_SHIFT 9
74 #define I40E_AQ_FLAG_RD_SHIFT 10
75 #define I40E_AQ_FLAG_VFC_SHIFT 11
76 #define I40E_AQ_FLAG_BUF_SHIFT 12
77 #define I40E_AQ_FLAG_SI_SHIFT 13
78 #define I40E_AQ_FLAG_EI_SHIFT 14
79 #define I40E_AQ_FLAG_FE_SHIFT 15
80
81 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
82 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
83 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
84 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
85 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
86 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
87 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
88 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
89 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
90 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
91 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
92
93 /* error codes */
94 enum i40e_admin_queue_err {
95 I40E_AQ_RC_OK = 0, /* success */
96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
97 I40E_AQ_RC_ENOENT = 2, /* No such element */
98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
100 I40E_AQ_RC_EIO = 5, /* I/O error */
101 I40E_AQ_RC_ENXIO = 6, /* No such resource */
102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
103 I40E_AQ_RC_EAGAIN = 8, /* Try again */
104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
105 I40E_AQ_RC_EACCES = 10, /* Permission denied */
106 I40E_AQ_RC_EFAULT = 11, /* Bad address */
107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
108 I40E_AQ_RC_EEXIST = 13, /* object already exists */
109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
117 I40E_AQ_RC_EFBIG = 22, /* File too large */
118 };
119
120 /* Admin Queue command opcodes */
121 enum i40e_admin_queue_opc {
122 /* aq commands */
123 i40e_aqc_opc_get_version = 0x0001,
124 i40e_aqc_opc_driver_version = 0x0002,
125 i40e_aqc_opc_queue_shutdown = 0x0003,
126 i40e_aqc_opc_set_pf_context = 0x0004,
127
128 /* resource ownership */
129 i40e_aqc_opc_request_resource = 0x0008,
130 i40e_aqc_opc_release_resource = 0x0009,
131
132 i40e_aqc_opc_list_func_capabilities = 0x000A,
133 i40e_aqc_opc_list_dev_capabilities = 0x000B,
134
135 /* LAA */
136 i40e_aqc_opc_mac_address_read = 0x0107,
137 i40e_aqc_opc_mac_address_write = 0x0108,
138
139 /* PXE */
140 i40e_aqc_opc_clear_pxe_mode = 0x0110,
141
142 /* internal switch commands */
143 i40e_aqc_opc_get_switch_config = 0x0200,
144 i40e_aqc_opc_add_statistics = 0x0201,
145 i40e_aqc_opc_remove_statistics = 0x0202,
146 i40e_aqc_opc_set_port_parameters = 0x0203,
147 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
148
149 i40e_aqc_opc_add_vsi = 0x0210,
150 i40e_aqc_opc_update_vsi_parameters = 0x0211,
151 i40e_aqc_opc_get_vsi_parameters = 0x0212,
152
153 i40e_aqc_opc_add_pv = 0x0220,
154 i40e_aqc_opc_update_pv_parameters = 0x0221,
155 i40e_aqc_opc_get_pv_parameters = 0x0222,
156
157 i40e_aqc_opc_add_veb = 0x0230,
158 i40e_aqc_opc_update_veb_parameters = 0x0231,
159 i40e_aqc_opc_get_veb_parameters = 0x0232,
160
161 i40e_aqc_opc_delete_element = 0x0243,
162
163 i40e_aqc_opc_add_macvlan = 0x0250,
164 i40e_aqc_opc_remove_macvlan = 0x0251,
165 i40e_aqc_opc_add_vlan = 0x0252,
166 i40e_aqc_opc_remove_vlan = 0x0253,
167 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
168 i40e_aqc_opc_add_tag = 0x0255,
169 i40e_aqc_opc_remove_tag = 0x0256,
170 i40e_aqc_opc_add_multicast_etag = 0x0257,
171 i40e_aqc_opc_remove_multicast_etag = 0x0258,
172 i40e_aqc_opc_update_tag = 0x0259,
173 i40e_aqc_opc_add_control_packet_filter = 0x025A,
174 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
175 i40e_aqc_opc_add_cloud_filters = 0x025C,
176 i40e_aqc_opc_remove_cloud_filters = 0x025D,
177
178 i40e_aqc_opc_add_mirror_rule = 0x0260,
179 i40e_aqc_opc_delete_mirror_rule = 0x0261,
180
181 /* DCB commands */
182 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
183 i40e_aqc_opc_dcb_updated = 0x0302,
184
185 /* TX scheduler */
186 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
187 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
188 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
189 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
190 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
191 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
192
193 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
194 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
195 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
196 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
197 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
198 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
199 i40e_aqc_opc_query_port_ets_config = 0x0419,
200 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
201 i40e_aqc_opc_suspend_port_tx = 0x041B,
202 i40e_aqc_opc_resume_port_tx = 0x041C,
203 i40e_aqc_opc_configure_partition_bw = 0x041D,
204
205 /* hmc */
206 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
207 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
208
209 /* phy commands*/
210 i40e_aqc_opc_get_phy_abilities = 0x0600,
211 i40e_aqc_opc_set_phy_config = 0x0601,
212 i40e_aqc_opc_set_mac_config = 0x0603,
213 i40e_aqc_opc_set_link_restart_an = 0x0605,
214 i40e_aqc_opc_get_link_status = 0x0607,
215 i40e_aqc_opc_set_phy_int_mask = 0x0613,
216 i40e_aqc_opc_get_local_advt_reg = 0x0614,
217 i40e_aqc_opc_set_local_advt_reg = 0x0615,
218 i40e_aqc_opc_get_partner_advt = 0x0616,
219 i40e_aqc_opc_set_lb_modes = 0x0618,
220 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
221 i40e_aqc_opc_set_phy_debug = 0x0622,
222 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
223
224 /* NVM commands */
225 i40e_aqc_opc_nvm_read = 0x0701,
226 i40e_aqc_opc_nvm_erase = 0x0702,
227 i40e_aqc_opc_nvm_update = 0x0703,
228 i40e_aqc_opc_nvm_config_read = 0x0704,
229 i40e_aqc_opc_nvm_config_write = 0x0705,
230 i40e_aqc_opc_oem_post_update = 0x0720,
231
232 /* virtualization commands */
233 i40e_aqc_opc_send_msg_to_pf = 0x0801,
234 i40e_aqc_opc_send_msg_to_vf = 0x0802,
235 i40e_aqc_opc_send_msg_to_peer = 0x0803,
236
237 /* alternate structure */
238 i40e_aqc_opc_alternate_write = 0x0900,
239 i40e_aqc_opc_alternate_write_indirect = 0x0901,
240 i40e_aqc_opc_alternate_read = 0x0902,
241 i40e_aqc_opc_alternate_read_indirect = 0x0903,
242 i40e_aqc_opc_alternate_write_done = 0x0904,
243 i40e_aqc_opc_alternate_set_mode = 0x0905,
244 i40e_aqc_opc_alternate_clear_port = 0x0906,
245
246 /* LLDP commands */
247 i40e_aqc_opc_lldp_get_mib = 0x0A00,
248 i40e_aqc_opc_lldp_update_mib = 0x0A01,
249 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
250 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
251 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
252 i40e_aqc_opc_lldp_stop = 0x0A05,
253 i40e_aqc_opc_lldp_start = 0x0A06,
254 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
255 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
256 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
257
258 /* Tunnel commands */
259 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
260 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
261 i40e_aqc_opc_set_rss_key = 0x0B02,
262 i40e_aqc_opc_set_rss_lut = 0x0B03,
263 i40e_aqc_opc_get_rss_key = 0x0B04,
264 i40e_aqc_opc_get_rss_lut = 0x0B05,
265
266 /* Async Events */
267 i40e_aqc_opc_event_lan_overflow = 0x1001,
268
269 /* OEM commands */
270 i40e_aqc_opc_oem_parameter_change = 0xFE00,
271 i40e_aqc_opc_oem_device_status_change = 0xFE01,
272 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
273 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
274
275 /* debug commands */
276 i40e_aqc_opc_debug_read_reg = 0xFF03,
277 i40e_aqc_opc_debug_write_reg = 0xFF04,
278 i40e_aqc_opc_debug_modify_reg = 0xFF07,
279 i40e_aqc_opc_debug_dump_internals = 0xFF08,
280 };
281
282 /* command structures and indirect data structures */
283
284 /* Structure naming conventions:
285 * - no suffix for direct command descriptor structures
286 * - _data for indirect sent data
287 * - _resp for indirect return data (data which is both will use _data)
288 * - _completion for direct return data
289 * - _element_ for repeated elements (may also be _data or _resp)
290 *
291 * Command structures are expected to overlay the params.raw member of the basic
292 * descriptor, and as such cannot exceed 16 bytes in length.
293 */
294
295 /* This macro is used to generate a compilation error if a structure
296 * is not exactly the correct length. It gives a divide by zero error if the
297 * structure is not of the correct size, otherwise it creates an enum that is
298 * never used.
299 */
300 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
301 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
302
303 /* This macro is used extensively to ensure that command structures are 16
304 * bytes in length as they have to map to the raw array of that size.
305 */
306 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
307
308 /* internal (0x00XX) commands */
309
310 /* Get version (direct 0x0001) */
311 struct i40e_aqc_get_version {
312 __le32 rom_ver;
313 __le32 fw_build;
314 __le16 fw_major;
315 __le16 fw_minor;
316 __le16 api_major;
317 __le16 api_minor;
318 };
319
320 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
321
322 /* Send driver version (indirect 0x0002) */
323 struct i40e_aqc_driver_version {
324 u8 driver_major_ver;
325 u8 driver_minor_ver;
326 u8 driver_build_ver;
327 u8 driver_subbuild_ver;
328 u8 reserved[4];
329 __le32 address_high;
330 __le32 address_low;
331 };
332
333 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
334
335 /* Queue Shutdown (direct 0x0003) */
336 struct i40e_aqc_queue_shutdown {
337 __le32 driver_unloading;
338 #define I40E_AQ_DRIVER_UNLOADING 0x1
339 u8 reserved[12];
340 };
341
342 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
343
344 /* Set PF context (0x0004, direct) */
345 struct i40e_aqc_set_pf_context {
346 u8 pf_id;
347 u8 reserved[15];
348 };
349
350 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
351
352 /* Request resource ownership (direct 0x0008)
353 * Release resource ownership (direct 0x0009)
354 */
355 #define I40E_AQ_RESOURCE_NVM 1
356 #define I40E_AQ_RESOURCE_SDP 2
357 #define I40E_AQ_RESOURCE_ACCESS_READ 1
358 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
359 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
360 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
361
362 struct i40e_aqc_request_resource {
363 __le16 resource_id;
364 __le16 access_type;
365 __le32 timeout;
366 __le32 resource_number;
367 u8 reserved[4];
368 };
369
370 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
371
372 /* Get function capabilities (indirect 0x000A)
373 * Get device capabilities (indirect 0x000B)
374 */
375 struct i40e_aqc_list_capabilites {
376 u8 command_flags;
377 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
378 u8 pf_index;
379 u8 reserved[2];
380 __le32 count;
381 __le32 addr_high;
382 __le32 addr_low;
383 };
384
385 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
386
387 struct i40e_aqc_list_capabilities_element_resp {
388 __le16 id;
389 u8 major_rev;
390 u8 minor_rev;
391 __le32 number;
392 __le32 logical_id;
393 __le32 phys_id;
394 u8 reserved[16];
395 };
396
397 /* list of caps */
398
399 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
400 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
401 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
402 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
403 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
404 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
405 #define I40E_AQ_CAP_ID_SRIOV 0x0012
406 #define I40E_AQ_CAP_ID_VF 0x0013
407 #define I40E_AQ_CAP_ID_VMDQ 0x0014
408 #define I40E_AQ_CAP_ID_8021QBG 0x0015
409 #define I40E_AQ_CAP_ID_8021QBR 0x0016
410 #define I40E_AQ_CAP_ID_VSI 0x0017
411 #define I40E_AQ_CAP_ID_DCB 0x0018
412 #define I40E_AQ_CAP_ID_FCOE 0x0021
413 #define I40E_AQ_CAP_ID_ISCSI 0x0022
414 #define I40E_AQ_CAP_ID_RSS 0x0040
415 #define I40E_AQ_CAP_ID_RXQ 0x0041
416 #define I40E_AQ_CAP_ID_TXQ 0x0042
417 #define I40E_AQ_CAP_ID_MSIX 0x0043
418 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
419 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
420 #define I40E_AQ_CAP_ID_1588 0x0046
421 #define I40E_AQ_CAP_ID_IWARP 0x0051
422 #define I40E_AQ_CAP_ID_LED 0x0061
423 #define I40E_AQ_CAP_ID_SDP 0x0062
424 #define I40E_AQ_CAP_ID_MDIO 0x0063
425 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
426 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
427 #define I40E_AQ_CAP_ID_CEM 0x00F2
428
429 /* Set CPPM Configuration (direct 0x0103) */
430 struct i40e_aqc_cppm_configuration {
431 __le16 command_flags;
432 #define I40E_AQ_CPPM_EN_LTRC 0x0800
433 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
434 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
435 #define I40E_AQ_CPPM_EN_HPTC 0x4000
436 #define I40E_AQ_CPPM_EN_DMARC 0x8000
437 __le16 ttlx;
438 __le32 dmacr;
439 __le16 dmcth;
440 u8 hptc;
441 u8 reserved;
442 __le32 pfltrc;
443 };
444
445 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
446
447 /* Set ARP Proxy command / response (indirect 0x0104) */
448 struct i40e_aqc_arp_proxy_data {
449 __le16 command_flags;
450 #define I40E_AQ_ARP_INIT_IPV4 0x0008
451 #define I40E_AQ_ARP_UNSUP_CTL 0x0010
452 #define I40E_AQ_ARP_ENA 0x0020
453 #define I40E_AQ_ARP_ADD_IPV4 0x0040
454 #define I40E_AQ_ARP_DEL_IPV4 0x0080
455 __le16 table_id;
456 __le32 pfpm_proxyfc;
457 __le32 ip_addr;
458 u8 mac_addr[6];
459 u8 reserved[2];
460 };
461
462 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
463
464 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
465 struct i40e_aqc_ns_proxy_data {
466 __le16 table_idx_mac_addr_0;
467 __le16 table_idx_mac_addr_1;
468 __le16 table_idx_ipv6_0;
469 __le16 table_idx_ipv6_1;
470 __le16 control;
471 #define I40E_AQ_NS_PROXY_ADD_0 0x0100
472 #define I40E_AQ_NS_PROXY_DEL_0 0x0200
473 #define I40E_AQ_NS_PROXY_ADD_1 0x0400
474 #define I40E_AQ_NS_PROXY_DEL_1 0x0800
475 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
476 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
477 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
478 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
479 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
480 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
481 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
482 u8 mac_addr_0[6];
483 u8 mac_addr_1[6];
484 u8 local_mac_addr[6];
485 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
486 u8 ipv6_addr_1[16];
487 };
488
489 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
490
491 /* Manage LAA Command (0x0106) - obsolete */
492 struct i40e_aqc_mng_laa {
493 __le16 command_flags;
494 #define I40E_AQ_LAA_FLAG_WR 0x8000
495 u8 reserved[2];
496 __le32 sal;
497 __le16 sah;
498 u8 reserved2[6];
499 };
500
501 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
502
503 /* Manage MAC Address Read Command (indirect 0x0107) */
504 struct i40e_aqc_mac_address_read {
505 __le16 command_flags;
506 #define I40E_AQC_LAN_ADDR_VALID 0x10
507 #define I40E_AQC_SAN_ADDR_VALID 0x20
508 #define I40E_AQC_PORT_ADDR_VALID 0x40
509 #define I40E_AQC_WOL_ADDR_VALID 0x80
510 #define I40E_AQC_MC_MAG_EN_VALID 0x100
511 #define I40E_AQC_ADDR_VALID_MASK 0x1F0
512 u8 reserved[6];
513 __le32 addr_high;
514 __le32 addr_low;
515 };
516
517 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
518
519 struct i40e_aqc_mac_address_read_data {
520 u8 pf_lan_mac[6];
521 u8 pf_san_mac[6];
522 u8 port_mac[6];
523 u8 pf_wol_mac[6];
524 };
525
526 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
527
528 /* Manage MAC Address Write Command (0x0108) */
529 struct i40e_aqc_mac_address_write {
530 __le16 command_flags;
531 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
532 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
533 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
534 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
535 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
536
537 __le16 mac_sah;
538 __le32 mac_sal;
539 u8 reserved[8];
540 };
541
542 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
543
544 /* PXE commands (0x011x) */
545
546 /* Clear PXE Command and response (direct 0x0110) */
547 struct i40e_aqc_clear_pxe {
548 u8 rx_cnt;
549 u8 reserved[15];
550 };
551
552 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
553
554 /* Switch configuration commands (0x02xx) */
555
556 /* Used by many indirect commands that only pass an seid and a buffer in the
557 * command
558 */
559 struct i40e_aqc_switch_seid {
560 __le16 seid;
561 u8 reserved[6];
562 __le32 addr_high;
563 __le32 addr_low;
564 };
565
566 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
567
568 /* Get Switch Configuration command (indirect 0x0200)
569 * uses i40e_aqc_switch_seid for the descriptor
570 */
571 struct i40e_aqc_get_switch_config_header_resp {
572 __le16 num_reported;
573 __le16 num_total;
574 u8 reserved[12];
575 };
576
577 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
578
579 struct i40e_aqc_switch_config_element_resp {
580 u8 element_type;
581 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
582 #define I40E_AQ_SW_ELEM_TYPE_PF 2
583 #define I40E_AQ_SW_ELEM_TYPE_VF 3
584 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
585 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
586 #define I40E_AQ_SW_ELEM_TYPE_PV 16
587 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
588 #define I40E_AQ_SW_ELEM_TYPE_PA 18
589 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
590 u8 revision;
591 #define I40E_AQ_SW_ELEM_REV_1 1
592 __le16 seid;
593 __le16 uplink_seid;
594 __le16 downlink_seid;
595 u8 reserved[3];
596 u8 connection_type;
597 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
598 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
599 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
600 __le16 scheduler_id;
601 __le16 element_info;
602 };
603
604 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
605
606 /* Get Switch Configuration (indirect 0x0200)
607 * an array of elements are returned in the response buffer
608 * the first in the array is the header, remainder are elements
609 */
610 struct i40e_aqc_get_switch_config_resp {
611 struct i40e_aqc_get_switch_config_header_resp header;
612 struct i40e_aqc_switch_config_element_resp element[1];
613 };
614
615 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
616
617 /* Add Statistics (direct 0x0201)
618 * Remove Statistics (direct 0x0202)
619 */
620 struct i40e_aqc_add_remove_statistics {
621 __le16 seid;
622 __le16 vlan;
623 __le16 stat_index;
624 u8 reserved[10];
625 };
626
627 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
628
629 /* Set Port Parameters command (direct 0x0203) */
630 struct i40e_aqc_set_port_parameters {
631 __le16 command_flags;
632 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
633 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
634 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
635 __le16 bad_frame_vsi;
636 __le16 default_seid; /* reserved for command */
637 u8 reserved[10];
638 };
639
640 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
641
642 /* Get Switch Resource Allocation (indirect 0x0204) */
643 struct i40e_aqc_get_switch_resource_alloc {
644 u8 num_entries; /* reserved for command */
645 u8 reserved[7];
646 __le32 addr_high;
647 __le32 addr_low;
648 };
649
650 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
651
652 /* expect an array of these structs in the response buffer */
653 struct i40e_aqc_switch_resource_alloc_element_resp {
654 u8 resource_type;
655 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
656 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
657 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
658 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
659 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
660 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
661 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
662 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
663 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
664 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
665 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
666 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
667 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
668 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
669 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
670 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
671 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
672 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
673 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
674 u8 reserved1;
675 __le16 guaranteed;
676 __le16 total;
677 __le16 used;
678 __le16 total_unalloced;
679 u8 reserved2[6];
680 };
681
682 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
683
684 /* Add VSI (indirect 0x0210)
685 * this indirect command uses struct i40e_aqc_vsi_properties_data
686 * as the indirect buffer (128 bytes)
687 *
688 * Update VSI (indirect 0x211)
689 * uses the same data structure as Add VSI
690 *
691 * Get VSI (indirect 0x0212)
692 * uses the same completion and data structure as Add VSI
693 */
694 struct i40e_aqc_add_get_update_vsi {
695 __le16 uplink_seid;
696 u8 connection_type;
697 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
698 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
699 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
700 u8 reserved1;
701 u8 vf_id;
702 u8 reserved2;
703 __le16 vsi_flags;
704 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
705 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
706 #define I40E_AQ_VSI_TYPE_VF 0x0
707 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
708 #define I40E_AQ_VSI_TYPE_PF 0x2
709 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
710 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
711 __le32 addr_high;
712 __le32 addr_low;
713 };
714
715 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
716
717 struct i40e_aqc_add_get_update_vsi_completion {
718 __le16 seid;
719 __le16 vsi_number;
720 __le16 vsi_used;
721 __le16 vsi_free;
722 __le32 addr_high;
723 __le32 addr_low;
724 };
725
726 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
727
728 struct i40e_aqc_vsi_properties_data {
729 /* first 96 byte are written by SW */
730 __le16 valid_sections;
731 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
732 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
733 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
734 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
735 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
736 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
737 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
738 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
739 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
740 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
741 /* switch section */
742 __le16 switch_id; /* 12bit id combined with flags below */
743 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
744 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
745 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
746 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
747 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
748 u8 sw_reserved[2];
749 /* security section */
750 u8 sec_flags;
751 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
752 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
753 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
754 u8 sec_reserved;
755 /* VLAN section */
756 __le16 pvid; /* VLANS include priority bits */
757 __le16 fcoe_pvid;
758 u8 port_vlan_flags;
759 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
760 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
761 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
762 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
763 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
764 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
765 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
766 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
767 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
768 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
769 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
770 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
771 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
772 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
773 u8 pvlan_reserved[3];
774 /* ingress egress up sections */
775 __le32 ingress_table; /* bitmap, 3 bits per up */
776 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
777 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
778 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
779 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
780 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
781 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
782 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
783 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
784 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
785 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
786 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
787 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
788 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
789 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
790 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
791 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
792 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
793 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
794 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
795 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
796 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
797 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
798 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
799 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
800 __le32 egress_table; /* same defines as for ingress table */
801 /* cascaded PV section */
802 __le16 cas_pv_tag;
803 u8 cas_pv_flags;
804 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
805 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
806 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
807 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
808 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
809 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
810 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
811 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
812 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
813 u8 cas_pv_reserved;
814 /* queue mapping section */
815 __le16 mapping_flags;
816 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
817 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
818 __le16 queue_mapping[16];
819 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
820 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
821 __le16 tc_mapping[8];
822 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
823 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
824 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
825 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
826 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
827 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
828 /* queueing option section */
829 u8 queueing_opt_flags;
830 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
831 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
832 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
833 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
834 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
835 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
836 u8 queueing_opt_reserved[3];
837 /* scheduler section */
838 u8 up_enable_bits;
839 u8 sched_reserved;
840 /* outer up section */
841 __le32 outer_up_table; /* same structure and defines as ingress tbl */
842 u8 cmd_reserved[8];
843 /* last 32 bytes are written by FW */
844 __le16 qs_handle[8];
845 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
846 __le16 stat_counter_idx;
847 __le16 sched_id;
848 u8 resp_reserved[12];
849 };
850
851 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
852
853 /* Add Port Virtualizer (direct 0x0220)
854 * also used for update PV (direct 0x0221) but only flags are used
855 * (IS_CTRL_PORT only works on add PV)
856 */
857 struct i40e_aqc_add_update_pv {
858 __le16 command_flags;
859 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
860 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
861 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
862 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
863 __le16 uplink_seid;
864 __le16 connected_seid;
865 u8 reserved[10];
866 };
867
868 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
869
870 struct i40e_aqc_add_update_pv_completion {
871 /* reserved for update; for add also encodes error if rc == ENOSPC */
872 __le16 pv_seid;
873 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
874 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
875 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
876 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
877 u8 reserved[14];
878 };
879
880 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
881
882 /* Get PV Params (direct 0x0222)
883 * uses i40e_aqc_switch_seid for the descriptor
884 */
885
886 struct i40e_aqc_get_pv_params_completion {
887 __le16 seid;
888 __le16 default_stag;
889 __le16 pv_flags; /* same flags as add_pv */
890 #define I40E_AQC_GET_PV_PV_TYPE 0x1
891 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
892 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
893 u8 reserved[8];
894 __le16 default_port_seid;
895 };
896
897 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
898
899 /* Add VEB (direct 0x0230) */
900 struct i40e_aqc_add_veb {
901 __le16 uplink_seid;
902 __le16 downlink_seid;
903 __le16 veb_flags;
904 #define I40E_AQC_ADD_VEB_FLOATING 0x1
905 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
906 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
907 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
908 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
909 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
910 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8
911 u8 enable_tcs;
912 u8 reserved[9];
913 };
914
915 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
916
917 struct i40e_aqc_add_veb_completion {
918 u8 reserved[6];
919 __le16 switch_seid;
920 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
921 __le16 veb_seid;
922 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
923 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
924 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
925 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
926 __le16 statistic_index;
927 __le16 vebs_used;
928 __le16 vebs_free;
929 };
930
931 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
932
933 /* Get VEB Parameters (direct 0x0232)
934 * uses i40e_aqc_switch_seid for the descriptor
935 */
936 struct i40e_aqc_get_veb_parameters_completion {
937 __le16 seid;
938 __le16 switch_id;
939 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
940 __le16 statistic_index;
941 __le16 vebs_used;
942 __le16 vebs_free;
943 u8 reserved[4];
944 };
945
946 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
947
948 /* Delete Element (direct 0x0243)
949 * uses the generic i40e_aqc_switch_seid
950 */
951
952 /* Add MAC-VLAN (indirect 0x0250) */
953
954 /* used for the command for most vlan commands */
955 struct i40e_aqc_macvlan {
956 __le16 num_addresses;
957 __le16 seid[3];
958 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
959 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
960 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
961 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
962 __le32 addr_high;
963 __le32 addr_low;
964 };
965
966 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
967
968 /* indirect data for command and response */
969 struct i40e_aqc_add_macvlan_element_data {
970 u8 mac_addr[6];
971 __le16 vlan_tag;
972 __le16 flags;
973 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
974 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
975 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
976 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
977 __le16 queue_number;
978 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
979 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
980 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
981 /* response section */
982 u8 match_method;
983 #define I40E_AQC_MM_PERFECT_MATCH 0x01
984 #define I40E_AQC_MM_HASH_MATCH 0x02
985 #define I40E_AQC_MM_ERR_NO_RES 0xFF
986 u8 reserved1[3];
987 };
988
989 struct i40e_aqc_add_remove_macvlan_completion {
990 __le16 perfect_mac_used;
991 __le16 perfect_mac_free;
992 __le16 unicast_hash_free;
993 __le16 multicast_hash_free;
994 __le32 addr_high;
995 __le32 addr_low;
996 };
997
998 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
999
1000 /* Remove MAC-VLAN (indirect 0x0251)
1001 * uses i40e_aqc_macvlan for the descriptor
1002 * data points to an array of num_addresses of elements
1003 */
1004
1005 struct i40e_aqc_remove_macvlan_element_data {
1006 u8 mac_addr[6];
1007 __le16 vlan_tag;
1008 u8 flags;
1009 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1010 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1011 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1012 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1013 u8 reserved[3];
1014 /* reply section */
1015 u8 error_code;
1016 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1017 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1018 u8 reply_reserved[3];
1019 };
1020
1021 /* Add VLAN (indirect 0x0252)
1022 * Remove VLAN (indirect 0x0253)
1023 * use the generic i40e_aqc_macvlan for the command
1024 */
1025 struct i40e_aqc_add_remove_vlan_element_data {
1026 __le16 vlan_tag;
1027 u8 vlan_flags;
1028 /* flags for add VLAN */
1029 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1030 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1031 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1032 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1033 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1034 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1035 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1036 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1037 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1038 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1039 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1040 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1041 /* flags for remove VLAN */
1042 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1043 u8 reserved;
1044 u8 result;
1045 /* flags for add VLAN */
1046 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1047 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1048 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1049 /* flags for remove VLAN */
1050 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1051 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1052 u8 reserved1[3];
1053 };
1054
1055 struct i40e_aqc_add_remove_vlan_completion {
1056 u8 reserved[4];
1057 __le16 vlans_used;
1058 __le16 vlans_free;
1059 __le32 addr_high;
1060 __le32 addr_low;
1061 };
1062
1063 /* Set VSI Promiscuous Modes (direct 0x0254) */
1064 struct i40e_aqc_set_vsi_promiscuous_modes {
1065 __le16 promiscuous_flags;
1066 __le16 valid_flags;
1067 /* flags used for both fields above */
1068 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1069 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1070 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1071 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1072 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1073 __le16 seid;
1074 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1075 __le16 vlan_tag;
1076 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1077 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1078 u8 reserved[8];
1079 };
1080
1081 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1082
1083 /* Add S/E-tag command (direct 0x0255)
1084 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1085 */
1086 struct i40e_aqc_add_tag {
1087 __le16 flags;
1088 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1089 __le16 seid;
1090 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1091 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1092 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1093 __le16 tag;
1094 __le16 queue_number;
1095 u8 reserved[8];
1096 };
1097
1098 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1099
1100 struct i40e_aqc_add_remove_tag_completion {
1101 u8 reserved[12];
1102 __le16 tags_used;
1103 __le16 tags_free;
1104 };
1105
1106 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1107
1108 /* Remove S/E-tag command (direct 0x0256)
1109 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1110 */
1111 struct i40e_aqc_remove_tag {
1112 __le16 seid;
1113 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1114 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1115 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1116 __le16 tag;
1117 u8 reserved[12];
1118 };
1119
1120 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1121
1122 /* Add multicast E-Tag (direct 0x0257)
1123 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1124 * and no external data
1125 */
1126 struct i40e_aqc_add_remove_mcast_etag {
1127 __le16 pv_seid;
1128 __le16 etag;
1129 u8 num_unicast_etags;
1130 u8 reserved[3];
1131 __le32 addr_high; /* address of array of 2-byte s-tags */
1132 __le32 addr_low;
1133 };
1134
1135 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1136
1137 struct i40e_aqc_add_remove_mcast_etag_completion {
1138 u8 reserved[4];
1139 __le16 mcast_etags_used;
1140 __le16 mcast_etags_free;
1141 __le32 addr_high;
1142 __le32 addr_low;
1143
1144 };
1145
1146 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1147
1148 /* Update S/E-Tag (direct 0x0259) */
1149 struct i40e_aqc_update_tag {
1150 __le16 seid;
1151 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1152 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1153 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1154 __le16 old_tag;
1155 __le16 new_tag;
1156 u8 reserved[10];
1157 };
1158
1159 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1160
1161 struct i40e_aqc_update_tag_completion {
1162 u8 reserved[12];
1163 __le16 tags_used;
1164 __le16 tags_free;
1165 };
1166
1167 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1168
1169 /* Add Control Packet filter (direct 0x025A)
1170 * Remove Control Packet filter (direct 0x025B)
1171 * uses the i40e_aqc_add_oveb_cloud,
1172 * and the generic direct completion structure
1173 */
1174 struct i40e_aqc_add_remove_control_packet_filter {
1175 u8 mac[6];
1176 __le16 etype;
1177 __le16 flags;
1178 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1179 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1180 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1181 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1182 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1183 __le16 seid;
1184 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1185 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1186 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1187 __le16 queue;
1188 u8 reserved[2];
1189 };
1190
1191 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1192
1193 struct i40e_aqc_add_remove_control_packet_filter_completion {
1194 __le16 mac_etype_used;
1195 __le16 etype_used;
1196 __le16 mac_etype_free;
1197 __le16 etype_free;
1198 u8 reserved[8];
1199 };
1200
1201 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1202
1203 /* Add Cloud filters (indirect 0x025C)
1204 * Remove Cloud filters (indirect 0x025D)
1205 * uses the i40e_aqc_add_remove_cloud_filters,
1206 * and the generic indirect completion structure
1207 */
1208 struct i40e_aqc_add_remove_cloud_filters {
1209 u8 num_filters;
1210 u8 reserved;
1211 __le16 seid;
1212 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1213 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1214 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1215 u8 reserved2[4];
1216 __le32 addr_high;
1217 __le32 addr_low;
1218 };
1219
1220 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1221
1222 struct i40e_aqc_add_remove_cloud_filters_element_data {
1223 u8 outer_mac[6];
1224 u8 inner_mac[6];
1225 __le16 inner_vlan;
1226 union {
1227 struct {
1228 u8 reserved[12];
1229 u8 data[4];
1230 } v4;
1231 struct {
1232 u8 data[16];
1233 } v6;
1234 } ipaddr;
1235 __le16 flags;
1236 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1237 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1238 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1239 /* 0x0000 reserved */
1240 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1241 /* 0x0002 reserved */
1242 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1243 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1244 /* 0x0005 reserved */
1245 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1246 /* 0x0007 reserved */
1247 /* 0x0008 reserved */
1248 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1249 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1250 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1251 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1252
1253 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1254 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1255 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1256 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1257 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1258
1259 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1260 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1261 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0
1262 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1263 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2
1264 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1265
1266 __le32 tenant_id;
1267 u8 reserved[4];
1268 __le16 queue_number;
1269 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1270 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1271 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1272 u8 reserved2[14];
1273 /* response section */
1274 u8 allocation_result;
1275 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1276 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1277 u8 response_reserved[7];
1278 };
1279
1280 struct i40e_aqc_remove_cloud_filters_completion {
1281 __le16 perfect_ovlan_used;
1282 __le16 perfect_ovlan_free;
1283 __le16 vlan_used;
1284 __le16 vlan_free;
1285 __le32 addr_high;
1286 __le32 addr_low;
1287 };
1288
1289 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1290
1291 /* Add Mirror Rule (indirect or direct 0x0260)
1292 * Delete Mirror Rule (indirect or direct 0x0261)
1293 * note: some rule types (4,5) do not use an external buffer.
1294 * take care to set the flags correctly.
1295 */
1296 struct i40e_aqc_add_delete_mirror_rule {
1297 __le16 seid;
1298 __le16 rule_type;
1299 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1300 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1301 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1302 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1303 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1304 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1305 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1306 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1307 __le16 num_entries;
1308 __le16 destination; /* VSI for add, rule id for delete */
1309 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1310 __le32 addr_low;
1311 };
1312
1313 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1314
1315 struct i40e_aqc_add_delete_mirror_rule_completion {
1316 u8 reserved[2];
1317 __le16 rule_id; /* only used on add */
1318 __le16 mirror_rules_used;
1319 __le16 mirror_rules_free;
1320 __le32 addr_high;
1321 __le32 addr_low;
1322 };
1323
1324 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1325
1326 /* DCB 0x03xx*/
1327
1328 /* PFC Ignore (direct 0x0301)
1329 * the command and response use the same descriptor structure
1330 */
1331 struct i40e_aqc_pfc_ignore {
1332 u8 tc_bitmap;
1333 u8 command_flags; /* unused on response */
1334 #define I40E_AQC_PFC_IGNORE_SET 0x80
1335 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1336 u8 reserved[14];
1337 };
1338
1339 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1340
1341 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1342 * with no parameters
1343 */
1344
1345 /* TX scheduler 0x04xx */
1346
1347 /* Almost all the indirect commands use
1348 * this generic struct to pass the SEID in param0
1349 */
1350 struct i40e_aqc_tx_sched_ind {
1351 __le16 vsi_seid;
1352 u8 reserved[6];
1353 __le32 addr_high;
1354 __le32 addr_low;
1355 };
1356
1357 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1358
1359 /* Several commands respond with a set of queue set handles */
1360 struct i40e_aqc_qs_handles_resp {
1361 __le16 qs_handles[8];
1362 };
1363
1364 /* Configure VSI BW limits (direct 0x0400) */
1365 struct i40e_aqc_configure_vsi_bw_limit {
1366 __le16 vsi_seid;
1367 u8 reserved[2];
1368 __le16 credit;
1369 u8 reserved1[2];
1370 u8 max_credit; /* 0-3, limit = 2^max */
1371 u8 reserved2[7];
1372 };
1373
1374 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1375
1376 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1377 * responds with i40e_aqc_qs_handles_resp
1378 */
1379 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1380 u8 tc_valid_bits;
1381 u8 reserved[15];
1382 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1383
1384 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1385 __le16 tc_bw_max[2];
1386 u8 reserved1[28];
1387 };
1388
1389 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1390
1391 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1392 * responds with i40e_aqc_qs_handles_resp
1393 */
1394 struct i40e_aqc_configure_vsi_tc_bw_data {
1395 u8 tc_valid_bits;
1396 u8 reserved[3];
1397 u8 tc_bw_credits[8];
1398 u8 reserved1[4];
1399 __le16 qs_handles[8];
1400 };
1401
1402 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1403
1404 /* Query vsi bw configuration (indirect 0x0408) */
1405 struct i40e_aqc_query_vsi_bw_config_resp {
1406 u8 tc_valid_bits;
1407 u8 tc_suspended_bits;
1408 u8 reserved[14];
1409 __le16 qs_handles[8];
1410 u8 reserved1[4];
1411 __le16 port_bw_limit;
1412 u8 reserved2[2];
1413 u8 max_bw; /* 0-3, limit = 2^max */
1414 u8 reserved3[23];
1415 };
1416
1417 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1418
1419 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1420 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1421 u8 tc_valid_bits;
1422 u8 reserved[3];
1423 u8 share_credits[8];
1424 __le16 credits[8];
1425
1426 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1427 __le16 tc_bw_max[2];
1428 };
1429
1430 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1431
1432 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1433 struct i40e_aqc_configure_switching_comp_bw_limit {
1434 __le16 seid;
1435 u8 reserved[2];
1436 __le16 credit;
1437 u8 reserved1[2];
1438 u8 max_bw; /* 0-3, limit = 2^max */
1439 u8 reserved2[7];
1440 };
1441
1442 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1443
1444 /* Enable Physical Port ETS (indirect 0x0413)
1445 * Modify Physical Port ETS (indirect 0x0414)
1446 * Disable Physical Port ETS (indirect 0x0415)
1447 */
1448 struct i40e_aqc_configure_switching_comp_ets_data {
1449 u8 reserved[4];
1450 u8 tc_valid_bits;
1451 u8 seepage;
1452 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1453 u8 tc_strict_priority_flags;
1454 u8 reserved1[17];
1455 u8 tc_bw_share_credits[8];
1456 u8 reserved2[96];
1457 };
1458
1459 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1460
1461 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1462 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1463 u8 tc_valid_bits;
1464 u8 reserved[15];
1465 __le16 tc_bw_credit[8];
1466
1467 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1468 __le16 tc_bw_max[2];
1469 u8 reserved1[28];
1470 };
1471
1472 I40E_CHECK_STRUCT_LEN(0x40,
1473 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1474
1475 /* Configure Switching Component Bandwidth Allocation per Tc
1476 * (indirect 0x0417)
1477 */
1478 struct i40e_aqc_configure_switching_comp_bw_config_data {
1479 u8 tc_valid_bits;
1480 u8 reserved[2];
1481 u8 absolute_credits; /* bool */
1482 u8 tc_bw_share_credits[8];
1483 u8 reserved1[20];
1484 };
1485
1486 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1487
1488 /* Query Switching Component Configuration (indirect 0x0418) */
1489 struct i40e_aqc_query_switching_comp_ets_config_resp {
1490 u8 tc_valid_bits;
1491 u8 reserved[35];
1492 __le16 port_bw_limit;
1493 u8 reserved1[2];
1494 u8 tc_bw_max; /* 0-3, limit = 2^max */
1495 u8 reserved2[23];
1496 };
1497
1498 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1499
1500 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1501 struct i40e_aqc_query_port_ets_config_resp {
1502 u8 reserved[4];
1503 u8 tc_valid_bits;
1504 u8 reserved1;
1505 u8 tc_strict_priority_bits;
1506 u8 reserved2;
1507 u8 tc_bw_share_credits[8];
1508 __le16 tc_bw_limits[8];
1509
1510 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1511 __le16 tc_bw_max[2];
1512 u8 reserved3[32];
1513 };
1514
1515 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1516
1517 /* Query Switching Component Bandwidth Allocation per Traffic Type
1518 * (indirect 0x041A)
1519 */
1520 struct i40e_aqc_query_switching_comp_bw_config_resp {
1521 u8 tc_valid_bits;
1522 u8 reserved[2];
1523 u8 absolute_credits_enable; /* bool */
1524 u8 tc_bw_share_credits[8];
1525 __le16 tc_bw_limits[8];
1526
1527 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1528 __le16 tc_bw_max[2];
1529 };
1530
1531 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1532
1533 /* Suspend/resume port TX traffic
1534 * (direct 0x041B and 0x041C) uses the generic SEID struct
1535 */
1536
1537 /* Configure partition BW
1538 * (indirect 0x041D)
1539 */
1540 struct i40e_aqc_configure_partition_bw_data {
1541 __le16 pf_valid_bits;
1542 u8 min_bw[16]; /* guaranteed bandwidth */
1543 u8 max_bw[16]; /* bandwidth limit */
1544 };
1545
1546 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1547
1548 /* Get and set the active HMC resource profile and status.
1549 * (direct 0x0500) and (direct 0x0501)
1550 */
1551 struct i40e_aq_get_set_hmc_resource_profile {
1552 u8 pm_profile;
1553 u8 pe_vf_enabled;
1554 u8 reserved[14];
1555 };
1556
1557 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1558
1559 enum i40e_aq_hmc_profile {
1560 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1561 I40E_HMC_PROFILE_DEFAULT = 1,
1562 I40E_HMC_PROFILE_FAVOR_VF = 2,
1563 I40E_HMC_PROFILE_EQUAL = 3,
1564 };
1565
1566 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1567 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1568
1569 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1570
1571 /* set in param0 for get phy abilities to report qualified modules */
1572 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1573 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1574
1575 enum i40e_aq_phy_type {
1576 I40E_PHY_TYPE_SGMII = 0x0,
1577 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1578 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1579 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1580 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1581 I40E_PHY_TYPE_XAUI = 0x5,
1582 I40E_PHY_TYPE_XFI = 0x6,
1583 I40E_PHY_TYPE_SFI = 0x7,
1584 I40E_PHY_TYPE_XLAUI = 0x8,
1585 I40E_PHY_TYPE_XLPPI = 0x9,
1586 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1587 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1588 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1589 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1590 I40E_PHY_TYPE_100BASE_TX = 0x11,
1591 I40E_PHY_TYPE_1000BASE_T = 0x12,
1592 I40E_PHY_TYPE_10GBASE_T = 0x13,
1593 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1594 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1595 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1596 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1597 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1598 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1599 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1600 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1601 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1602 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1603 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1604 I40E_PHY_TYPE_MAX
1605 };
1606
1607 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1608 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1609 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1610 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1611 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1612
1613 enum i40e_aq_link_speed {
1614 I40E_LINK_SPEED_UNKNOWN = 0,
1615 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1616 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1617 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1618 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1619 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1620 };
1621
1622 struct i40e_aqc_module_desc {
1623 u8 oui[3];
1624 u8 reserved1;
1625 u8 part_number[16];
1626 u8 revision[4];
1627 u8 reserved2[8];
1628 };
1629
1630 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1631
1632 struct i40e_aq_get_phy_abilities_resp {
1633 __le32 phy_type; /* bitmap using the above enum for offsets */
1634 u8 link_speed; /* bitmap using the above enum bit patterns */
1635 u8 abilities;
1636 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1637 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1638 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1639 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1640 #define I40E_AQ_PHY_AN_ENABLED 0x10
1641 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1642 __le16 eee_capability;
1643 #define I40E_AQ_EEE_100BASE_TX 0x0002
1644 #define I40E_AQ_EEE_1000BASE_T 0x0004
1645 #define I40E_AQ_EEE_10GBASE_T 0x0008
1646 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1647 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1648 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1649 __le32 eeer_val;
1650 u8 d3_lpan;
1651 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1652 u8 reserved[3];
1653 u8 phy_id[4];
1654 u8 module_type[3];
1655 u8 qualified_module_count;
1656 #define I40E_AQ_PHY_MAX_QMS 16
1657 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1658 };
1659
1660 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1661
1662 /* Set PHY Config (direct 0x0601) */
1663 struct i40e_aq_set_phy_config { /* same bits as above in all */
1664 __le32 phy_type;
1665 u8 link_speed;
1666 u8 abilities;
1667 /* bits 0-2 use the values from get_phy_abilities_resp */
1668 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1669 #define I40E_AQ_PHY_ENABLE_AN 0x10
1670 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1671 __le16 eee_capability;
1672 __le32 eeer;
1673 u8 low_power_ctrl;
1674 u8 reserved[3];
1675 };
1676
1677 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1678
1679 /* Set MAC Config command data structure (direct 0x0603) */
1680 struct i40e_aq_set_mac_config {
1681 __le16 max_frame_size;
1682 u8 params;
1683 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1684 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1685 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1686 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1687 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1688 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1689 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1690 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1691 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1692 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1693 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1694 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1695 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1696 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1697 u8 tx_timer_priority; /* bitmap */
1698 __le16 tx_timer_value;
1699 __le16 fc_refresh_threshold;
1700 u8 reserved[8];
1701 };
1702
1703 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1704
1705 /* Restart Auto-Negotiation (direct 0x605) */
1706 struct i40e_aqc_set_link_restart_an {
1707 u8 command;
1708 #define I40E_AQ_PHY_RESTART_AN 0x02
1709 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1710 u8 reserved[15];
1711 };
1712
1713 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1714
1715 /* Get Link Status cmd & response data structure (direct 0x0607) */
1716 struct i40e_aqc_get_link_status {
1717 __le16 command_flags; /* only field set on command */
1718 #define I40E_AQ_LSE_MASK 0x3
1719 #define I40E_AQ_LSE_NOP 0x0
1720 #define I40E_AQ_LSE_DISABLE 0x2
1721 #define I40E_AQ_LSE_ENABLE 0x3
1722 /* only response uses this flag */
1723 #define I40E_AQ_LSE_IS_ENABLED 0x1
1724 u8 phy_type; /* i40e_aq_phy_type */
1725 u8 link_speed; /* i40e_aq_link_speed */
1726 u8 link_info;
1727 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1728 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1729 #define I40E_AQ_LINK_FAULT 0x02
1730 #define I40E_AQ_LINK_FAULT_TX 0x04
1731 #define I40E_AQ_LINK_FAULT_RX 0x08
1732 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1733 #define I40E_AQ_LINK_UP_PORT 0x20
1734 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1735 #define I40E_AQ_SIGNAL_DETECT 0x80
1736 u8 an_info;
1737 #define I40E_AQ_AN_COMPLETED 0x01
1738 #define I40E_AQ_LP_AN_ABILITY 0x02
1739 #define I40E_AQ_PD_FAULT 0x04
1740 #define I40E_AQ_FEC_EN 0x08
1741 #define I40E_AQ_PHY_LOW_POWER 0x10
1742 #define I40E_AQ_LINK_PAUSE_TX 0x20
1743 #define I40E_AQ_LINK_PAUSE_RX 0x40
1744 #define I40E_AQ_QUALIFIED_MODULE 0x80
1745 u8 ext_info;
1746 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1747 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1748 #define I40E_AQ_LINK_TX_SHIFT 0x02
1749 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1750 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1751 #define I40E_AQ_LINK_TX_DRAINED 0x01
1752 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1753 #define I40E_AQ_LINK_FORCED_40G 0x10
1754 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1755 __le16 max_frame_size;
1756 u8 config;
1757 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1758 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1759 u8 reserved[5];
1760 };
1761
1762 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1763
1764 /* Set event mask command (direct 0x613) */
1765 struct i40e_aqc_set_phy_int_mask {
1766 u8 reserved[8];
1767 __le16 event_mask;
1768 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1769 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1770 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1771 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1772 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1773 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1774 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1775 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1776 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1777 u8 reserved1[6];
1778 };
1779
1780 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1781
1782 /* Get Local AN advt register (direct 0x0614)
1783 * Set Local AN advt register (direct 0x0615)
1784 * Get Link Partner AN advt register (direct 0x0616)
1785 */
1786 struct i40e_aqc_an_advt_reg {
1787 __le32 local_an_reg0;
1788 __le16 local_an_reg1;
1789 u8 reserved[10];
1790 };
1791
1792 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1793
1794 /* Set Loopback mode (0x0618) */
1795 struct i40e_aqc_set_lb_mode {
1796 __le16 lb_mode;
1797 #define I40E_AQ_LB_PHY_LOCAL 0x01
1798 #define I40E_AQ_LB_PHY_REMOTE 0x02
1799 #define I40E_AQ_LB_MAC_LOCAL 0x04
1800 u8 reserved[14];
1801 };
1802
1803 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1804
1805 /* Set PHY Debug command (0x0622) */
1806 struct i40e_aqc_set_phy_debug {
1807 u8 command_flags;
1808 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1809 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1810 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1811 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1812 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1813 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1814 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1815 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1816 u8 reserved[15];
1817 };
1818
1819 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1820
1821 enum i40e_aq_phy_reg_type {
1822 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1823 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1824 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1825 };
1826
1827 /* NVM Read command (indirect 0x0701)
1828 * NVM Erase commands (direct 0x0702)
1829 * NVM Update commands (indirect 0x0703)
1830 */
1831 struct i40e_aqc_nvm_update {
1832 u8 command_flags;
1833 #define I40E_AQ_NVM_LAST_CMD 0x01
1834 #define I40E_AQ_NVM_FLASH_ONLY 0x80
1835 u8 module_pointer;
1836 __le16 length;
1837 __le32 offset;
1838 __le32 addr_high;
1839 __le32 addr_low;
1840 };
1841
1842 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1843
1844 /* NVM Config Read (indirect 0x0704) */
1845 struct i40e_aqc_nvm_config_read {
1846 __le16 cmd_flags;
1847 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1848 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
1849 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
1850 __le16 element_count;
1851 __le16 element_id; /* Feature/field ID */
1852 __le16 element_id_msw; /* MSWord of field ID */
1853 __le32 address_high;
1854 __le32 address_low;
1855 };
1856
1857 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1858
1859 /* NVM Config Write (indirect 0x0705) */
1860 struct i40e_aqc_nvm_config_write {
1861 __le16 cmd_flags;
1862 __le16 element_count;
1863 u8 reserved[4];
1864 __le32 address_high;
1865 __le32 address_low;
1866 };
1867
1868 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1869
1870 /* Used for 0x0704 as well as for 0x0705 commands */
1871 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
1872 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
1873 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1874 #define I40E_AQ_ANVM_FEATURE 0
1875 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
1876 struct i40e_aqc_nvm_config_data_feature {
1877 __le16 feature_id;
1878 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
1879 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
1880 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
1881 __le16 feature_options;
1882 __le16 feature_selection;
1883 };
1884
1885 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1886
1887 struct i40e_aqc_nvm_config_data_immediate_field {
1888 __le32 field_id;
1889 __le32 field_value;
1890 __le16 field_options;
1891 __le16 reserved;
1892 };
1893
1894 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1895
1896 /* OEM Post Update (indirect 0x0720)
1897 * no command data struct used
1898 */
1899 struct i40e_aqc_nvm_oem_post_update {
1900 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
1901 u8 sel_data;
1902 u8 reserved[7];
1903 };
1904
1905 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1906
1907 struct i40e_aqc_nvm_oem_post_update_buffer {
1908 u8 str_len;
1909 u8 dev_addr;
1910 __le16 eeprom_addr;
1911 u8 data[36];
1912 };
1913
1914 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1915
1916 /* Send to PF command (indirect 0x0801) id is only used by PF
1917 * Send to VF command (indirect 0x0802) id is only used by PF
1918 * Send to Peer PF command (indirect 0x0803)
1919 */
1920 struct i40e_aqc_pf_vf_message {
1921 __le32 id;
1922 u8 reserved[4];
1923 __le32 addr_high;
1924 __le32 addr_low;
1925 };
1926
1927 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1928
1929 /* Alternate structure */
1930
1931 /* Direct write (direct 0x0900)
1932 * Direct read (direct 0x0902)
1933 */
1934 struct i40e_aqc_alternate_write {
1935 __le32 address0;
1936 __le32 data0;
1937 __le32 address1;
1938 __le32 data1;
1939 };
1940
1941 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1942
1943 /* Indirect write (indirect 0x0901)
1944 * Indirect read (indirect 0x0903)
1945 */
1946
1947 struct i40e_aqc_alternate_ind_write {
1948 __le32 address;
1949 __le32 length;
1950 __le32 addr_high;
1951 __le32 addr_low;
1952 };
1953
1954 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1955
1956 /* Done alternate write (direct 0x0904)
1957 * uses i40e_aq_desc
1958 */
1959 struct i40e_aqc_alternate_write_done {
1960 __le16 cmd_flags;
1961 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
1962 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
1963 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
1964 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
1965 u8 reserved[14];
1966 };
1967
1968 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1969
1970 /* Set OEM mode (direct 0x0905) */
1971 struct i40e_aqc_alternate_set_mode {
1972 __le32 mode;
1973 #define I40E_AQ_ALTERNATE_MODE_NONE 0
1974 #define I40E_AQ_ALTERNATE_MODE_OEM 1
1975 u8 reserved[12];
1976 };
1977
1978 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1979
1980 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1981
1982 /* async events 0x10xx */
1983
1984 /* Lan Queue Overflow Event (direct, 0x1001) */
1985 struct i40e_aqc_lan_overflow {
1986 __le32 prtdcb_rupto;
1987 __le32 otx_ctl;
1988 u8 reserved[8];
1989 };
1990
1991 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
1992
1993 /* Get LLDP MIB (indirect 0x0A00) */
1994 struct i40e_aqc_lldp_get_mib {
1995 u8 type;
1996 u8 reserved1;
1997 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
1998 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
1999 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2000 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2001 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2002 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2003 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2004 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2005 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2006 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2007 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2008 __le16 local_len;
2009 __le16 remote_len;
2010 u8 reserved2[2];
2011 __le32 addr_high;
2012 __le32 addr_low;
2013 };
2014
2015 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2016
2017 /* Configure LLDP MIB Change Event (direct 0x0A01)
2018 * also used for the event (with type in the command field)
2019 */
2020 struct i40e_aqc_lldp_update_mib {
2021 u8 command;
2022 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2023 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2024 u8 reserved[7];
2025 __le32 addr_high;
2026 __le32 addr_low;
2027 };
2028
2029 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2030
2031 /* Add LLDP TLV (indirect 0x0A02)
2032 * Delete LLDP TLV (indirect 0x0A04)
2033 */
2034 struct i40e_aqc_lldp_add_tlv {
2035 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2036 u8 reserved1[1];
2037 __le16 len;
2038 u8 reserved2[4];
2039 __le32 addr_high;
2040 __le32 addr_low;
2041 };
2042
2043 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2044
2045 /* Update LLDP TLV (indirect 0x0A03) */
2046 struct i40e_aqc_lldp_update_tlv {
2047 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2048 u8 reserved;
2049 __le16 old_len;
2050 __le16 new_offset;
2051 __le16 new_len;
2052 __le32 addr_high;
2053 __le32 addr_low;
2054 };
2055
2056 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2057
2058 /* Stop LLDP (direct 0x0A05) */
2059 struct i40e_aqc_lldp_stop {
2060 u8 command;
2061 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2062 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2063 u8 reserved[15];
2064 };
2065
2066 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2067
2068 /* Start LLDP (direct 0x0A06) */
2069
2070 struct i40e_aqc_lldp_start {
2071 u8 command;
2072 #define I40E_AQ_LLDP_AGENT_START 0x1
2073 u8 reserved[15];
2074 };
2075
2076 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2077
2078 /* Get CEE DCBX Oper Config (0x0A07)
2079 * uses the generic descriptor struct
2080 * returns below as indirect response
2081 */
2082
2083 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2084 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2085 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2086 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2087 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2088 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2089
2090 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2091 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2092 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2093 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2094 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2095 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2096 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2097 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2098 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2099 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2100 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2101 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2102
2103 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2104 * word boundary layout issues, which the Linux compilers silently deal
2105 * with by adding padding, making the actual struct larger than designed.
2106 * However, the FW compiler for the NIC is less lenient and complains
2107 * about the struct. Hence, the struct defined here has an extra byte in
2108 * fields reserved3 and reserved4 to directly acknowledge that padding,
2109 * and the new length is used in the length check macro.
2110 */
2111 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2112 u8 reserved1;
2113 u8 oper_num_tc;
2114 u8 oper_prio_tc[4];
2115 u8 reserved2;
2116 u8 oper_tc_bw[8];
2117 u8 oper_pfc_en;
2118 u8 reserved3[2];
2119 __le16 oper_app_prio;
2120 u8 reserved4[2];
2121 __le16 tlv_status;
2122 };
2123
2124 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2125
2126 struct i40e_aqc_get_cee_dcb_cfg_resp {
2127 u8 oper_num_tc;
2128 u8 oper_prio_tc[4];
2129 u8 oper_tc_bw[8];
2130 u8 oper_pfc_en;
2131 __le16 oper_app_prio;
2132 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2133 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2134 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2135 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2136 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2137 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2138 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2139 __le32 tlv_status;
2140 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2141 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2142 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2143 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2144 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2145 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2146 u8 reserved[12];
2147 };
2148
2149 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2150
2151 /* Set Local LLDP MIB (indirect 0x0A08)
2152 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2153 */
2154 struct i40e_aqc_lldp_set_local_mib {
2155 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2156 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2157 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2158 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2159 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2160 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2161 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2162 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2163 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2164 u8 type;
2165 u8 reserved0;
2166 __le16 length;
2167 u8 reserved1[4];
2168 __le32 address_high;
2169 __le32 address_low;
2170 };
2171
2172 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2173
2174 /* Stop/Start LLDP Agent (direct 0x0A09)
2175 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2176 */
2177 struct i40e_aqc_lldp_stop_start_specific_agent {
2178 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2179 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2180 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2181 u8 command;
2182 u8 reserved[15];
2183 };
2184
2185 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2186
2187 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2188 struct i40e_aqc_add_udp_tunnel {
2189 __le16 udp_port;
2190 u8 reserved0[3];
2191 u8 protocol_type;
2192 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2193 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2194 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2195 u8 reserved1[10];
2196 };
2197
2198 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2199
2200 struct i40e_aqc_add_udp_tunnel_completion {
2201 __le16 udp_port;
2202 u8 filter_entry_index;
2203 u8 multiple_pfs;
2204 #define I40E_AQC_SINGLE_PF 0x0
2205 #define I40E_AQC_MULTIPLE_PFS 0x1
2206 u8 total_filters;
2207 u8 reserved[11];
2208 };
2209
2210 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2211
2212 /* remove UDP Tunnel command (0x0B01) */
2213 struct i40e_aqc_remove_udp_tunnel {
2214 u8 reserved[2];
2215 u8 index; /* 0 to 15 */
2216 u8 reserved2[13];
2217 };
2218
2219 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2220
2221 struct i40e_aqc_del_udp_tunnel_completion {
2222 __le16 udp_port;
2223 u8 index; /* 0 to 15 */
2224 u8 multiple_pfs;
2225 u8 total_filters_used;
2226 u8 reserved1[11];
2227 };
2228
2229 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2230
2231 struct i40e_aqc_get_set_rss_key {
2232 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2233 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2234 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2235 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2236 __le16 vsi_id;
2237 u8 reserved[6];
2238 __le32 addr_high;
2239 __le32 addr_low;
2240 };
2241
2242 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2243
2244 struct i40e_aqc_get_set_rss_key_data {
2245 u8 standard_rss_key[0x28];
2246 u8 extended_hash_key[0xc];
2247 };
2248
2249 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2250
2251 struct i40e_aqc_get_set_rss_lut {
2252 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2253 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2254 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2255 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2256 __le16 vsi_id;
2257 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2258 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2259 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2260
2261 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2262 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2263 __le16 flags;
2264 u8 reserved[4];
2265 __le32 addr_high;
2266 __le32 addr_low;
2267 };
2268
2269 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2270
2271 /* tunnel key structure 0x0B10 */
2272
2273 struct i40e_aqc_tunnel_key_structure {
2274 u8 key1_off;
2275 u8 key2_off;
2276 u8 key1_len; /* 0 to 15 */
2277 u8 key2_len; /* 0 to 15 */
2278 u8 flags;
2279 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2280 /* response flags */
2281 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2282 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2283 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2284 u8 network_key_index;
2285 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2286 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2287 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2288 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2289 u8 reserved[10];
2290 };
2291
2292 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2293
2294 /* OEM mode commands (direct 0xFE0x) */
2295 struct i40e_aqc_oem_param_change {
2296 __le32 param_type;
2297 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2298 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2299 #define I40E_AQ_OEM_PARAM_MAC 2
2300 __le32 param_value1;
2301 __le16 param_value2;
2302 u8 reserved[6];
2303 };
2304
2305 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2306
2307 struct i40e_aqc_oem_state_change {
2308 __le32 state;
2309 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2310 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2311 u8 reserved[12];
2312 };
2313
2314 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2315
2316 /* Initialize OCSD (0xFE02, direct) */
2317 struct i40e_aqc_opc_oem_ocsd_initialize {
2318 u8 type_status;
2319 u8 reserved1[3];
2320 __le32 ocsd_memory_block_addr_high;
2321 __le32 ocsd_memory_block_addr_low;
2322 __le32 requested_update_interval;
2323 };
2324
2325 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2326
2327 /* Initialize OCBB (0xFE03, direct) */
2328 struct i40e_aqc_opc_oem_ocbb_initialize {
2329 u8 type_status;
2330 u8 reserved1[3];
2331 __le32 ocbb_memory_block_addr_high;
2332 __le32 ocbb_memory_block_addr_low;
2333 u8 reserved2[4];
2334 };
2335
2336 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2337
2338 /* debug commands */
2339
2340 /* get device id (0xFF00) uses the generic structure */
2341
2342 /* set test more (0xFF01, internal) */
2343
2344 struct i40e_acq_set_test_mode {
2345 u8 mode;
2346 #define I40E_AQ_TEST_PARTIAL 0
2347 #define I40E_AQ_TEST_FULL 1
2348 #define I40E_AQ_TEST_NVM 2
2349 u8 reserved[3];
2350 u8 command;
2351 #define I40E_AQ_TEST_OPEN 0
2352 #define I40E_AQ_TEST_CLOSE 1
2353 #define I40E_AQ_TEST_INC 2
2354 u8 reserved2[3];
2355 __le32 address_high;
2356 __le32 address_low;
2357 };
2358
2359 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2360
2361 /* Debug Read Register command (0xFF03)
2362 * Debug Write Register command (0xFF04)
2363 */
2364 struct i40e_aqc_debug_reg_read_write {
2365 __le32 reserved;
2366 __le32 address;
2367 __le32 value_high;
2368 __le32 value_low;
2369 };
2370
2371 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2372
2373 /* Scatter/gather Reg Read (indirect 0xFF05)
2374 * Scatter/gather Reg Write (indirect 0xFF06)
2375 */
2376
2377 /* i40e_aq_desc is used for the command */
2378 struct i40e_aqc_debug_reg_sg_element_data {
2379 __le32 address;
2380 __le32 value;
2381 };
2382
2383 /* Debug Modify register (direct 0xFF07) */
2384 struct i40e_aqc_debug_modify_reg {
2385 __le32 address;
2386 __le32 value;
2387 __le32 clear_mask;
2388 __le32 set_mask;
2389 };
2390
2391 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2392
2393 /* dump internal data (0xFF08, indirect) */
2394
2395 #define I40E_AQ_CLUSTER_ID_AUX 0
2396 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2397 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2398 #define I40E_AQ_CLUSTER_ID_HMC 3
2399 #define I40E_AQ_CLUSTER_ID_MAC0 4
2400 #define I40E_AQ_CLUSTER_ID_MAC1 5
2401 #define I40E_AQ_CLUSTER_ID_MAC2 6
2402 #define I40E_AQ_CLUSTER_ID_MAC3 7
2403 #define I40E_AQ_CLUSTER_ID_DCB 8
2404 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2405 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2406 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2407
2408 struct i40e_aqc_debug_dump_internals {
2409 u8 cluster_id;
2410 u8 table_id;
2411 __le16 data_size;
2412 __le32 idx;
2413 __le32 address_high;
2414 __le32 address_low;
2415 };
2416
2417 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2418
2419 struct i40e_aqc_debug_modify_internals {
2420 u8 cluster_id;
2421 u8 cluster_specific_params[7];
2422 __le32 address_high;
2423 __le32 address_low;
2424 };
2425
2426 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2427
2428 #endif /* _I40E_ADMINQ_CMD_H_ */
Linux kernel - Deliverables
This page took 0.081906 seconds and 5 git commands to generate.