1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
39 static i40e_status
i40e_set_mac_type(struct i40e_hw
*hw
)
41 i40e_status status
= 0;
43 if (hw
->vendor_id
== PCI_VENDOR_ID_INTEL
) {
44 switch (hw
->device_id
) {
45 case I40E_DEV_ID_SFP_XL710
:
46 case I40E_DEV_ID_QEMU
:
47 case I40E_DEV_ID_KX_A
:
48 case I40E_DEV_ID_KX_B
:
49 case I40E_DEV_ID_KX_C
:
50 case I40E_DEV_ID_QSFP_A
:
51 case I40E_DEV_ID_QSFP_B
:
52 case I40E_DEV_ID_QSFP_C
:
53 hw
->mac
.type
= I40E_MAC_XL710
;
56 case I40E_DEV_ID_VF_HV
:
57 hw
->mac
.type
= I40E_MAC_VF
;
60 hw
->mac
.type
= I40E_MAC_GENERIC
;
64 status
= I40E_ERR_DEVICE_NOT_SUPPORTED
;
67 hw_dbg(hw
, "i40e_set_mac_type found mac: %d, returns: %d\n",
68 hw
->mac
.type
, status
);
74 * @hw: debug mask related to admin queue
76 * @desc: pointer to admin queue descriptor
77 * @buffer: pointer to command buffer
78 * @buf_len: max length of buffer
80 * Dumps debug log about adminq command with descriptor contents.
82 void i40e_debug_aq(struct i40e_hw
*hw
, enum i40e_debug_mask mask
, void *desc
,
83 void *buffer
, u16 buf_len
)
85 struct i40e_aq_desc
*aq_desc
= (struct i40e_aq_desc
*)desc
;
86 u16 len
= le16_to_cpu(aq_desc
->datalen
);
87 u8
*aq_buffer
= (u8
*)buffer
;
91 if ((!(mask
& hw
->debug_mask
)) || (desc
== NULL
))
95 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
96 aq_desc
->opcode
, aq_desc
->flags
, aq_desc
->datalen
,
98 i40e_debug(hw
, mask
, "\tcookie (h,l) 0x%08X 0x%08X\n",
99 aq_desc
->cookie_high
, aq_desc
->cookie_low
);
100 i40e_debug(hw
, mask
, "\tparam (0,1) 0x%08X 0x%08X\n",
101 aq_desc
->params
.internal
.param0
,
102 aq_desc
->params
.internal
.param1
);
103 i40e_debug(hw
, mask
, "\taddr (h,l) 0x%08X 0x%08X\n",
104 aq_desc
->params
.external
.addr_high
,
105 aq_desc
->params
.external
.addr_low
);
107 if ((buffer
!= NULL
) && (aq_desc
->datalen
!= 0)) {
108 memset(data
, 0, sizeof(data
));
109 i40e_debug(hw
, mask
, "AQ CMD Buffer:\n");
112 for (i
= 0; i
< len
; i
++) {
113 data
[((i
% 16) / 4)] |=
114 ((u32
)aq_buffer
[i
]) << (8 * (i
% 4));
115 if ((i
% 16) == 15) {
117 "\t0x%04X %08X %08X %08X %08X\n",
118 i
- 15, data
[0], data
[1], data
[2],
120 memset(data
, 0, sizeof(data
));
124 i40e_debug(hw
, mask
, "\t0x%04X %08X %08X %08X %08X\n",
125 i
- (i
% 16), data
[0], data
[1], data
[2],
131 * i40e_check_asq_alive
132 * @hw: pointer to the hw struct
134 * Returns true if Queue is enabled else false.
136 bool i40e_check_asq_alive(struct i40e_hw
*hw
)
139 return !!(rd32(hw
, hw
->aq
.asq
.len
) &
140 I40E_PF_ATQLEN_ATQENABLE_MASK
);
146 * i40e_aq_queue_shutdown
147 * @hw: pointer to the hw struct
148 * @unloading: is the driver unloading itself
150 * Tell the Firmware that we're shutting down the AdminQ and whether
151 * or not the driver is unloading as well.
153 i40e_status
i40e_aq_queue_shutdown(struct i40e_hw
*hw
,
156 struct i40e_aq_desc desc
;
157 struct i40e_aqc_queue_shutdown
*cmd
=
158 (struct i40e_aqc_queue_shutdown
*)&desc
.params
.raw
;
161 i40e_fill_default_direct_cmd_desc(&desc
,
162 i40e_aqc_opc_queue_shutdown
);
165 cmd
->driver_unloading
= cpu_to_le32(I40E_AQ_DRIVER_UNLOADING
);
166 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, NULL
);
171 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
172 * hardware to a bit-field that can be used by SW to more easily determine the
175 * Macros are used to shorten the table lines and make this table human
178 * We store the PTYPE in the top byte of the bit field - this is just so that
179 * we can check that the table doesn't have a row missing, as the index into
180 * the table should be the PTYPE.
184 * IF NOT i40e_ptype_lookup[ptype].known
187 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
188 * Use the rest of the fields to look at the tunnels, inner protocols, etc
190 * Use the enum i40e_rx_l2_ptype to decode the packet type
194 /* macro to make the table lines short */
195 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
198 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
199 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
200 I40E_RX_PTYPE_##OUTER_FRAG, \
201 I40E_RX_PTYPE_TUNNEL_##T, \
202 I40E_RX_PTYPE_TUNNEL_END_##TE, \
203 I40E_RX_PTYPE_##TEF, \
204 I40E_RX_PTYPE_INNER_PROT_##I, \
205 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
207 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
208 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
210 /* shorter macros makes the table fit but are terse */
211 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
212 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
213 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
215 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
216 struct i40e_rx_ptype_decoded i40e_ptype_lookup
[] = {
217 /* L2 Packet types */
218 I40E_PTT_UNUSED_ENTRY(0),
219 I40E_PTT(1, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
220 I40E_PTT(2, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, TS
, PAY2
),
221 I40E_PTT(3, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
222 I40E_PTT_UNUSED_ENTRY(4),
223 I40E_PTT_UNUSED_ENTRY(5),
224 I40E_PTT(6, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
225 I40E_PTT(7, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
226 I40E_PTT_UNUSED_ENTRY(8),
227 I40E_PTT_UNUSED_ENTRY(9),
228 I40E_PTT(10, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
229 I40E_PTT(11, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, NONE
),
230 I40E_PTT(12, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
231 I40E_PTT(13, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
232 I40E_PTT(14, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
233 I40E_PTT(15, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
234 I40E_PTT(16, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
235 I40E_PTT(17, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
236 I40E_PTT(18, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
237 I40E_PTT(19, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
238 I40E_PTT(20, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
239 I40E_PTT(21, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
241 /* Non Tunneled IPv4 */
242 I40E_PTT(22, IP
, IPV4
, FRG
, NONE
, NONE
, NOF
, NONE
, PAY3
),
243 I40E_PTT(23, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
244 I40E_PTT(24, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, UDP
, PAY4
),
245 I40E_PTT_UNUSED_ENTRY(25),
246 I40E_PTT(26, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, TCP
, PAY4
),
247 I40E_PTT(27, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, SCTP
, PAY4
),
248 I40E_PTT(28, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, ICMP
, PAY4
),
251 I40E_PTT(29, IP
, IPV4
, NOF
, IP_IP
, IPV4
, FRG
, NONE
, PAY3
),
252 I40E_PTT(30, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, NONE
, PAY3
),
253 I40E_PTT(31, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, UDP
, PAY4
),
254 I40E_PTT_UNUSED_ENTRY(32),
255 I40E_PTT(33, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, TCP
, PAY4
),
256 I40E_PTT(34, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, SCTP
, PAY4
),
257 I40E_PTT(35, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, ICMP
, PAY4
),
260 I40E_PTT(36, IP
, IPV4
, NOF
, IP_IP
, IPV6
, FRG
, NONE
, PAY3
),
261 I40E_PTT(37, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, NONE
, PAY3
),
262 I40E_PTT(38, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, UDP
, PAY4
),
263 I40E_PTT_UNUSED_ENTRY(39),
264 I40E_PTT(40, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, TCP
, PAY4
),
265 I40E_PTT(41, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, SCTP
, PAY4
),
266 I40E_PTT(42, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, ICMP
, PAY4
),
268 /* IPv4 --> GRE/NAT */
269 I40E_PTT(43, IP
, IPV4
, NOF
, IP_GRENAT
, NONE
, NOF
, NONE
, PAY3
),
271 /* IPv4 --> GRE/NAT --> IPv4 */
272 I40E_PTT(44, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, FRG
, NONE
, PAY3
),
273 I40E_PTT(45, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, NONE
, PAY3
),
274 I40E_PTT(46, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, UDP
, PAY4
),
275 I40E_PTT_UNUSED_ENTRY(47),
276 I40E_PTT(48, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, TCP
, PAY4
),
277 I40E_PTT(49, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, SCTP
, PAY4
),
278 I40E_PTT(50, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, ICMP
, PAY4
),
280 /* IPv4 --> GRE/NAT --> IPv6 */
281 I40E_PTT(51, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, FRG
, NONE
, PAY3
),
282 I40E_PTT(52, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, NONE
, PAY3
),
283 I40E_PTT(53, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, UDP
, PAY4
),
284 I40E_PTT_UNUSED_ENTRY(54),
285 I40E_PTT(55, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, TCP
, PAY4
),
286 I40E_PTT(56, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, SCTP
, PAY4
),
287 I40E_PTT(57, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, ICMP
, PAY4
),
289 /* IPv4 --> GRE/NAT --> MAC */
290 I40E_PTT(58, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, NONE
, NOF
, NONE
, PAY3
),
292 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
293 I40E_PTT(59, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, FRG
, NONE
, PAY3
),
294 I40E_PTT(60, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, NONE
, PAY3
),
295 I40E_PTT(61, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, UDP
, PAY4
),
296 I40E_PTT_UNUSED_ENTRY(62),
297 I40E_PTT(63, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, TCP
, PAY4
),
298 I40E_PTT(64, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, SCTP
, PAY4
),
299 I40E_PTT(65, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, ICMP
, PAY4
),
301 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
302 I40E_PTT(66, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, FRG
, NONE
, PAY3
),
303 I40E_PTT(67, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, NONE
, PAY3
),
304 I40E_PTT(68, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, UDP
, PAY4
),
305 I40E_PTT_UNUSED_ENTRY(69),
306 I40E_PTT(70, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, TCP
, PAY4
),
307 I40E_PTT(71, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, SCTP
, PAY4
),
308 I40E_PTT(72, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, ICMP
, PAY4
),
310 /* IPv4 --> GRE/NAT --> MAC/VLAN */
311 I40E_PTT(73, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, NONE
, NOF
, NONE
, PAY3
),
313 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
314 I40E_PTT(74, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, FRG
, NONE
, PAY3
),
315 I40E_PTT(75, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, NONE
, PAY3
),
316 I40E_PTT(76, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, UDP
, PAY4
),
317 I40E_PTT_UNUSED_ENTRY(77),
318 I40E_PTT(78, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, TCP
, PAY4
),
319 I40E_PTT(79, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, SCTP
, PAY4
),
320 I40E_PTT(80, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, ICMP
, PAY4
),
322 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
323 I40E_PTT(81, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, FRG
, NONE
, PAY3
),
324 I40E_PTT(82, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, NONE
, PAY3
),
325 I40E_PTT(83, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, UDP
, PAY4
),
326 I40E_PTT_UNUSED_ENTRY(84),
327 I40E_PTT(85, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, TCP
, PAY4
),
328 I40E_PTT(86, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, SCTP
, PAY4
),
329 I40E_PTT(87, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, ICMP
, PAY4
),
331 /* Non Tunneled IPv6 */
332 I40E_PTT(88, IP
, IPV6
, FRG
, NONE
, NONE
, NOF
, NONE
, PAY3
),
333 I40E_PTT(89, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
334 I40E_PTT(90, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, UDP
, PAY3
),
335 I40E_PTT_UNUSED_ENTRY(91),
336 I40E_PTT(92, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, TCP
, PAY4
),
337 I40E_PTT(93, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, SCTP
, PAY4
),
338 I40E_PTT(94, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, ICMP
, PAY4
),
341 I40E_PTT(95, IP
, IPV6
, NOF
, IP_IP
, IPV4
, FRG
, NONE
, PAY3
),
342 I40E_PTT(96, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, NONE
, PAY3
),
343 I40E_PTT(97, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, UDP
, PAY4
),
344 I40E_PTT_UNUSED_ENTRY(98),
345 I40E_PTT(99, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, TCP
, PAY4
),
346 I40E_PTT(100, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, SCTP
, PAY4
),
347 I40E_PTT(101, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, ICMP
, PAY4
),
350 I40E_PTT(102, IP
, IPV6
, NOF
, IP_IP
, IPV6
, FRG
, NONE
, PAY3
),
351 I40E_PTT(103, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, NONE
, PAY3
),
352 I40E_PTT(104, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, UDP
, PAY4
),
353 I40E_PTT_UNUSED_ENTRY(105),
354 I40E_PTT(106, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, TCP
, PAY4
),
355 I40E_PTT(107, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, SCTP
, PAY4
),
356 I40E_PTT(108, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, ICMP
, PAY4
),
358 /* IPv6 --> GRE/NAT */
359 I40E_PTT(109, IP
, IPV6
, NOF
, IP_GRENAT
, NONE
, NOF
, NONE
, PAY3
),
361 /* IPv6 --> GRE/NAT -> IPv4 */
362 I40E_PTT(110, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, FRG
, NONE
, PAY3
),
363 I40E_PTT(111, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, NONE
, PAY3
),
364 I40E_PTT(112, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, UDP
, PAY4
),
365 I40E_PTT_UNUSED_ENTRY(113),
366 I40E_PTT(114, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, TCP
, PAY4
),
367 I40E_PTT(115, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, SCTP
, PAY4
),
368 I40E_PTT(116, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, ICMP
, PAY4
),
370 /* IPv6 --> GRE/NAT -> IPv6 */
371 I40E_PTT(117, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, FRG
, NONE
, PAY3
),
372 I40E_PTT(118, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, NONE
, PAY3
),
373 I40E_PTT(119, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, UDP
, PAY4
),
374 I40E_PTT_UNUSED_ENTRY(120),
375 I40E_PTT(121, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, TCP
, PAY4
),
376 I40E_PTT(122, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, SCTP
, PAY4
),
377 I40E_PTT(123, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, ICMP
, PAY4
),
379 /* IPv6 --> GRE/NAT -> MAC */
380 I40E_PTT(124, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, NONE
, NOF
, NONE
, PAY3
),
382 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
383 I40E_PTT(125, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, FRG
, NONE
, PAY3
),
384 I40E_PTT(126, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, NONE
, PAY3
),
385 I40E_PTT(127, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, UDP
, PAY4
),
386 I40E_PTT_UNUSED_ENTRY(128),
387 I40E_PTT(129, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, TCP
, PAY4
),
388 I40E_PTT(130, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, SCTP
, PAY4
),
389 I40E_PTT(131, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, ICMP
, PAY4
),
391 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
392 I40E_PTT(132, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, FRG
, NONE
, PAY3
),
393 I40E_PTT(133, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, NONE
, PAY3
),
394 I40E_PTT(134, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, UDP
, PAY4
),
395 I40E_PTT_UNUSED_ENTRY(135),
396 I40E_PTT(136, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, TCP
, PAY4
),
397 I40E_PTT(137, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, SCTP
, PAY4
),
398 I40E_PTT(138, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, ICMP
, PAY4
),
400 /* IPv6 --> GRE/NAT -> MAC/VLAN */
401 I40E_PTT(139, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, NONE
, NOF
, NONE
, PAY3
),
403 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
404 I40E_PTT(140, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, FRG
, NONE
, PAY3
),
405 I40E_PTT(141, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, NONE
, PAY3
),
406 I40E_PTT(142, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, UDP
, PAY4
),
407 I40E_PTT_UNUSED_ENTRY(143),
408 I40E_PTT(144, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, TCP
, PAY4
),
409 I40E_PTT(145, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, SCTP
, PAY4
),
410 I40E_PTT(146, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, ICMP
, PAY4
),
412 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
413 I40E_PTT(147, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, FRG
, NONE
, PAY3
),
414 I40E_PTT(148, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, NONE
, PAY3
),
415 I40E_PTT(149, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, UDP
, PAY4
),
416 I40E_PTT_UNUSED_ENTRY(150),
417 I40E_PTT(151, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, TCP
, PAY4
),
418 I40E_PTT(152, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, SCTP
, PAY4
),
419 I40E_PTT(153, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, ICMP
, PAY4
),
422 I40E_PTT_UNUSED_ENTRY(154),
423 I40E_PTT_UNUSED_ENTRY(155),
424 I40E_PTT_UNUSED_ENTRY(156),
425 I40E_PTT_UNUSED_ENTRY(157),
426 I40E_PTT_UNUSED_ENTRY(158),
427 I40E_PTT_UNUSED_ENTRY(159),
429 I40E_PTT_UNUSED_ENTRY(160),
430 I40E_PTT_UNUSED_ENTRY(161),
431 I40E_PTT_UNUSED_ENTRY(162),
432 I40E_PTT_UNUSED_ENTRY(163),
433 I40E_PTT_UNUSED_ENTRY(164),
434 I40E_PTT_UNUSED_ENTRY(165),
435 I40E_PTT_UNUSED_ENTRY(166),
436 I40E_PTT_UNUSED_ENTRY(167),
437 I40E_PTT_UNUSED_ENTRY(168),
438 I40E_PTT_UNUSED_ENTRY(169),
440 I40E_PTT_UNUSED_ENTRY(170),
441 I40E_PTT_UNUSED_ENTRY(171),
442 I40E_PTT_UNUSED_ENTRY(172),
443 I40E_PTT_UNUSED_ENTRY(173),
444 I40E_PTT_UNUSED_ENTRY(174),
445 I40E_PTT_UNUSED_ENTRY(175),
446 I40E_PTT_UNUSED_ENTRY(176),
447 I40E_PTT_UNUSED_ENTRY(177),
448 I40E_PTT_UNUSED_ENTRY(178),
449 I40E_PTT_UNUSED_ENTRY(179),
451 I40E_PTT_UNUSED_ENTRY(180),
452 I40E_PTT_UNUSED_ENTRY(181),
453 I40E_PTT_UNUSED_ENTRY(182),
454 I40E_PTT_UNUSED_ENTRY(183),
455 I40E_PTT_UNUSED_ENTRY(184),
456 I40E_PTT_UNUSED_ENTRY(185),
457 I40E_PTT_UNUSED_ENTRY(186),
458 I40E_PTT_UNUSED_ENTRY(187),
459 I40E_PTT_UNUSED_ENTRY(188),
460 I40E_PTT_UNUSED_ENTRY(189),
462 I40E_PTT_UNUSED_ENTRY(190),
463 I40E_PTT_UNUSED_ENTRY(191),
464 I40E_PTT_UNUSED_ENTRY(192),
465 I40E_PTT_UNUSED_ENTRY(193),
466 I40E_PTT_UNUSED_ENTRY(194),
467 I40E_PTT_UNUSED_ENTRY(195),
468 I40E_PTT_UNUSED_ENTRY(196),
469 I40E_PTT_UNUSED_ENTRY(197),
470 I40E_PTT_UNUSED_ENTRY(198),
471 I40E_PTT_UNUSED_ENTRY(199),
473 I40E_PTT_UNUSED_ENTRY(200),
474 I40E_PTT_UNUSED_ENTRY(201),
475 I40E_PTT_UNUSED_ENTRY(202),
476 I40E_PTT_UNUSED_ENTRY(203),
477 I40E_PTT_UNUSED_ENTRY(204),
478 I40E_PTT_UNUSED_ENTRY(205),
479 I40E_PTT_UNUSED_ENTRY(206),
480 I40E_PTT_UNUSED_ENTRY(207),
481 I40E_PTT_UNUSED_ENTRY(208),
482 I40E_PTT_UNUSED_ENTRY(209),
484 I40E_PTT_UNUSED_ENTRY(210),
485 I40E_PTT_UNUSED_ENTRY(211),
486 I40E_PTT_UNUSED_ENTRY(212),
487 I40E_PTT_UNUSED_ENTRY(213),
488 I40E_PTT_UNUSED_ENTRY(214),
489 I40E_PTT_UNUSED_ENTRY(215),
490 I40E_PTT_UNUSED_ENTRY(216),
491 I40E_PTT_UNUSED_ENTRY(217),
492 I40E_PTT_UNUSED_ENTRY(218),
493 I40E_PTT_UNUSED_ENTRY(219),
495 I40E_PTT_UNUSED_ENTRY(220),
496 I40E_PTT_UNUSED_ENTRY(221),
497 I40E_PTT_UNUSED_ENTRY(222),
498 I40E_PTT_UNUSED_ENTRY(223),
499 I40E_PTT_UNUSED_ENTRY(224),
500 I40E_PTT_UNUSED_ENTRY(225),
501 I40E_PTT_UNUSED_ENTRY(226),
502 I40E_PTT_UNUSED_ENTRY(227),
503 I40E_PTT_UNUSED_ENTRY(228),
504 I40E_PTT_UNUSED_ENTRY(229),
506 I40E_PTT_UNUSED_ENTRY(230),
507 I40E_PTT_UNUSED_ENTRY(231),
508 I40E_PTT_UNUSED_ENTRY(232),
509 I40E_PTT_UNUSED_ENTRY(233),
510 I40E_PTT_UNUSED_ENTRY(234),
511 I40E_PTT_UNUSED_ENTRY(235),
512 I40E_PTT_UNUSED_ENTRY(236),
513 I40E_PTT_UNUSED_ENTRY(237),
514 I40E_PTT_UNUSED_ENTRY(238),
515 I40E_PTT_UNUSED_ENTRY(239),
517 I40E_PTT_UNUSED_ENTRY(240),
518 I40E_PTT_UNUSED_ENTRY(241),
519 I40E_PTT_UNUSED_ENTRY(242),
520 I40E_PTT_UNUSED_ENTRY(243),
521 I40E_PTT_UNUSED_ENTRY(244),
522 I40E_PTT_UNUSED_ENTRY(245),
523 I40E_PTT_UNUSED_ENTRY(246),
524 I40E_PTT_UNUSED_ENTRY(247),
525 I40E_PTT_UNUSED_ENTRY(248),
526 I40E_PTT_UNUSED_ENTRY(249),
528 I40E_PTT_UNUSED_ENTRY(250),
529 I40E_PTT_UNUSED_ENTRY(251),
530 I40E_PTT_UNUSED_ENTRY(252),
531 I40E_PTT_UNUSED_ENTRY(253),
532 I40E_PTT_UNUSED_ENTRY(254),
533 I40E_PTT_UNUSED_ENTRY(255)
538 * i40e_init_shared_code - Initialize the shared code
539 * @hw: pointer to hardware structure
541 * This assigns the MAC type and PHY code and inits the NVM.
542 * Does not touch the hardware. This function must be called prior to any
543 * other function in the shared code. The i40e_hw structure should be
544 * memset to 0 prior to calling this function. The following fields in
545 * hw structure should be filled in prior to calling this function:
546 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
547 * subsystem_vendor_id, and revision_id
549 i40e_status
i40e_init_shared_code(struct i40e_hw
*hw
)
551 i40e_status status
= 0;
554 i40e_set_mac_type(hw
);
556 switch (hw
->mac
.type
) {
560 return I40E_ERR_DEVICE_NOT_SUPPORTED
;
563 hw
->phy
.get_link_info
= true;
565 /* Determine port number */
566 reg
= rd32(hw
, I40E_PFGEN_PORTNUM
);
567 reg
= ((reg
& I40E_PFGEN_PORTNUM_PORT_NUM_MASK
) >>
568 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT
);
571 /* Determine the PF number based on the PCI fn */
572 reg
= rd32(hw
, I40E_GLPCI_CAPSUP
);
573 if (reg
& I40E_GLPCI_CAPSUP_ARI_EN_MASK
)
574 hw
->pf_id
= (u8
)((hw
->bus
.device
<< 3) | hw
->bus
.func
);
576 hw
->pf_id
= (u8
)hw
->bus
.func
;
578 status
= i40e_init_nvm(hw
);
583 * i40e_aq_mac_address_read - Retrieve the MAC addresses
584 * @hw: pointer to the hw struct
585 * @flags: a return indicator of what addresses were added to the addr store
586 * @addrs: the requestor's mac addr store
587 * @cmd_details: pointer to command details structure or NULL
589 static i40e_status
i40e_aq_mac_address_read(struct i40e_hw
*hw
,
591 struct i40e_aqc_mac_address_read_data
*addrs
,
592 struct i40e_asq_cmd_details
*cmd_details
)
594 struct i40e_aq_desc desc
;
595 struct i40e_aqc_mac_address_read
*cmd_data
=
596 (struct i40e_aqc_mac_address_read
*)&desc
.params
.raw
;
599 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_mac_address_read
);
600 desc
.flags
|= cpu_to_le16(I40E_AQ_FLAG_BUF
);
602 status
= i40e_asq_send_command(hw
, &desc
, addrs
,
603 sizeof(*addrs
), cmd_details
);
604 *flags
= le16_to_cpu(cmd_data
->command_flags
);
610 * i40e_aq_mac_address_write - Change the MAC addresses
611 * @hw: pointer to the hw struct
612 * @flags: indicates which MAC to be written
613 * @mac_addr: address to write
614 * @cmd_details: pointer to command details structure or NULL
616 i40e_status
i40e_aq_mac_address_write(struct i40e_hw
*hw
,
617 u16 flags
, u8
*mac_addr
,
618 struct i40e_asq_cmd_details
*cmd_details
)
620 struct i40e_aq_desc desc
;
621 struct i40e_aqc_mac_address_write
*cmd_data
=
622 (struct i40e_aqc_mac_address_write
*)&desc
.params
.raw
;
625 i40e_fill_default_direct_cmd_desc(&desc
,
626 i40e_aqc_opc_mac_address_write
);
627 cmd_data
->command_flags
= cpu_to_le16(flags
);
628 cmd_data
->mac_sah
= cpu_to_le16((u16
)mac_addr
[0] << 8 | mac_addr
[1]);
629 cmd_data
->mac_sal
= cpu_to_le32(((u32
)mac_addr
[2] << 24) |
630 ((u32
)mac_addr
[3] << 16) |
631 ((u32
)mac_addr
[4] << 8) |
634 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
640 * i40e_get_mac_addr - get MAC address
641 * @hw: pointer to the HW structure
642 * @mac_addr: pointer to MAC address
644 * Reads the adapter's MAC address from register
646 i40e_status
i40e_get_mac_addr(struct i40e_hw
*hw
, u8
*mac_addr
)
648 struct i40e_aqc_mac_address_read_data addrs
;
652 status
= i40e_aq_mac_address_read(hw
, &flags
, &addrs
, NULL
);
654 if (flags
& I40E_AQC_LAN_ADDR_VALID
)
655 memcpy(mac_addr
, &addrs
.pf_lan_mac
, sizeof(addrs
.pf_lan_mac
));
661 * i40e_get_port_mac_addr - get Port MAC address
662 * @hw: pointer to the HW structure
663 * @mac_addr: pointer to Port MAC address
665 * Reads the adapter's Port MAC address
667 i40e_status
i40e_get_port_mac_addr(struct i40e_hw
*hw
, u8
*mac_addr
)
669 struct i40e_aqc_mac_address_read_data addrs
;
673 status
= i40e_aq_mac_address_read(hw
, &flags
, &addrs
, NULL
);
677 if (flags
& I40E_AQC_PORT_ADDR_VALID
)
678 memcpy(mac_addr
, &addrs
.port_mac
, sizeof(addrs
.port_mac
));
680 status
= I40E_ERR_INVALID_MAC_ADDR
;
686 * i40e_pre_tx_queue_cfg - pre tx queue configure
687 * @hw: pointer to the HW structure
688 * @queue: target pf queue index
689 * @enable: state change request
691 * Handles hw requirement to indicate intention to enable
692 * or disable target queue.
694 void i40e_pre_tx_queue_cfg(struct i40e_hw
*hw
, u32 queue
, bool enable
)
696 u32 abs_queue_idx
= hw
->func_caps
.base_queue
+ queue
;
700 if (abs_queue_idx
>= 128) {
701 reg_block
= abs_queue_idx
/ 128;
702 abs_queue_idx
%= 128;
705 reg_val
= rd32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
));
706 reg_val
&= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK
;
707 reg_val
|= (abs_queue_idx
<< I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT
);
710 reg_val
|= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK
;
712 reg_val
|= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK
;
714 wr32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
), reg_val
);
719 * i40e_get_san_mac_addr - get SAN MAC address
720 * @hw: pointer to the HW structure
721 * @mac_addr: pointer to SAN MAC address
723 * Reads the adapter's SAN MAC address from NVM
725 i40e_status
i40e_get_san_mac_addr(struct i40e_hw
*hw
, u8
*mac_addr
)
727 struct i40e_aqc_mac_address_read_data addrs
;
731 status
= i40e_aq_mac_address_read(hw
, &flags
, &addrs
, NULL
);
735 if (flags
& I40E_AQC_SAN_ADDR_VALID
)
736 memcpy(mac_addr
, &addrs
.pf_san_mac
, sizeof(addrs
.pf_san_mac
));
738 status
= I40E_ERR_INVALID_MAC_ADDR
;
745 * i40e_get_media_type - Gets media type
746 * @hw: pointer to the hardware structure
748 static enum i40e_media_type
i40e_get_media_type(struct i40e_hw
*hw
)
750 enum i40e_media_type media
;
752 switch (hw
->phy
.link_info
.phy_type
) {
753 case I40E_PHY_TYPE_10GBASE_SR
:
754 case I40E_PHY_TYPE_10GBASE_LR
:
755 case I40E_PHY_TYPE_40GBASE_SR4
:
756 case I40E_PHY_TYPE_40GBASE_LR4
:
757 media
= I40E_MEDIA_TYPE_FIBER
;
759 case I40E_PHY_TYPE_100BASE_TX
:
760 case I40E_PHY_TYPE_1000BASE_T
:
761 case I40E_PHY_TYPE_10GBASE_T
:
762 media
= I40E_MEDIA_TYPE_BASET
;
764 case I40E_PHY_TYPE_10GBASE_CR1_CU
:
765 case I40E_PHY_TYPE_40GBASE_CR4_CU
:
766 case I40E_PHY_TYPE_10GBASE_CR1
:
767 case I40E_PHY_TYPE_40GBASE_CR4
:
768 case I40E_PHY_TYPE_10GBASE_SFPP_CU
:
769 media
= I40E_MEDIA_TYPE_DA
;
771 case I40E_PHY_TYPE_1000BASE_KX
:
772 case I40E_PHY_TYPE_10GBASE_KX4
:
773 case I40E_PHY_TYPE_10GBASE_KR
:
774 case I40E_PHY_TYPE_40GBASE_KR4
:
775 media
= I40E_MEDIA_TYPE_BACKPLANE
;
777 case I40E_PHY_TYPE_SGMII
:
778 case I40E_PHY_TYPE_XAUI
:
779 case I40E_PHY_TYPE_XFI
:
780 case I40E_PHY_TYPE_XLAUI
:
781 case I40E_PHY_TYPE_XLPPI
:
783 media
= I40E_MEDIA_TYPE_UNKNOWN
;
790 #define I40E_PF_RESET_WAIT_COUNT_A0 200
791 #define I40E_PF_RESET_WAIT_COUNT 100
793 * i40e_pf_reset - Reset the PF
794 * @hw: pointer to the hardware structure
796 * Assuming someone else has triggered a global reset,
797 * assure the global reset is complete and then reset the PF
799 i40e_status
i40e_pf_reset(struct i40e_hw
*hw
)
806 /* Poll for Global Reset steady state in case of recent GRST.
807 * The grst delay value is in 100ms units, and we'll wait a
808 * couple counts longer to be sure we don't just miss the end.
810 grst_del
= rd32(hw
, I40E_GLGEN_RSTCTL
) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
811 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT
;
812 for (cnt
= 0; cnt
< grst_del
+ 2; cnt
++) {
813 reg
= rd32(hw
, I40E_GLGEN_RSTAT
);
814 if (!(reg
& I40E_GLGEN_RSTAT_DEVSTATE_MASK
))
818 if (reg
& I40E_GLGEN_RSTAT_DEVSTATE_MASK
) {
819 hw_dbg(hw
, "Global reset polling failed to complete.\n");
820 return I40E_ERR_RESET_FAILED
;
823 /* Now Wait for the FW to be ready */
824 for (cnt1
= 0; cnt1
< I40E_PF_RESET_WAIT_COUNT
; cnt1
++) {
825 reg
= rd32(hw
, I40E_GLNVM_ULD
);
826 reg
&= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
|
827 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
);
828 if (reg
== (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
|
829 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
)) {
830 hw_dbg(hw
, "Core and Global modules ready %d\n", cnt1
);
833 usleep_range(10000, 20000);
835 if (!(reg
& (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
|
836 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
))) {
837 hw_dbg(hw
, "wait for FW Reset complete timedout\n");
838 hw_dbg(hw
, "I40E_GLNVM_ULD = 0x%x\n", reg
);
839 return I40E_ERR_RESET_FAILED
;
842 /* If there was a Global Reset in progress when we got here,
843 * we don't need to do the PF Reset
846 if (hw
->revision_id
== 0)
847 cnt
= I40E_PF_RESET_WAIT_COUNT_A0
;
849 cnt
= I40E_PF_RESET_WAIT_COUNT
;
850 reg
= rd32(hw
, I40E_PFGEN_CTRL
);
851 wr32(hw
, I40E_PFGEN_CTRL
,
852 (reg
| I40E_PFGEN_CTRL_PFSWR_MASK
));
854 reg
= rd32(hw
, I40E_PFGEN_CTRL
);
855 if (!(reg
& I40E_PFGEN_CTRL_PFSWR_MASK
))
857 usleep_range(1000, 2000);
859 if (reg
& I40E_PFGEN_CTRL_PFSWR_MASK
) {
860 hw_dbg(hw
, "PF reset polling failed to complete.\n");
861 return I40E_ERR_RESET_FAILED
;
865 i40e_clear_pxe_mode(hw
);
871 * i40e_clear_hw - clear out any left over hw state
872 * @hw: pointer to the hw struct
874 * Clear queues and interrupts, typically called at init time,
875 * but after the capabilities have been found so we know how many
876 * queues and msix vectors have been allocated.
878 void i40e_clear_hw(struct i40e_hw
*hw
)
880 u32 num_queues
, base_queue
;
888 /* get number of interrupts, queues, and vfs */
889 val
= rd32(hw
, I40E_GLPCI_CNF2
);
890 num_pf_int
= (val
& I40E_GLPCI_CNF2_MSI_X_PF_N_MASK
) >>
891 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT
;
892 num_vf_int
= (val
& I40E_GLPCI_CNF2_MSI_X_VF_N_MASK
) >>
893 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT
;
895 val
= rd32(hw
, I40E_PFLAN_QALLOC
);
896 base_queue
= (val
& I40E_PFLAN_QALLOC_FIRSTQ_MASK
) >>
897 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT
;
898 j
= (val
& I40E_PFLAN_QALLOC_LASTQ_MASK
) >>
899 I40E_PFLAN_QALLOC_LASTQ_SHIFT
;
900 if (val
& I40E_PFLAN_QALLOC_VALID_MASK
)
901 num_queues
= (j
- base_queue
) + 1;
905 val
= rd32(hw
, I40E_PF_VT_PFALLOC
);
906 i
= (val
& I40E_PF_VT_PFALLOC_FIRSTVF_MASK
) >>
907 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT
;
908 j
= (val
& I40E_PF_VT_PFALLOC_LASTVF_MASK
) >>
909 I40E_PF_VT_PFALLOC_LASTVF_SHIFT
;
910 if (val
& I40E_PF_VT_PFALLOC_VALID_MASK
)
911 num_vfs
= (j
- i
) + 1;
915 /* stop all the interrupts */
916 wr32(hw
, I40E_PFINT_ICR0_ENA
, 0);
917 val
= 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT
;
918 for (i
= 0; i
< num_pf_int
- 2; i
++)
919 wr32(hw
, I40E_PFINT_DYN_CTLN(i
), val
);
921 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
922 val
= eol
<< I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT
;
923 wr32(hw
, I40E_PFINT_LNKLST0
, val
);
924 for (i
= 0; i
< num_pf_int
- 2; i
++)
925 wr32(hw
, I40E_PFINT_LNKLSTN(i
), val
);
926 val
= eol
<< I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT
;
927 for (i
= 0; i
< num_vfs
; i
++)
928 wr32(hw
, I40E_VPINT_LNKLST0(i
), val
);
929 for (i
= 0; i
< num_vf_int
- 2; i
++)
930 wr32(hw
, I40E_VPINT_LNKLSTN(i
), val
);
932 /* warn the HW of the coming Tx disables */
933 for (i
= 0; i
< num_queues
; i
++) {
934 u32 abs_queue_idx
= base_queue
+ i
;
937 if (abs_queue_idx
>= 128) {
938 reg_block
= abs_queue_idx
/ 128;
939 abs_queue_idx
%= 128;
942 val
= rd32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
));
943 val
&= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK
;
944 val
|= (abs_queue_idx
<< I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT
);
945 val
|= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK
;
947 wr32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
), val
);
951 /* stop all the queues */
952 for (i
= 0; i
< num_queues
; i
++) {
953 wr32(hw
, I40E_QINT_TQCTL(i
), 0);
954 wr32(hw
, I40E_QTX_ENA(i
), 0);
955 wr32(hw
, I40E_QINT_RQCTL(i
), 0);
956 wr32(hw
, I40E_QRX_ENA(i
), 0);
959 /* short wait for all queue disables to settle */
964 * i40e_clear_pxe_mode - clear pxe operations mode
965 * @hw: pointer to the hw struct
967 * Make sure all PXE mode settings are cleared, including things
968 * like descriptor fetch/write-back mode.
970 void i40e_clear_pxe_mode(struct i40e_hw
*hw
)
974 if (i40e_check_asq_alive(hw
))
975 i40e_aq_clear_pxe_mode(hw
, NULL
);
977 /* Clear single descriptor fetch/write-back mode */
978 reg
= rd32(hw
, I40E_GLLAN_RCTL_0
);
980 if (hw
->revision_id
== 0) {
981 /* As a work around clear PXE_MODE instead of setting it */
982 wr32(hw
, I40E_GLLAN_RCTL_0
, (reg
& (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK
)));
984 wr32(hw
, I40E_GLLAN_RCTL_0
, (reg
| I40E_GLLAN_RCTL_0_PXE_MODE_MASK
));
989 * i40e_led_is_mine - helper to find matching led
990 * @hw: pointer to the hw struct
991 * @idx: index into GPIO registers
993 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
995 static u32
i40e_led_is_mine(struct i40e_hw
*hw
, int idx
)
1000 if (!hw
->func_caps
.led
[idx
])
1003 gpio_val
= rd32(hw
, I40E_GLGEN_GPIO_CTL(idx
));
1004 port
= (gpio_val
& I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK
) >>
1005 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT
;
1007 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1008 * if it is not our port then ignore
1010 if ((gpio_val
& I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK
) ||
1017 #define I40E_LED0 22
1018 #define I40E_LINK_ACTIVITY 0xC
1021 * i40e_led_get - return current on/off mode
1022 * @hw: pointer to the hw struct
1024 * The value returned is the 'mode' field as defined in the
1025 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1026 * values are variations of possible behaviors relating to
1027 * blink, link, and wire.
1029 u32
i40e_led_get(struct i40e_hw
*hw
)
1034 /* as per the documentation GPIO 22-29 are the LED
1035 * GPIO pins named LED0..LED7
1037 for (i
= I40E_LED0
; i
<= I40E_GLGEN_GPIO_CTL_MAX_INDEX
; i
++) {
1038 u32 gpio_val
= i40e_led_is_mine(hw
, i
);
1043 mode
= (gpio_val
& I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
) >>
1044 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
;
1052 * i40e_led_set - set new on/off mode
1053 * @hw: pointer to the hw struct
1054 * @mode: 0=off, 0xf=on (else see manual for mode details)
1055 * @blink: true if the LED should blink when on, false if steady
1057 * if this function is used to turn on the blink it should
1058 * be used to disable the blink when restoring the original state.
1060 void i40e_led_set(struct i40e_hw
*hw
, u32 mode
, bool blink
)
1064 if (mode
& 0xfffffff0)
1065 hw_dbg(hw
, "invalid mode passed in %X\n", mode
);
1067 /* as per the documentation GPIO 22-29 are the LED
1068 * GPIO pins named LED0..LED7
1070 for (i
= I40E_LED0
; i
<= I40E_GLGEN_GPIO_CTL_MAX_INDEX
; i
++) {
1071 u32 gpio_val
= i40e_led_is_mine(hw
, i
);
1076 gpio_val
&= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
;
1077 /* this & is a bit of paranoia, but serves as a range check */
1078 gpio_val
|= ((mode
<< I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
) &
1079 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
);
1081 if (mode
== I40E_LINK_ACTIVITY
)
1084 gpio_val
|= (blink
? 1 : 0) <<
1085 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT
;
1087 wr32(hw
, I40E_GLGEN_GPIO_CTL(i
), gpio_val
);
1092 /* Admin command wrappers */
1095 * i40e_aq_get_phy_capabilities
1096 * @hw: pointer to the hw struct
1097 * @abilities: structure for PHY capabilities to be filled
1098 * @qualified_modules: report Qualified Modules
1099 * @report_init: report init capabilities (active are default)
1100 * @cmd_details: pointer to command details structure or NULL
1102 * Returns the various PHY abilities supported on the Port.
1104 i40e_status
i40e_aq_get_phy_capabilities(struct i40e_hw
*hw
,
1105 bool qualified_modules
, bool report_init
,
1106 struct i40e_aq_get_phy_abilities_resp
*abilities
,
1107 struct i40e_asq_cmd_details
*cmd_details
)
1109 struct i40e_aq_desc desc
;
1111 u16 abilities_size
= sizeof(struct i40e_aq_get_phy_abilities_resp
);
1114 return I40E_ERR_PARAM
;
1116 i40e_fill_default_direct_cmd_desc(&desc
,
1117 i40e_aqc_opc_get_phy_abilities
);
1119 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
1120 if (abilities_size
> I40E_AQ_LARGE_BUF
)
1121 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
1123 if (qualified_modules
)
1124 desc
.params
.external
.param0
|=
1125 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES
);
1128 desc
.params
.external
.param0
|=
1129 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES
);
1131 status
= i40e_asq_send_command(hw
, &desc
, abilities
, abilities_size
,
1134 if (hw
->aq
.asq_last_status
== I40E_AQ_RC_EIO
)
1135 status
= I40E_ERR_UNKNOWN_PHY
;
1141 * i40e_aq_set_phy_config
1142 * @hw: pointer to the hw struct
1143 * @config: structure with PHY configuration to be set
1144 * @cmd_details: pointer to command details structure or NULL
1146 * Set the various PHY configuration parameters
1147 * supported on the Port.One or more of the Set PHY config parameters may be
1148 * ignored in an MFP mode as the PF may not have the privilege to set some
1149 * of the PHY Config parameters. This status will be indicated by the
1152 enum i40e_status_code
i40e_aq_set_phy_config(struct i40e_hw
*hw
,
1153 struct i40e_aq_set_phy_config
*config
,
1154 struct i40e_asq_cmd_details
*cmd_details
)
1156 struct i40e_aq_desc desc
;
1157 struct i40e_aq_set_phy_config
*cmd
=
1158 (struct i40e_aq_set_phy_config
*)&desc
.params
.raw
;
1159 enum i40e_status_code status
;
1162 return I40E_ERR_PARAM
;
1164 i40e_fill_default_direct_cmd_desc(&desc
,
1165 i40e_aqc_opc_set_phy_config
);
1169 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1176 * @hw: pointer to the hw struct
1178 * Set the requested flow control mode using set_phy_config.
1180 enum i40e_status_code
i40e_set_fc(struct i40e_hw
*hw
, u8
*aq_failures
,
1181 bool atomic_restart
)
1183 enum i40e_fc_mode fc_mode
= hw
->fc
.requested_mode
;
1184 struct i40e_aq_get_phy_abilities_resp abilities
;
1185 struct i40e_aq_set_phy_config config
;
1186 enum i40e_status_code status
;
1187 u8 pause_mask
= 0x0;
1193 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_TX
;
1194 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_RX
;
1196 case I40E_FC_RX_PAUSE
:
1197 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_RX
;
1199 case I40E_FC_TX_PAUSE
:
1200 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_TX
;
1206 /* Get the current phy config */
1207 status
= i40e_aq_get_phy_capabilities(hw
, false, false, &abilities
,
1210 *aq_failures
|= I40E_SET_FC_AQ_FAIL_GET
;
1214 memset(&config
, 0, sizeof(struct i40e_aq_set_phy_config
));
1215 /* clear the old pause settings */
1216 config
.abilities
= abilities
.abilities
& ~(I40E_AQ_PHY_FLAG_PAUSE_TX
) &
1217 ~(I40E_AQ_PHY_FLAG_PAUSE_RX
);
1218 /* set the new abilities */
1219 config
.abilities
|= pause_mask
;
1220 /* If the abilities have changed, then set the new config */
1221 if (config
.abilities
!= abilities
.abilities
) {
1222 /* Auto restart link so settings take effect */
1224 config
.abilities
|= I40E_AQ_PHY_ENABLE_ATOMIC_LINK
;
1225 /* Copy over all the old settings */
1226 config
.phy_type
= abilities
.phy_type
;
1227 config
.link_speed
= abilities
.link_speed
;
1228 config
.eee_capability
= abilities
.eee_capability
;
1229 config
.eeer
= abilities
.eeer_val
;
1230 config
.low_power_ctrl
= abilities
.d3_lpan
;
1231 status
= i40e_aq_set_phy_config(hw
, &config
, NULL
);
1234 *aq_failures
|= I40E_SET_FC_AQ_FAIL_SET
;
1236 /* Update the link info */
1237 status
= i40e_update_link_info(hw
, true);
1239 /* Wait a little bit (on 40G cards it sometimes takes a really
1240 * long time for link to come back from the atomic reset)
1244 status
= i40e_update_link_info(hw
, true);
1247 *aq_failures
|= I40E_SET_FC_AQ_FAIL_UPDATE
;
1253 * i40e_aq_clear_pxe_mode
1254 * @hw: pointer to the hw struct
1255 * @cmd_details: pointer to command details structure or NULL
1257 * Tell the firmware that the driver is taking over from PXE
1259 i40e_status
i40e_aq_clear_pxe_mode(struct i40e_hw
*hw
,
1260 struct i40e_asq_cmd_details
*cmd_details
)
1263 struct i40e_aq_desc desc
;
1264 struct i40e_aqc_clear_pxe
*cmd
=
1265 (struct i40e_aqc_clear_pxe
*)&desc
.params
.raw
;
1267 i40e_fill_default_direct_cmd_desc(&desc
,
1268 i40e_aqc_opc_clear_pxe_mode
);
1272 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1274 wr32(hw
, I40E_GLLAN_RCTL_0
, 0x1);
1280 * i40e_aq_set_link_restart_an
1281 * @hw: pointer to the hw struct
1282 * @enable_link: if true: enable link, if false: disable link
1283 * @cmd_details: pointer to command details structure or NULL
1285 * Sets up the link and restarts the Auto-Negotiation over the link.
1287 i40e_status
i40e_aq_set_link_restart_an(struct i40e_hw
*hw
,
1289 struct i40e_asq_cmd_details
*cmd_details
)
1291 struct i40e_aq_desc desc
;
1292 struct i40e_aqc_set_link_restart_an
*cmd
=
1293 (struct i40e_aqc_set_link_restart_an
*)&desc
.params
.raw
;
1296 i40e_fill_default_direct_cmd_desc(&desc
,
1297 i40e_aqc_opc_set_link_restart_an
);
1299 cmd
->command
= I40E_AQ_PHY_RESTART_AN
;
1301 cmd
->command
|= I40E_AQ_PHY_LINK_ENABLE
;
1303 cmd
->command
&= ~I40E_AQ_PHY_LINK_ENABLE
;
1305 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1311 * i40e_aq_get_link_info
1312 * @hw: pointer to the hw struct
1313 * @enable_lse: enable/disable LinkStatusEvent reporting
1314 * @link: pointer to link status structure - optional
1315 * @cmd_details: pointer to command details structure or NULL
1317 * Returns the link status of the adapter.
1319 i40e_status
i40e_aq_get_link_info(struct i40e_hw
*hw
,
1320 bool enable_lse
, struct i40e_link_status
*link
,
1321 struct i40e_asq_cmd_details
*cmd_details
)
1323 struct i40e_aq_desc desc
;
1324 struct i40e_aqc_get_link_status
*resp
=
1325 (struct i40e_aqc_get_link_status
*)&desc
.params
.raw
;
1326 struct i40e_link_status
*hw_link_info
= &hw
->phy
.link_info
;
1328 bool tx_pause
, rx_pause
;
1331 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_get_link_status
);
1334 command_flags
= I40E_AQ_LSE_ENABLE
;
1336 command_flags
= I40E_AQ_LSE_DISABLE
;
1337 resp
->command_flags
= cpu_to_le16(command_flags
);
1339 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1342 goto aq_get_link_info_exit
;
1344 /* save off old link status information */
1345 hw
->phy
.link_info_old
= *hw_link_info
;
1347 /* update link status */
1348 hw_link_info
->phy_type
= (enum i40e_aq_phy_type
)resp
->phy_type
;
1349 hw
->phy
.media_type
= i40e_get_media_type(hw
);
1350 hw_link_info
->link_speed
= (enum i40e_aq_link_speed
)resp
->link_speed
;
1351 hw_link_info
->link_info
= resp
->link_info
;
1352 hw_link_info
->an_info
= resp
->an_info
;
1353 hw_link_info
->ext_info
= resp
->ext_info
;
1354 hw_link_info
->loopback
= resp
->loopback
;
1355 hw_link_info
->max_frame_size
= le16_to_cpu(resp
->max_frame_size
);
1356 hw_link_info
->pacing
= resp
->config
& I40E_AQ_CONFIG_PACING_MASK
;
1358 /* update fc info */
1359 tx_pause
= !!(resp
->an_info
& I40E_AQ_LINK_PAUSE_TX
);
1360 rx_pause
= !!(resp
->an_info
& I40E_AQ_LINK_PAUSE_RX
);
1361 if (tx_pause
& rx_pause
)
1362 hw
->fc
.current_mode
= I40E_FC_FULL
;
1364 hw
->fc
.current_mode
= I40E_FC_TX_PAUSE
;
1366 hw
->fc
.current_mode
= I40E_FC_RX_PAUSE
;
1368 hw
->fc
.current_mode
= I40E_FC_NONE
;
1370 if (resp
->config
& I40E_AQ_CONFIG_CRC_ENA
)
1371 hw_link_info
->crc_enable
= true;
1373 hw_link_info
->crc_enable
= false;
1375 if (resp
->command_flags
& cpu_to_le16(I40E_AQ_LSE_ENABLE
))
1376 hw_link_info
->lse_enable
= true;
1378 hw_link_info
->lse_enable
= false;
1380 /* save link status information */
1382 *link
= *hw_link_info
;
1384 /* flag cleared so helper functions don't call AQ again */
1385 hw
->phy
.get_link_info
= false;
1387 aq_get_link_info_exit
:
1392 * i40e_update_link_info
1393 * @hw: pointer to the hw struct
1394 * @enable_lse: enable/disable LinkStatusEvent reporting
1396 * Returns the link status of the adapter
1398 i40e_status
i40e_update_link_info(struct i40e_hw
*hw
, bool enable_lse
)
1400 struct i40e_aq_get_phy_abilities_resp abilities
;
1403 status
= i40e_aq_get_link_info(hw
, enable_lse
, NULL
, NULL
);
1407 status
= i40e_aq_get_phy_capabilities(hw
, false, false,
1412 if (abilities
.abilities
& I40E_AQ_PHY_AN_ENABLED
)
1413 hw
->phy
.link_info
.an_enabled
= true;
1415 hw
->phy
.link_info
.an_enabled
= false;
1422 * @hw: pointer to the hw struct
1423 * @vsi_ctx: pointer to a vsi context struct
1424 * @cmd_details: pointer to command details structure or NULL
1426 * Add a VSI context to the hardware.
1428 i40e_status
i40e_aq_add_vsi(struct i40e_hw
*hw
,
1429 struct i40e_vsi_context
*vsi_ctx
,
1430 struct i40e_asq_cmd_details
*cmd_details
)
1432 struct i40e_aq_desc desc
;
1433 struct i40e_aqc_add_get_update_vsi
*cmd
=
1434 (struct i40e_aqc_add_get_update_vsi
*)&desc
.params
.raw
;
1435 struct i40e_aqc_add_get_update_vsi_completion
*resp
=
1436 (struct i40e_aqc_add_get_update_vsi_completion
*)
1440 i40e_fill_default_direct_cmd_desc(&desc
,
1441 i40e_aqc_opc_add_vsi
);
1443 cmd
->uplink_seid
= cpu_to_le16(vsi_ctx
->uplink_seid
);
1444 cmd
->connection_type
= vsi_ctx
->connection_type
;
1445 cmd
->vf_id
= vsi_ctx
->vf_num
;
1446 cmd
->vsi_flags
= cpu_to_le16(vsi_ctx
->flags
);
1448 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
1450 status
= i40e_asq_send_command(hw
, &desc
, &vsi_ctx
->info
,
1451 sizeof(vsi_ctx
->info
), cmd_details
);
1454 goto aq_add_vsi_exit
;
1456 vsi_ctx
->seid
= le16_to_cpu(resp
->seid
);
1457 vsi_ctx
->vsi_number
= le16_to_cpu(resp
->vsi_number
);
1458 vsi_ctx
->vsis_allocated
= le16_to_cpu(resp
->vsi_used
);
1459 vsi_ctx
->vsis_unallocated
= le16_to_cpu(resp
->vsi_free
);
1466 * i40e_aq_set_vsi_unicast_promiscuous
1467 * @hw: pointer to the hw struct
1469 * @set: set unicast promiscuous enable/disable
1470 * @cmd_details: pointer to command details structure or NULL
1472 i40e_status
i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw
*hw
,
1474 struct i40e_asq_cmd_details
*cmd_details
)
1476 struct i40e_aq_desc desc
;
1477 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
1478 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
1482 i40e_fill_default_direct_cmd_desc(&desc
,
1483 i40e_aqc_opc_set_vsi_promiscuous_modes
);
1486 flags
|= I40E_AQC_SET_VSI_PROMISC_UNICAST
;
1488 cmd
->promiscuous_flags
= cpu_to_le16(flags
);
1490 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST
);
1492 cmd
->seid
= cpu_to_le16(seid
);
1493 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1499 * i40e_aq_set_vsi_multicast_promiscuous
1500 * @hw: pointer to the hw struct
1502 * @set: set multicast promiscuous enable/disable
1503 * @cmd_details: pointer to command details structure or NULL
1505 i40e_status
i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw
*hw
,
1506 u16 seid
, bool set
, struct i40e_asq_cmd_details
*cmd_details
)
1508 struct i40e_aq_desc desc
;
1509 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
1510 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
1514 i40e_fill_default_direct_cmd_desc(&desc
,
1515 i40e_aqc_opc_set_vsi_promiscuous_modes
);
1518 flags
|= I40E_AQC_SET_VSI_PROMISC_MULTICAST
;
1520 cmd
->promiscuous_flags
= cpu_to_le16(flags
);
1522 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST
);
1524 cmd
->seid
= cpu_to_le16(seid
);
1525 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1531 * i40e_aq_set_vsi_broadcast
1532 * @hw: pointer to the hw struct
1534 * @set_filter: true to set filter, false to clear filter
1535 * @cmd_details: pointer to command details structure or NULL
1537 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1539 i40e_status
i40e_aq_set_vsi_broadcast(struct i40e_hw
*hw
,
1540 u16 seid
, bool set_filter
,
1541 struct i40e_asq_cmd_details
*cmd_details
)
1543 struct i40e_aq_desc desc
;
1544 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
1545 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
1548 i40e_fill_default_direct_cmd_desc(&desc
,
1549 i40e_aqc_opc_set_vsi_promiscuous_modes
);
1552 cmd
->promiscuous_flags
1553 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST
);
1555 cmd
->promiscuous_flags
1556 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST
);
1558 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST
);
1559 cmd
->seid
= cpu_to_le16(seid
);
1560 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1566 * i40e_get_vsi_params - get VSI configuration info
1567 * @hw: pointer to the hw struct
1568 * @vsi_ctx: pointer to a vsi context struct
1569 * @cmd_details: pointer to command details structure or NULL
1571 i40e_status
i40e_aq_get_vsi_params(struct i40e_hw
*hw
,
1572 struct i40e_vsi_context
*vsi_ctx
,
1573 struct i40e_asq_cmd_details
*cmd_details
)
1575 struct i40e_aq_desc desc
;
1576 struct i40e_aqc_add_get_update_vsi
*cmd
=
1577 (struct i40e_aqc_add_get_update_vsi
*)&desc
.params
.raw
;
1578 struct i40e_aqc_add_get_update_vsi_completion
*resp
=
1579 (struct i40e_aqc_add_get_update_vsi_completion
*)
1583 i40e_fill_default_direct_cmd_desc(&desc
,
1584 i40e_aqc_opc_get_vsi_parameters
);
1586 cmd
->uplink_seid
= cpu_to_le16(vsi_ctx
->seid
);
1588 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
1590 status
= i40e_asq_send_command(hw
, &desc
, &vsi_ctx
->info
,
1591 sizeof(vsi_ctx
->info
), NULL
);
1594 goto aq_get_vsi_params_exit
;
1596 vsi_ctx
->seid
= le16_to_cpu(resp
->seid
);
1597 vsi_ctx
->vsi_number
= le16_to_cpu(resp
->vsi_number
);
1598 vsi_ctx
->vsis_allocated
= le16_to_cpu(resp
->vsi_used
);
1599 vsi_ctx
->vsis_unallocated
= le16_to_cpu(resp
->vsi_free
);
1601 aq_get_vsi_params_exit
:
1606 * i40e_aq_update_vsi_params
1607 * @hw: pointer to the hw struct
1608 * @vsi_ctx: pointer to a vsi context struct
1609 * @cmd_details: pointer to command details structure or NULL
1611 * Update a VSI context.
1613 i40e_status
i40e_aq_update_vsi_params(struct i40e_hw
*hw
,
1614 struct i40e_vsi_context
*vsi_ctx
,
1615 struct i40e_asq_cmd_details
*cmd_details
)
1617 struct i40e_aq_desc desc
;
1618 struct i40e_aqc_add_get_update_vsi
*cmd
=
1619 (struct i40e_aqc_add_get_update_vsi
*)&desc
.params
.raw
;
1622 i40e_fill_default_direct_cmd_desc(&desc
,
1623 i40e_aqc_opc_update_vsi_parameters
);
1624 cmd
->uplink_seid
= cpu_to_le16(vsi_ctx
->seid
);
1626 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
1628 status
= i40e_asq_send_command(hw
, &desc
, &vsi_ctx
->info
,
1629 sizeof(vsi_ctx
->info
), cmd_details
);
1635 * i40e_aq_get_switch_config
1636 * @hw: pointer to the hardware structure
1637 * @buf: pointer to the result buffer
1638 * @buf_size: length of input buffer
1639 * @start_seid: seid to start for the report, 0 == beginning
1640 * @cmd_details: pointer to command details structure or NULL
1642 * Fill the buf with switch configuration returned from AdminQ command
1644 i40e_status
i40e_aq_get_switch_config(struct i40e_hw
*hw
,
1645 struct i40e_aqc_get_switch_config_resp
*buf
,
1646 u16 buf_size
, u16
*start_seid
,
1647 struct i40e_asq_cmd_details
*cmd_details
)
1649 struct i40e_aq_desc desc
;
1650 struct i40e_aqc_switch_seid
*scfg
=
1651 (struct i40e_aqc_switch_seid
*)&desc
.params
.raw
;
1654 i40e_fill_default_direct_cmd_desc(&desc
,
1655 i40e_aqc_opc_get_switch_config
);
1656 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
1657 if (buf_size
> I40E_AQ_LARGE_BUF
)
1658 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
1659 scfg
->seid
= cpu_to_le16(*start_seid
);
1661 status
= i40e_asq_send_command(hw
, &desc
, buf
, buf_size
, cmd_details
);
1662 *start_seid
= le16_to_cpu(scfg
->seid
);
1668 * i40e_aq_get_firmware_version
1669 * @hw: pointer to the hw struct
1670 * @fw_major_version: firmware major version
1671 * @fw_minor_version: firmware minor version
1672 * @api_major_version: major queue version
1673 * @api_minor_version: minor queue version
1674 * @cmd_details: pointer to command details structure or NULL
1676 * Get the firmware version from the admin queue commands
1678 i40e_status
i40e_aq_get_firmware_version(struct i40e_hw
*hw
,
1679 u16
*fw_major_version
, u16
*fw_minor_version
,
1680 u16
*api_major_version
, u16
*api_minor_version
,
1681 struct i40e_asq_cmd_details
*cmd_details
)
1683 struct i40e_aq_desc desc
;
1684 struct i40e_aqc_get_version
*resp
=
1685 (struct i40e_aqc_get_version
*)&desc
.params
.raw
;
1688 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_get_version
);
1690 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1693 if (fw_major_version
!= NULL
)
1694 *fw_major_version
= le16_to_cpu(resp
->fw_major
);
1695 if (fw_minor_version
!= NULL
)
1696 *fw_minor_version
= le16_to_cpu(resp
->fw_minor
);
1697 if (api_major_version
!= NULL
)
1698 *api_major_version
= le16_to_cpu(resp
->api_major
);
1699 if (api_minor_version
!= NULL
)
1700 *api_minor_version
= le16_to_cpu(resp
->api_minor
);
1707 * i40e_aq_send_driver_version
1708 * @hw: pointer to the hw struct
1709 * @dv: driver's major, minor version
1710 * @cmd_details: pointer to command details structure or NULL
1712 * Send the driver version to the firmware
1714 i40e_status
i40e_aq_send_driver_version(struct i40e_hw
*hw
,
1715 struct i40e_driver_version
*dv
,
1716 struct i40e_asq_cmd_details
*cmd_details
)
1718 struct i40e_aq_desc desc
;
1719 struct i40e_aqc_driver_version
*cmd
=
1720 (struct i40e_aqc_driver_version
*)&desc
.params
.raw
;
1725 return I40E_ERR_PARAM
;
1727 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_driver_version
);
1729 desc
.flags
|= cpu_to_le16(I40E_AQ_FLAG_SI
);
1730 cmd
->driver_major_ver
= dv
->major_version
;
1731 cmd
->driver_minor_ver
= dv
->minor_version
;
1732 cmd
->driver_build_ver
= dv
->build_version
;
1733 cmd
->driver_subbuild_ver
= dv
->subbuild_version
;
1736 while (len
< sizeof(dv
->driver_string
) &&
1737 (dv
->driver_string
[len
] < 0x80) &&
1738 dv
->driver_string
[len
])
1740 status
= i40e_asq_send_command(hw
, &desc
, dv
->driver_string
,
1747 * i40e_get_link_status - get status of the HW network link
1748 * @hw: pointer to the hw struct
1750 * Returns true if link is up, false if link is down.
1752 * Side effect: LinkStatusEvent reporting becomes enabled
1754 bool i40e_get_link_status(struct i40e_hw
*hw
)
1756 i40e_status status
= 0;
1757 bool link_status
= false;
1759 if (hw
->phy
.get_link_info
) {
1760 status
= i40e_aq_get_link_info(hw
, true, NULL
, NULL
);
1763 goto i40e_get_link_status_exit
;
1766 link_status
= hw
->phy
.link_info
.link_info
& I40E_AQ_LINK_UP
;
1768 i40e_get_link_status_exit
:
1773 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1774 * @hw: pointer to the hw struct
1775 * @uplink_seid: the MAC or other gizmo SEID
1776 * @downlink_seid: the VSI SEID
1777 * @enabled_tc: bitmap of TCs to be enabled
1778 * @default_port: true for default port VSI, false for control port
1779 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
1780 * @veb_seid: pointer to where to put the resulting VEB SEID
1781 * @cmd_details: pointer to command details structure or NULL
1783 * This asks the FW to add a VEB between the uplink and downlink
1784 * elements. If the uplink SEID is 0, this will be a floating VEB.
1786 i40e_status
i40e_aq_add_veb(struct i40e_hw
*hw
, u16 uplink_seid
,
1787 u16 downlink_seid
, u8 enabled_tc
,
1788 bool default_port
, bool enable_l2_filtering
,
1790 struct i40e_asq_cmd_details
*cmd_details
)
1792 struct i40e_aq_desc desc
;
1793 struct i40e_aqc_add_veb
*cmd
=
1794 (struct i40e_aqc_add_veb
*)&desc
.params
.raw
;
1795 struct i40e_aqc_add_veb_completion
*resp
=
1796 (struct i40e_aqc_add_veb_completion
*)&desc
.params
.raw
;
1800 /* SEIDs need to either both be set or both be 0 for floating VEB */
1801 if (!!uplink_seid
!= !!downlink_seid
)
1802 return I40E_ERR_PARAM
;
1804 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_add_veb
);
1806 cmd
->uplink_seid
= cpu_to_le16(uplink_seid
);
1807 cmd
->downlink_seid
= cpu_to_le16(downlink_seid
);
1808 cmd
->enable_tcs
= enabled_tc
;
1810 veb_flags
|= I40E_AQC_ADD_VEB_FLOATING
;
1812 veb_flags
|= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT
;
1814 veb_flags
|= I40E_AQC_ADD_VEB_PORT_TYPE_DATA
;
1816 if (enable_l2_filtering
)
1817 veb_flags
|= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER
;
1819 cmd
->veb_flags
= cpu_to_le16(veb_flags
);
1821 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1823 if (!status
&& veb_seid
)
1824 *veb_seid
= le16_to_cpu(resp
->veb_seid
);
1830 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1831 * @hw: pointer to the hw struct
1832 * @veb_seid: the SEID of the VEB to query
1833 * @switch_id: the uplink switch id
1834 * @floating: set to true if the VEB is floating
1835 * @statistic_index: index of the stats counter block for this VEB
1836 * @vebs_used: number of VEB's used by function
1837 * @vebs_free: total VEB's not reserved by any function
1838 * @cmd_details: pointer to command details structure or NULL
1840 * This retrieves the parameters for a particular VEB, specified by
1841 * uplink_seid, and returns them to the caller.
1843 i40e_status
i40e_aq_get_veb_parameters(struct i40e_hw
*hw
,
1844 u16 veb_seid
, u16
*switch_id
,
1845 bool *floating
, u16
*statistic_index
,
1846 u16
*vebs_used
, u16
*vebs_free
,
1847 struct i40e_asq_cmd_details
*cmd_details
)
1849 struct i40e_aq_desc desc
;
1850 struct i40e_aqc_get_veb_parameters_completion
*cmd_resp
=
1851 (struct i40e_aqc_get_veb_parameters_completion
*)
1856 return I40E_ERR_PARAM
;
1858 i40e_fill_default_direct_cmd_desc(&desc
,
1859 i40e_aqc_opc_get_veb_parameters
);
1860 cmd_resp
->seid
= cpu_to_le16(veb_seid
);
1862 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1867 *switch_id
= le16_to_cpu(cmd_resp
->switch_id
);
1868 if (statistic_index
)
1869 *statistic_index
= le16_to_cpu(cmd_resp
->statistic_index
);
1871 *vebs_used
= le16_to_cpu(cmd_resp
->vebs_used
);
1873 *vebs_free
= le16_to_cpu(cmd_resp
->vebs_free
);
1875 u16 flags
= le16_to_cpu(cmd_resp
->veb_flags
);
1876 if (flags
& I40E_AQC_ADD_VEB_FLOATING
)
1887 * i40e_aq_add_macvlan
1888 * @hw: pointer to the hw struct
1889 * @seid: VSI for the mac address
1890 * @mv_list: list of macvlans to be added
1891 * @count: length of the list
1892 * @cmd_details: pointer to command details structure or NULL
1894 * Add MAC/VLAN addresses to the HW filtering
1896 i40e_status
i40e_aq_add_macvlan(struct i40e_hw
*hw
, u16 seid
,
1897 struct i40e_aqc_add_macvlan_element_data
*mv_list
,
1898 u16 count
, struct i40e_asq_cmd_details
*cmd_details
)
1900 struct i40e_aq_desc desc
;
1901 struct i40e_aqc_macvlan
*cmd
=
1902 (struct i40e_aqc_macvlan
*)&desc
.params
.raw
;
1906 if (count
== 0 || !mv_list
|| !hw
)
1907 return I40E_ERR_PARAM
;
1909 buf_size
= count
* sizeof(struct i40e_aqc_add_macvlan_element_data
);
1911 /* prep the rest of the request */
1912 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_add_macvlan
);
1913 cmd
->num_addresses
= cpu_to_le16(count
);
1914 cmd
->seid
[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID
| seid
);
1918 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
1919 if (buf_size
> I40E_AQ_LARGE_BUF
)
1920 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
1922 status
= i40e_asq_send_command(hw
, &desc
, mv_list
, buf_size
,
1929 * i40e_aq_remove_macvlan
1930 * @hw: pointer to the hw struct
1931 * @seid: VSI for the mac address
1932 * @mv_list: list of macvlans to be removed
1933 * @count: length of the list
1934 * @cmd_details: pointer to command details structure or NULL
1936 * Remove MAC/VLAN addresses from the HW filtering
1938 i40e_status
i40e_aq_remove_macvlan(struct i40e_hw
*hw
, u16 seid
,
1939 struct i40e_aqc_remove_macvlan_element_data
*mv_list
,
1940 u16 count
, struct i40e_asq_cmd_details
*cmd_details
)
1942 struct i40e_aq_desc desc
;
1943 struct i40e_aqc_macvlan
*cmd
=
1944 (struct i40e_aqc_macvlan
*)&desc
.params
.raw
;
1948 if (count
== 0 || !mv_list
|| !hw
)
1949 return I40E_ERR_PARAM
;
1951 buf_size
= count
* sizeof(struct i40e_aqc_remove_macvlan_element_data
);
1953 /* prep the rest of the request */
1954 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_remove_macvlan
);
1955 cmd
->num_addresses
= cpu_to_le16(count
);
1956 cmd
->seid
[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID
| seid
);
1960 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
1961 if (buf_size
> I40E_AQ_LARGE_BUF
)
1962 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
1964 status
= i40e_asq_send_command(hw
, &desc
, mv_list
, buf_size
,
1971 * i40e_aq_send_msg_to_vf
1972 * @hw: pointer to the hardware structure
1973 * @vfid: vf id to send msg
1974 * @v_opcode: opcodes for VF-PF communication
1975 * @v_retval: return error code
1976 * @msg: pointer to the msg buffer
1977 * @msglen: msg length
1978 * @cmd_details: pointer to command details
1982 i40e_status
i40e_aq_send_msg_to_vf(struct i40e_hw
*hw
, u16 vfid
,
1983 u32 v_opcode
, u32 v_retval
, u8
*msg
, u16 msglen
,
1984 struct i40e_asq_cmd_details
*cmd_details
)
1986 struct i40e_aq_desc desc
;
1987 struct i40e_aqc_pf_vf_message
*cmd
=
1988 (struct i40e_aqc_pf_vf_message
*)&desc
.params
.raw
;
1991 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_send_msg_to_vf
);
1992 cmd
->id
= cpu_to_le32(vfid
);
1993 desc
.cookie_high
= cpu_to_le32(v_opcode
);
1994 desc
.cookie_low
= cpu_to_le32(v_retval
);
1995 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_SI
);
1997 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
|
1999 if (msglen
> I40E_AQ_LARGE_BUF
)
2000 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2001 desc
.datalen
= cpu_to_le16(msglen
);
2003 status
= i40e_asq_send_command(hw
, &desc
, msg
, msglen
, cmd_details
);
2009 * i40e_aq_debug_write_register
2010 * @hw: pointer to the hw struct
2011 * @reg_addr: register address
2012 * @reg_val: register value
2013 * @cmd_details: pointer to command details structure or NULL
2015 * Write to a register using the admin queue commands
2017 i40e_status
i40e_aq_debug_write_register(struct i40e_hw
*hw
,
2018 u32 reg_addr
, u64 reg_val
,
2019 struct i40e_asq_cmd_details
*cmd_details
)
2021 struct i40e_aq_desc desc
;
2022 struct i40e_aqc_debug_reg_read_write
*cmd
=
2023 (struct i40e_aqc_debug_reg_read_write
*)&desc
.params
.raw
;
2026 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_debug_write_reg
);
2028 cmd
->address
= cpu_to_le32(reg_addr
);
2029 cmd
->value_high
= cpu_to_le32((u32
)(reg_val
>> 32));
2030 cmd
->value_low
= cpu_to_le32((u32
)(reg_val
& 0xFFFFFFFF));
2032 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2038 * i40e_aq_set_hmc_resource_profile
2039 * @hw: pointer to the hw struct
2040 * @profile: type of profile the HMC is to be set as
2041 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2042 * @cmd_details: pointer to command details structure or NULL
2044 * set the HMC profile of the device.
2046 i40e_status
i40e_aq_set_hmc_resource_profile(struct i40e_hw
*hw
,
2047 enum i40e_aq_hmc_profile profile
,
2048 u8 pe_vf_enabled_count
,
2049 struct i40e_asq_cmd_details
*cmd_details
)
2051 struct i40e_aq_desc desc
;
2052 struct i40e_aq_get_set_hmc_resource_profile
*cmd
=
2053 (struct i40e_aq_get_set_hmc_resource_profile
*)&desc
.params
.raw
;
2056 i40e_fill_default_direct_cmd_desc(&desc
,
2057 i40e_aqc_opc_set_hmc_resource_profile
);
2059 cmd
->pm_profile
= (u8
)profile
;
2060 cmd
->pe_vf_enabled
= pe_vf_enabled_count
;
2062 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2068 * i40e_aq_request_resource
2069 * @hw: pointer to the hw struct
2070 * @resource: resource id
2071 * @access: access type
2072 * @sdp_number: resource number
2073 * @timeout: the maximum time in ms that the driver may hold the resource
2074 * @cmd_details: pointer to command details structure or NULL
2076 * requests common resource using the admin queue commands
2078 i40e_status
i40e_aq_request_resource(struct i40e_hw
*hw
,
2079 enum i40e_aq_resources_ids resource
,
2080 enum i40e_aq_resource_access_type access
,
2081 u8 sdp_number
, u64
*timeout
,
2082 struct i40e_asq_cmd_details
*cmd_details
)
2084 struct i40e_aq_desc desc
;
2085 struct i40e_aqc_request_resource
*cmd_resp
=
2086 (struct i40e_aqc_request_resource
*)&desc
.params
.raw
;
2089 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_request_resource
);
2091 cmd_resp
->resource_id
= cpu_to_le16(resource
);
2092 cmd_resp
->access_type
= cpu_to_le16(access
);
2093 cmd_resp
->resource_number
= cpu_to_le32(sdp_number
);
2095 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2096 /* The completion specifies the maximum time in ms that the driver
2097 * may hold the resource in the Timeout field.
2098 * If the resource is held by someone else, the command completes with
2099 * busy return value and the timeout field indicates the maximum time
2100 * the current owner of the resource has to free it.
2102 if (!status
|| hw
->aq
.asq_last_status
== I40E_AQ_RC_EBUSY
)
2103 *timeout
= le32_to_cpu(cmd_resp
->timeout
);
2109 * i40e_aq_release_resource
2110 * @hw: pointer to the hw struct
2111 * @resource: resource id
2112 * @sdp_number: resource number
2113 * @cmd_details: pointer to command details structure or NULL
2115 * release common resource using the admin queue commands
2117 i40e_status
i40e_aq_release_resource(struct i40e_hw
*hw
,
2118 enum i40e_aq_resources_ids resource
,
2120 struct i40e_asq_cmd_details
*cmd_details
)
2122 struct i40e_aq_desc desc
;
2123 struct i40e_aqc_request_resource
*cmd
=
2124 (struct i40e_aqc_request_resource
*)&desc
.params
.raw
;
2127 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_release_resource
);
2129 cmd
->resource_id
= cpu_to_le16(resource
);
2130 cmd
->resource_number
= cpu_to_le32(sdp_number
);
2132 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2139 * @hw: pointer to the hw struct
2140 * @module_pointer: module pointer location in words from the NVM beginning
2141 * @offset: byte offset from the module beginning
2142 * @length: length of the section to be read (in bytes from the offset)
2143 * @data: command buffer (size [bytes] = length)
2144 * @last_command: tells if this is the last command in a series
2145 * @cmd_details: pointer to command details structure or NULL
2147 * Read the NVM using the admin queue commands
2149 i40e_status
i40e_aq_read_nvm(struct i40e_hw
*hw
, u8 module_pointer
,
2150 u32 offset
, u16 length
, void *data
,
2152 struct i40e_asq_cmd_details
*cmd_details
)
2154 struct i40e_aq_desc desc
;
2155 struct i40e_aqc_nvm_update
*cmd
=
2156 (struct i40e_aqc_nvm_update
*)&desc
.params
.raw
;
2159 /* In offset the highest byte must be zeroed. */
2160 if (offset
& 0xFF000000) {
2161 status
= I40E_ERR_PARAM
;
2162 goto i40e_aq_read_nvm_exit
;
2165 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_nvm_read
);
2167 /* If this is the last command in a series, set the proper flag. */
2169 cmd
->command_flags
|= I40E_AQ_NVM_LAST_CMD
;
2170 cmd
->module_pointer
= module_pointer
;
2171 cmd
->offset
= cpu_to_le32(offset
);
2172 cmd
->length
= cpu_to_le16(length
);
2174 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2175 if (length
> I40E_AQ_LARGE_BUF
)
2176 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2178 status
= i40e_asq_send_command(hw
, &desc
, data
, length
, cmd_details
);
2180 i40e_aq_read_nvm_exit
:
2186 * @hw: pointer to the hw struct
2187 * @module_pointer: module pointer location in words from the NVM beginning
2188 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2189 * @length: length of the section to be erased (expressed in 4 KB)
2190 * @last_command: tells if this is the last command in a series
2191 * @cmd_details: pointer to command details structure or NULL
2193 * Erase the NVM sector using the admin queue commands
2195 i40e_status
i40e_aq_erase_nvm(struct i40e_hw
*hw
, u8 module_pointer
,
2196 u32 offset
, u16 length
, bool last_command
,
2197 struct i40e_asq_cmd_details
*cmd_details
)
2199 struct i40e_aq_desc desc
;
2200 struct i40e_aqc_nvm_update
*cmd
=
2201 (struct i40e_aqc_nvm_update
*)&desc
.params
.raw
;
2204 /* In offset the highest byte must be zeroed. */
2205 if (offset
& 0xFF000000) {
2206 status
= I40E_ERR_PARAM
;
2207 goto i40e_aq_erase_nvm_exit
;
2210 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_nvm_erase
);
2212 /* If this is the last command in a series, set the proper flag. */
2214 cmd
->command_flags
|= I40E_AQ_NVM_LAST_CMD
;
2215 cmd
->module_pointer
= module_pointer
;
2216 cmd
->offset
= cpu_to_le32(offset
);
2217 cmd
->length
= cpu_to_le16(length
);
2219 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2221 i40e_aq_erase_nvm_exit
:
2225 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2226 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2227 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2228 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2229 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2230 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2231 #define I40E_DEV_FUNC_CAP_VF 0x13
2232 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2233 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2234 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2235 #define I40E_DEV_FUNC_CAP_VSI 0x17
2236 #define I40E_DEV_FUNC_CAP_DCB 0x18
2237 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2238 #define I40E_DEV_FUNC_CAP_RSS 0x40
2239 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2240 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2241 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2242 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2243 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2244 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2245 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2246 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2247 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2248 #define I40E_DEV_FUNC_CAP_LED 0x61
2249 #define I40E_DEV_FUNC_CAP_SDP 0x62
2250 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2253 * i40e_parse_discover_capabilities
2254 * @hw: pointer to the hw struct
2255 * @buff: pointer to a buffer containing device/function capability records
2256 * @cap_count: number of capability records in the list
2257 * @list_type_opc: type of capabilities list to parse
2259 * Parse the device/function capabilities list.
2261 static void i40e_parse_discover_capabilities(struct i40e_hw
*hw
, void *buff
,
2263 enum i40e_admin_queue_opc list_type_opc
)
2265 struct i40e_aqc_list_capabilities_element_resp
*cap
;
2266 u32 number
, logical_id
, phys_id
;
2267 struct i40e_hw_capabilities
*p
;
2271 cap
= (struct i40e_aqc_list_capabilities_element_resp
*) buff
;
2273 if (list_type_opc
== i40e_aqc_opc_list_dev_capabilities
)
2275 else if (list_type_opc
== i40e_aqc_opc_list_func_capabilities
)
2280 for (i
= 0; i
< cap_count
; i
++, cap
++) {
2281 id
= le16_to_cpu(cap
->id
);
2282 number
= le32_to_cpu(cap
->number
);
2283 logical_id
= le32_to_cpu(cap
->logical_id
);
2284 phys_id
= le32_to_cpu(cap
->phys_id
);
2287 case I40E_DEV_FUNC_CAP_SWITCH_MODE
:
2288 p
->switch_mode
= number
;
2290 case I40E_DEV_FUNC_CAP_MGMT_MODE
:
2291 p
->management_mode
= number
;
2293 case I40E_DEV_FUNC_CAP_NPAR
:
2294 p
->npar_enable
= number
;
2296 case I40E_DEV_FUNC_CAP_OS2BMC
:
2299 case I40E_DEV_FUNC_CAP_VALID_FUNC
:
2300 p
->valid_functions
= number
;
2302 case I40E_DEV_FUNC_CAP_SRIOV_1_1
:
2304 p
->sr_iov_1_1
= true;
2306 case I40E_DEV_FUNC_CAP_VF
:
2307 p
->num_vfs
= number
;
2308 p
->vf_base_id
= logical_id
;
2310 case I40E_DEV_FUNC_CAP_VMDQ
:
2314 case I40E_DEV_FUNC_CAP_802_1_QBG
:
2316 p
->evb_802_1_qbg
= true;
2318 case I40E_DEV_FUNC_CAP_802_1_QBH
:
2320 p
->evb_802_1_qbh
= true;
2322 case I40E_DEV_FUNC_CAP_VSI
:
2323 p
->num_vsis
= number
;
2325 case I40E_DEV_FUNC_CAP_DCB
:
2328 p
->enabled_tcmap
= logical_id
;
2332 case I40E_DEV_FUNC_CAP_FCOE
:
2336 case I40E_DEV_FUNC_CAP_RSS
:
2338 p
->rss_table_size
= number
;
2339 p
->rss_table_entry_width
= logical_id
;
2341 case I40E_DEV_FUNC_CAP_RX_QUEUES
:
2342 p
->num_rx_qp
= number
;
2343 p
->base_queue
= phys_id
;
2345 case I40E_DEV_FUNC_CAP_TX_QUEUES
:
2346 p
->num_tx_qp
= number
;
2347 p
->base_queue
= phys_id
;
2349 case I40E_DEV_FUNC_CAP_MSIX
:
2350 p
->num_msix_vectors
= number
;
2352 case I40E_DEV_FUNC_CAP_MSIX_VF
:
2353 p
->num_msix_vectors_vf
= number
;
2355 case I40E_DEV_FUNC_CAP_MFP_MODE_1
:
2357 p
->mfp_mode_1
= true;
2359 case I40E_DEV_FUNC_CAP_CEM
:
2363 case I40E_DEV_FUNC_CAP_IWARP
:
2367 case I40E_DEV_FUNC_CAP_LED
:
2368 if (phys_id
< I40E_HW_CAP_MAX_GPIO
)
2369 p
->led
[phys_id
] = true;
2371 case I40E_DEV_FUNC_CAP_SDP
:
2372 if (phys_id
< I40E_HW_CAP_MAX_GPIO
)
2373 p
->sdp
[phys_id
] = true;
2375 case I40E_DEV_FUNC_CAP_MDIO
:
2377 p
->mdio_port_num
= phys_id
;
2378 p
->mdio_port_mode
= logical_id
;
2381 case I40E_DEV_FUNC_CAP_IEEE_1588
:
2383 p
->ieee_1588
= true;
2385 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR
:
2387 p
->fd_filters_guaranteed
= number
;
2388 p
->fd_filters_best_effort
= logical_id
;
2395 /* Software override ensuring FCoE is disabled if npar or mfp
2396 * mode because it is not supported in these modes.
2398 if (p
->npar_enable
|| p
->mfp_mode_1
)
2401 /* additional HW specific goodies that might
2402 * someday be HW version specific
2404 p
->rx_buf_chain_len
= I40E_MAX_CHAINED_RX_BUFFERS
;
2408 * i40e_aq_discover_capabilities
2409 * @hw: pointer to the hw struct
2410 * @buff: a virtual buffer to hold the capabilities
2411 * @buff_size: Size of the virtual buffer
2412 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2413 * @list_type_opc: capabilities type to discover - pass in the command opcode
2414 * @cmd_details: pointer to command details structure or NULL
2416 * Get the device capabilities descriptions from the firmware
2418 i40e_status
i40e_aq_discover_capabilities(struct i40e_hw
*hw
,
2419 void *buff
, u16 buff_size
, u16
*data_size
,
2420 enum i40e_admin_queue_opc list_type_opc
,
2421 struct i40e_asq_cmd_details
*cmd_details
)
2423 struct i40e_aqc_list_capabilites
*cmd
;
2424 struct i40e_aq_desc desc
;
2425 i40e_status status
= 0;
2427 cmd
= (struct i40e_aqc_list_capabilites
*)&desc
.params
.raw
;
2429 if (list_type_opc
!= i40e_aqc_opc_list_func_capabilities
&&
2430 list_type_opc
!= i40e_aqc_opc_list_dev_capabilities
) {
2431 status
= I40E_ERR_PARAM
;
2435 i40e_fill_default_direct_cmd_desc(&desc
, list_type_opc
);
2437 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2438 if (buff_size
> I40E_AQ_LARGE_BUF
)
2439 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2441 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
2442 *data_size
= le16_to_cpu(desc
.datalen
);
2447 i40e_parse_discover_capabilities(hw
, buff
, le32_to_cpu(cmd
->count
),
2455 * i40e_aq_update_nvm
2456 * @hw: pointer to the hw struct
2457 * @module_pointer: module pointer location in words from the NVM beginning
2458 * @offset: byte offset from the module beginning
2459 * @length: length of the section to be written (in bytes from the offset)
2460 * @data: command buffer (size [bytes] = length)
2461 * @last_command: tells if this is the last command in a series
2462 * @cmd_details: pointer to command details structure or NULL
2464 * Update the NVM using the admin queue commands
2466 i40e_status
i40e_aq_update_nvm(struct i40e_hw
*hw
, u8 module_pointer
,
2467 u32 offset
, u16 length
, void *data
,
2469 struct i40e_asq_cmd_details
*cmd_details
)
2471 struct i40e_aq_desc desc
;
2472 struct i40e_aqc_nvm_update
*cmd
=
2473 (struct i40e_aqc_nvm_update
*)&desc
.params
.raw
;
2476 /* In offset the highest byte must be zeroed. */
2477 if (offset
& 0xFF000000) {
2478 status
= I40E_ERR_PARAM
;
2479 goto i40e_aq_update_nvm_exit
;
2482 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_nvm_update
);
2484 /* If this is the last command in a series, set the proper flag. */
2486 cmd
->command_flags
|= I40E_AQ_NVM_LAST_CMD
;
2487 cmd
->module_pointer
= module_pointer
;
2488 cmd
->offset
= cpu_to_le32(offset
);
2489 cmd
->length
= cpu_to_le16(length
);
2491 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
2492 if (length
> I40E_AQ_LARGE_BUF
)
2493 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2495 status
= i40e_asq_send_command(hw
, &desc
, data
, length
, cmd_details
);
2497 i40e_aq_update_nvm_exit
:
2502 * i40e_aq_get_lldp_mib
2503 * @hw: pointer to the hw struct
2504 * @bridge_type: type of bridge requested
2505 * @mib_type: Local, Remote or both Local and Remote MIBs
2506 * @buff: pointer to a user supplied buffer to store the MIB block
2507 * @buff_size: size of the buffer (in bytes)
2508 * @local_len : length of the returned Local LLDP MIB
2509 * @remote_len: length of the returned Remote LLDP MIB
2510 * @cmd_details: pointer to command details structure or NULL
2512 * Requests the complete LLDP MIB (entire packet).
2514 i40e_status
i40e_aq_get_lldp_mib(struct i40e_hw
*hw
, u8 bridge_type
,
2515 u8 mib_type
, void *buff
, u16 buff_size
,
2516 u16
*local_len
, u16
*remote_len
,
2517 struct i40e_asq_cmd_details
*cmd_details
)
2519 struct i40e_aq_desc desc
;
2520 struct i40e_aqc_lldp_get_mib
*cmd
=
2521 (struct i40e_aqc_lldp_get_mib
*)&desc
.params
.raw
;
2522 struct i40e_aqc_lldp_get_mib
*resp
=
2523 (struct i40e_aqc_lldp_get_mib
*)&desc
.params
.raw
;
2526 if (buff_size
== 0 || !buff
)
2527 return I40E_ERR_PARAM
;
2529 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_get_mib
);
2530 /* Indirect Command */
2531 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2533 cmd
->type
= mib_type
& I40E_AQ_LLDP_MIB_TYPE_MASK
;
2534 cmd
->type
|= ((bridge_type
<< I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT
) &
2535 I40E_AQ_LLDP_BRIDGE_TYPE_MASK
);
2537 desc
.datalen
= cpu_to_le16(buff_size
);
2539 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2540 if (buff_size
> I40E_AQ_LARGE_BUF
)
2541 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2543 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
2545 if (local_len
!= NULL
)
2546 *local_len
= le16_to_cpu(resp
->local_len
);
2547 if (remote_len
!= NULL
)
2548 *remote_len
= le16_to_cpu(resp
->remote_len
);
2555 * i40e_aq_cfg_lldp_mib_change_event
2556 * @hw: pointer to the hw struct
2557 * @enable_update: Enable or Disable event posting
2558 * @cmd_details: pointer to command details structure or NULL
2560 * Enable or Disable posting of an event on ARQ when LLDP MIB
2561 * associated with the interface changes
2563 i40e_status
i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw
*hw
,
2565 struct i40e_asq_cmd_details
*cmd_details
)
2567 struct i40e_aq_desc desc
;
2568 struct i40e_aqc_lldp_update_mib
*cmd
=
2569 (struct i40e_aqc_lldp_update_mib
*)&desc
.params
.raw
;
2572 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_update_mib
);
2575 cmd
->command
|= I40E_AQ_LLDP_MIB_UPDATE_DISABLE
;
2577 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2584 * @hw: pointer to the hw struct
2585 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2586 * @cmd_details: pointer to command details structure or NULL
2588 * Stop or Shutdown the embedded LLDP Agent
2590 i40e_status
i40e_aq_stop_lldp(struct i40e_hw
*hw
, bool shutdown_agent
,
2591 struct i40e_asq_cmd_details
*cmd_details
)
2593 struct i40e_aq_desc desc
;
2594 struct i40e_aqc_lldp_stop
*cmd
=
2595 (struct i40e_aqc_lldp_stop
*)&desc
.params
.raw
;
2598 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_stop
);
2601 cmd
->command
|= I40E_AQ_LLDP_AGENT_SHUTDOWN
;
2603 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2609 * i40e_aq_start_lldp
2610 * @hw: pointer to the hw struct
2611 * @cmd_details: pointer to command details structure or NULL
2613 * Start the embedded LLDP Agent on all ports.
2615 i40e_status
i40e_aq_start_lldp(struct i40e_hw
*hw
,
2616 struct i40e_asq_cmd_details
*cmd_details
)
2618 struct i40e_aq_desc desc
;
2619 struct i40e_aqc_lldp_start
*cmd
=
2620 (struct i40e_aqc_lldp_start
*)&desc
.params
.raw
;
2623 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_start
);
2625 cmd
->command
= I40E_AQ_LLDP_AGENT_START
;
2627 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2633 * i40e_aq_add_udp_tunnel
2634 * @hw: pointer to the hw struct
2635 * @udp_port: the UDP port to add
2636 * @header_len: length of the tunneling header length in DWords
2637 * @protocol_index: protocol index type
2638 * @filter_index: pointer to filter index
2639 * @cmd_details: pointer to command details structure or NULL
2641 i40e_status
i40e_aq_add_udp_tunnel(struct i40e_hw
*hw
,
2642 u16 udp_port
, u8 protocol_index
,
2644 struct i40e_asq_cmd_details
*cmd_details
)
2646 struct i40e_aq_desc desc
;
2647 struct i40e_aqc_add_udp_tunnel
*cmd
=
2648 (struct i40e_aqc_add_udp_tunnel
*)&desc
.params
.raw
;
2649 struct i40e_aqc_del_udp_tunnel_completion
*resp
=
2650 (struct i40e_aqc_del_udp_tunnel_completion
*)&desc
.params
.raw
;
2653 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_add_udp_tunnel
);
2655 cmd
->udp_port
= cpu_to_le16(udp_port
);
2656 cmd
->protocol_type
= protocol_index
;
2658 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2661 *filter_index
= resp
->index
;
2667 * i40e_aq_del_udp_tunnel
2668 * @hw: pointer to the hw struct
2669 * @index: filter index
2670 * @cmd_details: pointer to command details structure or NULL
2672 i40e_status
i40e_aq_del_udp_tunnel(struct i40e_hw
*hw
, u8 index
,
2673 struct i40e_asq_cmd_details
*cmd_details
)
2675 struct i40e_aq_desc desc
;
2676 struct i40e_aqc_remove_udp_tunnel
*cmd
=
2677 (struct i40e_aqc_remove_udp_tunnel
*)&desc
.params
.raw
;
2680 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_del_udp_tunnel
);
2684 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2690 * i40e_aq_delete_element - Delete switch element
2691 * @hw: pointer to the hw struct
2692 * @seid: the SEID to delete from the switch
2693 * @cmd_details: pointer to command details structure or NULL
2695 * This deletes a switch element from the switch.
2697 i40e_status
i40e_aq_delete_element(struct i40e_hw
*hw
, u16 seid
,
2698 struct i40e_asq_cmd_details
*cmd_details
)
2700 struct i40e_aq_desc desc
;
2701 struct i40e_aqc_switch_seid
*cmd
=
2702 (struct i40e_aqc_switch_seid
*)&desc
.params
.raw
;
2706 return I40E_ERR_PARAM
;
2708 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_delete_element
);
2710 cmd
->seid
= cpu_to_le16(seid
);
2712 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2718 * i40e_aq_dcb_updated - DCB Updated Command
2719 * @hw: pointer to the hw struct
2720 * @cmd_details: pointer to command details structure or NULL
2722 * EMP will return when the shared RPB settings have been
2723 * recomputed and modified. The retval field in the descriptor
2724 * will be set to 0 when RPB is modified.
2726 i40e_status
i40e_aq_dcb_updated(struct i40e_hw
*hw
,
2727 struct i40e_asq_cmd_details
*cmd_details
)
2729 struct i40e_aq_desc desc
;
2732 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_dcb_updated
);
2734 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2740 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2741 * @hw: pointer to the hw struct
2742 * @seid: seid for the physical port/switching component/vsi
2743 * @buff: Indirect buffer to hold data parameters and response
2744 * @buff_size: Indirect buffer size
2745 * @opcode: Tx scheduler AQ command opcode
2746 * @cmd_details: pointer to command details structure or NULL
2748 * Generic command handler for Tx scheduler AQ commands
2750 static i40e_status
i40e_aq_tx_sched_cmd(struct i40e_hw
*hw
, u16 seid
,
2751 void *buff
, u16 buff_size
,
2752 enum i40e_admin_queue_opc opcode
,
2753 struct i40e_asq_cmd_details
*cmd_details
)
2755 struct i40e_aq_desc desc
;
2756 struct i40e_aqc_tx_sched_ind
*cmd
=
2757 (struct i40e_aqc_tx_sched_ind
*)&desc
.params
.raw
;
2759 bool cmd_param_flag
= false;
2762 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit
:
2763 case i40e_aqc_opc_configure_vsi_tc_bw
:
2764 case i40e_aqc_opc_enable_switching_comp_ets
:
2765 case i40e_aqc_opc_modify_switching_comp_ets
:
2766 case i40e_aqc_opc_disable_switching_comp_ets
:
2767 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit
:
2768 case i40e_aqc_opc_configure_switching_comp_bw_config
:
2769 cmd_param_flag
= true;
2771 case i40e_aqc_opc_query_vsi_bw_config
:
2772 case i40e_aqc_opc_query_vsi_ets_sla_config
:
2773 case i40e_aqc_opc_query_switching_comp_ets_config
:
2774 case i40e_aqc_opc_query_port_ets_config
:
2775 case i40e_aqc_opc_query_switching_comp_bw_config
:
2776 cmd_param_flag
= false;
2779 return I40E_ERR_PARAM
;
2782 i40e_fill_default_direct_cmd_desc(&desc
, opcode
);
2784 /* Indirect command */
2785 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2787 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_RD
);
2788 if (buff_size
> I40E_AQ_LARGE_BUF
)
2789 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2791 desc
.datalen
= cpu_to_le16(buff_size
);
2793 cmd
->vsi_seid
= cpu_to_le16(seid
);
2795 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
2801 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
2802 * @hw: pointer to the hw struct
2804 * @credit: BW limit credits (0 = disabled)
2805 * @max_credit: Max BW limit credits
2806 * @cmd_details: pointer to command details structure or NULL
2808 i40e_status
i40e_aq_config_vsi_bw_limit(struct i40e_hw
*hw
,
2809 u16 seid
, u16 credit
, u8 max_credit
,
2810 struct i40e_asq_cmd_details
*cmd_details
)
2812 struct i40e_aq_desc desc
;
2813 struct i40e_aqc_configure_vsi_bw_limit
*cmd
=
2814 (struct i40e_aqc_configure_vsi_bw_limit
*)&desc
.params
.raw
;
2817 i40e_fill_default_direct_cmd_desc(&desc
,
2818 i40e_aqc_opc_configure_vsi_bw_limit
);
2820 cmd
->vsi_seid
= cpu_to_le16(seid
);
2821 cmd
->credit
= cpu_to_le16(credit
);
2822 cmd
->max_credit
= max_credit
;
2824 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2830 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
2831 * @hw: pointer to the hw struct
2833 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
2834 * @cmd_details: pointer to command details structure or NULL
2836 i40e_status
i40e_aq_config_vsi_tc_bw(struct i40e_hw
*hw
,
2838 struct i40e_aqc_configure_vsi_tc_bw_data
*bw_data
,
2839 struct i40e_asq_cmd_details
*cmd_details
)
2841 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2842 i40e_aqc_opc_configure_vsi_tc_bw
,
2847 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
2848 * @hw: pointer to the hw struct
2849 * @seid: seid of the switching component connected to Physical Port
2850 * @ets_data: Buffer holding ETS parameters
2851 * @cmd_details: pointer to command details structure or NULL
2853 i40e_status
i40e_aq_config_switch_comp_ets(struct i40e_hw
*hw
,
2855 struct i40e_aqc_configure_switching_comp_ets_data
*ets_data
,
2856 enum i40e_admin_queue_opc opcode
,
2857 struct i40e_asq_cmd_details
*cmd_details
)
2859 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)ets_data
,
2860 sizeof(*ets_data
), opcode
, cmd_details
);
2864 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
2865 * @hw: pointer to the hw struct
2866 * @seid: seid of the switching component
2867 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
2868 * @cmd_details: pointer to command details structure or NULL
2870 i40e_status
i40e_aq_config_switch_comp_bw_config(struct i40e_hw
*hw
,
2872 struct i40e_aqc_configure_switching_comp_bw_config_data
*bw_data
,
2873 struct i40e_asq_cmd_details
*cmd_details
)
2875 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2876 i40e_aqc_opc_configure_switching_comp_bw_config
,
2881 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
2882 * @hw: pointer to the hw struct
2883 * @seid: seid of the VSI
2884 * @bw_data: Buffer to hold VSI BW configuration
2885 * @cmd_details: pointer to command details structure or NULL
2887 i40e_status
i40e_aq_query_vsi_bw_config(struct i40e_hw
*hw
,
2889 struct i40e_aqc_query_vsi_bw_config_resp
*bw_data
,
2890 struct i40e_asq_cmd_details
*cmd_details
)
2892 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2893 i40e_aqc_opc_query_vsi_bw_config
,
2898 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
2899 * @hw: pointer to the hw struct
2900 * @seid: seid of the VSI
2901 * @bw_data: Buffer to hold VSI BW configuration per TC
2902 * @cmd_details: pointer to command details structure or NULL
2904 i40e_status
i40e_aq_query_vsi_ets_sla_config(struct i40e_hw
*hw
,
2906 struct i40e_aqc_query_vsi_ets_sla_config_resp
*bw_data
,
2907 struct i40e_asq_cmd_details
*cmd_details
)
2909 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2910 i40e_aqc_opc_query_vsi_ets_sla_config
,
2915 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
2916 * @hw: pointer to the hw struct
2917 * @seid: seid of the switching component
2918 * @bw_data: Buffer to hold switching component's per TC BW config
2919 * @cmd_details: pointer to command details structure or NULL
2921 i40e_status
i40e_aq_query_switch_comp_ets_config(struct i40e_hw
*hw
,
2923 struct i40e_aqc_query_switching_comp_ets_config_resp
*bw_data
,
2924 struct i40e_asq_cmd_details
*cmd_details
)
2926 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2927 i40e_aqc_opc_query_switching_comp_ets_config
,
2932 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
2933 * @hw: pointer to the hw struct
2934 * @seid: seid of the VSI or switching component connected to Physical Port
2935 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
2936 * @cmd_details: pointer to command details structure or NULL
2938 i40e_status
i40e_aq_query_port_ets_config(struct i40e_hw
*hw
,
2940 struct i40e_aqc_query_port_ets_config_resp
*bw_data
,
2941 struct i40e_asq_cmd_details
*cmd_details
)
2943 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2944 i40e_aqc_opc_query_port_ets_config
,
2949 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
2950 * @hw: pointer to the hw struct
2951 * @seid: seid of the switching component
2952 * @bw_data: Buffer to hold switching component's BW configuration
2953 * @cmd_details: pointer to command details structure or NULL
2955 i40e_status
i40e_aq_query_switch_comp_bw_config(struct i40e_hw
*hw
,
2957 struct i40e_aqc_query_switching_comp_bw_config_resp
*bw_data
,
2958 struct i40e_asq_cmd_details
*cmd_details
)
2960 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2961 i40e_aqc_opc_query_switching_comp_bw_config
,
2966 * i40e_validate_filter_settings
2967 * @hw: pointer to the hardware structure
2968 * @settings: Filter control settings
2970 * Check and validate the filter control settings passed.
2971 * The function checks for the valid filter/context sizes being
2972 * passed for FCoE and PE.
2974 * Returns 0 if the values passed are valid and within
2975 * range else returns an error.
2977 static i40e_status
i40e_validate_filter_settings(struct i40e_hw
*hw
,
2978 struct i40e_filter_control_settings
*settings
)
2980 u32 fcoe_cntx_size
, fcoe_filt_size
;
2981 u32 pe_cntx_size
, pe_filt_size
;
2985 /* Validate FCoE settings passed */
2986 switch (settings
->fcoe_filt_num
) {
2987 case I40E_HASH_FILTER_SIZE_1K
:
2988 case I40E_HASH_FILTER_SIZE_2K
:
2989 case I40E_HASH_FILTER_SIZE_4K
:
2990 case I40E_HASH_FILTER_SIZE_8K
:
2991 case I40E_HASH_FILTER_SIZE_16K
:
2992 case I40E_HASH_FILTER_SIZE_32K
:
2993 fcoe_filt_size
= I40E_HASH_FILTER_BASE_SIZE
;
2994 fcoe_filt_size
<<= (u32
)settings
->fcoe_filt_num
;
2997 return I40E_ERR_PARAM
;
3000 switch (settings
->fcoe_cntx_num
) {
3001 case I40E_DMA_CNTX_SIZE_512
:
3002 case I40E_DMA_CNTX_SIZE_1K
:
3003 case I40E_DMA_CNTX_SIZE_2K
:
3004 case I40E_DMA_CNTX_SIZE_4K
:
3005 fcoe_cntx_size
= I40E_DMA_CNTX_BASE_SIZE
;
3006 fcoe_cntx_size
<<= (u32
)settings
->fcoe_cntx_num
;
3009 return I40E_ERR_PARAM
;
3012 /* Validate PE settings passed */
3013 switch (settings
->pe_filt_num
) {
3014 case I40E_HASH_FILTER_SIZE_1K
:
3015 case I40E_HASH_FILTER_SIZE_2K
:
3016 case I40E_HASH_FILTER_SIZE_4K
:
3017 case I40E_HASH_FILTER_SIZE_8K
:
3018 case I40E_HASH_FILTER_SIZE_16K
:
3019 case I40E_HASH_FILTER_SIZE_32K
:
3020 case I40E_HASH_FILTER_SIZE_64K
:
3021 case I40E_HASH_FILTER_SIZE_128K
:
3022 case I40E_HASH_FILTER_SIZE_256K
:
3023 case I40E_HASH_FILTER_SIZE_512K
:
3024 case I40E_HASH_FILTER_SIZE_1M
:
3025 pe_filt_size
= I40E_HASH_FILTER_BASE_SIZE
;
3026 pe_filt_size
<<= (u32
)settings
->pe_filt_num
;
3029 return I40E_ERR_PARAM
;
3032 switch (settings
->pe_cntx_num
) {
3033 case I40E_DMA_CNTX_SIZE_512
:
3034 case I40E_DMA_CNTX_SIZE_1K
:
3035 case I40E_DMA_CNTX_SIZE_2K
:
3036 case I40E_DMA_CNTX_SIZE_4K
:
3037 case I40E_DMA_CNTX_SIZE_8K
:
3038 case I40E_DMA_CNTX_SIZE_16K
:
3039 case I40E_DMA_CNTX_SIZE_32K
:
3040 case I40E_DMA_CNTX_SIZE_64K
:
3041 case I40E_DMA_CNTX_SIZE_128K
:
3042 case I40E_DMA_CNTX_SIZE_256K
:
3043 pe_cntx_size
= I40E_DMA_CNTX_BASE_SIZE
;
3044 pe_cntx_size
<<= (u32
)settings
->pe_cntx_num
;
3047 return I40E_ERR_PARAM
;
3050 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3051 val
= rd32(hw
, I40E_GLHMC_FCOEFMAX
);
3052 fcoe_fmax
= (val
& I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK
)
3053 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT
;
3054 if (fcoe_filt_size
+ fcoe_cntx_size
> fcoe_fmax
)
3055 return I40E_ERR_INVALID_SIZE
;
3061 * i40e_set_filter_control
3062 * @hw: pointer to the hardware structure
3063 * @settings: Filter control settings
3065 * Set the Queue Filters for PE/FCoE and enable filters required
3066 * for a single PF. It is expected that these settings are programmed
3067 * at the driver initialization time.
3069 i40e_status
i40e_set_filter_control(struct i40e_hw
*hw
,
3070 struct i40e_filter_control_settings
*settings
)
3072 i40e_status ret
= 0;
3073 u32 hash_lut_size
= 0;
3077 return I40E_ERR_PARAM
;
3079 /* Validate the input settings */
3080 ret
= i40e_validate_filter_settings(hw
, settings
);
3084 /* Read the PF Queue Filter control register */
3085 val
= rd32(hw
, I40E_PFQF_CTL_0
);
3087 /* Program required PE hash buckets for the PF */
3088 val
&= ~I40E_PFQF_CTL_0_PEHSIZE_MASK
;
3089 val
|= ((u32
)settings
->pe_filt_num
<< I40E_PFQF_CTL_0_PEHSIZE_SHIFT
) &
3090 I40E_PFQF_CTL_0_PEHSIZE_MASK
;
3091 /* Program required PE contexts for the PF */
3092 val
&= ~I40E_PFQF_CTL_0_PEDSIZE_MASK
;
3093 val
|= ((u32
)settings
->pe_cntx_num
<< I40E_PFQF_CTL_0_PEDSIZE_SHIFT
) &
3094 I40E_PFQF_CTL_0_PEDSIZE_MASK
;
3096 /* Program required FCoE hash buckets for the PF */
3097 val
&= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK
;
3098 val
|= ((u32
)settings
->fcoe_filt_num
<<
3099 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT
) &
3100 I40E_PFQF_CTL_0_PFFCHSIZE_MASK
;
3101 /* Program required FCoE DDP contexts for the PF */
3102 val
&= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK
;
3103 val
|= ((u32
)settings
->fcoe_cntx_num
<<
3104 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT
) &
3105 I40E_PFQF_CTL_0_PFFCDSIZE_MASK
;
3107 /* Program Hash LUT size for the PF */
3108 val
&= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK
;
3109 if (settings
->hash_lut_size
== I40E_HASH_LUT_SIZE_512
)
3111 val
|= (hash_lut_size
<< I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT
) &
3112 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK
;
3114 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3115 if (settings
->enable_fdir
)
3116 val
|= I40E_PFQF_CTL_0_FD_ENA_MASK
;
3117 if (settings
->enable_ethtype
)
3118 val
|= I40E_PFQF_CTL_0_ETYPE_ENA_MASK
;
3119 if (settings
->enable_macvlan
)
3120 val
|= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK
;
3122 wr32(hw
, I40E_PFQF_CTL_0
, val
);
3128 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3129 * @hw: pointer to the hw struct
3130 * @mac_addr: MAC address to use in the filter
3131 * @ethtype: Ethertype to use in the filter
3132 * @flags: Flags that needs to be applied to the filter
3133 * @vsi_seid: seid of the control VSI
3134 * @queue: VSI queue number to send the packet to
3135 * @is_add: Add control packet filter if True else remove
3136 * @stats: Structure to hold information on control filter counts
3137 * @cmd_details: pointer to command details structure or NULL
3139 * This command will Add or Remove control packet filter for a control VSI.
3140 * In return it will update the total number of perfect filter count in
3143 i40e_status
i40e_aq_add_rem_control_packet_filter(struct i40e_hw
*hw
,
3144 u8
*mac_addr
, u16 ethtype
, u16 flags
,
3145 u16 vsi_seid
, u16 queue
, bool is_add
,
3146 struct i40e_control_filter_stats
*stats
,
3147 struct i40e_asq_cmd_details
*cmd_details
)
3149 struct i40e_aq_desc desc
;
3150 struct i40e_aqc_add_remove_control_packet_filter
*cmd
=
3151 (struct i40e_aqc_add_remove_control_packet_filter
*)
3153 struct i40e_aqc_add_remove_control_packet_filter_completion
*resp
=
3154 (struct i40e_aqc_add_remove_control_packet_filter_completion
*)
3159 return I40E_ERR_PARAM
;
3162 i40e_fill_default_direct_cmd_desc(&desc
,
3163 i40e_aqc_opc_add_control_packet_filter
);
3164 cmd
->queue
= cpu_to_le16(queue
);
3166 i40e_fill_default_direct_cmd_desc(&desc
,
3167 i40e_aqc_opc_remove_control_packet_filter
);
3171 memcpy(cmd
->mac
, mac_addr
, ETH_ALEN
);
3173 cmd
->etype
= cpu_to_le16(ethtype
);
3174 cmd
->flags
= cpu_to_le16(flags
);
3175 cmd
->seid
= cpu_to_le16(vsi_seid
);
3177 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3179 if (!status
&& stats
) {
3180 stats
->mac_etype_used
= le16_to_cpu(resp
->mac_etype_used
);
3181 stats
->etype_used
= le16_to_cpu(resp
->etype_used
);
3182 stats
->mac_etype_free
= le16_to_cpu(resp
->mac_etype_free
);
3183 stats
->etype_free
= le16_to_cpu(resp
->etype_free
);
3190 * i40e_set_pci_config_data - store PCI bus info
3191 * @hw: pointer to hardware structure
3192 * @link_status: the link status word from PCI config space
3194 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3196 void i40e_set_pci_config_data(struct i40e_hw
*hw
, u16 link_status
)
3198 hw
->bus
.type
= i40e_bus_type_pci_express
;
3200 switch (link_status
& PCI_EXP_LNKSTA_NLW
) {
3201 case PCI_EXP_LNKSTA_NLW_X1
:
3202 hw
->bus
.width
= i40e_bus_width_pcie_x1
;
3204 case PCI_EXP_LNKSTA_NLW_X2
:
3205 hw
->bus
.width
= i40e_bus_width_pcie_x2
;
3207 case PCI_EXP_LNKSTA_NLW_X4
:
3208 hw
->bus
.width
= i40e_bus_width_pcie_x4
;
3210 case PCI_EXP_LNKSTA_NLW_X8
:
3211 hw
->bus
.width
= i40e_bus_width_pcie_x8
;
3214 hw
->bus
.width
= i40e_bus_width_unknown
;
3218 switch (link_status
& PCI_EXP_LNKSTA_CLS
) {
3219 case PCI_EXP_LNKSTA_CLS_2_5GB
:
3220 hw
->bus
.speed
= i40e_bus_speed_2500
;
3222 case PCI_EXP_LNKSTA_CLS_5_0GB
:
3223 hw
->bus
.speed
= i40e_bus_speed_5000
;
3225 case PCI_EXP_LNKSTA_CLS_8_0GB
:
3226 hw
->bus
.speed
= i40e_bus_speed_8000
;
3229 hw
->bus
.speed
= i40e_bus_speed_unknown
;