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0bfc82b9e921e58d6393c382d59c3634bab6e804
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
31
32 /**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40 {
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
45 case I40E_DEV_ID_SFP_XL710:
46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_A:
48 case I40E_DEV_ID_KX_B:
49 case I40E_DEV_ID_KX_C:
50 case I40E_DEV_ID_QSFP_A:
51 case I40E_DEV_ID_QSFP_B:
52 case I40E_DEV_ID_QSFP_C:
53 case I40E_DEV_ID_10G_BASE_T:
54 hw->mac.type = I40E_MAC_XL710;
55 break;
56 case I40E_DEV_ID_VF:
57 case I40E_DEV_ID_VF_HV:
58 hw->mac.type = I40E_MAC_VF;
59 break;
60 default:
61 hw->mac.type = I40E_MAC_GENERIC;
62 break;
63 }
64 } else {
65 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
66 }
67
68 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
69 hw->mac.type, status);
70 return status;
71 }
72
73 /**
74 * i40e_debug_aq
75 * @hw: debug mask related to admin queue
76 * @mask: debug mask
77 * @desc: pointer to admin queue descriptor
78 * @buffer: pointer to command buffer
79 * @buf_len: max length of buffer
80 *
81 * Dumps debug log about adminq command with descriptor contents.
82 **/
83 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
84 void *buffer, u16 buf_len)
85 {
86 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
87 u16 len = le16_to_cpu(aq_desc->datalen);
88 u8 *aq_buffer = (u8 *)buffer;
89 u32 data[4];
90 u32 i = 0;
91
92 if ((!(mask & hw->debug_mask)) || (desc == NULL))
93 return;
94
95 i40e_debug(hw, mask,
96 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
97 le16_to_cpu(aq_desc->opcode),
98 le16_to_cpu(aq_desc->flags),
99 le16_to_cpu(aq_desc->datalen),
100 le16_to_cpu(aq_desc->retval));
101 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
102 le32_to_cpu(aq_desc->cookie_high),
103 le32_to_cpu(aq_desc->cookie_low));
104 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
105 le32_to_cpu(aq_desc->params.internal.param0),
106 le32_to_cpu(aq_desc->params.internal.param1));
107 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
108 le32_to_cpu(aq_desc->params.external.addr_high),
109 le32_to_cpu(aq_desc->params.external.addr_low));
110
111 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
112 memset(data, 0, sizeof(data));
113 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
114 if (buf_len < len)
115 len = buf_len;
116 for (i = 0; i < len; i++) {
117 data[((i % 16) / 4)] |=
118 ((u32)aq_buffer[i]) << (8 * (i % 4));
119 if ((i % 16) == 15) {
120 i40e_debug(hw, mask,
121 "\t0x%04X %08X %08X %08X %08X\n",
122 i - 15, le32_to_cpu(data[0]),
123 le32_to_cpu(data[1]),
124 le32_to_cpu(data[2]),
125 le32_to_cpu(data[3]));
126 memset(data, 0, sizeof(data));
127 }
128 }
129 if ((i % 16) != 0)
130 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
131 i - (i % 16), le32_to_cpu(data[0]),
132 le32_to_cpu(data[1]),
133 le32_to_cpu(data[2]),
134 le32_to_cpu(data[3]));
135 }
136 }
137
138 /**
139 * i40e_check_asq_alive
140 * @hw: pointer to the hw struct
141 *
142 * Returns true if Queue is enabled else false.
143 **/
144 bool i40e_check_asq_alive(struct i40e_hw *hw)
145 {
146 if (hw->aq.asq.len)
147 return !!(rd32(hw, hw->aq.asq.len) &
148 I40E_PF_ATQLEN_ATQENABLE_MASK);
149 else
150 return false;
151 }
152
153 /**
154 * i40e_aq_queue_shutdown
155 * @hw: pointer to the hw struct
156 * @unloading: is the driver unloading itself
157 *
158 * Tell the Firmware that we're shutting down the AdminQ and whether
159 * or not the driver is unloading as well.
160 **/
161 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
162 bool unloading)
163 {
164 struct i40e_aq_desc desc;
165 struct i40e_aqc_queue_shutdown *cmd =
166 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
167 i40e_status status;
168
169 i40e_fill_default_direct_cmd_desc(&desc,
170 i40e_aqc_opc_queue_shutdown);
171
172 if (unloading)
173 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
174 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
175
176 return status;
177 }
178
179 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
180 * hardware to a bit-field that can be used by SW to more easily determine the
181 * packet type.
182 *
183 * Macros are used to shorten the table lines and make this table human
184 * readable.
185 *
186 * We store the PTYPE in the top byte of the bit field - this is just so that
187 * we can check that the table doesn't have a row missing, as the index into
188 * the table should be the PTYPE.
189 *
190 * Typical work flow:
191 *
192 * IF NOT i40e_ptype_lookup[ptype].known
193 * THEN
194 * Packet is unknown
195 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
196 * Use the rest of the fields to look at the tunnels, inner protocols, etc
197 * ELSE
198 * Use the enum i40e_rx_l2_ptype to decode the packet type
199 * ENDIF
200 */
201
202 /* macro to make the table lines short */
203 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
204 { PTYPE, \
205 1, \
206 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
207 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
208 I40E_RX_PTYPE_##OUTER_FRAG, \
209 I40E_RX_PTYPE_TUNNEL_##T, \
210 I40E_RX_PTYPE_TUNNEL_END_##TE, \
211 I40E_RX_PTYPE_##TEF, \
212 I40E_RX_PTYPE_INNER_PROT_##I, \
213 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
214
215 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
216 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
217
218 /* shorter macros makes the table fit but are terse */
219 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
220 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
221 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
222
223 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
224 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
225 /* L2 Packet types */
226 I40E_PTT_UNUSED_ENTRY(0),
227 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
228 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
229 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
230 I40E_PTT_UNUSED_ENTRY(4),
231 I40E_PTT_UNUSED_ENTRY(5),
232 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
233 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
234 I40E_PTT_UNUSED_ENTRY(8),
235 I40E_PTT_UNUSED_ENTRY(9),
236 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
237 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
238 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
239 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
240 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
241 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
242 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
243 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
244 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
245 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
246 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
247 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
248
249 /* Non Tunneled IPv4 */
250 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
251 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
252 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
253 I40E_PTT_UNUSED_ENTRY(25),
254 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
255 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
256 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
257
258 /* IPv4 --> IPv4 */
259 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
260 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
261 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
262 I40E_PTT_UNUSED_ENTRY(32),
263 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
264 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
265 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
266
267 /* IPv4 --> IPv6 */
268 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
269 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
270 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
271 I40E_PTT_UNUSED_ENTRY(39),
272 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
273 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
274 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
275
276 /* IPv4 --> GRE/NAT */
277 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
278
279 /* IPv4 --> GRE/NAT --> IPv4 */
280 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
281 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
282 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
283 I40E_PTT_UNUSED_ENTRY(47),
284 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
285 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
286 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
287
288 /* IPv4 --> GRE/NAT --> IPv6 */
289 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
290 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
291 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
292 I40E_PTT_UNUSED_ENTRY(54),
293 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
294 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
295 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
296
297 /* IPv4 --> GRE/NAT --> MAC */
298 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
299
300 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
301 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
302 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
303 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
304 I40E_PTT_UNUSED_ENTRY(62),
305 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
306 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
307 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
308
309 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
310 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
311 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
312 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
313 I40E_PTT_UNUSED_ENTRY(69),
314 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
315 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
316 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
317
318 /* IPv4 --> GRE/NAT --> MAC/VLAN */
319 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
320
321 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
322 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
323 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
324 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
325 I40E_PTT_UNUSED_ENTRY(77),
326 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
327 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
328 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
329
330 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
331 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
332 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
333 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
334 I40E_PTT_UNUSED_ENTRY(84),
335 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
336 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
337 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
338
339 /* Non Tunneled IPv6 */
340 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
341 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
342 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
343 I40E_PTT_UNUSED_ENTRY(91),
344 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
345 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
346 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
347
348 /* IPv6 --> IPv4 */
349 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
350 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
351 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
352 I40E_PTT_UNUSED_ENTRY(98),
353 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
354 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
355 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
356
357 /* IPv6 --> IPv6 */
358 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
359 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
360 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
361 I40E_PTT_UNUSED_ENTRY(105),
362 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
363 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
364 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
365
366 /* IPv6 --> GRE/NAT */
367 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
368
369 /* IPv6 --> GRE/NAT -> IPv4 */
370 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
371 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
372 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
373 I40E_PTT_UNUSED_ENTRY(113),
374 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
375 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
376 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
377
378 /* IPv6 --> GRE/NAT -> IPv6 */
379 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
380 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
381 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
382 I40E_PTT_UNUSED_ENTRY(120),
383 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
384 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
385 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
386
387 /* IPv6 --> GRE/NAT -> MAC */
388 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
389
390 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
391 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
392 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
393 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
394 I40E_PTT_UNUSED_ENTRY(128),
395 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
396 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
397 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
398
399 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
400 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
401 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
402 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
403 I40E_PTT_UNUSED_ENTRY(135),
404 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
405 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
406 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
407
408 /* IPv6 --> GRE/NAT -> MAC/VLAN */
409 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
410
411 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
412 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
413 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
414 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
415 I40E_PTT_UNUSED_ENTRY(143),
416 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
417 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
418 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
419
420 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
421 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
422 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
423 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
424 I40E_PTT_UNUSED_ENTRY(150),
425 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
426 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
427 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
428
429 /* unused entries */
430 I40E_PTT_UNUSED_ENTRY(154),
431 I40E_PTT_UNUSED_ENTRY(155),
432 I40E_PTT_UNUSED_ENTRY(156),
433 I40E_PTT_UNUSED_ENTRY(157),
434 I40E_PTT_UNUSED_ENTRY(158),
435 I40E_PTT_UNUSED_ENTRY(159),
436
437 I40E_PTT_UNUSED_ENTRY(160),
438 I40E_PTT_UNUSED_ENTRY(161),
439 I40E_PTT_UNUSED_ENTRY(162),
440 I40E_PTT_UNUSED_ENTRY(163),
441 I40E_PTT_UNUSED_ENTRY(164),
442 I40E_PTT_UNUSED_ENTRY(165),
443 I40E_PTT_UNUSED_ENTRY(166),
444 I40E_PTT_UNUSED_ENTRY(167),
445 I40E_PTT_UNUSED_ENTRY(168),
446 I40E_PTT_UNUSED_ENTRY(169),
447
448 I40E_PTT_UNUSED_ENTRY(170),
449 I40E_PTT_UNUSED_ENTRY(171),
450 I40E_PTT_UNUSED_ENTRY(172),
451 I40E_PTT_UNUSED_ENTRY(173),
452 I40E_PTT_UNUSED_ENTRY(174),
453 I40E_PTT_UNUSED_ENTRY(175),
454 I40E_PTT_UNUSED_ENTRY(176),
455 I40E_PTT_UNUSED_ENTRY(177),
456 I40E_PTT_UNUSED_ENTRY(178),
457 I40E_PTT_UNUSED_ENTRY(179),
458
459 I40E_PTT_UNUSED_ENTRY(180),
460 I40E_PTT_UNUSED_ENTRY(181),
461 I40E_PTT_UNUSED_ENTRY(182),
462 I40E_PTT_UNUSED_ENTRY(183),
463 I40E_PTT_UNUSED_ENTRY(184),
464 I40E_PTT_UNUSED_ENTRY(185),
465 I40E_PTT_UNUSED_ENTRY(186),
466 I40E_PTT_UNUSED_ENTRY(187),
467 I40E_PTT_UNUSED_ENTRY(188),
468 I40E_PTT_UNUSED_ENTRY(189),
469
470 I40E_PTT_UNUSED_ENTRY(190),
471 I40E_PTT_UNUSED_ENTRY(191),
472 I40E_PTT_UNUSED_ENTRY(192),
473 I40E_PTT_UNUSED_ENTRY(193),
474 I40E_PTT_UNUSED_ENTRY(194),
475 I40E_PTT_UNUSED_ENTRY(195),
476 I40E_PTT_UNUSED_ENTRY(196),
477 I40E_PTT_UNUSED_ENTRY(197),
478 I40E_PTT_UNUSED_ENTRY(198),
479 I40E_PTT_UNUSED_ENTRY(199),
480
481 I40E_PTT_UNUSED_ENTRY(200),
482 I40E_PTT_UNUSED_ENTRY(201),
483 I40E_PTT_UNUSED_ENTRY(202),
484 I40E_PTT_UNUSED_ENTRY(203),
485 I40E_PTT_UNUSED_ENTRY(204),
486 I40E_PTT_UNUSED_ENTRY(205),
487 I40E_PTT_UNUSED_ENTRY(206),
488 I40E_PTT_UNUSED_ENTRY(207),
489 I40E_PTT_UNUSED_ENTRY(208),
490 I40E_PTT_UNUSED_ENTRY(209),
491
492 I40E_PTT_UNUSED_ENTRY(210),
493 I40E_PTT_UNUSED_ENTRY(211),
494 I40E_PTT_UNUSED_ENTRY(212),
495 I40E_PTT_UNUSED_ENTRY(213),
496 I40E_PTT_UNUSED_ENTRY(214),
497 I40E_PTT_UNUSED_ENTRY(215),
498 I40E_PTT_UNUSED_ENTRY(216),
499 I40E_PTT_UNUSED_ENTRY(217),
500 I40E_PTT_UNUSED_ENTRY(218),
501 I40E_PTT_UNUSED_ENTRY(219),
502
503 I40E_PTT_UNUSED_ENTRY(220),
504 I40E_PTT_UNUSED_ENTRY(221),
505 I40E_PTT_UNUSED_ENTRY(222),
506 I40E_PTT_UNUSED_ENTRY(223),
507 I40E_PTT_UNUSED_ENTRY(224),
508 I40E_PTT_UNUSED_ENTRY(225),
509 I40E_PTT_UNUSED_ENTRY(226),
510 I40E_PTT_UNUSED_ENTRY(227),
511 I40E_PTT_UNUSED_ENTRY(228),
512 I40E_PTT_UNUSED_ENTRY(229),
513
514 I40E_PTT_UNUSED_ENTRY(230),
515 I40E_PTT_UNUSED_ENTRY(231),
516 I40E_PTT_UNUSED_ENTRY(232),
517 I40E_PTT_UNUSED_ENTRY(233),
518 I40E_PTT_UNUSED_ENTRY(234),
519 I40E_PTT_UNUSED_ENTRY(235),
520 I40E_PTT_UNUSED_ENTRY(236),
521 I40E_PTT_UNUSED_ENTRY(237),
522 I40E_PTT_UNUSED_ENTRY(238),
523 I40E_PTT_UNUSED_ENTRY(239),
524
525 I40E_PTT_UNUSED_ENTRY(240),
526 I40E_PTT_UNUSED_ENTRY(241),
527 I40E_PTT_UNUSED_ENTRY(242),
528 I40E_PTT_UNUSED_ENTRY(243),
529 I40E_PTT_UNUSED_ENTRY(244),
530 I40E_PTT_UNUSED_ENTRY(245),
531 I40E_PTT_UNUSED_ENTRY(246),
532 I40E_PTT_UNUSED_ENTRY(247),
533 I40E_PTT_UNUSED_ENTRY(248),
534 I40E_PTT_UNUSED_ENTRY(249),
535
536 I40E_PTT_UNUSED_ENTRY(250),
537 I40E_PTT_UNUSED_ENTRY(251),
538 I40E_PTT_UNUSED_ENTRY(252),
539 I40E_PTT_UNUSED_ENTRY(253),
540 I40E_PTT_UNUSED_ENTRY(254),
541 I40E_PTT_UNUSED_ENTRY(255)
542 };
543
544
545 /**
546 * i40e_init_shared_code - Initialize the shared code
547 * @hw: pointer to hardware structure
548 *
549 * This assigns the MAC type and PHY code and inits the NVM.
550 * Does not touch the hardware. This function must be called prior to any
551 * other function in the shared code. The i40e_hw structure should be
552 * memset to 0 prior to calling this function. The following fields in
553 * hw structure should be filled in prior to calling this function:
554 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
555 * subsystem_vendor_id, and revision_id
556 **/
557 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
558 {
559 i40e_status status = 0;
560 u32 port, ari, func_rid;
561
562 i40e_set_mac_type(hw);
563
564 switch (hw->mac.type) {
565 case I40E_MAC_XL710:
566 break;
567 default:
568 return I40E_ERR_DEVICE_NOT_SUPPORTED;
569 }
570
571 hw->phy.get_link_info = true;
572
573 /* Determine port number and PF number*/
574 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
575 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
576 hw->port = (u8)port;
577 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
578 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
579 func_rid = rd32(hw, I40E_PF_FUNC_RID);
580 if (ari)
581 hw->pf_id = (u8)(func_rid & 0xff);
582 else
583 hw->pf_id = (u8)(func_rid & 0x7);
584
585 status = i40e_init_nvm(hw);
586 return status;
587 }
588
589 /**
590 * i40e_aq_mac_address_read - Retrieve the MAC addresses
591 * @hw: pointer to the hw struct
592 * @flags: a return indicator of what addresses were added to the addr store
593 * @addrs: the requestor's mac addr store
594 * @cmd_details: pointer to command details structure or NULL
595 **/
596 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
597 u16 *flags,
598 struct i40e_aqc_mac_address_read_data *addrs,
599 struct i40e_asq_cmd_details *cmd_details)
600 {
601 struct i40e_aq_desc desc;
602 struct i40e_aqc_mac_address_read *cmd_data =
603 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
604 i40e_status status;
605
606 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
607 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
608
609 status = i40e_asq_send_command(hw, &desc, addrs,
610 sizeof(*addrs), cmd_details);
611 *flags = le16_to_cpu(cmd_data->command_flags);
612
613 return status;
614 }
615
616 /**
617 * i40e_aq_mac_address_write - Change the MAC addresses
618 * @hw: pointer to the hw struct
619 * @flags: indicates which MAC to be written
620 * @mac_addr: address to write
621 * @cmd_details: pointer to command details structure or NULL
622 **/
623 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
624 u16 flags, u8 *mac_addr,
625 struct i40e_asq_cmd_details *cmd_details)
626 {
627 struct i40e_aq_desc desc;
628 struct i40e_aqc_mac_address_write *cmd_data =
629 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
630 i40e_status status;
631
632 i40e_fill_default_direct_cmd_desc(&desc,
633 i40e_aqc_opc_mac_address_write);
634 cmd_data->command_flags = cpu_to_le16(flags);
635 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
636 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
637 ((u32)mac_addr[3] << 16) |
638 ((u32)mac_addr[4] << 8) |
639 mac_addr[5]);
640
641 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
642
643 return status;
644 }
645
646 /**
647 * i40e_get_mac_addr - get MAC address
648 * @hw: pointer to the HW structure
649 * @mac_addr: pointer to MAC address
650 *
651 * Reads the adapter's MAC address from register
652 **/
653 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
654 {
655 struct i40e_aqc_mac_address_read_data addrs;
656 i40e_status status;
657 u16 flags = 0;
658
659 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
660
661 if (flags & I40E_AQC_LAN_ADDR_VALID)
662 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
663
664 return status;
665 }
666
667 /**
668 * i40e_get_port_mac_addr - get Port MAC address
669 * @hw: pointer to the HW structure
670 * @mac_addr: pointer to Port MAC address
671 *
672 * Reads the adapter's Port MAC address
673 **/
674 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
675 {
676 struct i40e_aqc_mac_address_read_data addrs;
677 i40e_status status;
678 u16 flags = 0;
679
680 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
681 if (status)
682 return status;
683
684 if (flags & I40E_AQC_PORT_ADDR_VALID)
685 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
686 else
687 status = I40E_ERR_INVALID_MAC_ADDR;
688
689 return status;
690 }
691
692 /**
693 * i40e_pre_tx_queue_cfg - pre tx queue configure
694 * @hw: pointer to the HW structure
695 * @queue: target pf queue index
696 * @enable: state change request
697 *
698 * Handles hw requirement to indicate intention to enable
699 * or disable target queue.
700 **/
701 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
702 {
703 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
704 u32 reg_block = 0;
705 u32 reg_val;
706
707 if (abs_queue_idx >= 128) {
708 reg_block = abs_queue_idx / 128;
709 abs_queue_idx %= 128;
710 }
711
712 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
713 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
714 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
715
716 if (enable)
717 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
718 else
719 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
720
721 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
722 }
723 #ifdef I40E_FCOE
724
725 /**
726 * i40e_get_san_mac_addr - get SAN MAC address
727 * @hw: pointer to the HW structure
728 * @mac_addr: pointer to SAN MAC address
729 *
730 * Reads the adapter's SAN MAC address from NVM
731 **/
732 i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
733 {
734 struct i40e_aqc_mac_address_read_data addrs;
735 i40e_status status;
736 u16 flags = 0;
737
738 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
739 if (status)
740 return status;
741
742 if (flags & I40E_AQC_SAN_ADDR_VALID)
743 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac));
744 else
745 status = I40E_ERR_INVALID_MAC_ADDR;
746
747 return status;
748 }
749 #endif
750
751 /**
752 * i40e_read_pba_string - Reads part number string from EEPROM
753 * @hw: pointer to hardware structure
754 * @pba_num: stores the part number string from the EEPROM
755 * @pba_num_size: part number string buffer length
756 *
757 * Reads the part number string from the EEPROM.
758 **/
759 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
760 u32 pba_num_size)
761 {
762 i40e_status status = 0;
763 u16 pba_word = 0;
764 u16 pba_size = 0;
765 u16 pba_ptr = 0;
766 u16 i = 0;
767
768 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
769 if (status || (pba_word != 0xFAFA)) {
770 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
771 return status;
772 }
773
774 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
775 if (status) {
776 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
777 return status;
778 }
779
780 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
781 if (status) {
782 hw_dbg(hw, "Failed to read PBA Block size.\n");
783 return status;
784 }
785
786 /* Subtract one to get PBA word count (PBA Size word is included in
787 * total size)
788 */
789 pba_size--;
790 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
791 hw_dbg(hw, "Buffer to small for PBA data.\n");
792 return I40E_ERR_PARAM;
793 }
794
795 for (i = 0; i < pba_size; i++) {
796 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
797 if (status) {
798 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
799 return status;
800 }
801
802 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
803 pba_num[(i * 2) + 1] = pba_word & 0xFF;
804 }
805 pba_num[(pba_size * 2)] = '\0';
806
807 return status;
808 }
809
810 /**
811 * i40e_get_media_type - Gets media type
812 * @hw: pointer to the hardware structure
813 **/
814 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
815 {
816 enum i40e_media_type media;
817
818 switch (hw->phy.link_info.phy_type) {
819 case I40E_PHY_TYPE_10GBASE_SR:
820 case I40E_PHY_TYPE_10GBASE_LR:
821 case I40E_PHY_TYPE_1000BASE_SX:
822 case I40E_PHY_TYPE_1000BASE_LX:
823 case I40E_PHY_TYPE_40GBASE_SR4:
824 case I40E_PHY_TYPE_40GBASE_LR4:
825 media = I40E_MEDIA_TYPE_FIBER;
826 break;
827 case I40E_PHY_TYPE_100BASE_TX:
828 case I40E_PHY_TYPE_1000BASE_T:
829 case I40E_PHY_TYPE_10GBASE_T:
830 media = I40E_MEDIA_TYPE_BASET;
831 break;
832 case I40E_PHY_TYPE_10GBASE_CR1_CU:
833 case I40E_PHY_TYPE_40GBASE_CR4_CU:
834 case I40E_PHY_TYPE_10GBASE_CR1:
835 case I40E_PHY_TYPE_40GBASE_CR4:
836 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
837 media = I40E_MEDIA_TYPE_DA;
838 break;
839 case I40E_PHY_TYPE_1000BASE_KX:
840 case I40E_PHY_TYPE_10GBASE_KX4:
841 case I40E_PHY_TYPE_10GBASE_KR:
842 case I40E_PHY_TYPE_40GBASE_KR4:
843 media = I40E_MEDIA_TYPE_BACKPLANE;
844 break;
845 case I40E_PHY_TYPE_SGMII:
846 case I40E_PHY_TYPE_XAUI:
847 case I40E_PHY_TYPE_XFI:
848 case I40E_PHY_TYPE_XLAUI:
849 case I40E_PHY_TYPE_XLPPI:
850 default:
851 media = I40E_MEDIA_TYPE_UNKNOWN;
852 break;
853 }
854
855 return media;
856 }
857
858 #define I40E_PF_RESET_WAIT_COUNT_A0 200
859 #define I40E_PF_RESET_WAIT_COUNT 110
860 /**
861 * i40e_pf_reset - Reset the PF
862 * @hw: pointer to the hardware structure
863 *
864 * Assuming someone else has triggered a global reset,
865 * assure the global reset is complete and then reset the PF
866 **/
867 i40e_status i40e_pf_reset(struct i40e_hw *hw)
868 {
869 u32 cnt = 0;
870 u32 cnt1 = 0;
871 u32 reg = 0;
872 u32 grst_del;
873
874 /* Poll for Global Reset steady state in case of recent GRST.
875 * The grst delay value is in 100ms units, and we'll wait a
876 * couple counts longer to be sure we don't just miss the end.
877 */
878 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
879 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
880 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
881 for (cnt = 0; cnt < grst_del + 2; cnt++) {
882 reg = rd32(hw, I40E_GLGEN_RSTAT);
883 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
884 break;
885 msleep(100);
886 }
887 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
888 hw_dbg(hw, "Global reset polling failed to complete.\n");
889 return I40E_ERR_RESET_FAILED;
890 }
891
892 /* Now Wait for the FW to be ready */
893 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
894 reg = rd32(hw, I40E_GLNVM_ULD);
895 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
896 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
897 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
898 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
899 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
900 break;
901 }
902 usleep_range(10000, 20000);
903 }
904 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
905 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
906 hw_dbg(hw, "wait for FW Reset complete timedout\n");
907 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
908 return I40E_ERR_RESET_FAILED;
909 }
910
911 /* If there was a Global Reset in progress when we got here,
912 * we don't need to do the PF Reset
913 */
914 if (!cnt) {
915 if (hw->revision_id == 0)
916 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
917 else
918 cnt = I40E_PF_RESET_WAIT_COUNT;
919 reg = rd32(hw, I40E_PFGEN_CTRL);
920 wr32(hw, I40E_PFGEN_CTRL,
921 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
922 for (; cnt; cnt--) {
923 reg = rd32(hw, I40E_PFGEN_CTRL);
924 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
925 break;
926 usleep_range(1000, 2000);
927 }
928 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
929 hw_dbg(hw, "PF reset polling failed to complete.\n");
930 return I40E_ERR_RESET_FAILED;
931 }
932 }
933
934 i40e_clear_pxe_mode(hw);
935
936 return 0;
937 }
938
939 /**
940 * i40e_clear_hw - clear out any left over hw state
941 * @hw: pointer to the hw struct
942 *
943 * Clear queues and interrupts, typically called at init time,
944 * but after the capabilities have been found so we know how many
945 * queues and msix vectors have been allocated.
946 **/
947 void i40e_clear_hw(struct i40e_hw *hw)
948 {
949 u32 num_queues, base_queue;
950 u32 num_pf_int;
951 u32 num_vf_int;
952 u32 num_vfs;
953 u32 i, j;
954 u32 val;
955 u32 eol = 0x7ff;
956
957 /* get number of interrupts, queues, and vfs */
958 val = rd32(hw, I40E_GLPCI_CNF2);
959 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
960 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
961 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
962 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
963
964 val = rd32(hw, I40E_PFLAN_QALLOC);
965 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
966 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
967 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
968 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
969 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
970 num_queues = (j - base_queue) + 1;
971 else
972 num_queues = 0;
973
974 val = rd32(hw, I40E_PF_VT_PFALLOC);
975 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
976 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
977 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
978 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
979 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
980 num_vfs = (j - i) + 1;
981 else
982 num_vfs = 0;
983
984 /* stop all the interrupts */
985 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
986 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
987 for (i = 0; i < num_pf_int - 2; i++)
988 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
989
990 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
991 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
992 wr32(hw, I40E_PFINT_LNKLST0, val);
993 for (i = 0; i < num_pf_int - 2; i++)
994 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
995 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
996 for (i = 0; i < num_vfs; i++)
997 wr32(hw, I40E_VPINT_LNKLST0(i), val);
998 for (i = 0; i < num_vf_int - 2; i++)
999 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1000
1001 /* warn the HW of the coming Tx disables */
1002 for (i = 0; i < num_queues; i++) {
1003 u32 abs_queue_idx = base_queue + i;
1004 u32 reg_block = 0;
1005
1006 if (abs_queue_idx >= 128) {
1007 reg_block = abs_queue_idx / 128;
1008 abs_queue_idx %= 128;
1009 }
1010
1011 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1012 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1013 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1014 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1015
1016 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1017 }
1018 udelay(400);
1019
1020 /* stop all the queues */
1021 for (i = 0; i < num_queues; i++) {
1022 wr32(hw, I40E_QINT_TQCTL(i), 0);
1023 wr32(hw, I40E_QTX_ENA(i), 0);
1024 wr32(hw, I40E_QINT_RQCTL(i), 0);
1025 wr32(hw, I40E_QRX_ENA(i), 0);
1026 }
1027
1028 /* short wait for all queue disables to settle */
1029 udelay(50);
1030 }
1031
1032 /**
1033 * i40e_clear_pxe_mode - clear pxe operations mode
1034 * @hw: pointer to the hw struct
1035 *
1036 * Make sure all PXE mode settings are cleared, including things
1037 * like descriptor fetch/write-back mode.
1038 **/
1039 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1040 {
1041 u32 reg;
1042
1043 if (i40e_check_asq_alive(hw))
1044 i40e_aq_clear_pxe_mode(hw, NULL);
1045
1046 /* Clear single descriptor fetch/write-back mode */
1047 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1048
1049 if (hw->revision_id == 0) {
1050 /* As a work around clear PXE_MODE instead of setting it */
1051 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1052 } else {
1053 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1054 }
1055 }
1056
1057 /**
1058 * i40e_led_is_mine - helper to find matching led
1059 * @hw: pointer to the hw struct
1060 * @idx: index into GPIO registers
1061 *
1062 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1063 */
1064 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1065 {
1066 u32 gpio_val = 0;
1067 u32 port;
1068
1069 if (!hw->func_caps.led[idx])
1070 return 0;
1071
1072 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1073 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1074 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1075
1076 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1077 * if it is not our port then ignore
1078 */
1079 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1080 (port != hw->port))
1081 return 0;
1082
1083 return gpio_val;
1084 }
1085
1086 #define I40E_COMBINED_ACTIVITY 0xA
1087 #define I40E_FILTER_ACTIVITY 0xE
1088 #define I40E_LINK_ACTIVITY 0xC
1089 #define I40E_MAC_ACTIVITY 0xD
1090 #define I40E_LED0 22
1091
1092 /**
1093 * i40e_led_get - return current on/off mode
1094 * @hw: pointer to the hw struct
1095 *
1096 * The value returned is the 'mode' field as defined in the
1097 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1098 * values are variations of possible behaviors relating to
1099 * blink, link, and wire.
1100 **/
1101 u32 i40e_led_get(struct i40e_hw *hw)
1102 {
1103 u32 current_mode = 0;
1104 u32 mode = 0;
1105 int i;
1106
1107 /* as per the documentation GPIO 22-29 are the LED
1108 * GPIO pins named LED0..LED7
1109 */
1110 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1111 u32 gpio_val = i40e_led_is_mine(hw, i);
1112
1113 if (!gpio_val)
1114 continue;
1115
1116 /* ignore gpio LED src mode entries related to the activity
1117 * LEDs
1118 */
1119 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1120 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1121 switch (current_mode) {
1122 case I40E_COMBINED_ACTIVITY:
1123 case I40E_FILTER_ACTIVITY:
1124 case I40E_MAC_ACTIVITY:
1125 continue;
1126 default:
1127 break;
1128 }
1129
1130 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1131 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1132 break;
1133 }
1134
1135 return mode;
1136 }
1137
1138 /**
1139 * i40e_led_set - set new on/off mode
1140 * @hw: pointer to the hw struct
1141 * @mode: 0=off, 0xf=on (else see manual for mode details)
1142 * @blink: true if the LED should blink when on, false if steady
1143 *
1144 * if this function is used to turn on the blink it should
1145 * be used to disable the blink when restoring the original state.
1146 **/
1147 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1148 {
1149 u32 current_mode = 0;
1150 int i;
1151
1152 if (mode & 0xfffffff0)
1153 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1154
1155 /* as per the documentation GPIO 22-29 are the LED
1156 * GPIO pins named LED0..LED7
1157 */
1158 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1159 u32 gpio_val = i40e_led_is_mine(hw, i);
1160
1161 if (!gpio_val)
1162 continue;
1163
1164 /* ignore gpio LED src mode entries related to the activity
1165 * LEDs
1166 */
1167 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1168 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1169 switch (current_mode) {
1170 case I40E_COMBINED_ACTIVITY:
1171 case I40E_FILTER_ACTIVITY:
1172 case I40E_MAC_ACTIVITY:
1173 continue;
1174 default:
1175 break;
1176 }
1177
1178 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1179 /* this & is a bit of paranoia, but serves as a range check */
1180 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1181 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1182
1183 if (mode == I40E_LINK_ACTIVITY)
1184 blink = false;
1185
1186 if (blink)
1187 gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1188 else
1189 gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1190
1191 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1192 break;
1193 }
1194 }
1195
1196 /* Admin command wrappers */
1197
1198 /**
1199 * i40e_aq_get_phy_capabilities
1200 * @hw: pointer to the hw struct
1201 * @abilities: structure for PHY capabilities to be filled
1202 * @qualified_modules: report Qualified Modules
1203 * @report_init: report init capabilities (active are default)
1204 * @cmd_details: pointer to command details structure or NULL
1205 *
1206 * Returns the various PHY abilities supported on the Port.
1207 **/
1208 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1209 bool qualified_modules, bool report_init,
1210 struct i40e_aq_get_phy_abilities_resp *abilities,
1211 struct i40e_asq_cmd_details *cmd_details)
1212 {
1213 struct i40e_aq_desc desc;
1214 i40e_status status;
1215 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1216
1217 if (!abilities)
1218 return I40E_ERR_PARAM;
1219
1220 i40e_fill_default_direct_cmd_desc(&desc,
1221 i40e_aqc_opc_get_phy_abilities);
1222
1223 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1224 if (abilities_size > I40E_AQ_LARGE_BUF)
1225 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1226
1227 if (qualified_modules)
1228 desc.params.external.param0 |=
1229 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1230
1231 if (report_init)
1232 desc.params.external.param0 |=
1233 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1234
1235 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1236 cmd_details);
1237
1238 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1239 status = I40E_ERR_UNKNOWN_PHY;
1240
1241 return status;
1242 }
1243
1244 /**
1245 * i40e_aq_set_phy_config
1246 * @hw: pointer to the hw struct
1247 * @config: structure with PHY configuration to be set
1248 * @cmd_details: pointer to command details structure or NULL
1249 *
1250 * Set the various PHY configuration parameters
1251 * supported on the Port.One or more of the Set PHY config parameters may be
1252 * ignored in an MFP mode as the PF may not have the privilege to set some
1253 * of the PHY Config parameters. This status will be indicated by the
1254 * command response.
1255 **/
1256 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1257 struct i40e_aq_set_phy_config *config,
1258 struct i40e_asq_cmd_details *cmd_details)
1259 {
1260 struct i40e_aq_desc desc;
1261 struct i40e_aq_set_phy_config *cmd =
1262 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1263 enum i40e_status_code status;
1264
1265 if (!config)
1266 return I40E_ERR_PARAM;
1267
1268 i40e_fill_default_direct_cmd_desc(&desc,
1269 i40e_aqc_opc_set_phy_config);
1270
1271 *cmd = *config;
1272
1273 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1274
1275 return status;
1276 }
1277
1278 /**
1279 * i40e_set_fc
1280 * @hw: pointer to the hw struct
1281 *
1282 * Set the requested flow control mode using set_phy_config.
1283 **/
1284 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1285 bool atomic_restart)
1286 {
1287 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1288 struct i40e_aq_get_phy_abilities_resp abilities;
1289 struct i40e_aq_set_phy_config config;
1290 enum i40e_status_code status;
1291 u8 pause_mask = 0x0;
1292
1293 *aq_failures = 0x0;
1294
1295 switch (fc_mode) {
1296 case I40E_FC_FULL:
1297 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1298 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1299 break;
1300 case I40E_FC_RX_PAUSE:
1301 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1302 break;
1303 case I40E_FC_TX_PAUSE:
1304 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1305 break;
1306 default:
1307 break;
1308 }
1309
1310 /* Get the current phy config */
1311 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1312 NULL);
1313 if (status) {
1314 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1315 return status;
1316 }
1317
1318 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1319 /* clear the old pause settings */
1320 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1321 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1322 /* set the new abilities */
1323 config.abilities |= pause_mask;
1324 /* If the abilities have changed, then set the new config */
1325 if (config.abilities != abilities.abilities) {
1326 /* Auto restart link so settings take effect */
1327 if (atomic_restart)
1328 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1329 /* Copy over all the old settings */
1330 config.phy_type = abilities.phy_type;
1331 config.link_speed = abilities.link_speed;
1332 config.eee_capability = abilities.eee_capability;
1333 config.eeer = abilities.eeer_val;
1334 config.low_power_ctrl = abilities.d3_lpan;
1335 status = i40e_aq_set_phy_config(hw, &config, NULL);
1336
1337 if (status)
1338 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1339 }
1340 /* Update the link info */
1341 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1342 if (status) {
1343 /* Wait a little bit (on 40G cards it sometimes takes a really
1344 * long time for link to come back from the atomic reset)
1345 * and try once more
1346 */
1347 msleep(1000);
1348 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1349 }
1350 if (status)
1351 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1352
1353 return status;
1354 }
1355
1356 /**
1357 * i40e_aq_clear_pxe_mode
1358 * @hw: pointer to the hw struct
1359 * @cmd_details: pointer to command details structure or NULL
1360 *
1361 * Tell the firmware that the driver is taking over from PXE
1362 **/
1363 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1364 struct i40e_asq_cmd_details *cmd_details)
1365 {
1366 i40e_status status;
1367 struct i40e_aq_desc desc;
1368 struct i40e_aqc_clear_pxe *cmd =
1369 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1370
1371 i40e_fill_default_direct_cmd_desc(&desc,
1372 i40e_aqc_opc_clear_pxe_mode);
1373
1374 cmd->rx_cnt = 0x2;
1375
1376 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1377
1378 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1379
1380 return status;
1381 }
1382
1383 /**
1384 * i40e_aq_set_link_restart_an
1385 * @hw: pointer to the hw struct
1386 * @enable_link: if true: enable link, if false: disable link
1387 * @cmd_details: pointer to command details structure or NULL
1388 *
1389 * Sets up the link and restarts the Auto-Negotiation over the link.
1390 **/
1391 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1392 bool enable_link,
1393 struct i40e_asq_cmd_details *cmd_details)
1394 {
1395 struct i40e_aq_desc desc;
1396 struct i40e_aqc_set_link_restart_an *cmd =
1397 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1398 i40e_status status;
1399
1400 i40e_fill_default_direct_cmd_desc(&desc,
1401 i40e_aqc_opc_set_link_restart_an);
1402
1403 cmd->command = I40E_AQ_PHY_RESTART_AN;
1404 if (enable_link)
1405 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1406 else
1407 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1408
1409 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1410
1411 return status;
1412 }
1413
1414 /**
1415 * i40e_aq_get_link_info
1416 * @hw: pointer to the hw struct
1417 * @enable_lse: enable/disable LinkStatusEvent reporting
1418 * @link: pointer to link status structure - optional
1419 * @cmd_details: pointer to command details structure or NULL
1420 *
1421 * Returns the link status of the adapter.
1422 **/
1423 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1424 bool enable_lse, struct i40e_link_status *link,
1425 struct i40e_asq_cmd_details *cmd_details)
1426 {
1427 struct i40e_aq_desc desc;
1428 struct i40e_aqc_get_link_status *resp =
1429 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1430 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1431 i40e_status status;
1432 bool tx_pause, rx_pause;
1433 u16 command_flags;
1434
1435 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1436
1437 if (enable_lse)
1438 command_flags = I40E_AQ_LSE_ENABLE;
1439 else
1440 command_flags = I40E_AQ_LSE_DISABLE;
1441 resp->command_flags = cpu_to_le16(command_flags);
1442
1443 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1444
1445 if (status)
1446 goto aq_get_link_info_exit;
1447
1448 /* save off old link status information */
1449 hw->phy.link_info_old = *hw_link_info;
1450
1451 /* update link status */
1452 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1453 hw->phy.media_type = i40e_get_media_type(hw);
1454 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1455 hw_link_info->link_info = resp->link_info;
1456 hw_link_info->an_info = resp->an_info;
1457 hw_link_info->ext_info = resp->ext_info;
1458 hw_link_info->loopback = resp->loopback;
1459 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1460 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1461
1462 /* update fc info */
1463 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1464 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1465 if (tx_pause & rx_pause)
1466 hw->fc.current_mode = I40E_FC_FULL;
1467 else if (tx_pause)
1468 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1469 else if (rx_pause)
1470 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1471 else
1472 hw->fc.current_mode = I40E_FC_NONE;
1473
1474 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1475 hw_link_info->crc_enable = true;
1476 else
1477 hw_link_info->crc_enable = false;
1478
1479 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1480 hw_link_info->lse_enable = true;
1481 else
1482 hw_link_info->lse_enable = false;
1483
1484 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1485 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1486 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1487
1488 /* save link status information */
1489 if (link)
1490 *link = *hw_link_info;
1491
1492 /* flag cleared so helper functions don't call AQ again */
1493 hw->phy.get_link_info = false;
1494
1495 aq_get_link_info_exit:
1496 return status;
1497 }
1498
1499 /**
1500 * i40e_aq_set_phy_int_mask
1501 * @hw: pointer to the hw struct
1502 * @mask: interrupt mask to be set
1503 * @cmd_details: pointer to command details structure or NULL
1504 *
1505 * Set link interrupt mask.
1506 **/
1507 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1508 u16 mask,
1509 struct i40e_asq_cmd_details *cmd_details)
1510 {
1511 struct i40e_aq_desc desc;
1512 struct i40e_aqc_set_phy_int_mask *cmd =
1513 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1514 i40e_status status;
1515
1516 i40e_fill_default_direct_cmd_desc(&desc,
1517 i40e_aqc_opc_set_phy_int_mask);
1518
1519 cmd->event_mask = cpu_to_le16(mask);
1520
1521 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1522
1523 return status;
1524 }
1525
1526 /**
1527 * i40e_aq_add_vsi
1528 * @hw: pointer to the hw struct
1529 * @vsi_ctx: pointer to a vsi context struct
1530 * @cmd_details: pointer to command details structure or NULL
1531 *
1532 * Add a VSI context to the hardware.
1533 **/
1534 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1535 struct i40e_vsi_context *vsi_ctx,
1536 struct i40e_asq_cmd_details *cmd_details)
1537 {
1538 struct i40e_aq_desc desc;
1539 struct i40e_aqc_add_get_update_vsi *cmd =
1540 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1541 struct i40e_aqc_add_get_update_vsi_completion *resp =
1542 (struct i40e_aqc_add_get_update_vsi_completion *)
1543 &desc.params.raw;
1544 i40e_status status;
1545
1546 i40e_fill_default_direct_cmd_desc(&desc,
1547 i40e_aqc_opc_add_vsi);
1548
1549 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1550 cmd->connection_type = vsi_ctx->connection_type;
1551 cmd->vf_id = vsi_ctx->vf_num;
1552 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1553
1554 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1555
1556 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1557 sizeof(vsi_ctx->info), cmd_details);
1558
1559 if (status)
1560 goto aq_add_vsi_exit;
1561
1562 vsi_ctx->seid = le16_to_cpu(resp->seid);
1563 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1564 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1565 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1566
1567 aq_add_vsi_exit:
1568 return status;
1569 }
1570
1571 /**
1572 * i40e_aq_set_vsi_unicast_promiscuous
1573 * @hw: pointer to the hw struct
1574 * @seid: vsi number
1575 * @set: set unicast promiscuous enable/disable
1576 * @cmd_details: pointer to command details structure or NULL
1577 **/
1578 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1579 u16 seid, bool set,
1580 struct i40e_asq_cmd_details *cmd_details)
1581 {
1582 struct i40e_aq_desc desc;
1583 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1584 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1585 i40e_status status;
1586 u16 flags = 0;
1587
1588 i40e_fill_default_direct_cmd_desc(&desc,
1589 i40e_aqc_opc_set_vsi_promiscuous_modes);
1590
1591 if (set)
1592 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1593
1594 cmd->promiscuous_flags = cpu_to_le16(flags);
1595
1596 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1597
1598 cmd->seid = cpu_to_le16(seid);
1599 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1600
1601 return status;
1602 }
1603
1604 /**
1605 * i40e_aq_set_vsi_multicast_promiscuous
1606 * @hw: pointer to the hw struct
1607 * @seid: vsi number
1608 * @set: set multicast promiscuous enable/disable
1609 * @cmd_details: pointer to command details structure or NULL
1610 **/
1611 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1612 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1613 {
1614 struct i40e_aq_desc desc;
1615 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1616 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1617 i40e_status status;
1618 u16 flags = 0;
1619
1620 i40e_fill_default_direct_cmd_desc(&desc,
1621 i40e_aqc_opc_set_vsi_promiscuous_modes);
1622
1623 if (set)
1624 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1625
1626 cmd->promiscuous_flags = cpu_to_le16(flags);
1627
1628 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1629
1630 cmd->seid = cpu_to_le16(seid);
1631 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1632
1633 return status;
1634 }
1635
1636 /**
1637 * i40e_aq_set_vsi_broadcast
1638 * @hw: pointer to the hw struct
1639 * @seid: vsi number
1640 * @set_filter: true to set filter, false to clear filter
1641 * @cmd_details: pointer to command details structure or NULL
1642 *
1643 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1644 **/
1645 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1646 u16 seid, bool set_filter,
1647 struct i40e_asq_cmd_details *cmd_details)
1648 {
1649 struct i40e_aq_desc desc;
1650 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1651 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1652 i40e_status status;
1653
1654 i40e_fill_default_direct_cmd_desc(&desc,
1655 i40e_aqc_opc_set_vsi_promiscuous_modes);
1656
1657 if (set_filter)
1658 cmd->promiscuous_flags
1659 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1660 else
1661 cmd->promiscuous_flags
1662 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1663
1664 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1665 cmd->seid = cpu_to_le16(seid);
1666 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1667
1668 return status;
1669 }
1670
1671 /**
1672 * i40e_get_vsi_params - get VSI configuration info
1673 * @hw: pointer to the hw struct
1674 * @vsi_ctx: pointer to a vsi context struct
1675 * @cmd_details: pointer to command details structure or NULL
1676 **/
1677 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
1678 struct i40e_vsi_context *vsi_ctx,
1679 struct i40e_asq_cmd_details *cmd_details)
1680 {
1681 struct i40e_aq_desc desc;
1682 struct i40e_aqc_add_get_update_vsi *cmd =
1683 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1684 struct i40e_aqc_add_get_update_vsi_completion *resp =
1685 (struct i40e_aqc_add_get_update_vsi_completion *)
1686 &desc.params.raw;
1687 i40e_status status;
1688
1689 i40e_fill_default_direct_cmd_desc(&desc,
1690 i40e_aqc_opc_get_vsi_parameters);
1691
1692 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
1693
1694 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1695
1696 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1697 sizeof(vsi_ctx->info), NULL);
1698
1699 if (status)
1700 goto aq_get_vsi_params_exit;
1701
1702 vsi_ctx->seid = le16_to_cpu(resp->seid);
1703 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1704 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1705 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1706
1707 aq_get_vsi_params_exit:
1708 return status;
1709 }
1710
1711 /**
1712 * i40e_aq_update_vsi_params
1713 * @hw: pointer to the hw struct
1714 * @vsi_ctx: pointer to a vsi context struct
1715 * @cmd_details: pointer to command details structure or NULL
1716 *
1717 * Update a VSI context.
1718 **/
1719 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
1720 struct i40e_vsi_context *vsi_ctx,
1721 struct i40e_asq_cmd_details *cmd_details)
1722 {
1723 struct i40e_aq_desc desc;
1724 struct i40e_aqc_add_get_update_vsi *cmd =
1725 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1726 i40e_status status;
1727
1728 i40e_fill_default_direct_cmd_desc(&desc,
1729 i40e_aqc_opc_update_vsi_parameters);
1730 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
1731
1732 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1733
1734 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1735 sizeof(vsi_ctx->info), cmd_details);
1736
1737 return status;
1738 }
1739
1740 /**
1741 * i40e_aq_get_switch_config
1742 * @hw: pointer to the hardware structure
1743 * @buf: pointer to the result buffer
1744 * @buf_size: length of input buffer
1745 * @start_seid: seid to start for the report, 0 == beginning
1746 * @cmd_details: pointer to command details structure or NULL
1747 *
1748 * Fill the buf with switch configuration returned from AdminQ command
1749 **/
1750 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
1751 struct i40e_aqc_get_switch_config_resp *buf,
1752 u16 buf_size, u16 *start_seid,
1753 struct i40e_asq_cmd_details *cmd_details)
1754 {
1755 struct i40e_aq_desc desc;
1756 struct i40e_aqc_switch_seid *scfg =
1757 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1758 i40e_status status;
1759
1760 i40e_fill_default_direct_cmd_desc(&desc,
1761 i40e_aqc_opc_get_switch_config);
1762 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1763 if (buf_size > I40E_AQ_LARGE_BUF)
1764 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1765 scfg->seid = cpu_to_le16(*start_seid);
1766
1767 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1768 *start_seid = le16_to_cpu(scfg->seid);
1769
1770 return status;
1771 }
1772
1773 /**
1774 * i40e_aq_get_firmware_version
1775 * @hw: pointer to the hw struct
1776 * @fw_major_version: firmware major version
1777 * @fw_minor_version: firmware minor version
1778 * @fw_build: firmware build number
1779 * @api_major_version: major queue version
1780 * @api_minor_version: minor queue version
1781 * @cmd_details: pointer to command details structure or NULL
1782 *
1783 * Get the firmware version from the admin queue commands
1784 **/
1785 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
1786 u16 *fw_major_version, u16 *fw_minor_version,
1787 u32 *fw_build,
1788 u16 *api_major_version, u16 *api_minor_version,
1789 struct i40e_asq_cmd_details *cmd_details)
1790 {
1791 struct i40e_aq_desc desc;
1792 struct i40e_aqc_get_version *resp =
1793 (struct i40e_aqc_get_version *)&desc.params.raw;
1794 i40e_status status;
1795
1796 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1797
1798 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1799
1800 if (!status) {
1801 if (fw_major_version)
1802 *fw_major_version = le16_to_cpu(resp->fw_major);
1803 if (fw_minor_version)
1804 *fw_minor_version = le16_to_cpu(resp->fw_minor);
1805 if (fw_build)
1806 *fw_build = le32_to_cpu(resp->fw_build);
1807 if (api_major_version)
1808 *api_major_version = le16_to_cpu(resp->api_major);
1809 if (api_minor_version)
1810 *api_minor_version = le16_to_cpu(resp->api_minor);
1811 }
1812
1813 return status;
1814 }
1815
1816 /**
1817 * i40e_aq_send_driver_version
1818 * @hw: pointer to the hw struct
1819 * @dv: driver's major, minor version
1820 * @cmd_details: pointer to command details structure or NULL
1821 *
1822 * Send the driver version to the firmware
1823 **/
1824 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
1825 struct i40e_driver_version *dv,
1826 struct i40e_asq_cmd_details *cmd_details)
1827 {
1828 struct i40e_aq_desc desc;
1829 struct i40e_aqc_driver_version *cmd =
1830 (struct i40e_aqc_driver_version *)&desc.params.raw;
1831 i40e_status status;
1832 u16 len;
1833
1834 if (dv == NULL)
1835 return I40E_ERR_PARAM;
1836
1837 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1838
1839 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
1840 cmd->driver_major_ver = dv->major_version;
1841 cmd->driver_minor_ver = dv->minor_version;
1842 cmd->driver_build_ver = dv->build_version;
1843 cmd->driver_subbuild_ver = dv->subbuild_version;
1844
1845 len = 0;
1846 while (len < sizeof(dv->driver_string) &&
1847 (dv->driver_string[len] < 0x80) &&
1848 dv->driver_string[len])
1849 len++;
1850 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1851 len, cmd_details);
1852
1853 return status;
1854 }
1855
1856 /**
1857 * i40e_get_link_status - get status of the HW network link
1858 * @hw: pointer to the hw struct
1859 *
1860 * Returns true if link is up, false if link is down.
1861 *
1862 * Side effect: LinkStatusEvent reporting becomes enabled
1863 **/
1864 bool i40e_get_link_status(struct i40e_hw *hw)
1865 {
1866 i40e_status status = 0;
1867 bool link_status = false;
1868
1869 if (hw->phy.get_link_info) {
1870 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1871
1872 if (status)
1873 goto i40e_get_link_status_exit;
1874 }
1875
1876 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1877
1878 i40e_get_link_status_exit:
1879 return link_status;
1880 }
1881
1882 /**
1883 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1884 * @hw: pointer to the hw struct
1885 * @uplink_seid: the MAC or other gizmo SEID
1886 * @downlink_seid: the VSI SEID
1887 * @enabled_tc: bitmap of TCs to be enabled
1888 * @default_port: true for default port VSI, false for control port
1889 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
1890 * @veb_seid: pointer to where to put the resulting VEB SEID
1891 * @cmd_details: pointer to command details structure or NULL
1892 *
1893 * This asks the FW to add a VEB between the uplink and downlink
1894 * elements. If the uplink SEID is 0, this will be a floating VEB.
1895 **/
1896 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
1897 u16 downlink_seid, u8 enabled_tc,
1898 bool default_port, bool enable_l2_filtering,
1899 u16 *veb_seid,
1900 struct i40e_asq_cmd_details *cmd_details)
1901 {
1902 struct i40e_aq_desc desc;
1903 struct i40e_aqc_add_veb *cmd =
1904 (struct i40e_aqc_add_veb *)&desc.params.raw;
1905 struct i40e_aqc_add_veb_completion *resp =
1906 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1907 i40e_status status;
1908 u16 veb_flags = 0;
1909
1910 /* SEIDs need to either both be set or both be 0 for floating VEB */
1911 if (!!uplink_seid != !!downlink_seid)
1912 return I40E_ERR_PARAM;
1913
1914 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1915
1916 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1917 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1918 cmd->enable_tcs = enabled_tc;
1919 if (!uplink_seid)
1920 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1921 if (default_port)
1922 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1923 else
1924 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
1925
1926 if (enable_l2_filtering)
1927 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1928
1929 cmd->veb_flags = cpu_to_le16(veb_flags);
1930
1931 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1932
1933 if (!status && veb_seid)
1934 *veb_seid = le16_to_cpu(resp->veb_seid);
1935
1936 return status;
1937 }
1938
1939 /**
1940 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1941 * @hw: pointer to the hw struct
1942 * @veb_seid: the SEID of the VEB to query
1943 * @switch_id: the uplink switch id
1944 * @floating: set to true if the VEB is floating
1945 * @statistic_index: index of the stats counter block for this VEB
1946 * @vebs_used: number of VEB's used by function
1947 * @vebs_free: total VEB's not reserved by any function
1948 * @cmd_details: pointer to command details structure or NULL
1949 *
1950 * This retrieves the parameters for a particular VEB, specified by
1951 * uplink_seid, and returns them to the caller.
1952 **/
1953 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1954 u16 veb_seid, u16 *switch_id,
1955 bool *floating, u16 *statistic_index,
1956 u16 *vebs_used, u16 *vebs_free,
1957 struct i40e_asq_cmd_details *cmd_details)
1958 {
1959 struct i40e_aq_desc desc;
1960 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1961 (struct i40e_aqc_get_veb_parameters_completion *)
1962 &desc.params.raw;
1963 i40e_status status;
1964
1965 if (veb_seid == 0)
1966 return I40E_ERR_PARAM;
1967
1968 i40e_fill_default_direct_cmd_desc(&desc,
1969 i40e_aqc_opc_get_veb_parameters);
1970 cmd_resp->seid = cpu_to_le16(veb_seid);
1971
1972 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1973 if (status)
1974 goto get_veb_exit;
1975
1976 if (switch_id)
1977 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1978 if (statistic_index)
1979 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1980 if (vebs_used)
1981 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1982 if (vebs_free)
1983 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1984 if (floating) {
1985 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1986 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1987 *floating = true;
1988 else
1989 *floating = false;
1990 }
1991
1992 get_veb_exit:
1993 return status;
1994 }
1995
1996 /**
1997 * i40e_aq_add_macvlan
1998 * @hw: pointer to the hw struct
1999 * @seid: VSI for the mac address
2000 * @mv_list: list of macvlans to be added
2001 * @count: length of the list
2002 * @cmd_details: pointer to command details structure or NULL
2003 *
2004 * Add MAC/VLAN addresses to the HW filtering
2005 **/
2006 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2007 struct i40e_aqc_add_macvlan_element_data *mv_list,
2008 u16 count, struct i40e_asq_cmd_details *cmd_details)
2009 {
2010 struct i40e_aq_desc desc;
2011 struct i40e_aqc_macvlan *cmd =
2012 (struct i40e_aqc_macvlan *)&desc.params.raw;
2013 i40e_status status;
2014 u16 buf_size;
2015
2016 if (count == 0 || !mv_list || !hw)
2017 return I40E_ERR_PARAM;
2018
2019 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
2020
2021 /* prep the rest of the request */
2022 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2023 cmd->num_addresses = cpu_to_le16(count);
2024 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2025 cmd->seid[1] = 0;
2026 cmd->seid[2] = 0;
2027
2028 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2029 if (buf_size > I40E_AQ_LARGE_BUF)
2030 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2031
2032 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2033 cmd_details);
2034
2035 return status;
2036 }
2037
2038 /**
2039 * i40e_aq_remove_macvlan
2040 * @hw: pointer to the hw struct
2041 * @seid: VSI for the mac address
2042 * @mv_list: list of macvlans to be removed
2043 * @count: length of the list
2044 * @cmd_details: pointer to command details structure or NULL
2045 *
2046 * Remove MAC/VLAN addresses from the HW filtering
2047 **/
2048 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2049 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2050 u16 count, struct i40e_asq_cmd_details *cmd_details)
2051 {
2052 struct i40e_aq_desc desc;
2053 struct i40e_aqc_macvlan *cmd =
2054 (struct i40e_aqc_macvlan *)&desc.params.raw;
2055 i40e_status status;
2056 u16 buf_size;
2057
2058 if (count == 0 || !mv_list || !hw)
2059 return I40E_ERR_PARAM;
2060
2061 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
2062
2063 /* prep the rest of the request */
2064 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2065 cmd->num_addresses = cpu_to_le16(count);
2066 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2067 cmd->seid[1] = 0;
2068 cmd->seid[2] = 0;
2069
2070 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2071 if (buf_size > I40E_AQ_LARGE_BUF)
2072 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2073
2074 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2075 cmd_details);
2076
2077 return status;
2078 }
2079
2080 /**
2081 * i40e_aq_send_msg_to_vf
2082 * @hw: pointer to the hardware structure
2083 * @vfid: vf id to send msg
2084 * @v_opcode: opcodes for VF-PF communication
2085 * @v_retval: return error code
2086 * @msg: pointer to the msg buffer
2087 * @msglen: msg length
2088 * @cmd_details: pointer to command details
2089 *
2090 * send msg to vf
2091 **/
2092 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2093 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2094 struct i40e_asq_cmd_details *cmd_details)
2095 {
2096 struct i40e_aq_desc desc;
2097 struct i40e_aqc_pf_vf_message *cmd =
2098 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2099 i40e_status status;
2100
2101 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2102 cmd->id = cpu_to_le32(vfid);
2103 desc.cookie_high = cpu_to_le32(v_opcode);
2104 desc.cookie_low = cpu_to_le32(v_retval);
2105 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2106 if (msglen) {
2107 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2108 I40E_AQ_FLAG_RD));
2109 if (msglen > I40E_AQ_LARGE_BUF)
2110 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2111 desc.datalen = cpu_to_le16(msglen);
2112 }
2113 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2114
2115 return status;
2116 }
2117
2118 /**
2119 * i40e_aq_debug_read_register
2120 * @hw: pointer to the hw struct
2121 * @reg_addr: register address
2122 * @reg_val: register value
2123 * @cmd_details: pointer to command details structure or NULL
2124 *
2125 * Read the register using the admin queue commands
2126 **/
2127 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2128 u32 reg_addr, u64 *reg_val,
2129 struct i40e_asq_cmd_details *cmd_details)
2130 {
2131 struct i40e_aq_desc desc;
2132 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2133 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2134 i40e_status status;
2135
2136 if (reg_val == NULL)
2137 return I40E_ERR_PARAM;
2138
2139 i40e_fill_default_direct_cmd_desc(&desc,
2140 i40e_aqc_opc_debug_read_reg);
2141
2142 cmd_resp->address = cpu_to_le32(reg_addr);
2143
2144 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2145
2146 if (!status) {
2147 *reg_val = ((u64)cmd_resp->value_high << 32) |
2148 (u64)cmd_resp->value_low;
2149 *reg_val = le64_to_cpu(*reg_val);
2150 }
2151
2152 return status;
2153 }
2154
2155 /**
2156 * i40e_aq_debug_write_register
2157 * @hw: pointer to the hw struct
2158 * @reg_addr: register address
2159 * @reg_val: register value
2160 * @cmd_details: pointer to command details structure or NULL
2161 *
2162 * Write to a register using the admin queue commands
2163 **/
2164 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2165 u32 reg_addr, u64 reg_val,
2166 struct i40e_asq_cmd_details *cmd_details)
2167 {
2168 struct i40e_aq_desc desc;
2169 struct i40e_aqc_debug_reg_read_write *cmd =
2170 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2171 i40e_status status;
2172
2173 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2174
2175 cmd->address = cpu_to_le32(reg_addr);
2176 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2177 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2178
2179 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2180
2181 return status;
2182 }
2183
2184 /**
2185 * i40e_aq_set_hmc_resource_profile
2186 * @hw: pointer to the hw struct
2187 * @profile: type of profile the HMC is to be set as
2188 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2189 * @cmd_details: pointer to command details structure or NULL
2190 *
2191 * set the HMC profile of the device.
2192 **/
2193 i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2194 enum i40e_aq_hmc_profile profile,
2195 u8 pe_vf_enabled_count,
2196 struct i40e_asq_cmd_details *cmd_details)
2197 {
2198 struct i40e_aq_desc desc;
2199 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2200 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2201 i40e_status status;
2202
2203 i40e_fill_default_direct_cmd_desc(&desc,
2204 i40e_aqc_opc_set_hmc_resource_profile);
2205
2206 cmd->pm_profile = (u8)profile;
2207 cmd->pe_vf_enabled = pe_vf_enabled_count;
2208
2209 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2210
2211 return status;
2212 }
2213
2214 /**
2215 * i40e_aq_request_resource
2216 * @hw: pointer to the hw struct
2217 * @resource: resource id
2218 * @access: access type
2219 * @sdp_number: resource number
2220 * @timeout: the maximum time in ms that the driver may hold the resource
2221 * @cmd_details: pointer to command details structure or NULL
2222 *
2223 * requests common resource using the admin queue commands
2224 **/
2225 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2226 enum i40e_aq_resources_ids resource,
2227 enum i40e_aq_resource_access_type access,
2228 u8 sdp_number, u64 *timeout,
2229 struct i40e_asq_cmd_details *cmd_details)
2230 {
2231 struct i40e_aq_desc desc;
2232 struct i40e_aqc_request_resource *cmd_resp =
2233 (struct i40e_aqc_request_resource *)&desc.params.raw;
2234 i40e_status status;
2235
2236 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2237
2238 cmd_resp->resource_id = cpu_to_le16(resource);
2239 cmd_resp->access_type = cpu_to_le16(access);
2240 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2241
2242 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2243 /* The completion specifies the maximum time in ms that the driver
2244 * may hold the resource in the Timeout field.
2245 * If the resource is held by someone else, the command completes with
2246 * busy return value and the timeout field indicates the maximum time
2247 * the current owner of the resource has to free it.
2248 */
2249 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2250 *timeout = le32_to_cpu(cmd_resp->timeout);
2251
2252 return status;
2253 }
2254
2255 /**
2256 * i40e_aq_release_resource
2257 * @hw: pointer to the hw struct
2258 * @resource: resource id
2259 * @sdp_number: resource number
2260 * @cmd_details: pointer to command details structure or NULL
2261 *
2262 * release common resource using the admin queue commands
2263 **/
2264 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2265 enum i40e_aq_resources_ids resource,
2266 u8 sdp_number,
2267 struct i40e_asq_cmd_details *cmd_details)
2268 {
2269 struct i40e_aq_desc desc;
2270 struct i40e_aqc_request_resource *cmd =
2271 (struct i40e_aqc_request_resource *)&desc.params.raw;
2272 i40e_status status;
2273
2274 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2275
2276 cmd->resource_id = cpu_to_le16(resource);
2277 cmd->resource_number = cpu_to_le32(sdp_number);
2278
2279 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2280
2281 return status;
2282 }
2283
2284 /**
2285 * i40e_aq_read_nvm
2286 * @hw: pointer to the hw struct
2287 * @module_pointer: module pointer location in words from the NVM beginning
2288 * @offset: byte offset from the module beginning
2289 * @length: length of the section to be read (in bytes from the offset)
2290 * @data: command buffer (size [bytes] = length)
2291 * @last_command: tells if this is the last command in a series
2292 * @cmd_details: pointer to command details structure or NULL
2293 *
2294 * Read the NVM using the admin queue commands
2295 **/
2296 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2297 u32 offset, u16 length, void *data,
2298 bool last_command,
2299 struct i40e_asq_cmd_details *cmd_details)
2300 {
2301 struct i40e_aq_desc desc;
2302 struct i40e_aqc_nvm_update *cmd =
2303 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2304 i40e_status status;
2305
2306 /* In offset the highest byte must be zeroed. */
2307 if (offset & 0xFF000000) {
2308 status = I40E_ERR_PARAM;
2309 goto i40e_aq_read_nvm_exit;
2310 }
2311
2312 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2313
2314 /* If this is the last command in a series, set the proper flag. */
2315 if (last_command)
2316 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2317 cmd->module_pointer = module_pointer;
2318 cmd->offset = cpu_to_le32(offset);
2319 cmd->length = cpu_to_le16(length);
2320
2321 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2322 if (length > I40E_AQ_LARGE_BUF)
2323 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2324
2325 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2326
2327 i40e_aq_read_nvm_exit:
2328 return status;
2329 }
2330
2331 /**
2332 * i40e_aq_erase_nvm
2333 * @hw: pointer to the hw struct
2334 * @module_pointer: module pointer location in words from the NVM beginning
2335 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2336 * @length: length of the section to be erased (expressed in 4 KB)
2337 * @last_command: tells if this is the last command in a series
2338 * @cmd_details: pointer to command details structure or NULL
2339 *
2340 * Erase the NVM sector using the admin queue commands
2341 **/
2342 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2343 u32 offset, u16 length, bool last_command,
2344 struct i40e_asq_cmd_details *cmd_details)
2345 {
2346 struct i40e_aq_desc desc;
2347 struct i40e_aqc_nvm_update *cmd =
2348 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2349 i40e_status status;
2350
2351 /* In offset the highest byte must be zeroed. */
2352 if (offset & 0xFF000000) {
2353 status = I40E_ERR_PARAM;
2354 goto i40e_aq_erase_nvm_exit;
2355 }
2356
2357 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2358
2359 /* If this is the last command in a series, set the proper flag. */
2360 if (last_command)
2361 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2362 cmd->module_pointer = module_pointer;
2363 cmd->offset = cpu_to_le32(offset);
2364 cmd->length = cpu_to_le16(length);
2365
2366 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2367
2368 i40e_aq_erase_nvm_exit:
2369 return status;
2370 }
2371
2372 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2373 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2374 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2375 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2376 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2377 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2378 #define I40E_DEV_FUNC_CAP_VF 0x13
2379 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2380 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2381 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2382 #define I40E_DEV_FUNC_CAP_VSI 0x17
2383 #define I40E_DEV_FUNC_CAP_DCB 0x18
2384 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2385 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
2386 #define I40E_DEV_FUNC_CAP_RSS 0x40
2387 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2388 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2389 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2390 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2391 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2392 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2393 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2394 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2395 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2396 #define I40E_DEV_FUNC_CAP_LED 0x61
2397 #define I40E_DEV_FUNC_CAP_SDP 0x62
2398 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2399
2400 /**
2401 * i40e_parse_discover_capabilities
2402 * @hw: pointer to the hw struct
2403 * @buff: pointer to a buffer containing device/function capability records
2404 * @cap_count: number of capability records in the list
2405 * @list_type_opc: type of capabilities list to parse
2406 *
2407 * Parse the device/function capabilities list.
2408 **/
2409 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2410 u32 cap_count,
2411 enum i40e_admin_queue_opc list_type_opc)
2412 {
2413 struct i40e_aqc_list_capabilities_element_resp *cap;
2414 u32 valid_functions, num_functions;
2415 u32 number, logical_id, phys_id;
2416 struct i40e_hw_capabilities *p;
2417 u32 i = 0;
2418 u16 id;
2419
2420 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2421
2422 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2423 p = &hw->dev_caps;
2424 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2425 p = &hw->func_caps;
2426 else
2427 return;
2428
2429 for (i = 0; i < cap_count; i++, cap++) {
2430 id = le16_to_cpu(cap->id);
2431 number = le32_to_cpu(cap->number);
2432 logical_id = le32_to_cpu(cap->logical_id);
2433 phys_id = le32_to_cpu(cap->phys_id);
2434
2435 switch (id) {
2436 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2437 p->switch_mode = number;
2438 break;
2439 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2440 p->management_mode = number;
2441 break;
2442 case I40E_DEV_FUNC_CAP_NPAR:
2443 p->npar_enable = number;
2444 break;
2445 case I40E_DEV_FUNC_CAP_OS2BMC:
2446 p->os2bmc = number;
2447 break;
2448 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2449 p->valid_functions = number;
2450 break;
2451 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2452 if (number == 1)
2453 p->sr_iov_1_1 = true;
2454 break;
2455 case I40E_DEV_FUNC_CAP_VF:
2456 p->num_vfs = number;
2457 p->vf_base_id = logical_id;
2458 break;
2459 case I40E_DEV_FUNC_CAP_VMDQ:
2460 if (number == 1)
2461 p->vmdq = true;
2462 break;
2463 case I40E_DEV_FUNC_CAP_802_1_QBG:
2464 if (number == 1)
2465 p->evb_802_1_qbg = true;
2466 break;
2467 case I40E_DEV_FUNC_CAP_802_1_QBH:
2468 if (number == 1)
2469 p->evb_802_1_qbh = true;
2470 break;
2471 case I40E_DEV_FUNC_CAP_VSI:
2472 p->num_vsis = number;
2473 break;
2474 case I40E_DEV_FUNC_CAP_DCB:
2475 if (number == 1) {
2476 p->dcb = true;
2477 p->enabled_tcmap = logical_id;
2478 p->maxtc = phys_id;
2479 }
2480 break;
2481 case I40E_DEV_FUNC_CAP_FCOE:
2482 if (number == 1)
2483 p->fcoe = true;
2484 break;
2485 case I40E_DEV_FUNC_CAP_ISCSI:
2486 if (number == 1)
2487 p->iscsi = true;
2488 break;
2489 case I40E_DEV_FUNC_CAP_RSS:
2490 p->rss = true;
2491 p->rss_table_size = number;
2492 p->rss_table_entry_width = logical_id;
2493 break;
2494 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2495 p->num_rx_qp = number;
2496 p->base_queue = phys_id;
2497 break;
2498 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2499 p->num_tx_qp = number;
2500 p->base_queue = phys_id;
2501 break;
2502 case I40E_DEV_FUNC_CAP_MSIX:
2503 p->num_msix_vectors = number;
2504 break;
2505 case I40E_DEV_FUNC_CAP_MSIX_VF:
2506 p->num_msix_vectors_vf = number;
2507 break;
2508 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2509 if (number == 1)
2510 p->mfp_mode_1 = true;
2511 break;
2512 case I40E_DEV_FUNC_CAP_CEM:
2513 if (number == 1)
2514 p->mgmt_cem = true;
2515 break;
2516 case I40E_DEV_FUNC_CAP_IWARP:
2517 if (number == 1)
2518 p->iwarp = true;
2519 break;
2520 case I40E_DEV_FUNC_CAP_LED:
2521 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2522 p->led[phys_id] = true;
2523 break;
2524 case I40E_DEV_FUNC_CAP_SDP:
2525 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2526 p->sdp[phys_id] = true;
2527 break;
2528 case I40E_DEV_FUNC_CAP_MDIO:
2529 if (number == 1) {
2530 p->mdio_port_num = phys_id;
2531 p->mdio_port_mode = logical_id;
2532 }
2533 break;
2534 case I40E_DEV_FUNC_CAP_IEEE_1588:
2535 if (number == 1)
2536 p->ieee_1588 = true;
2537 break;
2538 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2539 p->fd = true;
2540 p->fd_filters_guaranteed = number;
2541 p->fd_filters_best_effort = logical_id;
2542 break;
2543 default:
2544 break;
2545 }
2546 }
2547
2548 /* Software override ensuring FCoE is disabled if npar or mfp
2549 * mode because it is not supported in these modes.
2550 */
2551 if (p->npar_enable || p->mfp_mode_1)
2552 p->fcoe = false;
2553
2554 /* count the enabled ports (aka the "not disabled" ports) */
2555 hw->num_ports = 0;
2556 for (i = 0; i < 4; i++) {
2557 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
2558 u64 port_cfg = 0;
2559
2560 /* use AQ read to get the physical register offset instead
2561 * of the port relative offset
2562 */
2563 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
2564 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
2565 hw->num_ports++;
2566 }
2567
2568 valid_functions = p->valid_functions;
2569 num_functions = 0;
2570 while (valid_functions) {
2571 if (valid_functions & 1)
2572 num_functions++;
2573 valid_functions >>= 1;
2574 }
2575
2576 /* partition id is 1-based, and functions are evenly spread
2577 * across the ports as partitions
2578 */
2579 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
2580 hw->num_partitions = num_functions / hw->num_ports;
2581
2582 /* additional HW specific goodies that might
2583 * someday be HW version specific
2584 */
2585 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2586 }
2587
2588 /**
2589 * i40e_aq_discover_capabilities
2590 * @hw: pointer to the hw struct
2591 * @buff: a virtual buffer to hold the capabilities
2592 * @buff_size: Size of the virtual buffer
2593 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2594 * @list_type_opc: capabilities type to discover - pass in the command opcode
2595 * @cmd_details: pointer to command details structure or NULL
2596 *
2597 * Get the device capabilities descriptions from the firmware
2598 **/
2599 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
2600 void *buff, u16 buff_size, u16 *data_size,
2601 enum i40e_admin_queue_opc list_type_opc,
2602 struct i40e_asq_cmd_details *cmd_details)
2603 {
2604 struct i40e_aqc_list_capabilites *cmd;
2605 struct i40e_aq_desc desc;
2606 i40e_status status = 0;
2607
2608 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2609
2610 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2611 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2612 status = I40E_ERR_PARAM;
2613 goto exit;
2614 }
2615
2616 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2617
2618 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2619 if (buff_size > I40E_AQ_LARGE_BUF)
2620 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2621
2622 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2623 *data_size = le16_to_cpu(desc.datalen);
2624
2625 if (status)
2626 goto exit;
2627
2628 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
2629 list_type_opc);
2630
2631 exit:
2632 return status;
2633 }
2634
2635 /**
2636 * i40e_aq_update_nvm
2637 * @hw: pointer to the hw struct
2638 * @module_pointer: module pointer location in words from the NVM beginning
2639 * @offset: byte offset from the module beginning
2640 * @length: length of the section to be written (in bytes from the offset)
2641 * @data: command buffer (size [bytes] = length)
2642 * @last_command: tells if this is the last command in a series
2643 * @cmd_details: pointer to command details structure or NULL
2644 *
2645 * Update the NVM using the admin queue commands
2646 **/
2647 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2648 u32 offset, u16 length, void *data,
2649 bool last_command,
2650 struct i40e_asq_cmd_details *cmd_details)
2651 {
2652 struct i40e_aq_desc desc;
2653 struct i40e_aqc_nvm_update *cmd =
2654 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2655 i40e_status status;
2656
2657 /* In offset the highest byte must be zeroed. */
2658 if (offset & 0xFF000000) {
2659 status = I40E_ERR_PARAM;
2660 goto i40e_aq_update_nvm_exit;
2661 }
2662
2663 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2664
2665 /* If this is the last command in a series, set the proper flag. */
2666 if (last_command)
2667 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2668 cmd->module_pointer = module_pointer;
2669 cmd->offset = cpu_to_le32(offset);
2670 cmd->length = cpu_to_le16(length);
2671
2672 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2673 if (length > I40E_AQ_LARGE_BUF)
2674 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2675
2676 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2677
2678 i40e_aq_update_nvm_exit:
2679 return status;
2680 }
2681
2682 /**
2683 * i40e_aq_get_lldp_mib
2684 * @hw: pointer to the hw struct
2685 * @bridge_type: type of bridge requested
2686 * @mib_type: Local, Remote or both Local and Remote MIBs
2687 * @buff: pointer to a user supplied buffer to store the MIB block
2688 * @buff_size: size of the buffer (in bytes)
2689 * @local_len : length of the returned Local LLDP MIB
2690 * @remote_len: length of the returned Remote LLDP MIB
2691 * @cmd_details: pointer to command details structure or NULL
2692 *
2693 * Requests the complete LLDP MIB (entire packet).
2694 **/
2695 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2696 u8 mib_type, void *buff, u16 buff_size,
2697 u16 *local_len, u16 *remote_len,
2698 struct i40e_asq_cmd_details *cmd_details)
2699 {
2700 struct i40e_aq_desc desc;
2701 struct i40e_aqc_lldp_get_mib *cmd =
2702 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2703 struct i40e_aqc_lldp_get_mib *resp =
2704 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2705 i40e_status status;
2706
2707 if (buff_size == 0 || !buff)
2708 return I40E_ERR_PARAM;
2709
2710 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2711 /* Indirect Command */
2712 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2713
2714 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2715 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2716 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2717
2718 desc.datalen = cpu_to_le16(buff_size);
2719
2720 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2721 if (buff_size > I40E_AQ_LARGE_BUF)
2722 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2723
2724 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2725 if (!status) {
2726 if (local_len != NULL)
2727 *local_len = le16_to_cpu(resp->local_len);
2728 if (remote_len != NULL)
2729 *remote_len = le16_to_cpu(resp->remote_len);
2730 }
2731
2732 return status;
2733 }
2734
2735 /**
2736 * i40e_aq_cfg_lldp_mib_change_event
2737 * @hw: pointer to the hw struct
2738 * @enable_update: Enable or Disable event posting
2739 * @cmd_details: pointer to command details structure or NULL
2740 *
2741 * Enable or Disable posting of an event on ARQ when LLDP MIB
2742 * associated with the interface changes
2743 **/
2744 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2745 bool enable_update,
2746 struct i40e_asq_cmd_details *cmd_details)
2747 {
2748 struct i40e_aq_desc desc;
2749 struct i40e_aqc_lldp_update_mib *cmd =
2750 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2751 i40e_status status;
2752
2753 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2754
2755 if (!enable_update)
2756 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2757
2758 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2759
2760 return status;
2761 }
2762
2763 /**
2764 * i40e_aq_stop_lldp
2765 * @hw: pointer to the hw struct
2766 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2767 * @cmd_details: pointer to command details structure or NULL
2768 *
2769 * Stop or Shutdown the embedded LLDP Agent
2770 **/
2771 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
2772 struct i40e_asq_cmd_details *cmd_details)
2773 {
2774 struct i40e_aq_desc desc;
2775 struct i40e_aqc_lldp_stop *cmd =
2776 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
2777 i40e_status status;
2778
2779 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
2780
2781 if (shutdown_agent)
2782 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
2783
2784 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2785
2786 return status;
2787 }
2788
2789 /**
2790 * i40e_aq_start_lldp
2791 * @hw: pointer to the hw struct
2792 * @cmd_details: pointer to command details structure or NULL
2793 *
2794 * Start the embedded LLDP Agent on all ports.
2795 **/
2796 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
2797 struct i40e_asq_cmd_details *cmd_details)
2798 {
2799 struct i40e_aq_desc desc;
2800 struct i40e_aqc_lldp_start *cmd =
2801 (struct i40e_aqc_lldp_start *)&desc.params.raw;
2802 i40e_status status;
2803
2804 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
2805
2806 cmd->command = I40E_AQ_LLDP_AGENT_START;
2807
2808 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2809
2810 return status;
2811 }
2812
2813 /**
2814 * i40e_aq_get_cee_dcb_config
2815 * @hw: pointer to the hw struct
2816 * @buff: response buffer that stores CEE operational configuration
2817 * @buff_size: size of the buffer passed
2818 * @cmd_details: pointer to command details structure or NULL
2819 *
2820 * Get CEE DCBX mode operational configuration from firmware
2821 **/
2822 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
2823 void *buff, u16 buff_size,
2824 struct i40e_asq_cmd_details *cmd_details)
2825 {
2826 struct i40e_aq_desc desc;
2827 i40e_status status;
2828
2829 if (buff_size == 0 || !buff)
2830 return I40E_ERR_PARAM;
2831
2832 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
2833
2834 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2835 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
2836 cmd_details);
2837
2838 return status;
2839 }
2840
2841 /**
2842 * i40e_aq_add_udp_tunnel
2843 * @hw: pointer to the hw struct
2844 * @udp_port: the UDP port to add
2845 * @header_len: length of the tunneling header length in DWords
2846 * @protocol_index: protocol index type
2847 * @filter_index: pointer to filter index
2848 * @cmd_details: pointer to command details structure or NULL
2849 **/
2850 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
2851 u16 udp_port, u8 protocol_index,
2852 u8 *filter_index,
2853 struct i40e_asq_cmd_details *cmd_details)
2854 {
2855 struct i40e_aq_desc desc;
2856 struct i40e_aqc_add_udp_tunnel *cmd =
2857 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
2858 struct i40e_aqc_del_udp_tunnel_completion *resp =
2859 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
2860 i40e_status status;
2861
2862 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
2863
2864 cmd->udp_port = cpu_to_le16(udp_port);
2865 cmd->protocol_type = protocol_index;
2866
2867 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2868
2869 if (!status && filter_index)
2870 *filter_index = resp->index;
2871
2872 return status;
2873 }
2874
2875 /**
2876 * i40e_aq_del_udp_tunnel
2877 * @hw: pointer to the hw struct
2878 * @index: filter index
2879 * @cmd_details: pointer to command details structure or NULL
2880 **/
2881 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
2882 struct i40e_asq_cmd_details *cmd_details)
2883 {
2884 struct i40e_aq_desc desc;
2885 struct i40e_aqc_remove_udp_tunnel *cmd =
2886 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
2887 i40e_status status;
2888
2889 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
2890
2891 cmd->index = index;
2892
2893 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2894
2895 return status;
2896 }
2897
2898 /**
2899 * i40e_aq_delete_element - Delete switch element
2900 * @hw: pointer to the hw struct
2901 * @seid: the SEID to delete from the switch
2902 * @cmd_details: pointer to command details structure or NULL
2903 *
2904 * This deletes a switch element from the switch.
2905 **/
2906 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
2907 struct i40e_asq_cmd_details *cmd_details)
2908 {
2909 struct i40e_aq_desc desc;
2910 struct i40e_aqc_switch_seid *cmd =
2911 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2912 i40e_status status;
2913
2914 if (seid == 0)
2915 return I40E_ERR_PARAM;
2916
2917 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
2918
2919 cmd->seid = cpu_to_le16(seid);
2920
2921 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2922
2923 return status;
2924 }
2925
2926 /**
2927 * i40e_aq_dcb_updated - DCB Updated Command
2928 * @hw: pointer to the hw struct
2929 * @cmd_details: pointer to command details structure or NULL
2930 *
2931 * EMP will return when the shared RPB settings have been
2932 * recomputed and modified. The retval field in the descriptor
2933 * will be set to 0 when RPB is modified.
2934 **/
2935 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
2936 struct i40e_asq_cmd_details *cmd_details)
2937 {
2938 struct i40e_aq_desc desc;
2939 i40e_status status;
2940
2941 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
2942
2943 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2944
2945 return status;
2946 }
2947
2948 /**
2949 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2950 * @hw: pointer to the hw struct
2951 * @seid: seid for the physical port/switching component/vsi
2952 * @buff: Indirect buffer to hold data parameters and response
2953 * @buff_size: Indirect buffer size
2954 * @opcode: Tx scheduler AQ command opcode
2955 * @cmd_details: pointer to command details structure or NULL
2956 *
2957 * Generic command handler for Tx scheduler AQ commands
2958 **/
2959 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
2960 void *buff, u16 buff_size,
2961 enum i40e_admin_queue_opc opcode,
2962 struct i40e_asq_cmd_details *cmd_details)
2963 {
2964 struct i40e_aq_desc desc;
2965 struct i40e_aqc_tx_sched_ind *cmd =
2966 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
2967 i40e_status status;
2968 bool cmd_param_flag = false;
2969
2970 switch (opcode) {
2971 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
2972 case i40e_aqc_opc_configure_vsi_tc_bw:
2973 case i40e_aqc_opc_enable_switching_comp_ets:
2974 case i40e_aqc_opc_modify_switching_comp_ets:
2975 case i40e_aqc_opc_disable_switching_comp_ets:
2976 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
2977 case i40e_aqc_opc_configure_switching_comp_bw_config:
2978 cmd_param_flag = true;
2979 break;
2980 case i40e_aqc_opc_query_vsi_bw_config:
2981 case i40e_aqc_opc_query_vsi_ets_sla_config:
2982 case i40e_aqc_opc_query_switching_comp_ets_config:
2983 case i40e_aqc_opc_query_port_ets_config:
2984 case i40e_aqc_opc_query_switching_comp_bw_config:
2985 cmd_param_flag = false;
2986 break;
2987 default:
2988 return I40E_ERR_PARAM;
2989 }
2990
2991 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2992
2993 /* Indirect command */
2994 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2995 if (cmd_param_flag)
2996 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
2997 if (buff_size > I40E_AQ_LARGE_BUF)
2998 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2999
3000 desc.datalen = cpu_to_le16(buff_size);
3001
3002 cmd->vsi_seid = cpu_to_le16(seid);
3003
3004 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3005
3006 return status;
3007 }
3008
3009 /**
3010 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3011 * @hw: pointer to the hw struct
3012 * @seid: VSI seid
3013 * @credit: BW limit credits (0 = disabled)
3014 * @max_credit: Max BW limit credits
3015 * @cmd_details: pointer to command details structure or NULL
3016 **/
3017 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3018 u16 seid, u16 credit, u8 max_credit,
3019 struct i40e_asq_cmd_details *cmd_details)
3020 {
3021 struct i40e_aq_desc desc;
3022 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3023 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3024 i40e_status status;
3025
3026 i40e_fill_default_direct_cmd_desc(&desc,
3027 i40e_aqc_opc_configure_vsi_bw_limit);
3028
3029 cmd->vsi_seid = cpu_to_le16(seid);
3030 cmd->credit = cpu_to_le16(credit);
3031 cmd->max_credit = max_credit;
3032
3033 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3034
3035 return status;
3036 }
3037
3038 /**
3039 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3040 * @hw: pointer to the hw struct
3041 * @seid: VSI seid
3042 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3043 * @cmd_details: pointer to command details structure or NULL
3044 **/
3045 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3046 u16 seid,
3047 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3048 struct i40e_asq_cmd_details *cmd_details)
3049 {
3050 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3051 i40e_aqc_opc_configure_vsi_tc_bw,
3052 cmd_details);
3053 }
3054
3055 /**
3056 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3057 * @hw: pointer to the hw struct
3058 * @seid: seid of the switching component connected to Physical Port
3059 * @ets_data: Buffer holding ETS parameters
3060 * @cmd_details: pointer to command details structure or NULL
3061 **/
3062 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3063 u16 seid,
3064 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3065 enum i40e_admin_queue_opc opcode,
3066 struct i40e_asq_cmd_details *cmd_details)
3067 {
3068 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3069 sizeof(*ets_data), opcode, cmd_details);
3070 }
3071
3072 /**
3073 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3074 * @hw: pointer to the hw struct
3075 * @seid: seid of the switching component
3076 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3077 * @cmd_details: pointer to command details structure or NULL
3078 **/
3079 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3080 u16 seid,
3081 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3082 struct i40e_asq_cmd_details *cmd_details)
3083 {
3084 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3085 i40e_aqc_opc_configure_switching_comp_bw_config,
3086 cmd_details);
3087 }
3088
3089 /**
3090 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3091 * @hw: pointer to the hw struct
3092 * @seid: seid of the VSI
3093 * @bw_data: Buffer to hold VSI BW configuration
3094 * @cmd_details: pointer to command details structure or NULL
3095 **/
3096 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3097 u16 seid,
3098 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3099 struct i40e_asq_cmd_details *cmd_details)
3100 {
3101 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3102 i40e_aqc_opc_query_vsi_bw_config,
3103 cmd_details);
3104 }
3105
3106 /**
3107 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3108 * @hw: pointer to the hw struct
3109 * @seid: seid of the VSI
3110 * @bw_data: Buffer to hold VSI BW configuration per TC
3111 * @cmd_details: pointer to command details structure or NULL
3112 **/
3113 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3114 u16 seid,
3115 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3116 struct i40e_asq_cmd_details *cmd_details)
3117 {
3118 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3119 i40e_aqc_opc_query_vsi_ets_sla_config,
3120 cmd_details);
3121 }
3122
3123 /**
3124 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3125 * @hw: pointer to the hw struct
3126 * @seid: seid of the switching component
3127 * @bw_data: Buffer to hold switching component's per TC BW config
3128 * @cmd_details: pointer to command details structure or NULL
3129 **/
3130 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3131 u16 seid,
3132 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3133 struct i40e_asq_cmd_details *cmd_details)
3134 {
3135 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3136 i40e_aqc_opc_query_switching_comp_ets_config,
3137 cmd_details);
3138 }
3139
3140 /**
3141 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3142 * @hw: pointer to the hw struct
3143 * @seid: seid of the VSI or switching component connected to Physical Port
3144 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3145 * @cmd_details: pointer to command details structure or NULL
3146 **/
3147 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3148 u16 seid,
3149 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3150 struct i40e_asq_cmd_details *cmd_details)
3151 {
3152 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3153 i40e_aqc_opc_query_port_ets_config,
3154 cmd_details);
3155 }
3156
3157 /**
3158 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3159 * @hw: pointer to the hw struct
3160 * @seid: seid of the switching component
3161 * @bw_data: Buffer to hold switching component's BW configuration
3162 * @cmd_details: pointer to command details structure or NULL
3163 **/
3164 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3165 u16 seid,
3166 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3167 struct i40e_asq_cmd_details *cmd_details)
3168 {
3169 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3170 i40e_aqc_opc_query_switching_comp_bw_config,
3171 cmd_details);
3172 }
3173
3174 /**
3175 * i40e_validate_filter_settings
3176 * @hw: pointer to the hardware structure
3177 * @settings: Filter control settings
3178 *
3179 * Check and validate the filter control settings passed.
3180 * The function checks for the valid filter/context sizes being
3181 * passed for FCoE and PE.
3182 *
3183 * Returns 0 if the values passed are valid and within
3184 * range else returns an error.
3185 **/
3186 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3187 struct i40e_filter_control_settings *settings)
3188 {
3189 u32 fcoe_cntx_size, fcoe_filt_size;
3190 u32 pe_cntx_size, pe_filt_size;
3191 u32 fcoe_fmax;
3192 u32 val;
3193
3194 /* Validate FCoE settings passed */
3195 switch (settings->fcoe_filt_num) {
3196 case I40E_HASH_FILTER_SIZE_1K:
3197 case I40E_HASH_FILTER_SIZE_2K:
3198 case I40E_HASH_FILTER_SIZE_4K:
3199 case I40E_HASH_FILTER_SIZE_8K:
3200 case I40E_HASH_FILTER_SIZE_16K:
3201 case I40E_HASH_FILTER_SIZE_32K:
3202 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3203 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3204 break;
3205 default:
3206 return I40E_ERR_PARAM;
3207 }
3208
3209 switch (settings->fcoe_cntx_num) {
3210 case I40E_DMA_CNTX_SIZE_512:
3211 case I40E_DMA_CNTX_SIZE_1K:
3212 case I40E_DMA_CNTX_SIZE_2K:
3213 case I40E_DMA_CNTX_SIZE_4K:
3214 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3215 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3216 break;
3217 default:
3218 return I40E_ERR_PARAM;
3219 }
3220
3221 /* Validate PE settings passed */
3222 switch (settings->pe_filt_num) {
3223 case I40E_HASH_FILTER_SIZE_1K:
3224 case I40E_HASH_FILTER_SIZE_2K:
3225 case I40E_HASH_FILTER_SIZE_4K:
3226 case I40E_HASH_FILTER_SIZE_8K:
3227 case I40E_HASH_FILTER_SIZE_16K:
3228 case I40E_HASH_FILTER_SIZE_32K:
3229 case I40E_HASH_FILTER_SIZE_64K:
3230 case I40E_HASH_FILTER_SIZE_128K:
3231 case I40E_HASH_FILTER_SIZE_256K:
3232 case I40E_HASH_FILTER_SIZE_512K:
3233 case I40E_HASH_FILTER_SIZE_1M:
3234 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3235 pe_filt_size <<= (u32)settings->pe_filt_num;
3236 break;
3237 default:
3238 return I40E_ERR_PARAM;
3239 }
3240
3241 switch (settings->pe_cntx_num) {
3242 case I40E_DMA_CNTX_SIZE_512:
3243 case I40E_DMA_CNTX_SIZE_1K:
3244 case I40E_DMA_CNTX_SIZE_2K:
3245 case I40E_DMA_CNTX_SIZE_4K:
3246 case I40E_DMA_CNTX_SIZE_8K:
3247 case I40E_DMA_CNTX_SIZE_16K:
3248 case I40E_DMA_CNTX_SIZE_32K:
3249 case I40E_DMA_CNTX_SIZE_64K:
3250 case I40E_DMA_CNTX_SIZE_128K:
3251 case I40E_DMA_CNTX_SIZE_256K:
3252 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3253 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3254 break;
3255 default:
3256 return I40E_ERR_PARAM;
3257 }
3258
3259 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3260 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3261 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3262 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3263 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3264 return I40E_ERR_INVALID_SIZE;
3265
3266 return 0;
3267 }
3268
3269 /**
3270 * i40e_set_filter_control
3271 * @hw: pointer to the hardware structure
3272 * @settings: Filter control settings
3273 *
3274 * Set the Queue Filters for PE/FCoE and enable filters required
3275 * for a single PF. It is expected that these settings are programmed
3276 * at the driver initialization time.
3277 **/
3278 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3279 struct i40e_filter_control_settings *settings)
3280 {
3281 i40e_status ret = 0;
3282 u32 hash_lut_size = 0;
3283 u32 val;
3284
3285 if (!settings)
3286 return I40E_ERR_PARAM;
3287
3288 /* Validate the input settings */
3289 ret = i40e_validate_filter_settings(hw, settings);
3290 if (ret)
3291 return ret;
3292
3293 /* Read the PF Queue Filter control register */
3294 val = rd32(hw, I40E_PFQF_CTL_0);
3295
3296 /* Program required PE hash buckets for the PF */
3297 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3298 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3299 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3300 /* Program required PE contexts for the PF */
3301 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3302 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3303 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3304
3305 /* Program required FCoE hash buckets for the PF */
3306 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3307 val |= ((u32)settings->fcoe_filt_num <<
3308 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3309 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3310 /* Program required FCoE DDP contexts for the PF */
3311 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3312 val |= ((u32)settings->fcoe_cntx_num <<
3313 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3314 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3315
3316 /* Program Hash LUT size for the PF */
3317 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3318 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3319 hash_lut_size = 1;
3320 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3321 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3322
3323 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3324 if (settings->enable_fdir)
3325 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3326 if (settings->enable_ethtype)
3327 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3328 if (settings->enable_macvlan)
3329 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3330
3331 wr32(hw, I40E_PFQF_CTL_0, val);
3332
3333 return 0;
3334 }
3335
3336 /**
3337 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3338 * @hw: pointer to the hw struct
3339 * @mac_addr: MAC address to use in the filter
3340 * @ethtype: Ethertype to use in the filter
3341 * @flags: Flags that needs to be applied to the filter
3342 * @vsi_seid: seid of the control VSI
3343 * @queue: VSI queue number to send the packet to
3344 * @is_add: Add control packet filter if True else remove
3345 * @stats: Structure to hold information on control filter counts
3346 * @cmd_details: pointer to command details structure or NULL
3347 *
3348 * This command will Add or Remove control packet filter for a control VSI.
3349 * In return it will update the total number of perfect filter count in
3350 * the stats member.
3351 **/
3352 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3353 u8 *mac_addr, u16 ethtype, u16 flags,
3354 u16 vsi_seid, u16 queue, bool is_add,
3355 struct i40e_control_filter_stats *stats,
3356 struct i40e_asq_cmd_details *cmd_details)
3357 {
3358 struct i40e_aq_desc desc;
3359 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3360 (struct i40e_aqc_add_remove_control_packet_filter *)
3361 &desc.params.raw;
3362 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3363 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3364 &desc.params.raw;
3365 i40e_status status;
3366
3367 if (vsi_seid == 0)
3368 return I40E_ERR_PARAM;
3369
3370 if (is_add) {
3371 i40e_fill_default_direct_cmd_desc(&desc,
3372 i40e_aqc_opc_add_control_packet_filter);
3373 cmd->queue = cpu_to_le16(queue);
3374 } else {
3375 i40e_fill_default_direct_cmd_desc(&desc,
3376 i40e_aqc_opc_remove_control_packet_filter);
3377 }
3378
3379 if (mac_addr)
3380 memcpy(cmd->mac, mac_addr, ETH_ALEN);
3381
3382 cmd->etype = cpu_to_le16(ethtype);
3383 cmd->flags = cpu_to_le16(flags);
3384 cmd->seid = cpu_to_le16(vsi_seid);
3385
3386 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3387
3388 if (!status && stats) {
3389 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3390 stats->etype_used = le16_to_cpu(resp->etype_used);
3391 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3392 stats->etype_free = le16_to_cpu(resp->etype_free);
3393 }
3394
3395 return status;
3396 }
3397
3398 /**
3399 * i40e_aq_alternate_read
3400 * @hw: pointer to the hardware structure
3401 * @reg_addr0: address of first dword to be read
3402 * @reg_val0: pointer for data read from 'reg_addr0'
3403 * @reg_addr1: address of second dword to be read
3404 * @reg_val1: pointer for data read from 'reg_addr1'
3405 *
3406 * Read one or two dwords from alternate structure. Fields are indicated
3407 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
3408 * is not passed then only register at 'reg_addr0' is read.
3409 *
3410 **/
3411 i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
3412 u32 reg_addr0, u32 *reg_val0,
3413 u32 reg_addr1, u32 *reg_val1)
3414 {
3415 struct i40e_aq_desc desc;
3416 struct i40e_aqc_alternate_write *cmd_resp =
3417 (struct i40e_aqc_alternate_write *)&desc.params.raw;
3418 i40e_status status;
3419
3420 if (!reg_val0)
3421 return I40E_ERR_PARAM;
3422
3423 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
3424 cmd_resp->address0 = cpu_to_le32(reg_addr0);
3425 cmd_resp->address1 = cpu_to_le32(reg_addr1);
3426
3427 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3428
3429 if (!status) {
3430 *reg_val0 = le32_to_cpu(cmd_resp->data0);
3431
3432 if (reg_val1)
3433 *reg_val1 = le32_to_cpu(cmd_resp->data1);
3434 }
3435
3436 return status;
3437 }
3438
3439 /**
3440 * i40e_aq_resume_port_tx
3441 * @hw: pointer to the hardware structure
3442 * @cmd_details: pointer to command details structure or NULL
3443 *
3444 * Resume port's Tx traffic
3445 **/
3446 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
3447 struct i40e_asq_cmd_details *cmd_details)
3448 {
3449 struct i40e_aq_desc desc;
3450 i40e_status status;
3451
3452 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
3453
3454 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3455
3456 return status;
3457 }
3458
3459 /**
3460 * i40e_set_pci_config_data - store PCI bus info
3461 * @hw: pointer to hardware structure
3462 * @link_status: the link status word from PCI config space
3463 *
3464 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3465 **/
3466 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
3467 {
3468 hw->bus.type = i40e_bus_type_pci_express;
3469
3470 switch (link_status & PCI_EXP_LNKSTA_NLW) {
3471 case PCI_EXP_LNKSTA_NLW_X1:
3472 hw->bus.width = i40e_bus_width_pcie_x1;
3473 break;
3474 case PCI_EXP_LNKSTA_NLW_X2:
3475 hw->bus.width = i40e_bus_width_pcie_x2;
3476 break;
3477 case PCI_EXP_LNKSTA_NLW_X4:
3478 hw->bus.width = i40e_bus_width_pcie_x4;
3479 break;
3480 case PCI_EXP_LNKSTA_NLW_X8:
3481 hw->bus.width = i40e_bus_width_pcie_x8;
3482 break;
3483 default:
3484 hw->bus.width = i40e_bus_width_unknown;
3485 break;
3486 }
3487
3488 switch (link_status & PCI_EXP_LNKSTA_CLS) {
3489 case PCI_EXP_LNKSTA_CLS_2_5GB:
3490 hw->bus.speed = i40e_bus_speed_2500;
3491 break;
3492 case PCI_EXP_LNKSTA_CLS_5_0GB:
3493 hw->bus.speed = i40e_bus_speed_5000;
3494 break;
3495 case PCI_EXP_LNKSTA_CLS_8_0GB:
3496 hw->bus.speed = i40e_bus_speed_8000;
3497 break;
3498 default:
3499 hw->bus.speed = i40e_bus_speed_unknown;
3500 break;
3501 }
3502 }
3503
3504 /**
3505 * i40e_read_bw_from_alt_ram
3506 * @hw: pointer to the hardware structure
3507 * @max_bw: pointer for max_bw read
3508 * @min_bw: pointer for min_bw read
3509 * @min_valid: pointer for bool that is true if min_bw is a valid value
3510 * @max_valid: pointer for bool that is true if max_bw is a valid value
3511 *
3512 * Read bw from the alternate ram for the given pf
3513 **/
3514 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
3515 u32 *max_bw, u32 *min_bw,
3516 bool *min_valid, bool *max_valid)
3517 {
3518 i40e_status status;
3519 u32 max_bw_addr, min_bw_addr;
3520
3521 /* Calculate the address of the min/max bw registers */
3522 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
3523 I40E_ALT_STRUCT_MAX_BW_OFFSET +
3524 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
3525 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
3526 I40E_ALT_STRUCT_MIN_BW_OFFSET +
3527 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
3528
3529 /* Read the bandwidths from alt ram */
3530 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
3531 min_bw_addr, min_bw);
3532
3533 if (*min_bw & I40E_ALT_BW_VALID_MASK)
3534 *min_valid = true;
3535 else
3536 *min_valid = false;
3537
3538 if (*max_bw & I40E_ALT_BW_VALID_MASK)
3539 *max_valid = true;
3540 else
3541 *max_valid = false;
3542
3543 return status;
3544 }
3545
3546 /**
3547 * i40e_aq_configure_partition_bw
3548 * @hw: pointer to the hardware structure
3549 * @bw_data: Buffer holding valid pfs and bw limits
3550 * @cmd_details: pointer to command details
3551 *
3552 * Configure partitions guaranteed/max bw
3553 **/
3554 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
3555 struct i40e_aqc_configure_partition_bw_data *bw_data,
3556 struct i40e_asq_cmd_details *cmd_details)
3557 {
3558 i40e_status status;
3559 struct i40e_aq_desc desc;
3560 u16 bwd_size = sizeof(*bw_data);
3561
3562 i40e_fill_default_direct_cmd_desc(&desc,
3563 i40e_aqc_opc_configure_partition_bw);
3564
3565 /* Indirect command */
3566 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3567 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3568
3569 if (bwd_size > I40E_AQ_LARGE_BUF)
3570 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3571
3572 desc.datalen = cpu_to_le16(bwd_size);
3573
3574 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
3575 cmd_details);
3576
3577 return status;
3578 }
Linux kernel - Deliverables
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