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MAINTAINERS: Add phy-miphy28lp.c and phy-miphy365x.c to ARCH/STI architecture
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
31
32 /**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40 {
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
45 case I40E_DEV_ID_SFP_XL710:
46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_A:
48 case I40E_DEV_ID_KX_B:
49 case I40E_DEV_ID_KX_C:
50 case I40E_DEV_ID_QSFP_A:
51 case I40E_DEV_ID_QSFP_B:
52 case I40E_DEV_ID_QSFP_C:
53 case I40E_DEV_ID_10G_BASE_T:
54 hw->mac.type = I40E_MAC_XL710;
55 break;
56 case I40E_DEV_ID_VF:
57 case I40E_DEV_ID_VF_HV:
58 hw->mac.type = I40E_MAC_VF;
59 break;
60 default:
61 hw->mac.type = I40E_MAC_GENERIC;
62 break;
63 }
64 } else {
65 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
66 }
67
68 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
69 hw->mac.type, status);
70 return status;
71 }
72
73 /**
74 * i40e_debug_aq
75 * @hw: debug mask related to admin queue
76 * @mask: debug mask
77 * @desc: pointer to admin queue descriptor
78 * @buffer: pointer to command buffer
79 * @buf_len: max length of buffer
80 *
81 * Dumps debug log about adminq command with descriptor contents.
82 **/
83 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
84 void *buffer, u16 buf_len)
85 {
86 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
87 u16 len = le16_to_cpu(aq_desc->datalen);
88 u8 *aq_buffer = (u8 *)buffer;
89 u32 data[4];
90 u32 i = 0;
91
92 if ((!(mask & hw->debug_mask)) || (desc == NULL))
93 return;
94
95 i40e_debug(hw, mask,
96 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
97 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
98 aq_desc->retval);
99 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
100 aq_desc->cookie_high, aq_desc->cookie_low);
101 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
102 aq_desc->params.internal.param0,
103 aq_desc->params.internal.param1);
104 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
105 aq_desc->params.external.addr_high,
106 aq_desc->params.external.addr_low);
107
108 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
109 memset(data, 0, sizeof(data));
110 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
111 if (buf_len < len)
112 len = buf_len;
113 for (i = 0; i < len; i++) {
114 data[((i % 16) / 4)] |=
115 ((u32)aq_buffer[i]) << (8 * (i % 4));
116 if ((i % 16) == 15) {
117 i40e_debug(hw, mask,
118 "\t0x%04X %08X %08X %08X %08X\n",
119 i - 15, data[0], data[1], data[2],
120 data[3]);
121 memset(data, 0, sizeof(data));
122 }
123 }
124 if ((i % 16) != 0)
125 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
126 i - (i % 16), data[0], data[1], data[2],
127 data[3]);
128 }
129 }
130
131 /**
132 * i40e_check_asq_alive
133 * @hw: pointer to the hw struct
134 *
135 * Returns true if Queue is enabled else false.
136 **/
137 bool i40e_check_asq_alive(struct i40e_hw *hw)
138 {
139 if (hw->aq.asq.len)
140 return !!(rd32(hw, hw->aq.asq.len) &
141 I40E_PF_ATQLEN_ATQENABLE_MASK);
142 else
143 return false;
144 }
145
146 /**
147 * i40e_aq_queue_shutdown
148 * @hw: pointer to the hw struct
149 * @unloading: is the driver unloading itself
150 *
151 * Tell the Firmware that we're shutting down the AdminQ and whether
152 * or not the driver is unloading as well.
153 **/
154 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
155 bool unloading)
156 {
157 struct i40e_aq_desc desc;
158 struct i40e_aqc_queue_shutdown *cmd =
159 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
160 i40e_status status;
161
162 i40e_fill_default_direct_cmd_desc(&desc,
163 i40e_aqc_opc_queue_shutdown);
164
165 if (unloading)
166 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
167 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
168
169 return status;
170 }
171
172 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
173 * hardware to a bit-field that can be used by SW to more easily determine the
174 * packet type.
175 *
176 * Macros are used to shorten the table lines and make this table human
177 * readable.
178 *
179 * We store the PTYPE in the top byte of the bit field - this is just so that
180 * we can check that the table doesn't have a row missing, as the index into
181 * the table should be the PTYPE.
182 *
183 * Typical work flow:
184 *
185 * IF NOT i40e_ptype_lookup[ptype].known
186 * THEN
187 * Packet is unknown
188 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
189 * Use the rest of the fields to look at the tunnels, inner protocols, etc
190 * ELSE
191 * Use the enum i40e_rx_l2_ptype to decode the packet type
192 * ENDIF
193 */
194
195 /* macro to make the table lines short */
196 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
197 { PTYPE, \
198 1, \
199 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
200 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
201 I40E_RX_PTYPE_##OUTER_FRAG, \
202 I40E_RX_PTYPE_TUNNEL_##T, \
203 I40E_RX_PTYPE_TUNNEL_END_##TE, \
204 I40E_RX_PTYPE_##TEF, \
205 I40E_RX_PTYPE_INNER_PROT_##I, \
206 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
207
208 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
209 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
210
211 /* shorter macros makes the table fit but are terse */
212 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
213 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
214 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
215
216 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
217 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
218 /* L2 Packet types */
219 I40E_PTT_UNUSED_ENTRY(0),
220 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
221 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
222 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
223 I40E_PTT_UNUSED_ENTRY(4),
224 I40E_PTT_UNUSED_ENTRY(5),
225 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
226 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
227 I40E_PTT_UNUSED_ENTRY(8),
228 I40E_PTT_UNUSED_ENTRY(9),
229 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
230 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
231 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
232 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
233 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
234 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
235 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
236 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
237 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
238 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
239 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
240 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
241
242 /* Non Tunneled IPv4 */
243 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
244 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
245 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
246 I40E_PTT_UNUSED_ENTRY(25),
247 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
248 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
249 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
250
251 /* IPv4 --> IPv4 */
252 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
253 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
254 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
255 I40E_PTT_UNUSED_ENTRY(32),
256 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
257 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
258 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
259
260 /* IPv4 --> IPv6 */
261 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
262 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
263 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
264 I40E_PTT_UNUSED_ENTRY(39),
265 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
266 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
267 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
268
269 /* IPv4 --> GRE/NAT */
270 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
271
272 /* IPv4 --> GRE/NAT --> IPv4 */
273 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
274 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
275 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
276 I40E_PTT_UNUSED_ENTRY(47),
277 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
278 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
279 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
280
281 /* IPv4 --> GRE/NAT --> IPv6 */
282 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
283 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
284 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
285 I40E_PTT_UNUSED_ENTRY(54),
286 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
287 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
288 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
289
290 /* IPv4 --> GRE/NAT --> MAC */
291 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
292
293 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
294 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
295 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
296 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
297 I40E_PTT_UNUSED_ENTRY(62),
298 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
299 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
300 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
301
302 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
303 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
304 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
305 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
306 I40E_PTT_UNUSED_ENTRY(69),
307 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
308 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
309 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
310
311 /* IPv4 --> GRE/NAT --> MAC/VLAN */
312 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
313
314 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
315 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
316 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
317 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
318 I40E_PTT_UNUSED_ENTRY(77),
319 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
320 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
321 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
322
323 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
324 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
325 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
326 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
327 I40E_PTT_UNUSED_ENTRY(84),
328 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
329 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
330 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
331
332 /* Non Tunneled IPv6 */
333 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
334 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
335 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
336 I40E_PTT_UNUSED_ENTRY(91),
337 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
338 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
339 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
340
341 /* IPv6 --> IPv4 */
342 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
343 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
344 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
345 I40E_PTT_UNUSED_ENTRY(98),
346 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
347 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
348 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
349
350 /* IPv6 --> IPv6 */
351 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
352 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
353 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
354 I40E_PTT_UNUSED_ENTRY(105),
355 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
356 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
357 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
358
359 /* IPv6 --> GRE/NAT */
360 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
361
362 /* IPv6 --> GRE/NAT -> IPv4 */
363 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
364 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
365 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
366 I40E_PTT_UNUSED_ENTRY(113),
367 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
368 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
369 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
370
371 /* IPv6 --> GRE/NAT -> IPv6 */
372 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
373 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
374 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
375 I40E_PTT_UNUSED_ENTRY(120),
376 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
377 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
378 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
379
380 /* IPv6 --> GRE/NAT -> MAC */
381 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
382
383 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
384 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
385 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
386 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
387 I40E_PTT_UNUSED_ENTRY(128),
388 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
389 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
390 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
391
392 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
393 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
394 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
395 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
396 I40E_PTT_UNUSED_ENTRY(135),
397 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
398 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
399 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
400
401 /* IPv6 --> GRE/NAT -> MAC/VLAN */
402 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
403
404 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
405 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
406 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
407 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
408 I40E_PTT_UNUSED_ENTRY(143),
409 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
410 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
411 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
412
413 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
414 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
415 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
416 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
417 I40E_PTT_UNUSED_ENTRY(150),
418 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
419 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
420 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
421
422 /* unused entries */
423 I40E_PTT_UNUSED_ENTRY(154),
424 I40E_PTT_UNUSED_ENTRY(155),
425 I40E_PTT_UNUSED_ENTRY(156),
426 I40E_PTT_UNUSED_ENTRY(157),
427 I40E_PTT_UNUSED_ENTRY(158),
428 I40E_PTT_UNUSED_ENTRY(159),
429
430 I40E_PTT_UNUSED_ENTRY(160),
431 I40E_PTT_UNUSED_ENTRY(161),
432 I40E_PTT_UNUSED_ENTRY(162),
433 I40E_PTT_UNUSED_ENTRY(163),
434 I40E_PTT_UNUSED_ENTRY(164),
435 I40E_PTT_UNUSED_ENTRY(165),
436 I40E_PTT_UNUSED_ENTRY(166),
437 I40E_PTT_UNUSED_ENTRY(167),
438 I40E_PTT_UNUSED_ENTRY(168),
439 I40E_PTT_UNUSED_ENTRY(169),
440
441 I40E_PTT_UNUSED_ENTRY(170),
442 I40E_PTT_UNUSED_ENTRY(171),
443 I40E_PTT_UNUSED_ENTRY(172),
444 I40E_PTT_UNUSED_ENTRY(173),
445 I40E_PTT_UNUSED_ENTRY(174),
446 I40E_PTT_UNUSED_ENTRY(175),
447 I40E_PTT_UNUSED_ENTRY(176),
448 I40E_PTT_UNUSED_ENTRY(177),
449 I40E_PTT_UNUSED_ENTRY(178),
450 I40E_PTT_UNUSED_ENTRY(179),
451
452 I40E_PTT_UNUSED_ENTRY(180),
453 I40E_PTT_UNUSED_ENTRY(181),
454 I40E_PTT_UNUSED_ENTRY(182),
455 I40E_PTT_UNUSED_ENTRY(183),
456 I40E_PTT_UNUSED_ENTRY(184),
457 I40E_PTT_UNUSED_ENTRY(185),
458 I40E_PTT_UNUSED_ENTRY(186),
459 I40E_PTT_UNUSED_ENTRY(187),
460 I40E_PTT_UNUSED_ENTRY(188),
461 I40E_PTT_UNUSED_ENTRY(189),
462
463 I40E_PTT_UNUSED_ENTRY(190),
464 I40E_PTT_UNUSED_ENTRY(191),
465 I40E_PTT_UNUSED_ENTRY(192),
466 I40E_PTT_UNUSED_ENTRY(193),
467 I40E_PTT_UNUSED_ENTRY(194),
468 I40E_PTT_UNUSED_ENTRY(195),
469 I40E_PTT_UNUSED_ENTRY(196),
470 I40E_PTT_UNUSED_ENTRY(197),
471 I40E_PTT_UNUSED_ENTRY(198),
472 I40E_PTT_UNUSED_ENTRY(199),
473
474 I40E_PTT_UNUSED_ENTRY(200),
475 I40E_PTT_UNUSED_ENTRY(201),
476 I40E_PTT_UNUSED_ENTRY(202),
477 I40E_PTT_UNUSED_ENTRY(203),
478 I40E_PTT_UNUSED_ENTRY(204),
479 I40E_PTT_UNUSED_ENTRY(205),
480 I40E_PTT_UNUSED_ENTRY(206),
481 I40E_PTT_UNUSED_ENTRY(207),
482 I40E_PTT_UNUSED_ENTRY(208),
483 I40E_PTT_UNUSED_ENTRY(209),
484
485 I40E_PTT_UNUSED_ENTRY(210),
486 I40E_PTT_UNUSED_ENTRY(211),
487 I40E_PTT_UNUSED_ENTRY(212),
488 I40E_PTT_UNUSED_ENTRY(213),
489 I40E_PTT_UNUSED_ENTRY(214),
490 I40E_PTT_UNUSED_ENTRY(215),
491 I40E_PTT_UNUSED_ENTRY(216),
492 I40E_PTT_UNUSED_ENTRY(217),
493 I40E_PTT_UNUSED_ENTRY(218),
494 I40E_PTT_UNUSED_ENTRY(219),
495
496 I40E_PTT_UNUSED_ENTRY(220),
497 I40E_PTT_UNUSED_ENTRY(221),
498 I40E_PTT_UNUSED_ENTRY(222),
499 I40E_PTT_UNUSED_ENTRY(223),
500 I40E_PTT_UNUSED_ENTRY(224),
501 I40E_PTT_UNUSED_ENTRY(225),
502 I40E_PTT_UNUSED_ENTRY(226),
503 I40E_PTT_UNUSED_ENTRY(227),
504 I40E_PTT_UNUSED_ENTRY(228),
505 I40E_PTT_UNUSED_ENTRY(229),
506
507 I40E_PTT_UNUSED_ENTRY(230),
508 I40E_PTT_UNUSED_ENTRY(231),
509 I40E_PTT_UNUSED_ENTRY(232),
510 I40E_PTT_UNUSED_ENTRY(233),
511 I40E_PTT_UNUSED_ENTRY(234),
512 I40E_PTT_UNUSED_ENTRY(235),
513 I40E_PTT_UNUSED_ENTRY(236),
514 I40E_PTT_UNUSED_ENTRY(237),
515 I40E_PTT_UNUSED_ENTRY(238),
516 I40E_PTT_UNUSED_ENTRY(239),
517
518 I40E_PTT_UNUSED_ENTRY(240),
519 I40E_PTT_UNUSED_ENTRY(241),
520 I40E_PTT_UNUSED_ENTRY(242),
521 I40E_PTT_UNUSED_ENTRY(243),
522 I40E_PTT_UNUSED_ENTRY(244),
523 I40E_PTT_UNUSED_ENTRY(245),
524 I40E_PTT_UNUSED_ENTRY(246),
525 I40E_PTT_UNUSED_ENTRY(247),
526 I40E_PTT_UNUSED_ENTRY(248),
527 I40E_PTT_UNUSED_ENTRY(249),
528
529 I40E_PTT_UNUSED_ENTRY(250),
530 I40E_PTT_UNUSED_ENTRY(251),
531 I40E_PTT_UNUSED_ENTRY(252),
532 I40E_PTT_UNUSED_ENTRY(253),
533 I40E_PTT_UNUSED_ENTRY(254),
534 I40E_PTT_UNUSED_ENTRY(255)
535 };
536
537
538 /**
539 * i40e_init_shared_code - Initialize the shared code
540 * @hw: pointer to hardware structure
541 *
542 * This assigns the MAC type and PHY code and inits the NVM.
543 * Does not touch the hardware. This function must be called prior to any
544 * other function in the shared code. The i40e_hw structure should be
545 * memset to 0 prior to calling this function. The following fields in
546 * hw structure should be filled in prior to calling this function:
547 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
548 * subsystem_vendor_id, and revision_id
549 **/
550 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
551 {
552 i40e_status status = 0;
553 u32 port, ari, func_rid;
554
555 i40e_set_mac_type(hw);
556
557 switch (hw->mac.type) {
558 case I40E_MAC_XL710:
559 break;
560 default:
561 return I40E_ERR_DEVICE_NOT_SUPPORTED;
562 }
563
564 hw->phy.get_link_info = true;
565
566 /* Determine port number and PF number*/
567 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
568 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
569 hw->port = (u8)port;
570 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
571 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
572 func_rid = rd32(hw, I40E_PF_FUNC_RID);
573 if (ari)
574 hw->pf_id = (u8)(func_rid & 0xff);
575 else
576 hw->pf_id = (u8)(func_rid & 0x7);
577
578 status = i40e_init_nvm(hw);
579 return status;
580 }
581
582 /**
583 * i40e_aq_mac_address_read - Retrieve the MAC addresses
584 * @hw: pointer to the hw struct
585 * @flags: a return indicator of what addresses were added to the addr store
586 * @addrs: the requestor's mac addr store
587 * @cmd_details: pointer to command details structure or NULL
588 **/
589 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
590 u16 *flags,
591 struct i40e_aqc_mac_address_read_data *addrs,
592 struct i40e_asq_cmd_details *cmd_details)
593 {
594 struct i40e_aq_desc desc;
595 struct i40e_aqc_mac_address_read *cmd_data =
596 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
597 i40e_status status;
598
599 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
600 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
601
602 status = i40e_asq_send_command(hw, &desc, addrs,
603 sizeof(*addrs), cmd_details);
604 *flags = le16_to_cpu(cmd_data->command_flags);
605
606 return status;
607 }
608
609 /**
610 * i40e_aq_mac_address_write - Change the MAC addresses
611 * @hw: pointer to the hw struct
612 * @flags: indicates which MAC to be written
613 * @mac_addr: address to write
614 * @cmd_details: pointer to command details structure or NULL
615 **/
616 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
617 u16 flags, u8 *mac_addr,
618 struct i40e_asq_cmd_details *cmd_details)
619 {
620 struct i40e_aq_desc desc;
621 struct i40e_aqc_mac_address_write *cmd_data =
622 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
623 i40e_status status;
624
625 i40e_fill_default_direct_cmd_desc(&desc,
626 i40e_aqc_opc_mac_address_write);
627 cmd_data->command_flags = cpu_to_le16(flags);
628 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
629 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
630 ((u32)mac_addr[3] << 16) |
631 ((u32)mac_addr[4] << 8) |
632 mac_addr[5]);
633
634 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
635
636 return status;
637 }
638
639 /**
640 * i40e_get_mac_addr - get MAC address
641 * @hw: pointer to the HW structure
642 * @mac_addr: pointer to MAC address
643 *
644 * Reads the adapter's MAC address from register
645 **/
646 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
647 {
648 struct i40e_aqc_mac_address_read_data addrs;
649 i40e_status status;
650 u16 flags = 0;
651
652 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
653
654 if (flags & I40E_AQC_LAN_ADDR_VALID)
655 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
656
657 return status;
658 }
659
660 /**
661 * i40e_get_port_mac_addr - get Port MAC address
662 * @hw: pointer to the HW structure
663 * @mac_addr: pointer to Port MAC address
664 *
665 * Reads the adapter's Port MAC address
666 **/
667 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
668 {
669 struct i40e_aqc_mac_address_read_data addrs;
670 i40e_status status;
671 u16 flags = 0;
672
673 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
674 if (status)
675 return status;
676
677 if (flags & I40E_AQC_PORT_ADDR_VALID)
678 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
679 else
680 status = I40E_ERR_INVALID_MAC_ADDR;
681
682 return status;
683 }
684
685 /**
686 * i40e_pre_tx_queue_cfg - pre tx queue configure
687 * @hw: pointer to the HW structure
688 * @queue: target pf queue index
689 * @enable: state change request
690 *
691 * Handles hw requirement to indicate intention to enable
692 * or disable target queue.
693 **/
694 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
695 {
696 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
697 u32 reg_block = 0;
698 u32 reg_val;
699
700 if (abs_queue_idx >= 128) {
701 reg_block = abs_queue_idx / 128;
702 abs_queue_idx %= 128;
703 }
704
705 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
706 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
707 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
708
709 if (enable)
710 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
711 else
712 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
713
714 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
715 }
716 #ifdef I40E_FCOE
717
718 /**
719 * i40e_get_san_mac_addr - get SAN MAC address
720 * @hw: pointer to the HW structure
721 * @mac_addr: pointer to SAN MAC address
722 *
723 * Reads the adapter's SAN MAC address from NVM
724 **/
725 i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
726 {
727 struct i40e_aqc_mac_address_read_data addrs;
728 i40e_status status;
729 u16 flags = 0;
730
731 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
732 if (status)
733 return status;
734
735 if (flags & I40E_AQC_SAN_ADDR_VALID)
736 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac));
737 else
738 status = I40E_ERR_INVALID_MAC_ADDR;
739
740 return status;
741 }
742 #endif
743
744 /**
745 * i40e_read_pba_string - Reads part number string from EEPROM
746 * @hw: pointer to hardware structure
747 * @pba_num: stores the part number string from the EEPROM
748 * @pba_num_size: part number string buffer length
749 *
750 * Reads the part number string from the EEPROM.
751 **/
752 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
753 u32 pba_num_size)
754 {
755 i40e_status status = 0;
756 u16 pba_word = 0;
757 u16 pba_size = 0;
758 u16 pba_ptr = 0;
759 u16 i = 0;
760
761 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
762 if (status || (pba_word != 0xFAFA)) {
763 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
764 return status;
765 }
766
767 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
768 if (status) {
769 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
770 return status;
771 }
772
773 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
774 if (status) {
775 hw_dbg(hw, "Failed to read PBA Block size.\n");
776 return status;
777 }
778
779 /* Subtract one to get PBA word count (PBA Size word is included in
780 * total size)
781 */
782 pba_size--;
783 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
784 hw_dbg(hw, "Buffer to small for PBA data.\n");
785 return I40E_ERR_PARAM;
786 }
787
788 for (i = 0; i < pba_size; i++) {
789 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
790 if (status) {
791 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
792 return status;
793 }
794
795 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
796 pba_num[(i * 2) + 1] = pba_word & 0xFF;
797 }
798 pba_num[(pba_size * 2)] = '\0';
799
800 return status;
801 }
802
803 /**
804 * i40e_get_media_type - Gets media type
805 * @hw: pointer to the hardware structure
806 **/
807 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
808 {
809 enum i40e_media_type media;
810
811 switch (hw->phy.link_info.phy_type) {
812 case I40E_PHY_TYPE_10GBASE_SR:
813 case I40E_PHY_TYPE_10GBASE_LR:
814 case I40E_PHY_TYPE_1000BASE_SX:
815 case I40E_PHY_TYPE_1000BASE_LX:
816 case I40E_PHY_TYPE_40GBASE_SR4:
817 case I40E_PHY_TYPE_40GBASE_LR4:
818 media = I40E_MEDIA_TYPE_FIBER;
819 break;
820 case I40E_PHY_TYPE_100BASE_TX:
821 case I40E_PHY_TYPE_1000BASE_T:
822 case I40E_PHY_TYPE_10GBASE_T:
823 media = I40E_MEDIA_TYPE_BASET;
824 break;
825 case I40E_PHY_TYPE_10GBASE_CR1_CU:
826 case I40E_PHY_TYPE_40GBASE_CR4_CU:
827 case I40E_PHY_TYPE_10GBASE_CR1:
828 case I40E_PHY_TYPE_40GBASE_CR4:
829 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
830 media = I40E_MEDIA_TYPE_DA;
831 break;
832 case I40E_PHY_TYPE_1000BASE_KX:
833 case I40E_PHY_TYPE_10GBASE_KX4:
834 case I40E_PHY_TYPE_10GBASE_KR:
835 case I40E_PHY_TYPE_40GBASE_KR4:
836 media = I40E_MEDIA_TYPE_BACKPLANE;
837 break;
838 case I40E_PHY_TYPE_SGMII:
839 case I40E_PHY_TYPE_XAUI:
840 case I40E_PHY_TYPE_XFI:
841 case I40E_PHY_TYPE_XLAUI:
842 case I40E_PHY_TYPE_XLPPI:
843 default:
844 media = I40E_MEDIA_TYPE_UNKNOWN;
845 break;
846 }
847
848 return media;
849 }
850
851 #define I40E_PF_RESET_WAIT_COUNT_A0 200
852 #define I40E_PF_RESET_WAIT_COUNT 110
853 /**
854 * i40e_pf_reset - Reset the PF
855 * @hw: pointer to the hardware structure
856 *
857 * Assuming someone else has triggered a global reset,
858 * assure the global reset is complete and then reset the PF
859 **/
860 i40e_status i40e_pf_reset(struct i40e_hw *hw)
861 {
862 u32 cnt = 0;
863 u32 cnt1 = 0;
864 u32 reg = 0;
865 u32 grst_del;
866
867 /* Poll for Global Reset steady state in case of recent GRST.
868 * The grst delay value is in 100ms units, and we'll wait a
869 * couple counts longer to be sure we don't just miss the end.
870 */
871 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
872 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
873 for (cnt = 0; cnt < grst_del + 2; cnt++) {
874 reg = rd32(hw, I40E_GLGEN_RSTAT);
875 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
876 break;
877 msleep(100);
878 }
879 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
880 hw_dbg(hw, "Global reset polling failed to complete.\n");
881 return I40E_ERR_RESET_FAILED;
882 }
883
884 /* Now Wait for the FW to be ready */
885 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
886 reg = rd32(hw, I40E_GLNVM_ULD);
887 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
888 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
889 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
890 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
891 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
892 break;
893 }
894 usleep_range(10000, 20000);
895 }
896 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
897 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
898 hw_dbg(hw, "wait for FW Reset complete timedout\n");
899 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
900 return I40E_ERR_RESET_FAILED;
901 }
902
903 /* If there was a Global Reset in progress when we got here,
904 * we don't need to do the PF Reset
905 */
906 if (!cnt) {
907 if (hw->revision_id == 0)
908 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
909 else
910 cnt = I40E_PF_RESET_WAIT_COUNT;
911 reg = rd32(hw, I40E_PFGEN_CTRL);
912 wr32(hw, I40E_PFGEN_CTRL,
913 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
914 for (; cnt; cnt--) {
915 reg = rd32(hw, I40E_PFGEN_CTRL);
916 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
917 break;
918 usleep_range(1000, 2000);
919 }
920 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
921 hw_dbg(hw, "PF reset polling failed to complete.\n");
922 return I40E_ERR_RESET_FAILED;
923 }
924 }
925
926 i40e_clear_pxe_mode(hw);
927
928 return 0;
929 }
930
931 /**
932 * i40e_clear_hw - clear out any left over hw state
933 * @hw: pointer to the hw struct
934 *
935 * Clear queues and interrupts, typically called at init time,
936 * but after the capabilities have been found so we know how many
937 * queues and msix vectors have been allocated.
938 **/
939 void i40e_clear_hw(struct i40e_hw *hw)
940 {
941 u32 num_queues, base_queue;
942 u32 num_pf_int;
943 u32 num_vf_int;
944 u32 num_vfs;
945 u32 i, j;
946 u32 val;
947 u32 eol = 0x7ff;
948
949 /* get number of interrupts, queues, and vfs */
950 val = rd32(hw, I40E_GLPCI_CNF2);
951 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
952 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
953 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
954 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
955
956 val = rd32(hw, I40E_PFLAN_QALLOC);
957 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
958 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
959 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
960 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
961 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
962 num_queues = (j - base_queue) + 1;
963 else
964 num_queues = 0;
965
966 val = rd32(hw, I40E_PF_VT_PFALLOC);
967 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
968 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
969 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
970 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
971 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
972 num_vfs = (j - i) + 1;
973 else
974 num_vfs = 0;
975
976 /* stop all the interrupts */
977 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
978 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
979 for (i = 0; i < num_pf_int - 2; i++)
980 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
981
982 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
983 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
984 wr32(hw, I40E_PFINT_LNKLST0, val);
985 for (i = 0; i < num_pf_int - 2; i++)
986 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
987 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
988 for (i = 0; i < num_vfs; i++)
989 wr32(hw, I40E_VPINT_LNKLST0(i), val);
990 for (i = 0; i < num_vf_int - 2; i++)
991 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
992
993 /* warn the HW of the coming Tx disables */
994 for (i = 0; i < num_queues; i++) {
995 u32 abs_queue_idx = base_queue + i;
996 u32 reg_block = 0;
997
998 if (abs_queue_idx >= 128) {
999 reg_block = abs_queue_idx / 128;
1000 abs_queue_idx %= 128;
1001 }
1002
1003 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1004 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1005 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1006 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1007
1008 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1009 }
1010 udelay(400);
1011
1012 /* stop all the queues */
1013 for (i = 0; i < num_queues; i++) {
1014 wr32(hw, I40E_QINT_TQCTL(i), 0);
1015 wr32(hw, I40E_QTX_ENA(i), 0);
1016 wr32(hw, I40E_QINT_RQCTL(i), 0);
1017 wr32(hw, I40E_QRX_ENA(i), 0);
1018 }
1019
1020 /* short wait for all queue disables to settle */
1021 udelay(50);
1022 }
1023
1024 /**
1025 * i40e_clear_pxe_mode - clear pxe operations mode
1026 * @hw: pointer to the hw struct
1027 *
1028 * Make sure all PXE mode settings are cleared, including things
1029 * like descriptor fetch/write-back mode.
1030 **/
1031 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1032 {
1033 u32 reg;
1034
1035 if (i40e_check_asq_alive(hw))
1036 i40e_aq_clear_pxe_mode(hw, NULL);
1037
1038 /* Clear single descriptor fetch/write-back mode */
1039 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1040
1041 if (hw->revision_id == 0) {
1042 /* As a work around clear PXE_MODE instead of setting it */
1043 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1044 } else {
1045 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1046 }
1047 }
1048
1049 /**
1050 * i40e_led_is_mine - helper to find matching led
1051 * @hw: pointer to the hw struct
1052 * @idx: index into GPIO registers
1053 *
1054 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1055 */
1056 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1057 {
1058 u32 gpio_val = 0;
1059 u32 port;
1060
1061 if (!hw->func_caps.led[idx])
1062 return 0;
1063
1064 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1065 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1066 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1067
1068 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1069 * if it is not our port then ignore
1070 */
1071 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1072 (port != hw->port))
1073 return 0;
1074
1075 return gpio_val;
1076 }
1077
1078 #define I40E_LED0 22
1079 #define I40E_LINK_ACTIVITY 0xC
1080
1081 /**
1082 * i40e_led_get - return current on/off mode
1083 * @hw: pointer to the hw struct
1084 *
1085 * The value returned is the 'mode' field as defined in the
1086 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1087 * values are variations of possible behaviors relating to
1088 * blink, link, and wire.
1089 **/
1090 u32 i40e_led_get(struct i40e_hw *hw)
1091 {
1092 u32 mode = 0;
1093 int i;
1094
1095 /* as per the documentation GPIO 22-29 are the LED
1096 * GPIO pins named LED0..LED7
1097 */
1098 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1099 u32 gpio_val = i40e_led_is_mine(hw, i);
1100
1101 if (!gpio_val)
1102 continue;
1103
1104 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1105 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1106 break;
1107 }
1108
1109 return mode;
1110 }
1111
1112 /**
1113 * i40e_led_set - set new on/off mode
1114 * @hw: pointer to the hw struct
1115 * @mode: 0=off, 0xf=on (else see manual for mode details)
1116 * @blink: true if the LED should blink when on, false if steady
1117 *
1118 * if this function is used to turn on the blink it should
1119 * be used to disable the blink when restoring the original state.
1120 **/
1121 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1122 {
1123 int i;
1124
1125 if (mode & 0xfffffff0)
1126 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1127
1128 /* as per the documentation GPIO 22-29 are the LED
1129 * GPIO pins named LED0..LED7
1130 */
1131 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1132 u32 gpio_val = i40e_led_is_mine(hw, i);
1133
1134 if (!gpio_val)
1135 continue;
1136
1137 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1138 /* this & is a bit of paranoia, but serves as a range check */
1139 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1140 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1141
1142 if (mode == I40E_LINK_ACTIVITY)
1143 blink = false;
1144
1145 if (blink)
1146 gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1147 else
1148 gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1149
1150 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1151 break;
1152 }
1153 }
1154
1155 /* Admin command wrappers */
1156
1157 /**
1158 * i40e_aq_get_phy_capabilities
1159 * @hw: pointer to the hw struct
1160 * @abilities: structure for PHY capabilities to be filled
1161 * @qualified_modules: report Qualified Modules
1162 * @report_init: report init capabilities (active are default)
1163 * @cmd_details: pointer to command details structure or NULL
1164 *
1165 * Returns the various PHY abilities supported on the Port.
1166 **/
1167 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1168 bool qualified_modules, bool report_init,
1169 struct i40e_aq_get_phy_abilities_resp *abilities,
1170 struct i40e_asq_cmd_details *cmd_details)
1171 {
1172 struct i40e_aq_desc desc;
1173 i40e_status status;
1174 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1175
1176 if (!abilities)
1177 return I40E_ERR_PARAM;
1178
1179 i40e_fill_default_direct_cmd_desc(&desc,
1180 i40e_aqc_opc_get_phy_abilities);
1181
1182 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1183 if (abilities_size > I40E_AQ_LARGE_BUF)
1184 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1185
1186 if (qualified_modules)
1187 desc.params.external.param0 |=
1188 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1189
1190 if (report_init)
1191 desc.params.external.param0 |=
1192 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1193
1194 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1195 cmd_details);
1196
1197 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1198 status = I40E_ERR_UNKNOWN_PHY;
1199
1200 return status;
1201 }
1202
1203 /**
1204 * i40e_aq_set_phy_config
1205 * @hw: pointer to the hw struct
1206 * @config: structure with PHY configuration to be set
1207 * @cmd_details: pointer to command details structure or NULL
1208 *
1209 * Set the various PHY configuration parameters
1210 * supported on the Port.One or more of the Set PHY config parameters may be
1211 * ignored in an MFP mode as the PF may not have the privilege to set some
1212 * of the PHY Config parameters. This status will be indicated by the
1213 * command response.
1214 **/
1215 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1216 struct i40e_aq_set_phy_config *config,
1217 struct i40e_asq_cmd_details *cmd_details)
1218 {
1219 struct i40e_aq_desc desc;
1220 struct i40e_aq_set_phy_config *cmd =
1221 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1222 enum i40e_status_code status;
1223
1224 if (!config)
1225 return I40E_ERR_PARAM;
1226
1227 i40e_fill_default_direct_cmd_desc(&desc,
1228 i40e_aqc_opc_set_phy_config);
1229
1230 *cmd = *config;
1231
1232 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1233
1234 return status;
1235 }
1236
1237 /**
1238 * i40e_set_fc
1239 * @hw: pointer to the hw struct
1240 *
1241 * Set the requested flow control mode using set_phy_config.
1242 **/
1243 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1244 bool atomic_restart)
1245 {
1246 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1247 struct i40e_aq_get_phy_abilities_resp abilities;
1248 struct i40e_aq_set_phy_config config;
1249 enum i40e_status_code status;
1250 u8 pause_mask = 0x0;
1251
1252 *aq_failures = 0x0;
1253
1254 switch (fc_mode) {
1255 case I40E_FC_FULL:
1256 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1257 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1258 break;
1259 case I40E_FC_RX_PAUSE:
1260 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1261 break;
1262 case I40E_FC_TX_PAUSE:
1263 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1264 break;
1265 default:
1266 break;
1267 }
1268
1269 /* Get the current phy config */
1270 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1271 NULL);
1272 if (status) {
1273 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1274 return status;
1275 }
1276
1277 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1278 /* clear the old pause settings */
1279 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1280 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1281 /* set the new abilities */
1282 config.abilities |= pause_mask;
1283 /* If the abilities have changed, then set the new config */
1284 if (config.abilities != abilities.abilities) {
1285 /* Auto restart link so settings take effect */
1286 if (atomic_restart)
1287 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1288 /* Copy over all the old settings */
1289 config.phy_type = abilities.phy_type;
1290 config.link_speed = abilities.link_speed;
1291 config.eee_capability = abilities.eee_capability;
1292 config.eeer = abilities.eeer_val;
1293 config.low_power_ctrl = abilities.d3_lpan;
1294 status = i40e_aq_set_phy_config(hw, &config, NULL);
1295
1296 if (status)
1297 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1298 }
1299 /* Update the link info */
1300 status = i40e_update_link_info(hw, true);
1301 if (status) {
1302 /* Wait a little bit (on 40G cards it sometimes takes a really
1303 * long time for link to come back from the atomic reset)
1304 * and try once more
1305 */
1306 msleep(1000);
1307 status = i40e_update_link_info(hw, true);
1308 }
1309 if (status)
1310 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1311
1312 return status;
1313 }
1314
1315 /**
1316 * i40e_aq_clear_pxe_mode
1317 * @hw: pointer to the hw struct
1318 * @cmd_details: pointer to command details structure or NULL
1319 *
1320 * Tell the firmware that the driver is taking over from PXE
1321 **/
1322 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1323 struct i40e_asq_cmd_details *cmd_details)
1324 {
1325 i40e_status status;
1326 struct i40e_aq_desc desc;
1327 struct i40e_aqc_clear_pxe *cmd =
1328 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1329
1330 i40e_fill_default_direct_cmd_desc(&desc,
1331 i40e_aqc_opc_clear_pxe_mode);
1332
1333 cmd->rx_cnt = 0x2;
1334
1335 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1336
1337 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1338
1339 return status;
1340 }
1341
1342 /**
1343 * i40e_aq_set_link_restart_an
1344 * @hw: pointer to the hw struct
1345 * @enable_link: if true: enable link, if false: disable link
1346 * @cmd_details: pointer to command details structure or NULL
1347 *
1348 * Sets up the link and restarts the Auto-Negotiation over the link.
1349 **/
1350 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1351 bool enable_link,
1352 struct i40e_asq_cmd_details *cmd_details)
1353 {
1354 struct i40e_aq_desc desc;
1355 struct i40e_aqc_set_link_restart_an *cmd =
1356 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1357 i40e_status status;
1358
1359 i40e_fill_default_direct_cmd_desc(&desc,
1360 i40e_aqc_opc_set_link_restart_an);
1361
1362 cmd->command = I40E_AQ_PHY_RESTART_AN;
1363 if (enable_link)
1364 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1365 else
1366 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1367
1368 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1369
1370 return status;
1371 }
1372
1373 /**
1374 * i40e_aq_get_link_info
1375 * @hw: pointer to the hw struct
1376 * @enable_lse: enable/disable LinkStatusEvent reporting
1377 * @link: pointer to link status structure - optional
1378 * @cmd_details: pointer to command details structure or NULL
1379 *
1380 * Returns the link status of the adapter.
1381 **/
1382 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1383 bool enable_lse, struct i40e_link_status *link,
1384 struct i40e_asq_cmd_details *cmd_details)
1385 {
1386 struct i40e_aq_desc desc;
1387 struct i40e_aqc_get_link_status *resp =
1388 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1389 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1390 i40e_status status;
1391 bool tx_pause, rx_pause;
1392 u16 command_flags;
1393
1394 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1395
1396 if (enable_lse)
1397 command_flags = I40E_AQ_LSE_ENABLE;
1398 else
1399 command_flags = I40E_AQ_LSE_DISABLE;
1400 resp->command_flags = cpu_to_le16(command_flags);
1401
1402 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1403
1404 if (status)
1405 goto aq_get_link_info_exit;
1406
1407 /* save off old link status information */
1408 hw->phy.link_info_old = *hw_link_info;
1409
1410 /* update link status */
1411 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1412 hw->phy.media_type = i40e_get_media_type(hw);
1413 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1414 hw_link_info->link_info = resp->link_info;
1415 hw_link_info->an_info = resp->an_info;
1416 hw_link_info->ext_info = resp->ext_info;
1417 hw_link_info->loopback = resp->loopback;
1418 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1419 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1420
1421 /* update fc info */
1422 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1423 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1424 if (tx_pause & rx_pause)
1425 hw->fc.current_mode = I40E_FC_FULL;
1426 else if (tx_pause)
1427 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1428 else if (rx_pause)
1429 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1430 else
1431 hw->fc.current_mode = I40E_FC_NONE;
1432
1433 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1434 hw_link_info->crc_enable = true;
1435 else
1436 hw_link_info->crc_enable = false;
1437
1438 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1439 hw_link_info->lse_enable = true;
1440 else
1441 hw_link_info->lse_enable = false;
1442
1443 /* save link status information */
1444 if (link)
1445 *link = *hw_link_info;
1446
1447 /* flag cleared so helper functions don't call AQ again */
1448 hw->phy.get_link_info = false;
1449
1450 aq_get_link_info_exit:
1451 return status;
1452 }
1453
1454 /**
1455 * i40e_update_link_info
1456 * @hw: pointer to the hw struct
1457 * @enable_lse: enable/disable LinkStatusEvent reporting
1458 *
1459 * Returns the link status of the adapter
1460 **/
1461 i40e_status i40e_update_link_info(struct i40e_hw *hw, bool enable_lse)
1462 {
1463 struct i40e_aq_get_phy_abilities_resp abilities;
1464 i40e_status status;
1465
1466 status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL);
1467 if (status)
1468 return status;
1469
1470 status = i40e_aq_get_phy_capabilities(hw, false, false,
1471 &abilities, NULL);
1472 if (status)
1473 return status;
1474
1475 if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED)
1476 hw->phy.link_info.an_enabled = true;
1477 else
1478 hw->phy.link_info.an_enabled = false;
1479
1480 return status;
1481 }
1482
1483 /**
1484 * i40e_aq_set_phy_int_mask
1485 * @hw: pointer to the hw struct
1486 * @mask: interrupt mask to be set
1487 * @cmd_details: pointer to command details structure or NULL
1488 *
1489 * Set link interrupt mask.
1490 **/
1491 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1492 u16 mask,
1493 struct i40e_asq_cmd_details *cmd_details)
1494 {
1495 struct i40e_aq_desc desc;
1496 struct i40e_aqc_set_phy_int_mask *cmd =
1497 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1498 i40e_status status;
1499
1500 i40e_fill_default_direct_cmd_desc(&desc,
1501 i40e_aqc_opc_set_phy_int_mask);
1502
1503 cmd->event_mask = cpu_to_le16(mask);
1504
1505 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1506
1507 return status;
1508 }
1509
1510 /**
1511 * i40e_aq_add_vsi
1512 * @hw: pointer to the hw struct
1513 * @vsi_ctx: pointer to a vsi context struct
1514 * @cmd_details: pointer to command details structure or NULL
1515 *
1516 * Add a VSI context to the hardware.
1517 **/
1518 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1519 struct i40e_vsi_context *vsi_ctx,
1520 struct i40e_asq_cmd_details *cmd_details)
1521 {
1522 struct i40e_aq_desc desc;
1523 struct i40e_aqc_add_get_update_vsi *cmd =
1524 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1525 struct i40e_aqc_add_get_update_vsi_completion *resp =
1526 (struct i40e_aqc_add_get_update_vsi_completion *)
1527 &desc.params.raw;
1528 i40e_status status;
1529
1530 i40e_fill_default_direct_cmd_desc(&desc,
1531 i40e_aqc_opc_add_vsi);
1532
1533 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1534 cmd->connection_type = vsi_ctx->connection_type;
1535 cmd->vf_id = vsi_ctx->vf_num;
1536 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1537
1538 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1539
1540 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1541 sizeof(vsi_ctx->info), cmd_details);
1542
1543 if (status)
1544 goto aq_add_vsi_exit;
1545
1546 vsi_ctx->seid = le16_to_cpu(resp->seid);
1547 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1548 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1549 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1550
1551 aq_add_vsi_exit:
1552 return status;
1553 }
1554
1555 /**
1556 * i40e_aq_set_vsi_unicast_promiscuous
1557 * @hw: pointer to the hw struct
1558 * @seid: vsi number
1559 * @set: set unicast promiscuous enable/disable
1560 * @cmd_details: pointer to command details structure or NULL
1561 **/
1562 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1563 u16 seid, bool set,
1564 struct i40e_asq_cmd_details *cmd_details)
1565 {
1566 struct i40e_aq_desc desc;
1567 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1568 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1569 i40e_status status;
1570 u16 flags = 0;
1571
1572 i40e_fill_default_direct_cmd_desc(&desc,
1573 i40e_aqc_opc_set_vsi_promiscuous_modes);
1574
1575 if (set)
1576 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1577
1578 cmd->promiscuous_flags = cpu_to_le16(flags);
1579
1580 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1581
1582 cmd->seid = cpu_to_le16(seid);
1583 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1584
1585 return status;
1586 }
1587
1588 /**
1589 * i40e_aq_set_vsi_multicast_promiscuous
1590 * @hw: pointer to the hw struct
1591 * @seid: vsi number
1592 * @set: set multicast promiscuous enable/disable
1593 * @cmd_details: pointer to command details structure or NULL
1594 **/
1595 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1596 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1597 {
1598 struct i40e_aq_desc desc;
1599 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1600 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1601 i40e_status status;
1602 u16 flags = 0;
1603
1604 i40e_fill_default_direct_cmd_desc(&desc,
1605 i40e_aqc_opc_set_vsi_promiscuous_modes);
1606
1607 if (set)
1608 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1609
1610 cmd->promiscuous_flags = cpu_to_le16(flags);
1611
1612 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1613
1614 cmd->seid = cpu_to_le16(seid);
1615 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1616
1617 return status;
1618 }
1619
1620 /**
1621 * i40e_aq_set_vsi_broadcast
1622 * @hw: pointer to the hw struct
1623 * @seid: vsi number
1624 * @set_filter: true to set filter, false to clear filter
1625 * @cmd_details: pointer to command details structure or NULL
1626 *
1627 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1628 **/
1629 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1630 u16 seid, bool set_filter,
1631 struct i40e_asq_cmd_details *cmd_details)
1632 {
1633 struct i40e_aq_desc desc;
1634 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1635 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1636 i40e_status status;
1637
1638 i40e_fill_default_direct_cmd_desc(&desc,
1639 i40e_aqc_opc_set_vsi_promiscuous_modes);
1640
1641 if (set_filter)
1642 cmd->promiscuous_flags
1643 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1644 else
1645 cmd->promiscuous_flags
1646 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1647
1648 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1649 cmd->seid = cpu_to_le16(seid);
1650 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1651
1652 return status;
1653 }
1654
1655 /**
1656 * i40e_get_vsi_params - get VSI configuration info
1657 * @hw: pointer to the hw struct
1658 * @vsi_ctx: pointer to a vsi context struct
1659 * @cmd_details: pointer to command details structure or NULL
1660 **/
1661 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
1662 struct i40e_vsi_context *vsi_ctx,
1663 struct i40e_asq_cmd_details *cmd_details)
1664 {
1665 struct i40e_aq_desc desc;
1666 struct i40e_aqc_add_get_update_vsi *cmd =
1667 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1668 struct i40e_aqc_add_get_update_vsi_completion *resp =
1669 (struct i40e_aqc_add_get_update_vsi_completion *)
1670 &desc.params.raw;
1671 i40e_status status;
1672
1673 i40e_fill_default_direct_cmd_desc(&desc,
1674 i40e_aqc_opc_get_vsi_parameters);
1675
1676 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
1677
1678 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1679
1680 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1681 sizeof(vsi_ctx->info), NULL);
1682
1683 if (status)
1684 goto aq_get_vsi_params_exit;
1685
1686 vsi_ctx->seid = le16_to_cpu(resp->seid);
1687 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1688 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1689 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1690
1691 aq_get_vsi_params_exit:
1692 return status;
1693 }
1694
1695 /**
1696 * i40e_aq_update_vsi_params
1697 * @hw: pointer to the hw struct
1698 * @vsi_ctx: pointer to a vsi context struct
1699 * @cmd_details: pointer to command details structure or NULL
1700 *
1701 * Update a VSI context.
1702 **/
1703 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
1704 struct i40e_vsi_context *vsi_ctx,
1705 struct i40e_asq_cmd_details *cmd_details)
1706 {
1707 struct i40e_aq_desc desc;
1708 struct i40e_aqc_add_get_update_vsi *cmd =
1709 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1710 i40e_status status;
1711
1712 i40e_fill_default_direct_cmd_desc(&desc,
1713 i40e_aqc_opc_update_vsi_parameters);
1714 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
1715
1716 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1717
1718 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1719 sizeof(vsi_ctx->info), cmd_details);
1720
1721 return status;
1722 }
1723
1724 /**
1725 * i40e_aq_get_switch_config
1726 * @hw: pointer to the hardware structure
1727 * @buf: pointer to the result buffer
1728 * @buf_size: length of input buffer
1729 * @start_seid: seid to start for the report, 0 == beginning
1730 * @cmd_details: pointer to command details structure or NULL
1731 *
1732 * Fill the buf with switch configuration returned from AdminQ command
1733 **/
1734 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
1735 struct i40e_aqc_get_switch_config_resp *buf,
1736 u16 buf_size, u16 *start_seid,
1737 struct i40e_asq_cmd_details *cmd_details)
1738 {
1739 struct i40e_aq_desc desc;
1740 struct i40e_aqc_switch_seid *scfg =
1741 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1742 i40e_status status;
1743
1744 i40e_fill_default_direct_cmd_desc(&desc,
1745 i40e_aqc_opc_get_switch_config);
1746 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1747 if (buf_size > I40E_AQ_LARGE_BUF)
1748 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1749 scfg->seid = cpu_to_le16(*start_seid);
1750
1751 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1752 *start_seid = le16_to_cpu(scfg->seid);
1753
1754 return status;
1755 }
1756
1757 /**
1758 * i40e_aq_get_firmware_version
1759 * @hw: pointer to the hw struct
1760 * @fw_major_version: firmware major version
1761 * @fw_minor_version: firmware minor version
1762 * @api_major_version: major queue version
1763 * @api_minor_version: minor queue version
1764 * @cmd_details: pointer to command details structure or NULL
1765 *
1766 * Get the firmware version from the admin queue commands
1767 **/
1768 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
1769 u16 *fw_major_version, u16 *fw_minor_version,
1770 u16 *api_major_version, u16 *api_minor_version,
1771 struct i40e_asq_cmd_details *cmd_details)
1772 {
1773 struct i40e_aq_desc desc;
1774 struct i40e_aqc_get_version *resp =
1775 (struct i40e_aqc_get_version *)&desc.params.raw;
1776 i40e_status status;
1777
1778 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1779
1780 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1781
1782 if (!status) {
1783 if (fw_major_version != NULL)
1784 *fw_major_version = le16_to_cpu(resp->fw_major);
1785 if (fw_minor_version != NULL)
1786 *fw_minor_version = le16_to_cpu(resp->fw_minor);
1787 if (api_major_version != NULL)
1788 *api_major_version = le16_to_cpu(resp->api_major);
1789 if (api_minor_version != NULL)
1790 *api_minor_version = le16_to_cpu(resp->api_minor);
1791 }
1792
1793 return status;
1794 }
1795
1796 /**
1797 * i40e_aq_send_driver_version
1798 * @hw: pointer to the hw struct
1799 * @dv: driver's major, minor version
1800 * @cmd_details: pointer to command details structure or NULL
1801 *
1802 * Send the driver version to the firmware
1803 **/
1804 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
1805 struct i40e_driver_version *dv,
1806 struct i40e_asq_cmd_details *cmd_details)
1807 {
1808 struct i40e_aq_desc desc;
1809 struct i40e_aqc_driver_version *cmd =
1810 (struct i40e_aqc_driver_version *)&desc.params.raw;
1811 i40e_status status;
1812 u16 len;
1813
1814 if (dv == NULL)
1815 return I40E_ERR_PARAM;
1816
1817 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1818
1819 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
1820 cmd->driver_major_ver = dv->major_version;
1821 cmd->driver_minor_ver = dv->minor_version;
1822 cmd->driver_build_ver = dv->build_version;
1823 cmd->driver_subbuild_ver = dv->subbuild_version;
1824
1825 len = 0;
1826 while (len < sizeof(dv->driver_string) &&
1827 (dv->driver_string[len] < 0x80) &&
1828 dv->driver_string[len])
1829 len++;
1830 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1831 len, cmd_details);
1832
1833 return status;
1834 }
1835
1836 /**
1837 * i40e_get_link_status - get status of the HW network link
1838 * @hw: pointer to the hw struct
1839 *
1840 * Returns true if link is up, false if link is down.
1841 *
1842 * Side effect: LinkStatusEvent reporting becomes enabled
1843 **/
1844 bool i40e_get_link_status(struct i40e_hw *hw)
1845 {
1846 i40e_status status = 0;
1847 bool link_status = false;
1848
1849 if (hw->phy.get_link_info) {
1850 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1851
1852 if (status)
1853 goto i40e_get_link_status_exit;
1854 }
1855
1856 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1857
1858 i40e_get_link_status_exit:
1859 return link_status;
1860 }
1861
1862 /**
1863 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1864 * @hw: pointer to the hw struct
1865 * @uplink_seid: the MAC or other gizmo SEID
1866 * @downlink_seid: the VSI SEID
1867 * @enabled_tc: bitmap of TCs to be enabled
1868 * @default_port: true for default port VSI, false for control port
1869 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
1870 * @veb_seid: pointer to where to put the resulting VEB SEID
1871 * @cmd_details: pointer to command details structure or NULL
1872 *
1873 * This asks the FW to add a VEB between the uplink and downlink
1874 * elements. If the uplink SEID is 0, this will be a floating VEB.
1875 **/
1876 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
1877 u16 downlink_seid, u8 enabled_tc,
1878 bool default_port, bool enable_l2_filtering,
1879 u16 *veb_seid,
1880 struct i40e_asq_cmd_details *cmd_details)
1881 {
1882 struct i40e_aq_desc desc;
1883 struct i40e_aqc_add_veb *cmd =
1884 (struct i40e_aqc_add_veb *)&desc.params.raw;
1885 struct i40e_aqc_add_veb_completion *resp =
1886 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1887 i40e_status status;
1888 u16 veb_flags = 0;
1889
1890 /* SEIDs need to either both be set or both be 0 for floating VEB */
1891 if (!!uplink_seid != !!downlink_seid)
1892 return I40E_ERR_PARAM;
1893
1894 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1895
1896 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1897 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1898 cmd->enable_tcs = enabled_tc;
1899 if (!uplink_seid)
1900 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1901 if (default_port)
1902 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1903 else
1904 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
1905
1906 if (enable_l2_filtering)
1907 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1908
1909 cmd->veb_flags = cpu_to_le16(veb_flags);
1910
1911 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1912
1913 if (!status && veb_seid)
1914 *veb_seid = le16_to_cpu(resp->veb_seid);
1915
1916 return status;
1917 }
1918
1919 /**
1920 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1921 * @hw: pointer to the hw struct
1922 * @veb_seid: the SEID of the VEB to query
1923 * @switch_id: the uplink switch id
1924 * @floating: set to true if the VEB is floating
1925 * @statistic_index: index of the stats counter block for this VEB
1926 * @vebs_used: number of VEB's used by function
1927 * @vebs_free: total VEB's not reserved by any function
1928 * @cmd_details: pointer to command details structure or NULL
1929 *
1930 * This retrieves the parameters for a particular VEB, specified by
1931 * uplink_seid, and returns them to the caller.
1932 **/
1933 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1934 u16 veb_seid, u16 *switch_id,
1935 bool *floating, u16 *statistic_index,
1936 u16 *vebs_used, u16 *vebs_free,
1937 struct i40e_asq_cmd_details *cmd_details)
1938 {
1939 struct i40e_aq_desc desc;
1940 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1941 (struct i40e_aqc_get_veb_parameters_completion *)
1942 &desc.params.raw;
1943 i40e_status status;
1944
1945 if (veb_seid == 0)
1946 return I40E_ERR_PARAM;
1947
1948 i40e_fill_default_direct_cmd_desc(&desc,
1949 i40e_aqc_opc_get_veb_parameters);
1950 cmd_resp->seid = cpu_to_le16(veb_seid);
1951
1952 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1953 if (status)
1954 goto get_veb_exit;
1955
1956 if (switch_id)
1957 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1958 if (statistic_index)
1959 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1960 if (vebs_used)
1961 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1962 if (vebs_free)
1963 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1964 if (floating) {
1965 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1966 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1967 *floating = true;
1968 else
1969 *floating = false;
1970 }
1971
1972 get_veb_exit:
1973 return status;
1974 }
1975
1976 /**
1977 * i40e_aq_add_macvlan
1978 * @hw: pointer to the hw struct
1979 * @seid: VSI for the mac address
1980 * @mv_list: list of macvlans to be added
1981 * @count: length of the list
1982 * @cmd_details: pointer to command details structure or NULL
1983 *
1984 * Add MAC/VLAN addresses to the HW filtering
1985 **/
1986 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1987 struct i40e_aqc_add_macvlan_element_data *mv_list,
1988 u16 count, struct i40e_asq_cmd_details *cmd_details)
1989 {
1990 struct i40e_aq_desc desc;
1991 struct i40e_aqc_macvlan *cmd =
1992 (struct i40e_aqc_macvlan *)&desc.params.raw;
1993 i40e_status status;
1994 u16 buf_size;
1995
1996 if (count == 0 || !mv_list || !hw)
1997 return I40E_ERR_PARAM;
1998
1999 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
2000
2001 /* prep the rest of the request */
2002 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2003 cmd->num_addresses = cpu_to_le16(count);
2004 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2005 cmd->seid[1] = 0;
2006 cmd->seid[2] = 0;
2007
2008 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2009 if (buf_size > I40E_AQ_LARGE_BUF)
2010 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2011
2012 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2013 cmd_details);
2014
2015 return status;
2016 }
2017
2018 /**
2019 * i40e_aq_remove_macvlan
2020 * @hw: pointer to the hw struct
2021 * @seid: VSI for the mac address
2022 * @mv_list: list of macvlans to be removed
2023 * @count: length of the list
2024 * @cmd_details: pointer to command details structure or NULL
2025 *
2026 * Remove MAC/VLAN addresses from the HW filtering
2027 **/
2028 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2029 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2030 u16 count, struct i40e_asq_cmd_details *cmd_details)
2031 {
2032 struct i40e_aq_desc desc;
2033 struct i40e_aqc_macvlan *cmd =
2034 (struct i40e_aqc_macvlan *)&desc.params.raw;
2035 i40e_status status;
2036 u16 buf_size;
2037
2038 if (count == 0 || !mv_list || !hw)
2039 return I40E_ERR_PARAM;
2040
2041 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
2042
2043 /* prep the rest of the request */
2044 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2045 cmd->num_addresses = cpu_to_le16(count);
2046 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2047 cmd->seid[1] = 0;
2048 cmd->seid[2] = 0;
2049
2050 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2051 if (buf_size > I40E_AQ_LARGE_BUF)
2052 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2053
2054 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2055 cmd_details);
2056
2057 return status;
2058 }
2059
2060 /**
2061 * i40e_aq_send_msg_to_vf
2062 * @hw: pointer to the hardware structure
2063 * @vfid: vf id to send msg
2064 * @v_opcode: opcodes for VF-PF communication
2065 * @v_retval: return error code
2066 * @msg: pointer to the msg buffer
2067 * @msglen: msg length
2068 * @cmd_details: pointer to command details
2069 *
2070 * send msg to vf
2071 **/
2072 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2073 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2074 struct i40e_asq_cmd_details *cmd_details)
2075 {
2076 struct i40e_aq_desc desc;
2077 struct i40e_aqc_pf_vf_message *cmd =
2078 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2079 i40e_status status;
2080
2081 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2082 cmd->id = cpu_to_le32(vfid);
2083 desc.cookie_high = cpu_to_le32(v_opcode);
2084 desc.cookie_low = cpu_to_le32(v_retval);
2085 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2086 if (msglen) {
2087 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2088 I40E_AQ_FLAG_RD));
2089 if (msglen > I40E_AQ_LARGE_BUF)
2090 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2091 desc.datalen = cpu_to_le16(msglen);
2092 }
2093 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2094
2095 return status;
2096 }
2097
2098 /**
2099 * i40e_aq_debug_read_register
2100 * @hw: pointer to the hw struct
2101 * @reg_addr: register address
2102 * @reg_val: register value
2103 * @cmd_details: pointer to command details structure or NULL
2104 *
2105 * Read the register using the admin queue commands
2106 **/
2107 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2108 u32 reg_addr, u64 *reg_val,
2109 struct i40e_asq_cmd_details *cmd_details)
2110 {
2111 struct i40e_aq_desc desc;
2112 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2113 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2114 i40e_status status;
2115
2116 if (reg_val == NULL)
2117 return I40E_ERR_PARAM;
2118
2119 i40e_fill_default_direct_cmd_desc(&desc,
2120 i40e_aqc_opc_debug_read_reg);
2121
2122 cmd_resp->address = cpu_to_le32(reg_addr);
2123
2124 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2125
2126 if (!status) {
2127 *reg_val = ((u64)cmd_resp->value_high << 32) |
2128 (u64)cmd_resp->value_low;
2129 *reg_val = le64_to_cpu(*reg_val);
2130 }
2131
2132 return status;
2133 }
2134
2135 /**
2136 * i40e_aq_debug_write_register
2137 * @hw: pointer to the hw struct
2138 * @reg_addr: register address
2139 * @reg_val: register value
2140 * @cmd_details: pointer to command details structure or NULL
2141 *
2142 * Write to a register using the admin queue commands
2143 **/
2144 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2145 u32 reg_addr, u64 reg_val,
2146 struct i40e_asq_cmd_details *cmd_details)
2147 {
2148 struct i40e_aq_desc desc;
2149 struct i40e_aqc_debug_reg_read_write *cmd =
2150 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2151 i40e_status status;
2152
2153 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2154
2155 cmd->address = cpu_to_le32(reg_addr);
2156 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2157 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2158
2159 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2160
2161 return status;
2162 }
2163
2164 /**
2165 * i40e_aq_set_hmc_resource_profile
2166 * @hw: pointer to the hw struct
2167 * @profile: type of profile the HMC is to be set as
2168 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2169 * @cmd_details: pointer to command details structure or NULL
2170 *
2171 * set the HMC profile of the device.
2172 **/
2173 i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2174 enum i40e_aq_hmc_profile profile,
2175 u8 pe_vf_enabled_count,
2176 struct i40e_asq_cmd_details *cmd_details)
2177 {
2178 struct i40e_aq_desc desc;
2179 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2180 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2181 i40e_status status;
2182
2183 i40e_fill_default_direct_cmd_desc(&desc,
2184 i40e_aqc_opc_set_hmc_resource_profile);
2185
2186 cmd->pm_profile = (u8)profile;
2187 cmd->pe_vf_enabled = pe_vf_enabled_count;
2188
2189 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2190
2191 return status;
2192 }
2193
2194 /**
2195 * i40e_aq_request_resource
2196 * @hw: pointer to the hw struct
2197 * @resource: resource id
2198 * @access: access type
2199 * @sdp_number: resource number
2200 * @timeout: the maximum time in ms that the driver may hold the resource
2201 * @cmd_details: pointer to command details structure or NULL
2202 *
2203 * requests common resource using the admin queue commands
2204 **/
2205 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2206 enum i40e_aq_resources_ids resource,
2207 enum i40e_aq_resource_access_type access,
2208 u8 sdp_number, u64 *timeout,
2209 struct i40e_asq_cmd_details *cmd_details)
2210 {
2211 struct i40e_aq_desc desc;
2212 struct i40e_aqc_request_resource *cmd_resp =
2213 (struct i40e_aqc_request_resource *)&desc.params.raw;
2214 i40e_status status;
2215
2216 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2217
2218 cmd_resp->resource_id = cpu_to_le16(resource);
2219 cmd_resp->access_type = cpu_to_le16(access);
2220 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2221
2222 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2223 /* The completion specifies the maximum time in ms that the driver
2224 * may hold the resource in the Timeout field.
2225 * If the resource is held by someone else, the command completes with
2226 * busy return value and the timeout field indicates the maximum time
2227 * the current owner of the resource has to free it.
2228 */
2229 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2230 *timeout = le32_to_cpu(cmd_resp->timeout);
2231
2232 return status;
2233 }
2234
2235 /**
2236 * i40e_aq_release_resource
2237 * @hw: pointer to the hw struct
2238 * @resource: resource id
2239 * @sdp_number: resource number
2240 * @cmd_details: pointer to command details structure or NULL
2241 *
2242 * release common resource using the admin queue commands
2243 **/
2244 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2245 enum i40e_aq_resources_ids resource,
2246 u8 sdp_number,
2247 struct i40e_asq_cmd_details *cmd_details)
2248 {
2249 struct i40e_aq_desc desc;
2250 struct i40e_aqc_request_resource *cmd =
2251 (struct i40e_aqc_request_resource *)&desc.params.raw;
2252 i40e_status status;
2253
2254 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2255
2256 cmd->resource_id = cpu_to_le16(resource);
2257 cmd->resource_number = cpu_to_le32(sdp_number);
2258
2259 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2260
2261 return status;
2262 }
2263
2264 /**
2265 * i40e_aq_read_nvm
2266 * @hw: pointer to the hw struct
2267 * @module_pointer: module pointer location in words from the NVM beginning
2268 * @offset: byte offset from the module beginning
2269 * @length: length of the section to be read (in bytes from the offset)
2270 * @data: command buffer (size [bytes] = length)
2271 * @last_command: tells if this is the last command in a series
2272 * @cmd_details: pointer to command details structure or NULL
2273 *
2274 * Read the NVM using the admin queue commands
2275 **/
2276 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2277 u32 offset, u16 length, void *data,
2278 bool last_command,
2279 struct i40e_asq_cmd_details *cmd_details)
2280 {
2281 struct i40e_aq_desc desc;
2282 struct i40e_aqc_nvm_update *cmd =
2283 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2284 i40e_status status;
2285
2286 /* In offset the highest byte must be zeroed. */
2287 if (offset & 0xFF000000) {
2288 status = I40E_ERR_PARAM;
2289 goto i40e_aq_read_nvm_exit;
2290 }
2291
2292 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2293
2294 /* If this is the last command in a series, set the proper flag. */
2295 if (last_command)
2296 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2297 cmd->module_pointer = module_pointer;
2298 cmd->offset = cpu_to_le32(offset);
2299 cmd->length = cpu_to_le16(length);
2300
2301 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2302 if (length > I40E_AQ_LARGE_BUF)
2303 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2304
2305 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2306
2307 i40e_aq_read_nvm_exit:
2308 return status;
2309 }
2310
2311 /**
2312 * i40e_aq_erase_nvm
2313 * @hw: pointer to the hw struct
2314 * @module_pointer: module pointer location in words from the NVM beginning
2315 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2316 * @length: length of the section to be erased (expressed in 4 KB)
2317 * @last_command: tells if this is the last command in a series
2318 * @cmd_details: pointer to command details structure or NULL
2319 *
2320 * Erase the NVM sector using the admin queue commands
2321 **/
2322 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2323 u32 offset, u16 length, bool last_command,
2324 struct i40e_asq_cmd_details *cmd_details)
2325 {
2326 struct i40e_aq_desc desc;
2327 struct i40e_aqc_nvm_update *cmd =
2328 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2329 i40e_status status;
2330
2331 /* In offset the highest byte must be zeroed. */
2332 if (offset & 0xFF000000) {
2333 status = I40E_ERR_PARAM;
2334 goto i40e_aq_erase_nvm_exit;
2335 }
2336
2337 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2338
2339 /* If this is the last command in a series, set the proper flag. */
2340 if (last_command)
2341 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2342 cmd->module_pointer = module_pointer;
2343 cmd->offset = cpu_to_le32(offset);
2344 cmd->length = cpu_to_le16(length);
2345
2346 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2347
2348 i40e_aq_erase_nvm_exit:
2349 return status;
2350 }
2351
2352 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2353 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2354 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2355 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2356 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2357 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2358 #define I40E_DEV_FUNC_CAP_VF 0x13
2359 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2360 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2361 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2362 #define I40E_DEV_FUNC_CAP_VSI 0x17
2363 #define I40E_DEV_FUNC_CAP_DCB 0x18
2364 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2365 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
2366 #define I40E_DEV_FUNC_CAP_RSS 0x40
2367 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2368 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2369 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2370 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2371 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2372 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2373 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2374 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2375 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2376 #define I40E_DEV_FUNC_CAP_LED 0x61
2377 #define I40E_DEV_FUNC_CAP_SDP 0x62
2378 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2379
2380 /**
2381 * i40e_parse_discover_capabilities
2382 * @hw: pointer to the hw struct
2383 * @buff: pointer to a buffer containing device/function capability records
2384 * @cap_count: number of capability records in the list
2385 * @list_type_opc: type of capabilities list to parse
2386 *
2387 * Parse the device/function capabilities list.
2388 **/
2389 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2390 u32 cap_count,
2391 enum i40e_admin_queue_opc list_type_opc)
2392 {
2393 struct i40e_aqc_list_capabilities_element_resp *cap;
2394 u32 valid_functions, num_functions;
2395 u32 number, logical_id, phys_id;
2396 struct i40e_hw_capabilities *p;
2397 u32 i = 0;
2398 u16 id;
2399
2400 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2401
2402 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2403 p = &hw->dev_caps;
2404 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2405 p = &hw->func_caps;
2406 else
2407 return;
2408
2409 for (i = 0; i < cap_count; i++, cap++) {
2410 id = le16_to_cpu(cap->id);
2411 number = le32_to_cpu(cap->number);
2412 logical_id = le32_to_cpu(cap->logical_id);
2413 phys_id = le32_to_cpu(cap->phys_id);
2414
2415 switch (id) {
2416 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2417 p->switch_mode = number;
2418 break;
2419 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2420 p->management_mode = number;
2421 break;
2422 case I40E_DEV_FUNC_CAP_NPAR:
2423 p->npar_enable = number;
2424 break;
2425 case I40E_DEV_FUNC_CAP_OS2BMC:
2426 p->os2bmc = number;
2427 break;
2428 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2429 p->valid_functions = number;
2430 break;
2431 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2432 if (number == 1)
2433 p->sr_iov_1_1 = true;
2434 break;
2435 case I40E_DEV_FUNC_CAP_VF:
2436 p->num_vfs = number;
2437 p->vf_base_id = logical_id;
2438 break;
2439 case I40E_DEV_FUNC_CAP_VMDQ:
2440 if (number == 1)
2441 p->vmdq = true;
2442 break;
2443 case I40E_DEV_FUNC_CAP_802_1_QBG:
2444 if (number == 1)
2445 p->evb_802_1_qbg = true;
2446 break;
2447 case I40E_DEV_FUNC_CAP_802_1_QBH:
2448 if (number == 1)
2449 p->evb_802_1_qbh = true;
2450 break;
2451 case I40E_DEV_FUNC_CAP_VSI:
2452 p->num_vsis = number;
2453 break;
2454 case I40E_DEV_FUNC_CAP_DCB:
2455 if (number == 1) {
2456 p->dcb = true;
2457 p->enabled_tcmap = logical_id;
2458 p->maxtc = phys_id;
2459 }
2460 break;
2461 case I40E_DEV_FUNC_CAP_FCOE:
2462 if (number == 1)
2463 p->fcoe = true;
2464 break;
2465 case I40E_DEV_FUNC_CAP_ISCSI:
2466 if (number == 1)
2467 p->iscsi = true;
2468 break;
2469 case I40E_DEV_FUNC_CAP_RSS:
2470 p->rss = true;
2471 p->rss_table_size = number;
2472 p->rss_table_entry_width = logical_id;
2473 break;
2474 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2475 p->num_rx_qp = number;
2476 p->base_queue = phys_id;
2477 break;
2478 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2479 p->num_tx_qp = number;
2480 p->base_queue = phys_id;
2481 break;
2482 case I40E_DEV_FUNC_CAP_MSIX:
2483 p->num_msix_vectors = number;
2484 break;
2485 case I40E_DEV_FUNC_CAP_MSIX_VF:
2486 p->num_msix_vectors_vf = number;
2487 break;
2488 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2489 if (number == 1)
2490 p->mfp_mode_1 = true;
2491 break;
2492 case I40E_DEV_FUNC_CAP_CEM:
2493 if (number == 1)
2494 p->mgmt_cem = true;
2495 break;
2496 case I40E_DEV_FUNC_CAP_IWARP:
2497 if (number == 1)
2498 p->iwarp = true;
2499 break;
2500 case I40E_DEV_FUNC_CAP_LED:
2501 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2502 p->led[phys_id] = true;
2503 break;
2504 case I40E_DEV_FUNC_CAP_SDP:
2505 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2506 p->sdp[phys_id] = true;
2507 break;
2508 case I40E_DEV_FUNC_CAP_MDIO:
2509 if (number == 1) {
2510 p->mdio_port_num = phys_id;
2511 p->mdio_port_mode = logical_id;
2512 }
2513 break;
2514 case I40E_DEV_FUNC_CAP_IEEE_1588:
2515 if (number == 1)
2516 p->ieee_1588 = true;
2517 break;
2518 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2519 p->fd = true;
2520 p->fd_filters_guaranteed = number;
2521 p->fd_filters_best_effort = logical_id;
2522 break;
2523 default:
2524 break;
2525 }
2526 }
2527
2528 /* Software override ensuring FCoE is disabled if npar or mfp
2529 * mode because it is not supported in these modes.
2530 */
2531 if (p->npar_enable || p->mfp_mode_1)
2532 p->fcoe = false;
2533
2534 /* count the enabled ports (aka the "not disabled" ports) */
2535 hw->num_ports = 0;
2536 for (i = 0; i < 4; i++) {
2537 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
2538 u64 port_cfg = 0;
2539
2540 /* use AQ read to get the physical register offset instead
2541 * of the port relative offset
2542 */
2543 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
2544 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
2545 hw->num_ports++;
2546 }
2547
2548 valid_functions = p->valid_functions;
2549 num_functions = 0;
2550 while (valid_functions) {
2551 if (valid_functions & 1)
2552 num_functions++;
2553 valid_functions >>= 1;
2554 }
2555
2556 /* partition id is 1-based, and functions are evenly spread
2557 * across the ports as partitions
2558 */
2559 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
2560 hw->num_partitions = num_functions / hw->num_ports;
2561
2562 /* additional HW specific goodies that might
2563 * someday be HW version specific
2564 */
2565 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2566 }
2567
2568 /**
2569 * i40e_aq_discover_capabilities
2570 * @hw: pointer to the hw struct
2571 * @buff: a virtual buffer to hold the capabilities
2572 * @buff_size: Size of the virtual buffer
2573 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2574 * @list_type_opc: capabilities type to discover - pass in the command opcode
2575 * @cmd_details: pointer to command details structure or NULL
2576 *
2577 * Get the device capabilities descriptions from the firmware
2578 **/
2579 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
2580 void *buff, u16 buff_size, u16 *data_size,
2581 enum i40e_admin_queue_opc list_type_opc,
2582 struct i40e_asq_cmd_details *cmd_details)
2583 {
2584 struct i40e_aqc_list_capabilites *cmd;
2585 struct i40e_aq_desc desc;
2586 i40e_status status = 0;
2587
2588 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2589
2590 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2591 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2592 status = I40E_ERR_PARAM;
2593 goto exit;
2594 }
2595
2596 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2597
2598 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2599 if (buff_size > I40E_AQ_LARGE_BUF)
2600 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2601
2602 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2603 *data_size = le16_to_cpu(desc.datalen);
2604
2605 if (status)
2606 goto exit;
2607
2608 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
2609 list_type_opc);
2610
2611 exit:
2612 return status;
2613 }
2614
2615 /**
2616 * i40e_aq_update_nvm
2617 * @hw: pointer to the hw struct
2618 * @module_pointer: module pointer location in words from the NVM beginning
2619 * @offset: byte offset from the module beginning
2620 * @length: length of the section to be written (in bytes from the offset)
2621 * @data: command buffer (size [bytes] = length)
2622 * @last_command: tells if this is the last command in a series
2623 * @cmd_details: pointer to command details structure or NULL
2624 *
2625 * Update the NVM using the admin queue commands
2626 **/
2627 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2628 u32 offset, u16 length, void *data,
2629 bool last_command,
2630 struct i40e_asq_cmd_details *cmd_details)
2631 {
2632 struct i40e_aq_desc desc;
2633 struct i40e_aqc_nvm_update *cmd =
2634 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2635 i40e_status status;
2636
2637 /* In offset the highest byte must be zeroed. */
2638 if (offset & 0xFF000000) {
2639 status = I40E_ERR_PARAM;
2640 goto i40e_aq_update_nvm_exit;
2641 }
2642
2643 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2644
2645 /* If this is the last command in a series, set the proper flag. */
2646 if (last_command)
2647 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2648 cmd->module_pointer = module_pointer;
2649 cmd->offset = cpu_to_le32(offset);
2650 cmd->length = cpu_to_le16(length);
2651
2652 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2653 if (length > I40E_AQ_LARGE_BUF)
2654 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2655
2656 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2657
2658 i40e_aq_update_nvm_exit:
2659 return status;
2660 }
2661
2662 /**
2663 * i40e_aq_get_lldp_mib
2664 * @hw: pointer to the hw struct
2665 * @bridge_type: type of bridge requested
2666 * @mib_type: Local, Remote or both Local and Remote MIBs
2667 * @buff: pointer to a user supplied buffer to store the MIB block
2668 * @buff_size: size of the buffer (in bytes)
2669 * @local_len : length of the returned Local LLDP MIB
2670 * @remote_len: length of the returned Remote LLDP MIB
2671 * @cmd_details: pointer to command details structure or NULL
2672 *
2673 * Requests the complete LLDP MIB (entire packet).
2674 **/
2675 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2676 u8 mib_type, void *buff, u16 buff_size,
2677 u16 *local_len, u16 *remote_len,
2678 struct i40e_asq_cmd_details *cmd_details)
2679 {
2680 struct i40e_aq_desc desc;
2681 struct i40e_aqc_lldp_get_mib *cmd =
2682 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2683 struct i40e_aqc_lldp_get_mib *resp =
2684 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2685 i40e_status status;
2686
2687 if (buff_size == 0 || !buff)
2688 return I40E_ERR_PARAM;
2689
2690 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2691 /* Indirect Command */
2692 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2693
2694 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2695 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2696 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2697
2698 desc.datalen = cpu_to_le16(buff_size);
2699
2700 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2701 if (buff_size > I40E_AQ_LARGE_BUF)
2702 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2703
2704 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2705 if (!status) {
2706 if (local_len != NULL)
2707 *local_len = le16_to_cpu(resp->local_len);
2708 if (remote_len != NULL)
2709 *remote_len = le16_to_cpu(resp->remote_len);
2710 }
2711
2712 return status;
2713 }
2714
2715 /**
2716 * i40e_aq_cfg_lldp_mib_change_event
2717 * @hw: pointer to the hw struct
2718 * @enable_update: Enable or Disable event posting
2719 * @cmd_details: pointer to command details structure or NULL
2720 *
2721 * Enable or Disable posting of an event on ARQ when LLDP MIB
2722 * associated with the interface changes
2723 **/
2724 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2725 bool enable_update,
2726 struct i40e_asq_cmd_details *cmd_details)
2727 {
2728 struct i40e_aq_desc desc;
2729 struct i40e_aqc_lldp_update_mib *cmd =
2730 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2731 i40e_status status;
2732
2733 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2734
2735 if (!enable_update)
2736 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2737
2738 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2739
2740 return status;
2741 }
2742
2743 /**
2744 * i40e_aq_stop_lldp
2745 * @hw: pointer to the hw struct
2746 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2747 * @cmd_details: pointer to command details structure or NULL
2748 *
2749 * Stop or Shutdown the embedded LLDP Agent
2750 **/
2751 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
2752 struct i40e_asq_cmd_details *cmd_details)
2753 {
2754 struct i40e_aq_desc desc;
2755 struct i40e_aqc_lldp_stop *cmd =
2756 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
2757 i40e_status status;
2758
2759 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
2760
2761 if (shutdown_agent)
2762 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
2763
2764 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2765
2766 return status;
2767 }
2768
2769 /**
2770 * i40e_aq_start_lldp
2771 * @hw: pointer to the hw struct
2772 * @cmd_details: pointer to command details structure or NULL
2773 *
2774 * Start the embedded LLDP Agent on all ports.
2775 **/
2776 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
2777 struct i40e_asq_cmd_details *cmd_details)
2778 {
2779 struct i40e_aq_desc desc;
2780 struct i40e_aqc_lldp_start *cmd =
2781 (struct i40e_aqc_lldp_start *)&desc.params.raw;
2782 i40e_status status;
2783
2784 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
2785
2786 cmd->command = I40E_AQ_LLDP_AGENT_START;
2787
2788 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2789
2790 return status;
2791 }
2792
2793 /**
2794 * i40e_aq_get_cee_dcb_config
2795 * @hw: pointer to the hw struct
2796 * @buff: response buffer that stores CEE operational configuration
2797 * @buff_size: size of the buffer passed
2798 * @cmd_details: pointer to command details structure or NULL
2799 *
2800 * Get CEE DCBX mode operational configuration from firmware
2801 **/
2802 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
2803 void *buff, u16 buff_size,
2804 struct i40e_asq_cmd_details *cmd_details)
2805 {
2806 struct i40e_aq_desc desc;
2807 i40e_status status;
2808
2809 if (buff_size == 0 || !buff)
2810 return I40E_ERR_PARAM;
2811
2812 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
2813
2814 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2815 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
2816 cmd_details);
2817
2818 return status;
2819 }
2820
2821 /**
2822 * i40e_aq_add_udp_tunnel
2823 * @hw: pointer to the hw struct
2824 * @udp_port: the UDP port to add
2825 * @header_len: length of the tunneling header length in DWords
2826 * @protocol_index: protocol index type
2827 * @filter_index: pointer to filter index
2828 * @cmd_details: pointer to command details structure or NULL
2829 **/
2830 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
2831 u16 udp_port, u8 protocol_index,
2832 u8 *filter_index,
2833 struct i40e_asq_cmd_details *cmd_details)
2834 {
2835 struct i40e_aq_desc desc;
2836 struct i40e_aqc_add_udp_tunnel *cmd =
2837 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
2838 struct i40e_aqc_del_udp_tunnel_completion *resp =
2839 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
2840 i40e_status status;
2841
2842 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
2843
2844 cmd->udp_port = cpu_to_le16(udp_port);
2845 cmd->protocol_type = protocol_index;
2846
2847 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2848
2849 if (!status)
2850 *filter_index = resp->index;
2851
2852 return status;
2853 }
2854
2855 /**
2856 * i40e_aq_del_udp_tunnel
2857 * @hw: pointer to the hw struct
2858 * @index: filter index
2859 * @cmd_details: pointer to command details structure or NULL
2860 **/
2861 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
2862 struct i40e_asq_cmd_details *cmd_details)
2863 {
2864 struct i40e_aq_desc desc;
2865 struct i40e_aqc_remove_udp_tunnel *cmd =
2866 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
2867 i40e_status status;
2868
2869 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
2870
2871 cmd->index = index;
2872
2873 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2874
2875 return status;
2876 }
2877
2878 /**
2879 * i40e_aq_delete_element - Delete switch element
2880 * @hw: pointer to the hw struct
2881 * @seid: the SEID to delete from the switch
2882 * @cmd_details: pointer to command details structure or NULL
2883 *
2884 * This deletes a switch element from the switch.
2885 **/
2886 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
2887 struct i40e_asq_cmd_details *cmd_details)
2888 {
2889 struct i40e_aq_desc desc;
2890 struct i40e_aqc_switch_seid *cmd =
2891 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2892 i40e_status status;
2893
2894 if (seid == 0)
2895 return I40E_ERR_PARAM;
2896
2897 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
2898
2899 cmd->seid = cpu_to_le16(seid);
2900
2901 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2902
2903 return status;
2904 }
2905
2906 /**
2907 * i40e_aq_dcb_updated - DCB Updated Command
2908 * @hw: pointer to the hw struct
2909 * @cmd_details: pointer to command details structure or NULL
2910 *
2911 * EMP will return when the shared RPB settings have been
2912 * recomputed and modified. The retval field in the descriptor
2913 * will be set to 0 when RPB is modified.
2914 **/
2915 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
2916 struct i40e_asq_cmd_details *cmd_details)
2917 {
2918 struct i40e_aq_desc desc;
2919 i40e_status status;
2920
2921 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
2922
2923 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2924
2925 return status;
2926 }
2927
2928 /**
2929 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2930 * @hw: pointer to the hw struct
2931 * @seid: seid for the physical port/switching component/vsi
2932 * @buff: Indirect buffer to hold data parameters and response
2933 * @buff_size: Indirect buffer size
2934 * @opcode: Tx scheduler AQ command opcode
2935 * @cmd_details: pointer to command details structure or NULL
2936 *
2937 * Generic command handler for Tx scheduler AQ commands
2938 **/
2939 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
2940 void *buff, u16 buff_size,
2941 enum i40e_admin_queue_opc opcode,
2942 struct i40e_asq_cmd_details *cmd_details)
2943 {
2944 struct i40e_aq_desc desc;
2945 struct i40e_aqc_tx_sched_ind *cmd =
2946 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
2947 i40e_status status;
2948 bool cmd_param_flag = false;
2949
2950 switch (opcode) {
2951 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
2952 case i40e_aqc_opc_configure_vsi_tc_bw:
2953 case i40e_aqc_opc_enable_switching_comp_ets:
2954 case i40e_aqc_opc_modify_switching_comp_ets:
2955 case i40e_aqc_opc_disable_switching_comp_ets:
2956 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
2957 case i40e_aqc_opc_configure_switching_comp_bw_config:
2958 cmd_param_flag = true;
2959 break;
2960 case i40e_aqc_opc_query_vsi_bw_config:
2961 case i40e_aqc_opc_query_vsi_ets_sla_config:
2962 case i40e_aqc_opc_query_switching_comp_ets_config:
2963 case i40e_aqc_opc_query_port_ets_config:
2964 case i40e_aqc_opc_query_switching_comp_bw_config:
2965 cmd_param_flag = false;
2966 break;
2967 default:
2968 return I40E_ERR_PARAM;
2969 }
2970
2971 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2972
2973 /* Indirect command */
2974 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2975 if (cmd_param_flag)
2976 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
2977 if (buff_size > I40E_AQ_LARGE_BUF)
2978 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2979
2980 desc.datalen = cpu_to_le16(buff_size);
2981
2982 cmd->vsi_seid = cpu_to_le16(seid);
2983
2984 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2985
2986 return status;
2987 }
2988
2989 /**
2990 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
2991 * @hw: pointer to the hw struct
2992 * @seid: VSI seid
2993 * @credit: BW limit credits (0 = disabled)
2994 * @max_credit: Max BW limit credits
2995 * @cmd_details: pointer to command details structure or NULL
2996 **/
2997 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
2998 u16 seid, u16 credit, u8 max_credit,
2999 struct i40e_asq_cmd_details *cmd_details)
3000 {
3001 struct i40e_aq_desc desc;
3002 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3003 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3004 i40e_status status;
3005
3006 i40e_fill_default_direct_cmd_desc(&desc,
3007 i40e_aqc_opc_configure_vsi_bw_limit);
3008
3009 cmd->vsi_seid = cpu_to_le16(seid);
3010 cmd->credit = cpu_to_le16(credit);
3011 cmd->max_credit = max_credit;
3012
3013 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3014
3015 return status;
3016 }
3017
3018 /**
3019 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3020 * @hw: pointer to the hw struct
3021 * @seid: VSI seid
3022 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3023 * @cmd_details: pointer to command details structure or NULL
3024 **/
3025 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3026 u16 seid,
3027 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3028 struct i40e_asq_cmd_details *cmd_details)
3029 {
3030 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3031 i40e_aqc_opc_configure_vsi_tc_bw,
3032 cmd_details);
3033 }
3034
3035 /**
3036 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3037 * @hw: pointer to the hw struct
3038 * @seid: seid of the switching component connected to Physical Port
3039 * @ets_data: Buffer holding ETS parameters
3040 * @cmd_details: pointer to command details structure or NULL
3041 **/
3042 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3043 u16 seid,
3044 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3045 enum i40e_admin_queue_opc opcode,
3046 struct i40e_asq_cmd_details *cmd_details)
3047 {
3048 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3049 sizeof(*ets_data), opcode, cmd_details);
3050 }
3051
3052 /**
3053 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3054 * @hw: pointer to the hw struct
3055 * @seid: seid of the switching component
3056 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3057 * @cmd_details: pointer to command details structure or NULL
3058 **/
3059 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3060 u16 seid,
3061 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3062 struct i40e_asq_cmd_details *cmd_details)
3063 {
3064 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3065 i40e_aqc_opc_configure_switching_comp_bw_config,
3066 cmd_details);
3067 }
3068
3069 /**
3070 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3071 * @hw: pointer to the hw struct
3072 * @seid: seid of the VSI
3073 * @bw_data: Buffer to hold VSI BW configuration
3074 * @cmd_details: pointer to command details structure or NULL
3075 **/
3076 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3077 u16 seid,
3078 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3079 struct i40e_asq_cmd_details *cmd_details)
3080 {
3081 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3082 i40e_aqc_opc_query_vsi_bw_config,
3083 cmd_details);
3084 }
3085
3086 /**
3087 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3088 * @hw: pointer to the hw struct
3089 * @seid: seid of the VSI
3090 * @bw_data: Buffer to hold VSI BW configuration per TC
3091 * @cmd_details: pointer to command details structure or NULL
3092 **/
3093 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3094 u16 seid,
3095 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3096 struct i40e_asq_cmd_details *cmd_details)
3097 {
3098 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3099 i40e_aqc_opc_query_vsi_ets_sla_config,
3100 cmd_details);
3101 }
3102
3103 /**
3104 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3105 * @hw: pointer to the hw struct
3106 * @seid: seid of the switching component
3107 * @bw_data: Buffer to hold switching component's per TC BW config
3108 * @cmd_details: pointer to command details structure or NULL
3109 **/
3110 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3111 u16 seid,
3112 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3113 struct i40e_asq_cmd_details *cmd_details)
3114 {
3115 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3116 i40e_aqc_opc_query_switching_comp_ets_config,
3117 cmd_details);
3118 }
3119
3120 /**
3121 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3122 * @hw: pointer to the hw struct
3123 * @seid: seid of the VSI or switching component connected to Physical Port
3124 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3125 * @cmd_details: pointer to command details structure or NULL
3126 **/
3127 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3128 u16 seid,
3129 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3130 struct i40e_asq_cmd_details *cmd_details)
3131 {
3132 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3133 i40e_aqc_opc_query_port_ets_config,
3134 cmd_details);
3135 }
3136
3137 /**
3138 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3139 * @hw: pointer to the hw struct
3140 * @seid: seid of the switching component
3141 * @bw_data: Buffer to hold switching component's BW configuration
3142 * @cmd_details: pointer to command details structure or NULL
3143 **/
3144 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3145 u16 seid,
3146 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3147 struct i40e_asq_cmd_details *cmd_details)
3148 {
3149 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3150 i40e_aqc_opc_query_switching_comp_bw_config,
3151 cmd_details);
3152 }
3153
3154 /**
3155 * i40e_validate_filter_settings
3156 * @hw: pointer to the hardware structure
3157 * @settings: Filter control settings
3158 *
3159 * Check and validate the filter control settings passed.
3160 * The function checks for the valid filter/context sizes being
3161 * passed for FCoE and PE.
3162 *
3163 * Returns 0 if the values passed are valid and within
3164 * range else returns an error.
3165 **/
3166 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3167 struct i40e_filter_control_settings *settings)
3168 {
3169 u32 fcoe_cntx_size, fcoe_filt_size;
3170 u32 pe_cntx_size, pe_filt_size;
3171 u32 fcoe_fmax;
3172 u32 val;
3173
3174 /* Validate FCoE settings passed */
3175 switch (settings->fcoe_filt_num) {
3176 case I40E_HASH_FILTER_SIZE_1K:
3177 case I40E_HASH_FILTER_SIZE_2K:
3178 case I40E_HASH_FILTER_SIZE_4K:
3179 case I40E_HASH_FILTER_SIZE_8K:
3180 case I40E_HASH_FILTER_SIZE_16K:
3181 case I40E_HASH_FILTER_SIZE_32K:
3182 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3183 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3184 break;
3185 default:
3186 return I40E_ERR_PARAM;
3187 }
3188
3189 switch (settings->fcoe_cntx_num) {
3190 case I40E_DMA_CNTX_SIZE_512:
3191 case I40E_DMA_CNTX_SIZE_1K:
3192 case I40E_DMA_CNTX_SIZE_2K:
3193 case I40E_DMA_CNTX_SIZE_4K:
3194 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3195 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3196 break;
3197 default:
3198 return I40E_ERR_PARAM;
3199 }
3200
3201 /* Validate PE settings passed */
3202 switch (settings->pe_filt_num) {
3203 case I40E_HASH_FILTER_SIZE_1K:
3204 case I40E_HASH_FILTER_SIZE_2K:
3205 case I40E_HASH_FILTER_SIZE_4K:
3206 case I40E_HASH_FILTER_SIZE_8K:
3207 case I40E_HASH_FILTER_SIZE_16K:
3208 case I40E_HASH_FILTER_SIZE_32K:
3209 case I40E_HASH_FILTER_SIZE_64K:
3210 case I40E_HASH_FILTER_SIZE_128K:
3211 case I40E_HASH_FILTER_SIZE_256K:
3212 case I40E_HASH_FILTER_SIZE_512K:
3213 case I40E_HASH_FILTER_SIZE_1M:
3214 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3215 pe_filt_size <<= (u32)settings->pe_filt_num;
3216 break;
3217 default:
3218 return I40E_ERR_PARAM;
3219 }
3220
3221 switch (settings->pe_cntx_num) {
3222 case I40E_DMA_CNTX_SIZE_512:
3223 case I40E_DMA_CNTX_SIZE_1K:
3224 case I40E_DMA_CNTX_SIZE_2K:
3225 case I40E_DMA_CNTX_SIZE_4K:
3226 case I40E_DMA_CNTX_SIZE_8K:
3227 case I40E_DMA_CNTX_SIZE_16K:
3228 case I40E_DMA_CNTX_SIZE_32K:
3229 case I40E_DMA_CNTX_SIZE_64K:
3230 case I40E_DMA_CNTX_SIZE_128K:
3231 case I40E_DMA_CNTX_SIZE_256K:
3232 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3233 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3234 break;
3235 default:
3236 return I40E_ERR_PARAM;
3237 }
3238
3239 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3240 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3241 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3242 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3243 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3244 return I40E_ERR_INVALID_SIZE;
3245
3246 return 0;
3247 }
3248
3249 /**
3250 * i40e_set_filter_control
3251 * @hw: pointer to the hardware structure
3252 * @settings: Filter control settings
3253 *
3254 * Set the Queue Filters for PE/FCoE and enable filters required
3255 * for a single PF. It is expected that these settings are programmed
3256 * at the driver initialization time.
3257 **/
3258 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3259 struct i40e_filter_control_settings *settings)
3260 {
3261 i40e_status ret = 0;
3262 u32 hash_lut_size = 0;
3263 u32 val;
3264
3265 if (!settings)
3266 return I40E_ERR_PARAM;
3267
3268 /* Validate the input settings */
3269 ret = i40e_validate_filter_settings(hw, settings);
3270 if (ret)
3271 return ret;
3272
3273 /* Read the PF Queue Filter control register */
3274 val = rd32(hw, I40E_PFQF_CTL_0);
3275
3276 /* Program required PE hash buckets for the PF */
3277 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3278 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3279 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3280 /* Program required PE contexts for the PF */
3281 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3282 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3283 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3284
3285 /* Program required FCoE hash buckets for the PF */
3286 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3287 val |= ((u32)settings->fcoe_filt_num <<
3288 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3289 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3290 /* Program required FCoE DDP contexts for the PF */
3291 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3292 val |= ((u32)settings->fcoe_cntx_num <<
3293 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3294 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3295
3296 /* Program Hash LUT size for the PF */
3297 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3298 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3299 hash_lut_size = 1;
3300 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3301 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3302
3303 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3304 if (settings->enable_fdir)
3305 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3306 if (settings->enable_ethtype)
3307 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3308 if (settings->enable_macvlan)
3309 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3310
3311 wr32(hw, I40E_PFQF_CTL_0, val);
3312
3313 return 0;
3314 }
3315
3316 /**
3317 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3318 * @hw: pointer to the hw struct
3319 * @mac_addr: MAC address to use in the filter
3320 * @ethtype: Ethertype to use in the filter
3321 * @flags: Flags that needs to be applied to the filter
3322 * @vsi_seid: seid of the control VSI
3323 * @queue: VSI queue number to send the packet to
3324 * @is_add: Add control packet filter if True else remove
3325 * @stats: Structure to hold information on control filter counts
3326 * @cmd_details: pointer to command details structure or NULL
3327 *
3328 * This command will Add or Remove control packet filter for a control VSI.
3329 * In return it will update the total number of perfect filter count in
3330 * the stats member.
3331 **/
3332 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3333 u8 *mac_addr, u16 ethtype, u16 flags,
3334 u16 vsi_seid, u16 queue, bool is_add,
3335 struct i40e_control_filter_stats *stats,
3336 struct i40e_asq_cmd_details *cmd_details)
3337 {
3338 struct i40e_aq_desc desc;
3339 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3340 (struct i40e_aqc_add_remove_control_packet_filter *)
3341 &desc.params.raw;
3342 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3343 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3344 &desc.params.raw;
3345 i40e_status status;
3346
3347 if (vsi_seid == 0)
3348 return I40E_ERR_PARAM;
3349
3350 if (is_add) {
3351 i40e_fill_default_direct_cmd_desc(&desc,
3352 i40e_aqc_opc_add_control_packet_filter);
3353 cmd->queue = cpu_to_le16(queue);
3354 } else {
3355 i40e_fill_default_direct_cmd_desc(&desc,
3356 i40e_aqc_opc_remove_control_packet_filter);
3357 }
3358
3359 if (mac_addr)
3360 memcpy(cmd->mac, mac_addr, ETH_ALEN);
3361
3362 cmd->etype = cpu_to_le16(ethtype);
3363 cmd->flags = cpu_to_le16(flags);
3364 cmd->seid = cpu_to_le16(vsi_seid);
3365
3366 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3367
3368 if (!status && stats) {
3369 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3370 stats->etype_used = le16_to_cpu(resp->etype_used);
3371 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3372 stats->etype_free = le16_to_cpu(resp->etype_free);
3373 }
3374
3375 return status;
3376 }
3377
3378 /**
3379 * i40e_aq_resume_port_tx
3380 * @hw: pointer to the hardware structure
3381 * @cmd_details: pointer to command details structure or NULL
3382 *
3383 * Resume port's Tx traffic
3384 **/
3385 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
3386 struct i40e_asq_cmd_details *cmd_details)
3387 {
3388 struct i40e_aq_desc desc;
3389 i40e_status status;
3390
3391 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
3392
3393 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3394
3395 return status;
3396 }
3397
3398 /**
3399 * i40e_set_pci_config_data - store PCI bus info
3400 * @hw: pointer to hardware structure
3401 * @link_status: the link status word from PCI config space
3402 *
3403 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3404 **/
3405 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
3406 {
3407 hw->bus.type = i40e_bus_type_pci_express;
3408
3409 switch (link_status & PCI_EXP_LNKSTA_NLW) {
3410 case PCI_EXP_LNKSTA_NLW_X1:
3411 hw->bus.width = i40e_bus_width_pcie_x1;
3412 break;
3413 case PCI_EXP_LNKSTA_NLW_X2:
3414 hw->bus.width = i40e_bus_width_pcie_x2;
3415 break;
3416 case PCI_EXP_LNKSTA_NLW_X4:
3417 hw->bus.width = i40e_bus_width_pcie_x4;
3418 break;
3419 case PCI_EXP_LNKSTA_NLW_X8:
3420 hw->bus.width = i40e_bus_width_pcie_x8;
3421 break;
3422 default:
3423 hw->bus.width = i40e_bus_width_unknown;
3424 break;
3425 }
3426
3427 switch (link_status & PCI_EXP_LNKSTA_CLS) {
3428 case PCI_EXP_LNKSTA_CLS_2_5GB:
3429 hw->bus.speed = i40e_bus_speed_2500;
3430 break;
3431 case PCI_EXP_LNKSTA_CLS_5_0GB:
3432 hw->bus.speed = i40e_bus_speed_5000;
3433 break;
3434 case PCI_EXP_LNKSTA_CLS_8_0GB:
3435 hw->bus.speed = i40e_bus_speed_8000;
3436 break;
3437 default:
3438 hw->bus.speed = i40e_bus_speed_unknown;
3439 break;
3440 }
3441 }
Linux kernel - Deliverables
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