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i40e: When in promisc mode apply promisc mode to Tx Traffic as well
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
31
32 /**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40 {
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
45 case I40E_DEV_ID_SFP_XL710:
46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_B:
48 case I40E_DEV_ID_KX_C:
49 case I40E_DEV_ID_QSFP_A:
50 case I40E_DEV_ID_QSFP_B:
51 case I40E_DEV_ID_QSFP_C:
52 case I40E_DEV_ID_10G_BASE_T:
53 case I40E_DEV_ID_10G_BASE_T4:
54 case I40E_DEV_ID_20G_KR2:
55 case I40E_DEV_ID_20G_KR2_A:
56 hw->mac.type = I40E_MAC_XL710;
57 break;
58 case I40E_DEV_ID_KX_X722:
59 case I40E_DEV_ID_QSFP_X722:
60 case I40E_DEV_ID_SFP_X722:
61 case I40E_DEV_ID_1G_BASE_T_X722:
62 case I40E_DEV_ID_10G_BASE_T_X722:
63 hw->mac.type = I40E_MAC_X722;
64 break;
65 default:
66 hw->mac.type = I40E_MAC_GENERIC;
67 break;
68 }
69 } else {
70 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
71 }
72
73 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
74 hw->mac.type, status);
75 return status;
76 }
77
78 /**
79 * i40e_aq_str - convert AQ err code to a string
80 * @hw: pointer to the HW structure
81 * @aq_err: the AQ error code to convert
82 **/
83 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
84 {
85 switch (aq_err) {
86 case I40E_AQ_RC_OK:
87 return "OK";
88 case I40E_AQ_RC_EPERM:
89 return "I40E_AQ_RC_EPERM";
90 case I40E_AQ_RC_ENOENT:
91 return "I40E_AQ_RC_ENOENT";
92 case I40E_AQ_RC_ESRCH:
93 return "I40E_AQ_RC_ESRCH";
94 case I40E_AQ_RC_EINTR:
95 return "I40E_AQ_RC_EINTR";
96 case I40E_AQ_RC_EIO:
97 return "I40E_AQ_RC_EIO";
98 case I40E_AQ_RC_ENXIO:
99 return "I40E_AQ_RC_ENXIO";
100 case I40E_AQ_RC_E2BIG:
101 return "I40E_AQ_RC_E2BIG";
102 case I40E_AQ_RC_EAGAIN:
103 return "I40E_AQ_RC_EAGAIN";
104 case I40E_AQ_RC_ENOMEM:
105 return "I40E_AQ_RC_ENOMEM";
106 case I40E_AQ_RC_EACCES:
107 return "I40E_AQ_RC_EACCES";
108 case I40E_AQ_RC_EFAULT:
109 return "I40E_AQ_RC_EFAULT";
110 case I40E_AQ_RC_EBUSY:
111 return "I40E_AQ_RC_EBUSY";
112 case I40E_AQ_RC_EEXIST:
113 return "I40E_AQ_RC_EEXIST";
114 case I40E_AQ_RC_EINVAL:
115 return "I40E_AQ_RC_EINVAL";
116 case I40E_AQ_RC_ENOTTY:
117 return "I40E_AQ_RC_ENOTTY";
118 case I40E_AQ_RC_ENOSPC:
119 return "I40E_AQ_RC_ENOSPC";
120 case I40E_AQ_RC_ENOSYS:
121 return "I40E_AQ_RC_ENOSYS";
122 case I40E_AQ_RC_ERANGE:
123 return "I40E_AQ_RC_ERANGE";
124 case I40E_AQ_RC_EFLUSHED:
125 return "I40E_AQ_RC_EFLUSHED";
126 case I40E_AQ_RC_BAD_ADDR:
127 return "I40E_AQ_RC_BAD_ADDR";
128 case I40E_AQ_RC_EMODE:
129 return "I40E_AQ_RC_EMODE";
130 case I40E_AQ_RC_EFBIG:
131 return "I40E_AQ_RC_EFBIG";
132 }
133
134 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
135 return hw->err_str;
136 }
137
138 /**
139 * i40e_stat_str - convert status err code to a string
140 * @hw: pointer to the HW structure
141 * @stat_err: the status error code to convert
142 **/
143 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
144 {
145 switch (stat_err) {
146 case 0:
147 return "OK";
148 case I40E_ERR_NVM:
149 return "I40E_ERR_NVM";
150 case I40E_ERR_NVM_CHECKSUM:
151 return "I40E_ERR_NVM_CHECKSUM";
152 case I40E_ERR_PHY:
153 return "I40E_ERR_PHY";
154 case I40E_ERR_CONFIG:
155 return "I40E_ERR_CONFIG";
156 case I40E_ERR_PARAM:
157 return "I40E_ERR_PARAM";
158 case I40E_ERR_MAC_TYPE:
159 return "I40E_ERR_MAC_TYPE";
160 case I40E_ERR_UNKNOWN_PHY:
161 return "I40E_ERR_UNKNOWN_PHY";
162 case I40E_ERR_LINK_SETUP:
163 return "I40E_ERR_LINK_SETUP";
164 case I40E_ERR_ADAPTER_STOPPED:
165 return "I40E_ERR_ADAPTER_STOPPED";
166 case I40E_ERR_INVALID_MAC_ADDR:
167 return "I40E_ERR_INVALID_MAC_ADDR";
168 case I40E_ERR_DEVICE_NOT_SUPPORTED:
169 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
170 case I40E_ERR_MASTER_REQUESTS_PENDING:
171 return "I40E_ERR_MASTER_REQUESTS_PENDING";
172 case I40E_ERR_INVALID_LINK_SETTINGS:
173 return "I40E_ERR_INVALID_LINK_SETTINGS";
174 case I40E_ERR_AUTONEG_NOT_COMPLETE:
175 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
176 case I40E_ERR_RESET_FAILED:
177 return "I40E_ERR_RESET_FAILED";
178 case I40E_ERR_SWFW_SYNC:
179 return "I40E_ERR_SWFW_SYNC";
180 case I40E_ERR_NO_AVAILABLE_VSI:
181 return "I40E_ERR_NO_AVAILABLE_VSI";
182 case I40E_ERR_NO_MEMORY:
183 return "I40E_ERR_NO_MEMORY";
184 case I40E_ERR_BAD_PTR:
185 return "I40E_ERR_BAD_PTR";
186 case I40E_ERR_RING_FULL:
187 return "I40E_ERR_RING_FULL";
188 case I40E_ERR_INVALID_PD_ID:
189 return "I40E_ERR_INVALID_PD_ID";
190 case I40E_ERR_INVALID_QP_ID:
191 return "I40E_ERR_INVALID_QP_ID";
192 case I40E_ERR_INVALID_CQ_ID:
193 return "I40E_ERR_INVALID_CQ_ID";
194 case I40E_ERR_INVALID_CEQ_ID:
195 return "I40E_ERR_INVALID_CEQ_ID";
196 case I40E_ERR_INVALID_AEQ_ID:
197 return "I40E_ERR_INVALID_AEQ_ID";
198 case I40E_ERR_INVALID_SIZE:
199 return "I40E_ERR_INVALID_SIZE";
200 case I40E_ERR_INVALID_ARP_INDEX:
201 return "I40E_ERR_INVALID_ARP_INDEX";
202 case I40E_ERR_INVALID_FPM_FUNC_ID:
203 return "I40E_ERR_INVALID_FPM_FUNC_ID";
204 case I40E_ERR_QP_INVALID_MSG_SIZE:
205 return "I40E_ERR_QP_INVALID_MSG_SIZE";
206 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
207 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
208 case I40E_ERR_INVALID_FRAG_COUNT:
209 return "I40E_ERR_INVALID_FRAG_COUNT";
210 case I40E_ERR_QUEUE_EMPTY:
211 return "I40E_ERR_QUEUE_EMPTY";
212 case I40E_ERR_INVALID_ALIGNMENT:
213 return "I40E_ERR_INVALID_ALIGNMENT";
214 case I40E_ERR_FLUSHED_QUEUE:
215 return "I40E_ERR_FLUSHED_QUEUE";
216 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
217 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
218 case I40E_ERR_INVALID_IMM_DATA_SIZE:
219 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
220 case I40E_ERR_TIMEOUT:
221 return "I40E_ERR_TIMEOUT";
222 case I40E_ERR_OPCODE_MISMATCH:
223 return "I40E_ERR_OPCODE_MISMATCH";
224 case I40E_ERR_CQP_COMPL_ERROR:
225 return "I40E_ERR_CQP_COMPL_ERROR";
226 case I40E_ERR_INVALID_VF_ID:
227 return "I40E_ERR_INVALID_VF_ID";
228 case I40E_ERR_INVALID_HMCFN_ID:
229 return "I40E_ERR_INVALID_HMCFN_ID";
230 case I40E_ERR_BACKING_PAGE_ERROR:
231 return "I40E_ERR_BACKING_PAGE_ERROR";
232 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
233 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
234 case I40E_ERR_INVALID_PBLE_INDEX:
235 return "I40E_ERR_INVALID_PBLE_INDEX";
236 case I40E_ERR_INVALID_SD_INDEX:
237 return "I40E_ERR_INVALID_SD_INDEX";
238 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
239 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
240 case I40E_ERR_INVALID_SD_TYPE:
241 return "I40E_ERR_INVALID_SD_TYPE";
242 case I40E_ERR_MEMCPY_FAILED:
243 return "I40E_ERR_MEMCPY_FAILED";
244 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
245 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
246 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
247 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
248 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
249 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
250 case I40E_ERR_SRQ_ENABLED:
251 return "I40E_ERR_SRQ_ENABLED";
252 case I40E_ERR_ADMIN_QUEUE_ERROR:
253 return "I40E_ERR_ADMIN_QUEUE_ERROR";
254 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
255 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
256 case I40E_ERR_BUF_TOO_SHORT:
257 return "I40E_ERR_BUF_TOO_SHORT";
258 case I40E_ERR_ADMIN_QUEUE_FULL:
259 return "I40E_ERR_ADMIN_QUEUE_FULL";
260 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
261 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
262 case I40E_ERR_BAD_IWARP_CQE:
263 return "I40E_ERR_BAD_IWARP_CQE";
264 case I40E_ERR_NVM_BLANK_MODE:
265 return "I40E_ERR_NVM_BLANK_MODE";
266 case I40E_ERR_NOT_IMPLEMENTED:
267 return "I40E_ERR_NOT_IMPLEMENTED";
268 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
269 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
270 case I40E_ERR_DIAG_TEST_FAILED:
271 return "I40E_ERR_DIAG_TEST_FAILED";
272 case I40E_ERR_NOT_READY:
273 return "I40E_ERR_NOT_READY";
274 case I40E_NOT_SUPPORTED:
275 return "I40E_NOT_SUPPORTED";
276 case I40E_ERR_FIRMWARE_API_VERSION:
277 return "I40E_ERR_FIRMWARE_API_VERSION";
278 }
279
280 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
281 return hw->err_str;
282 }
283
284 /**
285 * i40e_debug_aq
286 * @hw: debug mask related to admin queue
287 * @mask: debug mask
288 * @desc: pointer to admin queue descriptor
289 * @buffer: pointer to command buffer
290 * @buf_len: max length of buffer
291 *
292 * Dumps debug log about adminq command with descriptor contents.
293 **/
294 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
295 void *buffer, u16 buf_len)
296 {
297 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
298 u16 len = le16_to_cpu(aq_desc->datalen);
299 u8 *buf = (u8 *)buffer;
300 u16 i = 0;
301
302 if ((!(mask & hw->debug_mask)) || (desc == NULL))
303 return;
304
305 i40e_debug(hw, mask,
306 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
307 le16_to_cpu(aq_desc->opcode),
308 le16_to_cpu(aq_desc->flags),
309 le16_to_cpu(aq_desc->datalen),
310 le16_to_cpu(aq_desc->retval));
311 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
312 le32_to_cpu(aq_desc->cookie_high),
313 le32_to_cpu(aq_desc->cookie_low));
314 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
315 le32_to_cpu(aq_desc->params.internal.param0),
316 le32_to_cpu(aq_desc->params.internal.param1));
317 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
318 le32_to_cpu(aq_desc->params.external.addr_high),
319 le32_to_cpu(aq_desc->params.external.addr_low));
320
321 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
322 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
323 if (buf_len < len)
324 len = buf_len;
325 /* write the full 16-byte chunks */
326 for (i = 0; i < (len - 16); i += 16)
327 i40e_debug(hw, mask, "\t0x%04X %16ph\n", i, buf + i);
328 /* write whatever's left over without overrunning the buffer */
329 if (i < len)
330 i40e_debug(hw, mask, "\t0x%04X %*ph\n",
331 i, len - i, buf + i);
332 }
333 }
334
335 /**
336 * i40e_check_asq_alive
337 * @hw: pointer to the hw struct
338 *
339 * Returns true if Queue is enabled else false.
340 **/
341 bool i40e_check_asq_alive(struct i40e_hw *hw)
342 {
343 if (hw->aq.asq.len)
344 return !!(rd32(hw, hw->aq.asq.len) &
345 I40E_PF_ATQLEN_ATQENABLE_MASK);
346 else
347 return false;
348 }
349
350 /**
351 * i40e_aq_queue_shutdown
352 * @hw: pointer to the hw struct
353 * @unloading: is the driver unloading itself
354 *
355 * Tell the Firmware that we're shutting down the AdminQ and whether
356 * or not the driver is unloading as well.
357 **/
358 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
359 bool unloading)
360 {
361 struct i40e_aq_desc desc;
362 struct i40e_aqc_queue_shutdown *cmd =
363 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
364 i40e_status status;
365
366 i40e_fill_default_direct_cmd_desc(&desc,
367 i40e_aqc_opc_queue_shutdown);
368
369 if (unloading)
370 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
371 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
372
373 return status;
374 }
375
376 /**
377 * i40e_aq_get_set_rss_lut
378 * @hw: pointer to the hardware structure
379 * @vsi_id: vsi fw index
380 * @pf_lut: for PF table set true, for VSI table set false
381 * @lut: pointer to the lut buffer provided by the caller
382 * @lut_size: size of the lut buffer
383 * @set: set true to set the table, false to get the table
384 *
385 * Internal function to get or set RSS look up table
386 **/
387 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
388 u16 vsi_id, bool pf_lut,
389 u8 *lut, u16 lut_size,
390 bool set)
391 {
392 i40e_status status;
393 struct i40e_aq_desc desc;
394 struct i40e_aqc_get_set_rss_lut *cmd_resp =
395 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
396
397 if (set)
398 i40e_fill_default_direct_cmd_desc(&desc,
399 i40e_aqc_opc_set_rss_lut);
400 else
401 i40e_fill_default_direct_cmd_desc(&desc,
402 i40e_aqc_opc_get_rss_lut);
403
404 /* Indirect command */
405 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
406 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
407
408 cmd_resp->vsi_id =
409 cpu_to_le16((u16)((vsi_id <<
410 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
411 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
412 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
413
414 if (pf_lut)
415 cmd_resp->flags |= cpu_to_le16((u16)
416 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
417 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
418 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
419 else
420 cmd_resp->flags |= cpu_to_le16((u16)
421 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
422 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
423 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
424
425 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
426
427 return status;
428 }
429
430 /**
431 * i40e_aq_get_rss_lut
432 * @hw: pointer to the hardware structure
433 * @vsi_id: vsi fw index
434 * @pf_lut: for PF table set true, for VSI table set false
435 * @lut: pointer to the lut buffer provided by the caller
436 * @lut_size: size of the lut buffer
437 *
438 * get the RSS lookup table, PF or VSI type
439 **/
440 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
441 bool pf_lut, u8 *lut, u16 lut_size)
442 {
443 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
444 false);
445 }
446
447 /**
448 * i40e_aq_set_rss_lut
449 * @hw: pointer to the hardware structure
450 * @vsi_id: vsi fw index
451 * @pf_lut: for PF table set true, for VSI table set false
452 * @lut: pointer to the lut buffer provided by the caller
453 * @lut_size: size of the lut buffer
454 *
455 * set the RSS lookup table, PF or VSI type
456 **/
457 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
458 bool pf_lut, u8 *lut, u16 lut_size)
459 {
460 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
461 }
462
463 /**
464 * i40e_aq_get_set_rss_key
465 * @hw: pointer to the hw struct
466 * @vsi_id: vsi fw index
467 * @key: pointer to key info struct
468 * @set: set true to set the key, false to get the key
469 *
470 * get the RSS key per VSI
471 **/
472 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
473 u16 vsi_id,
474 struct i40e_aqc_get_set_rss_key_data *key,
475 bool set)
476 {
477 i40e_status status;
478 struct i40e_aq_desc desc;
479 struct i40e_aqc_get_set_rss_key *cmd_resp =
480 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
481 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
482
483 if (set)
484 i40e_fill_default_direct_cmd_desc(&desc,
485 i40e_aqc_opc_set_rss_key);
486 else
487 i40e_fill_default_direct_cmd_desc(&desc,
488 i40e_aqc_opc_get_rss_key);
489
490 /* Indirect command */
491 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
492 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
493
494 cmd_resp->vsi_id =
495 cpu_to_le16((u16)((vsi_id <<
496 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
497 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
498 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
499
500 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
501
502 return status;
503 }
504
505 /**
506 * i40e_aq_get_rss_key
507 * @hw: pointer to the hw struct
508 * @vsi_id: vsi fw index
509 * @key: pointer to key info struct
510 *
511 **/
512 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
513 u16 vsi_id,
514 struct i40e_aqc_get_set_rss_key_data *key)
515 {
516 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
517 }
518
519 /**
520 * i40e_aq_set_rss_key
521 * @hw: pointer to the hw struct
522 * @vsi_id: vsi fw index
523 * @key: pointer to key info struct
524 *
525 * set the RSS key per VSI
526 **/
527 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
528 u16 vsi_id,
529 struct i40e_aqc_get_set_rss_key_data *key)
530 {
531 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
532 }
533
534 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
535 * hardware to a bit-field that can be used by SW to more easily determine the
536 * packet type.
537 *
538 * Macros are used to shorten the table lines and make this table human
539 * readable.
540 *
541 * We store the PTYPE in the top byte of the bit field - this is just so that
542 * we can check that the table doesn't have a row missing, as the index into
543 * the table should be the PTYPE.
544 *
545 * Typical work flow:
546 *
547 * IF NOT i40e_ptype_lookup[ptype].known
548 * THEN
549 * Packet is unknown
550 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
551 * Use the rest of the fields to look at the tunnels, inner protocols, etc
552 * ELSE
553 * Use the enum i40e_rx_l2_ptype to decode the packet type
554 * ENDIF
555 */
556
557 /* macro to make the table lines short */
558 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
559 { PTYPE, \
560 1, \
561 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
562 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
563 I40E_RX_PTYPE_##OUTER_FRAG, \
564 I40E_RX_PTYPE_TUNNEL_##T, \
565 I40E_RX_PTYPE_TUNNEL_END_##TE, \
566 I40E_RX_PTYPE_##TEF, \
567 I40E_RX_PTYPE_INNER_PROT_##I, \
568 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
569
570 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
571 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
572
573 /* shorter macros makes the table fit but are terse */
574 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
575 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
576 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
577
578 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
579 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
580 /* L2 Packet types */
581 I40E_PTT_UNUSED_ENTRY(0),
582 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
583 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
584 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
585 I40E_PTT_UNUSED_ENTRY(4),
586 I40E_PTT_UNUSED_ENTRY(5),
587 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
588 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
589 I40E_PTT_UNUSED_ENTRY(8),
590 I40E_PTT_UNUSED_ENTRY(9),
591 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
592 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
593 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
594 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
595 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
596 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
597 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
598 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
599 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
600 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
601 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
602 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
603
604 /* Non Tunneled IPv4 */
605 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
606 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
607 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
608 I40E_PTT_UNUSED_ENTRY(25),
609 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
610 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
611 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
612
613 /* IPv4 --> IPv4 */
614 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
615 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
616 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
617 I40E_PTT_UNUSED_ENTRY(32),
618 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
619 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
620 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
621
622 /* IPv4 --> IPv6 */
623 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
624 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
625 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
626 I40E_PTT_UNUSED_ENTRY(39),
627 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
628 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
629 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
630
631 /* IPv4 --> GRE/NAT */
632 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
633
634 /* IPv4 --> GRE/NAT --> IPv4 */
635 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
636 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
637 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
638 I40E_PTT_UNUSED_ENTRY(47),
639 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
640 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
641 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
642
643 /* IPv4 --> GRE/NAT --> IPv6 */
644 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
645 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
646 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
647 I40E_PTT_UNUSED_ENTRY(54),
648 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
649 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
650 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
651
652 /* IPv4 --> GRE/NAT --> MAC */
653 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
654
655 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
656 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
657 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
658 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
659 I40E_PTT_UNUSED_ENTRY(62),
660 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
661 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
662 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
663
664 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
665 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
666 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
667 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
668 I40E_PTT_UNUSED_ENTRY(69),
669 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
670 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
671 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
672
673 /* IPv4 --> GRE/NAT --> MAC/VLAN */
674 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
675
676 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
677 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
678 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
679 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
680 I40E_PTT_UNUSED_ENTRY(77),
681 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
682 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
683 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
684
685 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
686 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
687 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
688 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
689 I40E_PTT_UNUSED_ENTRY(84),
690 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
691 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
692 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
693
694 /* Non Tunneled IPv6 */
695 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
696 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
697 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
698 I40E_PTT_UNUSED_ENTRY(91),
699 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
700 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
701 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
702
703 /* IPv6 --> IPv4 */
704 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
705 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
706 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
707 I40E_PTT_UNUSED_ENTRY(98),
708 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
709 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
710 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
711
712 /* IPv6 --> IPv6 */
713 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
714 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
715 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
716 I40E_PTT_UNUSED_ENTRY(105),
717 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
718 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
719 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
720
721 /* IPv6 --> GRE/NAT */
722 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
723
724 /* IPv6 --> GRE/NAT -> IPv4 */
725 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
726 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
727 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
728 I40E_PTT_UNUSED_ENTRY(113),
729 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
730 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
731 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
732
733 /* IPv6 --> GRE/NAT -> IPv6 */
734 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
735 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
736 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
737 I40E_PTT_UNUSED_ENTRY(120),
738 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
739 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
740 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
741
742 /* IPv6 --> GRE/NAT -> MAC */
743 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
744
745 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
746 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
747 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
748 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
749 I40E_PTT_UNUSED_ENTRY(128),
750 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
751 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
752 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
753
754 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
755 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
756 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
757 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
758 I40E_PTT_UNUSED_ENTRY(135),
759 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
760 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
761 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
762
763 /* IPv6 --> GRE/NAT -> MAC/VLAN */
764 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
765
766 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
767 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
768 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
769 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
770 I40E_PTT_UNUSED_ENTRY(143),
771 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
772 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
773 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
774
775 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
776 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
777 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
778 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
779 I40E_PTT_UNUSED_ENTRY(150),
780 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
781 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
782 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
783
784 /* unused entries */
785 I40E_PTT_UNUSED_ENTRY(154),
786 I40E_PTT_UNUSED_ENTRY(155),
787 I40E_PTT_UNUSED_ENTRY(156),
788 I40E_PTT_UNUSED_ENTRY(157),
789 I40E_PTT_UNUSED_ENTRY(158),
790 I40E_PTT_UNUSED_ENTRY(159),
791
792 I40E_PTT_UNUSED_ENTRY(160),
793 I40E_PTT_UNUSED_ENTRY(161),
794 I40E_PTT_UNUSED_ENTRY(162),
795 I40E_PTT_UNUSED_ENTRY(163),
796 I40E_PTT_UNUSED_ENTRY(164),
797 I40E_PTT_UNUSED_ENTRY(165),
798 I40E_PTT_UNUSED_ENTRY(166),
799 I40E_PTT_UNUSED_ENTRY(167),
800 I40E_PTT_UNUSED_ENTRY(168),
801 I40E_PTT_UNUSED_ENTRY(169),
802
803 I40E_PTT_UNUSED_ENTRY(170),
804 I40E_PTT_UNUSED_ENTRY(171),
805 I40E_PTT_UNUSED_ENTRY(172),
806 I40E_PTT_UNUSED_ENTRY(173),
807 I40E_PTT_UNUSED_ENTRY(174),
808 I40E_PTT_UNUSED_ENTRY(175),
809 I40E_PTT_UNUSED_ENTRY(176),
810 I40E_PTT_UNUSED_ENTRY(177),
811 I40E_PTT_UNUSED_ENTRY(178),
812 I40E_PTT_UNUSED_ENTRY(179),
813
814 I40E_PTT_UNUSED_ENTRY(180),
815 I40E_PTT_UNUSED_ENTRY(181),
816 I40E_PTT_UNUSED_ENTRY(182),
817 I40E_PTT_UNUSED_ENTRY(183),
818 I40E_PTT_UNUSED_ENTRY(184),
819 I40E_PTT_UNUSED_ENTRY(185),
820 I40E_PTT_UNUSED_ENTRY(186),
821 I40E_PTT_UNUSED_ENTRY(187),
822 I40E_PTT_UNUSED_ENTRY(188),
823 I40E_PTT_UNUSED_ENTRY(189),
824
825 I40E_PTT_UNUSED_ENTRY(190),
826 I40E_PTT_UNUSED_ENTRY(191),
827 I40E_PTT_UNUSED_ENTRY(192),
828 I40E_PTT_UNUSED_ENTRY(193),
829 I40E_PTT_UNUSED_ENTRY(194),
830 I40E_PTT_UNUSED_ENTRY(195),
831 I40E_PTT_UNUSED_ENTRY(196),
832 I40E_PTT_UNUSED_ENTRY(197),
833 I40E_PTT_UNUSED_ENTRY(198),
834 I40E_PTT_UNUSED_ENTRY(199),
835
836 I40E_PTT_UNUSED_ENTRY(200),
837 I40E_PTT_UNUSED_ENTRY(201),
838 I40E_PTT_UNUSED_ENTRY(202),
839 I40E_PTT_UNUSED_ENTRY(203),
840 I40E_PTT_UNUSED_ENTRY(204),
841 I40E_PTT_UNUSED_ENTRY(205),
842 I40E_PTT_UNUSED_ENTRY(206),
843 I40E_PTT_UNUSED_ENTRY(207),
844 I40E_PTT_UNUSED_ENTRY(208),
845 I40E_PTT_UNUSED_ENTRY(209),
846
847 I40E_PTT_UNUSED_ENTRY(210),
848 I40E_PTT_UNUSED_ENTRY(211),
849 I40E_PTT_UNUSED_ENTRY(212),
850 I40E_PTT_UNUSED_ENTRY(213),
851 I40E_PTT_UNUSED_ENTRY(214),
852 I40E_PTT_UNUSED_ENTRY(215),
853 I40E_PTT_UNUSED_ENTRY(216),
854 I40E_PTT_UNUSED_ENTRY(217),
855 I40E_PTT_UNUSED_ENTRY(218),
856 I40E_PTT_UNUSED_ENTRY(219),
857
858 I40E_PTT_UNUSED_ENTRY(220),
859 I40E_PTT_UNUSED_ENTRY(221),
860 I40E_PTT_UNUSED_ENTRY(222),
861 I40E_PTT_UNUSED_ENTRY(223),
862 I40E_PTT_UNUSED_ENTRY(224),
863 I40E_PTT_UNUSED_ENTRY(225),
864 I40E_PTT_UNUSED_ENTRY(226),
865 I40E_PTT_UNUSED_ENTRY(227),
866 I40E_PTT_UNUSED_ENTRY(228),
867 I40E_PTT_UNUSED_ENTRY(229),
868
869 I40E_PTT_UNUSED_ENTRY(230),
870 I40E_PTT_UNUSED_ENTRY(231),
871 I40E_PTT_UNUSED_ENTRY(232),
872 I40E_PTT_UNUSED_ENTRY(233),
873 I40E_PTT_UNUSED_ENTRY(234),
874 I40E_PTT_UNUSED_ENTRY(235),
875 I40E_PTT_UNUSED_ENTRY(236),
876 I40E_PTT_UNUSED_ENTRY(237),
877 I40E_PTT_UNUSED_ENTRY(238),
878 I40E_PTT_UNUSED_ENTRY(239),
879
880 I40E_PTT_UNUSED_ENTRY(240),
881 I40E_PTT_UNUSED_ENTRY(241),
882 I40E_PTT_UNUSED_ENTRY(242),
883 I40E_PTT_UNUSED_ENTRY(243),
884 I40E_PTT_UNUSED_ENTRY(244),
885 I40E_PTT_UNUSED_ENTRY(245),
886 I40E_PTT_UNUSED_ENTRY(246),
887 I40E_PTT_UNUSED_ENTRY(247),
888 I40E_PTT_UNUSED_ENTRY(248),
889 I40E_PTT_UNUSED_ENTRY(249),
890
891 I40E_PTT_UNUSED_ENTRY(250),
892 I40E_PTT_UNUSED_ENTRY(251),
893 I40E_PTT_UNUSED_ENTRY(252),
894 I40E_PTT_UNUSED_ENTRY(253),
895 I40E_PTT_UNUSED_ENTRY(254),
896 I40E_PTT_UNUSED_ENTRY(255)
897 };
898
899 /**
900 * i40e_init_shared_code - Initialize the shared code
901 * @hw: pointer to hardware structure
902 *
903 * This assigns the MAC type and PHY code and inits the NVM.
904 * Does not touch the hardware. This function must be called prior to any
905 * other function in the shared code. The i40e_hw structure should be
906 * memset to 0 prior to calling this function. The following fields in
907 * hw structure should be filled in prior to calling this function:
908 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
909 * subsystem_vendor_id, and revision_id
910 **/
911 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
912 {
913 i40e_status status = 0;
914 u32 port, ari, func_rid;
915
916 i40e_set_mac_type(hw);
917
918 switch (hw->mac.type) {
919 case I40E_MAC_XL710:
920 case I40E_MAC_X722:
921 break;
922 default:
923 return I40E_ERR_DEVICE_NOT_SUPPORTED;
924 }
925
926 hw->phy.get_link_info = true;
927
928 /* Determine port number and PF number*/
929 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
930 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
931 hw->port = (u8)port;
932 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
933 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
934 func_rid = rd32(hw, I40E_PF_FUNC_RID);
935 if (ari)
936 hw->pf_id = (u8)(func_rid & 0xff);
937 else
938 hw->pf_id = (u8)(func_rid & 0x7);
939
940 if (hw->mac.type == I40E_MAC_X722)
941 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
942
943 status = i40e_init_nvm(hw);
944 return status;
945 }
946
947 /**
948 * i40e_aq_mac_address_read - Retrieve the MAC addresses
949 * @hw: pointer to the hw struct
950 * @flags: a return indicator of what addresses were added to the addr store
951 * @addrs: the requestor's mac addr store
952 * @cmd_details: pointer to command details structure or NULL
953 **/
954 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
955 u16 *flags,
956 struct i40e_aqc_mac_address_read_data *addrs,
957 struct i40e_asq_cmd_details *cmd_details)
958 {
959 struct i40e_aq_desc desc;
960 struct i40e_aqc_mac_address_read *cmd_data =
961 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
962 i40e_status status;
963
964 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
965 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
966
967 status = i40e_asq_send_command(hw, &desc, addrs,
968 sizeof(*addrs), cmd_details);
969 *flags = le16_to_cpu(cmd_data->command_flags);
970
971 return status;
972 }
973
974 /**
975 * i40e_aq_mac_address_write - Change the MAC addresses
976 * @hw: pointer to the hw struct
977 * @flags: indicates which MAC to be written
978 * @mac_addr: address to write
979 * @cmd_details: pointer to command details structure or NULL
980 **/
981 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
982 u16 flags, u8 *mac_addr,
983 struct i40e_asq_cmd_details *cmd_details)
984 {
985 struct i40e_aq_desc desc;
986 struct i40e_aqc_mac_address_write *cmd_data =
987 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
988 i40e_status status;
989
990 i40e_fill_default_direct_cmd_desc(&desc,
991 i40e_aqc_opc_mac_address_write);
992 cmd_data->command_flags = cpu_to_le16(flags);
993 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
994 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
995 ((u32)mac_addr[3] << 16) |
996 ((u32)mac_addr[4] << 8) |
997 mac_addr[5]);
998
999 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1000
1001 return status;
1002 }
1003
1004 /**
1005 * i40e_get_mac_addr - get MAC address
1006 * @hw: pointer to the HW structure
1007 * @mac_addr: pointer to MAC address
1008 *
1009 * Reads the adapter's MAC address from register
1010 **/
1011 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1012 {
1013 struct i40e_aqc_mac_address_read_data addrs;
1014 i40e_status status;
1015 u16 flags = 0;
1016
1017 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1018
1019 if (flags & I40E_AQC_LAN_ADDR_VALID)
1020 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
1021
1022 return status;
1023 }
1024
1025 /**
1026 * i40e_get_port_mac_addr - get Port MAC address
1027 * @hw: pointer to the HW structure
1028 * @mac_addr: pointer to Port MAC address
1029 *
1030 * Reads the adapter's Port MAC address
1031 **/
1032 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1033 {
1034 struct i40e_aqc_mac_address_read_data addrs;
1035 i40e_status status;
1036 u16 flags = 0;
1037
1038 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1039 if (status)
1040 return status;
1041
1042 if (flags & I40E_AQC_PORT_ADDR_VALID)
1043 ether_addr_copy(mac_addr, addrs.port_mac);
1044 else
1045 status = I40E_ERR_INVALID_MAC_ADDR;
1046
1047 return status;
1048 }
1049
1050 /**
1051 * i40e_pre_tx_queue_cfg - pre tx queue configure
1052 * @hw: pointer to the HW structure
1053 * @queue: target PF queue index
1054 * @enable: state change request
1055 *
1056 * Handles hw requirement to indicate intention to enable
1057 * or disable target queue.
1058 **/
1059 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1060 {
1061 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1062 u32 reg_block = 0;
1063 u32 reg_val;
1064
1065 if (abs_queue_idx >= 128) {
1066 reg_block = abs_queue_idx / 128;
1067 abs_queue_idx %= 128;
1068 }
1069
1070 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1071 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1072 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1073
1074 if (enable)
1075 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1076 else
1077 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1078
1079 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1080 }
1081 #ifdef I40E_FCOE
1082
1083 /**
1084 * i40e_get_san_mac_addr - get SAN MAC address
1085 * @hw: pointer to the HW structure
1086 * @mac_addr: pointer to SAN MAC address
1087 *
1088 * Reads the adapter's SAN MAC address from NVM
1089 **/
1090 i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1091 {
1092 struct i40e_aqc_mac_address_read_data addrs;
1093 i40e_status status;
1094 u16 flags = 0;
1095
1096 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1097 if (status)
1098 return status;
1099
1100 if (flags & I40E_AQC_SAN_ADDR_VALID)
1101 ether_addr_copy(mac_addr, addrs.pf_san_mac);
1102 else
1103 status = I40E_ERR_INVALID_MAC_ADDR;
1104
1105 return status;
1106 }
1107 #endif
1108
1109 /**
1110 * i40e_read_pba_string - Reads part number string from EEPROM
1111 * @hw: pointer to hardware structure
1112 * @pba_num: stores the part number string from the EEPROM
1113 * @pba_num_size: part number string buffer length
1114 *
1115 * Reads the part number string from the EEPROM.
1116 **/
1117 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1118 u32 pba_num_size)
1119 {
1120 i40e_status status = 0;
1121 u16 pba_word = 0;
1122 u16 pba_size = 0;
1123 u16 pba_ptr = 0;
1124 u16 i = 0;
1125
1126 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1127 if (status || (pba_word != 0xFAFA)) {
1128 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1129 return status;
1130 }
1131
1132 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1133 if (status) {
1134 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1135 return status;
1136 }
1137
1138 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1139 if (status) {
1140 hw_dbg(hw, "Failed to read PBA Block size.\n");
1141 return status;
1142 }
1143
1144 /* Subtract one to get PBA word count (PBA Size word is included in
1145 * total size)
1146 */
1147 pba_size--;
1148 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1149 hw_dbg(hw, "Buffer to small for PBA data.\n");
1150 return I40E_ERR_PARAM;
1151 }
1152
1153 for (i = 0; i < pba_size; i++) {
1154 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1155 if (status) {
1156 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1157 return status;
1158 }
1159
1160 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1161 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1162 }
1163 pba_num[(pba_size * 2)] = '\0';
1164
1165 return status;
1166 }
1167
1168 /**
1169 * i40e_get_media_type - Gets media type
1170 * @hw: pointer to the hardware structure
1171 **/
1172 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1173 {
1174 enum i40e_media_type media;
1175
1176 switch (hw->phy.link_info.phy_type) {
1177 case I40E_PHY_TYPE_10GBASE_SR:
1178 case I40E_PHY_TYPE_10GBASE_LR:
1179 case I40E_PHY_TYPE_1000BASE_SX:
1180 case I40E_PHY_TYPE_1000BASE_LX:
1181 case I40E_PHY_TYPE_40GBASE_SR4:
1182 case I40E_PHY_TYPE_40GBASE_LR4:
1183 media = I40E_MEDIA_TYPE_FIBER;
1184 break;
1185 case I40E_PHY_TYPE_100BASE_TX:
1186 case I40E_PHY_TYPE_1000BASE_T:
1187 case I40E_PHY_TYPE_10GBASE_T:
1188 media = I40E_MEDIA_TYPE_BASET;
1189 break;
1190 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1191 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1192 case I40E_PHY_TYPE_10GBASE_CR1:
1193 case I40E_PHY_TYPE_40GBASE_CR4:
1194 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1195 case I40E_PHY_TYPE_40GBASE_AOC:
1196 case I40E_PHY_TYPE_10GBASE_AOC:
1197 media = I40E_MEDIA_TYPE_DA;
1198 break;
1199 case I40E_PHY_TYPE_1000BASE_KX:
1200 case I40E_PHY_TYPE_10GBASE_KX4:
1201 case I40E_PHY_TYPE_10GBASE_KR:
1202 case I40E_PHY_TYPE_40GBASE_KR4:
1203 case I40E_PHY_TYPE_20GBASE_KR2:
1204 media = I40E_MEDIA_TYPE_BACKPLANE;
1205 break;
1206 case I40E_PHY_TYPE_SGMII:
1207 case I40E_PHY_TYPE_XAUI:
1208 case I40E_PHY_TYPE_XFI:
1209 case I40E_PHY_TYPE_XLAUI:
1210 case I40E_PHY_TYPE_XLPPI:
1211 default:
1212 media = I40E_MEDIA_TYPE_UNKNOWN;
1213 break;
1214 }
1215
1216 return media;
1217 }
1218
1219 #define I40E_PF_RESET_WAIT_COUNT_A0 200
1220 #define I40E_PF_RESET_WAIT_COUNT 200
1221 /**
1222 * i40e_pf_reset - Reset the PF
1223 * @hw: pointer to the hardware structure
1224 *
1225 * Assuming someone else has triggered a global reset,
1226 * assure the global reset is complete and then reset the PF
1227 **/
1228 i40e_status i40e_pf_reset(struct i40e_hw *hw)
1229 {
1230 u32 cnt = 0;
1231 u32 cnt1 = 0;
1232 u32 reg = 0;
1233 u32 grst_del;
1234
1235 /* Poll for Global Reset steady state in case of recent GRST.
1236 * The grst delay value is in 100ms units, and we'll wait a
1237 * couple counts longer to be sure we don't just miss the end.
1238 */
1239 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1240 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1241 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1242 for (cnt = 0; cnt < grst_del + 10; cnt++) {
1243 reg = rd32(hw, I40E_GLGEN_RSTAT);
1244 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1245 break;
1246 msleep(100);
1247 }
1248 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1249 hw_dbg(hw, "Global reset polling failed to complete.\n");
1250 return I40E_ERR_RESET_FAILED;
1251 }
1252
1253 /* Now Wait for the FW to be ready */
1254 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1255 reg = rd32(hw, I40E_GLNVM_ULD);
1256 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1257 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1258 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1259 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1260 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1261 break;
1262 }
1263 usleep_range(10000, 20000);
1264 }
1265 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1266 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1267 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1268 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1269 return I40E_ERR_RESET_FAILED;
1270 }
1271
1272 /* If there was a Global Reset in progress when we got here,
1273 * we don't need to do the PF Reset
1274 */
1275 if (!cnt) {
1276 if (hw->revision_id == 0)
1277 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1278 else
1279 cnt = I40E_PF_RESET_WAIT_COUNT;
1280 reg = rd32(hw, I40E_PFGEN_CTRL);
1281 wr32(hw, I40E_PFGEN_CTRL,
1282 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1283 for (; cnt; cnt--) {
1284 reg = rd32(hw, I40E_PFGEN_CTRL);
1285 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1286 break;
1287 usleep_range(1000, 2000);
1288 }
1289 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1290 hw_dbg(hw, "PF reset polling failed to complete.\n");
1291 return I40E_ERR_RESET_FAILED;
1292 }
1293 }
1294
1295 i40e_clear_pxe_mode(hw);
1296
1297 return 0;
1298 }
1299
1300 /**
1301 * i40e_clear_hw - clear out any left over hw state
1302 * @hw: pointer to the hw struct
1303 *
1304 * Clear queues and interrupts, typically called at init time,
1305 * but after the capabilities have been found so we know how many
1306 * queues and msix vectors have been allocated.
1307 **/
1308 void i40e_clear_hw(struct i40e_hw *hw)
1309 {
1310 u32 num_queues, base_queue;
1311 u32 num_pf_int;
1312 u32 num_vf_int;
1313 u32 num_vfs;
1314 u32 i, j;
1315 u32 val;
1316 u32 eol = 0x7ff;
1317
1318 /* get number of interrupts, queues, and VFs */
1319 val = rd32(hw, I40E_GLPCI_CNF2);
1320 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1321 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1322 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1323 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1324
1325 val = rd32(hw, I40E_PFLAN_QALLOC);
1326 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1327 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1328 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1329 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1330 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1331 num_queues = (j - base_queue) + 1;
1332 else
1333 num_queues = 0;
1334
1335 val = rd32(hw, I40E_PF_VT_PFALLOC);
1336 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1337 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1338 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1339 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1340 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1341 num_vfs = (j - i) + 1;
1342 else
1343 num_vfs = 0;
1344
1345 /* stop all the interrupts */
1346 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1347 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1348 for (i = 0; i < num_pf_int - 2; i++)
1349 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1350
1351 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1352 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1353 wr32(hw, I40E_PFINT_LNKLST0, val);
1354 for (i = 0; i < num_pf_int - 2; i++)
1355 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1356 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1357 for (i = 0; i < num_vfs; i++)
1358 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1359 for (i = 0; i < num_vf_int - 2; i++)
1360 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1361
1362 /* warn the HW of the coming Tx disables */
1363 for (i = 0; i < num_queues; i++) {
1364 u32 abs_queue_idx = base_queue + i;
1365 u32 reg_block = 0;
1366
1367 if (abs_queue_idx >= 128) {
1368 reg_block = abs_queue_idx / 128;
1369 abs_queue_idx %= 128;
1370 }
1371
1372 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1373 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1374 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1375 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1376
1377 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1378 }
1379 udelay(400);
1380
1381 /* stop all the queues */
1382 for (i = 0; i < num_queues; i++) {
1383 wr32(hw, I40E_QINT_TQCTL(i), 0);
1384 wr32(hw, I40E_QTX_ENA(i), 0);
1385 wr32(hw, I40E_QINT_RQCTL(i), 0);
1386 wr32(hw, I40E_QRX_ENA(i), 0);
1387 }
1388
1389 /* short wait for all queue disables to settle */
1390 udelay(50);
1391 }
1392
1393 /**
1394 * i40e_clear_pxe_mode - clear pxe operations mode
1395 * @hw: pointer to the hw struct
1396 *
1397 * Make sure all PXE mode settings are cleared, including things
1398 * like descriptor fetch/write-back mode.
1399 **/
1400 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1401 {
1402 u32 reg;
1403
1404 if (i40e_check_asq_alive(hw))
1405 i40e_aq_clear_pxe_mode(hw, NULL);
1406
1407 /* Clear single descriptor fetch/write-back mode */
1408 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1409
1410 if (hw->revision_id == 0) {
1411 /* As a work around clear PXE_MODE instead of setting it */
1412 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1413 } else {
1414 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1415 }
1416 }
1417
1418 /**
1419 * i40e_led_is_mine - helper to find matching led
1420 * @hw: pointer to the hw struct
1421 * @idx: index into GPIO registers
1422 *
1423 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1424 */
1425 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1426 {
1427 u32 gpio_val = 0;
1428 u32 port;
1429
1430 if (!hw->func_caps.led[idx])
1431 return 0;
1432
1433 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1434 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1435 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1436
1437 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1438 * if it is not our port then ignore
1439 */
1440 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1441 (port != hw->port))
1442 return 0;
1443
1444 return gpio_val;
1445 }
1446
1447 #define I40E_COMBINED_ACTIVITY 0xA
1448 #define I40E_FILTER_ACTIVITY 0xE
1449 #define I40E_LINK_ACTIVITY 0xC
1450 #define I40E_MAC_ACTIVITY 0xD
1451 #define I40E_LED0 22
1452
1453 /**
1454 * i40e_led_get - return current on/off mode
1455 * @hw: pointer to the hw struct
1456 *
1457 * The value returned is the 'mode' field as defined in the
1458 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1459 * values are variations of possible behaviors relating to
1460 * blink, link, and wire.
1461 **/
1462 u32 i40e_led_get(struct i40e_hw *hw)
1463 {
1464 u32 current_mode = 0;
1465 u32 mode = 0;
1466 int i;
1467
1468 /* as per the documentation GPIO 22-29 are the LED
1469 * GPIO pins named LED0..LED7
1470 */
1471 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1472 u32 gpio_val = i40e_led_is_mine(hw, i);
1473
1474 if (!gpio_val)
1475 continue;
1476
1477 /* ignore gpio LED src mode entries related to the activity
1478 * LEDs
1479 */
1480 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1481 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1482 switch (current_mode) {
1483 case I40E_COMBINED_ACTIVITY:
1484 case I40E_FILTER_ACTIVITY:
1485 case I40E_MAC_ACTIVITY:
1486 continue;
1487 default:
1488 break;
1489 }
1490
1491 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1492 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1493 break;
1494 }
1495
1496 return mode;
1497 }
1498
1499 /**
1500 * i40e_led_set - set new on/off mode
1501 * @hw: pointer to the hw struct
1502 * @mode: 0=off, 0xf=on (else see manual for mode details)
1503 * @blink: true if the LED should blink when on, false if steady
1504 *
1505 * if this function is used to turn on the blink it should
1506 * be used to disable the blink when restoring the original state.
1507 **/
1508 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1509 {
1510 u32 current_mode = 0;
1511 int i;
1512
1513 if (mode & 0xfffffff0)
1514 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1515
1516 /* as per the documentation GPIO 22-29 are the LED
1517 * GPIO pins named LED0..LED7
1518 */
1519 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1520 u32 gpio_val = i40e_led_is_mine(hw, i);
1521
1522 if (!gpio_val)
1523 continue;
1524
1525 /* ignore gpio LED src mode entries related to the activity
1526 * LEDs
1527 */
1528 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1529 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1530 switch (current_mode) {
1531 case I40E_COMBINED_ACTIVITY:
1532 case I40E_FILTER_ACTIVITY:
1533 case I40E_MAC_ACTIVITY:
1534 continue;
1535 default:
1536 break;
1537 }
1538
1539 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1540 /* this & is a bit of paranoia, but serves as a range check */
1541 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1542 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1543
1544 if (mode == I40E_LINK_ACTIVITY)
1545 blink = false;
1546
1547 if (blink)
1548 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1549 else
1550 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1551
1552 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1553 break;
1554 }
1555 }
1556
1557 /* Admin command wrappers */
1558
1559 /**
1560 * i40e_aq_get_phy_capabilities
1561 * @hw: pointer to the hw struct
1562 * @abilities: structure for PHY capabilities to be filled
1563 * @qualified_modules: report Qualified Modules
1564 * @report_init: report init capabilities (active are default)
1565 * @cmd_details: pointer to command details structure or NULL
1566 *
1567 * Returns the various PHY abilities supported on the Port.
1568 **/
1569 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1570 bool qualified_modules, bool report_init,
1571 struct i40e_aq_get_phy_abilities_resp *abilities,
1572 struct i40e_asq_cmd_details *cmd_details)
1573 {
1574 struct i40e_aq_desc desc;
1575 i40e_status status;
1576 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1577
1578 if (!abilities)
1579 return I40E_ERR_PARAM;
1580
1581 i40e_fill_default_direct_cmd_desc(&desc,
1582 i40e_aqc_opc_get_phy_abilities);
1583
1584 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1585 if (abilities_size > I40E_AQ_LARGE_BUF)
1586 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1587
1588 if (qualified_modules)
1589 desc.params.external.param0 |=
1590 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1591
1592 if (report_init)
1593 desc.params.external.param0 |=
1594 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1595
1596 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1597 cmd_details);
1598
1599 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1600 status = I40E_ERR_UNKNOWN_PHY;
1601
1602 if (report_init)
1603 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1604
1605 return status;
1606 }
1607
1608 /**
1609 * i40e_aq_set_phy_config
1610 * @hw: pointer to the hw struct
1611 * @config: structure with PHY configuration to be set
1612 * @cmd_details: pointer to command details structure or NULL
1613 *
1614 * Set the various PHY configuration parameters
1615 * supported on the Port.One or more of the Set PHY config parameters may be
1616 * ignored in an MFP mode as the PF may not have the privilege to set some
1617 * of the PHY Config parameters. This status will be indicated by the
1618 * command response.
1619 **/
1620 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1621 struct i40e_aq_set_phy_config *config,
1622 struct i40e_asq_cmd_details *cmd_details)
1623 {
1624 struct i40e_aq_desc desc;
1625 struct i40e_aq_set_phy_config *cmd =
1626 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1627 enum i40e_status_code status;
1628
1629 if (!config)
1630 return I40E_ERR_PARAM;
1631
1632 i40e_fill_default_direct_cmd_desc(&desc,
1633 i40e_aqc_opc_set_phy_config);
1634
1635 *cmd = *config;
1636
1637 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1638
1639 return status;
1640 }
1641
1642 /**
1643 * i40e_set_fc
1644 * @hw: pointer to the hw struct
1645 *
1646 * Set the requested flow control mode using set_phy_config.
1647 **/
1648 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1649 bool atomic_restart)
1650 {
1651 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1652 struct i40e_aq_get_phy_abilities_resp abilities;
1653 struct i40e_aq_set_phy_config config;
1654 enum i40e_status_code status;
1655 u8 pause_mask = 0x0;
1656
1657 *aq_failures = 0x0;
1658
1659 switch (fc_mode) {
1660 case I40E_FC_FULL:
1661 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1662 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1663 break;
1664 case I40E_FC_RX_PAUSE:
1665 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1666 break;
1667 case I40E_FC_TX_PAUSE:
1668 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1669 break;
1670 default:
1671 break;
1672 }
1673
1674 /* Get the current phy config */
1675 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1676 NULL);
1677 if (status) {
1678 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1679 return status;
1680 }
1681
1682 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1683 /* clear the old pause settings */
1684 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1685 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1686 /* set the new abilities */
1687 config.abilities |= pause_mask;
1688 /* If the abilities have changed, then set the new config */
1689 if (config.abilities != abilities.abilities) {
1690 /* Auto restart link so settings take effect */
1691 if (atomic_restart)
1692 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1693 /* Copy over all the old settings */
1694 config.phy_type = abilities.phy_type;
1695 config.link_speed = abilities.link_speed;
1696 config.eee_capability = abilities.eee_capability;
1697 config.eeer = abilities.eeer_val;
1698 config.low_power_ctrl = abilities.d3_lpan;
1699 status = i40e_aq_set_phy_config(hw, &config, NULL);
1700
1701 if (status)
1702 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1703 }
1704 /* Update the link info */
1705 status = i40e_update_link_info(hw);
1706 if (status) {
1707 /* Wait a little bit (on 40G cards it sometimes takes a really
1708 * long time for link to come back from the atomic reset)
1709 * and try once more
1710 */
1711 msleep(1000);
1712 status = i40e_update_link_info(hw);
1713 }
1714 if (status)
1715 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1716
1717 return status;
1718 }
1719
1720 /**
1721 * i40e_aq_clear_pxe_mode
1722 * @hw: pointer to the hw struct
1723 * @cmd_details: pointer to command details structure or NULL
1724 *
1725 * Tell the firmware that the driver is taking over from PXE
1726 **/
1727 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1728 struct i40e_asq_cmd_details *cmd_details)
1729 {
1730 i40e_status status;
1731 struct i40e_aq_desc desc;
1732 struct i40e_aqc_clear_pxe *cmd =
1733 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1734
1735 i40e_fill_default_direct_cmd_desc(&desc,
1736 i40e_aqc_opc_clear_pxe_mode);
1737
1738 cmd->rx_cnt = 0x2;
1739
1740 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1741
1742 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1743
1744 return status;
1745 }
1746
1747 /**
1748 * i40e_aq_set_link_restart_an
1749 * @hw: pointer to the hw struct
1750 * @enable_link: if true: enable link, if false: disable link
1751 * @cmd_details: pointer to command details structure or NULL
1752 *
1753 * Sets up the link and restarts the Auto-Negotiation over the link.
1754 **/
1755 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1756 bool enable_link,
1757 struct i40e_asq_cmd_details *cmd_details)
1758 {
1759 struct i40e_aq_desc desc;
1760 struct i40e_aqc_set_link_restart_an *cmd =
1761 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1762 i40e_status status;
1763
1764 i40e_fill_default_direct_cmd_desc(&desc,
1765 i40e_aqc_opc_set_link_restart_an);
1766
1767 cmd->command = I40E_AQ_PHY_RESTART_AN;
1768 if (enable_link)
1769 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1770 else
1771 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1772
1773 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1774
1775 return status;
1776 }
1777
1778 /**
1779 * i40e_aq_get_link_info
1780 * @hw: pointer to the hw struct
1781 * @enable_lse: enable/disable LinkStatusEvent reporting
1782 * @link: pointer to link status structure - optional
1783 * @cmd_details: pointer to command details structure or NULL
1784 *
1785 * Returns the link status of the adapter.
1786 **/
1787 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1788 bool enable_lse, struct i40e_link_status *link,
1789 struct i40e_asq_cmd_details *cmd_details)
1790 {
1791 struct i40e_aq_desc desc;
1792 struct i40e_aqc_get_link_status *resp =
1793 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1794 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1795 i40e_status status;
1796 bool tx_pause, rx_pause;
1797 u16 command_flags;
1798
1799 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1800
1801 if (enable_lse)
1802 command_flags = I40E_AQ_LSE_ENABLE;
1803 else
1804 command_flags = I40E_AQ_LSE_DISABLE;
1805 resp->command_flags = cpu_to_le16(command_flags);
1806
1807 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1808
1809 if (status)
1810 goto aq_get_link_info_exit;
1811
1812 /* save off old link status information */
1813 hw->phy.link_info_old = *hw_link_info;
1814
1815 /* update link status */
1816 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1817 hw->phy.media_type = i40e_get_media_type(hw);
1818 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1819 hw_link_info->link_info = resp->link_info;
1820 hw_link_info->an_info = resp->an_info;
1821 hw_link_info->ext_info = resp->ext_info;
1822 hw_link_info->loopback = resp->loopback;
1823 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1824 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1825
1826 /* update fc info */
1827 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1828 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1829 if (tx_pause & rx_pause)
1830 hw->fc.current_mode = I40E_FC_FULL;
1831 else if (tx_pause)
1832 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1833 else if (rx_pause)
1834 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1835 else
1836 hw->fc.current_mode = I40E_FC_NONE;
1837
1838 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1839 hw_link_info->crc_enable = true;
1840 else
1841 hw_link_info->crc_enable = false;
1842
1843 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1844 hw_link_info->lse_enable = true;
1845 else
1846 hw_link_info->lse_enable = false;
1847
1848 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1849 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1850 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1851
1852 /* save link status information */
1853 if (link)
1854 *link = *hw_link_info;
1855
1856 /* flag cleared so helper functions don't call AQ again */
1857 hw->phy.get_link_info = false;
1858
1859 aq_get_link_info_exit:
1860 return status;
1861 }
1862
1863 /**
1864 * i40e_aq_set_phy_int_mask
1865 * @hw: pointer to the hw struct
1866 * @mask: interrupt mask to be set
1867 * @cmd_details: pointer to command details structure or NULL
1868 *
1869 * Set link interrupt mask.
1870 **/
1871 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1872 u16 mask,
1873 struct i40e_asq_cmd_details *cmd_details)
1874 {
1875 struct i40e_aq_desc desc;
1876 struct i40e_aqc_set_phy_int_mask *cmd =
1877 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1878 i40e_status status;
1879
1880 i40e_fill_default_direct_cmd_desc(&desc,
1881 i40e_aqc_opc_set_phy_int_mask);
1882
1883 cmd->event_mask = cpu_to_le16(mask);
1884
1885 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1886
1887 return status;
1888 }
1889
1890 /**
1891 * i40e_aq_add_vsi
1892 * @hw: pointer to the hw struct
1893 * @vsi_ctx: pointer to a vsi context struct
1894 * @cmd_details: pointer to command details structure or NULL
1895 *
1896 * Add a VSI context to the hardware.
1897 **/
1898 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1899 struct i40e_vsi_context *vsi_ctx,
1900 struct i40e_asq_cmd_details *cmd_details)
1901 {
1902 struct i40e_aq_desc desc;
1903 struct i40e_aqc_add_get_update_vsi *cmd =
1904 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1905 struct i40e_aqc_add_get_update_vsi_completion *resp =
1906 (struct i40e_aqc_add_get_update_vsi_completion *)
1907 &desc.params.raw;
1908 i40e_status status;
1909
1910 i40e_fill_default_direct_cmd_desc(&desc,
1911 i40e_aqc_opc_add_vsi);
1912
1913 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1914 cmd->connection_type = vsi_ctx->connection_type;
1915 cmd->vf_id = vsi_ctx->vf_num;
1916 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1917
1918 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1919
1920 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1921 sizeof(vsi_ctx->info), cmd_details);
1922
1923 if (status)
1924 goto aq_add_vsi_exit;
1925
1926 vsi_ctx->seid = le16_to_cpu(resp->seid);
1927 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1928 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1929 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1930
1931 aq_add_vsi_exit:
1932 return status;
1933 }
1934
1935 /**
1936 * i40e_aq_set_vsi_unicast_promiscuous
1937 * @hw: pointer to the hw struct
1938 * @seid: vsi number
1939 * @set: set unicast promiscuous enable/disable
1940 * @cmd_details: pointer to command details structure or NULL
1941 **/
1942 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1943 u16 seid, bool set,
1944 struct i40e_asq_cmd_details *cmd_details)
1945 {
1946 struct i40e_aq_desc desc;
1947 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1948 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1949 i40e_status status;
1950 u16 flags = 0;
1951
1952 i40e_fill_default_direct_cmd_desc(&desc,
1953 i40e_aqc_opc_set_vsi_promiscuous_modes);
1954
1955 if (set) {
1956 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1957 if (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
1958 (hw->aq.api_maj_ver > 1))
1959 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
1960 }
1961
1962 cmd->promiscuous_flags = cpu_to_le16(flags);
1963
1964 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1965 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
1966 (hw->aq.api_maj_ver > 1))
1967 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX);
1968
1969 cmd->seid = cpu_to_le16(seid);
1970 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1971
1972 return status;
1973 }
1974
1975 /**
1976 * i40e_aq_set_vsi_multicast_promiscuous
1977 * @hw: pointer to the hw struct
1978 * @seid: vsi number
1979 * @set: set multicast promiscuous enable/disable
1980 * @cmd_details: pointer to command details structure or NULL
1981 **/
1982 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1983 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1984 {
1985 struct i40e_aq_desc desc;
1986 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1987 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1988 i40e_status status;
1989 u16 flags = 0;
1990
1991 i40e_fill_default_direct_cmd_desc(&desc,
1992 i40e_aqc_opc_set_vsi_promiscuous_modes);
1993
1994 if (set)
1995 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1996
1997 cmd->promiscuous_flags = cpu_to_le16(flags);
1998
1999 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2000
2001 cmd->seid = cpu_to_le16(seid);
2002 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2003
2004 return status;
2005 }
2006
2007 /**
2008 * i40e_aq_set_vsi_broadcast
2009 * @hw: pointer to the hw struct
2010 * @seid: vsi number
2011 * @set_filter: true to set filter, false to clear filter
2012 * @cmd_details: pointer to command details structure or NULL
2013 *
2014 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2015 **/
2016 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2017 u16 seid, bool set_filter,
2018 struct i40e_asq_cmd_details *cmd_details)
2019 {
2020 struct i40e_aq_desc desc;
2021 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2022 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2023 i40e_status status;
2024
2025 i40e_fill_default_direct_cmd_desc(&desc,
2026 i40e_aqc_opc_set_vsi_promiscuous_modes);
2027
2028 if (set_filter)
2029 cmd->promiscuous_flags
2030 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2031 else
2032 cmd->promiscuous_flags
2033 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2034
2035 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2036 cmd->seid = cpu_to_le16(seid);
2037 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2038
2039 return status;
2040 }
2041
2042 /**
2043 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2044 * @hw: pointer to the hw struct
2045 * @seid: vsi number
2046 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2047 * @cmd_details: pointer to command details structure or NULL
2048 **/
2049 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2050 u16 seid, bool enable,
2051 struct i40e_asq_cmd_details *cmd_details)
2052 {
2053 struct i40e_aq_desc desc;
2054 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2055 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2056 i40e_status status;
2057 u16 flags = 0;
2058
2059 i40e_fill_default_direct_cmd_desc(&desc,
2060 i40e_aqc_opc_set_vsi_promiscuous_modes);
2061 if (enable)
2062 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2063
2064 cmd->promiscuous_flags = cpu_to_le16(flags);
2065 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2066 cmd->seid = cpu_to_le16(seid);
2067
2068 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2069
2070 return status;
2071 }
2072
2073 /**
2074 * i40e_get_vsi_params - get VSI configuration info
2075 * @hw: pointer to the hw struct
2076 * @vsi_ctx: pointer to a vsi context struct
2077 * @cmd_details: pointer to command details structure or NULL
2078 **/
2079 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2080 struct i40e_vsi_context *vsi_ctx,
2081 struct i40e_asq_cmd_details *cmd_details)
2082 {
2083 struct i40e_aq_desc desc;
2084 struct i40e_aqc_add_get_update_vsi *cmd =
2085 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2086 struct i40e_aqc_add_get_update_vsi_completion *resp =
2087 (struct i40e_aqc_add_get_update_vsi_completion *)
2088 &desc.params.raw;
2089 i40e_status status;
2090
2091 i40e_fill_default_direct_cmd_desc(&desc,
2092 i40e_aqc_opc_get_vsi_parameters);
2093
2094 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2095
2096 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2097
2098 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2099 sizeof(vsi_ctx->info), NULL);
2100
2101 if (status)
2102 goto aq_get_vsi_params_exit;
2103
2104 vsi_ctx->seid = le16_to_cpu(resp->seid);
2105 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2106 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2107 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2108
2109 aq_get_vsi_params_exit:
2110 return status;
2111 }
2112
2113 /**
2114 * i40e_aq_update_vsi_params
2115 * @hw: pointer to the hw struct
2116 * @vsi_ctx: pointer to a vsi context struct
2117 * @cmd_details: pointer to command details structure or NULL
2118 *
2119 * Update a VSI context.
2120 **/
2121 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2122 struct i40e_vsi_context *vsi_ctx,
2123 struct i40e_asq_cmd_details *cmd_details)
2124 {
2125 struct i40e_aq_desc desc;
2126 struct i40e_aqc_add_get_update_vsi *cmd =
2127 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2128 i40e_status status;
2129
2130 i40e_fill_default_direct_cmd_desc(&desc,
2131 i40e_aqc_opc_update_vsi_parameters);
2132 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2133
2134 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2135
2136 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2137 sizeof(vsi_ctx->info), cmd_details);
2138
2139 return status;
2140 }
2141
2142 /**
2143 * i40e_aq_get_switch_config
2144 * @hw: pointer to the hardware structure
2145 * @buf: pointer to the result buffer
2146 * @buf_size: length of input buffer
2147 * @start_seid: seid to start for the report, 0 == beginning
2148 * @cmd_details: pointer to command details structure or NULL
2149 *
2150 * Fill the buf with switch configuration returned from AdminQ command
2151 **/
2152 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2153 struct i40e_aqc_get_switch_config_resp *buf,
2154 u16 buf_size, u16 *start_seid,
2155 struct i40e_asq_cmd_details *cmd_details)
2156 {
2157 struct i40e_aq_desc desc;
2158 struct i40e_aqc_switch_seid *scfg =
2159 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2160 i40e_status status;
2161
2162 i40e_fill_default_direct_cmd_desc(&desc,
2163 i40e_aqc_opc_get_switch_config);
2164 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2165 if (buf_size > I40E_AQ_LARGE_BUF)
2166 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2167 scfg->seid = cpu_to_le16(*start_seid);
2168
2169 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2170 *start_seid = le16_to_cpu(scfg->seid);
2171
2172 return status;
2173 }
2174
2175 /**
2176 * i40e_aq_get_firmware_version
2177 * @hw: pointer to the hw struct
2178 * @fw_major_version: firmware major version
2179 * @fw_minor_version: firmware minor version
2180 * @fw_build: firmware build number
2181 * @api_major_version: major queue version
2182 * @api_minor_version: minor queue version
2183 * @cmd_details: pointer to command details structure or NULL
2184 *
2185 * Get the firmware version from the admin queue commands
2186 **/
2187 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2188 u16 *fw_major_version, u16 *fw_minor_version,
2189 u32 *fw_build,
2190 u16 *api_major_version, u16 *api_minor_version,
2191 struct i40e_asq_cmd_details *cmd_details)
2192 {
2193 struct i40e_aq_desc desc;
2194 struct i40e_aqc_get_version *resp =
2195 (struct i40e_aqc_get_version *)&desc.params.raw;
2196 i40e_status status;
2197
2198 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2199
2200 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2201
2202 if (!status) {
2203 if (fw_major_version)
2204 *fw_major_version = le16_to_cpu(resp->fw_major);
2205 if (fw_minor_version)
2206 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2207 if (fw_build)
2208 *fw_build = le32_to_cpu(resp->fw_build);
2209 if (api_major_version)
2210 *api_major_version = le16_to_cpu(resp->api_major);
2211 if (api_minor_version)
2212 *api_minor_version = le16_to_cpu(resp->api_minor);
2213 }
2214
2215 return status;
2216 }
2217
2218 /**
2219 * i40e_aq_send_driver_version
2220 * @hw: pointer to the hw struct
2221 * @dv: driver's major, minor version
2222 * @cmd_details: pointer to command details structure or NULL
2223 *
2224 * Send the driver version to the firmware
2225 **/
2226 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2227 struct i40e_driver_version *dv,
2228 struct i40e_asq_cmd_details *cmd_details)
2229 {
2230 struct i40e_aq_desc desc;
2231 struct i40e_aqc_driver_version *cmd =
2232 (struct i40e_aqc_driver_version *)&desc.params.raw;
2233 i40e_status status;
2234 u16 len;
2235
2236 if (dv == NULL)
2237 return I40E_ERR_PARAM;
2238
2239 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2240
2241 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2242 cmd->driver_major_ver = dv->major_version;
2243 cmd->driver_minor_ver = dv->minor_version;
2244 cmd->driver_build_ver = dv->build_version;
2245 cmd->driver_subbuild_ver = dv->subbuild_version;
2246
2247 len = 0;
2248 while (len < sizeof(dv->driver_string) &&
2249 (dv->driver_string[len] < 0x80) &&
2250 dv->driver_string[len])
2251 len++;
2252 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2253 len, cmd_details);
2254
2255 return status;
2256 }
2257
2258 /**
2259 * i40e_get_link_status - get status of the HW network link
2260 * @hw: pointer to the hw struct
2261 * @link_up: pointer to bool (true/false = linkup/linkdown)
2262 *
2263 * Variable link_up true if link is up, false if link is down.
2264 * The variable link_up is invalid if returned value of status != 0
2265 *
2266 * Side effect: LinkStatusEvent reporting becomes enabled
2267 **/
2268 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2269 {
2270 i40e_status status = 0;
2271
2272 if (hw->phy.get_link_info) {
2273 status = i40e_update_link_info(hw);
2274
2275 if (status)
2276 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2277 status);
2278 }
2279
2280 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2281
2282 return status;
2283 }
2284
2285 /**
2286 * i40e_updatelink_status - update status of the HW network link
2287 * @hw: pointer to the hw struct
2288 **/
2289 i40e_status i40e_update_link_info(struct i40e_hw *hw)
2290 {
2291 struct i40e_aq_get_phy_abilities_resp abilities;
2292 i40e_status status = 0;
2293
2294 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2295 if (status)
2296 return status;
2297
2298 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2299 status = i40e_aq_get_phy_capabilities(hw, false, false,
2300 &abilities, NULL);
2301 if (status)
2302 return status;
2303
2304 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2305 sizeof(hw->phy.link_info.module_type));
2306 }
2307
2308 return status;
2309 }
2310
2311 /**
2312 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2313 * @hw: pointer to the hw struct
2314 * @uplink_seid: the MAC or other gizmo SEID
2315 * @downlink_seid: the VSI SEID
2316 * @enabled_tc: bitmap of TCs to be enabled
2317 * @default_port: true for default port VSI, false for control port
2318 * @veb_seid: pointer to where to put the resulting VEB SEID
2319 * @enable_stats: true to turn on VEB stats
2320 * @cmd_details: pointer to command details structure or NULL
2321 *
2322 * This asks the FW to add a VEB between the uplink and downlink
2323 * elements. If the uplink SEID is 0, this will be a floating VEB.
2324 **/
2325 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2326 u16 downlink_seid, u8 enabled_tc,
2327 bool default_port, u16 *veb_seid,
2328 bool enable_stats,
2329 struct i40e_asq_cmd_details *cmd_details)
2330 {
2331 struct i40e_aq_desc desc;
2332 struct i40e_aqc_add_veb *cmd =
2333 (struct i40e_aqc_add_veb *)&desc.params.raw;
2334 struct i40e_aqc_add_veb_completion *resp =
2335 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2336 i40e_status status;
2337 u16 veb_flags = 0;
2338
2339 /* SEIDs need to either both be set or both be 0 for floating VEB */
2340 if (!!uplink_seid != !!downlink_seid)
2341 return I40E_ERR_PARAM;
2342
2343 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2344
2345 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2346 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2347 cmd->enable_tcs = enabled_tc;
2348 if (!uplink_seid)
2349 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2350 if (default_port)
2351 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2352 else
2353 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2354
2355 /* reverse logic here: set the bitflag to disable the stats */
2356 if (!enable_stats)
2357 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2358
2359 cmd->veb_flags = cpu_to_le16(veb_flags);
2360
2361 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2362
2363 if (!status && veb_seid)
2364 *veb_seid = le16_to_cpu(resp->veb_seid);
2365
2366 return status;
2367 }
2368
2369 /**
2370 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2371 * @hw: pointer to the hw struct
2372 * @veb_seid: the SEID of the VEB to query
2373 * @switch_id: the uplink switch id
2374 * @floating: set to true if the VEB is floating
2375 * @statistic_index: index of the stats counter block for this VEB
2376 * @vebs_used: number of VEB's used by function
2377 * @vebs_free: total VEB's not reserved by any function
2378 * @cmd_details: pointer to command details structure or NULL
2379 *
2380 * This retrieves the parameters for a particular VEB, specified by
2381 * uplink_seid, and returns them to the caller.
2382 **/
2383 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2384 u16 veb_seid, u16 *switch_id,
2385 bool *floating, u16 *statistic_index,
2386 u16 *vebs_used, u16 *vebs_free,
2387 struct i40e_asq_cmd_details *cmd_details)
2388 {
2389 struct i40e_aq_desc desc;
2390 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2391 (struct i40e_aqc_get_veb_parameters_completion *)
2392 &desc.params.raw;
2393 i40e_status status;
2394
2395 if (veb_seid == 0)
2396 return I40E_ERR_PARAM;
2397
2398 i40e_fill_default_direct_cmd_desc(&desc,
2399 i40e_aqc_opc_get_veb_parameters);
2400 cmd_resp->seid = cpu_to_le16(veb_seid);
2401
2402 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2403 if (status)
2404 goto get_veb_exit;
2405
2406 if (switch_id)
2407 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2408 if (statistic_index)
2409 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2410 if (vebs_used)
2411 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2412 if (vebs_free)
2413 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2414 if (floating) {
2415 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2416
2417 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2418 *floating = true;
2419 else
2420 *floating = false;
2421 }
2422
2423 get_veb_exit:
2424 return status;
2425 }
2426
2427 /**
2428 * i40e_aq_add_macvlan
2429 * @hw: pointer to the hw struct
2430 * @seid: VSI for the mac address
2431 * @mv_list: list of macvlans to be added
2432 * @count: length of the list
2433 * @cmd_details: pointer to command details structure or NULL
2434 *
2435 * Add MAC/VLAN addresses to the HW filtering
2436 **/
2437 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2438 struct i40e_aqc_add_macvlan_element_data *mv_list,
2439 u16 count, struct i40e_asq_cmd_details *cmd_details)
2440 {
2441 struct i40e_aq_desc desc;
2442 struct i40e_aqc_macvlan *cmd =
2443 (struct i40e_aqc_macvlan *)&desc.params.raw;
2444 i40e_status status;
2445 u16 buf_size;
2446 int i;
2447
2448 if (count == 0 || !mv_list || !hw)
2449 return I40E_ERR_PARAM;
2450
2451 buf_size = count * sizeof(*mv_list);
2452
2453 /* prep the rest of the request */
2454 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2455 cmd->num_addresses = cpu_to_le16(count);
2456 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2457 cmd->seid[1] = 0;
2458 cmd->seid[2] = 0;
2459
2460 for (i = 0; i < count; i++)
2461 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2462 mv_list[i].flags |=
2463 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2464
2465 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2466 if (buf_size > I40E_AQ_LARGE_BUF)
2467 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2468
2469 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2470 cmd_details);
2471
2472 return status;
2473 }
2474
2475 /**
2476 * i40e_aq_remove_macvlan
2477 * @hw: pointer to the hw struct
2478 * @seid: VSI for the mac address
2479 * @mv_list: list of macvlans to be removed
2480 * @count: length of the list
2481 * @cmd_details: pointer to command details structure or NULL
2482 *
2483 * Remove MAC/VLAN addresses from the HW filtering
2484 **/
2485 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2486 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2487 u16 count, struct i40e_asq_cmd_details *cmd_details)
2488 {
2489 struct i40e_aq_desc desc;
2490 struct i40e_aqc_macvlan *cmd =
2491 (struct i40e_aqc_macvlan *)&desc.params.raw;
2492 i40e_status status;
2493 u16 buf_size;
2494
2495 if (count == 0 || !mv_list || !hw)
2496 return I40E_ERR_PARAM;
2497
2498 buf_size = count * sizeof(*mv_list);
2499
2500 /* prep the rest of the request */
2501 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2502 cmd->num_addresses = cpu_to_le16(count);
2503 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2504 cmd->seid[1] = 0;
2505 cmd->seid[2] = 0;
2506
2507 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2508 if (buf_size > I40E_AQ_LARGE_BUF)
2509 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2510
2511 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2512 cmd_details);
2513
2514 return status;
2515 }
2516
2517 /**
2518 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2519 * @hw: pointer to the hw struct
2520 * @opcode: AQ opcode for add or delete mirror rule
2521 * @sw_seid: Switch SEID (to which rule refers)
2522 * @rule_type: Rule Type (ingress/egress/VLAN)
2523 * @id: Destination VSI SEID or Rule ID
2524 * @count: length of the list
2525 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2526 * @cmd_details: pointer to command details structure or NULL
2527 * @rule_id: Rule ID returned from FW
2528 * @rule_used: Number of rules used in internal switch
2529 * @rule_free: Number of rules free in internal switch
2530 *
2531 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2532 * VEBs/VEPA elements only
2533 **/
2534 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2535 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2536 u16 count, __le16 *mr_list,
2537 struct i40e_asq_cmd_details *cmd_details,
2538 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2539 {
2540 struct i40e_aq_desc desc;
2541 struct i40e_aqc_add_delete_mirror_rule *cmd =
2542 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2543 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2544 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2545 i40e_status status;
2546 u16 buf_size;
2547
2548 buf_size = count * sizeof(*mr_list);
2549
2550 /* prep the rest of the request */
2551 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2552 cmd->seid = cpu_to_le16(sw_seid);
2553 cmd->rule_type = cpu_to_le16(rule_type &
2554 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2555 cmd->num_entries = cpu_to_le16(count);
2556 /* Dest VSI for add, rule_id for delete */
2557 cmd->destination = cpu_to_le16(id);
2558 if (mr_list) {
2559 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2560 I40E_AQ_FLAG_RD));
2561 if (buf_size > I40E_AQ_LARGE_BUF)
2562 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2563 }
2564
2565 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2566 cmd_details);
2567 if (!status ||
2568 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2569 if (rule_id)
2570 *rule_id = le16_to_cpu(resp->rule_id);
2571 if (rules_used)
2572 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2573 if (rules_free)
2574 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2575 }
2576 return status;
2577 }
2578
2579 /**
2580 * i40e_aq_add_mirrorrule - add a mirror rule
2581 * @hw: pointer to the hw struct
2582 * @sw_seid: Switch SEID (to which rule refers)
2583 * @rule_type: Rule Type (ingress/egress/VLAN)
2584 * @dest_vsi: SEID of VSI to which packets will be mirrored
2585 * @count: length of the list
2586 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2587 * @cmd_details: pointer to command details structure or NULL
2588 * @rule_id: Rule ID returned from FW
2589 * @rule_used: Number of rules used in internal switch
2590 * @rule_free: Number of rules free in internal switch
2591 *
2592 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2593 **/
2594 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2595 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2596 struct i40e_asq_cmd_details *cmd_details,
2597 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2598 {
2599 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2600 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2601 if (count == 0 || !mr_list)
2602 return I40E_ERR_PARAM;
2603 }
2604
2605 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2606 rule_type, dest_vsi, count, mr_list,
2607 cmd_details, rule_id, rules_used, rules_free);
2608 }
2609
2610 /**
2611 * i40e_aq_delete_mirrorrule - delete a mirror rule
2612 * @hw: pointer to the hw struct
2613 * @sw_seid: Switch SEID (to which rule refers)
2614 * @rule_type: Rule Type (ingress/egress/VLAN)
2615 * @count: length of the list
2616 * @rule_id: Rule ID that is returned in the receive desc as part of
2617 * add_mirrorrule.
2618 * @mr_list: list of mirrored VLAN IDs to be removed
2619 * @cmd_details: pointer to command details structure or NULL
2620 * @rule_used: Number of rules used in internal switch
2621 * @rule_free: Number of rules free in internal switch
2622 *
2623 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2624 **/
2625 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2626 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2627 struct i40e_asq_cmd_details *cmd_details,
2628 u16 *rules_used, u16 *rules_free)
2629 {
2630 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2631 if (rule_type != I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2632 if (!rule_id)
2633 return I40E_ERR_PARAM;
2634 } else {
2635 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2636 * mirroring. For other rule_type, count and rule_type should
2637 * not matter.
2638 */
2639 if (count == 0 || !mr_list)
2640 return I40E_ERR_PARAM;
2641 }
2642
2643 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2644 rule_type, rule_id, count, mr_list,
2645 cmd_details, NULL, rules_used, rules_free);
2646 }
2647
2648 /**
2649 * i40e_aq_send_msg_to_vf
2650 * @hw: pointer to the hardware structure
2651 * @vfid: VF id to send msg
2652 * @v_opcode: opcodes for VF-PF communication
2653 * @v_retval: return error code
2654 * @msg: pointer to the msg buffer
2655 * @msglen: msg length
2656 * @cmd_details: pointer to command details
2657 *
2658 * send msg to vf
2659 **/
2660 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2661 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2662 struct i40e_asq_cmd_details *cmd_details)
2663 {
2664 struct i40e_aq_desc desc;
2665 struct i40e_aqc_pf_vf_message *cmd =
2666 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2667 i40e_status status;
2668
2669 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2670 cmd->id = cpu_to_le32(vfid);
2671 desc.cookie_high = cpu_to_le32(v_opcode);
2672 desc.cookie_low = cpu_to_le32(v_retval);
2673 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2674 if (msglen) {
2675 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2676 I40E_AQ_FLAG_RD));
2677 if (msglen > I40E_AQ_LARGE_BUF)
2678 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2679 desc.datalen = cpu_to_le16(msglen);
2680 }
2681 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2682
2683 return status;
2684 }
2685
2686 /**
2687 * i40e_aq_debug_read_register
2688 * @hw: pointer to the hw struct
2689 * @reg_addr: register address
2690 * @reg_val: register value
2691 * @cmd_details: pointer to command details structure or NULL
2692 *
2693 * Read the register using the admin queue commands
2694 **/
2695 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2696 u32 reg_addr, u64 *reg_val,
2697 struct i40e_asq_cmd_details *cmd_details)
2698 {
2699 struct i40e_aq_desc desc;
2700 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2701 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2702 i40e_status status;
2703
2704 if (reg_val == NULL)
2705 return I40E_ERR_PARAM;
2706
2707 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2708
2709 cmd_resp->address = cpu_to_le32(reg_addr);
2710
2711 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2712
2713 if (!status) {
2714 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2715 (u64)le32_to_cpu(cmd_resp->value_low);
2716 }
2717
2718 return status;
2719 }
2720
2721 /**
2722 * i40e_aq_debug_write_register
2723 * @hw: pointer to the hw struct
2724 * @reg_addr: register address
2725 * @reg_val: register value
2726 * @cmd_details: pointer to command details structure or NULL
2727 *
2728 * Write to a register using the admin queue commands
2729 **/
2730 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2731 u32 reg_addr, u64 reg_val,
2732 struct i40e_asq_cmd_details *cmd_details)
2733 {
2734 struct i40e_aq_desc desc;
2735 struct i40e_aqc_debug_reg_read_write *cmd =
2736 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2737 i40e_status status;
2738
2739 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2740
2741 cmd->address = cpu_to_le32(reg_addr);
2742 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2743 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2744
2745 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2746
2747 return status;
2748 }
2749
2750 /**
2751 * i40e_aq_set_hmc_resource_profile
2752 * @hw: pointer to the hw struct
2753 * @profile: type of profile the HMC is to be set as
2754 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2755 * @cmd_details: pointer to command details structure or NULL
2756 *
2757 * set the HMC profile of the device.
2758 **/
2759 i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2760 enum i40e_aq_hmc_profile profile,
2761 u8 pe_vf_enabled_count,
2762 struct i40e_asq_cmd_details *cmd_details)
2763 {
2764 struct i40e_aq_desc desc;
2765 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2766 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2767 i40e_status status;
2768
2769 i40e_fill_default_direct_cmd_desc(&desc,
2770 i40e_aqc_opc_set_hmc_resource_profile);
2771
2772 cmd->pm_profile = (u8)profile;
2773 cmd->pe_vf_enabled = pe_vf_enabled_count;
2774
2775 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2776
2777 return status;
2778 }
2779
2780 /**
2781 * i40e_aq_request_resource
2782 * @hw: pointer to the hw struct
2783 * @resource: resource id
2784 * @access: access type
2785 * @sdp_number: resource number
2786 * @timeout: the maximum time in ms that the driver may hold the resource
2787 * @cmd_details: pointer to command details structure or NULL
2788 *
2789 * requests common resource using the admin queue commands
2790 **/
2791 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2792 enum i40e_aq_resources_ids resource,
2793 enum i40e_aq_resource_access_type access,
2794 u8 sdp_number, u64 *timeout,
2795 struct i40e_asq_cmd_details *cmd_details)
2796 {
2797 struct i40e_aq_desc desc;
2798 struct i40e_aqc_request_resource *cmd_resp =
2799 (struct i40e_aqc_request_resource *)&desc.params.raw;
2800 i40e_status status;
2801
2802 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2803
2804 cmd_resp->resource_id = cpu_to_le16(resource);
2805 cmd_resp->access_type = cpu_to_le16(access);
2806 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2807
2808 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2809 /* The completion specifies the maximum time in ms that the driver
2810 * may hold the resource in the Timeout field.
2811 * If the resource is held by someone else, the command completes with
2812 * busy return value and the timeout field indicates the maximum time
2813 * the current owner of the resource has to free it.
2814 */
2815 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2816 *timeout = le32_to_cpu(cmd_resp->timeout);
2817
2818 return status;
2819 }
2820
2821 /**
2822 * i40e_aq_release_resource
2823 * @hw: pointer to the hw struct
2824 * @resource: resource id
2825 * @sdp_number: resource number
2826 * @cmd_details: pointer to command details structure or NULL
2827 *
2828 * release common resource using the admin queue commands
2829 **/
2830 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2831 enum i40e_aq_resources_ids resource,
2832 u8 sdp_number,
2833 struct i40e_asq_cmd_details *cmd_details)
2834 {
2835 struct i40e_aq_desc desc;
2836 struct i40e_aqc_request_resource *cmd =
2837 (struct i40e_aqc_request_resource *)&desc.params.raw;
2838 i40e_status status;
2839
2840 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2841
2842 cmd->resource_id = cpu_to_le16(resource);
2843 cmd->resource_number = cpu_to_le32(sdp_number);
2844
2845 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2846
2847 return status;
2848 }
2849
2850 /**
2851 * i40e_aq_read_nvm
2852 * @hw: pointer to the hw struct
2853 * @module_pointer: module pointer location in words from the NVM beginning
2854 * @offset: byte offset from the module beginning
2855 * @length: length of the section to be read (in bytes from the offset)
2856 * @data: command buffer (size [bytes] = length)
2857 * @last_command: tells if this is the last command in a series
2858 * @cmd_details: pointer to command details structure or NULL
2859 *
2860 * Read the NVM using the admin queue commands
2861 **/
2862 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2863 u32 offset, u16 length, void *data,
2864 bool last_command,
2865 struct i40e_asq_cmd_details *cmd_details)
2866 {
2867 struct i40e_aq_desc desc;
2868 struct i40e_aqc_nvm_update *cmd =
2869 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2870 i40e_status status;
2871
2872 /* In offset the highest byte must be zeroed. */
2873 if (offset & 0xFF000000) {
2874 status = I40E_ERR_PARAM;
2875 goto i40e_aq_read_nvm_exit;
2876 }
2877
2878 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2879
2880 /* If this is the last command in a series, set the proper flag. */
2881 if (last_command)
2882 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2883 cmd->module_pointer = module_pointer;
2884 cmd->offset = cpu_to_le32(offset);
2885 cmd->length = cpu_to_le16(length);
2886
2887 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2888 if (length > I40E_AQ_LARGE_BUF)
2889 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2890
2891 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2892
2893 i40e_aq_read_nvm_exit:
2894 return status;
2895 }
2896
2897 /**
2898 * i40e_aq_erase_nvm
2899 * @hw: pointer to the hw struct
2900 * @module_pointer: module pointer location in words from the NVM beginning
2901 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2902 * @length: length of the section to be erased (expressed in 4 KB)
2903 * @last_command: tells if this is the last command in a series
2904 * @cmd_details: pointer to command details structure or NULL
2905 *
2906 * Erase the NVM sector using the admin queue commands
2907 **/
2908 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2909 u32 offset, u16 length, bool last_command,
2910 struct i40e_asq_cmd_details *cmd_details)
2911 {
2912 struct i40e_aq_desc desc;
2913 struct i40e_aqc_nvm_update *cmd =
2914 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2915 i40e_status status;
2916
2917 /* In offset the highest byte must be zeroed. */
2918 if (offset & 0xFF000000) {
2919 status = I40E_ERR_PARAM;
2920 goto i40e_aq_erase_nvm_exit;
2921 }
2922
2923 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2924
2925 /* If this is the last command in a series, set the proper flag. */
2926 if (last_command)
2927 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2928 cmd->module_pointer = module_pointer;
2929 cmd->offset = cpu_to_le32(offset);
2930 cmd->length = cpu_to_le16(length);
2931
2932 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2933
2934 i40e_aq_erase_nvm_exit:
2935 return status;
2936 }
2937
2938 /**
2939 * i40e_parse_discover_capabilities
2940 * @hw: pointer to the hw struct
2941 * @buff: pointer to a buffer containing device/function capability records
2942 * @cap_count: number of capability records in the list
2943 * @list_type_opc: type of capabilities list to parse
2944 *
2945 * Parse the device/function capabilities list.
2946 **/
2947 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2948 u32 cap_count,
2949 enum i40e_admin_queue_opc list_type_opc)
2950 {
2951 struct i40e_aqc_list_capabilities_element_resp *cap;
2952 u32 valid_functions, num_functions;
2953 u32 number, logical_id, phys_id;
2954 struct i40e_hw_capabilities *p;
2955 u8 major_rev;
2956 u32 i = 0;
2957 u16 id;
2958
2959 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2960
2961 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2962 p = &hw->dev_caps;
2963 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2964 p = &hw->func_caps;
2965 else
2966 return;
2967
2968 for (i = 0; i < cap_count; i++, cap++) {
2969 id = le16_to_cpu(cap->id);
2970 number = le32_to_cpu(cap->number);
2971 logical_id = le32_to_cpu(cap->logical_id);
2972 phys_id = le32_to_cpu(cap->phys_id);
2973 major_rev = cap->major_rev;
2974
2975 switch (id) {
2976 case I40E_AQ_CAP_ID_SWITCH_MODE:
2977 p->switch_mode = number;
2978 break;
2979 case I40E_AQ_CAP_ID_MNG_MODE:
2980 p->management_mode = number;
2981 break;
2982 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
2983 p->npar_enable = number;
2984 break;
2985 case I40E_AQ_CAP_ID_OS2BMC_CAP:
2986 p->os2bmc = number;
2987 break;
2988 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
2989 p->valid_functions = number;
2990 break;
2991 case I40E_AQ_CAP_ID_SRIOV:
2992 if (number == 1)
2993 p->sr_iov_1_1 = true;
2994 break;
2995 case I40E_AQ_CAP_ID_VF:
2996 p->num_vfs = number;
2997 p->vf_base_id = logical_id;
2998 break;
2999 case I40E_AQ_CAP_ID_VMDQ:
3000 if (number == 1)
3001 p->vmdq = true;
3002 break;
3003 case I40E_AQ_CAP_ID_8021QBG:
3004 if (number == 1)
3005 p->evb_802_1_qbg = true;
3006 break;
3007 case I40E_AQ_CAP_ID_8021QBR:
3008 if (number == 1)
3009 p->evb_802_1_qbh = true;
3010 break;
3011 case I40E_AQ_CAP_ID_VSI:
3012 p->num_vsis = number;
3013 break;
3014 case I40E_AQ_CAP_ID_DCB:
3015 if (number == 1) {
3016 p->dcb = true;
3017 p->enabled_tcmap = logical_id;
3018 p->maxtc = phys_id;
3019 }
3020 break;
3021 case I40E_AQ_CAP_ID_FCOE:
3022 if (number == 1)
3023 p->fcoe = true;
3024 break;
3025 case I40E_AQ_CAP_ID_ISCSI:
3026 if (number == 1)
3027 p->iscsi = true;
3028 break;
3029 case I40E_AQ_CAP_ID_RSS:
3030 p->rss = true;
3031 p->rss_table_size = number;
3032 p->rss_table_entry_width = logical_id;
3033 break;
3034 case I40E_AQ_CAP_ID_RXQ:
3035 p->num_rx_qp = number;
3036 p->base_queue = phys_id;
3037 break;
3038 case I40E_AQ_CAP_ID_TXQ:
3039 p->num_tx_qp = number;
3040 p->base_queue = phys_id;
3041 break;
3042 case I40E_AQ_CAP_ID_MSIX:
3043 p->num_msix_vectors = number;
3044 break;
3045 case I40E_AQ_CAP_ID_VF_MSIX:
3046 p->num_msix_vectors_vf = number;
3047 break;
3048 case I40E_AQ_CAP_ID_FLEX10:
3049 if (major_rev == 1) {
3050 if (number == 1) {
3051 p->flex10_enable = true;
3052 p->flex10_capable = true;
3053 }
3054 } else {
3055 /* Capability revision >= 2 */
3056 if (number & 1)
3057 p->flex10_enable = true;
3058 if (number & 2)
3059 p->flex10_capable = true;
3060 }
3061 p->flex10_mode = logical_id;
3062 p->flex10_status = phys_id;
3063 break;
3064 case I40E_AQ_CAP_ID_CEM:
3065 if (number == 1)
3066 p->mgmt_cem = true;
3067 break;
3068 case I40E_AQ_CAP_ID_IWARP:
3069 if (number == 1)
3070 p->iwarp = true;
3071 break;
3072 case I40E_AQ_CAP_ID_LED:
3073 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3074 p->led[phys_id] = true;
3075 break;
3076 case I40E_AQ_CAP_ID_SDP:
3077 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3078 p->sdp[phys_id] = true;
3079 break;
3080 case I40E_AQ_CAP_ID_MDIO:
3081 if (number == 1) {
3082 p->mdio_port_num = phys_id;
3083 p->mdio_port_mode = logical_id;
3084 }
3085 break;
3086 case I40E_AQ_CAP_ID_1588:
3087 if (number == 1)
3088 p->ieee_1588 = true;
3089 break;
3090 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3091 p->fd = true;
3092 p->fd_filters_guaranteed = number;
3093 p->fd_filters_best_effort = logical_id;
3094 break;
3095 case I40E_AQ_CAP_ID_WSR_PROT:
3096 p->wr_csr_prot = (u64)number;
3097 p->wr_csr_prot |= (u64)logical_id << 32;
3098 break;
3099 default:
3100 break;
3101 }
3102 }
3103
3104 if (p->fcoe)
3105 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3106
3107 /* Software override ensuring FCoE is disabled if npar or mfp
3108 * mode because it is not supported in these modes.
3109 */
3110 if (p->npar_enable || p->flex10_enable)
3111 p->fcoe = false;
3112
3113 /* count the enabled ports (aka the "not disabled" ports) */
3114 hw->num_ports = 0;
3115 for (i = 0; i < 4; i++) {
3116 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3117 u64 port_cfg = 0;
3118
3119 /* use AQ read to get the physical register offset instead
3120 * of the port relative offset
3121 */
3122 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3123 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3124 hw->num_ports++;
3125 }
3126
3127 valid_functions = p->valid_functions;
3128 num_functions = 0;
3129 while (valid_functions) {
3130 if (valid_functions & 1)
3131 num_functions++;
3132 valid_functions >>= 1;
3133 }
3134
3135 /* partition id is 1-based, and functions are evenly spread
3136 * across the ports as partitions
3137 */
3138 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3139 hw->num_partitions = num_functions / hw->num_ports;
3140
3141 /* additional HW specific goodies that might
3142 * someday be HW version specific
3143 */
3144 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3145 }
3146
3147 /**
3148 * i40e_aq_discover_capabilities
3149 * @hw: pointer to the hw struct
3150 * @buff: a virtual buffer to hold the capabilities
3151 * @buff_size: Size of the virtual buffer
3152 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3153 * @list_type_opc: capabilities type to discover - pass in the command opcode
3154 * @cmd_details: pointer to command details structure or NULL
3155 *
3156 * Get the device capabilities descriptions from the firmware
3157 **/
3158 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3159 void *buff, u16 buff_size, u16 *data_size,
3160 enum i40e_admin_queue_opc list_type_opc,
3161 struct i40e_asq_cmd_details *cmd_details)
3162 {
3163 struct i40e_aqc_list_capabilites *cmd;
3164 struct i40e_aq_desc desc;
3165 i40e_status status = 0;
3166
3167 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3168
3169 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3170 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3171 status = I40E_ERR_PARAM;
3172 goto exit;
3173 }
3174
3175 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3176
3177 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3178 if (buff_size > I40E_AQ_LARGE_BUF)
3179 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3180
3181 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3182 *data_size = le16_to_cpu(desc.datalen);
3183
3184 if (status)
3185 goto exit;
3186
3187 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3188 list_type_opc);
3189
3190 exit:
3191 return status;
3192 }
3193
3194 /**
3195 * i40e_aq_update_nvm
3196 * @hw: pointer to the hw struct
3197 * @module_pointer: module pointer location in words from the NVM beginning
3198 * @offset: byte offset from the module beginning
3199 * @length: length of the section to be written (in bytes from the offset)
3200 * @data: command buffer (size [bytes] = length)
3201 * @last_command: tells if this is the last command in a series
3202 * @cmd_details: pointer to command details structure or NULL
3203 *
3204 * Update the NVM using the admin queue commands
3205 **/
3206 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3207 u32 offset, u16 length, void *data,
3208 bool last_command,
3209 struct i40e_asq_cmd_details *cmd_details)
3210 {
3211 struct i40e_aq_desc desc;
3212 struct i40e_aqc_nvm_update *cmd =
3213 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3214 i40e_status status;
3215
3216 /* In offset the highest byte must be zeroed. */
3217 if (offset & 0xFF000000) {
3218 status = I40E_ERR_PARAM;
3219 goto i40e_aq_update_nvm_exit;
3220 }
3221
3222 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3223
3224 /* If this is the last command in a series, set the proper flag. */
3225 if (last_command)
3226 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3227 cmd->module_pointer = module_pointer;
3228 cmd->offset = cpu_to_le32(offset);
3229 cmd->length = cpu_to_le16(length);
3230
3231 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3232 if (length > I40E_AQ_LARGE_BUF)
3233 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3234
3235 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3236
3237 i40e_aq_update_nvm_exit:
3238 return status;
3239 }
3240
3241 /**
3242 * i40e_aq_get_lldp_mib
3243 * @hw: pointer to the hw struct
3244 * @bridge_type: type of bridge requested
3245 * @mib_type: Local, Remote or both Local and Remote MIBs
3246 * @buff: pointer to a user supplied buffer to store the MIB block
3247 * @buff_size: size of the buffer (in bytes)
3248 * @local_len : length of the returned Local LLDP MIB
3249 * @remote_len: length of the returned Remote LLDP MIB
3250 * @cmd_details: pointer to command details structure or NULL
3251 *
3252 * Requests the complete LLDP MIB (entire packet).
3253 **/
3254 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3255 u8 mib_type, void *buff, u16 buff_size,
3256 u16 *local_len, u16 *remote_len,
3257 struct i40e_asq_cmd_details *cmd_details)
3258 {
3259 struct i40e_aq_desc desc;
3260 struct i40e_aqc_lldp_get_mib *cmd =
3261 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3262 struct i40e_aqc_lldp_get_mib *resp =
3263 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3264 i40e_status status;
3265
3266 if (buff_size == 0 || !buff)
3267 return I40E_ERR_PARAM;
3268
3269 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3270 /* Indirect Command */
3271 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3272
3273 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3274 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3275 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3276
3277 desc.datalen = cpu_to_le16(buff_size);
3278
3279 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3280 if (buff_size > I40E_AQ_LARGE_BUF)
3281 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3282
3283 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3284 if (!status) {
3285 if (local_len != NULL)
3286 *local_len = le16_to_cpu(resp->local_len);
3287 if (remote_len != NULL)
3288 *remote_len = le16_to_cpu(resp->remote_len);
3289 }
3290
3291 return status;
3292 }
3293
3294 /**
3295 * i40e_aq_cfg_lldp_mib_change_event
3296 * @hw: pointer to the hw struct
3297 * @enable_update: Enable or Disable event posting
3298 * @cmd_details: pointer to command details structure or NULL
3299 *
3300 * Enable or Disable posting of an event on ARQ when LLDP MIB
3301 * associated with the interface changes
3302 **/
3303 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3304 bool enable_update,
3305 struct i40e_asq_cmd_details *cmd_details)
3306 {
3307 struct i40e_aq_desc desc;
3308 struct i40e_aqc_lldp_update_mib *cmd =
3309 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3310 i40e_status status;
3311
3312 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3313
3314 if (!enable_update)
3315 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3316
3317 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3318
3319 return status;
3320 }
3321
3322 /**
3323 * i40e_aq_stop_lldp
3324 * @hw: pointer to the hw struct
3325 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3326 * @cmd_details: pointer to command details structure or NULL
3327 *
3328 * Stop or Shutdown the embedded LLDP Agent
3329 **/
3330 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3331 struct i40e_asq_cmd_details *cmd_details)
3332 {
3333 struct i40e_aq_desc desc;
3334 struct i40e_aqc_lldp_stop *cmd =
3335 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3336 i40e_status status;
3337
3338 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3339
3340 if (shutdown_agent)
3341 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3342
3343 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3344
3345 return status;
3346 }
3347
3348 /**
3349 * i40e_aq_start_lldp
3350 * @hw: pointer to the hw struct
3351 * @cmd_details: pointer to command details structure or NULL
3352 *
3353 * Start the embedded LLDP Agent on all ports.
3354 **/
3355 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3356 struct i40e_asq_cmd_details *cmd_details)
3357 {
3358 struct i40e_aq_desc desc;
3359 struct i40e_aqc_lldp_start *cmd =
3360 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3361 i40e_status status;
3362
3363 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3364
3365 cmd->command = I40E_AQ_LLDP_AGENT_START;
3366
3367 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3368
3369 return status;
3370 }
3371
3372 /**
3373 * i40e_aq_get_cee_dcb_config
3374 * @hw: pointer to the hw struct
3375 * @buff: response buffer that stores CEE operational configuration
3376 * @buff_size: size of the buffer passed
3377 * @cmd_details: pointer to command details structure or NULL
3378 *
3379 * Get CEE DCBX mode operational configuration from firmware
3380 **/
3381 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3382 void *buff, u16 buff_size,
3383 struct i40e_asq_cmd_details *cmd_details)
3384 {
3385 struct i40e_aq_desc desc;
3386 i40e_status status;
3387
3388 if (buff_size == 0 || !buff)
3389 return I40E_ERR_PARAM;
3390
3391 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3392
3393 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3394 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3395 cmd_details);
3396
3397 return status;
3398 }
3399
3400 /**
3401 * i40e_aq_add_udp_tunnel
3402 * @hw: pointer to the hw struct
3403 * @udp_port: the UDP port to add
3404 * @header_len: length of the tunneling header length in DWords
3405 * @protocol_index: protocol index type
3406 * @filter_index: pointer to filter index
3407 * @cmd_details: pointer to command details structure or NULL
3408 **/
3409 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3410 u16 udp_port, u8 protocol_index,
3411 u8 *filter_index,
3412 struct i40e_asq_cmd_details *cmd_details)
3413 {
3414 struct i40e_aq_desc desc;
3415 struct i40e_aqc_add_udp_tunnel *cmd =
3416 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3417 struct i40e_aqc_del_udp_tunnel_completion *resp =
3418 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3419 i40e_status status;
3420
3421 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3422
3423 cmd->udp_port = cpu_to_le16(udp_port);
3424 cmd->protocol_type = protocol_index;
3425
3426 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3427
3428 if (!status && filter_index)
3429 *filter_index = resp->index;
3430
3431 return status;
3432 }
3433
3434 /**
3435 * i40e_aq_del_udp_tunnel
3436 * @hw: pointer to the hw struct
3437 * @index: filter index
3438 * @cmd_details: pointer to command details structure or NULL
3439 **/
3440 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3441 struct i40e_asq_cmd_details *cmd_details)
3442 {
3443 struct i40e_aq_desc desc;
3444 struct i40e_aqc_remove_udp_tunnel *cmd =
3445 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3446 i40e_status status;
3447
3448 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3449
3450 cmd->index = index;
3451
3452 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3453
3454 return status;
3455 }
3456
3457 /**
3458 * i40e_aq_delete_element - Delete switch element
3459 * @hw: pointer to the hw struct
3460 * @seid: the SEID to delete from the switch
3461 * @cmd_details: pointer to command details structure or NULL
3462 *
3463 * This deletes a switch element from the switch.
3464 **/
3465 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3466 struct i40e_asq_cmd_details *cmd_details)
3467 {
3468 struct i40e_aq_desc desc;
3469 struct i40e_aqc_switch_seid *cmd =
3470 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3471 i40e_status status;
3472
3473 if (seid == 0)
3474 return I40E_ERR_PARAM;
3475
3476 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3477
3478 cmd->seid = cpu_to_le16(seid);
3479
3480 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3481
3482 return status;
3483 }
3484
3485 /**
3486 * i40e_aq_dcb_updated - DCB Updated Command
3487 * @hw: pointer to the hw struct
3488 * @cmd_details: pointer to command details structure or NULL
3489 *
3490 * EMP will return when the shared RPB settings have been
3491 * recomputed and modified. The retval field in the descriptor
3492 * will be set to 0 when RPB is modified.
3493 **/
3494 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3495 struct i40e_asq_cmd_details *cmd_details)
3496 {
3497 struct i40e_aq_desc desc;
3498 i40e_status status;
3499
3500 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3501
3502 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3503
3504 return status;
3505 }
3506
3507 /**
3508 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3509 * @hw: pointer to the hw struct
3510 * @seid: seid for the physical port/switching component/vsi
3511 * @buff: Indirect buffer to hold data parameters and response
3512 * @buff_size: Indirect buffer size
3513 * @opcode: Tx scheduler AQ command opcode
3514 * @cmd_details: pointer to command details structure or NULL
3515 *
3516 * Generic command handler for Tx scheduler AQ commands
3517 **/
3518 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3519 void *buff, u16 buff_size,
3520 enum i40e_admin_queue_opc opcode,
3521 struct i40e_asq_cmd_details *cmd_details)
3522 {
3523 struct i40e_aq_desc desc;
3524 struct i40e_aqc_tx_sched_ind *cmd =
3525 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3526 i40e_status status;
3527 bool cmd_param_flag = false;
3528
3529 switch (opcode) {
3530 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3531 case i40e_aqc_opc_configure_vsi_tc_bw:
3532 case i40e_aqc_opc_enable_switching_comp_ets:
3533 case i40e_aqc_opc_modify_switching_comp_ets:
3534 case i40e_aqc_opc_disable_switching_comp_ets:
3535 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3536 case i40e_aqc_opc_configure_switching_comp_bw_config:
3537 cmd_param_flag = true;
3538 break;
3539 case i40e_aqc_opc_query_vsi_bw_config:
3540 case i40e_aqc_opc_query_vsi_ets_sla_config:
3541 case i40e_aqc_opc_query_switching_comp_ets_config:
3542 case i40e_aqc_opc_query_port_ets_config:
3543 case i40e_aqc_opc_query_switching_comp_bw_config:
3544 cmd_param_flag = false;
3545 break;
3546 default:
3547 return I40E_ERR_PARAM;
3548 }
3549
3550 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3551
3552 /* Indirect command */
3553 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3554 if (cmd_param_flag)
3555 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3556 if (buff_size > I40E_AQ_LARGE_BUF)
3557 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3558
3559 desc.datalen = cpu_to_le16(buff_size);
3560
3561 cmd->vsi_seid = cpu_to_le16(seid);
3562
3563 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3564
3565 return status;
3566 }
3567
3568 /**
3569 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3570 * @hw: pointer to the hw struct
3571 * @seid: VSI seid
3572 * @credit: BW limit credits (0 = disabled)
3573 * @max_credit: Max BW limit credits
3574 * @cmd_details: pointer to command details structure or NULL
3575 **/
3576 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3577 u16 seid, u16 credit, u8 max_credit,
3578 struct i40e_asq_cmd_details *cmd_details)
3579 {
3580 struct i40e_aq_desc desc;
3581 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3582 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3583 i40e_status status;
3584
3585 i40e_fill_default_direct_cmd_desc(&desc,
3586 i40e_aqc_opc_configure_vsi_bw_limit);
3587
3588 cmd->vsi_seid = cpu_to_le16(seid);
3589 cmd->credit = cpu_to_le16(credit);
3590 cmd->max_credit = max_credit;
3591
3592 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3593
3594 return status;
3595 }
3596
3597 /**
3598 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3599 * @hw: pointer to the hw struct
3600 * @seid: VSI seid
3601 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3602 * @cmd_details: pointer to command details structure or NULL
3603 **/
3604 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3605 u16 seid,
3606 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3607 struct i40e_asq_cmd_details *cmd_details)
3608 {
3609 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3610 i40e_aqc_opc_configure_vsi_tc_bw,
3611 cmd_details);
3612 }
3613
3614 /**
3615 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3616 * @hw: pointer to the hw struct
3617 * @seid: seid of the switching component connected to Physical Port
3618 * @ets_data: Buffer holding ETS parameters
3619 * @cmd_details: pointer to command details structure or NULL
3620 **/
3621 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3622 u16 seid,
3623 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3624 enum i40e_admin_queue_opc opcode,
3625 struct i40e_asq_cmd_details *cmd_details)
3626 {
3627 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3628 sizeof(*ets_data), opcode, cmd_details);
3629 }
3630
3631 /**
3632 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3633 * @hw: pointer to the hw struct
3634 * @seid: seid of the switching component
3635 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3636 * @cmd_details: pointer to command details structure or NULL
3637 **/
3638 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3639 u16 seid,
3640 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3641 struct i40e_asq_cmd_details *cmd_details)
3642 {
3643 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3644 i40e_aqc_opc_configure_switching_comp_bw_config,
3645 cmd_details);
3646 }
3647
3648 /**
3649 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3650 * @hw: pointer to the hw struct
3651 * @seid: seid of the VSI
3652 * @bw_data: Buffer to hold VSI BW configuration
3653 * @cmd_details: pointer to command details structure or NULL
3654 **/
3655 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3656 u16 seid,
3657 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3658 struct i40e_asq_cmd_details *cmd_details)
3659 {
3660 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3661 i40e_aqc_opc_query_vsi_bw_config,
3662 cmd_details);
3663 }
3664
3665 /**
3666 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3667 * @hw: pointer to the hw struct
3668 * @seid: seid of the VSI
3669 * @bw_data: Buffer to hold VSI BW configuration per TC
3670 * @cmd_details: pointer to command details structure or NULL
3671 **/
3672 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3673 u16 seid,
3674 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3675 struct i40e_asq_cmd_details *cmd_details)
3676 {
3677 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3678 i40e_aqc_opc_query_vsi_ets_sla_config,
3679 cmd_details);
3680 }
3681
3682 /**
3683 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3684 * @hw: pointer to the hw struct
3685 * @seid: seid of the switching component
3686 * @bw_data: Buffer to hold switching component's per TC BW config
3687 * @cmd_details: pointer to command details structure or NULL
3688 **/
3689 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3690 u16 seid,
3691 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3692 struct i40e_asq_cmd_details *cmd_details)
3693 {
3694 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3695 i40e_aqc_opc_query_switching_comp_ets_config,
3696 cmd_details);
3697 }
3698
3699 /**
3700 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3701 * @hw: pointer to the hw struct
3702 * @seid: seid of the VSI or switching component connected to Physical Port
3703 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3704 * @cmd_details: pointer to command details structure or NULL
3705 **/
3706 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3707 u16 seid,
3708 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3709 struct i40e_asq_cmd_details *cmd_details)
3710 {
3711 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3712 i40e_aqc_opc_query_port_ets_config,
3713 cmd_details);
3714 }
3715
3716 /**
3717 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3718 * @hw: pointer to the hw struct
3719 * @seid: seid of the switching component
3720 * @bw_data: Buffer to hold switching component's BW configuration
3721 * @cmd_details: pointer to command details structure or NULL
3722 **/
3723 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3724 u16 seid,
3725 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3726 struct i40e_asq_cmd_details *cmd_details)
3727 {
3728 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3729 i40e_aqc_opc_query_switching_comp_bw_config,
3730 cmd_details);
3731 }
3732
3733 /**
3734 * i40e_validate_filter_settings
3735 * @hw: pointer to the hardware structure
3736 * @settings: Filter control settings
3737 *
3738 * Check and validate the filter control settings passed.
3739 * The function checks for the valid filter/context sizes being
3740 * passed for FCoE and PE.
3741 *
3742 * Returns 0 if the values passed are valid and within
3743 * range else returns an error.
3744 **/
3745 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3746 struct i40e_filter_control_settings *settings)
3747 {
3748 u32 fcoe_cntx_size, fcoe_filt_size;
3749 u32 pe_cntx_size, pe_filt_size;
3750 u32 fcoe_fmax;
3751 u32 val;
3752
3753 /* Validate FCoE settings passed */
3754 switch (settings->fcoe_filt_num) {
3755 case I40E_HASH_FILTER_SIZE_1K:
3756 case I40E_HASH_FILTER_SIZE_2K:
3757 case I40E_HASH_FILTER_SIZE_4K:
3758 case I40E_HASH_FILTER_SIZE_8K:
3759 case I40E_HASH_FILTER_SIZE_16K:
3760 case I40E_HASH_FILTER_SIZE_32K:
3761 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3762 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3763 break;
3764 default:
3765 return I40E_ERR_PARAM;
3766 }
3767
3768 switch (settings->fcoe_cntx_num) {
3769 case I40E_DMA_CNTX_SIZE_512:
3770 case I40E_DMA_CNTX_SIZE_1K:
3771 case I40E_DMA_CNTX_SIZE_2K:
3772 case I40E_DMA_CNTX_SIZE_4K:
3773 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3774 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3775 break;
3776 default:
3777 return I40E_ERR_PARAM;
3778 }
3779
3780 /* Validate PE settings passed */
3781 switch (settings->pe_filt_num) {
3782 case I40E_HASH_FILTER_SIZE_1K:
3783 case I40E_HASH_FILTER_SIZE_2K:
3784 case I40E_HASH_FILTER_SIZE_4K:
3785 case I40E_HASH_FILTER_SIZE_8K:
3786 case I40E_HASH_FILTER_SIZE_16K:
3787 case I40E_HASH_FILTER_SIZE_32K:
3788 case I40E_HASH_FILTER_SIZE_64K:
3789 case I40E_HASH_FILTER_SIZE_128K:
3790 case I40E_HASH_FILTER_SIZE_256K:
3791 case I40E_HASH_FILTER_SIZE_512K:
3792 case I40E_HASH_FILTER_SIZE_1M:
3793 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3794 pe_filt_size <<= (u32)settings->pe_filt_num;
3795 break;
3796 default:
3797 return I40E_ERR_PARAM;
3798 }
3799
3800 switch (settings->pe_cntx_num) {
3801 case I40E_DMA_CNTX_SIZE_512:
3802 case I40E_DMA_CNTX_SIZE_1K:
3803 case I40E_DMA_CNTX_SIZE_2K:
3804 case I40E_DMA_CNTX_SIZE_4K:
3805 case I40E_DMA_CNTX_SIZE_8K:
3806 case I40E_DMA_CNTX_SIZE_16K:
3807 case I40E_DMA_CNTX_SIZE_32K:
3808 case I40E_DMA_CNTX_SIZE_64K:
3809 case I40E_DMA_CNTX_SIZE_128K:
3810 case I40E_DMA_CNTX_SIZE_256K:
3811 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3812 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3813 break;
3814 default:
3815 return I40E_ERR_PARAM;
3816 }
3817
3818 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3819 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3820 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3821 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3822 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3823 return I40E_ERR_INVALID_SIZE;
3824
3825 return 0;
3826 }
3827
3828 /**
3829 * i40e_set_filter_control
3830 * @hw: pointer to the hardware structure
3831 * @settings: Filter control settings
3832 *
3833 * Set the Queue Filters for PE/FCoE and enable filters required
3834 * for a single PF. It is expected that these settings are programmed
3835 * at the driver initialization time.
3836 **/
3837 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3838 struct i40e_filter_control_settings *settings)
3839 {
3840 i40e_status ret = 0;
3841 u32 hash_lut_size = 0;
3842 u32 val;
3843
3844 if (!settings)
3845 return I40E_ERR_PARAM;
3846
3847 /* Validate the input settings */
3848 ret = i40e_validate_filter_settings(hw, settings);
3849 if (ret)
3850 return ret;
3851
3852 /* Read the PF Queue Filter control register */
3853 val = rd32(hw, I40E_PFQF_CTL_0);
3854
3855 /* Program required PE hash buckets for the PF */
3856 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3857 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3858 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3859 /* Program required PE contexts for the PF */
3860 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3861 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3862 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3863
3864 /* Program required FCoE hash buckets for the PF */
3865 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3866 val |= ((u32)settings->fcoe_filt_num <<
3867 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3868 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3869 /* Program required FCoE DDP contexts for the PF */
3870 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3871 val |= ((u32)settings->fcoe_cntx_num <<
3872 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3873 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3874
3875 /* Program Hash LUT size for the PF */
3876 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3877 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3878 hash_lut_size = 1;
3879 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3880 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3881
3882 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3883 if (settings->enable_fdir)
3884 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3885 if (settings->enable_ethtype)
3886 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3887 if (settings->enable_macvlan)
3888 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3889
3890 wr32(hw, I40E_PFQF_CTL_0, val);
3891
3892 return 0;
3893 }
3894
3895 /**
3896 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3897 * @hw: pointer to the hw struct
3898 * @mac_addr: MAC address to use in the filter
3899 * @ethtype: Ethertype to use in the filter
3900 * @flags: Flags that needs to be applied to the filter
3901 * @vsi_seid: seid of the control VSI
3902 * @queue: VSI queue number to send the packet to
3903 * @is_add: Add control packet filter if True else remove
3904 * @stats: Structure to hold information on control filter counts
3905 * @cmd_details: pointer to command details structure or NULL
3906 *
3907 * This command will Add or Remove control packet filter for a control VSI.
3908 * In return it will update the total number of perfect filter count in
3909 * the stats member.
3910 **/
3911 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3912 u8 *mac_addr, u16 ethtype, u16 flags,
3913 u16 vsi_seid, u16 queue, bool is_add,
3914 struct i40e_control_filter_stats *stats,
3915 struct i40e_asq_cmd_details *cmd_details)
3916 {
3917 struct i40e_aq_desc desc;
3918 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3919 (struct i40e_aqc_add_remove_control_packet_filter *)
3920 &desc.params.raw;
3921 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3922 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3923 &desc.params.raw;
3924 i40e_status status;
3925
3926 if (vsi_seid == 0)
3927 return I40E_ERR_PARAM;
3928
3929 if (is_add) {
3930 i40e_fill_default_direct_cmd_desc(&desc,
3931 i40e_aqc_opc_add_control_packet_filter);
3932 cmd->queue = cpu_to_le16(queue);
3933 } else {
3934 i40e_fill_default_direct_cmd_desc(&desc,
3935 i40e_aqc_opc_remove_control_packet_filter);
3936 }
3937
3938 if (mac_addr)
3939 ether_addr_copy(cmd->mac, mac_addr);
3940
3941 cmd->etype = cpu_to_le16(ethtype);
3942 cmd->flags = cpu_to_le16(flags);
3943 cmd->seid = cpu_to_le16(vsi_seid);
3944
3945 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3946
3947 if (!status && stats) {
3948 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3949 stats->etype_used = le16_to_cpu(resp->etype_used);
3950 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3951 stats->etype_free = le16_to_cpu(resp->etype_free);
3952 }
3953
3954 return status;
3955 }
3956
3957 /**
3958 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
3959 * @hw: pointer to the hw struct
3960 * @seid: VSI seid to add ethertype filter from
3961 **/
3962 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
3963 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
3964 u16 seid)
3965 {
3966 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
3967 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
3968 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
3969 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
3970 i40e_status status;
3971
3972 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
3973 seid, 0, true, NULL,
3974 NULL);
3975 if (status)
3976 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
3977 }
3978
3979 /**
3980 * i40e_aq_alternate_read
3981 * @hw: pointer to the hardware structure
3982 * @reg_addr0: address of first dword to be read
3983 * @reg_val0: pointer for data read from 'reg_addr0'
3984 * @reg_addr1: address of second dword to be read
3985 * @reg_val1: pointer for data read from 'reg_addr1'
3986 *
3987 * Read one or two dwords from alternate structure. Fields are indicated
3988 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
3989 * is not passed then only register at 'reg_addr0' is read.
3990 *
3991 **/
3992 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
3993 u32 reg_addr0, u32 *reg_val0,
3994 u32 reg_addr1, u32 *reg_val1)
3995 {
3996 struct i40e_aq_desc desc;
3997 struct i40e_aqc_alternate_write *cmd_resp =
3998 (struct i40e_aqc_alternate_write *)&desc.params.raw;
3999 i40e_status status;
4000
4001 if (!reg_val0)
4002 return I40E_ERR_PARAM;
4003
4004 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4005 cmd_resp->address0 = cpu_to_le32(reg_addr0);
4006 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4007
4008 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4009
4010 if (!status) {
4011 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4012
4013 if (reg_val1)
4014 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4015 }
4016
4017 return status;
4018 }
4019
4020 /**
4021 * i40e_aq_resume_port_tx
4022 * @hw: pointer to the hardware structure
4023 * @cmd_details: pointer to command details structure or NULL
4024 *
4025 * Resume port's Tx traffic
4026 **/
4027 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4028 struct i40e_asq_cmd_details *cmd_details)
4029 {
4030 struct i40e_aq_desc desc;
4031 i40e_status status;
4032
4033 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4034
4035 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4036
4037 return status;
4038 }
4039
4040 /**
4041 * i40e_set_pci_config_data - store PCI bus info
4042 * @hw: pointer to hardware structure
4043 * @link_status: the link status word from PCI config space
4044 *
4045 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4046 **/
4047 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4048 {
4049 hw->bus.type = i40e_bus_type_pci_express;
4050
4051 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4052 case PCI_EXP_LNKSTA_NLW_X1:
4053 hw->bus.width = i40e_bus_width_pcie_x1;
4054 break;
4055 case PCI_EXP_LNKSTA_NLW_X2:
4056 hw->bus.width = i40e_bus_width_pcie_x2;
4057 break;
4058 case PCI_EXP_LNKSTA_NLW_X4:
4059 hw->bus.width = i40e_bus_width_pcie_x4;
4060 break;
4061 case PCI_EXP_LNKSTA_NLW_X8:
4062 hw->bus.width = i40e_bus_width_pcie_x8;
4063 break;
4064 default:
4065 hw->bus.width = i40e_bus_width_unknown;
4066 break;
4067 }
4068
4069 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4070 case PCI_EXP_LNKSTA_CLS_2_5GB:
4071 hw->bus.speed = i40e_bus_speed_2500;
4072 break;
4073 case PCI_EXP_LNKSTA_CLS_5_0GB:
4074 hw->bus.speed = i40e_bus_speed_5000;
4075 break;
4076 case PCI_EXP_LNKSTA_CLS_8_0GB:
4077 hw->bus.speed = i40e_bus_speed_8000;
4078 break;
4079 default:
4080 hw->bus.speed = i40e_bus_speed_unknown;
4081 break;
4082 }
4083 }
4084
4085 /**
4086 * i40e_aq_debug_dump
4087 * @hw: pointer to the hardware structure
4088 * @cluster_id: specific cluster to dump
4089 * @table_id: table id within cluster
4090 * @start_index: index of line in the block to read
4091 * @buff_size: dump buffer size
4092 * @buff: dump buffer
4093 * @ret_buff_size: actual buffer size returned
4094 * @ret_next_table: next block to read
4095 * @ret_next_index: next index to read
4096 *
4097 * Dump internal FW/HW data for debug purposes.
4098 *
4099 **/
4100 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4101 u8 table_id, u32 start_index, u16 buff_size,
4102 void *buff, u16 *ret_buff_size,
4103 u8 *ret_next_table, u32 *ret_next_index,
4104 struct i40e_asq_cmd_details *cmd_details)
4105 {
4106 struct i40e_aq_desc desc;
4107 struct i40e_aqc_debug_dump_internals *cmd =
4108 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4109 struct i40e_aqc_debug_dump_internals *resp =
4110 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4111 i40e_status status;
4112
4113 if (buff_size == 0 || !buff)
4114 return I40E_ERR_PARAM;
4115
4116 i40e_fill_default_direct_cmd_desc(&desc,
4117 i40e_aqc_opc_debug_dump_internals);
4118 /* Indirect Command */
4119 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4120 if (buff_size > I40E_AQ_LARGE_BUF)
4121 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4122
4123 cmd->cluster_id = cluster_id;
4124 cmd->table_id = table_id;
4125 cmd->idx = cpu_to_le32(start_index);
4126
4127 desc.datalen = cpu_to_le16(buff_size);
4128
4129 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4130 if (!status) {
4131 if (ret_buff_size)
4132 *ret_buff_size = le16_to_cpu(desc.datalen);
4133 if (ret_next_table)
4134 *ret_next_table = resp->table_id;
4135 if (ret_next_index)
4136 *ret_next_index = le32_to_cpu(resp->idx);
4137 }
4138
4139 return status;
4140 }
4141
4142 /**
4143 * i40e_read_bw_from_alt_ram
4144 * @hw: pointer to the hardware structure
4145 * @max_bw: pointer for max_bw read
4146 * @min_bw: pointer for min_bw read
4147 * @min_valid: pointer for bool that is true if min_bw is a valid value
4148 * @max_valid: pointer for bool that is true if max_bw is a valid value
4149 *
4150 * Read bw from the alternate ram for the given pf
4151 **/
4152 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4153 u32 *max_bw, u32 *min_bw,
4154 bool *min_valid, bool *max_valid)
4155 {
4156 i40e_status status;
4157 u32 max_bw_addr, min_bw_addr;
4158
4159 /* Calculate the address of the min/max bw registers */
4160 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4161 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4162 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4163 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4164 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4165 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4166
4167 /* Read the bandwidths from alt ram */
4168 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4169 min_bw_addr, min_bw);
4170
4171 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4172 *min_valid = true;
4173 else
4174 *min_valid = false;
4175
4176 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4177 *max_valid = true;
4178 else
4179 *max_valid = false;
4180
4181 return status;
4182 }
4183
4184 /**
4185 * i40e_aq_configure_partition_bw
4186 * @hw: pointer to the hardware structure
4187 * @bw_data: Buffer holding valid pfs and bw limits
4188 * @cmd_details: pointer to command details
4189 *
4190 * Configure partitions guaranteed/max bw
4191 **/
4192 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4193 struct i40e_aqc_configure_partition_bw_data *bw_data,
4194 struct i40e_asq_cmd_details *cmd_details)
4195 {
4196 i40e_status status;
4197 struct i40e_aq_desc desc;
4198 u16 bwd_size = sizeof(*bw_data);
4199
4200 i40e_fill_default_direct_cmd_desc(&desc,
4201 i40e_aqc_opc_configure_partition_bw);
4202
4203 /* Indirect command */
4204 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4205 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4206
4207 if (bwd_size > I40E_AQ_LARGE_BUF)
4208 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4209
4210 desc.datalen = cpu_to_le16(bwd_size);
4211
4212 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4213 cmd_details);
4214
4215 return status;
4216 }
Linux kernel - Deliverables
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