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Merge tag 'batman-adv-for-davem' of git://git.open-mesh.org/linux-merge
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
31
32 /**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40 {
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
45 case I40E_SFP_XL710_DEVICE_ID:
46 case I40E_SFP_X710_DEVICE_ID:
47 case I40E_QEMU_DEVICE_ID:
48 case I40E_KX_A_DEVICE_ID:
49 case I40E_KX_B_DEVICE_ID:
50 case I40E_KX_C_DEVICE_ID:
51 case I40E_KX_D_DEVICE_ID:
52 case I40E_QSFP_A_DEVICE_ID:
53 case I40E_QSFP_B_DEVICE_ID:
54 case I40E_QSFP_C_DEVICE_ID:
55 hw->mac.type = I40E_MAC_XL710;
56 break;
57 case I40E_VF_DEVICE_ID:
58 case I40E_VF_HV_DEVICE_ID:
59 hw->mac.type = I40E_MAC_VF;
60 break;
61 default:
62 hw->mac.type = I40E_MAC_GENERIC;
63 break;
64 }
65 } else {
66 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
67 }
68
69 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
70 hw->mac.type, status);
71 return status;
72 }
73
74 /**
75 * i40e_debug_aq
76 * @hw: debug mask related to admin queue
77 * @cap: pointer to adminq command descriptor
78 * @buffer: pointer to command buffer
79 *
80 * Dumps debug log about adminq command with descriptor contents.
81 **/
82 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
83 void *buffer)
84 {
85 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
86 u8 *aq_buffer = (u8 *)buffer;
87 u32 data[4];
88 u32 i = 0;
89
90 if ((!(mask & hw->debug_mask)) || (desc == NULL))
91 return;
92
93 i40e_debug(hw, mask,
94 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
95 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
96 aq_desc->retval);
97 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
98 aq_desc->cookie_high, aq_desc->cookie_low);
99 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
100 aq_desc->params.internal.param0,
101 aq_desc->params.internal.param1);
102 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
103 aq_desc->params.external.addr_high,
104 aq_desc->params.external.addr_low);
105
106 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
107 memset(data, 0, sizeof(data));
108 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
109 for (i = 0; i < le16_to_cpu(aq_desc->datalen); i++) {
110 data[((i % 16) / 4)] |=
111 ((u32)aq_buffer[i]) << (8 * (i % 4));
112 if ((i % 16) == 15) {
113 i40e_debug(hw, mask,
114 "\t0x%04X %08X %08X %08X %08X\n",
115 i - 15, data[0], data[1], data[2],
116 data[3]);
117 memset(data, 0, sizeof(data));
118 }
119 }
120 if ((i % 16) != 0)
121 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
122 i - (i % 16), data[0], data[1], data[2],
123 data[3]);
124 }
125 }
126
127 /**
128 * i40e_check_asq_alive
129 * @hw: pointer to the hw struct
130 *
131 * Returns true if Queue is enabled else false.
132 **/
133 bool i40e_check_asq_alive(struct i40e_hw *hw)
134 {
135 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
136 }
137
138 /**
139 * i40e_aq_queue_shutdown
140 * @hw: pointer to the hw struct
141 * @unloading: is the driver unloading itself
142 *
143 * Tell the Firmware that we're shutting down the AdminQ and whether
144 * or not the driver is unloading as well.
145 **/
146 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
147 bool unloading)
148 {
149 struct i40e_aq_desc desc;
150 struct i40e_aqc_queue_shutdown *cmd =
151 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
152 i40e_status status;
153
154 i40e_fill_default_direct_cmd_desc(&desc,
155 i40e_aqc_opc_queue_shutdown);
156
157 if (unloading)
158 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
159 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
160
161 return status;
162 }
163
164
165 /**
166 * i40e_init_shared_code - Initialize the shared code
167 * @hw: pointer to hardware structure
168 *
169 * This assigns the MAC type and PHY code and inits the NVM.
170 * Does not touch the hardware. This function must be called prior to any
171 * other function in the shared code. The i40e_hw structure should be
172 * memset to 0 prior to calling this function. The following fields in
173 * hw structure should be filled in prior to calling this function:
174 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
175 * subsystem_vendor_id, and revision_id
176 **/
177 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
178 {
179 i40e_status status = 0;
180 u32 reg;
181
182 i40e_set_mac_type(hw);
183
184 switch (hw->mac.type) {
185 case I40E_MAC_XL710:
186 break;
187 default:
188 return I40E_ERR_DEVICE_NOT_SUPPORTED;
189 break;
190 }
191
192 hw->phy.get_link_info = true;
193
194 /* Determine port number */
195 reg = rd32(hw, I40E_PFGEN_PORTNUM);
196 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
197 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
198 hw->port = (u8)reg;
199
200 /* Determine the PF number based on the PCI fn */
201 reg = rd32(hw, I40E_GLPCI_CAPSUP);
202 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
203 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
204 else
205 hw->pf_id = (u8)hw->bus.func;
206
207 status = i40e_init_nvm(hw);
208 return status;
209 }
210
211 /**
212 * i40e_aq_mac_address_read - Retrieve the MAC addresses
213 * @hw: pointer to the hw struct
214 * @flags: a return indicator of what addresses were added to the addr store
215 * @addrs: the requestor's mac addr store
216 * @cmd_details: pointer to command details structure or NULL
217 **/
218 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
219 u16 *flags,
220 struct i40e_aqc_mac_address_read_data *addrs,
221 struct i40e_asq_cmd_details *cmd_details)
222 {
223 struct i40e_aq_desc desc;
224 struct i40e_aqc_mac_address_read *cmd_data =
225 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
226 i40e_status status;
227
228 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
229 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
230
231 status = i40e_asq_send_command(hw, &desc, addrs,
232 sizeof(*addrs), cmd_details);
233 *flags = le16_to_cpu(cmd_data->command_flags);
234
235 return status;
236 }
237
238 /**
239 * i40e_aq_mac_address_write - Change the MAC addresses
240 * @hw: pointer to the hw struct
241 * @flags: indicates which MAC to be written
242 * @mac_addr: address to write
243 * @cmd_details: pointer to command details structure or NULL
244 **/
245 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
246 u16 flags, u8 *mac_addr,
247 struct i40e_asq_cmd_details *cmd_details)
248 {
249 struct i40e_aq_desc desc;
250 struct i40e_aqc_mac_address_write *cmd_data =
251 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
252 i40e_status status;
253
254 i40e_fill_default_direct_cmd_desc(&desc,
255 i40e_aqc_opc_mac_address_write);
256 cmd_data->command_flags = cpu_to_le16(flags);
257 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
258 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
259 ((u32)mac_addr[3] << 16) |
260 ((u32)mac_addr[4] << 8) |
261 mac_addr[5]);
262
263 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
264
265 return status;
266 }
267
268 /**
269 * i40e_get_mac_addr - get MAC address
270 * @hw: pointer to the HW structure
271 * @mac_addr: pointer to MAC address
272 *
273 * Reads the adapter's MAC address from register
274 **/
275 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
276 {
277 struct i40e_aqc_mac_address_read_data addrs;
278 i40e_status status;
279 u16 flags = 0;
280
281 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
282
283 if (flags & I40E_AQC_LAN_ADDR_VALID)
284 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
285
286 return status;
287 }
288
289 /**
290 * i40e_get_media_type - Gets media type
291 * @hw: pointer to the hardware structure
292 **/
293 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
294 {
295 enum i40e_media_type media;
296
297 switch (hw->phy.link_info.phy_type) {
298 case I40E_PHY_TYPE_10GBASE_SR:
299 case I40E_PHY_TYPE_10GBASE_LR:
300 case I40E_PHY_TYPE_40GBASE_SR4:
301 case I40E_PHY_TYPE_40GBASE_LR4:
302 media = I40E_MEDIA_TYPE_FIBER;
303 break;
304 case I40E_PHY_TYPE_100BASE_TX:
305 case I40E_PHY_TYPE_1000BASE_T:
306 case I40E_PHY_TYPE_10GBASE_T:
307 media = I40E_MEDIA_TYPE_BASET;
308 break;
309 case I40E_PHY_TYPE_10GBASE_CR1_CU:
310 case I40E_PHY_TYPE_40GBASE_CR4_CU:
311 case I40E_PHY_TYPE_10GBASE_CR1:
312 case I40E_PHY_TYPE_40GBASE_CR4:
313 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
314 media = I40E_MEDIA_TYPE_DA;
315 break;
316 case I40E_PHY_TYPE_1000BASE_KX:
317 case I40E_PHY_TYPE_10GBASE_KX4:
318 case I40E_PHY_TYPE_10GBASE_KR:
319 case I40E_PHY_TYPE_40GBASE_KR4:
320 media = I40E_MEDIA_TYPE_BACKPLANE;
321 break;
322 case I40E_PHY_TYPE_SGMII:
323 case I40E_PHY_TYPE_XAUI:
324 case I40E_PHY_TYPE_XFI:
325 case I40E_PHY_TYPE_XLAUI:
326 case I40E_PHY_TYPE_XLPPI:
327 default:
328 media = I40E_MEDIA_TYPE_UNKNOWN;
329 break;
330 }
331
332 return media;
333 }
334
335 #define I40E_PF_RESET_WAIT_COUNT_A0 200
336 #define I40E_PF_RESET_WAIT_COUNT 10
337 /**
338 * i40e_pf_reset - Reset the PF
339 * @hw: pointer to the hardware structure
340 *
341 * Assuming someone else has triggered a global reset,
342 * assure the global reset is complete and then reset the PF
343 **/
344 i40e_status i40e_pf_reset(struct i40e_hw *hw)
345 {
346 u32 cnt = 0;
347 u32 cnt1 = 0;
348 u32 reg = 0;
349 u32 grst_del;
350
351 /* Poll for Global Reset steady state in case of recent GRST.
352 * The grst delay value is in 100ms units, and we'll wait a
353 * couple counts longer to be sure we don't just miss the end.
354 */
355 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
356 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
357 for (cnt = 0; cnt < grst_del + 2; cnt++) {
358 reg = rd32(hw, I40E_GLGEN_RSTAT);
359 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
360 break;
361 msleep(100);
362 }
363 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
364 hw_dbg(hw, "Global reset polling failed to complete.\n");
365 return I40E_ERR_RESET_FAILED;
366 }
367
368 /* Now Wait for the FW to be ready */
369 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
370 reg = rd32(hw, I40E_GLNVM_ULD);
371 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
372 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
373 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
374 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
375 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
376 break;
377 }
378 usleep_range(10000, 20000);
379 }
380 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
381 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
382 hw_dbg(hw, "wait for FW Reset complete timedout\n");
383 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
384 return I40E_ERR_RESET_FAILED;
385 }
386
387 /* If there was a Global Reset in progress when we got here,
388 * we don't need to do the PF Reset
389 */
390 if (!cnt) {
391 if (hw->revision_id == 0)
392 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
393 else
394 cnt = I40E_PF_RESET_WAIT_COUNT;
395 reg = rd32(hw, I40E_PFGEN_CTRL);
396 wr32(hw, I40E_PFGEN_CTRL,
397 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
398 for (; cnt; cnt--) {
399 reg = rd32(hw, I40E_PFGEN_CTRL);
400 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
401 break;
402 usleep_range(1000, 2000);
403 }
404 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
405 hw_dbg(hw, "PF reset polling failed to complete.\n");
406 return I40E_ERR_RESET_FAILED;
407 }
408 }
409
410 i40e_clear_pxe_mode(hw);
411
412 return 0;
413 }
414
415 /**
416 * i40e_clear_pxe_mode - clear pxe operations mode
417 * @hw: pointer to the hw struct
418 *
419 * Make sure all PXE mode settings are cleared, including things
420 * like descriptor fetch/write-back mode.
421 **/
422 void i40e_clear_pxe_mode(struct i40e_hw *hw)
423 {
424 u32 reg;
425
426 /* Clear single descriptor fetch/write-back mode */
427 reg = rd32(hw, I40E_GLLAN_RCTL_0);
428
429 if (hw->revision_id == 0) {
430 /* As a work around clear PXE_MODE instead of setting it */
431 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
432 } else {
433 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
434 }
435 }
436
437 /**
438 * i40e_led_is_mine - helper to find matching led
439 * @hw: pointer to the hw struct
440 * @idx: index into GPIO registers
441 *
442 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
443 */
444 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
445 {
446 u32 gpio_val = 0;
447 u32 port;
448
449 if (!hw->func_caps.led[idx])
450 return 0;
451
452 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
453 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
454 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
455
456 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
457 * if it is not our port then ignore
458 */
459 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
460 (port != hw->port))
461 return 0;
462
463 return gpio_val;
464 }
465
466 #define I40E_LED0 22
467 #define I40E_LINK_ACTIVITY 0xC
468
469 /**
470 * i40e_led_get - return current on/off mode
471 * @hw: pointer to the hw struct
472 *
473 * The value returned is the 'mode' field as defined in the
474 * GPIO register definitions: 0x0 = off, 0xf = on, and other
475 * values are variations of possible behaviors relating to
476 * blink, link, and wire.
477 **/
478 u32 i40e_led_get(struct i40e_hw *hw)
479 {
480 u32 mode = 0;
481 int i;
482
483 /* as per the documentation GPIO 22-29 are the LED
484 * GPIO pins named LED0..LED7
485 */
486 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
487 u32 gpio_val = i40e_led_is_mine(hw, i);
488
489 if (!gpio_val)
490 continue;
491
492 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
493 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
494 break;
495 }
496
497 return mode;
498 }
499
500 /**
501 * i40e_led_set - set new on/off mode
502 * @hw: pointer to the hw struct
503 * @mode: 0=off, 0xf=on (else see manual for mode details)
504 * @blink: true if the LED should blink when on, false if steady
505 *
506 * if this function is used to turn on the blink it should
507 * be used to disable the blink when restoring the original state.
508 **/
509 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
510 {
511 int i;
512
513 if (mode & 0xfffffff0)
514 hw_dbg(hw, "invalid mode passed in %X\n", mode);
515
516 /* as per the documentation GPIO 22-29 are the LED
517 * GPIO pins named LED0..LED7
518 */
519 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
520 u32 gpio_val = i40e_led_is_mine(hw, i);
521
522 if (!gpio_val)
523 continue;
524
525 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
526 /* this & is a bit of paranoia, but serves as a range check */
527 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
528 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
529
530 if (mode == I40E_LINK_ACTIVITY)
531 blink = false;
532
533 gpio_val |= (blink ? 1 : 0) <<
534 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
535
536 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
537 break;
538 }
539 }
540
541 /* Admin command wrappers */
542
543 /**
544 * i40e_aq_set_link_restart_an
545 * @hw: pointer to the hw struct
546 * @cmd_details: pointer to command details structure or NULL
547 *
548 * Sets up the link and restarts the Auto-Negotiation over the link.
549 **/
550 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
551 struct i40e_asq_cmd_details *cmd_details)
552 {
553 struct i40e_aq_desc desc;
554 struct i40e_aqc_set_link_restart_an *cmd =
555 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
556 i40e_status status;
557
558 i40e_fill_default_direct_cmd_desc(&desc,
559 i40e_aqc_opc_set_link_restart_an);
560
561 cmd->command = I40E_AQ_PHY_RESTART_AN;
562
563 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
564
565 return status;
566 }
567
568 /**
569 * i40e_aq_get_link_info
570 * @hw: pointer to the hw struct
571 * @enable_lse: enable/disable LinkStatusEvent reporting
572 * @link: pointer to link status structure - optional
573 * @cmd_details: pointer to command details structure or NULL
574 *
575 * Returns the link status of the adapter.
576 **/
577 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
578 bool enable_lse, struct i40e_link_status *link,
579 struct i40e_asq_cmd_details *cmd_details)
580 {
581 struct i40e_aq_desc desc;
582 struct i40e_aqc_get_link_status *resp =
583 (struct i40e_aqc_get_link_status *)&desc.params.raw;
584 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
585 i40e_status status;
586 u16 command_flags;
587
588 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
589
590 if (enable_lse)
591 command_flags = I40E_AQ_LSE_ENABLE;
592 else
593 command_flags = I40E_AQ_LSE_DISABLE;
594 resp->command_flags = cpu_to_le16(command_flags);
595
596 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
597
598 if (status)
599 goto aq_get_link_info_exit;
600
601 /* save off old link status information */
602 memcpy(&hw->phy.link_info_old, hw_link_info,
603 sizeof(struct i40e_link_status));
604
605 /* update link status */
606 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
607 hw->phy.media_type = i40e_get_media_type(hw);
608 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
609 hw_link_info->link_info = resp->link_info;
610 hw_link_info->an_info = resp->an_info;
611 hw_link_info->ext_info = resp->ext_info;
612 hw_link_info->loopback = resp->loopback;
613
614 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
615 hw_link_info->lse_enable = true;
616 else
617 hw_link_info->lse_enable = false;
618
619 /* save link status information */
620 if (link)
621 *link = *hw_link_info;
622
623 /* flag cleared so helper functions don't call AQ again */
624 hw->phy.get_link_info = false;
625
626 aq_get_link_info_exit:
627 return status;
628 }
629
630 /**
631 * i40e_aq_add_vsi
632 * @hw: pointer to the hw struct
633 * @vsi: pointer to a vsi context struct
634 * @cmd_details: pointer to command details structure or NULL
635 *
636 * Add a VSI context to the hardware.
637 **/
638 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
639 struct i40e_vsi_context *vsi_ctx,
640 struct i40e_asq_cmd_details *cmd_details)
641 {
642 struct i40e_aq_desc desc;
643 struct i40e_aqc_add_get_update_vsi *cmd =
644 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
645 struct i40e_aqc_add_get_update_vsi_completion *resp =
646 (struct i40e_aqc_add_get_update_vsi_completion *)
647 &desc.params.raw;
648 i40e_status status;
649
650 i40e_fill_default_direct_cmd_desc(&desc,
651 i40e_aqc_opc_add_vsi);
652
653 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
654 cmd->connection_type = vsi_ctx->connection_type;
655 cmd->vf_id = vsi_ctx->vf_num;
656 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
657
658 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
659 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
660 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
661
662 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
663 sizeof(vsi_ctx->info), cmd_details);
664
665 if (status)
666 goto aq_add_vsi_exit;
667
668 vsi_ctx->seid = le16_to_cpu(resp->seid);
669 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
670 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
671 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
672
673 aq_add_vsi_exit:
674 return status;
675 }
676
677 /**
678 * i40e_aq_set_vsi_unicast_promiscuous
679 * @hw: pointer to the hw struct
680 * @seid: vsi number
681 * @set: set unicast promiscuous enable/disable
682 * @cmd_details: pointer to command details structure or NULL
683 **/
684 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
685 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
686 {
687 struct i40e_aq_desc desc;
688 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
689 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
690 i40e_status status;
691 u16 flags = 0;
692
693 i40e_fill_default_direct_cmd_desc(&desc,
694 i40e_aqc_opc_set_vsi_promiscuous_modes);
695
696 if (set)
697 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
698
699 cmd->promiscuous_flags = cpu_to_le16(flags);
700
701 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
702
703 cmd->seid = cpu_to_le16(seid);
704 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
705
706 return status;
707 }
708
709 /**
710 * i40e_aq_set_vsi_multicast_promiscuous
711 * @hw: pointer to the hw struct
712 * @seid: vsi number
713 * @set: set multicast promiscuous enable/disable
714 * @cmd_details: pointer to command details structure or NULL
715 **/
716 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
717 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
718 {
719 struct i40e_aq_desc desc;
720 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
721 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
722 i40e_status status;
723 u16 flags = 0;
724
725 i40e_fill_default_direct_cmd_desc(&desc,
726 i40e_aqc_opc_set_vsi_promiscuous_modes);
727
728 if (set)
729 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
730
731 cmd->promiscuous_flags = cpu_to_le16(flags);
732
733 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
734
735 cmd->seid = cpu_to_le16(seid);
736 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
737
738 return status;
739 }
740
741 /**
742 * i40e_aq_set_vsi_broadcast
743 * @hw: pointer to the hw struct
744 * @seid: vsi number
745 * @set_filter: true to set filter, false to clear filter
746 * @cmd_details: pointer to command details structure or NULL
747 *
748 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
749 **/
750 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
751 u16 seid, bool set_filter,
752 struct i40e_asq_cmd_details *cmd_details)
753 {
754 struct i40e_aq_desc desc;
755 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
756 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
757 i40e_status status;
758
759 i40e_fill_default_direct_cmd_desc(&desc,
760 i40e_aqc_opc_set_vsi_promiscuous_modes);
761
762 if (set_filter)
763 cmd->promiscuous_flags
764 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
765 else
766 cmd->promiscuous_flags
767 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
768
769 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
770 cmd->seid = cpu_to_le16(seid);
771 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
772
773 return status;
774 }
775
776 /**
777 * i40e_get_vsi_params - get VSI configuration info
778 * @hw: pointer to the hw struct
779 * @vsi: pointer to a vsi context struct
780 * @cmd_details: pointer to command details structure or NULL
781 **/
782 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
783 struct i40e_vsi_context *vsi_ctx,
784 struct i40e_asq_cmd_details *cmd_details)
785 {
786 struct i40e_aq_desc desc;
787 struct i40e_aqc_add_get_update_vsi *cmd =
788 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
789 struct i40e_aqc_add_get_update_vsi_completion *resp =
790 (struct i40e_aqc_add_get_update_vsi_completion *)
791 &desc.params.raw;
792 i40e_status status;
793
794 i40e_fill_default_direct_cmd_desc(&desc,
795 i40e_aqc_opc_get_vsi_parameters);
796
797 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
798
799 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
800 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
801 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
802
803 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
804 sizeof(vsi_ctx->info), NULL);
805
806 if (status)
807 goto aq_get_vsi_params_exit;
808
809 vsi_ctx->seid = le16_to_cpu(resp->seid);
810 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
811 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
812 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
813
814 aq_get_vsi_params_exit:
815 return status;
816 }
817
818 /**
819 * i40e_aq_update_vsi_params
820 * @hw: pointer to the hw struct
821 * @vsi: pointer to a vsi context struct
822 * @cmd_details: pointer to command details structure or NULL
823 *
824 * Update a VSI context.
825 **/
826 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
827 struct i40e_vsi_context *vsi_ctx,
828 struct i40e_asq_cmd_details *cmd_details)
829 {
830 struct i40e_aq_desc desc;
831 struct i40e_aqc_add_get_update_vsi *cmd =
832 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
833 i40e_status status;
834
835 i40e_fill_default_direct_cmd_desc(&desc,
836 i40e_aqc_opc_update_vsi_parameters);
837 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
838
839 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
840 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
841 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
842
843 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
844 sizeof(vsi_ctx->info), cmd_details);
845
846 return status;
847 }
848
849 /**
850 * i40e_aq_get_switch_config
851 * @hw: pointer to the hardware structure
852 * @buf: pointer to the result buffer
853 * @buf_size: length of input buffer
854 * @start_seid: seid to start for the report, 0 == beginning
855 * @cmd_details: pointer to command details structure or NULL
856 *
857 * Fill the buf with switch configuration returned from AdminQ command
858 **/
859 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
860 struct i40e_aqc_get_switch_config_resp *buf,
861 u16 buf_size, u16 *start_seid,
862 struct i40e_asq_cmd_details *cmd_details)
863 {
864 struct i40e_aq_desc desc;
865 struct i40e_aqc_switch_seid *scfg =
866 (struct i40e_aqc_switch_seid *)&desc.params.raw;
867 i40e_status status;
868
869 i40e_fill_default_direct_cmd_desc(&desc,
870 i40e_aqc_opc_get_switch_config);
871 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
872 if (buf_size > I40E_AQ_LARGE_BUF)
873 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
874 scfg->seid = cpu_to_le16(*start_seid);
875
876 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
877 *start_seid = le16_to_cpu(scfg->seid);
878
879 return status;
880 }
881
882 /**
883 * i40e_aq_get_firmware_version
884 * @hw: pointer to the hw struct
885 * @fw_major_version: firmware major version
886 * @fw_minor_version: firmware minor version
887 * @api_major_version: major queue version
888 * @api_minor_version: minor queue version
889 * @cmd_details: pointer to command details structure or NULL
890 *
891 * Get the firmware version from the admin queue commands
892 **/
893 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
894 u16 *fw_major_version, u16 *fw_minor_version,
895 u16 *api_major_version, u16 *api_minor_version,
896 struct i40e_asq_cmd_details *cmd_details)
897 {
898 struct i40e_aq_desc desc;
899 struct i40e_aqc_get_version *resp =
900 (struct i40e_aqc_get_version *)&desc.params.raw;
901 i40e_status status;
902
903 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
904
905 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
906
907 if (!status) {
908 if (fw_major_version != NULL)
909 *fw_major_version = le16_to_cpu(resp->fw_major);
910 if (fw_minor_version != NULL)
911 *fw_minor_version = le16_to_cpu(resp->fw_minor);
912 if (api_major_version != NULL)
913 *api_major_version = le16_to_cpu(resp->api_major);
914 if (api_minor_version != NULL)
915 *api_minor_version = le16_to_cpu(resp->api_minor);
916 }
917
918 return status;
919 }
920
921 /**
922 * i40e_aq_send_driver_version
923 * @hw: pointer to the hw struct
924 * @event: driver event: driver ok, start or stop
925 * @dv: driver's major, minor version
926 * @cmd_details: pointer to command details structure or NULL
927 *
928 * Send the driver version to the firmware
929 **/
930 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
931 struct i40e_driver_version *dv,
932 struct i40e_asq_cmd_details *cmd_details)
933 {
934 struct i40e_aq_desc desc;
935 struct i40e_aqc_driver_version *cmd =
936 (struct i40e_aqc_driver_version *)&desc.params.raw;
937 i40e_status status;
938
939 if (dv == NULL)
940 return I40E_ERR_PARAM;
941
942 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
943
944 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
945 cmd->driver_major_ver = dv->major_version;
946 cmd->driver_minor_ver = dv->minor_version;
947 cmd->driver_build_ver = dv->build_version;
948 cmd->driver_subbuild_ver = dv->subbuild_version;
949 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
950
951 return status;
952 }
953
954 /**
955 * i40e_get_link_status - get status of the HW network link
956 * @hw: pointer to the hw struct
957 *
958 * Returns true if link is up, false if link is down.
959 *
960 * Side effect: LinkStatusEvent reporting becomes enabled
961 **/
962 bool i40e_get_link_status(struct i40e_hw *hw)
963 {
964 i40e_status status = 0;
965 bool link_status = false;
966
967 if (hw->phy.get_link_info) {
968 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
969
970 if (status)
971 goto i40e_get_link_status_exit;
972 }
973
974 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
975
976 i40e_get_link_status_exit:
977 return link_status;
978 }
979
980 /**
981 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
982 * @hw: pointer to the hw struct
983 * @uplink_seid: the MAC or other gizmo SEID
984 * @downlink_seid: the VSI SEID
985 * @enabled_tc: bitmap of TCs to be enabled
986 * @default_port: true for default port VSI, false for control port
987 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
988 * @veb_seid: pointer to where to put the resulting VEB SEID
989 * @cmd_details: pointer to command details structure or NULL
990 *
991 * This asks the FW to add a VEB between the uplink and downlink
992 * elements. If the uplink SEID is 0, this will be a floating VEB.
993 **/
994 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
995 u16 downlink_seid, u8 enabled_tc,
996 bool default_port, bool enable_l2_filtering,
997 u16 *veb_seid,
998 struct i40e_asq_cmd_details *cmd_details)
999 {
1000 struct i40e_aq_desc desc;
1001 struct i40e_aqc_add_veb *cmd =
1002 (struct i40e_aqc_add_veb *)&desc.params.raw;
1003 struct i40e_aqc_add_veb_completion *resp =
1004 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1005 i40e_status status;
1006 u16 veb_flags = 0;
1007
1008 /* SEIDs need to either both be set or both be 0 for floating VEB */
1009 if (!!uplink_seid != !!downlink_seid)
1010 return I40E_ERR_PARAM;
1011
1012 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1013
1014 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1015 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1016 cmd->enable_tcs = enabled_tc;
1017 if (!uplink_seid)
1018 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1019 if (default_port)
1020 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1021 else
1022 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
1023
1024 if (enable_l2_filtering)
1025 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1026
1027 cmd->veb_flags = cpu_to_le16(veb_flags);
1028
1029 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1030
1031 if (!status && veb_seid)
1032 *veb_seid = le16_to_cpu(resp->veb_seid);
1033
1034 return status;
1035 }
1036
1037 /**
1038 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1039 * @hw: pointer to the hw struct
1040 * @veb_seid: the SEID of the VEB to query
1041 * @switch_id: the uplink switch id
1042 * @floating_veb: set to true if the VEB is floating
1043 * @statistic_index: index of the stats counter block for this VEB
1044 * @vebs_used: number of VEB's used by function
1045 * @vebs_unallocated: total VEB's not reserved by any function
1046 * @cmd_details: pointer to command details structure or NULL
1047 *
1048 * This retrieves the parameters for a particular VEB, specified by
1049 * uplink_seid, and returns them to the caller.
1050 **/
1051 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1052 u16 veb_seid, u16 *switch_id,
1053 bool *floating, u16 *statistic_index,
1054 u16 *vebs_used, u16 *vebs_free,
1055 struct i40e_asq_cmd_details *cmd_details)
1056 {
1057 struct i40e_aq_desc desc;
1058 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1059 (struct i40e_aqc_get_veb_parameters_completion *)
1060 &desc.params.raw;
1061 i40e_status status;
1062
1063 if (veb_seid == 0)
1064 return I40E_ERR_PARAM;
1065
1066 i40e_fill_default_direct_cmd_desc(&desc,
1067 i40e_aqc_opc_get_veb_parameters);
1068 cmd_resp->seid = cpu_to_le16(veb_seid);
1069
1070 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1071 if (status)
1072 goto get_veb_exit;
1073
1074 if (switch_id)
1075 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1076 if (statistic_index)
1077 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1078 if (vebs_used)
1079 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1080 if (vebs_free)
1081 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1082 if (floating) {
1083 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1084 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1085 *floating = true;
1086 else
1087 *floating = false;
1088 }
1089
1090 get_veb_exit:
1091 return status;
1092 }
1093
1094 /**
1095 * i40e_aq_add_macvlan
1096 * @hw: pointer to the hw struct
1097 * @seid: VSI for the mac address
1098 * @mv_list: list of macvlans to be added
1099 * @count: length of the list
1100 * @cmd_details: pointer to command details structure or NULL
1101 *
1102 * Add MAC/VLAN addresses to the HW filtering
1103 **/
1104 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1105 struct i40e_aqc_add_macvlan_element_data *mv_list,
1106 u16 count, struct i40e_asq_cmd_details *cmd_details)
1107 {
1108 struct i40e_aq_desc desc;
1109 struct i40e_aqc_macvlan *cmd =
1110 (struct i40e_aqc_macvlan *)&desc.params.raw;
1111 i40e_status status;
1112 u16 buf_size;
1113
1114 if (count == 0 || !mv_list || !hw)
1115 return I40E_ERR_PARAM;
1116
1117 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
1118
1119 /* prep the rest of the request */
1120 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
1121 cmd->num_addresses = cpu_to_le16(count);
1122 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1123 cmd->seid[1] = 0;
1124 cmd->seid[2] = 0;
1125
1126 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1127 if (buf_size > I40E_AQ_LARGE_BUF)
1128 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1129
1130 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1131 cmd_details);
1132
1133 return status;
1134 }
1135
1136 /**
1137 * i40e_aq_remove_macvlan
1138 * @hw: pointer to the hw struct
1139 * @seid: VSI for the mac address
1140 * @mv_list: list of macvlans to be removed
1141 * @count: length of the list
1142 * @cmd_details: pointer to command details structure or NULL
1143 *
1144 * Remove MAC/VLAN addresses from the HW filtering
1145 **/
1146 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
1147 struct i40e_aqc_remove_macvlan_element_data *mv_list,
1148 u16 count, struct i40e_asq_cmd_details *cmd_details)
1149 {
1150 struct i40e_aq_desc desc;
1151 struct i40e_aqc_macvlan *cmd =
1152 (struct i40e_aqc_macvlan *)&desc.params.raw;
1153 i40e_status status;
1154 u16 buf_size;
1155
1156 if (count == 0 || !mv_list || !hw)
1157 return I40E_ERR_PARAM;
1158
1159 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
1160
1161 /* prep the rest of the request */
1162 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
1163 cmd->num_addresses = cpu_to_le16(count);
1164 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1165 cmd->seid[1] = 0;
1166 cmd->seid[2] = 0;
1167
1168 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1169 if (buf_size > I40E_AQ_LARGE_BUF)
1170 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1171
1172 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1173 cmd_details);
1174
1175 return status;
1176 }
1177
1178 /**
1179 * i40e_aq_send_msg_to_vf
1180 * @hw: pointer to the hardware structure
1181 * @vfid: vf id to send msg
1182 * @msg: pointer to the msg buffer
1183 * @msglen: msg length
1184 * @cmd_details: pointer to command details
1185 *
1186 * send msg to vf
1187 **/
1188 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
1189 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
1190 struct i40e_asq_cmd_details *cmd_details)
1191 {
1192 struct i40e_aq_desc desc;
1193 struct i40e_aqc_pf_vf_message *cmd =
1194 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
1195 i40e_status status;
1196
1197 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
1198 cmd->id = cpu_to_le32(vfid);
1199 desc.cookie_high = cpu_to_le32(v_opcode);
1200 desc.cookie_low = cpu_to_le32(v_retval);
1201 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
1202 if (msglen) {
1203 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
1204 I40E_AQ_FLAG_RD));
1205 if (msglen > I40E_AQ_LARGE_BUF)
1206 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1207 desc.datalen = cpu_to_le16(msglen);
1208 }
1209 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
1210
1211 return status;
1212 }
1213
1214 /**
1215 * i40e_aq_set_hmc_resource_profile
1216 * @hw: pointer to the hw struct
1217 * @profile: type of profile the HMC is to be set as
1218 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
1219 * @cmd_details: pointer to command details structure or NULL
1220 *
1221 * set the HMC profile of the device.
1222 **/
1223 i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
1224 enum i40e_aq_hmc_profile profile,
1225 u8 pe_vf_enabled_count,
1226 struct i40e_asq_cmd_details *cmd_details)
1227 {
1228 struct i40e_aq_desc desc;
1229 struct i40e_aq_get_set_hmc_resource_profile *cmd =
1230 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
1231 i40e_status status;
1232
1233 i40e_fill_default_direct_cmd_desc(&desc,
1234 i40e_aqc_opc_set_hmc_resource_profile);
1235
1236 cmd->pm_profile = (u8)profile;
1237 cmd->pe_vf_enabled = pe_vf_enabled_count;
1238
1239 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1240
1241 return status;
1242 }
1243
1244 /**
1245 * i40e_aq_request_resource
1246 * @hw: pointer to the hw struct
1247 * @resource: resource id
1248 * @access: access type
1249 * @sdp_number: resource number
1250 * @timeout: the maximum time in ms that the driver may hold the resource
1251 * @cmd_details: pointer to command details structure or NULL
1252 *
1253 * requests common resource using the admin queue commands
1254 **/
1255 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
1256 enum i40e_aq_resources_ids resource,
1257 enum i40e_aq_resource_access_type access,
1258 u8 sdp_number, u64 *timeout,
1259 struct i40e_asq_cmd_details *cmd_details)
1260 {
1261 struct i40e_aq_desc desc;
1262 struct i40e_aqc_request_resource *cmd_resp =
1263 (struct i40e_aqc_request_resource *)&desc.params.raw;
1264 i40e_status status;
1265
1266 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
1267
1268 cmd_resp->resource_id = cpu_to_le16(resource);
1269 cmd_resp->access_type = cpu_to_le16(access);
1270 cmd_resp->resource_number = cpu_to_le32(sdp_number);
1271
1272 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1273 /* The completion specifies the maximum time in ms that the driver
1274 * may hold the resource in the Timeout field.
1275 * If the resource is held by someone else, the command completes with
1276 * busy return value and the timeout field indicates the maximum time
1277 * the current owner of the resource has to free it.
1278 */
1279 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
1280 *timeout = le32_to_cpu(cmd_resp->timeout);
1281
1282 return status;
1283 }
1284
1285 /**
1286 * i40e_aq_release_resource
1287 * @hw: pointer to the hw struct
1288 * @resource: resource id
1289 * @sdp_number: resource number
1290 * @cmd_details: pointer to command details structure or NULL
1291 *
1292 * release common resource using the admin queue commands
1293 **/
1294 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
1295 enum i40e_aq_resources_ids resource,
1296 u8 sdp_number,
1297 struct i40e_asq_cmd_details *cmd_details)
1298 {
1299 struct i40e_aq_desc desc;
1300 struct i40e_aqc_request_resource *cmd =
1301 (struct i40e_aqc_request_resource *)&desc.params.raw;
1302 i40e_status status;
1303
1304 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
1305
1306 cmd->resource_id = cpu_to_le16(resource);
1307 cmd->resource_number = cpu_to_le32(sdp_number);
1308
1309 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1310
1311 return status;
1312 }
1313
1314 /**
1315 * i40e_aq_read_nvm
1316 * @hw: pointer to the hw struct
1317 * @module_pointer: module pointer location in words from the NVM beginning
1318 * @offset: byte offset from the module beginning
1319 * @length: length of the section to be read (in bytes from the offset)
1320 * @data: command buffer (size [bytes] = length)
1321 * @last_command: tells if this is the last command in a series
1322 * @cmd_details: pointer to command details structure or NULL
1323 *
1324 * Read the NVM using the admin queue commands
1325 **/
1326 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
1327 u32 offset, u16 length, void *data,
1328 bool last_command,
1329 struct i40e_asq_cmd_details *cmd_details)
1330 {
1331 struct i40e_aq_desc desc;
1332 struct i40e_aqc_nvm_update *cmd =
1333 (struct i40e_aqc_nvm_update *)&desc.params.raw;
1334 i40e_status status;
1335
1336 /* In offset the highest byte must be zeroed. */
1337 if (offset & 0xFF000000) {
1338 status = I40E_ERR_PARAM;
1339 goto i40e_aq_read_nvm_exit;
1340 }
1341
1342 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
1343
1344 /* If this is the last command in a series, set the proper flag. */
1345 if (last_command)
1346 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
1347 cmd->module_pointer = module_pointer;
1348 cmd->offset = cpu_to_le32(offset);
1349 cmd->length = cpu_to_le16(length);
1350
1351 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1352 if (length > I40E_AQ_LARGE_BUF)
1353 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1354
1355 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
1356
1357 i40e_aq_read_nvm_exit:
1358 return status;
1359 }
1360
1361 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
1362 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
1363 #define I40E_DEV_FUNC_CAP_NPAR 0x03
1364 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
1365 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
1366 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
1367 #define I40E_DEV_FUNC_CAP_VF 0x13
1368 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
1369 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
1370 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
1371 #define I40E_DEV_FUNC_CAP_VSI 0x17
1372 #define I40E_DEV_FUNC_CAP_DCB 0x18
1373 #define I40E_DEV_FUNC_CAP_FCOE 0x21
1374 #define I40E_DEV_FUNC_CAP_RSS 0x40
1375 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
1376 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
1377 #define I40E_DEV_FUNC_CAP_MSIX 0x43
1378 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
1379 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
1380 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
1381 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
1382 #define I40E_DEV_FUNC_CAP_CEM 0xF2
1383 #define I40E_DEV_FUNC_CAP_IWARP 0x51
1384 #define I40E_DEV_FUNC_CAP_LED 0x61
1385 #define I40E_DEV_FUNC_CAP_SDP 0x62
1386 #define I40E_DEV_FUNC_CAP_MDIO 0x63
1387
1388 /**
1389 * i40e_parse_discover_capabilities
1390 * @hw: pointer to the hw struct
1391 * @buff: pointer to a buffer containing device/function capability records
1392 * @cap_count: number of capability records in the list
1393 * @list_type_opc: type of capabilities list to parse
1394 *
1395 * Parse the device/function capabilities list.
1396 **/
1397 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
1398 u32 cap_count,
1399 enum i40e_admin_queue_opc list_type_opc)
1400 {
1401 struct i40e_aqc_list_capabilities_element_resp *cap;
1402 u32 number, logical_id, phys_id;
1403 struct i40e_hw_capabilities *p;
1404 u32 reg_val;
1405 u32 i = 0;
1406 u16 id;
1407
1408 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
1409
1410 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
1411 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
1412 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
1413 p = (struct i40e_hw_capabilities *)&hw->func_caps;
1414 else
1415 return;
1416
1417 for (i = 0; i < cap_count; i++, cap++) {
1418 id = le16_to_cpu(cap->id);
1419 number = le32_to_cpu(cap->number);
1420 logical_id = le32_to_cpu(cap->logical_id);
1421 phys_id = le32_to_cpu(cap->phys_id);
1422
1423 switch (id) {
1424 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
1425 p->switch_mode = number;
1426 break;
1427 case I40E_DEV_FUNC_CAP_MGMT_MODE:
1428 p->management_mode = number;
1429 break;
1430 case I40E_DEV_FUNC_CAP_NPAR:
1431 p->npar_enable = number;
1432 break;
1433 case I40E_DEV_FUNC_CAP_OS2BMC:
1434 p->os2bmc = number;
1435 break;
1436 case I40E_DEV_FUNC_CAP_VALID_FUNC:
1437 p->valid_functions = number;
1438 break;
1439 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
1440 if (number == 1)
1441 p->sr_iov_1_1 = true;
1442 break;
1443 case I40E_DEV_FUNC_CAP_VF:
1444 p->num_vfs = number;
1445 p->vf_base_id = logical_id;
1446 break;
1447 case I40E_DEV_FUNC_CAP_VMDQ:
1448 if (number == 1)
1449 p->vmdq = true;
1450 break;
1451 case I40E_DEV_FUNC_CAP_802_1_QBG:
1452 if (number == 1)
1453 p->evb_802_1_qbg = true;
1454 break;
1455 case I40E_DEV_FUNC_CAP_802_1_QBH:
1456 if (number == 1)
1457 p->evb_802_1_qbh = true;
1458 break;
1459 case I40E_DEV_FUNC_CAP_VSI:
1460 p->num_vsis = number;
1461 break;
1462 case I40E_DEV_FUNC_CAP_DCB:
1463 if (number == 1) {
1464 p->dcb = true;
1465 p->enabled_tcmap = logical_id;
1466 p->maxtc = phys_id;
1467 }
1468 break;
1469 case I40E_DEV_FUNC_CAP_FCOE:
1470 if (number == 1)
1471 p->fcoe = true;
1472 break;
1473 case I40E_DEV_FUNC_CAP_RSS:
1474 p->rss = true;
1475 reg_val = rd32(hw, I40E_PFQF_CTL_0);
1476 if (reg_val & I40E_PFQF_CTL_0_HASHLUTSIZE_MASK)
1477 p->rss_table_size = number;
1478 else
1479 p->rss_table_size = 128;
1480 p->rss_table_entry_width = logical_id;
1481 break;
1482 case I40E_DEV_FUNC_CAP_RX_QUEUES:
1483 p->num_rx_qp = number;
1484 p->base_queue = phys_id;
1485 break;
1486 case I40E_DEV_FUNC_CAP_TX_QUEUES:
1487 p->num_tx_qp = number;
1488 p->base_queue = phys_id;
1489 break;
1490 case I40E_DEV_FUNC_CAP_MSIX:
1491 p->num_msix_vectors = number;
1492 break;
1493 case I40E_DEV_FUNC_CAP_MSIX_VF:
1494 p->num_msix_vectors_vf = number;
1495 break;
1496 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
1497 if (number == 1)
1498 p->mfp_mode_1 = true;
1499 break;
1500 case I40E_DEV_FUNC_CAP_CEM:
1501 if (number == 1)
1502 p->mgmt_cem = true;
1503 break;
1504 case I40E_DEV_FUNC_CAP_IWARP:
1505 if (number == 1)
1506 p->iwarp = true;
1507 break;
1508 case I40E_DEV_FUNC_CAP_LED:
1509 if (phys_id < I40E_HW_CAP_MAX_GPIO)
1510 p->led[phys_id] = true;
1511 break;
1512 case I40E_DEV_FUNC_CAP_SDP:
1513 if (phys_id < I40E_HW_CAP_MAX_GPIO)
1514 p->sdp[phys_id] = true;
1515 break;
1516 case I40E_DEV_FUNC_CAP_MDIO:
1517 if (number == 1) {
1518 p->mdio_port_num = phys_id;
1519 p->mdio_port_mode = logical_id;
1520 }
1521 break;
1522 case I40E_DEV_FUNC_CAP_IEEE_1588:
1523 if (number == 1)
1524 p->ieee_1588 = true;
1525 break;
1526 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
1527 p->fd = true;
1528 p->fd_filters_guaranteed = number;
1529 p->fd_filters_best_effort = logical_id;
1530 break;
1531 default:
1532 break;
1533 }
1534 }
1535
1536 /* additional HW specific goodies that might
1537 * someday be HW version specific
1538 */
1539 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
1540 }
1541
1542 /**
1543 * i40e_aq_discover_capabilities
1544 * @hw: pointer to the hw struct
1545 * @buff: a virtual buffer to hold the capabilities
1546 * @buff_size: Size of the virtual buffer
1547 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
1548 * @list_type_opc: capabilities type to discover - pass in the command opcode
1549 * @cmd_details: pointer to command details structure or NULL
1550 *
1551 * Get the device capabilities descriptions from the firmware
1552 **/
1553 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
1554 void *buff, u16 buff_size, u16 *data_size,
1555 enum i40e_admin_queue_opc list_type_opc,
1556 struct i40e_asq_cmd_details *cmd_details)
1557 {
1558 struct i40e_aqc_list_capabilites *cmd;
1559 i40e_status status = 0;
1560 struct i40e_aq_desc desc;
1561
1562 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
1563
1564 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
1565 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
1566 status = I40E_ERR_PARAM;
1567 goto exit;
1568 }
1569
1570 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
1571
1572 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1573 if (buff_size > I40E_AQ_LARGE_BUF)
1574 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1575
1576 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1577 *data_size = le16_to_cpu(desc.datalen);
1578
1579 if (status)
1580 goto exit;
1581
1582 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
1583 list_type_opc);
1584
1585 exit:
1586 return status;
1587 }
1588
1589 /**
1590 * i40e_aq_get_lldp_mib
1591 * @hw: pointer to the hw struct
1592 * @bridge_type: type of bridge requested
1593 * @mib_type: Local, Remote or both Local and Remote MIBs
1594 * @buff: pointer to a user supplied buffer to store the MIB block
1595 * @buff_size: size of the buffer (in bytes)
1596 * @local_len : length of the returned Local LLDP MIB
1597 * @remote_len: length of the returned Remote LLDP MIB
1598 * @cmd_details: pointer to command details structure or NULL
1599 *
1600 * Requests the complete LLDP MIB (entire packet).
1601 **/
1602 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
1603 u8 mib_type, void *buff, u16 buff_size,
1604 u16 *local_len, u16 *remote_len,
1605 struct i40e_asq_cmd_details *cmd_details)
1606 {
1607 struct i40e_aq_desc desc;
1608 struct i40e_aqc_lldp_get_mib *cmd =
1609 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
1610 struct i40e_aqc_lldp_get_mib *resp =
1611 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
1612 i40e_status status;
1613
1614 if (buff_size == 0 || !buff)
1615 return I40E_ERR_PARAM;
1616
1617 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
1618 /* Indirect Command */
1619 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1620
1621 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
1622 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
1623 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
1624
1625 desc.datalen = cpu_to_le16(buff_size);
1626
1627 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1628 if (buff_size > I40E_AQ_LARGE_BUF)
1629 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1630
1631 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1632 if (!status) {
1633 if (local_len != NULL)
1634 *local_len = le16_to_cpu(resp->local_len);
1635 if (remote_len != NULL)
1636 *remote_len = le16_to_cpu(resp->remote_len);
1637 }
1638
1639 return status;
1640 }
1641
1642 /**
1643 * i40e_aq_cfg_lldp_mib_change_event
1644 * @hw: pointer to the hw struct
1645 * @enable_update: Enable or Disable event posting
1646 * @cmd_details: pointer to command details structure or NULL
1647 *
1648 * Enable or Disable posting of an event on ARQ when LLDP MIB
1649 * associated with the interface changes
1650 **/
1651 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
1652 bool enable_update,
1653 struct i40e_asq_cmd_details *cmd_details)
1654 {
1655 struct i40e_aq_desc desc;
1656 struct i40e_aqc_lldp_update_mib *cmd =
1657 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
1658 i40e_status status;
1659
1660 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
1661
1662 if (!enable_update)
1663 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
1664
1665 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1666
1667 return status;
1668 }
1669
1670 /**
1671 * i40e_aq_stop_lldp
1672 * @hw: pointer to the hw struct
1673 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
1674 * @cmd_details: pointer to command details structure or NULL
1675 *
1676 * Stop or Shutdown the embedded LLDP Agent
1677 **/
1678 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
1679 struct i40e_asq_cmd_details *cmd_details)
1680 {
1681 struct i40e_aq_desc desc;
1682 struct i40e_aqc_lldp_stop *cmd =
1683 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
1684 i40e_status status;
1685
1686 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
1687
1688 if (shutdown_agent)
1689 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
1690
1691 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1692
1693 return status;
1694 }
1695
1696 /**
1697 * i40e_aq_start_lldp
1698 * @hw: pointer to the hw struct
1699 * @cmd_details: pointer to command details structure or NULL
1700 *
1701 * Start the embedded LLDP Agent on all ports.
1702 **/
1703 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
1704 struct i40e_asq_cmd_details *cmd_details)
1705 {
1706 struct i40e_aq_desc desc;
1707 struct i40e_aqc_lldp_start *cmd =
1708 (struct i40e_aqc_lldp_start *)&desc.params.raw;
1709 i40e_status status;
1710
1711 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
1712
1713 cmd->command = I40E_AQ_LLDP_AGENT_START;
1714
1715 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1716
1717 return status;
1718 }
1719
1720 /**
1721 * i40e_aq_add_udp_tunnel
1722 * @hw: pointer to the hw struct
1723 * @udp_port: the UDP port to add
1724 * @header_len: length of the tunneling header length in DWords
1725 * @protocol_index: protocol index type
1726 * @cmd_details: pointer to command details structure or NULL
1727 **/
1728 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
1729 u16 udp_port, u8 header_len,
1730 u8 protocol_index, u8 *filter_index,
1731 struct i40e_asq_cmd_details *cmd_details)
1732 {
1733 struct i40e_aq_desc desc;
1734 struct i40e_aqc_add_udp_tunnel *cmd =
1735 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
1736 struct i40e_aqc_del_udp_tunnel_completion *resp =
1737 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
1738 i40e_status status;
1739
1740 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
1741
1742 cmd->udp_port = cpu_to_le16(udp_port);
1743 cmd->header_len = header_len;
1744 cmd->protocol_type = protocol_index;
1745
1746 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1747
1748 if (!status)
1749 *filter_index = resp->index;
1750
1751 return status;
1752 }
1753
1754 /**
1755 * i40e_aq_del_udp_tunnel
1756 * @hw: pointer to the hw struct
1757 * @index: filter index
1758 * @cmd_details: pointer to command details structure or NULL
1759 **/
1760 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
1761 struct i40e_asq_cmd_details *cmd_details)
1762 {
1763 struct i40e_aq_desc desc;
1764 struct i40e_aqc_remove_udp_tunnel *cmd =
1765 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
1766 i40e_status status;
1767
1768 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
1769
1770 cmd->index = index;
1771
1772 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1773
1774 return status;
1775 }
1776
1777 /**
1778 * i40e_aq_delete_element - Delete switch element
1779 * @hw: pointer to the hw struct
1780 * @seid: the SEID to delete from the switch
1781 * @cmd_details: pointer to command details structure or NULL
1782 *
1783 * This deletes a switch element from the switch.
1784 **/
1785 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
1786 struct i40e_asq_cmd_details *cmd_details)
1787 {
1788 struct i40e_aq_desc desc;
1789 struct i40e_aqc_switch_seid *cmd =
1790 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1791 i40e_status status;
1792
1793 if (seid == 0)
1794 return I40E_ERR_PARAM;
1795
1796 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
1797
1798 cmd->seid = cpu_to_le16(seid);
1799
1800 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1801
1802 return status;
1803 }
1804
1805 /**
1806 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
1807 * @hw: pointer to the hw struct
1808 * @seid: seid for the physical port/switching component/vsi
1809 * @buff: Indirect buffer to hold data parameters and response
1810 * @buff_size: Indirect buffer size
1811 * @opcode: Tx scheduler AQ command opcode
1812 * @cmd_details: pointer to command details structure or NULL
1813 *
1814 * Generic command handler for Tx scheduler AQ commands
1815 **/
1816 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
1817 void *buff, u16 buff_size,
1818 enum i40e_admin_queue_opc opcode,
1819 struct i40e_asq_cmd_details *cmd_details)
1820 {
1821 struct i40e_aq_desc desc;
1822 struct i40e_aqc_tx_sched_ind *cmd =
1823 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
1824 i40e_status status;
1825 bool cmd_param_flag = false;
1826
1827 switch (opcode) {
1828 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
1829 case i40e_aqc_opc_configure_vsi_tc_bw:
1830 case i40e_aqc_opc_enable_switching_comp_ets:
1831 case i40e_aqc_opc_modify_switching_comp_ets:
1832 case i40e_aqc_opc_disable_switching_comp_ets:
1833 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
1834 case i40e_aqc_opc_configure_switching_comp_bw_config:
1835 cmd_param_flag = true;
1836 break;
1837 case i40e_aqc_opc_query_vsi_bw_config:
1838 case i40e_aqc_opc_query_vsi_ets_sla_config:
1839 case i40e_aqc_opc_query_switching_comp_ets_config:
1840 case i40e_aqc_opc_query_port_ets_config:
1841 case i40e_aqc_opc_query_switching_comp_bw_config:
1842 cmd_param_flag = false;
1843 break;
1844 default:
1845 return I40E_ERR_PARAM;
1846 }
1847
1848 i40e_fill_default_direct_cmd_desc(&desc, opcode);
1849
1850 /* Indirect command */
1851 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1852 if (cmd_param_flag)
1853 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
1854 if (buff_size > I40E_AQ_LARGE_BUF)
1855 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1856
1857 desc.datalen = cpu_to_le16(buff_size);
1858
1859 cmd->vsi_seid = cpu_to_le16(seid);
1860
1861 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1862
1863 return status;
1864 }
1865
1866 /**
1867 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
1868 * @hw: pointer to the hw struct
1869 * @seid: VSI seid
1870 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
1871 * @cmd_details: pointer to command details structure or NULL
1872 **/
1873 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
1874 u16 seid,
1875 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
1876 struct i40e_asq_cmd_details *cmd_details)
1877 {
1878 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1879 i40e_aqc_opc_configure_vsi_tc_bw,
1880 cmd_details);
1881 }
1882
1883 /**
1884 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
1885 * @hw: pointer to the hw struct
1886 * @seid: seid of the VSI
1887 * @bw_data: Buffer to hold VSI BW configuration
1888 * @cmd_details: pointer to command details structure or NULL
1889 **/
1890 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
1891 u16 seid,
1892 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
1893 struct i40e_asq_cmd_details *cmd_details)
1894 {
1895 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1896 i40e_aqc_opc_query_vsi_bw_config,
1897 cmd_details);
1898 }
1899
1900 /**
1901 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
1902 * @hw: pointer to the hw struct
1903 * @seid: seid of the VSI
1904 * @bw_data: Buffer to hold VSI BW configuration per TC
1905 * @cmd_details: pointer to command details structure or NULL
1906 **/
1907 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
1908 u16 seid,
1909 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
1910 struct i40e_asq_cmd_details *cmd_details)
1911 {
1912 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1913 i40e_aqc_opc_query_vsi_ets_sla_config,
1914 cmd_details);
1915 }
1916
1917 /**
1918 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
1919 * @hw: pointer to the hw struct
1920 * @seid: seid of the switching component
1921 * @bw_data: Buffer to hold switching component's per TC BW config
1922 * @cmd_details: pointer to command details structure or NULL
1923 **/
1924 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
1925 u16 seid,
1926 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
1927 struct i40e_asq_cmd_details *cmd_details)
1928 {
1929 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1930 i40e_aqc_opc_query_switching_comp_ets_config,
1931 cmd_details);
1932 }
1933
1934 /**
1935 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
1936 * @hw: pointer to the hw struct
1937 * @seid: seid of the VSI or switching component connected to Physical Port
1938 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
1939 * @cmd_details: pointer to command details structure or NULL
1940 **/
1941 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
1942 u16 seid,
1943 struct i40e_aqc_query_port_ets_config_resp *bw_data,
1944 struct i40e_asq_cmd_details *cmd_details)
1945 {
1946 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1947 i40e_aqc_opc_query_port_ets_config,
1948 cmd_details);
1949 }
1950
1951 /**
1952 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
1953 * @hw: pointer to the hw struct
1954 * @seid: seid of the switching component
1955 * @bw_data: Buffer to hold switching component's BW configuration
1956 * @cmd_details: pointer to command details structure or NULL
1957 **/
1958 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
1959 u16 seid,
1960 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
1961 struct i40e_asq_cmd_details *cmd_details)
1962 {
1963 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1964 i40e_aqc_opc_query_switching_comp_bw_config,
1965 cmd_details);
1966 }
1967
1968 /**
1969 * i40e_validate_filter_settings
1970 * @hw: pointer to the hardware structure
1971 * @settings: Filter control settings
1972 *
1973 * Check and validate the filter control settings passed.
1974 * The function checks for the valid filter/context sizes being
1975 * passed for FCoE and PE.
1976 *
1977 * Returns 0 if the values passed are valid and within
1978 * range else returns an error.
1979 **/
1980 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
1981 struct i40e_filter_control_settings *settings)
1982 {
1983 u32 fcoe_cntx_size, fcoe_filt_size;
1984 u32 pe_cntx_size, pe_filt_size;
1985 u32 fcoe_fmax, pe_fmax;
1986 u32 val;
1987
1988 /* Validate FCoE settings passed */
1989 switch (settings->fcoe_filt_num) {
1990 case I40E_HASH_FILTER_SIZE_1K:
1991 case I40E_HASH_FILTER_SIZE_2K:
1992 case I40E_HASH_FILTER_SIZE_4K:
1993 case I40E_HASH_FILTER_SIZE_8K:
1994 case I40E_HASH_FILTER_SIZE_16K:
1995 case I40E_HASH_FILTER_SIZE_32K:
1996 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
1997 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
1998 break;
1999 default:
2000 return I40E_ERR_PARAM;
2001 }
2002
2003 switch (settings->fcoe_cntx_num) {
2004 case I40E_DMA_CNTX_SIZE_512:
2005 case I40E_DMA_CNTX_SIZE_1K:
2006 case I40E_DMA_CNTX_SIZE_2K:
2007 case I40E_DMA_CNTX_SIZE_4K:
2008 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2009 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
2010 break;
2011 default:
2012 return I40E_ERR_PARAM;
2013 }
2014
2015 /* Validate PE settings passed */
2016 switch (settings->pe_filt_num) {
2017 case I40E_HASH_FILTER_SIZE_1K:
2018 case I40E_HASH_FILTER_SIZE_2K:
2019 case I40E_HASH_FILTER_SIZE_4K:
2020 case I40E_HASH_FILTER_SIZE_8K:
2021 case I40E_HASH_FILTER_SIZE_16K:
2022 case I40E_HASH_FILTER_SIZE_32K:
2023 case I40E_HASH_FILTER_SIZE_64K:
2024 case I40E_HASH_FILTER_SIZE_128K:
2025 case I40E_HASH_FILTER_SIZE_256K:
2026 case I40E_HASH_FILTER_SIZE_512K:
2027 case I40E_HASH_FILTER_SIZE_1M:
2028 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2029 pe_filt_size <<= (u32)settings->pe_filt_num;
2030 break;
2031 default:
2032 return I40E_ERR_PARAM;
2033 }
2034
2035 switch (settings->pe_cntx_num) {
2036 case I40E_DMA_CNTX_SIZE_512:
2037 case I40E_DMA_CNTX_SIZE_1K:
2038 case I40E_DMA_CNTX_SIZE_2K:
2039 case I40E_DMA_CNTX_SIZE_4K:
2040 case I40E_DMA_CNTX_SIZE_8K:
2041 case I40E_DMA_CNTX_SIZE_16K:
2042 case I40E_DMA_CNTX_SIZE_32K:
2043 case I40E_DMA_CNTX_SIZE_64K:
2044 case I40E_DMA_CNTX_SIZE_128K:
2045 case I40E_DMA_CNTX_SIZE_256K:
2046 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2047 pe_cntx_size <<= (u32)settings->pe_cntx_num;
2048 break;
2049 default:
2050 return I40E_ERR_PARAM;
2051 }
2052
2053 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
2054 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
2055 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
2056 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
2057 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
2058 return I40E_ERR_INVALID_SIZE;
2059
2060 /* PEHSIZE + PEDSIZE should not be greater than PMPEXFMAX */
2061 val = rd32(hw, I40E_GLHMC_PEXFMAX);
2062 pe_fmax = (val & I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK)
2063 >> I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT;
2064 if (pe_filt_size + pe_cntx_size > pe_fmax)
2065 return I40E_ERR_INVALID_SIZE;
2066
2067 return 0;
2068 }
2069
2070 /**
2071 * i40e_set_filter_control
2072 * @hw: pointer to the hardware structure
2073 * @settings: Filter control settings
2074 *
2075 * Set the Queue Filters for PE/FCoE and enable filters required
2076 * for a single PF. It is expected that these settings are programmed
2077 * at the driver initialization time.
2078 **/
2079 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
2080 struct i40e_filter_control_settings *settings)
2081 {
2082 i40e_status ret = 0;
2083 u32 hash_lut_size = 0;
2084 u32 val;
2085
2086 if (!settings)
2087 return I40E_ERR_PARAM;
2088
2089 /* Validate the input settings */
2090 ret = i40e_validate_filter_settings(hw, settings);
2091 if (ret)
2092 return ret;
2093
2094 /* Read the PF Queue Filter control register */
2095 val = rd32(hw, I40E_PFQF_CTL_0);
2096
2097 /* Program required PE hash buckets for the PF */
2098 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
2099 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
2100 I40E_PFQF_CTL_0_PEHSIZE_MASK;
2101 /* Program required PE contexts for the PF */
2102 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
2103 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
2104 I40E_PFQF_CTL_0_PEDSIZE_MASK;
2105
2106 /* Program required FCoE hash buckets for the PF */
2107 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2108 val |= ((u32)settings->fcoe_filt_num <<
2109 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
2110 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2111 /* Program required FCoE DDP contexts for the PF */
2112 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2113 val |= ((u32)settings->fcoe_cntx_num <<
2114 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
2115 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2116
2117 /* Program Hash LUT size for the PF */
2118 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2119 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
2120 hash_lut_size = 1;
2121 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
2122 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2123
2124 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
2125 if (settings->enable_fdir)
2126 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
2127 if (settings->enable_ethtype)
2128 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
2129 if (settings->enable_macvlan)
2130 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
2131
2132 wr32(hw, I40E_PFQF_CTL_0, val);
2133
2134 return 0;
2135 }
2136 /**
2137 * i40e_set_pci_config_data - store PCI bus info
2138 * @hw: pointer to hardware structure
2139 * @link_status: the link status word from PCI config space
2140 *
2141 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
2142 **/
2143 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
2144 {
2145 hw->bus.type = i40e_bus_type_pci_express;
2146
2147 switch (link_status & PCI_EXP_LNKSTA_NLW) {
2148 case PCI_EXP_LNKSTA_NLW_X1:
2149 hw->bus.width = i40e_bus_width_pcie_x1;
2150 break;
2151 case PCI_EXP_LNKSTA_NLW_X2:
2152 hw->bus.width = i40e_bus_width_pcie_x2;
2153 break;
2154 case PCI_EXP_LNKSTA_NLW_X4:
2155 hw->bus.width = i40e_bus_width_pcie_x4;
2156 break;
2157 case PCI_EXP_LNKSTA_NLW_X8:
2158 hw->bus.width = i40e_bus_width_pcie_x8;
2159 break;
2160 default:
2161 hw->bus.width = i40e_bus_width_unknown;
2162 break;
2163 }
2164
2165 switch (link_status & PCI_EXP_LNKSTA_CLS) {
2166 case PCI_EXP_LNKSTA_CLS_2_5GB:
2167 hw->bus.speed = i40e_bus_speed_2500;
2168 break;
2169 case PCI_EXP_LNKSTA_CLS_5_0GB:
2170 hw->bus.speed = i40e_bus_speed_5000;
2171 break;
2172 case PCI_EXP_LNKSTA_CLS_8_0GB:
2173 hw->bus.speed = i40e_bus_speed_8000;
2174 break;
2175 default:
2176 hw->bus.speed = i40e_bus_speed_unknown;
2177 break;
2178 }
2179 }
Linux kernel - Deliverables
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