1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
39 static i40e_status
i40e_set_mac_type(struct i40e_hw
*hw
)
41 i40e_status status
= 0;
43 if (hw
->vendor_id
== PCI_VENDOR_ID_INTEL
) {
44 switch (hw
->device_id
) {
45 case I40E_DEV_ID_SFP_XL710
:
46 case I40E_DEV_ID_QEMU
:
47 case I40E_DEV_ID_KX_A
:
48 case I40E_DEV_ID_KX_B
:
49 case I40E_DEV_ID_KX_C
:
50 case I40E_DEV_ID_QSFP_A
:
51 case I40E_DEV_ID_QSFP_B
:
52 case I40E_DEV_ID_QSFP_C
:
53 hw
->mac
.type
= I40E_MAC_XL710
;
56 case I40E_DEV_ID_VF_HV
:
57 hw
->mac
.type
= I40E_MAC_VF
;
60 hw
->mac
.type
= I40E_MAC_GENERIC
;
64 status
= I40E_ERR_DEVICE_NOT_SUPPORTED
;
67 hw_dbg(hw
, "i40e_set_mac_type found mac: %d, returns: %d\n",
68 hw
->mac
.type
, status
);
74 * @hw: debug mask related to admin queue
76 * @desc: pointer to admin queue descriptor
77 * @buffer: pointer to command buffer
79 * Dumps debug log about adminq command with descriptor contents.
81 void i40e_debug_aq(struct i40e_hw
*hw
, enum i40e_debug_mask mask
, void *desc
,
84 struct i40e_aq_desc
*aq_desc
= (struct i40e_aq_desc
*)desc
;
85 u8
*aq_buffer
= (u8
*)buffer
;
89 if ((!(mask
& hw
->debug_mask
)) || (desc
== NULL
))
93 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
94 aq_desc
->opcode
, aq_desc
->flags
, aq_desc
->datalen
,
96 i40e_debug(hw
, mask
, "\tcookie (h,l) 0x%08X 0x%08X\n",
97 aq_desc
->cookie_high
, aq_desc
->cookie_low
);
98 i40e_debug(hw
, mask
, "\tparam (0,1) 0x%08X 0x%08X\n",
99 aq_desc
->params
.internal
.param0
,
100 aq_desc
->params
.internal
.param1
);
101 i40e_debug(hw
, mask
, "\taddr (h,l) 0x%08X 0x%08X\n",
102 aq_desc
->params
.external
.addr_high
,
103 aq_desc
->params
.external
.addr_low
);
105 if ((buffer
!= NULL
) && (aq_desc
->datalen
!= 0)) {
106 memset(data
, 0, sizeof(data
));
107 i40e_debug(hw
, mask
, "AQ CMD Buffer:\n");
108 for (i
= 0; i
< le16_to_cpu(aq_desc
->datalen
); i
++) {
109 data
[((i
% 16) / 4)] |=
110 ((u32
)aq_buffer
[i
]) << (8 * (i
% 4));
111 if ((i
% 16) == 15) {
113 "\t0x%04X %08X %08X %08X %08X\n",
114 i
- 15, data
[0], data
[1], data
[2],
116 memset(data
, 0, sizeof(data
));
120 i40e_debug(hw
, mask
, "\t0x%04X %08X %08X %08X %08X\n",
121 i
- (i
% 16), data
[0], data
[1], data
[2],
127 * i40e_check_asq_alive
128 * @hw: pointer to the hw struct
130 * Returns true if Queue is enabled else false.
132 bool i40e_check_asq_alive(struct i40e_hw
*hw
)
135 return !!(rd32(hw
, hw
->aq
.asq
.len
) &
136 I40E_PF_ATQLEN_ATQENABLE_MASK
);
142 * i40e_aq_queue_shutdown
143 * @hw: pointer to the hw struct
144 * @unloading: is the driver unloading itself
146 * Tell the Firmware that we're shutting down the AdminQ and whether
147 * or not the driver is unloading as well.
149 i40e_status
i40e_aq_queue_shutdown(struct i40e_hw
*hw
,
152 struct i40e_aq_desc desc
;
153 struct i40e_aqc_queue_shutdown
*cmd
=
154 (struct i40e_aqc_queue_shutdown
*)&desc
.params
.raw
;
157 i40e_fill_default_direct_cmd_desc(&desc
,
158 i40e_aqc_opc_queue_shutdown
);
161 cmd
->driver_unloading
= cpu_to_le32(I40E_AQ_DRIVER_UNLOADING
);
162 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, NULL
);
167 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
168 * hardware to a bit-field that can be used by SW to more easily determine the
171 * Macros are used to shorten the table lines and make this table human
174 * We store the PTYPE in the top byte of the bit field - this is just so that
175 * we can check that the table doesn't have a row missing, as the index into
176 * the table should be the PTYPE.
180 * IF NOT i40e_ptype_lookup[ptype].known
183 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
184 * Use the rest of the fields to look at the tunnels, inner protocols, etc
186 * Use the enum i40e_rx_l2_ptype to decode the packet type
190 /* macro to make the table lines short */
191 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
194 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
195 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
196 I40E_RX_PTYPE_##OUTER_FRAG, \
197 I40E_RX_PTYPE_TUNNEL_##T, \
198 I40E_RX_PTYPE_TUNNEL_END_##TE, \
199 I40E_RX_PTYPE_##TEF, \
200 I40E_RX_PTYPE_INNER_PROT_##I, \
201 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
203 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
204 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
206 /* shorter macros makes the table fit but are terse */
207 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
208 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
209 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
211 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
212 struct i40e_rx_ptype_decoded i40e_ptype_lookup
[] = {
213 /* L2 Packet types */
214 I40E_PTT_UNUSED_ENTRY(0),
215 I40E_PTT(1, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
216 I40E_PTT(2, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, TS
, PAY2
),
217 I40E_PTT(3, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
218 I40E_PTT_UNUSED_ENTRY(4),
219 I40E_PTT_UNUSED_ENTRY(5),
220 I40E_PTT(6, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
221 I40E_PTT(7, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
222 I40E_PTT_UNUSED_ENTRY(8),
223 I40E_PTT_UNUSED_ENTRY(9),
224 I40E_PTT(10, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
225 I40E_PTT(11, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, NONE
),
226 I40E_PTT(12, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
227 I40E_PTT(13, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
228 I40E_PTT(14, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
229 I40E_PTT(15, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
230 I40E_PTT(16, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
231 I40E_PTT(17, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
232 I40E_PTT(18, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
233 I40E_PTT(19, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
234 I40E_PTT(20, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
235 I40E_PTT(21, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
237 /* Non Tunneled IPv4 */
238 I40E_PTT(22, IP
, IPV4
, FRG
, NONE
, NONE
, NOF
, NONE
, PAY3
),
239 I40E_PTT(23, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
240 I40E_PTT(24, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, UDP
, PAY4
),
241 I40E_PTT_UNUSED_ENTRY(25),
242 I40E_PTT(26, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, TCP
, PAY4
),
243 I40E_PTT(27, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, SCTP
, PAY4
),
244 I40E_PTT(28, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, ICMP
, PAY4
),
247 I40E_PTT(29, IP
, IPV4
, NOF
, IP_IP
, IPV4
, FRG
, NONE
, PAY3
),
248 I40E_PTT(30, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, NONE
, PAY3
),
249 I40E_PTT(31, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, UDP
, PAY4
),
250 I40E_PTT_UNUSED_ENTRY(32),
251 I40E_PTT(33, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, TCP
, PAY4
),
252 I40E_PTT(34, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, SCTP
, PAY4
),
253 I40E_PTT(35, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, ICMP
, PAY4
),
256 I40E_PTT(36, IP
, IPV4
, NOF
, IP_IP
, IPV6
, FRG
, NONE
, PAY3
),
257 I40E_PTT(37, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, NONE
, PAY3
),
258 I40E_PTT(38, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, UDP
, PAY4
),
259 I40E_PTT_UNUSED_ENTRY(39),
260 I40E_PTT(40, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, TCP
, PAY4
),
261 I40E_PTT(41, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, SCTP
, PAY4
),
262 I40E_PTT(42, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, ICMP
, PAY4
),
264 /* IPv4 --> GRE/NAT */
265 I40E_PTT(43, IP
, IPV4
, NOF
, IP_GRENAT
, NONE
, NOF
, NONE
, PAY3
),
267 /* IPv4 --> GRE/NAT --> IPv4 */
268 I40E_PTT(44, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, FRG
, NONE
, PAY3
),
269 I40E_PTT(45, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, NONE
, PAY3
),
270 I40E_PTT(46, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, UDP
, PAY4
),
271 I40E_PTT_UNUSED_ENTRY(47),
272 I40E_PTT(48, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, TCP
, PAY4
),
273 I40E_PTT(49, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, SCTP
, PAY4
),
274 I40E_PTT(50, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, ICMP
, PAY4
),
276 /* IPv4 --> GRE/NAT --> IPv6 */
277 I40E_PTT(51, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, FRG
, NONE
, PAY3
),
278 I40E_PTT(52, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, NONE
, PAY3
),
279 I40E_PTT(53, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, UDP
, PAY4
),
280 I40E_PTT_UNUSED_ENTRY(54),
281 I40E_PTT(55, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, TCP
, PAY4
),
282 I40E_PTT(56, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, SCTP
, PAY4
),
283 I40E_PTT(57, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, ICMP
, PAY4
),
285 /* IPv4 --> GRE/NAT --> MAC */
286 I40E_PTT(58, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, NONE
, NOF
, NONE
, PAY3
),
288 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
289 I40E_PTT(59, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, FRG
, NONE
, PAY3
),
290 I40E_PTT(60, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, NONE
, PAY3
),
291 I40E_PTT(61, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, UDP
, PAY4
),
292 I40E_PTT_UNUSED_ENTRY(62),
293 I40E_PTT(63, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, TCP
, PAY4
),
294 I40E_PTT(64, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, SCTP
, PAY4
),
295 I40E_PTT(65, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, ICMP
, PAY4
),
297 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
298 I40E_PTT(66, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, FRG
, NONE
, PAY3
),
299 I40E_PTT(67, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, NONE
, PAY3
),
300 I40E_PTT(68, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, UDP
, PAY4
),
301 I40E_PTT_UNUSED_ENTRY(69),
302 I40E_PTT(70, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, TCP
, PAY4
),
303 I40E_PTT(71, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, SCTP
, PAY4
),
304 I40E_PTT(72, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, ICMP
, PAY4
),
306 /* IPv4 --> GRE/NAT --> MAC/VLAN */
307 I40E_PTT(73, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, NONE
, NOF
, NONE
, PAY3
),
309 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
310 I40E_PTT(74, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, FRG
, NONE
, PAY3
),
311 I40E_PTT(75, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, NONE
, PAY3
),
312 I40E_PTT(76, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, UDP
, PAY4
),
313 I40E_PTT_UNUSED_ENTRY(77),
314 I40E_PTT(78, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, TCP
, PAY4
),
315 I40E_PTT(79, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, SCTP
, PAY4
),
316 I40E_PTT(80, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, ICMP
, PAY4
),
318 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
319 I40E_PTT(81, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, FRG
, NONE
, PAY3
),
320 I40E_PTT(82, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, NONE
, PAY3
),
321 I40E_PTT(83, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, UDP
, PAY4
),
322 I40E_PTT_UNUSED_ENTRY(84),
323 I40E_PTT(85, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, TCP
, PAY4
),
324 I40E_PTT(86, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, SCTP
, PAY4
),
325 I40E_PTT(87, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, ICMP
, PAY4
),
327 /* Non Tunneled IPv6 */
328 I40E_PTT(88, IP
, IPV6
, FRG
, NONE
, NONE
, NOF
, NONE
, PAY3
),
329 I40E_PTT(89, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
330 I40E_PTT(90, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, UDP
, PAY3
),
331 I40E_PTT_UNUSED_ENTRY(91),
332 I40E_PTT(92, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, TCP
, PAY4
),
333 I40E_PTT(93, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, SCTP
, PAY4
),
334 I40E_PTT(94, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, ICMP
, PAY4
),
337 I40E_PTT(95, IP
, IPV6
, NOF
, IP_IP
, IPV4
, FRG
, NONE
, PAY3
),
338 I40E_PTT(96, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, NONE
, PAY3
),
339 I40E_PTT(97, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, UDP
, PAY4
),
340 I40E_PTT_UNUSED_ENTRY(98),
341 I40E_PTT(99, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, TCP
, PAY4
),
342 I40E_PTT(100, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, SCTP
, PAY4
),
343 I40E_PTT(101, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, ICMP
, PAY4
),
346 I40E_PTT(102, IP
, IPV6
, NOF
, IP_IP
, IPV6
, FRG
, NONE
, PAY3
),
347 I40E_PTT(103, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, NONE
, PAY3
),
348 I40E_PTT(104, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, UDP
, PAY4
),
349 I40E_PTT_UNUSED_ENTRY(105),
350 I40E_PTT(106, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, TCP
, PAY4
),
351 I40E_PTT(107, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, SCTP
, PAY4
),
352 I40E_PTT(108, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, ICMP
, PAY4
),
354 /* IPv6 --> GRE/NAT */
355 I40E_PTT(109, IP
, IPV6
, NOF
, IP_GRENAT
, NONE
, NOF
, NONE
, PAY3
),
357 /* IPv6 --> GRE/NAT -> IPv4 */
358 I40E_PTT(110, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, FRG
, NONE
, PAY3
),
359 I40E_PTT(111, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, NONE
, PAY3
),
360 I40E_PTT(112, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, UDP
, PAY4
),
361 I40E_PTT_UNUSED_ENTRY(113),
362 I40E_PTT(114, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, TCP
, PAY4
),
363 I40E_PTT(115, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, SCTP
, PAY4
),
364 I40E_PTT(116, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, ICMP
, PAY4
),
366 /* IPv6 --> GRE/NAT -> IPv6 */
367 I40E_PTT(117, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, FRG
, NONE
, PAY3
),
368 I40E_PTT(118, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, NONE
, PAY3
),
369 I40E_PTT(119, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, UDP
, PAY4
),
370 I40E_PTT_UNUSED_ENTRY(120),
371 I40E_PTT(121, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, TCP
, PAY4
),
372 I40E_PTT(122, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, SCTP
, PAY4
),
373 I40E_PTT(123, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, ICMP
, PAY4
),
375 /* IPv6 --> GRE/NAT -> MAC */
376 I40E_PTT(124, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, NONE
, NOF
, NONE
, PAY3
),
378 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
379 I40E_PTT(125, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, FRG
, NONE
, PAY3
),
380 I40E_PTT(126, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, NONE
, PAY3
),
381 I40E_PTT(127, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, UDP
, PAY4
),
382 I40E_PTT_UNUSED_ENTRY(128),
383 I40E_PTT(129, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, TCP
, PAY4
),
384 I40E_PTT(130, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, SCTP
, PAY4
),
385 I40E_PTT(131, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, ICMP
, PAY4
),
387 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
388 I40E_PTT(132, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, FRG
, NONE
, PAY3
),
389 I40E_PTT(133, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, NONE
, PAY3
),
390 I40E_PTT(134, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, UDP
, PAY4
),
391 I40E_PTT_UNUSED_ENTRY(135),
392 I40E_PTT(136, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, TCP
, PAY4
),
393 I40E_PTT(137, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, SCTP
, PAY4
),
394 I40E_PTT(138, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, ICMP
, PAY4
),
396 /* IPv6 --> GRE/NAT -> MAC/VLAN */
397 I40E_PTT(139, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, NONE
, NOF
, NONE
, PAY3
),
399 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
400 I40E_PTT(140, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, FRG
, NONE
, PAY3
),
401 I40E_PTT(141, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, NONE
, PAY3
),
402 I40E_PTT(142, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, UDP
, PAY4
),
403 I40E_PTT_UNUSED_ENTRY(143),
404 I40E_PTT(144, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, TCP
, PAY4
),
405 I40E_PTT(145, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, SCTP
, PAY4
),
406 I40E_PTT(146, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, ICMP
, PAY4
),
408 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
409 I40E_PTT(147, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, FRG
, NONE
, PAY3
),
410 I40E_PTT(148, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, NONE
, PAY3
),
411 I40E_PTT(149, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, UDP
, PAY4
),
412 I40E_PTT_UNUSED_ENTRY(150),
413 I40E_PTT(151, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, TCP
, PAY4
),
414 I40E_PTT(152, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, SCTP
, PAY4
),
415 I40E_PTT(153, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, ICMP
, PAY4
),
418 I40E_PTT_UNUSED_ENTRY(154),
419 I40E_PTT_UNUSED_ENTRY(155),
420 I40E_PTT_UNUSED_ENTRY(156),
421 I40E_PTT_UNUSED_ENTRY(157),
422 I40E_PTT_UNUSED_ENTRY(158),
423 I40E_PTT_UNUSED_ENTRY(159),
425 I40E_PTT_UNUSED_ENTRY(160),
426 I40E_PTT_UNUSED_ENTRY(161),
427 I40E_PTT_UNUSED_ENTRY(162),
428 I40E_PTT_UNUSED_ENTRY(163),
429 I40E_PTT_UNUSED_ENTRY(164),
430 I40E_PTT_UNUSED_ENTRY(165),
431 I40E_PTT_UNUSED_ENTRY(166),
432 I40E_PTT_UNUSED_ENTRY(167),
433 I40E_PTT_UNUSED_ENTRY(168),
434 I40E_PTT_UNUSED_ENTRY(169),
436 I40E_PTT_UNUSED_ENTRY(170),
437 I40E_PTT_UNUSED_ENTRY(171),
438 I40E_PTT_UNUSED_ENTRY(172),
439 I40E_PTT_UNUSED_ENTRY(173),
440 I40E_PTT_UNUSED_ENTRY(174),
441 I40E_PTT_UNUSED_ENTRY(175),
442 I40E_PTT_UNUSED_ENTRY(176),
443 I40E_PTT_UNUSED_ENTRY(177),
444 I40E_PTT_UNUSED_ENTRY(178),
445 I40E_PTT_UNUSED_ENTRY(179),
447 I40E_PTT_UNUSED_ENTRY(180),
448 I40E_PTT_UNUSED_ENTRY(181),
449 I40E_PTT_UNUSED_ENTRY(182),
450 I40E_PTT_UNUSED_ENTRY(183),
451 I40E_PTT_UNUSED_ENTRY(184),
452 I40E_PTT_UNUSED_ENTRY(185),
453 I40E_PTT_UNUSED_ENTRY(186),
454 I40E_PTT_UNUSED_ENTRY(187),
455 I40E_PTT_UNUSED_ENTRY(188),
456 I40E_PTT_UNUSED_ENTRY(189),
458 I40E_PTT_UNUSED_ENTRY(190),
459 I40E_PTT_UNUSED_ENTRY(191),
460 I40E_PTT_UNUSED_ENTRY(192),
461 I40E_PTT_UNUSED_ENTRY(193),
462 I40E_PTT_UNUSED_ENTRY(194),
463 I40E_PTT_UNUSED_ENTRY(195),
464 I40E_PTT_UNUSED_ENTRY(196),
465 I40E_PTT_UNUSED_ENTRY(197),
466 I40E_PTT_UNUSED_ENTRY(198),
467 I40E_PTT_UNUSED_ENTRY(199),
469 I40E_PTT_UNUSED_ENTRY(200),
470 I40E_PTT_UNUSED_ENTRY(201),
471 I40E_PTT_UNUSED_ENTRY(202),
472 I40E_PTT_UNUSED_ENTRY(203),
473 I40E_PTT_UNUSED_ENTRY(204),
474 I40E_PTT_UNUSED_ENTRY(205),
475 I40E_PTT_UNUSED_ENTRY(206),
476 I40E_PTT_UNUSED_ENTRY(207),
477 I40E_PTT_UNUSED_ENTRY(208),
478 I40E_PTT_UNUSED_ENTRY(209),
480 I40E_PTT_UNUSED_ENTRY(210),
481 I40E_PTT_UNUSED_ENTRY(211),
482 I40E_PTT_UNUSED_ENTRY(212),
483 I40E_PTT_UNUSED_ENTRY(213),
484 I40E_PTT_UNUSED_ENTRY(214),
485 I40E_PTT_UNUSED_ENTRY(215),
486 I40E_PTT_UNUSED_ENTRY(216),
487 I40E_PTT_UNUSED_ENTRY(217),
488 I40E_PTT_UNUSED_ENTRY(218),
489 I40E_PTT_UNUSED_ENTRY(219),
491 I40E_PTT_UNUSED_ENTRY(220),
492 I40E_PTT_UNUSED_ENTRY(221),
493 I40E_PTT_UNUSED_ENTRY(222),
494 I40E_PTT_UNUSED_ENTRY(223),
495 I40E_PTT_UNUSED_ENTRY(224),
496 I40E_PTT_UNUSED_ENTRY(225),
497 I40E_PTT_UNUSED_ENTRY(226),
498 I40E_PTT_UNUSED_ENTRY(227),
499 I40E_PTT_UNUSED_ENTRY(228),
500 I40E_PTT_UNUSED_ENTRY(229),
502 I40E_PTT_UNUSED_ENTRY(230),
503 I40E_PTT_UNUSED_ENTRY(231),
504 I40E_PTT_UNUSED_ENTRY(232),
505 I40E_PTT_UNUSED_ENTRY(233),
506 I40E_PTT_UNUSED_ENTRY(234),
507 I40E_PTT_UNUSED_ENTRY(235),
508 I40E_PTT_UNUSED_ENTRY(236),
509 I40E_PTT_UNUSED_ENTRY(237),
510 I40E_PTT_UNUSED_ENTRY(238),
511 I40E_PTT_UNUSED_ENTRY(239),
513 I40E_PTT_UNUSED_ENTRY(240),
514 I40E_PTT_UNUSED_ENTRY(241),
515 I40E_PTT_UNUSED_ENTRY(242),
516 I40E_PTT_UNUSED_ENTRY(243),
517 I40E_PTT_UNUSED_ENTRY(244),
518 I40E_PTT_UNUSED_ENTRY(245),
519 I40E_PTT_UNUSED_ENTRY(246),
520 I40E_PTT_UNUSED_ENTRY(247),
521 I40E_PTT_UNUSED_ENTRY(248),
522 I40E_PTT_UNUSED_ENTRY(249),
524 I40E_PTT_UNUSED_ENTRY(250),
525 I40E_PTT_UNUSED_ENTRY(251),
526 I40E_PTT_UNUSED_ENTRY(252),
527 I40E_PTT_UNUSED_ENTRY(253),
528 I40E_PTT_UNUSED_ENTRY(254),
529 I40E_PTT_UNUSED_ENTRY(255)
534 * i40e_init_shared_code - Initialize the shared code
535 * @hw: pointer to hardware structure
537 * This assigns the MAC type and PHY code and inits the NVM.
538 * Does not touch the hardware. This function must be called prior to any
539 * other function in the shared code. The i40e_hw structure should be
540 * memset to 0 prior to calling this function. The following fields in
541 * hw structure should be filled in prior to calling this function:
542 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
543 * subsystem_vendor_id, and revision_id
545 i40e_status
i40e_init_shared_code(struct i40e_hw
*hw
)
547 i40e_status status
= 0;
550 i40e_set_mac_type(hw
);
552 switch (hw
->mac
.type
) {
556 return I40E_ERR_DEVICE_NOT_SUPPORTED
;
560 hw
->phy
.get_link_info
= true;
562 /* Determine port number */
563 reg
= rd32(hw
, I40E_PFGEN_PORTNUM
);
564 reg
= ((reg
& I40E_PFGEN_PORTNUM_PORT_NUM_MASK
) >>
565 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT
);
568 /* Determine the PF number based on the PCI fn */
569 reg
= rd32(hw
, I40E_GLPCI_CAPSUP
);
570 if (reg
& I40E_GLPCI_CAPSUP_ARI_EN_MASK
)
571 hw
->pf_id
= (u8
)((hw
->bus
.device
<< 3) | hw
->bus
.func
);
573 hw
->pf_id
= (u8
)hw
->bus
.func
;
575 status
= i40e_init_nvm(hw
);
580 * i40e_aq_mac_address_read - Retrieve the MAC addresses
581 * @hw: pointer to the hw struct
582 * @flags: a return indicator of what addresses were added to the addr store
583 * @addrs: the requestor's mac addr store
584 * @cmd_details: pointer to command details structure or NULL
586 static i40e_status
i40e_aq_mac_address_read(struct i40e_hw
*hw
,
588 struct i40e_aqc_mac_address_read_data
*addrs
,
589 struct i40e_asq_cmd_details
*cmd_details
)
591 struct i40e_aq_desc desc
;
592 struct i40e_aqc_mac_address_read
*cmd_data
=
593 (struct i40e_aqc_mac_address_read
*)&desc
.params
.raw
;
596 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_mac_address_read
);
597 desc
.flags
|= cpu_to_le16(I40E_AQ_FLAG_BUF
);
599 status
= i40e_asq_send_command(hw
, &desc
, addrs
,
600 sizeof(*addrs
), cmd_details
);
601 *flags
= le16_to_cpu(cmd_data
->command_flags
);
607 * i40e_aq_mac_address_write - Change the MAC addresses
608 * @hw: pointer to the hw struct
609 * @flags: indicates which MAC to be written
610 * @mac_addr: address to write
611 * @cmd_details: pointer to command details structure or NULL
613 i40e_status
i40e_aq_mac_address_write(struct i40e_hw
*hw
,
614 u16 flags
, u8
*mac_addr
,
615 struct i40e_asq_cmd_details
*cmd_details
)
617 struct i40e_aq_desc desc
;
618 struct i40e_aqc_mac_address_write
*cmd_data
=
619 (struct i40e_aqc_mac_address_write
*)&desc
.params
.raw
;
622 i40e_fill_default_direct_cmd_desc(&desc
,
623 i40e_aqc_opc_mac_address_write
);
624 cmd_data
->command_flags
= cpu_to_le16(flags
);
625 cmd_data
->mac_sah
= cpu_to_le16((u16
)mac_addr
[0] << 8 | mac_addr
[1]);
626 cmd_data
->mac_sal
= cpu_to_le32(((u32
)mac_addr
[2] << 24) |
627 ((u32
)mac_addr
[3] << 16) |
628 ((u32
)mac_addr
[4] << 8) |
631 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
637 * i40e_get_mac_addr - get MAC address
638 * @hw: pointer to the HW structure
639 * @mac_addr: pointer to MAC address
641 * Reads the adapter's MAC address from register
643 i40e_status
i40e_get_mac_addr(struct i40e_hw
*hw
, u8
*mac_addr
)
645 struct i40e_aqc_mac_address_read_data addrs
;
649 status
= i40e_aq_mac_address_read(hw
, &flags
, &addrs
, NULL
);
651 if (flags
& I40E_AQC_LAN_ADDR_VALID
)
652 memcpy(mac_addr
, &addrs
.pf_lan_mac
, sizeof(addrs
.pf_lan_mac
));
658 * i40e_pre_tx_queue_cfg - pre tx queue configure
659 * @hw: pointer to the HW structure
660 * @queue: target pf queue index
661 * @enable: state change request
663 * Handles hw requirement to indicate intention to enable
664 * or disable target queue.
666 void i40e_pre_tx_queue_cfg(struct i40e_hw
*hw
, u32 queue
, bool enable
)
668 u32 abs_queue_idx
= hw
->func_caps
.base_queue
+ queue
;
672 if (abs_queue_idx
>= 128)
673 reg_block
= abs_queue_idx
/ 128;
675 reg_val
= rd32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
));
676 reg_val
&= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK
;
677 reg_val
|= (abs_queue_idx
<< I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT
);
680 reg_val
|= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK
;
682 reg_val
|= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK
;
684 wr32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
), reg_val
);
688 * i40e_get_media_type - Gets media type
689 * @hw: pointer to the hardware structure
691 static enum i40e_media_type
i40e_get_media_type(struct i40e_hw
*hw
)
693 enum i40e_media_type media
;
695 switch (hw
->phy
.link_info
.phy_type
) {
696 case I40E_PHY_TYPE_10GBASE_SR
:
697 case I40E_PHY_TYPE_10GBASE_LR
:
698 case I40E_PHY_TYPE_40GBASE_SR4
:
699 case I40E_PHY_TYPE_40GBASE_LR4
:
700 media
= I40E_MEDIA_TYPE_FIBER
;
702 case I40E_PHY_TYPE_100BASE_TX
:
703 case I40E_PHY_TYPE_1000BASE_T
:
704 case I40E_PHY_TYPE_10GBASE_T
:
705 media
= I40E_MEDIA_TYPE_BASET
;
707 case I40E_PHY_TYPE_10GBASE_CR1_CU
:
708 case I40E_PHY_TYPE_40GBASE_CR4_CU
:
709 case I40E_PHY_TYPE_10GBASE_CR1
:
710 case I40E_PHY_TYPE_40GBASE_CR4
:
711 case I40E_PHY_TYPE_10GBASE_SFPP_CU
:
712 media
= I40E_MEDIA_TYPE_DA
;
714 case I40E_PHY_TYPE_1000BASE_KX
:
715 case I40E_PHY_TYPE_10GBASE_KX4
:
716 case I40E_PHY_TYPE_10GBASE_KR
:
717 case I40E_PHY_TYPE_40GBASE_KR4
:
718 media
= I40E_MEDIA_TYPE_BACKPLANE
;
720 case I40E_PHY_TYPE_SGMII
:
721 case I40E_PHY_TYPE_XAUI
:
722 case I40E_PHY_TYPE_XFI
:
723 case I40E_PHY_TYPE_XLAUI
:
724 case I40E_PHY_TYPE_XLPPI
:
726 media
= I40E_MEDIA_TYPE_UNKNOWN
;
733 #define I40E_PF_RESET_WAIT_COUNT_A0 200
734 #define I40E_PF_RESET_WAIT_COUNT 100
736 * i40e_pf_reset - Reset the PF
737 * @hw: pointer to the hardware structure
739 * Assuming someone else has triggered a global reset,
740 * assure the global reset is complete and then reset the PF
742 i40e_status
i40e_pf_reset(struct i40e_hw
*hw
)
749 /* Poll for Global Reset steady state in case of recent GRST.
750 * The grst delay value is in 100ms units, and we'll wait a
751 * couple counts longer to be sure we don't just miss the end.
753 grst_del
= rd32(hw
, I40E_GLGEN_RSTCTL
) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
754 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT
;
755 for (cnt
= 0; cnt
< grst_del
+ 2; cnt
++) {
756 reg
= rd32(hw
, I40E_GLGEN_RSTAT
);
757 if (!(reg
& I40E_GLGEN_RSTAT_DEVSTATE_MASK
))
761 if (reg
& I40E_GLGEN_RSTAT_DEVSTATE_MASK
) {
762 hw_dbg(hw
, "Global reset polling failed to complete.\n");
763 return I40E_ERR_RESET_FAILED
;
766 /* Now Wait for the FW to be ready */
767 for (cnt1
= 0; cnt1
< I40E_PF_RESET_WAIT_COUNT
; cnt1
++) {
768 reg
= rd32(hw
, I40E_GLNVM_ULD
);
769 reg
&= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
|
770 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
);
771 if (reg
== (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
|
772 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
)) {
773 hw_dbg(hw
, "Core and Global modules ready %d\n", cnt1
);
776 usleep_range(10000, 20000);
778 if (!(reg
& (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
|
779 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
))) {
780 hw_dbg(hw
, "wait for FW Reset complete timedout\n");
781 hw_dbg(hw
, "I40E_GLNVM_ULD = 0x%x\n", reg
);
782 return I40E_ERR_RESET_FAILED
;
785 /* If there was a Global Reset in progress when we got here,
786 * we don't need to do the PF Reset
789 if (hw
->revision_id
== 0)
790 cnt
= I40E_PF_RESET_WAIT_COUNT_A0
;
792 cnt
= I40E_PF_RESET_WAIT_COUNT
;
793 reg
= rd32(hw
, I40E_PFGEN_CTRL
);
794 wr32(hw
, I40E_PFGEN_CTRL
,
795 (reg
| I40E_PFGEN_CTRL_PFSWR_MASK
));
797 reg
= rd32(hw
, I40E_PFGEN_CTRL
);
798 if (!(reg
& I40E_PFGEN_CTRL_PFSWR_MASK
))
800 usleep_range(1000, 2000);
802 if (reg
& I40E_PFGEN_CTRL_PFSWR_MASK
) {
803 hw_dbg(hw
, "PF reset polling failed to complete.\n");
804 return I40E_ERR_RESET_FAILED
;
808 i40e_clear_pxe_mode(hw
);
814 * i40e_clear_pxe_mode - clear pxe operations mode
815 * @hw: pointer to the hw struct
817 * Make sure all PXE mode settings are cleared, including things
818 * like descriptor fetch/write-back mode.
820 void i40e_clear_pxe_mode(struct i40e_hw
*hw
)
824 if (i40e_check_asq_alive(hw
))
825 i40e_aq_clear_pxe_mode(hw
, NULL
);
827 /* Clear single descriptor fetch/write-back mode */
828 reg
= rd32(hw
, I40E_GLLAN_RCTL_0
);
830 if (hw
->revision_id
== 0) {
831 /* As a work around clear PXE_MODE instead of setting it */
832 wr32(hw
, I40E_GLLAN_RCTL_0
, (reg
& (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK
)));
834 wr32(hw
, I40E_GLLAN_RCTL_0
, (reg
| I40E_GLLAN_RCTL_0_PXE_MODE_MASK
));
839 * i40e_led_is_mine - helper to find matching led
840 * @hw: pointer to the hw struct
841 * @idx: index into GPIO registers
843 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
845 static u32
i40e_led_is_mine(struct i40e_hw
*hw
, int idx
)
850 if (!hw
->func_caps
.led
[idx
])
853 gpio_val
= rd32(hw
, I40E_GLGEN_GPIO_CTL(idx
));
854 port
= (gpio_val
& I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK
) >>
855 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT
;
857 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
858 * if it is not our port then ignore
860 if ((gpio_val
& I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK
) ||
868 #define I40E_LINK_ACTIVITY 0xC
871 * i40e_led_get - return current on/off mode
872 * @hw: pointer to the hw struct
874 * The value returned is the 'mode' field as defined in the
875 * GPIO register definitions: 0x0 = off, 0xf = on, and other
876 * values are variations of possible behaviors relating to
877 * blink, link, and wire.
879 u32
i40e_led_get(struct i40e_hw
*hw
)
884 /* as per the documentation GPIO 22-29 are the LED
885 * GPIO pins named LED0..LED7
887 for (i
= I40E_LED0
; i
<= I40E_GLGEN_GPIO_CTL_MAX_INDEX
; i
++) {
888 u32 gpio_val
= i40e_led_is_mine(hw
, i
);
893 mode
= (gpio_val
& I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
) >>
894 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
;
902 * i40e_led_set - set new on/off mode
903 * @hw: pointer to the hw struct
904 * @mode: 0=off, 0xf=on (else see manual for mode details)
905 * @blink: true if the LED should blink when on, false if steady
907 * if this function is used to turn on the blink it should
908 * be used to disable the blink when restoring the original state.
910 void i40e_led_set(struct i40e_hw
*hw
, u32 mode
, bool blink
)
914 if (mode
& 0xfffffff0)
915 hw_dbg(hw
, "invalid mode passed in %X\n", mode
);
917 /* as per the documentation GPIO 22-29 are the LED
918 * GPIO pins named LED0..LED7
920 for (i
= I40E_LED0
; i
<= I40E_GLGEN_GPIO_CTL_MAX_INDEX
; i
++) {
921 u32 gpio_val
= i40e_led_is_mine(hw
, i
);
926 gpio_val
&= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
;
927 /* this & is a bit of paranoia, but serves as a range check */
928 gpio_val
|= ((mode
<< I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
) &
929 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
);
931 if (mode
== I40E_LINK_ACTIVITY
)
934 gpio_val
|= (blink
? 1 : 0) <<
935 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT
;
937 wr32(hw
, I40E_GLGEN_GPIO_CTL(i
), gpio_val
);
942 /* Admin command wrappers */
945 * i40e_aq_clear_pxe_mode
946 * @hw: pointer to the hw struct
947 * @cmd_details: pointer to command details structure or NULL
949 * Tell the firmware that the driver is taking over from PXE
951 i40e_status
i40e_aq_clear_pxe_mode(struct i40e_hw
*hw
,
952 struct i40e_asq_cmd_details
*cmd_details
)
955 struct i40e_aq_desc desc
;
956 struct i40e_aqc_clear_pxe
*cmd
=
957 (struct i40e_aqc_clear_pxe
*)&desc
.params
.raw
;
959 i40e_fill_default_direct_cmd_desc(&desc
,
960 i40e_aqc_opc_clear_pxe_mode
);
964 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
966 wr32(hw
, I40E_GLLAN_RCTL_0
, 0x1);
972 * i40e_aq_set_link_restart_an
973 * @hw: pointer to the hw struct
974 * @cmd_details: pointer to command details structure or NULL
976 * Sets up the link and restarts the Auto-Negotiation over the link.
978 i40e_status
i40e_aq_set_link_restart_an(struct i40e_hw
*hw
,
979 struct i40e_asq_cmd_details
*cmd_details
)
981 struct i40e_aq_desc desc
;
982 struct i40e_aqc_set_link_restart_an
*cmd
=
983 (struct i40e_aqc_set_link_restart_an
*)&desc
.params
.raw
;
986 i40e_fill_default_direct_cmd_desc(&desc
,
987 i40e_aqc_opc_set_link_restart_an
);
989 cmd
->command
= I40E_AQ_PHY_RESTART_AN
;
991 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
997 * i40e_aq_get_link_info
998 * @hw: pointer to the hw struct
999 * @enable_lse: enable/disable LinkStatusEvent reporting
1000 * @link: pointer to link status structure - optional
1001 * @cmd_details: pointer to command details structure or NULL
1003 * Returns the link status of the adapter.
1005 i40e_status
i40e_aq_get_link_info(struct i40e_hw
*hw
,
1006 bool enable_lse
, struct i40e_link_status
*link
,
1007 struct i40e_asq_cmd_details
*cmd_details
)
1009 struct i40e_aq_desc desc
;
1010 struct i40e_aqc_get_link_status
*resp
=
1011 (struct i40e_aqc_get_link_status
*)&desc
.params
.raw
;
1012 struct i40e_link_status
*hw_link_info
= &hw
->phy
.link_info
;
1016 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_get_link_status
);
1019 command_flags
= I40E_AQ_LSE_ENABLE
;
1021 command_flags
= I40E_AQ_LSE_DISABLE
;
1022 resp
->command_flags
= cpu_to_le16(command_flags
);
1024 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1027 goto aq_get_link_info_exit
;
1029 /* save off old link status information */
1030 hw
->phy
.link_info_old
= *hw_link_info
;
1032 /* update link status */
1033 hw_link_info
->phy_type
= (enum i40e_aq_phy_type
)resp
->phy_type
;
1034 hw
->phy
.media_type
= i40e_get_media_type(hw
);
1035 hw_link_info
->link_speed
= (enum i40e_aq_link_speed
)resp
->link_speed
;
1036 hw_link_info
->link_info
= resp
->link_info
;
1037 hw_link_info
->an_info
= resp
->an_info
;
1038 hw_link_info
->ext_info
= resp
->ext_info
;
1039 hw_link_info
->loopback
= resp
->loopback
;
1040 hw_link_info
->max_frame_size
= le16_to_cpu(resp
->max_frame_size
);
1041 hw_link_info
->pacing
= resp
->config
& I40E_AQ_CONFIG_PACING_MASK
;
1043 if (resp
->config
& I40E_AQ_CONFIG_CRC_ENA
)
1044 hw_link_info
->crc_enable
= true;
1046 hw_link_info
->crc_enable
= false;
1048 if (resp
->command_flags
& cpu_to_le16(I40E_AQ_LSE_ENABLE
))
1049 hw_link_info
->lse_enable
= true;
1051 hw_link_info
->lse_enable
= false;
1053 /* save link status information */
1055 *link
= *hw_link_info
;
1057 /* flag cleared so helper functions don't call AQ again */
1058 hw
->phy
.get_link_info
= false;
1060 aq_get_link_info_exit
:
1066 * @hw: pointer to the hw struct
1067 * @vsi_ctx: pointer to a vsi context struct
1068 * @cmd_details: pointer to command details structure or NULL
1070 * Add a VSI context to the hardware.
1072 i40e_status
i40e_aq_add_vsi(struct i40e_hw
*hw
,
1073 struct i40e_vsi_context
*vsi_ctx
,
1074 struct i40e_asq_cmd_details
*cmd_details
)
1076 struct i40e_aq_desc desc
;
1077 struct i40e_aqc_add_get_update_vsi
*cmd
=
1078 (struct i40e_aqc_add_get_update_vsi
*)&desc
.params
.raw
;
1079 struct i40e_aqc_add_get_update_vsi_completion
*resp
=
1080 (struct i40e_aqc_add_get_update_vsi_completion
*)
1084 i40e_fill_default_direct_cmd_desc(&desc
,
1085 i40e_aqc_opc_add_vsi
);
1087 cmd
->uplink_seid
= cpu_to_le16(vsi_ctx
->uplink_seid
);
1088 cmd
->connection_type
= vsi_ctx
->connection_type
;
1089 cmd
->vf_id
= vsi_ctx
->vf_num
;
1090 cmd
->vsi_flags
= cpu_to_le16(vsi_ctx
->flags
);
1092 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
1094 status
= i40e_asq_send_command(hw
, &desc
, &vsi_ctx
->info
,
1095 sizeof(vsi_ctx
->info
), cmd_details
);
1098 goto aq_add_vsi_exit
;
1100 vsi_ctx
->seid
= le16_to_cpu(resp
->seid
);
1101 vsi_ctx
->vsi_number
= le16_to_cpu(resp
->vsi_number
);
1102 vsi_ctx
->vsis_allocated
= le16_to_cpu(resp
->vsi_used
);
1103 vsi_ctx
->vsis_unallocated
= le16_to_cpu(resp
->vsi_free
);
1110 * i40e_aq_set_vsi_unicast_promiscuous
1111 * @hw: pointer to the hw struct
1113 * @set: set unicast promiscuous enable/disable
1114 * @cmd_details: pointer to command details structure or NULL
1116 i40e_status
i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw
*hw
,
1118 struct i40e_asq_cmd_details
*cmd_details
)
1120 struct i40e_aq_desc desc
;
1121 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
1122 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
1126 i40e_fill_default_direct_cmd_desc(&desc
,
1127 i40e_aqc_opc_set_vsi_promiscuous_modes
);
1130 flags
|= I40E_AQC_SET_VSI_PROMISC_UNICAST
;
1132 cmd
->promiscuous_flags
= cpu_to_le16(flags
);
1134 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST
);
1136 cmd
->seid
= cpu_to_le16(seid
);
1137 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1143 * i40e_aq_set_vsi_multicast_promiscuous
1144 * @hw: pointer to the hw struct
1146 * @set: set multicast promiscuous enable/disable
1147 * @cmd_details: pointer to command details structure or NULL
1149 i40e_status
i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw
*hw
,
1150 u16 seid
, bool set
, struct i40e_asq_cmd_details
*cmd_details
)
1152 struct i40e_aq_desc desc
;
1153 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
1154 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
1158 i40e_fill_default_direct_cmd_desc(&desc
,
1159 i40e_aqc_opc_set_vsi_promiscuous_modes
);
1162 flags
|= I40E_AQC_SET_VSI_PROMISC_MULTICAST
;
1164 cmd
->promiscuous_flags
= cpu_to_le16(flags
);
1166 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST
);
1168 cmd
->seid
= cpu_to_le16(seid
);
1169 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1175 * i40e_aq_set_vsi_broadcast
1176 * @hw: pointer to the hw struct
1178 * @set_filter: true to set filter, false to clear filter
1179 * @cmd_details: pointer to command details structure or NULL
1181 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1183 i40e_status
i40e_aq_set_vsi_broadcast(struct i40e_hw
*hw
,
1184 u16 seid
, bool set_filter
,
1185 struct i40e_asq_cmd_details
*cmd_details
)
1187 struct i40e_aq_desc desc
;
1188 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
1189 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
1192 i40e_fill_default_direct_cmd_desc(&desc
,
1193 i40e_aqc_opc_set_vsi_promiscuous_modes
);
1196 cmd
->promiscuous_flags
1197 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST
);
1199 cmd
->promiscuous_flags
1200 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST
);
1202 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST
);
1203 cmd
->seid
= cpu_to_le16(seid
);
1204 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1210 * i40e_get_vsi_params - get VSI configuration info
1211 * @hw: pointer to the hw struct
1212 * @vsi_ctx: pointer to a vsi context struct
1213 * @cmd_details: pointer to command details structure or NULL
1215 i40e_status
i40e_aq_get_vsi_params(struct i40e_hw
*hw
,
1216 struct i40e_vsi_context
*vsi_ctx
,
1217 struct i40e_asq_cmd_details
*cmd_details
)
1219 struct i40e_aq_desc desc
;
1220 struct i40e_aqc_add_get_update_vsi
*cmd
=
1221 (struct i40e_aqc_add_get_update_vsi
*)&desc
.params
.raw
;
1222 struct i40e_aqc_add_get_update_vsi_completion
*resp
=
1223 (struct i40e_aqc_add_get_update_vsi_completion
*)
1227 i40e_fill_default_direct_cmd_desc(&desc
,
1228 i40e_aqc_opc_get_vsi_parameters
);
1230 cmd
->uplink_seid
= cpu_to_le16(vsi_ctx
->seid
);
1232 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
1234 status
= i40e_asq_send_command(hw
, &desc
, &vsi_ctx
->info
,
1235 sizeof(vsi_ctx
->info
), NULL
);
1238 goto aq_get_vsi_params_exit
;
1240 vsi_ctx
->seid
= le16_to_cpu(resp
->seid
);
1241 vsi_ctx
->vsi_number
= le16_to_cpu(resp
->vsi_number
);
1242 vsi_ctx
->vsis_allocated
= le16_to_cpu(resp
->vsi_used
);
1243 vsi_ctx
->vsis_unallocated
= le16_to_cpu(resp
->vsi_free
);
1245 aq_get_vsi_params_exit
:
1250 * i40e_aq_update_vsi_params
1251 * @hw: pointer to the hw struct
1252 * @vsi_ctx: pointer to a vsi context struct
1253 * @cmd_details: pointer to command details structure or NULL
1255 * Update a VSI context.
1257 i40e_status
i40e_aq_update_vsi_params(struct i40e_hw
*hw
,
1258 struct i40e_vsi_context
*vsi_ctx
,
1259 struct i40e_asq_cmd_details
*cmd_details
)
1261 struct i40e_aq_desc desc
;
1262 struct i40e_aqc_add_get_update_vsi
*cmd
=
1263 (struct i40e_aqc_add_get_update_vsi
*)&desc
.params
.raw
;
1266 i40e_fill_default_direct_cmd_desc(&desc
,
1267 i40e_aqc_opc_update_vsi_parameters
);
1268 cmd
->uplink_seid
= cpu_to_le16(vsi_ctx
->seid
);
1270 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
1272 status
= i40e_asq_send_command(hw
, &desc
, &vsi_ctx
->info
,
1273 sizeof(vsi_ctx
->info
), cmd_details
);
1279 * i40e_aq_get_switch_config
1280 * @hw: pointer to the hardware structure
1281 * @buf: pointer to the result buffer
1282 * @buf_size: length of input buffer
1283 * @start_seid: seid to start for the report, 0 == beginning
1284 * @cmd_details: pointer to command details structure or NULL
1286 * Fill the buf with switch configuration returned from AdminQ command
1288 i40e_status
i40e_aq_get_switch_config(struct i40e_hw
*hw
,
1289 struct i40e_aqc_get_switch_config_resp
*buf
,
1290 u16 buf_size
, u16
*start_seid
,
1291 struct i40e_asq_cmd_details
*cmd_details
)
1293 struct i40e_aq_desc desc
;
1294 struct i40e_aqc_switch_seid
*scfg
=
1295 (struct i40e_aqc_switch_seid
*)&desc
.params
.raw
;
1298 i40e_fill_default_direct_cmd_desc(&desc
,
1299 i40e_aqc_opc_get_switch_config
);
1300 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
1301 if (buf_size
> I40E_AQ_LARGE_BUF
)
1302 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
1303 scfg
->seid
= cpu_to_le16(*start_seid
);
1305 status
= i40e_asq_send_command(hw
, &desc
, buf
, buf_size
, cmd_details
);
1306 *start_seid
= le16_to_cpu(scfg
->seid
);
1312 * i40e_aq_get_firmware_version
1313 * @hw: pointer to the hw struct
1314 * @fw_major_version: firmware major version
1315 * @fw_minor_version: firmware minor version
1316 * @api_major_version: major queue version
1317 * @api_minor_version: minor queue version
1318 * @cmd_details: pointer to command details structure or NULL
1320 * Get the firmware version from the admin queue commands
1322 i40e_status
i40e_aq_get_firmware_version(struct i40e_hw
*hw
,
1323 u16
*fw_major_version
, u16
*fw_minor_version
,
1324 u16
*api_major_version
, u16
*api_minor_version
,
1325 struct i40e_asq_cmd_details
*cmd_details
)
1327 struct i40e_aq_desc desc
;
1328 struct i40e_aqc_get_version
*resp
=
1329 (struct i40e_aqc_get_version
*)&desc
.params
.raw
;
1332 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_get_version
);
1334 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1337 if (fw_major_version
!= NULL
)
1338 *fw_major_version
= le16_to_cpu(resp
->fw_major
);
1339 if (fw_minor_version
!= NULL
)
1340 *fw_minor_version
= le16_to_cpu(resp
->fw_minor
);
1341 if (api_major_version
!= NULL
)
1342 *api_major_version
= le16_to_cpu(resp
->api_major
);
1343 if (api_minor_version
!= NULL
)
1344 *api_minor_version
= le16_to_cpu(resp
->api_minor
);
1351 * i40e_aq_send_driver_version
1352 * @hw: pointer to the hw struct
1353 * @dv: driver's major, minor version
1354 * @cmd_details: pointer to command details structure or NULL
1356 * Send the driver version to the firmware
1358 i40e_status
i40e_aq_send_driver_version(struct i40e_hw
*hw
,
1359 struct i40e_driver_version
*dv
,
1360 struct i40e_asq_cmd_details
*cmd_details
)
1362 struct i40e_aq_desc desc
;
1363 struct i40e_aqc_driver_version
*cmd
=
1364 (struct i40e_aqc_driver_version
*)&desc
.params
.raw
;
1369 return I40E_ERR_PARAM
;
1371 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_driver_version
);
1373 desc
.flags
|= cpu_to_le16(I40E_AQ_FLAG_SI
);
1374 cmd
->driver_major_ver
= dv
->major_version
;
1375 cmd
->driver_minor_ver
= dv
->minor_version
;
1376 cmd
->driver_build_ver
= dv
->build_version
;
1377 cmd
->driver_subbuild_ver
= dv
->subbuild_version
;
1380 while (len
< sizeof(dv
->driver_string
) &&
1381 (dv
->driver_string
[len
] < 0x80) &&
1382 dv
->driver_string
[len
])
1384 status
= i40e_asq_send_command(hw
, &desc
, dv
->driver_string
,
1391 * i40e_get_link_status - get status of the HW network link
1392 * @hw: pointer to the hw struct
1394 * Returns true if link is up, false if link is down.
1396 * Side effect: LinkStatusEvent reporting becomes enabled
1398 bool i40e_get_link_status(struct i40e_hw
*hw
)
1400 i40e_status status
= 0;
1401 bool link_status
= false;
1403 if (hw
->phy
.get_link_info
) {
1404 status
= i40e_aq_get_link_info(hw
, true, NULL
, NULL
);
1407 goto i40e_get_link_status_exit
;
1410 link_status
= hw
->phy
.link_info
.link_info
& I40E_AQ_LINK_UP
;
1412 i40e_get_link_status_exit
:
1417 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1418 * @hw: pointer to the hw struct
1419 * @uplink_seid: the MAC or other gizmo SEID
1420 * @downlink_seid: the VSI SEID
1421 * @enabled_tc: bitmap of TCs to be enabled
1422 * @default_port: true for default port VSI, false for control port
1423 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
1424 * @veb_seid: pointer to where to put the resulting VEB SEID
1425 * @cmd_details: pointer to command details structure or NULL
1427 * This asks the FW to add a VEB between the uplink and downlink
1428 * elements. If the uplink SEID is 0, this will be a floating VEB.
1430 i40e_status
i40e_aq_add_veb(struct i40e_hw
*hw
, u16 uplink_seid
,
1431 u16 downlink_seid
, u8 enabled_tc
,
1432 bool default_port
, bool enable_l2_filtering
,
1434 struct i40e_asq_cmd_details
*cmd_details
)
1436 struct i40e_aq_desc desc
;
1437 struct i40e_aqc_add_veb
*cmd
=
1438 (struct i40e_aqc_add_veb
*)&desc
.params
.raw
;
1439 struct i40e_aqc_add_veb_completion
*resp
=
1440 (struct i40e_aqc_add_veb_completion
*)&desc
.params
.raw
;
1444 /* SEIDs need to either both be set or both be 0 for floating VEB */
1445 if (!!uplink_seid
!= !!downlink_seid
)
1446 return I40E_ERR_PARAM
;
1448 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_add_veb
);
1450 cmd
->uplink_seid
= cpu_to_le16(uplink_seid
);
1451 cmd
->downlink_seid
= cpu_to_le16(downlink_seid
);
1452 cmd
->enable_tcs
= enabled_tc
;
1454 veb_flags
|= I40E_AQC_ADD_VEB_FLOATING
;
1456 veb_flags
|= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT
;
1458 veb_flags
|= I40E_AQC_ADD_VEB_PORT_TYPE_DATA
;
1460 if (enable_l2_filtering
)
1461 veb_flags
|= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER
;
1463 cmd
->veb_flags
= cpu_to_le16(veb_flags
);
1465 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1467 if (!status
&& veb_seid
)
1468 *veb_seid
= le16_to_cpu(resp
->veb_seid
);
1474 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1475 * @hw: pointer to the hw struct
1476 * @veb_seid: the SEID of the VEB to query
1477 * @switch_id: the uplink switch id
1478 * @floating: set to true if the VEB is floating
1479 * @statistic_index: index of the stats counter block for this VEB
1480 * @vebs_used: number of VEB's used by function
1481 * @vebs_free: total VEB's not reserved by any function
1482 * @cmd_details: pointer to command details structure or NULL
1484 * This retrieves the parameters for a particular VEB, specified by
1485 * uplink_seid, and returns them to the caller.
1487 i40e_status
i40e_aq_get_veb_parameters(struct i40e_hw
*hw
,
1488 u16 veb_seid
, u16
*switch_id
,
1489 bool *floating
, u16
*statistic_index
,
1490 u16
*vebs_used
, u16
*vebs_free
,
1491 struct i40e_asq_cmd_details
*cmd_details
)
1493 struct i40e_aq_desc desc
;
1494 struct i40e_aqc_get_veb_parameters_completion
*cmd_resp
=
1495 (struct i40e_aqc_get_veb_parameters_completion
*)
1500 return I40E_ERR_PARAM
;
1502 i40e_fill_default_direct_cmd_desc(&desc
,
1503 i40e_aqc_opc_get_veb_parameters
);
1504 cmd_resp
->seid
= cpu_to_le16(veb_seid
);
1506 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1511 *switch_id
= le16_to_cpu(cmd_resp
->switch_id
);
1512 if (statistic_index
)
1513 *statistic_index
= le16_to_cpu(cmd_resp
->statistic_index
);
1515 *vebs_used
= le16_to_cpu(cmd_resp
->vebs_used
);
1517 *vebs_free
= le16_to_cpu(cmd_resp
->vebs_free
);
1519 u16 flags
= le16_to_cpu(cmd_resp
->veb_flags
);
1520 if (flags
& I40E_AQC_ADD_VEB_FLOATING
)
1531 * i40e_aq_add_macvlan
1532 * @hw: pointer to the hw struct
1533 * @seid: VSI for the mac address
1534 * @mv_list: list of macvlans to be added
1535 * @count: length of the list
1536 * @cmd_details: pointer to command details structure or NULL
1538 * Add MAC/VLAN addresses to the HW filtering
1540 i40e_status
i40e_aq_add_macvlan(struct i40e_hw
*hw
, u16 seid
,
1541 struct i40e_aqc_add_macvlan_element_data
*mv_list
,
1542 u16 count
, struct i40e_asq_cmd_details
*cmd_details
)
1544 struct i40e_aq_desc desc
;
1545 struct i40e_aqc_macvlan
*cmd
=
1546 (struct i40e_aqc_macvlan
*)&desc
.params
.raw
;
1550 if (count
== 0 || !mv_list
|| !hw
)
1551 return I40E_ERR_PARAM
;
1553 buf_size
= count
* sizeof(struct i40e_aqc_add_macvlan_element_data
);
1555 /* prep the rest of the request */
1556 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_add_macvlan
);
1557 cmd
->num_addresses
= cpu_to_le16(count
);
1558 cmd
->seid
[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID
| seid
);
1562 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
1563 if (buf_size
> I40E_AQ_LARGE_BUF
)
1564 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
1566 status
= i40e_asq_send_command(hw
, &desc
, mv_list
, buf_size
,
1573 * i40e_aq_remove_macvlan
1574 * @hw: pointer to the hw struct
1575 * @seid: VSI for the mac address
1576 * @mv_list: list of macvlans to be removed
1577 * @count: length of the list
1578 * @cmd_details: pointer to command details structure or NULL
1580 * Remove MAC/VLAN addresses from the HW filtering
1582 i40e_status
i40e_aq_remove_macvlan(struct i40e_hw
*hw
, u16 seid
,
1583 struct i40e_aqc_remove_macvlan_element_data
*mv_list
,
1584 u16 count
, struct i40e_asq_cmd_details
*cmd_details
)
1586 struct i40e_aq_desc desc
;
1587 struct i40e_aqc_macvlan
*cmd
=
1588 (struct i40e_aqc_macvlan
*)&desc
.params
.raw
;
1592 if (count
== 0 || !mv_list
|| !hw
)
1593 return I40E_ERR_PARAM
;
1595 buf_size
= count
* sizeof(struct i40e_aqc_remove_macvlan_element_data
);
1597 /* prep the rest of the request */
1598 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_remove_macvlan
);
1599 cmd
->num_addresses
= cpu_to_le16(count
);
1600 cmd
->seid
[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID
| seid
);
1604 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
1605 if (buf_size
> I40E_AQ_LARGE_BUF
)
1606 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
1608 status
= i40e_asq_send_command(hw
, &desc
, mv_list
, buf_size
,
1615 * i40e_aq_send_msg_to_vf
1616 * @hw: pointer to the hardware structure
1617 * @vfid: vf id to send msg
1618 * @v_opcode: opcodes for VF-PF communication
1619 * @v_retval: return error code
1620 * @msg: pointer to the msg buffer
1621 * @msglen: msg length
1622 * @cmd_details: pointer to command details
1626 i40e_status
i40e_aq_send_msg_to_vf(struct i40e_hw
*hw
, u16 vfid
,
1627 u32 v_opcode
, u32 v_retval
, u8
*msg
, u16 msglen
,
1628 struct i40e_asq_cmd_details
*cmd_details
)
1630 struct i40e_aq_desc desc
;
1631 struct i40e_aqc_pf_vf_message
*cmd
=
1632 (struct i40e_aqc_pf_vf_message
*)&desc
.params
.raw
;
1635 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_send_msg_to_vf
);
1636 cmd
->id
= cpu_to_le32(vfid
);
1637 desc
.cookie_high
= cpu_to_le32(v_opcode
);
1638 desc
.cookie_low
= cpu_to_le32(v_retval
);
1639 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_SI
);
1641 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
|
1643 if (msglen
> I40E_AQ_LARGE_BUF
)
1644 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
1645 desc
.datalen
= cpu_to_le16(msglen
);
1647 status
= i40e_asq_send_command(hw
, &desc
, msg
, msglen
, cmd_details
);
1653 * i40e_aq_set_hmc_resource_profile
1654 * @hw: pointer to the hw struct
1655 * @profile: type of profile the HMC is to be set as
1656 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
1657 * @cmd_details: pointer to command details structure or NULL
1659 * set the HMC profile of the device.
1661 i40e_status
i40e_aq_set_hmc_resource_profile(struct i40e_hw
*hw
,
1662 enum i40e_aq_hmc_profile profile
,
1663 u8 pe_vf_enabled_count
,
1664 struct i40e_asq_cmd_details
*cmd_details
)
1666 struct i40e_aq_desc desc
;
1667 struct i40e_aq_get_set_hmc_resource_profile
*cmd
=
1668 (struct i40e_aq_get_set_hmc_resource_profile
*)&desc
.params
.raw
;
1671 i40e_fill_default_direct_cmd_desc(&desc
,
1672 i40e_aqc_opc_set_hmc_resource_profile
);
1674 cmd
->pm_profile
= (u8
)profile
;
1675 cmd
->pe_vf_enabled
= pe_vf_enabled_count
;
1677 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1683 * i40e_aq_request_resource
1684 * @hw: pointer to the hw struct
1685 * @resource: resource id
1686 * @access: access type
1687 * @sdp_number: resource number
1688 * @timeout: the maximum time in ms that the driver may hold the resource
1689 * @cmd_details: pointer to command details structure or NULL
1691 * requests common resource using the admin queue commands
1693 i40e_status
i40e_aq_request_resource(struct i40e_hw
*hw
,
1694 enum i40e_aq_resources_ids resource
,
1695 enum i40e_aq_resource_access_type access
,
1696 u8 sdp_number
, u64
*timeout
,
1697 struct i40e_asq_cmd_details
*cmd_details
)
1699 struct i40e_aq_desc desc
;
1700 struct i40e_aqc_request_resource
*cmd_resp
=
1701 (struct i40e_aqc_request_resource
*)&desc
.params
.raw
;
1704 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_request_resource
);
1706 cmd_resp
->resource_id
= cpu_to_le16(resource
);
1707 cmd_resp
->access_type
= cpu_to_le16(access
);
1708 cmd_resp
->resource_number
= cpu_to_le32(sdp_number
);
1710 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1711 /* The completion specifies the maximum time in ms that the driver
1712 * may hold the resource in the Timeout field.
1713 * If the resource is held by someone else, the command completes with
1714 * busy return value and the timeout field indicates the maximum time
1715 * the current owner of the resource has to free it.
1717 if (!status
|| hw
->aq
.asq_last_status
== I40E_AQ_RC_EBUSY
)
1718 *timeout
= le32_to_cpu(cmd_resp
->timeout
);
1724 * i40e_aq_release_resource
1725 * @hw: pointer to the hw struct
1726 * @resource: resource id
1727 * @sdp_number: resource number
1728 * @cmd_details: pointer to command details structure or NULL
1730 * release common resource using the admin queue commands
1732 i40e_status
i40e_aq_release_resource(struct i40e_hw
*hw
,
1733 enum i40e_aq_resources_ids resource
,
1735 struct i40e_asq_cmd_details
*cmd_details
)
1737 struct i40e_aq_desc desc
;
1738 struct i40e_aqc_request_resource
*cmd
=
1739 (struct i40e_aqc_request_resource
*)&desc
.params
.raw
;
1742 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_release_resource
);
1744 cmd
->resource_id
= cpu_to_le16(resource
);
1745 cmd
->resource_number
= cpu_to_le32(sdp_number
);
1747 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1754 * @hw: pointer to the hw struct
1755 * @module_pointer: module pointer location in words from the NVM beginning
1756 * @offset: byte offset from the module beginning
1757 * @length: length of the section to be read (in bytes from the offset)
1758 * @data: command buffer (size [bytes] = length)
1759 * @last_command: tells if this is the last command in a series
1760 * @cmd_details: pointer to command details structure or NULL
1762 * Read the NVM using the admin queue commands
1764 i40e_status
i40e_aq_read_nvm(struct i40e_hw
*hw
, u8 module_pointer
,
1765 u32 offset
, u16 length
, void *data
,
1767 struct i40e_asq_cmd_details
*cmd_details
)
1769 struct i40e_aq_desc desc
;
1770 struct i40e_aqc_nvm_update
*cmd
=
1771 (struct i40e_aqc_nvm_update
*)&desc
.params
.raw
;
1774 /* In offset the highest byte must be zeroed. */
1775 if (offset
& 0xFF000000) {
1776 status
= I40E_ERR_PARAM
;
1777 goto i40e_aq_read_nvm_exit
;
1780 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_nvm_read
);
1782 /* If this is the last command in a series, set the proper flag. */
1784 cmd
->command_flags
|= I40E_AQ_NVM_LAST_CMD
;
1785 cmd
->module_pointer
= module_pointer
;
1786 cmd
->offset
= cpu_to_le32(offset
);
1787 cmd
->length
= cpu_to_le16(length
);
1789 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
1790 if (length
> I40E_AQ_LARGE_BUF
)
1791 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
1793 status
= i40e_asq_send_command(hw
, &desc
, data
, length
, cmd_details
);
1795 i40e_aq_read_nvm_exit
:
1799 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
1800 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
1801 #define I40E_DEV_FUNC_CAP_NPAR 0x03
1802 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
1803 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
1804 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
1805 #define I40E_DEV_FUNC_CAP_VF 0x13
1806 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
1807 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
1808 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
1809 #define I40E_DEV_FUNC_CAP_VSI 0x17
1810 #define I40E_DEV_FUNC_CAP_DCB 0x18
1811 #define I40E_DEV_FUNC_CAP_FCOE 0x21
1812 #define I40E_DEV_FUNC_CAP_RSS 0x40
1813 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
1814 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
1815 #define I40E_DEV_FUNC_CAP_MSIX 0x43
1816 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
1817 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
1818 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
1819 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
1820 #define I40E_DEV_FUNC_CAP_CEM 0xF2
1821 #define I40E_DEV_FUNC_CAP_IWARP 0x51
1822 #define I40E_DEV_FUNC_CAP_LED 0x61
1823 #define I40E_DEV_FUNC_CAP_SDP 0x62
1824 #define I40E_DEV_FUNC_CAP_MDIO 0x63
1827 * i40e_parse_discover_capabilities
1828 * @hw: pointer to the hw struct
1829 * @buff: pointer to a buffer containing device/function capability records
1830 * @cap_count: number of capability records in the list
1831 * @list_type_opc: type of capabilities list to parse
1833 * Parse the device/function capabilities list.
1835 static void i40e_parse_discover_capabilities(struct i40e_hw
*hw
, void *buff
,
1837 enum i40e_admin_queue_opc list_type_opc
)
1839 struct i40e_aqc_list_capabilities_element_resp
*cap
;
1840 u32 number
, logical_id
, phys_id
;
1841 struct i40e_hw_capabilities
*p
;
1846 cap
= (struct i40e_aqc_list_capabilities_element_resp
*) buff
;
1848 if (list_type_opc
== i40e_aqc_opc_list_dev_capabilities
)
1850 else if (list_type_opc
== i40e_aqc_opc_list_func_capabilities
)
1855 for (i
= 0; i
< cap_count
; i
++, cap
++) {
1856 id
= le16_to_cpu(cap
->id
);
1857 number
= le32_to_cpu(cap
->number
);
1858 logical_id
= le32_to_cpu(cap
->logical_id
);
1859 phys_id
= le32_to_cpu(cap
->phys_id
);
1862 case I40E_DEV_FUNC_CAP_SWITCH_MODE
:
1863 p
->switch_mode
= number
;
1865 case I40E_DEV_FUNC_CAP_MGMT_MODE
:
1866 p
->management_mode
= number
;
1868 case I40E_DEV_FUNC_CAP_NPAR
:
1869 p
->npar_enable
= number
;
1871 case I40E_DEV_FUNC_CAP_OS2BMC
:
1874 case I40E_DEV_FUNC_CAP_VALID_FUNC
:
1875 p
->valid_functions
= number
;
1877 case I40E_DEV_FUNC_CAP_SRIOV_1_1
:
1879 p
->sr_iov_1_1
= true;
1881 case I40E_DEV_FUNC_CAP_VF
:
1882 p
->num_vfs
= number
;
1883 p
->vf_base_id
= logical_id
;
1885 case I40E_DEV_FUNC_CAP_VMDQ
:
1889 case I40E_DEV_FUNC_CAP_802_1_QBG
:
1891 p
->evb_802_1_qbg
= true;
1893 case I40E_DEV_FUNC_CAP_802_1_QBH
:
1895 p
->evb_802_1_qbh
= true;
1897 case I40E_DEV_FUNC_CAP_VSI
:
1898 p
->num_vsis
= number
;
1900 case I40E_DEV_FUNC_CAP_DCB
:
1903 p
->enabled_tcmap
= logical_id
;
1907 case I40E_DEV_FUNC_CAP_FCOE
:
1911 case I40E_DEV_FUNC_CAP_RSS
:
1913 reg_val
= rd32(hw
, I40E_PFQF_CTL_0
);
1914 if (reg_val
& I40E_PFQF_CTL_0_HASHLUTSIZE_MASK
)
1915 p
->rss_table_size
= number
;
1917 p
->rss_table_size
= 128;
1918 p
->rss_table_entry_width
= logical_id
;
1920 case I40E_DEV_FUNC_CAP_RX_QUEUES
:
1921 p
->num_rx_qp
= number
;
1922 p
->base_queue
= phys_id
;
1924 case I40E_DEV_FUNC_CAP_TX_QUEUES
:
1925 p
->num_tx_qp
= number
;
1926 p
->base_queue
= phys_id
;
1928 case I40E_DEV_FUNC_CAP_MSIX
:
1929 p
->num_msix_vectors
= number
;
1931 case I40E_DEV_FUNC_CAP_MSIX_VF
:
1932 p
->num_msix_vectors_vf
= number
;
1934 case I40E_DEV_FUNC_CAP_MFP_MODE_1
:
1936 p
->mfp_mode_1
= true;
1938 case I40E_DEV_FUNC_CAP_CEM
:
1942 case I40E_DEV_FUNC_CAP_IWARP
:
1946 case I40E_DEV_FUNC_CAP_LED
:
1947 if (phys_id
< I40E_HW_CAP_MAX_GPIO
)
1948 p
->led
[phys_id
] = true;
1950 case I40E_DEV_FUNC_CAP_SDP
:
1951 if (phys_id
< I40E_HW_CAP_MAX_GPIO
)
1952 p
->sdp
[phys_id
] = true;
1954 case I40E_DEV_FUNC_CAP_MDIO
:
1956 p
->mdio_port_num
= phys_id
;
1957 p
->mdio_port_mode
= logical_id
;
1960 case I40E_DEV_FUNC_CAP_IEEE_1588
:
1962 p
->ieee_1588
= true;
1964 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR
:
1966 p
->fd_filters_guaranteed
= number
;
1967 p
->fd_filters_best_effort
= logical_id
;
1974 /* Software override ensuring FCoE is disabled if npar or mfp
1975 * mode because it is not supported in these modes.
1977 if (p
->npar_enable
|| p
->mfp_mode_1
)
1980 /* additional HW specific goodies that might
1981 * someday be HW version specific
1983 p
->rx_buf_chain_len
= I40E_MAX_CHAINED_RX_BUFFERS
;
1987 * i40e_aq_discover_capabilities
1988 * @hw: pointer to the hw struct
1989 * @buff: a virtual buffer to hold the capabilities
1990 * @buff_size: Size of the virtual buffer
1991 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
1992 * @list_type_opc: capabilities type to discover - pass in the command opcode
1993 * @cmd_details: pointer to command details structure or NULL
1995 * Get the device capabilities descriptions from the firmware
1997 i40e_status
i40e_aq_discover_capabilities(struct i40e_hw
*hw
,
1998 void *buff
, u16 buff_size
, u16
*data_size
,
1999 enum i40e_admin_queue_opc list_type_opc
,
2000 struct i40e_asq_cmd_details
*cmd_details
)
2002 struct i40e_aqc_list_capabilites
*cmd
;
2003 struct i40e_aq_desc desc
;
2004 i40e_status status
= 0;
2006 cmd
= (struct i40e_aqc_list_capabilites
*)&desc
.params
.raw
;
2008 if (list_type_opc
!= i40e_aqc_opc_list_func_capabilities
&&
2009 list_type_opc
!= i40e_aqc_opc_list_dev_capabilities
) {
2010 status
= I40E_ERR_PARAM
;
2014 i40e_fill_default_direct_cmd_desc(&desc
, list_type_opc
);
2016 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2017 if (buff_size
> I40E_AQ_LARGE_BUF
)
2018 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2020 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
2021 *data_size
= le16_to_cpu(desc
.datalen
);
2026 i40e_parse_discover_capabilities(hw
, buff
, le32_to_cpu(cmd
->count
),
2034 * i40e_aq_get_lldp_mib
2035 * @hw: pointer to the hw struct
2036 * @bridge_type: type of bridge requested
2037 * @mib_type: Local, Remote or both Local and Remote MIBs
2038 * @buff: pointer to a user supplied buffer to store the MIB block
2039 * @buff_size: size of the buffer (in bytes)
2040 * @local_len : length of the returned Local LLDP MIB
2041 * @remote_len: length of the returned Remote LLDP MIB
2042 * @cmd_details: pointer to command details structure or NULL
2044 * Requests the complete LLDP MIB (entire packet).
2046 i40e_status
i40e_aq_get_lldp_mib(struct i40e_hw
*hw
, u8 bridge_type
,
2047 u8 mib_type
, void *buff
, u16 buff_size
,
2048 u16
*local_len
, u16
*remote_len
,
2049 struct i40e_asq_cmd_details
*cmd_details
)
2051 struct i40e_aq_desc desc
;
2052 struct i40e_aqc_lldp_get_mib
*cmd
=
2053 (struct i40e_aqc_lldp_get_mib
*)&desc
.params
.raw
;
2054 struct i40e_aqc_lldp_get_mib
*resp
=
2055 (struct i40e_aqc_lldp_get_mib
*)&desc
.params
.raw
;
2058 if (buff_size
== 0 || !buff
)
2059 return I40E_ERR_PARAM
;
2061 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_get_mib
);
2062 /* Indirect Command */
2063 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2065 cmd
->type
= mib_type
& I40E_AQ_LLDP_MIB_TYPE_MASK
;
2066 cmd
->type
|= ((bridge_type
<< I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT
) &
2067 I40E_AQ_LLDP_BRIDGE_TYPE_MASK
);
2069 desc
.datalen
= cpu_to_le16(buff_size
);
2071 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2072 if (buff_size
> I40E_AQ_LARGE_BUF
)
2073 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2075 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
2077 if (local_len
!= NULL
)
2078 *local_len
= le16_to_cpu(resp
->local_len
);
2079 if (remote_len
!= NULL
)
2080 *remote_len
= le16_to_cpu(resp
->remote_len
);
2087 * i40e_aq_cfg_lldp_mib_change_event
2088 * @hw: pointer to the hw struct
2089 * @enable_update: Enable or Disable event posting
2090 * @cmd_details: pointer to command details structure or NULL
2092 * Enable or Disable posting of an event on ARQ when LLDP MIB
2093 * associated with the interface changes
2095 i40e_status
i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw
*hw
,
2097 struct i40e_asq_cmd_details
*cmd_details
)
2099 struct i40e_aq_desc desc
;
2100 struct i40e_aqc_lldp_update_mib
*cmd
=
2101 (struct i40e_aqc_lldp_update_mib
*)&desc
.params
.raw
;
2104 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_update_mib
);
2107 cmd
->command
|= I40E_AQ_LLDP_MIB_UPDATE_DISABLE
;
2109 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2116 * @hw: pointer to the hw struct
2117 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2118 * @cmd_details: pointer to command details structure or NULL
2120 * Stop or Shutdown the embedded LLDP Agent
2122 i40e_status
i40e_aq_stop_lldp(struct i40e_hw
*hw
, bool shutdown_agent
,
2123 struct i40e_asq_cmd_details
*cmd_details
)
2125 struct i40e_aq_desc desc
;
2126 struct i40e_aqc_lldp_stop
*cmd
=
2127 (struct i40e_aqc_lldp_stop
*)&desc
.params
.raw
;
2130 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_stop
);
2133 cmd
->command
|= I40E_AQ_LLDP_AGENT_SHUTDOWN
;
2135 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2141 * i40e_aq_start_lldp
2142 * @hw: pointer to the hw struct
2143 * @cmd_details: pointer to command details structure or NULL
2145 * Start the embedded LLDP Agent on all ports.
2147 i40e_status
i40e_aq_start_lldp(struct i40e_hw
*hw
,
2148 struct i40e_asq_cmd_details
*cmd_details
)
2150 struct i40e_aq_desc desc
;
2151 struct i40e_aqc_lldp_start
*cmd
=
2152 (struct i40e_aqc_lldp_start
*)&desc
.params
.raw
;
2155 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_start
);
2157 cmd
->command
= I40E_AQ_LLDP_AGENT_START
;
2159 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2165 * i40e_aq_add_udp_tunnel
2166 * @hw: pointer to the hw struct
2167 * @udp_port: the UDP port to add
2168 * @header_len: length of the tunneling header length in DWords
2169 * @protocol_index: protocol index type
2170 * @filter_index: pointer to filter index
2171 * @cmd_details: pointer to command details structure or NULL
2173 i40e_status
i40e_aq_add_udp_tunnel(struct i40e_hw
*hw
,
2174 u16 udp_port
, u8 protocol_index
,
2176 struct i40e_asq_cmd_details
*cmd_details
)
2178 struct i40e_aq_desc desc
;
2179 struct i40e_aqc_add_udp_tunnel
*cmd
=
2180 (struct i40e_aqc_add_udp_tunnel
*)&desc
.params
.raw
;
2181 struct i40e_aqc_del_udp_tunnel_completion
*resp
=
2182 (struct i40e_aqc_del_udp_tunnel_completion
*)&desc
.params
.raw
;
2185 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_add_udp_tunnel
);
2187 cmd
->udp_port
= cpu_to_le16(udp_port
);
2188 cmd
->protocol_type
= protocol_index
;
2190 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2193 *filter_index
= resp
->index
;
2199 * i40e_aq_del_udp_tunnel
2200 * @hw: pointer to the hw struct
2201 * @index: filter index
2202 * @cmd_details: pointer to command details structure or NULL
2204 i40e_status
i40e_aq_del_udp_tunnel(struct i40e_hw
*hw
, u8 index
,
2205 struct i40e_asq_cmd_details
*cmd_details
)
2207 struct i40e_aq_desc desc
;
2208 struct i40e_aqc_remove_udp_tunnel
*cmd
=
2209 (struct i40e_aqc_remove_udp_tunnel
*)&desc
.params
.raw
;
2212 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_del_udp_tunnel
);
2216 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2222 * i40e_aq_delete_element - Delete switch element
2223 * @hw: pointer to the hw struct
2224 * @seid: the SEID to delete from the switch
2225 * @cmd_details: pointer to command details structure or NULL
2227 * This deletes a switch element from the switch.
2229 i40e_status
i40e_aq_delete_element(struct i40e_hw
*hw
, u16 seid
,
2230 struct i40e_asq_cmd_details
*cmd_details
)
2232 struct i40e_aq_desc desc
;
2233 struct i40e_aqc_switch_seid
*cmd
=
2234 (struct i40e_aqc_switch_seid
*)&desc
.params
.raw
;
2238 return I40E_ERR_PARAM
;
2240 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_delete_element
);
2242 cmd
->seid
= cpu_to_le16(seid
);
2244 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2250 * i40e_aq_dcb_updated - DCB Updated Command
2251 * @hw: pointer to the hw struct
2252 * @cmd_details: pointer to command details structure or NULL
2254 * EMP will return when the shared RPB settings have been
2255 * recomputed and modified. The retval field in the descriptor
2256 * will be set to 0 when RPB is modified.
2258 i40e_status
i40e_aq_dcb_updated(struct i40e_hw
*hw
,
2259 struct i40e_asq_cmd_details
*cmd_details
)
2261 struct i40e_aq_desc desc
;
2264 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_dcb_updated
);
2266 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2272 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2273 * @hw: pointer to the hw struct
2274 * @seid: seid for the physical port/switching component/vsi
2275 * @buff: Indirect buffer to hold data parameters and response
2276 * @buff_size: Indirect buffer size
2277 * @opcode: Tx scheduler AQ command opcode
2278 * @cmd_details: pointer to command details structure or NULL
2280 * Generic command handler for Tx scheduler AQ commands
2282 static i40e_status
i40e_aq_tx_sched_cmd(struct i40e_hw
*hw
, u16 seid
,
2283 void *buff
, u16 buff_size
,
2284 enum i40e_admin_queue_opc opcode
,
2285 struct i40e_asq_cmd_details
*cmd_details
)
2287 struct i40e_aq_desc desc
;
2288 struct i40e_aqc_tx_sched_ind
*cmd
=
2289 (struct i40e_aqc_tx_sched_ind
*)&desc
.params
.raw
;
2291 bool cmd_param_flag
= false;
2294 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit
:
2295 case i40e_aqc_opc_configure_vsi_tc_bw
:
2296 case i40e_aqc_opc_enable_switching_comp_ets
:
2297 case i40e_aqc_opc_modify_switching_comp_ets
:
2298 case i40e_aqc_opc_disable_switching_comp_ets
:
2299 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit
:
2300 case i40e_aqc_opc_configure_switching_comp_bw_config
:
2301 cmd_param_flag
= true;
2303 case i40e_aqc_opc_query_vsi_bw_config
:
2304 case i40e_aqc_opc_query_vsi_ets_sla_config
:
2305 case i40e_aqc_opc_query_switching_comp_ets_config
:
2306 case i40e_aqc_opc_query_port_ets_config
:
2307 case i40e_aqc_opc_query_switching_comp_bw_config
:
2308 cmd_param_flag
= false;
2311 return I40E_ERR_PARAM
;
2314 i40e_fill_default_direct_cmd_desc(&desc
, opcode
);
2316 /* Indirect command */
2317 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2319 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_RD
);
2320 if (buff_size
> I40E_AQ_LARGE_BUF
)
2321 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2323 desc
.datalen
= cpu_to_le16(buff_size
);
2325 cmd
->vsi_seid
= cpu_to_le16(seid
);
2327 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
2333 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
2334 * @hw: pointer to the hw struct
2336 * @credit: BW limit credits (0 = disabled)
2337 * @max_credit: Max BW limit credits
2338 * @cmd_details: pointer to command details structure or NULL
2340 i40e_status
i40e_aq_config_vsi_bw_limit(struct i40e_hw
*hw
,
2341 u16 seid
, u16 credit
, u8 max_credit
,
2342 struct i40e_asq_cmd_details
*cmd_details
)
2344 struct i40e_aq_desc desc
;
2345 struct i40e_aqc_configure_vsi_bw_limit
*cmd
=
2346 (struct i40e_aqc_configure_vsi_bw_limit
*)&desc
.params
.raw
;
2349 i40e_fill_default_direct_cmd_desc(&desc
,
2350 i40e_aqc_opc_configure_vsi_bw_limit
);
2352 cmd
->vsi_seid
= cpu_to_le16(seid
);
2353 cmd
->credit
= cpu_to_le16(credit
);
2354 cmd
->max_credit
= max_credit
;
2356 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2362 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
2363 * @hw: pointer to the hw struct
2365 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
2366 * @cmd_details: pointer to command details structure or NULL
2368 i40e_status
i40e_aq_config_vsi_tc_bw(struct i40e_hw
*hw
,
2370 struct i40e_aqc_configure_vsi_tc_bw_data
*bw_data
,
2371 struct i40e_asq_cmd_details
*cmd_details
)
2373 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2374 i40e_aqc_opc_configure_vsi_tc_bw
,
2379 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
2380 * @hw: pointer to the hw struct
2381 * @seid: seid of the switching component connected to Physical Port
2382 * @ets_data: Buffer holding ETS parameters
2383 * @cmd_details: pointer to command details structure or NULL
2385 i40e_status
i40e_aq_config_switch_comp_ets(struct i40e_hw
*hw
,
2387 struct i40e_aqc_configure_switching_comp_ets_data
*ets_data
,
2388 enum i40e_admin_queue_opc opcode
,
2389 struct i40e_asq_cmd_details
*cmd_details
)
2391 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)ets_data
,
2392 sizeof(*ets_data
), opcode
, cmd_details
);
2396 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
2397 * @hw: pointer to the hw struct
2398 * @seid: seid of the switching component
2399 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
2400 * @cmd_details: pointer to command details structure or NULL
2402 i40e_status
i40e_aq_config_switch_comp_bw_config(struct i40e_hw
*hw
,
2404 struct i40e_aqc_configure_switching_comp_bw_config_data
*bw_data
,
2405 struct i40e_asq_cmd_details
*cmd_details
)
2407 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2408 i40e_aqc_opc_configure_switching_comp_bw_config
,
2413 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
2414 * @hw: pointer to the hw struct
2415 * @seid: seid of the VSI
2416 * @bw_data: Buffer to hold VSI BW configuration
2417 * @cmd_details: pointer to command details structure or NULL
2419 i40e_status
i40e_aq_query_vsi_bw_config(struct i40e_hw
*hw
,
2421 struct i40e_aqc_query_vsi_bw_config_resp
*bw_data
,
2422 struct i40e_asq_cmd_details
*cmd_details
)
2424 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2425 i40e_aqc_opc_query_vsi_bw_config
,
2430 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
2431 * @hw: pointer to the hw struct
2432 * @seid: seid of the VSI
2433 * @bw_data: Buffer to hold VSI BW configuration per TC
2434 * @cmd_details: pointer to command details structure or NULL
2436 i40e_status
i40e_aq_query_vsi_ets_sla_config(struct i40e_hw
*hw
,
2438 struct i40e_aqc_query_vsi_ets_sla_config_resp
*bw_data
,
2439 struct i40e_asq_cmd_details
*cmd_details
)
2441 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2442 i40e_aqc_opc_query_vsi_ets_sla_config
,
2447 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
2448 * @hw: pointer to the hw struct
2449 * @seid: seid of the switching component
2450 * @bw_data: Buffer to hold switching component's per TC BW config
2451 * @cmd_details: pointer to command details structure or NULL
2453 i40e_status
i40e_aq_query_switch_comp_ets_config(struct i40e_hw
*hw
,
2455 struct i40e_aqc_query_switching_comp_ets_config_resp
*bw_data
,
2456 struct i40e_asq_cmd_details
*cmd_details
)
2458 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2459 i40e_aqc_opc_query_switching_comp_ets_config
,
2464 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
2465 * @hw: pointer to the hw struct
2466 * @seid: seid of the VSI or switching component connected to Physical Port
2467 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
2468 * @cmd_details: pointer to command details structure or NULL
2470 i40e_status
i40e_aq_query_port_ets_config(struct i40e_hw
*hw
,
2472 struct i40e_aqc_query_port_ets_config_resp
*bw_data
,
2473 struct i40e_asq_cmd_details
*cmd_details
)
2475 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2476 i40e_aqc_opc_query_port_ets_config
,
2481 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
2482 * @hw: pointer to the hw struct
2483 * @seid: seid of the switching component
2484 * @bw_data: Buffer to hold switching component's BW configuration
2485 * @cmd_details: pointer to command details structure or NULL
2487 i40e_status
i40e_aq_query_switch_comp_bw_config(struct i40e_hw
*hw
,
2489 struct i40e_aqc_query_switching_comp_bw_config_resp
*bw_data
,
2490 struct i40e_asq_cmd_details
*cmd_details
)
2492 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2493 i40e_aqc_opc_query_switching_comp_bw_config
,
2498 * i40e_validate_filter_settings
2499 * @hw: pointer to the hardware structure
2500 * @settings: Filter control settings
2502 * Check and validate the filter control settings passed.
2503 * The function checks for the valid filter/context sizes being
2504 * passed for FCoE and PE.
2506 * Returns 0 if the values passed are valid and within
2507 * range else returns an error.
2509 static i40e_status
i40e_validate_filter_settings(struct i40e_hw
*hw
,
2510 struct i40e_filter_control_settings
*settings
)
2512 u32 fcoe_cntx_size
, fcoe_filt_size
;
2513 u32 pe_cntx_size
, pe_filt_size
;
2517 /* Validate FCoE settings passed */
2518 switch (settings
->fcoe_filt_num
) {
2519 case I40E_HASH_FILTER_SIZE_1K
:
2520 case I40E_HASH_FILTER_SIZE_2K
:
2521 case I40E_HASH_FILTER_SIZE_4K
:
2522 case I40E_HASH_FILTER_SIZE_8K
:
2523 case I40E_HASH_FILTER_SIZE_16K
:
2524 case I40E_HASH_FILTER_SIZE_32K
:
2525 fcoe_filt_size
= I40E_HASH_FILTER_BASE_SIZE
;
2526 fcoe_filt_size
<<= (u32
)settings
->fcoe_filt_num
;
2529 return I40E_ERR_PARAM
;
2532 switch (settings
->fcoe_cntx_num
) {
2533 case I40E_DMA_CNTX_SIZE_512
:
2534 case I40E_DMA_CNTX_SIZE_1K
:
2535 case I40E_DMA_CNTX_SIZE_2K
:
2536 case I40E_DMA_CNTX_SIZE_4K
:
2537 fcoe_cntx_size
= I40E_DMA_CNTX_BASE_SIZE
;
2538 fcoe_cntx_size
<<= (u32
)settings
->fcoe_cntx_num
;
2541 return I40E_ERR_PARAM
;
2544 /* Validate PE settings passed */
2545 switch (settings
->pe_filt_num
) {
2546 case I40E_HASH_FILTER_SIZE_1K
:
2547 case I40E_HASH_FILTER_SIZE_2K
:
2548 case I40E_HASH_FILTER_SIZE_4K
:
2549 case I40E_HASH_FILTER_SIZE_8K
:
2550 case I40E_HASH_FILTER_SIZE_16K
:
2551 case I40E_HASH_FILTER_SIZE_32K
:
2552 case I40E_HASH_FILTER_SIZE_64K
:
2553 case I40E_HASH_FILTER_SIZE_128K
:
2554 case I40E_HASH_FILTER_SIZE_256K
:
2555 case I40E_HASH_FILTER_SIZE_512K
:
2556 case I40E_HASH_FILTER_SIZE_1M
:
2557 pe_filt_size
= I40E_HASH_FILTER_BASE_SIZE
;
2558 pe_filt_size
<<= (u32
)settings
->pe_filt_num
;
2561 return I40E_ERR_PARAM
;
2564 switch (settings
->pe_cntx_num
) {
2565 case I40E_DMA_CNTX_SIZE_512
:
2566 case I40E_DMA_CNTX_SIZE_1K
:
2567 case I40E_DMA_CNTX_SIZE_2K
:
2568 case I40E_DMA_CNTX_SIZE_4K
:
2569 case I40E_DMA_CNTX_SIZE_8K
:
2570 case I40E_DMA_CNTX_SIZE_16K
:
2571 case I40E_DMA_CNTX_SIZE_32K
:
2572 case I40E_DMA_CNTX_SIZE_64K
:
2573 case I40E_DMA_CNTX_SIZE_128K
:
2574 case I40E_DMA_CNTX_SIZE_256K
:
2575 pe_cntx_size
= I40E_DMA_CNTX_BASE_SIZE
;
2576 pe_cntx_size
<<= (u32
)settings
->pe_cntx_num
;
2579 return I40E_ERR_PARAM
;
2582 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
2583 val
= rd32(hw
, I40E_GLHMC_FCOEFMAX
);
2584 fcoe_fmax
= (val
& I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK
)
2585 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT
;
2586 if (fcoe_filt_size
+ fcoe_cntx_size
> fcoe_fmax
)
2587 return I40E_ERR_INVALID_SIZE
;
2593 * i40e_set_filter_control
2594 * @hw: pointer to the hardware structure
2595 * @settings: Filter control settings
2597 * Set the Queue Filters for PE/FCoE and enable filters required
2598 * for a single PF. It is expected that these settings are programmed
2599 * at the driver initialization time.
2601 i40e_status
i40e_set_filter_control(struct i40e_hw
*hw
,
2602 struct i40e_filter_control_settings
*settings
)
2604 i40e_status ret
= 0;
2605 u32 hash_lut_size
= 0;
2609 return I40E_ERR_PARAM
;
2611 /* Validate the input settings */
2612 ret
= i40e_validate_filter_settings(hw
, settings
);
2616 /* Read the PF Queue Filter control register */
2617 val
= rd32(hw
, I40E_PFQF_CTL_0
);
2619 /* Program required PE hash buckets for the PF */
2620 val
&= ~I40E_PFQF_CTL_0_PEHSIZE_MASK
;
2621 val
|= ((u32
)settings
->pe_filt_num
<< I40E_PFQF_CTL_0_PEHSIZE_SHIFT
) &
2622 I40E_PFQF_CTL_0_PEHSIZE_MASK
;
2623 /* Program required PE contexts for the PF */
2624 val
&= ~I40E_PFQF_CTL_0_PEDSIZE_MASK
;
2625 val
|= ((u32
)settings
->pe_cntx_num
<< I40E_PFQF_CTL_0_PEDSIZE_SHIFT
) &
2626 I40E_PFQF_CTL_0_PEDSIZE_MASK
;
2628 /* Program required FCoE hash buckets for the PF */
2629 val
&= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK
;
2630 val
|= ((u32
)settings
->fcoe_filt_num
<<
2631 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT
) &
2632 I40E_PFQF_CTL_0_PFFCHSIZE_MASK
;
2633 /* Program required FCoE DDP contexts for the PF */
2634 val
&= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK
;
2635 val
|= ((u32
)settings
->fcoe_cntx_num
<<
2636 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT
) &
2637 I40E_PFQF_CTL_0_PFFCDSIZE_MASK
;
2639 /* Program Hash LUT size for the PF */
2640 val
&= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK
;
2641 if (settings
->hash_lut_size
== I40E_HASH_LUT_SIZE_512
)
2643 val
|= (hash_lut_size
<< I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT
) &
2644 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK
;
2646 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
2647 if (settings
->enable_fdir
)
2648 val
|= I40E_PFQF_CTL_0_FD_ENA_MASK
;
2649 if (settings
->enable_ethtype
)
2650 val
|= I40E_PFQF_CTL_0_ETYPE_ENA_MASK
;
2651 if (settings
->enable_macvlan
)
2652 val
|= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK
;
2654 wr32(hw
, I40E_PFQF_CTL_0
, val
);
2660 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
2661 * @hw: pointer to the hw struct
2662 * @mac_addr: MAC address to use in the filter
2663 * @ethtype: Ethertype to use in the filter
2664 * @flags: Flags that needs to be applied to the filter
2665 * @vsi_seid: seid of the control VSI
2666 * @queue: VSI queue number to send the packet to
2667 * @is_add: Add control packet filter if True else remove
2668 * @stats: Structure to hold information on control filter counts
2669 * @cmd_details: pointer to command details structure or NULL
2671 * This command will Add or Remove control packet filter for a control VSI.
2672 * In return it will update the total number of perfect filter count in
2675 i40e_status
i40e_aq_add_rem_control_packet_filter(struct i40e_hw
*hw
,
2676 u8
*mac_addr
, u16 ethtype
, u16 flags
,
2677 u16 vsi_seid
, u16 queue
, bool is_add
,
2678 struct i40e_control_filter_stats
*stats
,
2679 struct i40e_asq_cmd_details
*cmd_details
)
2681 struct i40e_aq_desc desc
;
2682 struct i40e_aqc_add_remove_control_packet_filter
*cmd
=
2683 (struct i40e_aqc_add_remove_control_packet_filter
*)
2685 struct i40e_aqc_add_remove_control_packet_filter_completion
*resp
=
2686 (struct i40e_aqc_add_remove_control_packet_filter_completion
*)
2691 return I40E_ERR_PARAM
;
2694 i40e_fill_default_direct_cmd_desc(&desc
,
2695 i40e_aqc_opc_add_control_packet_filter
);
2696 cmd
->queue
= cpu_to_le16(queue
);
2698 i40e_fill_default_direct_cmd_desc(&desc
,
2699 i40e_aqc_opc_remove_control_packet_filter
);
2703 memcpy(cmd
->mac
, mac_addr
, ETH_ALEN
);
2705 cmd
->etype
= cpu_to_le16(ethtype
);
2706 cmd
->flags
= cpu_to_le16(flags
);
2707 cmd
->seid
= cpu_to_le16(vsi_seid
);
2709 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2711 if (!status
&& stats
) {
2712 stats
->mac_etype_used
= le16_to_cpu(resp
->mac_etype_used
);
2713 stats
->etype_used
= le16_to_cpu(resp
->etype_used
);
2714 stats
->mac_etype_free
= le16_to_cpu(resp
->mac_etype_free
);
2715 stats
->etype_free
= le16_to_cpu(resp
->etype_free
);
2722 * i40e_set_pci_config_data - store PCI bus info
2723 * @hw: pointer to hardware structure
2724 * @link_status: the link status word from PCI config space
2726 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
2728 void i40e_set_pci_config_data(struct i40e_hw
*hw
, u16 link_status
)
2730 hw
->bus
.type
= i40e_bus_type_pci_express
;
2732 switch (link_status
& PCI_EXP_LNKSTA_NLW
) {
2733 case PCI_EXP_LNKSTA_NLW_X1
:
2734 hw
->bus
.width
= i40e_bus_width_pcie_x1
;
2736 case PCI_EXP_LNKSTA_NLW_X2
:
2737 hw
->bus
.width
= i40e_bus_width_pcie_x2
;
2739 case PCI_EXP_LNKSTA_NLW_X4
:
2740 hw
->bus
.width
= i40e_bus_width_pcie_x4
;
2742 case PCI_EXP_LNKSTA_NLW_X8
:
2743 hw
->bus
.width
= i40e_bus_width_pcie_x8
;
2746 hw
->bus
.width
= i40e_bus_width_unknown
;
2750 switch (link_status
& PCI_EXP_LNKSTA_CLS
) {
2751 case PCI_EXP_LNKSTA_CLS_2_5GB
:
2752 hw
->bus
.speed
= i40e_bus_speed_2500
;
2754 case PCI_EXP_LNKSTA_CLS_5_0GB
:
2755 hw
->bus
.speed
= i40e_bus_speed_5000
;
2757 case PCI_EXP_LNKSTA_CLS_8_0GB
:
2758 hw
->bus
.speed
= i40e_bus_speed_8000
;
2761 hw
->bus
.speed
= i40e_bus_speed_unknown
;