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Merge tag 'batman-adv-for-davem' of git://git.open-mesh.org/linux-merge
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
31
32 /**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40 {
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
45 case I40E_DEV_ID_SFP_XL710:
46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_B:
48 case I40E_DEV_ID_KX_C:
49 case I40E_DEV_ID_QSFP_A:
50 case I40E_DEV_ID_QSFP_B:
51 case I40E_DEV_ID_QSFP_C:
52 case I40E_DEV_ID_10G_BASE_T:
53 case I40E_DEV_ID_10G_BASE_T4:
54 case I40E_DEV_ID_20G_KR2:
55 case I40E_DEV_ID_20G_KR2_A:
56 hw->mac.type = I40E_MAC_XL710;
57 break;
58 case I40E_DEV_ID_KX_X722:
59 case I40E_DEV_ID_QSFP_X722:
60 case I40E_DEV_ID_SFP_X722:
61 case I40E_DEV_ID_1G_BASE_T_X722:
62 case I40E_DEV_ID_10G_BASE_T_X722:
63 hw->mac.type = I40E_MAC_X722;
64 break;
65 case I40E_DEV_ID_X722_VF:
66 case I40E_DEV_ID_X722_VF_HV:
67 hw->mac.type = I40E_MAC_X722_VF;
68 break;
69 case I40E_DEV_ID_VF:
70 case I40E_DEV_ID_VF_HV:
71 hw->mac.type = I40E_MAC_VF;
72 break;
73 default:
74 hw->mac.type = I40E_MAC_GENERIC;
75 break;
76 }
77 } else {
78 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
79 }
80
81 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
82 hw->mac.type, status);
83 return status;
84 }
85
86 /**
87 * i40e_aq_str - convert AQ err code to a string
88 * @hw: pointer to the HW structure
89 * @aq_err: the AQ error code to convert
90 **/
91 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
92 {
93 switch (aq_err) {
94 case I40E_AQ_RC_OK:
95 return "OK";
96 case I40E_AQ_RC_EPERM:
97 return "I40E_AQ_RC_EPERM";
98 case I40E_AQ_RC_ENOENT:
99 return "I40E_AQ_RC_ENOENT";
100 case I40E_AQ_RC_ESRCH:
101 return "I40E_AQ_RC_ESRCH";
102 case I40E_AQ_RC_EINTR:
103 return "I40E_AQ_RC_EINTR";
104 case I40E_AQ_RC_EIO:
105 return "I40E_AQ_RC_EIO";
106 case I40E_AQ_RC_ENXIO:
107 return "I40E_AQ_RC_ENXIO";
108 case I40E_AQ_RC_E2BIG:
109 return "I40E_AQ_RC_E2BIG";
110 case I40E_AQ_RC_EAGAIN:
111 return "I40E_AQ_RC_EAGAIN";
112 case I40E_AQ_RC_ENOMEM:
113 return "I40E_AQ_RC_ENOMEM";
114 case I40E_AQ_RC_EACCES:
115 return "I40E_AQ_RC_EACCES";
116 case I40E_AQ_RC_EFAULT:
117 return "I40E_AQ_RC_EFAULT";
118 case I40E_AQ_RC_EBUSY:
119 return "I40E_AQ_RC_EBUSY";
120 case I40E_AQ_RC_EEXIST:
121 return "I40E_AQ_RC_EEXIST";
122 case I40E_AQ_RC_EINVAL:
123 return "I40E_AQ_RC_EINVAL";
124 case I40E_AQ_RC_ENOTTY:
125 return "I40E_AQ_RC_ENOTTY";
126 case I40E_AQ_RC_ENOSPC:
127 return "I40E_AQ_RC_ENOSPC";
128 case I40E_AQ_RC_ENOSYS:
129 return "I40E_AQ_RC_ENOSYS";
130 case I40E_AQ_RC_ERANGE:
131 return "I40E_AQ_RC_ERANGE";
132 case I40E_AQ_RC_EFLUSHED:
133 return "I40E_AQ_RC_EFLUSHED";
134 case I40E_AQ_RC_BAD_ADDR:
135 return "I40E_AQ_RC_BAD_ADDR";
136 case I40E_AQ_RC_EMODE:
137 return "I40E_AQ_RC_EMODE";
138 case I40E_AQ_RC_EFBIG:
139 return "I40E_AQ_RC_EFBIG";
140 }
141
142 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
143 return hw->err_str;
144 }
145
146 /**
147 * i40e_stat_str - convert status err code to a string
148 * @hw: pointer to the HW structure
149 * @stat_err: the status error code to convert
150 **/
151 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
152 {
153 switch (stat_err) {
154 case 0:
155 return "OK";
156 case I40E_ERR_NVM:
157 return "I40E_ERR_NVM";
158 case I40E_ERR_NVM_CHECKSUM:
159 return "I40E_ERR_NVM_CHECKSUM";
160 case I40E_ERR_PHY:
161 return "I40E_ERR_PHY";
162 case I40E_ERR_CONFIG:
163 return "I40E_ERR_CONFIG";
164 case I40E_ERR_PARAM:
165 return "I40E_ERR_PARAM";
166 case I40E_ERR_MAC_TYPE:
167 return "I40E_ERR_MAC_TYPE";
168 case I40E_ERR_UNKNOWN_PHY:
169 return "I40E_ERR_UNKNOWN_PHY";
170 case I40E_ERR_LINK_SETUP:
171 return "I40E_ERR_LINK_SETUP";
172 case I40E_ERR_ADAPTER_STOPPED:
173 return "I40E_ERR_ADAPTER_STOPPED";
174 case I40E_ERR_INVALID_MAC_ADDR:
175 return "I40E_ERR_INVALID_MAC_ADDR";
176 case I40E_ERR_DEVICE_NOT_SUPPORTED:
177 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
178 case I40E_ERR_MASTER_REQUESTS_PENDING:
179 return "I40E_ERR_MASTER_REQUESTS_PENDING";
180 case I40E_ERR_INVALID_LINK_SETTINGS:
181 return "I40E_ERR_INVALID_LINK_SETTINGS";
182 case I40E_ERR_AUTONEG_NOT_COMPLETE:
183 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
184 case I40E_ERR_RESET_FAILED:
185 return "I40E_ERR_RESET_FAILED";
186 case I40E_ERR_SWFW_SYNC:
187 return "I40E_ERR_SWFW_SYNC";
188 case I40E_ERR_NO_AVAILABLE_VSI:
189 return "I40E_ERR_NO_AVAILABLE_VSI";
190 case I40E_ERR_NO_MEMORY:
191 return "I40E_ERR_NO_MEMORY";
192 case I40E_ERR_BAD_PTR:
193 return "I40E_ERR_BAD_PTR";
194 case I40E_ERR_RING_FULL:
195 return "I40E_ERR_RING_FULL";
196 case I40E_ERR_INVALID_PD_ID:
197 return "I40E_ERR_INVALID_PD_ID";
198 case I40E_ERR_INVALID_QP_ID:
199 return "I40E_ERR_INVALID_QP_ID";
200 case I40E_ERR_INVALID_CQ_ID:
201 return "I40E_ERR_INVALID_CQ_ID";
202 case I40E_ERR_INVALID_CEQ_ID:
203 return "I40E_ERR_INVALID_CEQ_ID";
204 case I40E_ERR_INVALID_AEQ_ID:
205 return "I40E_ERR_INVALID_AEQ_ID";
206 case I40E_ERR_INVALID_SIZE:
207 return "I40E_ERR_INVALID_SIZE";
208 case I40E_ERR_INVALID_ARP_INDEX:
209 return "I40E_ERR_INVALID_ARP_INDEX";
210 case I40E_ERR_INVALID_FPM_FUNC_ID:
211 return "I40E_ERR_INVALID_FPM_FUNC_ID";
212 case I40E_ERR_QP_INVALID_MSG_SIZE:
213 return "I40E_ERR_QP_INVALID_MSG_SIZE";
214 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
215 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
216 case I40E_ERR_INVALID_FRAG_COUNT:
217 return "I40E_ERR_INVALID_FRAG_COUNT";
218 case I40E_ERR_QUEUE_EMPTY:
219 return "I40E_ERR_QUEUE_EMPTY";
220 case I40E_ERR_INVALID_ALIGNMENT:
221 return "I40E_ERR_INVALID_ALIGNMENT";
222 case I40E_ERR_FLUSHED_QUEUE:
223 return "I40E_ERR_FLUSHED_QUEUE";
224 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
225 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
226 case I40E_ERR_INVALID_IMM_DATA_SIZE:
227 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
228 case I40E_ERR_TIMEOUT:
229 return "I40E_ERR_TIMEOUT";
230 case I40E_ERR_OPCODE_MISMATCH:
231 return "I40E_ERR_OPCODE_MISMATCH";
232 case I40E_ERR_CQP_COMPL_ERROR:
233 return "I40E_ERR_CQP_COMPL_ERROR";
234 case I40E_ERR_INVALID_VF_ID:
235 return "I40E_ERR_INVALID_VF_ID";
236 case I40E_ERR_INVALID_HMCFN_ID:
237 return "I40E_ERR_INVALID_HMCFN_ID";
238 case I40E_ERR_BACKING_PAGE_ERROR:
239 return "I40E_ERR_BACKING_PAGE_ERROR";
240 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
241 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
242 case I40E_ERR_INVALID_PBLE_INDEX:
243 return "I40E_ERR_INVALID_PBLE_INDEX";
244 case I40E_ERR_INVALID_SD_INDEX:
245 return "I40E_ERR_INVALID_SD_INDEX";
246 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
247 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
248 case I40E_ERR_INVALID_SD_TYPE:
249 return "I40E_ERR_INVALID_SD_TYPE";
250 case I40E_ERR_MEMCPY_FAILED:
251 return "I40E_ERR_MEMCPY_FAILED";
252 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
253 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
254 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
255 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
256 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
257 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
258 case I40E_ERR_SRQ_ENABLED:
259 return "I40E_ERR_SRQ_ENABLED";
260 case I40E_ERR_ADMIN_QUEUE_ERROR:
261 return "I40E_ERR_ADMIN_QUEUE_ERROR";
262 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
263 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
264 case I40E_ERR_BUF_TOO_SHORT:
265 return "I40E_ERR_BUF_TOO_SHORT";
266 case I40E_ERR_ADMIN_QUEUE_FULL:
267 return "I40E_ERR_ADMIN_QUEUE_FULL";
268 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
269 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
270 case I40E_ERR_BAD_IWARP_CQE:
271 return "I40E_ERR_BAD_IWARP_CQE";
272 case I40E_ERR_NVM_BLANK_MODE:
273 return "I40E_ERR_NVM_BLANK_MODE";
274 case I40E_ERR_NOT_IMPLEMENTED:
275 return "I40E_ERR_NOT_IMPLEMENTED";
276 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
277 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
278 case I40E_ERR_DIAG_TEST_FAILED:
279 return "I40E_ERR_DIAG_TEST_FAILED";
280 case I40E_ERR_NOT_READY:
281 return "I40E_ERR_NOT_READY";
282 case I40E_NOT_SUPPORTED:
283 return "I40E_NOT_SUPPORTED";
284 case I40E_ERR_FIRMWARE_API_VERSION:
285 return "I40E_ERR_FIRMWARE_API_VERSION";
286 }
287
288 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
289 return hw->err_str;
290 }
291
292 /**
293 * i40e_debug_aq
294 * @hw: debug mask related to admin queue
295 * @mask: debug mask
296 * @desc: pointer to admin queue descriptor
297 * @buffer: pointer to command buffer
298 * @buf_len: max length of buffer
299 *
300 * Dumps debug log about adminq command with descriptor contents.
301 **/
302 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
303 void *buffer, u16 buf_len)
304 {
305 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
306 u16 len = le16_to_cpu(aq_desc->datalen);
307 u8 *buf = (u8 *)buffer;
308 u16 i = 0;
309
310 if ((!(mask & hw->debug_mask)) || (desc == NULL))
311 return;
312
313 i40e_debug(hw, mask,
314 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
315 le16_to_cpu(aq_desc->opcode),
316 le16_to_cpu(aq_desc->flags),
317 le16_to_cpu(aq_desc->datalen),
318 le16_to_cpu(aq_desc->retval));
319 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
320 le32_to_cpu(aq_desc->cookie_high),
321 le32_to_cpu(aq_desc->cookie_low));
322 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
323 le32_to_cpu(aq_desc->params.internal.param0),
324 le32_to_cpu(aq_desc->params.internal.param1));
325 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
326 le32_to_cpu(aq_desc->params.external.addr_high),
327 le32_to_cpu(aq_desc->params.external.addr_low));
328
329 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
330 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
331 if (buf_len < len)
332 len = buf_len;
333 /* write the full 16-byte chunks */
334 for (i = 0; i < (len - 16); i += 16)
335 i40e_debug(hw, mask, "\t0x%04X %16ph\n", i, buf + i);
336 /* write whatever's left over without overrunning the buffer */
337 if (i < len)
338 i40e_debug(hw, mask, "\t0x%04X %*ph\n",
339 i, len - i, buf + i);
340 }
341 }
342
343 /**
344 * i40e_check_asq_alive
345 * @hw: pointer to the hw struct
346 *
347 * Returns true if Queue is enabled else false.
348 **/
349 bool i40e_check_asq_alive(struct i40e_hw *hw)
350 {
351 if (hw->aq.asq.len)
352 return !!(rd32(hw, hw->aq.asq.len) &
353 I40E_PF_ATQLEN_ATQENABLE_MASK);
354 else
355 return false;
356 }
357
358 /**
359 * i40e_aq_queue_shutdown
360 * @hw: pointer to the hw struct
361 * @unloading: is the driver unloading itself
362 *
363 * Tell the Firmware that we're shutting down the AdminQ and whether
364 * or not the driver is unloading as well.
365 **/
366 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
367 bool unloading)
368 {
369 struct i40e_aq_desc desc;
370 struct i40e_aqc_queue_shutdown *cmd =
371 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
372 i40e_status status;
373
374 i40e_fill_default_direct_cmd_desc(&desc,
375 i40e_aqc_opc_queue_shutdown);
376
377 if (unloading)
378 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
379 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
380
381 return status;
382 }
383
384 /**
385 * i40e_aq_get_set_rss_lut
386 * @hw: pointer to the hardware structure
387 * @vsi_id: vsi fw index
388 * @pf_lut: for PF table set true, for VSI table set false
389 * @lut: pointer to the lut buffer provided by the caller
390 * @lut_size: size of the lut buffer
391 * @set: set true to set the table, false to get the table
392 *
393 * Internal function to get or set RSS look up table
394 **/
395 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
396 u16 vsi_id, bool pf_lut,
397 u8 *lut, u16 lut_size,
398 bool set)
399 {
400 i40e_status status;
401 struct i40e_aq_desc desc;
402 struct i40e_aqc_get_set_rss_lut *cmd_resp =
403 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
404
405 if (set)
406 i40e_fill_default_direct_cmd_desc(&desc,
407 i40e_aqc_opc_set_rss_lut);
408 else
409 i40e_fill_default_direct_cmd_desc(&desc,
410 i40e_aqc_opc_get_rss_lut);
411
412 /* Indirect command */
413 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
414 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
415
416 cmd_resp->vsi_id =
417 cpu_to_le16((u16)((vsi_id <<
418 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
419 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
420 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
421
422 if (pf_lut)
423 cmd_resp->flags |= cpu_to_le16((u16)
424 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
425 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
426 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
427 else
428 cmd_resp->flags |= cpu_to_le16((u16)
429 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
430 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
431 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
432
433 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
434
435 return status;
436 }
437
438 /**
439 * i40e_aq_get_rss_lut
440 * @hw: pointer to the hardware structure
441 * @vsi_id: vsi fw index
442 * @pf_lut: for PF table set true, for VSI table set false
443 * @lut: pointer to the lut buffer provided by the caller
444 * @lut_size: size of the lut buffer
445 *
446 * get the RSS lookup table, PF or VSI type
447 **/
448 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
449 bool pf_lut, u8 *lut, u16 lut_size)
450 {
451 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
452 false);
453 }
454
455 /**
456 * i40e_aq_set_rss_lut
457 * @hw: pointer to the hardware structure
458 * @vsi_id: vsi fw index
459 * @pf_lut: for PF table set true, for VSI table set false
460 * @lut: pointer to the lut buffer provided by the caller
461 * @lut_size: size of the lut buffer
462 *
463 * set the RSS lookup table, PF or VSI type
464 **/
465 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
466 bool pf_lut, u8 *lut, u16 lut_size)
467 {
468 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
469 }
470
471 /**
472 * i40e_aq_get_set_rss_key
473 * @hw: pointer to the hw struct
474 * @vsi_id: vsi fw index
475 * @key: pointer to key info struct
476 * @set: set true to set the key, false to get the key
477 *
478 * get the RSS key per VSI
479 **/
480 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
481 u16 vsi_id,
482 struct i40e_aqc_get_set_rss_key_data *key,
483 bool set)
484 {
485 i40e_status status;
486 struct i40e_aq_desc desc;
487 struct i40e_aqc_get_set_rss_key *cmd_resp =
488 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
489 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
490
491 if (set)
492 i40e_fill_default_direct_cmd_desc(&desc,
493 i40e_aqc_opc_set_rss_key);
494 else
495 i40e_fill_default_direct_cmd_desc(&desc,
496 i40e_aqc_opc_get_rss_key);
497
498 /* Indirect command */
499 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
500 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
501
502 cmd_resp->vsi_id =
503 cpu_to_le16((u16)((vsi_id <<
504 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
505 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
506 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
507
508 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
509
510 return status;
511 }
512
513 /**
514 * i40e_aq_get_rss_key
515 * @hw: pointer to the hw struct
516 * @vsi_id: vsi fw index
517 * @key: pointer to key info struct
518 *
519 **/
520 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
521 u16 vsi_id,
522 struct i40e_aqc_get_set_rss_key_data *key)
523 {
524 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
525 }
526
527 /**
528 * i40e_aq_set_rss_key
529 * @hw: pointer to the hw struct
530 * @vsi_id: vsi fw index
531 * @key: pointer to key info struct
532 *
533 * set the RSS key per VSI
534 **/
535 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
536 u16 vsi_id,
537 struct i40e_aqc_get_set_rss_key_data *key)
538 {
539 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
540 }
541
542 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
543 * hardware to a bit-field that can be used by SW to more easily determine the
544 * packet type.
545 *
546 * Macros are used to shorten the table lines and make this table human
547 * readable.
548 *
549 * We store the PTYPE in the top byte of the bit field - this is just so that
550 * we can check that the table doesn't have a row missing, as the index into
551 * the table should be the PTYPE.
552 *
553 * Typical work flow:
554 *
555 * IF NOT i40e_ptype_lookup[ptype].known
556 * THEN
557 * Packet is unknown
558 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
559 * Use the rest of the fields to look at the tunnels, inner protocols, etc
560 * ELSE
561 * Use the enum i40e_rx_l2_ptype to decode the packet type
562 * ENDIF
563 */
564
565 /* macro to make the table lines short */
566 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
567 { PTYPE, \
568 1, \
569 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
570 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
571 I40E_RX_PTYPE_##OUTER_FRAG, \
572 I40E_RX_PTYPE_TUNNEL_##T, \
573 I40E_RX_PTYPE_TUNNEL_END_##TE, \
574 I40E_RX_PTYPE_##TEF, \
575 I40E_RX_PTYPE_INNER_PROT_##I, \
576 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
577
578 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
579 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
580
581 /* shorter macros makes the table fit but are terse */
582 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
583 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
584 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
585
586 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
587 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
588 /* L2 Packet types */
589 I40E_PTT_UNUSED_ENTRY(0),
590 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
591 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
592 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
593 I40E_PTT_UNUSED_ENTRY(4),
594 I40E_PTT_UNUSED_ENTRY(5),
595 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
596 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
597 I40E_PTT_UNUSED_ENTRY(8),
598 I40E_PTT_UNUSED_ENTRY(9),
599 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
600 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
601 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
602 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
603 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
604 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
605 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
606 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
607 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
608 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
609 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
610 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
611
612 /* Non Tunneled IPv4 */
613 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
614 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
615 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
616 I40E_PTT_UNUSED_ENTRY(25),
617 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
618 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
619 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
620
621 /* IPv4 --> IPv4 */
622 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
623 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
624 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
625 I40E_PTT_UNUSED_ENTRY(32),
626 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
627 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
628 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
629
630 /* IPv4 --> IPv6 */
631 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
632 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
633 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
634 I40E_PTT_UNUSED_ENTRY(39),
635 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
636 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
637 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
638
639 /* IPv4 --> GRE/NAT */
640 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
641
642 /* IPv4 --> GRE/NAT --> IPv4 */
643 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
644 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
645 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
646 I40E_PTT_UNUSED_ENTRY(47),
647 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
648 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
649 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
650
651 /* IPv4 --> GRE/NAT --> IPv6 */
652 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
653 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
654 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
655 I40E_PTT_UNUSED_ENTRY(54),
656 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
657 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
658 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
659
660 /* IPv4 --> GRE/NAT --> MAC */
661 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
662
663 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
664 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
665 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
666 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
667 I40E_PTT_UNUSED_ENTRY(62),
668 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
669 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
670 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
671
672 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
673 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
674 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
675 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
676 I40E_PTT_UNUSED_ENTRY(69),
677 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
678 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
679 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
680
681 /* IPv4 --> GRE/NAT --> MAC/VLAN */
682 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
683
684 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
685 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
686 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
687 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
688 I40E_PTT_UNUSED_ENTRY(77),
689 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
690 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
691 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
692
693 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
694 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
695 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
696 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
697 I40E_PTT_UNUSED_ENTRY(84),
698 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
699 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
700 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
701
702 /* Non Tunneled IPv6 */
703 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
704 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
705 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
706 I40E_PTT_UNUSED_ENTRY(91),
707 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
708 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
709 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
710
711 /* IPv6 --> IPv4 */
712 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
713 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
714 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
715 I40E_PTT_UNUSED_ENTRY(98),
716 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
717 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
718 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
719
720 /* IPv6 --> IPv6 */
721 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
722 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
723 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
724 I40E_PTT_UNUSED_ENTRY(105),
725 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
726 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
727 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
728
729 /* IPv6 --> GRE/NAT */
730 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
731
732 /* IPv6 --> GRE/NAT -> IPv4 */
733 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
734 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
735 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
736 I40E_PTT_UNUSED_ENTRY(113),
737 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
738 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
739 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
740
741 /* IPv6 --> GRE/NAT -> IPv6 */
742 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
743 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
744 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
745 I40E_PTT_UNUSED_ENTRY(120),
746 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
747 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
748 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
749
750 /* IPv6 --> GRE/NAT -> MAC */
751 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
752
753 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
754 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
755 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
756 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
757 I40E_PTT_UNUSED_ENTRY(128),
758 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
759 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
760 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
761
762 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
763 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
764 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
765 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
766 I40E_PTT_UNUSED_ENTRY(135),
767 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
768 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
769 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
770
771 /* IPv6 --> GRE/NAT -> MAC/VLAN */
772 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
773
774 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
775 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
776 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
777 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
778 I40E_PTT_UNUSED_ENTRY(143),
779 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
780 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
781 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
782
783 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
784 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
785 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
786 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
787 I40E_PTT_UNUSED_ENTRY(150),
788 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
789 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
790 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
791
792 /* unused entries */
793 I40E_PTT_UNUSED_ENTRY(154),
794 I40E_PTT_UNUSED_ENTRY(155),
795 I40E_PTT_UNUSED_ENTRY(156),
796 I40E_PTT_UNUSED_ENTRY(157),
797 I40E_PTT_UNUSED_ENTRY(158),
798 I40E_PTT_UNUSED_ENTRY(159),
799
800 I40E_PTT_UNUSED_ENTRY(160),
801 I40E_PTT_UNUSED_ENTRY(161),
802 I40E_PTT_UNUSED_ENTRY(162),
803 I40E_PTT_UNUSED_ENTRY(163),
804 I40E_PTT_UNUSED_ENTRY(164),
805 I40E_PTT_UNUSED_ENTRY(165),
806 I40E_PTT_UNUSED_ENTRY(166),
807 I40E_PTT_UNUSED_ENTRY(167),
808 I40E_PTT_UNUSED_ENTRY(168),
809 I40E_PTT_UNUSED_ENTRY(169),
810
811 I40E_PTT_UNUSED_ENTRY(170),
812 I40E_PTT_UNUSED_ENTRY(171),
813 I40E_PTT_UNUSED_ENTRY(172),
814 I40E_PTT_UNUSED_ENTRY(173),
815 I40E_PTT_UNUSED_ENTRY(174),
816 I40E_PTT_UNUSED_ENTRY(175),
817 I40E_PTT_UNUSED_ENTRY(176),
818 I40E_PTT_UNUSED_ENTRY(177),
819 I40E_PTT_UNUSED_ENTRY(178),
820 I40E_PTT_UNUSED_ENTRY(179),
821
822 I40E_PTT_UNUSED_ENTRY(180),
823 I40E_PTT_UNUSED_ENTRY(181),
824 I40E_PTT_UNUSED_ENTRY(182),
825 I40E_PTT_UNUSED_ENTRY(183),
826 I40E_PTT_UNUSED_ENTRY(184),
827 I40E_PTT_UNUSED_ENTRY(185),
828 I40E_PTT_UNUSED_ENTRY(186),
829 I40E_PTT_UNUSED_ENTRY(187),
830 I40E_PTT_UNUSED_ENTRY(188),
831 I40E_PTT_UNUSED_ENTRY(189),
832
833 I40E_PTT_UNUSED_ENTRY(190),
834 I40E_PTT_UNUSED_ENTRY(191),
835 I40E_PTT_UNUSED_ENTRY(192),
836 I40E_PTT_UNUSED_ENTRY(193),
837 I40E_PTT_UNUSED_ENTRY(194),
838 I40E_PTT_UNUSED_ENTRY(195),
839 I40E_PTT_UNUSED_ENTRY(196),
840 I40E_PTT_UNUSED_ENTRY(197),
841 I40E_PTT_UNUSED_ENTRY(198),
842 I40E_PTT_UNUSED_ENTRY(199),
843
844 I40E_PTT_UNUSED_ENTRY(200),
845 I40E_PTT_UNUSED_ENTRY(201),
846 I40E_PTT_UNUSED_ENTRY(202),
847 I40E_PTT_UNUSED_ENTRY(203),
848 I40E_PTT_UNUSED_ENTRY(204),
849 I40E_PTT_UNUSED_ENTRY(205),
850 I40E_PTT_UNUSED_ENTRY(206),
851 I40E_PTT_UNUSED_ENTRY(207),
852 I40E_PTT_UNUSED_ENTRY(208),
853 I40E_PTT_UNUSED_ENTRY(209),
854
855 I40E_PTT_UNUSED_ENTRY(210),
856 I40E_PTT_UNUSED_ENTRY(211),
857 I40E_PTT_UNUSED_ENTRY(212),
858 I40E_PTT_UNUSED_ENTRY(213),
859 I40E_PTT_UNUSED_ENTRY(214),
860 I40E_PTT_UNUSED_ENTRY(215),
861 I40E_PTT_UNUSED_ENTRY(216),
862 I40E_PTT_UNUSED_ENTRY(217),
863 I40E_PTT_UNUSED_ENTRY(218),
864 I40E_PTT_UNUSED_ENTRY(219),
865
866 I40E_PTT_UNUSED_ENTRY(220),
867 I40E_PTT_UNUSED_ENTRY(221),
868 I40E_PTT_UNUSED_ENTRY(222),
869 I40E_PTT_UNUSED_ENTRY(223),
870 I40E_PTT_UNUSED_ENTRY(224),
871 I40E_PTT_UNUSED_ENTRY(225),
872 I40E_PTT_UNUSED_ENTRY(226),
873 I40E_PTT_UNUSED_ENTRY(227),
874 I40E_PTT_UNUSED_ENTRY(228),
875 I40E_PTT_UNUSED_ENTRY(229),
876
877 I40E_PTT_UNUSED_ENTRY(230),
878 I40E_PTT_UNUSED_ENTRY(231),
879 I40E_PTT_UNUSED_ENTRY(232),
880 I40E_PTT_UNUSED_ENTRY(233),
881 I40E_PTT_UNUSED_ENTRY(234),
882 I40E_PTT_UNUSED_ENTRY(235),
883 I40E_PTT_UNUSED_ENTRY(236),
884 I40E_PTT_UNUSED_ENTRY(237),
885 I40E_PTT_UNUSED_ENTRY(238),
886 I40E_PTT_UNUSED_ENTRY(239),
887
888 I40E_PTT_UNUSED_ENTRY(240),
889 I40E_PTT_UNUSED_ENTRY(241),
890 I40E_PTT_UNUSED_ENTRY(242),
891 I40E_PTT_UNUSED_ENTRY(243),
892 I40E_PTT_UNUSED_ENTRY(244),
893 I40E_PTT_UNUSED_ENTRY(245),
894 I40E_PTT_UNUSED_ENTRY(246),
895 I40E_PTT_UNUSED_ENTRY(247),
896 I40E_PTT_UNUSED_ENTRY(248),
897 I40E_PTT_UNUSED_ENTRY(249),
898
899 I40E_PTT_UNUSED_ENTRY(250),
900 I40E_PTT_UNUSED_ENTRY(251),
901 I40E_PTT_UNUSED_ENTRY(252),
902 I40E_PTT_UNUSED_ENTRY(253),
903 I40E_PTT_UNUSED_ENTRY(254),
904 I40E_PTT_UNUSED_ENTRY(255)
905 };
906
907 /**
908 * i40e_init_shared_code - Initialize the shared code
909 * @hw: pointer to hardware structure
910 *
911 * This assigns the MAC type and PHY code and inits the NVM.
912 * Does not touch the hardware. This function must be called prior to any
913 * other function in the shared code. The i40e_hw structure should be
914 * memset to 0 prior to calling this function. The following fields in
915 * hw structure should be filled in prior to calling this function:
916 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
917 * subsystem_vendor_id, and revision_id
918 **/
919 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
920 {
921 i40e_status status = 0;
922 u32 port, ari, func_rid;
923
924 i40e_set_mac_type(hw);
925
926 switch (hw->mac.type) {
927 case I40E_MAC_XL710:
928 case I40E_MAC_X722:
929 break;
930 default:
931 return I40E_ERR_DEVICE_NOT_SUPPORTED;
932 }
933
934 hw->phy.get_link_info = true;
935
936 /* Determine port number and PF number*/
937 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
938 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
939 hw->port = (u8)port;
940 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
941 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
942 func_rid = rd32(hw, I40E_PF_FUNC_RID);
943 if (ari)
944 hw->pf_id = (u8)(func_rid & 0xff);
945 else
946 hw->pf_id = (u8)(func_rid & 0x7);
947
948 if (hw->mac.type == I40E_MAC_X722)
949 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
950
951 status = i40e_init_nvm(hw);
952 return status;
953 }
954
955 /**
956 * i40e_aq_mac_address_read - Retrieve the MAC addresses
957 * @hw: pointer to the hw struct
958 * @flags: a return indicator of what addresses were added to the addr store
959 * @addrs: the requestor's mac addr store
960 * @cmd_details: pointer to command details structure or NULL
961 **/
962 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
963 u16 *flags,
964 struct i40e_aqc_mac_address_read_data *addrs,
965 struct i40e_asq_cmd_details *cmd_details)
966 {
967 struct i40e_aq_desc desc;
968 struct i40e_aqc_mac_address_read *cmd_data =
969 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
970 i40e_status status;
971
972 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
973 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
974
975 status = i40e_asq_send_command(hw, &desc, addrs,
976 sizeof(*addrs), cmd_details);
977 *flags = le16_to_cpu(cmd_data->command_flags);
978
979 return status;
980 }
981
982 /**
983 * i40e_aq_mac_address_write - Change the MAC addresses
984 * @hw: pointer to the hw struct
985 * @flags: indicates which MAC to be written
986 * @mac_addr: address to write
987 * @cmd_details: pointer to command details structure or NULL
988 **/
989 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
990 u16 flags, u8 *mac_addr,
991 struct i40e_asq_cmd_details *cmd_details)
992 {
993 struct i40e_aq_desc desc;
994 struct i40e_aqc_mac_address_write *cmd_data =
995 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
996 i40e_status status;
997
998 i40e_fill_default_direct_cmd_desc(&desc,
999 i40e_aqc_opc_mac_address_write);
1000 cmd_data->command_flags = cpu_to_le16(flags);
1001 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
1002 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
1003 ((u32)mac_addr[3] << 16) |
1004 ((u32)mac_addr[4] << 8) |
1005 mac_addr[5]);
1006
1007 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1008
1009 return status;
1010 }
1011
1012 /**
1013 * i40e_get_mac_addr - get MAC address
1014 * @hw: pointer to the HW structure
1015 * @mac_addr: pointer to MAC address
1016 *
1017 * Reads the adapter's MAC address from register
1018 **/
1019 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1020 {
1021 struct i40e_aqc_mac_address_read_data addrs;
1022 i40e_status status;
1023 u16 flags = 0;
1024
1025 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1026
1027 if (flags & I40E_AQC_LAN_ADDR_VALID)
1028 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
1029
1030 return status;
1031 }
1032
1033 /**
1034 * i40e_get_port_mac_addr - get Port MAC address
1035 * @hw: pointer to the HW structure
1036 * @mac_addr: pointer to Port MAC address
1037 *
1038 * Reads the adapter's Port MAC address
1039 **/
1040 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1041 {
1042 struct i40e_aqc_mac_address_read_data addrs;
1043 i40e_status status;
1044 u16 flags = 0;
1045
1046 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1047 if (status)
1048 return status;
1049
1050 if (flags & I40E_AQC_PORT_ADDR_VALID)
1051 ether_addr_copy(mac_addr, addrs.port_mac);
1052 else
1053 status = I40E_ERR_INVALID_MAC_ADDR;
1054
1055 return status;
1056 }
1057
1058 /**
1059 * i40e_pre_tx_queue_cfg - pre tx queue configure
1060 * @hw: pointer to the HW structure
1061 * @queue: target PF queue index
1062 * @enable: state change request
1063 *
1064 * Handles hw requirement to indicate intention to enable
1065 * or disable target queue.
1066 **/
1067 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1068 {
1069 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1070 u32 reg_block = 0;
1071 u32 reg_val;
1072
1073 if (abs_queue_idx >= 128) {
1074 reg_block = abs_queue_idx / 128;
1075 abs_queue_idx %= 128;
1076 }
1077
1078 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1079 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1080 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1081
1082 if (enable)
1083 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1084 else
1085 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1086
1087 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1088 }
1089 #ifdef I40E_FCOE
1090
1091 /**
1092 * i40e_get_san_mac_addr - get SAN MAC address
1093 * @hw: pointer to the HW structure
1094 * @mac_addr: pointer to SAN MAC address
1095 *
1096 * Reads the adapter's SAN MAC address from NVM
1097 **/
1098 i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1099 {
1100 struct i40e_aqc_mac_address_read_data addrs;
1101 i40e_status status;
1102 u16 flags = 0;
1103
1104 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1105 if (status)
1106 return status;
1107
1108 if (flags & I40E_AQC_SAN_ADDR_VALID)
1109 ether_addr_copy(mac_addr, addrs.pf_san_mac);
1110 else
1111 status = I40E_ERR_INVALID_MAC_ADDR;
1112
1113 return status;
1114 }
1115 #endif
1116
1117 /**
1118 * i40e_read_pba_string - Reads part number string from EEPROM
1119 * @hw: pointer to hardware structure
1120 * @pba_num: stores the part number string from the EEPROM
1121 * @pba_num_size: part number string buffer length
1122 *
1123 * Reads the part number string from the EEPROM.
1124 **/
1125 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1126 u32 pba_num_size)
1127 {
1128 i40e_status status = 0;
1129 u16 pba_word = 0;
1130 u16 pba_size = 0;
1131 u16 pba_ptr = 0;
1132 u16 i = 0;
1133
1134 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1135 if (status || (pba_word != 0xFAFA)) {
1136 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1137 return status;
1138 }
1139
1140 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1141 if (status) {
1142 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1143 return status;
1144 }
1145
1146 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1147 if (status) {
1148 hw_dbg(hw, "Failed to read PBA Block size.\n");
1149 return status;
1150 }
1151
1152 /* Subtract one to get PBA word count (PBA Size word is included in
1153 * total size)
1154 */
1155 pba_size--;
1156 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1157 hw_dbg(hw, "Buffer to small for PBA data.\n");
1158 return I40E_ERR_PARAM;
1159 }
1160
1161 for (i = 0; i < pba_size; i++) {
1162 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1163 if (status) {
1164 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1165 return status;
1166 }
1167
1168 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1169 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1170 }
1171 pba_num[(pba_size * 2)] = '\0';
1172
1173 return status;
1174 }
1175
1176 /**
1177 * i40e_get_media_type - Gets media type
1178 * @hw: pointer to the hardware structure
1179 **/
1180 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1181 {
1182 enum i40e_media_type media;
1183
1184 switch (hw->phy.link_info.phy_type) {
1185 case I40E_PHY_TYPE_10GBASE_SR:
1186 case I40E_PHY_TYPE_10GBASE_LR:
1187 case I40E_PHY_TYPE_1000BASE_SX:
1188 case I40E_PHY_TYPE_1000BASE_LX:
1189 case I40E_PHY_TYPE_40GBASE_SR4:
1190 case I40E_PHY_TYPE_40GBASE_LR4:
1191 media = I40E_MEDIA_TYPE_FIBER;
1192 break;
1193 case I40E_PHY_TYPE_100BASE_TX:
1194 case I40E_PHY_TYPE_1000BASE_T:
1195 case I40E_PHY_TYPE_10GBASE_T:
1196 media = I40E_MEDIA_TYPE_BASET;
1197 break;
1198 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1199 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1200 case I40E_PHY_TYPE_10GBASE_CR1:
1201 case I40E_PHY_TYPE_40GBASE_CR4:
1202 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1203 case I40E_PHY_TYPE_40GBASE_AOC:
1204 case I40E_PHY_TYPE_10GBASE_AOC:
1205 media = I40E_MEDIA_TYPE_DA;
1206 break;
1207 case I40E_PHY_TYPE_1000BASE_KX:
1208 case I40E_PHY_TYPE_10GBASE_KX4:
1209 case I40E_PHY_TYPE_10GBASE_KR:
1210 case I40E_PHY_TYPE_40GBASE_KR4:
1211 case I40E_PHY_TYPE_20GBASE_KR2:
1212 media = I40E_MEDIA_TYPE_BACKPLANE;
1213 break;
1214 case I40E_PHY_TYPE_SGMII:
1215 case I40E_PHY_TYPE_XAUI:
1216 case I40E_PHY_TYPE_XFI:
1217 case I40E_PHY_TYPE_XLAUI:
1218 case I40E_PHY_TYPE_XLPPI:
1219 default:
1220 media = I40E_MEDIA_TYPE_UNKNOWN;
1221 break;
1222 }
1223
1224 return media;
1225 }
1226
1227 #define I40E_PF_RESET_WAIT_COUNT_A0 200
1228 #define I40E_PF_RESET_WAIT_COUNT 200
1229 /**
1230 * i40e_pf_reset - Reset the PF
1231 * @hw: pointer to the hardware structure
1232 *
1233 * Assuming someone else has triggered a global reset,
1234 * assure the global reset is complete and then reset the PF
1235 **/
1236 i40e_status i40e_pf_reset(struct i40e_hw *hw)
1237 {
1238 u32 cnt = 0;
1239 u32 cnt1 = 0;
1240 u32 reg = 0;
1241 u32 grst_del;
1242
1243 /* Poll for Global Reset steady state in case of recent GRST.
1244 * The grst delay value is in 100ms units, and we'll wait a
1245 * couple counts longer to be sure we don't just miss the end.
1246 */
1247 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1248 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1249 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1250 for (cnt = 0; cnt < grst_del + 10; cnt++) {
1251 reg = rd32(hw, I40E_GLGEN_RSTAT);
1252 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1253 break;
1254 msleep(100);
1255 }
1256 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1257 hw_dbg(hw, "Global reset polling failed to complete.\n");
1258 return I40E_ERR_RESET_FAILED;
1259 }
1260
1261 /* Now Wait for the FW to be ready */
1262 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1263 reg = rd32(hw, I40E_GLNVM_ULD);
1264 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1265 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1266 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1267 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1268 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1269 break;
1270 }
1271 usleep_range(10000, 20000);
1272 }
1273 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1274 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1275 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1276 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1277 return I40E_ERR_RESET_FAILED;
1278 }
1279
1280 /* If there was a Global Reset in progress when we got here,
1281 * we don't need to do the PF Reset
1282 */
1283 if (!cnt) {
1284 if (hw->revision_id == 0)
1285 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1286 else
1287 cnt = I40E_PF_RESET_WAIT_COUNT;
1288 reg = rd32(hw, I40E_PFGEN_CTRL);
1289 wr32(hw, I40E_PFGEN_CTRL,
1290 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1291 for (; cnt; cnt--) {
1292 reg = rd32(hw, I40E_PFGEN_CTRL);
1293 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1294 break;
1295 usleep_range(1000, 2000);
1296 }
1297 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1298 hw_dbg(hw, "PF reset polling failed to complete.\n");
1299 return I40E_ERR_RESET_FAILED;
1300 }
1301 }
1302
1303 i40e_clear_pxe_mode(hw);
1304
1305 return 0;
1306 }
1307
1308 /**
1309 * i40e_clear_hw - clear out any left over hw state
1310 * @hw: pointer to the hw struct
1311 *
1312 * Clear queues and interrupts, typically called at init time,
1313 * but after the capabilities have been found so we know how many
1314 * queues and msix vectors have been allocated.
1315 **/
1316 void i40e_clear_hw(struct i40e_hw *hw)
1317 {
1318 u32 num_queues, base_queue;
1319 u32 num_pf_int;
1320 u32 num_vf_int;
1321 u32 num_vfs;
1322 u32 i, j;
1323 u32 val;
1324 u32 eol = 0x7ff;
1325
1326 /* get number of interrupts, queues, and VFs */
1327 val = rd32(hw, I40E_GLPCI_CNF2);
1328 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1329 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1330 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1331 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1332
1333 val = rd32(hw, I40E_PFLAN_QALLOC);
1334 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1335 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1336 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1337 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1338 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1339 num_queues = (j - base_queue) + 1;
1340 else
1341 num_queues = 0;
1342
1343 val = rd32(hw, I40E_PF_VT_PFALLOC);
1344 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1345 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1346 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1347 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1348 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1349 num_vfs = (j - i) + 1;
1350 else
1351 num_vfs = 0;
1352
1353 /* stop all the interrupts */
1354 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1355 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1356 for (i = 0; i < num_pf_int - 2; i++)
1357 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1358
1359 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1360 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1361 wr32(hw, I40E_PFINT_LNKLST0, val);
1362 for (i = 0; i < num_pf_int - 2; i++)
1363 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1364 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1365 for (i = 0; i < num_vfs; i++)
1366 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1367 for (i = 0; i < num_vf_int - 2; i++)
1368 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1369
1370 /* warn the HW of the coming Tx disables */
1371 for (i = 0; i < num_queues; i++) {
1372 u32 abs_queue_idx = base_queue + i;
1373 u32 reg_block = 0;
1374
1375 if (abs_queue_idx >= 128) {
1376 reg_block = abs_queue_idx / 128;
1377 abs_queue_idx %= 128;
1378 }
1379
1380 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1381 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1382 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1383 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1384
1385 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1386 }
1387 udelay(400);
1388
1389 /* stop all the queues */
1390 for (i = 0; i < num_queues; i++) {
1391 wr32(hw, I40E_QINT_TQCTL(i), 0);
1392 wr32(hw, I40E_QTX_ENA(i), 0);
1393 wr32(hw, I40E_QINT_RQCTL(i), 0);
1394 wr32(hw, I40E_QRX_ENA(i), 0);
1395 }
1396
1397 /* short wait for all queue disables to settle */
1398 udelay(50);
1399 }
1400
1401 /**
1402 * i40e_clear_pxe_mode - clear pxe operations mode
1403 * @hw: pointer to the hw struct
1404 *
1405 * Make sure all PXE mode settings are cleared, including things
1406 * like descriptor fetch/write-back mode.
1407 **/
1408 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1409 {
1410 u32 reg;
1411
1412 if (i40e_check_asq_alive(hw))
1413 i40e_aq_clear_pxe_mode(hw, NULL);
1414
1415 /* Clear single descriptor fetch/write-back mode */
1416 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1417
1418 if (hw->revision_id == 0) {
1419 /* As a work around clear PXE_MODE instead of setting it */
1420 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1421 } else {
1422 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1423 }
1424 }
1425
1426 /**
1427 * i40e_led_is_mine - helper to find matching led
1428 * @hw: pointer to the hw struct
1429 * @idx: index into GPIO registers
1430 *
1431 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1432 */
1433 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1434 {
1435 u32 gpio_val = 0;
1436 u32 port;
1437
1438 if (!hw->func_caps.led[idx])
1439 return 0;
1440
1441 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1442 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1443 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1444
1445 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1446 * if it is not our port then ignore
1447 */
1448 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1449 (port != hw->port))
1450 return 0;
1451
1452 return gpio_val;
1453 }
1454
1455 #define I40E_COMBINED_ACTIVITY 0xA
1456 #define I40E_FILTER_ACTIVITY 0xE
1457 #define I40E_LINK_ACTIVITY 0xC
1458 #define I40E_MAC_ACTIVITY 0xD
1459 #define I40E_LED0 22
1460
1461 /**
1462 * i40e_led_get - return current on/off mode
1463 * @hw: pointer to the hw struct
1464 *
1465 * The value returned is the 'mode' field as defined in the
1466 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1467 * values are variations of possible behaviors relating to
1468 * blink, link, and wire.
1469 **/
1470 u32 i40e_led_get(struct i40e_hw *hw)
1471 {
1472 u32 current_mode = 0;
1473 u32 mode = 0;
1474 int i;
1475
1476 /* as per the documentation GPIO 22-29 are the LED
1477 * GPIO pins named LED0..LED7
1478 */
1479 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1480 u32 gpio_val = i40e_led_is_mine(hw, i);
1481
1482 if (!gpio_val)
1483 continue;
1484
1485 /* ignore gpio LED src mode entries related to the activity
1486 * LEDs
1487 */
1488 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1489 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1490 switch (current_mode) {
1491 case I40E_COMBINED_ACTIVITY:
1492 case I40E_FILTER_ACTIVITY:
1493 case I40E_MAC_ACTIVITY:
1494 continue;
1495 default:
1496 break;
1497 }
1498
1499 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1500 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1501 break;
1502 }
1503
1504 return mode;
1505 }
1506
1507 /**
1508 * i40e_led_set - set new on/off mode
1509 * @hw: pointer to the hw struct
1510 * @mode: 0=off, 0xf=on (else see manual for mode details)
1511 * @blink: true if the LED should blink when on, false if steady
1512 *
1513 * if this function is used to turn on the blink it should
1514 * be used to disable the blink when restoring the original state.
1515 **/
1516 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1517 {
1518 u32 current_mode = 0;
1519 int i;
1520
1521 if (mode & 0xfffffff0)
1522 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1523
1524 /* as per the documentation GPIO 22-29 are the LED
1525 * GPIO pins named LED0..LED7
1526 */
1527 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1528 u32 gpio_val = i40e_led_is_mine(hw, i);
1529
1530 if (!gpio_val)
1531 continue;
1532
1533 /* ignore gpio LED src mode entries related to the activity
1534 * LEDs
1535 */
1536 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1537 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1538 switch (current_mode) {
1539 case I40E_COMBINED_ACTIVITY:
1540 case I40E_FILTER_ACTIVITY:
1541 case I40E_MAC_ACTIVITY:
1542 continue;
1543 default:
1544 break;
1545 }
1546
1547 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1548 /* this & is a bit of paranoia, but serves as a range check */
1549 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1550 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1551
1552 if (mode == I40E_LINK_ACTIVITY)
1553 blink = false;
1554
1555 if (blink)
1556 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1557 else
1558 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1559
1560 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1561 break;
1562 }
1563 }
1564
1565 /* Admin command wrappers */
1566
1567 /**
1568 * i40e_aq_get_phy_capabilities
1569 * @hw: pointer to the hw struct
1570 * @abilities: structure for PHY capabilities to be filled
1571 * @qualified_modules: report Qualified Modules
1572 * @report_init: report init capabilities (active are default)
1573 * @cmd_details: pointer to command details structure or NULL
1574 *
1575 * Returns the various PHY abilities supported on the Port.
1576 **/
1577 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1578 bool qualified_modules, bool report_init,
1579 struct i40e_aq_get_phy_abilities_resp *abilities,
1580 struct i40e_asq_cmd_details *cmd_details)
1581 {
1582 struct i40e_aq_desc desc;
1583 i40e_status status;
1584 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1585
1586 if (!abilities)
1587 return I40E_ERR_PARAM;
1588
1589 i40e_fill_default_direct_cmd_desc(&desc,
1590 i40e_aqc_opc_get_phy_abilities);
1591
1592 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1593 if (abilities_size > I40E_AQ_LARGE_BUF)
1594 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1595
1596 if (qualified_modules)
1597 desc.params.external.param0 |=
1598 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1599
1600 if (report_init)
1601 desc.params.external.param0 |=
1602 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1603
1604 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1605 cmd_details);
1606
1607 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1608 status = I40E_ERR_UNKNOWN_PHY;
1609
1610 if (report_init)
1611 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1612
1613 return status;
1614 }
1615
1616 /**
1617 * i40e_aq_set_phy_config
1618 * @hw: pointer to the hw struct
1619 * @config: structure with PHY configuration to be set
1620 * @cmd_details: pointer to command details structure or NULL
1621 *
1622 * Set the various PHY configuration parameters
1623 * supported on the Port.One or more of the Set PHY config parameters may be
1624 * ignored in an MFP mode as the PF may not have the privilege to set some
1625 * of the PHY Config parameters. This status will be indicated by the
1626 * command response.
1627 **/
1628 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1629 struct i40e_aq_set_phy_config *config,
1630 struct i40e_asq_cmd_details *cmd_details)
1631 {
1632 struct i40e_aq_desc desc;
1633 struct i40e_aq_set_phy_config *cmd =
1634 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1635 enum i40e_status_code status;
1636
1637 if (!config)
1638 return I40E_ERR_PARAM;
1639
1640 i40e_fill_default_direct_cmd_desc(&desc,
1641 i40e_aqc_opc_set_phy_config);
1642
1643 *cmd = *config;
1644
1645 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1646
1647 return status;
1648 }
1649
1650 /**
1651 * i40e_set_fc
1652 * @hw: pointer to the hw struct
1653 *
1654 * Set the requested flow control mode using set_phy_config.
1655 **/
1656 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1657 bool atomic_restart)
1658 {
1659 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1660 struct i40e_aq_get_phy_abilities_resp abilities;
1661 struct i40e_aq_set_phy_config config;
1662 enum i40e_status_code status;
1663 u8 pause_mask = 0x0;
1664
1665 *aq_failures = 0x0;
1666
1667 switch (fc_mode) {
1668 case I40E_FC_FULL:
1669 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1670 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1671 break;
1672 case I40E_FC_RX_PAUSE:
1673 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1674 break;
1675 case I40E_FC_TX_PAUSE:
1676 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1677 break;
1678 default:
1679 break;
1680 }
1681
1682 /* Get the current phy config */
1683 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1684 NULL);
1685 if (status) {
1686 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1687 return status;
1688 }
1689
1690 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1691 /* clear the old pause settings */
1692 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1693 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1694 /* set the new abilities */
1695 config.abilities |= pause_mask;
1696 /* If the abilities have changed, then set the new config */
1697 if (config.abilities != abilities.abilities) {
1698 /* Auto restart link so settings take effect */
1699 if (atomic_restart)
1700 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1701 /* Copy over all the old settings */
1702 config.phy_type = abilities.phy_type;
1703 config.link_speed = abilities.link_speed;
1704 config.eee_capability = abilities.eee_capability;
1705 config.eeer = abilities.eeer_val;
1706 config.low_power_ctrl = abilities.d3_lpan;
1707 status = i40e_aq_set_phy_config(hw, &config, NULL);
1708
1709 if (status)
1710 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1711 }
1712 /* Update the link info */
1713 status = i40e_update_link_info(hw);
1714 if (status) {
1715 /* Wait a little bit (on 40G cards it sometimes takes a really
1716 * long time for link to come back from the atomic reset)
1717 * and try once more
1718 */
1719 msleep(1000);
1720 status = i40e_update_link_info(hw);
1721 }
1722 if (status)
1723 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1724
1725 return status;
1726 }
1727
1728 /**
1729 * i40e_aq_clear_pxe_mode
1730 * @hw: pointer to the hw struct
1731 * @cmd_details: pointer to command details structure or NULL
1732 *
1733 * Tell the firmware that the driver is taking over from PXE
1734 **/
1735 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1736 struct i40e_asq_cmd_details *cmd_details)
1737 {
1738 i40e_status status;
1739 struct i40e_aq_desc desc;
1740 struct i40e_aqc_clear_pxe *cmd =
1741 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1742
1743 i40e_fill_default_direct_cmd_desc(&desc,
1744 i40e_aqc_opc_clear_pxe_mode);
1745
1746 cmd->rx_cnt = 0x2;
1747
1748 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1749
1750 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1751
1752 return status;
1753 }
1754
1755 /**
1756 * i40e_aq_set_link_restart_an
1757 * @hw: pointer to the hw struct
1758 * @enable_link: if true: enable link, if false: disable link
1759 * @cmd_details: pointer to command details structure or NULL
1760 *
1761 * Sets up the link and restarts the Auto-Negotiation over the link.
1762 **/
1763 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1764 bool enable_link,
1765 struct i40e_asq_cmd_details *cmd_details)
1766 {
1767 struct i40e_aq_desc desc;
1768 struct i40e_aqc_set_link_restart_an *cmd =
1769 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1770 i40e_status status;
1771
1772 i40e_fill_default_direct_cmd_desc(&desc,
1773 i40e_aqc_opc_set_link_restart_an);
1774
1775 cmd->command = I40E_AQ_PHY_RESTART_AN;
1776 if (enable_link)
1777 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1778 else
1779 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1780
1781 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1782
1783 return status;
1784 }
1785
1786 /**
1787 * i40e_aq_get_link_info
1788 * @hw: pointer to the hw struct
1789 * @enable_lse: enable/disable LinkStatusEvent reporting
1790 * @link: pointer to link status structure - optional
1791 * @cmd_details: pointer to command details structure or NULL
1792 *
1793 * Returns the link status of the adapter.
1794 **/
1795 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1796 bool enable_lse, struct i40e_link_status *link,
1797 struct i40e_asq_cmd_details *cmd_details)
1798 {
1799 struct i40e_aq_desc desc;
1800 struct i40e_aqc_get_link_status *resp =
1801 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1802 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1803 i40e_status status;
1804 bool tx_pause, rx_pause;
1805 u16 command_flags;
1806
1807 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1808
1809 if (enable_lse)
1810 command_flags = I40E_AQ_LSE_ENABLE;
1811 else
1812 command_flags = I40E_AQ_LSE_DISABLE;
1813 resp->command_flags = cpu_to_le16(command_flags);
1814
1815 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1816
1817 if (status)
1818 goto aq_get_link_info_exit;
1819
1820 /* save off old link status information */
1821 hw->phy.link_info_old = *hw_link_info;
1822
1823 /* update link status */
1824 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1825 hw->phy.media_type = i40e_get_media_type(hw);
1826 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1827 hw_link_info->link_info = resp->link_info;
1828 hw_link_info->an_info = resp->an_info;
1829 hw_link_info->ext_info = resp->ext_info;
1830 hw_link_info->loopback = resp->loopback;
1831 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1832 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1833
1834 /* update fc info */
1835 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1836 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1837 if (tx_pause & rx_pause)
1838 hw->fc.current_mode = I40E_FC_FULL;
1839 else if (tx_pause)
1840 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1841 else if (rx_pause)
1842 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1843 else
1844 hw->fc.current_mode = I40E_FC_NONE;
1845
1846 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1847 hw_link_info->crc_enable = true;
1848 else
1849 hw_link_info->crc_enable = false;
1850
1851 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1852 hw_link_info->lse_enable = true;
1853 else
1854 hw_link_info->lse_enable = false;
1855
1856 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1857 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1858 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1859
1860 /* save link status information */
1861 if (link)
1862 *link = *hw_link_info;
1863
1864 /* flag cleared so helper functions don't call AQ again */
1865 hw->phy.get_link_info = false;
1866
1867 aq_get_link_info_exit:
1868 return status;
1869 }
1870
1871 /**
1872 * i40e_aq_set_phy_int_mask
1873 * @hw: pointer to the hw struct
1874 * @mask: interrupt mask to be set
1875 * @cmd_details: pointer to command details structure or NULL
1876 *
1877 * Set link interrupt mask.
1878 **/
1879 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1880 u16 mask,
1881 struct i40e_asq_cmd_details *cmd_details)
1882 {
1883 struct i40e_aq_desc desc;
1884 struct i40e_aqc_set_phy_int_mask *cmd =
1885 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1886 i40e_status status;
1887
1888 i40e_fill_default_direct_cmd_desc(&desc,
1889 i40e_aqc_opc_set_phy_int_mask);
1890
1891 cmd->event_mask = cpu_to_le16(mask);
1892
1893 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1894
1895 return status;
1896 }
1897
1898 /**
1899 * i40e_aq_add_vsi
1900 * @hw: pointer to the hw struct
1901 * @vsi_ctx: pointer to a vsi context struct
1902 * @cmd_details: pointer to command details structure or NULL
1903 *
1904 * Add a VSI context to the hardware.
1905 **/
1906 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1907 struct i40e_vsi_context *vsi_ctx,
1908 struct i40e_asq_cmd_details *cmd_details)
1909 {
1910 struct i40e_aq_desc desc;
1911 struct i40e_aqc_add_get_update_vsi *cmd =
1912 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1913 struct i40e_aqc_add_get_update_vsi_completion *resp =
1914 (struct i40e_aqc_add_get_update_vsi_completion *)
1915 &desc.params.raw;
1916 i40e_status status;
1917
1918 i40e_fill_default_direct_cmd_desc(&desc,
1919 i40e_aqc_opc_add_vsi);
1920
1921 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1922 cmd->connection_type = vsi_ctx->connection_type;
1923 cmd->vf_id = vsi_ctx->vf_num;
1924 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1925
1926 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1927
1928 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1929 sizeof(vsi_ctx->info), cmd_details);
1930
1931 if (status)
1932 goto aq_add_vsi_exit;
1933
1934 vsi_ctx->seid = le16_to_cpu(resp->seid);
1935 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1936 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1937 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1938
1939 aq_add_vsi_exit:
1940 return status;
1941 }
1942
1943 /**
1944 * i40e_aq_set_vsi_unicast_promiscuous
1945 * @hw: pointer to the hw struct
1946 * @seid: vsi number
1947 * @set: set unicast promiscuous enable/disable
1948 * @cmd_details: pointer to command details structure or NULL
1949 **/
1950 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1951 u16 seid, bool set,
1952 struct i40e_asq_cmd_details *cmd_details)
1953 {
1954 struct i40e_aq_desc desc;
1955 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1956 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1957 i40e_status status;
1958 u16 flags = 0;
1959
1960 i40e_fill_default_direct_cmd_desc(&desc,
1961 i40e_aqc_opc_set_vsi_promiscuous_modes);
1962
1963 if (set)
1964 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1965
1966 cmd->promiscuous_flags = cpu_to_le16(flags);
1967
1968 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1969
1970 cmd->seid = cpu_to_le16(seid);
1971 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1972
1973 return status;
1974 }
1975
1976 /**
1977 * i40e_aq_set_vsi_multicast_promiscuous
1978 * @hw: pointer to the hw struct
1979 * @seid: vsi number
1980 * @set: set multicast promiscuous enable/disable
1981 * @cmd_details: pointer to command details structure or NULL
1982 **/
1983 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1984 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1985 {
1986 struct i40e_aq_desc desc;
1987 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1988 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1989 i40e_status status;
1990 u16 flags = 0;
1991
1992 i40e_fill_default_direct_cmd_desc(&desc,
1993 i40e_aqc_opc_set_vsi_promiscuous_modes);
1994
1995 if (set)
1996 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1997
1998 cmd->promiscuous_flags = cpu_to_le16(flags);
1999
2000 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2001
2002 cmd->seid = cpu_to_le16(seid);
2003 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2004
2005 return status;
2006 }
2007
2008 /**
2009 * i40e_aq_set_vsi_broadcast
2010 * @hw: pointer to the hw struct
2011 * @seid: vsi number
2012 * @set_filter: true to set filter, false to clear filter
2013 * @cmd_details: pointer to command details structure or NULL
2014 *
2015 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2016 **/
2017 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2018 u16 seid, bool set_filter,
2019 struct i40e_asq_cmd_details *cmd_details)
2020 {
2021 struct i40e_aq_desc desc;
2022 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2023 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2024 i40e_status status;
2025
2026 i40e_fill_default_direct_cmd_desc(&desc,
2027 i40e_aqc_opc_set_vsi_promiscuous_modes);
2028
2029 if (set_filter)
2030 cmd->promiscuous_flags
2031 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2032 else
2033 cmd->promiscuous_flags
2034 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2035
2036 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2037 cmd->seid = cpu_to_le16(seid);
2038 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2039
2040 return status;
2041 }
2042
2043 /**
2044 * i40e_get_vsi_params - get VSI configuration info
2045 * @hw: pointer to the hw struct
2046 * @vsi_ctx: pointer to a vsi context struct
2047 * @cmd_details: pointer to command details structure or NULL
2048 **/
2049 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2050 struct i40e_vsi_context *vsi_ctx,
2051 struct i40e_asq_cmd_details *cmd_details)
2052 {
2053 struct i40e_aq_desc desc;
2054 struct i40e_aqc_add_get_update_vsi *cmd =
2055 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2056 struct i40e_aqc_add_get_update_vsi_completion *resp =
2057 (struct i40e_aqc_add_get_update_vsi_completion *)
2058 &desc.params.raw;
2059 i40e_status status;
2060
2061 i40e_fill_default_direct_cmd_desc(&desc,
2062 i40e_aqc_opc_get_vsi_parameters);
2063
2064 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2065
2066 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2067
2068 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2069 sizeof(vsi_ctx->info), NULL);
2070
2071 if (status)
2072 goto aq_get_vsi_params_exit;
2073
2074 vsi_ctx->seid = le16_to_cpu(resp->seid);
2075 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2076 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2077 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2078
2079 aq_get_vsi_params_exit:
2080 return status;
2081 }
2082
2083 /**
2084 * i40e_aq_update_vsi_params
2085 * @hw: pointer to the hw struct
2086 * @vsi_ctx: pointer to a vsi context struct
2087 * @cmd_details: pointer to command details structure or NULL
2088 *
2089 * Update a VSI context.
2090 **/
2091 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2092 struct i40e_vsi_context *vsi_ctx,
2093 struct i40e_asq_cmd_details *cmd_details)
2094 {
2095 struct i40e_aq_desc desc;
2096 struct i40e_aqc_add_get_update_vsi *cmd =
2097 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2098 i40e_status status;
2099
2100 i40e_fill_default_direct_cmd_desc(&desc,
2101 i40e_aqc_opc_update_vsi_parameters);
2102 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2103
2104 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2105
2106 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2107 sizeof(vsi_ctx->info), cmd_details);
2108
2109 return status;
2110 }
2111
2112 /**
2113 * i40e_aq_get_switch_config
2114 * @hw: pointer to the hardware structure
2115 * @buf: pointer to the result buffer
2116 * @buf_size: length of input buffer
2117 * @start_seid: seid to start for the report, 0 == beginning
2118 * @cmd_details: pointer to command details structure or NULL
2119 *
2120 * Fill the buf with switch configuration returned from AdminQ command
2121 **/
2122 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2123 struct i40e_aqc_get_switch_config_resp *buf,
2124 u16 buf_size, u16 *start_seid,
2125 struct i40e_asq_cmd_details *cmd_details)
2126 {
2127 struct i40e_aq_desc desc;
2128 struct i40e_aqc_switch_seid *scfg =
2129 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2130 i40e_status status;
2131
2132 i40e_fill_default_direct_cmd_desc(&desc,
2133 i40e_aqc_opc_get_switch_config);
2134 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2135 if (buf_size > I40E_AQ_LARGE_BUF)
2136 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2137 scfg->seid = cpu_to_le16(*start_seid);
2138
2139 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2140 *start_seid = le16_to_cpu(scfg->seid);
2141
2142 return status;
2143 }
2144
2145 /**
2146 * i40e_aq_get_firmware_version
2147 * @hw: pointer to the hw struct
2148 * @fw_major_version: firmware major version
2149 * @fw_minor_version: firmware minor version
2150 * @fw_build: firmware build number
2151 * @api_major_version: major queue version
2152 * @api_minor_version: minor queue version
2153 * @cmd_details: pointer to command details structure or NULL
2154 *
2155 * Get the firmware version from the admin queue commands
2156 **/
2157 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2158 u16 *fw_major_version, u16 *fw_minor_version,
2159 u32 *fw_build,
2160 u16 *api_major_version, u16 *api_minor_version,
2161 struct i40e_asq_cmd_details *cmd_details)
2162 {
2163 struct i40e_aq_desc desc;
2164 struct i40e_aqc_get_version *resp =
2165 (struct i40e_aqc_get_version *)&desc.params.raw;
2166 i40e_status status;
2167
2168 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2169
2170 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2171
2172 if (!status) {
2173 if (fw_major_version)
2174 *fw_major_version = le16_to_cpu(resp->fw_major);
2175 if (fw_minor_version)
2176 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2177 if (fw_build)
2178 *fw_build = le32_to_cpu(resp->fw_build);
2179 if (api_major_version)
2180 *api_major_version = le16_to_cpu(resp->api_major);
2181 if (api_minor_version)
2182 *api_minor_version = le16_to_cpu(resp->api_minor);
2183 }
2184
2185 return status;
2186 }
2187
2188 /**
2189 * i40e_aq_send_driver_version
2190 * @hw: pointer to the hw struct
2191 * @dv: driver's major, minor version
2192 * @cmd_details: pointer to command details structure or NULL
2193 *
2194 * Send the driver version to the firmware
2195 **/
2196 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2197 struct i40e_driver_version *dv,
2198 struct i40e_asq_cmd_details *cmd_details)
2199 {
2200 struct i40e_aq_desc desc;
2201 struct i40e_aqc_driver_version *cmd =
2202 (struct i40e_aqc_driver_version *)&desc.params.raw;
2203 i40e_status status;
2204 u16 len;
2205
2206 if (dv == NULL)
2207 return I40E_ERR_PARAM;
2208
2209 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2210
2211 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2212 cmd->driver_major_ver = dv->major_version;
2213 cmd->driver_minor_ver = dv->minor_version;
2214 cmd->driver_build_ver = dv->build_version;
2215 cmd->driver_subbuild_ver = dv->subbuild_version;
2216
2217 len = 0;
2218 while (len < sizeof(dv->driver_string) &&
2219 (dv->driver_string[len] < 0x80) &&
2220 dv->driver_string[len])
2221 len++;
2222 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2223 len, cmd_details);
2224
2225 return status;
2226 }
2227
2228 /**
2229 * i40e_get_link_status - get status of the HW network link
2230 * @hw: pointer to the hw struct
2231 * @link_up: pointer to bool (true/false = linkup/linkdown)
2232 *
2233 * Variable link_up true if link is up, false if link is down.
2234 * The variable link_up is invalid if returned value of status != 0
2235 *
2236 * Side effect: LinkStatusEvent reporting becomes enabled
2237 **/
2238 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2239 {
2240 i40e_status status = 0;
2241
2242 if (hw->phy.get_link_info) {
2243 status = i40e_update_link_info(hw);
2244
2245 if (status)
2246 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2247 status);
2248 }
2249
2250 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2251
2252 return status;
2253 }
2254
2255 /**
2256 * i40e_updatelink_status - update status of the HW network link
2257 * @hw: pointer to the hw struct
2258 **/
2259 i40e_status i40e_update_link_info(struct i40e_hw *hw)
2260 {
2261 struct i40e_aq_get_phy_abilities_resp abilities;
2262 i40e_status status = 0;
2263
2264 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2265 if (status)
2266 return status;
2267
2268 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2269 status = i40e_aq_get_phy_capabilities(hw, false, false,
2270 &abilities, NULL);
2271 if (status)
2272 return status;
2273
2274 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2275 sizeof(hw->phy.link_info.module_type));
2276 }
2277
2278 return status;
2279 }
2280
2281 /**
2282 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2283 * @hw: pointer to the hw struct
2284 * @uplink_seid: the MAC or other gizmo SEID
2285 * @downlink_seid: the VSI SEID
2286 * @enabled_tc: bitmap of TCs to be enabled
2287 * @default_port: true for default port VSI, false for control port
2288 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2289 * @veb_seid: pointer to where to put the resulting VEB SEID
2290 * @cmd_details: pointer to command details structure or NULL
2291 *
2292 * This asks the FW to add a VEB between the uplink and downlink
2293 * elements. If the uplink SEID is 0, this will be a floating VEB.
2294 **/
2295 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2296 u16 downlink_seid, u8 enabled_tc,
2297 bool default_port, bool enable_l2_filtering,
2298 u16 *veb_seid,
2299 struct i40e_asq_cmd_details *cmd_details)
2300 {
2301 struct i40e_aq_desc desc;
2302 struct i40e_aqc_add_veb *cmd =
2303 (struct i40e_aqc_add_veb *)&desc.params.raw;
2304 struct i40e_aqc_add_veb_completion *resp =
2305 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2306 i40e_status status;
2307 u16 veb_flags = 0;
2308
2309 /* SEIDs need to either both be set or both be 0 for floating VEB */
2310 if (!!uplink_seid != !!downlink_seid)
2311 return I40E_ERR_PARAM;
2312
2313 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2314
2315 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2316 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2317 cmd->enable_tcs = enabled_tc;
2318 if (!uplink_seid)
2319 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2320 if (default_port)
2321 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2322 else
2323 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2324
2325 if (enable_l2_filtering)
2326 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2327
2328 cmd->veb_flags = cpu_to_le16(veb_flags);
2329
2330 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2331
2332 if (!status && veb_seid)
2333 *veb_seid = le16_to_cpu(resp->veb_seid);
2334
2335 return status;
2336 }
2337
2338 /**
2339 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2340 * @hw: pointer to the hw struct
2341 * @veb_seid: the SEID of the VEB to query
2342 * @switch_id: the uplink switch id
2343 * @floating: set to true if the VEB is floating
2344 * @statistic_index: index of the stats counter block for this VEB
2345 * @vebs_used: number of VEB's used by function
2346 * @vebs_free: total VEB's not reserved by any function
2347 * @cmd_details: pointer to command details structure or NULL
2348 *
2349 * This retrieves the parameters for a particular VEB, specified by
2350 * uplink_seid, and returns them to the caller.
2351 **/
2352 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2353 u16 veb_seid, u16 *switch_id,
2354 bool *floating, u16 *statistic_index,
2355 u16 *vebs_used, u16 *vebs_free,
2356 struct i40e_asq_cmd_details *cmd_details)
2357 {
2358 struct i40e_aq_desc desc;
2359 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2360 (struct i40e_aqc_get_veb_parameters_completion *)
2361 &desc.params.raw;
2362 i40e_status status;
2363
2364 if (veb_seid == 0)
2365 return I40E_ERR_PARAM;
2366
2367 i40e_fill_default_direct_cmd_desc(&desc,
2368 i40e_aqc_opc_get_veb_parameters);
2369 cmd_resp->seid = cpu_to_le16(veb_seid);
2370
2371 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2372 if (status)
2373 goto get_veb_exit;
2374
2375 if (switch_id)
2376 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2377 if (statistic_index)
2378 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2379 if (vebs_used)
2380 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2381 if (vebs_free)
2382 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2383 if (floating) {
2384 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2385
2386 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2387 *floating = true;
2388 else
2389 *floating = false;
2390 }
2391
2392 get_veb_exit:
2393 return status;
2394 }
2395
2396 /**
2397 * i40e_aq_add_macvlan
2398 * @hw: pointer to the hw struct
2399 * @seid: VSI for the mac address
2400 * @mv_list: list of macvlans to be added
2401 * @count: length of the list
2402 * @cmd_details: pointer to command details structure or NULL
2403 *
2404 * Add MAC/VLAN addresses to the HW filtering
2405 **/
2406 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2407 struct i40e_aqc_add_macvlan_element_data *mv_list,
2408 u16 count, struct i40e_asq_cmd_details *cmd_details)
2409 {
2410 struct i40e_aq_desc desc;
2411 struct i40e_aqc_macvlan *cmd =
2412 (struct i40e_aqc_macvlan *)&desc.params.raw;
2413 i40e_status status;
2414 u16 buf_size;
2415
2416 if (count == 0 || !mv_list || !hw)
2417 return I40E_ERR_PARAM;
2418
2419 buf_size = count * sizeof(*mv_list);
2420
2421 /* prep the rest of the request */
2422 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2423 cmd->num_addresses = cpu_to_le16(count);
2424 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2425 cmd->seid[1] = 0;
2426 cmd->seid[2] = 0;
2427
2428 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2429 if (buf_size > I40E_AQ_LARGE_BUF)
2430 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2431
2432 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2433 cmd_details);
2434
2435 return status;
2436 }
2437
2438 /**
2439 * i40e_aq_remove_macvlan
2440 * @hw: pointer to the hw struct
2441 * @seid: VSI for the mac address
2442 * @mv_list: list of macvlans to be removed
2443 * @count: length of the list
2444 * @cmd_details: pointer to command details structure or NULL
2445 *
2446 * Remove MAC/VLAN addresses from the HW filtering
2447 **/
2448 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2449 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2450 u16 count, struct i40e_asq_cmd_details *cmd_details)
2451 {
2452 struct i40e_aq_desc desc;
2453 struct i40e_aqc_macvlan *cmd =
2454 (struct i40e_aqc_macvlan *)&desc.params.raw;
2455 i40e_status status;
2456 u16 buf_size;
2457
2458 if (count == 0 || !mv_list || !hw)
2459 return I40E_ERR_PARAM;
2460
2461 buf_size = count * sizeof(*mv_list);
2462
2463 /* prep the rest of the request */
2464 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2465 cmd->num_addresses = cpu_to_le16(count);
2466 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2467 cmd->seid[1] = 0;
2468 cmd->seid[2] = 0;
2469
2470 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2471 if (buf_size > I40E_AQ_LARGE_BUF)
2472 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2473
2474 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2475 cmd_details);
2476
2477 return status;
2478 }
2479
2480 /**
2481 * i40e_aq_send_msg_to_vf
2482 * @hw: pointer to the hardware structure
2483 * @vfid: VF id to send msg
2484 * @v_opcode: opcodes for VF-PF communication
2485 * @v_retval: return error code
2486 * @msg: pointer to the msg buffer
2487 * @msglen: msg length
2488 * @cmd_details: pointer to command details
2489 *
2490 * send msg to vf
2491 **/
2492 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2493 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2494 struct i40e_asq_cmd_details *cmd_details)
2495 {
2496 struct i40e_aq_desc desc;
2497 struct i40e_aqc_pf_vf_message *cmd =
2498 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2499 i40e_status status;
2500
2501 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2502 cmd->id = cpu_to_le32(vfid);
2503 desc.cookie_high = cpu_to_le32(v_opcode);
2504 desc.cookie_low = cpu_to_le32(v_retval);
2505 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2506 if (msglen) {
2507 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2508 I40E_AQ_FLAG_RD));
2509 if (msglen > I40E_AQ_LARGE_BUF)
2510 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2511 desc.datalen = cpu_to_le16(msglen);
2512 }
2513 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2514
2515 return status;
2516 }
2517
2518 /**
2519 * i40e_aq_debug_read_register
2520 * @hw: pointer to the hw struct
2521 * @reg_addr: register address
2522 * @reg_val: register value
2523 * @cmd_details: pointer to command details structure or NULL
2524 *
2525 * Read the register using the admin queue commands
2526 **/
2527 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2528 u32 reg_addr, u64 *reg_val,
2529 struct i40e_asq_cmd_details *cmd_details)
2530 {
2531 struct i40e_aq_desc desc;
2532 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2533 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2534 i40e_status status;
2535
2536 if (reg_val == NULL)
2537 return I40E_ERR_PARAM;
2538
2539 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2540
2541 cmd_resp->address = cpu_to_le32(reg_addr);
2542
2543 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2544
2545 if (!status) {
2546 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2547 (u64)le32_to_cpu(cmd_resp->value_low);
2548 }
2549
2550 return status;
2551 }
2552
2553 /**
2554 * i40e_aq_debug_write_register
2555 * @hw: pointer to the hw struct
2556 * @reg_addr: register address
2557 * @reg_val: register value
2558 * @cmd_details: pointer to command details structure or NULL
2559 *
2560 * Write to a register using the admin queue commands
2561 **/
2562 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2563 u32 reg_addr, u64 reg_val,
2564 struct i40e_asq_cmd_details *cmd_details)
2565 {
2566 struct i40e_aq_desc desc;
2567 struct i40e_aqc_debug_reg_read_write *cmd =
2568 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2569 i40e_status status;
2570
2571 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2572
2573 cmd->address = cpu_to_le32(reg_addr);
2574 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2575 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2576
2577 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2578
2579 return status;
2580 }
2581
2582 /**
2583 * i40e_aq_set_hmc_resource_profile
2584 * @hw: pointer to the hw struct
2585 * @profile: type of profile the HMC is to be set as
2586 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2587 * @cmd_details: pointer to command details structure or NULL
2588 *
2589 * set the HMC profile of the device.
2590 **/
2591 i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2592 enum i40e_aq_hmc_profile profile,
2593 u8 pe_vf_enabled_count,
2594 struct i40e_asq_cmd_details *cmd_details)
2595 {
2596 struct i40e_aq_desc desc;
2597 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2598 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2599 i40e_status status;
2600
2601 i40e_fill_default_direct_cmd_desc(&desc,
2602 i40e_aqc_opc_set_hmc_resource_profile);
2603
2604 cmd->pm_profile = (u8)profile;
2605 cmd->pe_vf_enabled = pe_vf_enabled_count;
2606
2607 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2608
2609 return status;
2610 }
2611
2612 /**
2613 * i40e_aq_request_resource
2614 * @hw: pointer to the hw struct
2615 * @resource: resource id
2616 * @access: access type
2617 * @sdp_number: resource number
2618 * @timeout: the maximum time in ms that the driver may hold the resource
2619 * @cmd_details: pointer to command details structure or NULL
2620 *
2621 * requests common resource using the admin queue commands
2622 **/
2623 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2624 enum i40e_aq_resources_ids resource,
2625 enum i40e_aq_resource_access_type access,
2626 u8 sdp_number, u64 *timeout,
2627 struct i40e_asq_cmd_details *cmd_details)
2628 {
2629 struct i40e_aq_desc desc;
2630 struct i40e_aqc_request_resource *cmd_resp =
2631 (struct i40e_aqc_request_resource *)&desc.params.raw;
2632 i40e_status status;
2633
2634 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2635
2636 cmd_resp->resource_id = cpu_to_le16(resource);
2637 cmd_resp->access_type = cpu_to_le16(access);
2638 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2639
2640 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2641 /* The completion specifies the maximum time in ms that the driver
2642 * may hold the resource in the Timeout field.
2643 * If the resource is held by someone else, the command completes with
2644 * busy return value and the timeout field indicates the maximum time
2645 * the current owner of the resource has to free it.
2646 */
2647 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2648 *timeout = le32_to_cpu(cmd_resp->timeout);
2649
2650 return status;
2651 }
2652
2653 /**
2654 * i40e_aq_release_resource
2655 * @hw: pointer to the hw struct
2656 * @resource: resource id
2657 * @sdp_number: resource number
2658 * @cmd_details: pointer to command details structure or NULL
2659 *
2660 * release common resource using the admin queue commands
2661 **/
2662 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2663 enum i40e_aq_resources_ids resource,
2664 u8 sdp_number,
2665 struct i40e_asq_cmd_details *cmd_details)
2666 {
2667 struct i40e_aq_desc desc;
2668 struct i40e_aqc_request_resource *cmd =
2669 (struct i40e_aqc_request_resource *)&desc.params.raw;
2670 i40e_status status;
2671
2672 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2673
2674 cmd->resource_id = cpu_to_le16(resource);
2675 cmd->resource_number = cpu_to_le32(sdp_number);
2676
2677 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2678
2679 return status;
2680 }
2681
2682 /**
2683 * i40e_aq_read_nvm
2684 * @hw: pointer to the hw struct
2685 * @module_pointer: module pointer location in words from the NVM beginning
2686 * @offset: byte offset from the module beginning
2687 * @length: length of the section to be read (in bytes from the offset)
2688 * @data: command buffer (size [bytes] = length)
2689 * @last_command: tells if this is the last command in a series
2690 * @cmd_details: pointer to command details structure or NULL
2691 *
2692 * Read the NVM using the admin queue commands
2693 **/
2694 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2695 u32 offset, u16 length, void *data,
2696 bool last_command,
2697 struct i40e_asq_cmd_details *cmd_details)
2698 {
2699 struct i40e_aq_desc desc;
2700 struct i40e_aqc_nvm_update *cmd =
2701 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2702 i40e_status status;
2703
2704 /* In offset the highest byte must be zeroed. */
2705 if (offset & 0xFF000000) {
2706 status = I40E_ERR_PARAM;
2707 goto i40e_aq_read_nvm_exit;
2708 }
2709
2710 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2711
2712 /* If this is the last command in a series, set the proper flag. */
2713 if (last_command)
2714 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2715 cmd->module_pointer = module_pointer;
2716 cmd->offset = cpu_to_le32(offset);
2717 cmd->length = cpu_to_le16(length);
2718
2719 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2720 if (length > I40E_AQ_LARGE_BUF)
2721 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2722
2723 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2724
2725 i40e_aq_read_nvm_exit:
2726 return status;
2727 }
2728
2729 /**
2730 * i40e_aq_erase_nvm
2731 * @hw: pointer to the hw struct
2732 * @module_pointer: module pointer location in words from the NVM beginning
2733 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2734 * @length: length of the section to be erased (expressed in 4 KB)
2735 * @last_command: tells if this is the last command in a series
2736 * @cmd_details: pointer to command details structure or NULL
2737 *
2738 * Erase the NVM sector using the admin queue commands
2739 **/
2740 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2741 u32 offset, u16 length, bool last_command,
2742 struct i40e_asq_cmd_details *cmd_details)
2743 {
2744 struct i40e_aq_desc desc;
2745 struct i40e_aqc_nvm_update *cmd =
2746 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2747 i40e_status status;
2748
2749 /* In offset the highest byte must be zeroed. */
2750 if (offset & 0xFF000000) {
2751 status = I40E_ERR_PARAM;
2752 goto i40e_aq_erase_nvm_exit;
2753 }
2754
2755 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2756
2757 /* If this is the last command in a series, set the proper flag. */
2758 if (last_command)
2759 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2760 cmd->module_pointer = module_pointer;
2761 cmd->offset = cpu_to_le32(offset);
2762 cmd->length = cpu_to_le16(length);
2763
2764 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2765
2766 i40e_aq_erase_nvm_exit:
2767 return status;
2768 }
2769
2770 /**
2771 * i40e_parse_discover_capabilities
2772 * @hw: pointer to the hw struct
2773 * @buff: pointer to a buffer containing device/function capability records
2774 * @cap_count: number of capability records in the list
2775 * @list_type_opc: type of capabilities list to parse
2776 *
2777 * Parse the device/function capabilities list.
2778 **/
2779 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2780 u32 cap_count,
2781 enum i40e_admin_queue_opc list_type_opc)
2782 {
2783 struct i40e_aqc_list_capabilities_element_resp *cap;
2784 u32 valid_functions, num_functions;
2785 u32 number, logical_id, phys_id;
2786 struct i40e_hw_capabilities *p;
2787 u8 major_rev;
2788 u32 i = 0;
2789 u16 id;
2790
2791 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2792
2793 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2794 p = &hw->dev_caps;
2795 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2796 p = &hw->func_caps;
2797 else
2798 return;
2799
2800 for (i = 0; i < cap_count; i++, cap++) {
2801 id = le16_to_cpu(cap->id);
2802 number = le32_to_cpu(cap->number);
2803 logical_id = le32_to_cpu(cap->logical_id);
2804 phys_id = le32_to_cpu(cap->phys_id);
2805 major_rev = cap->major_rev;
2806
2807 switch (id) {
2808 case I40E_AQ_CAP_ID_SWITCH_MODE:
2809 p->switch_mode = number;
2810 break;
2811 case I40E_AQ_CAP_ID_MNG_MODE:
2812 p->management_mode = number;
2813 break;
2814 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
2815 p->npar_enable = number;
2816 break;
2817 case I40E_AQ_CAP_ID_OS2BMC_CAP:
2818 p->os2bmc = number;
2819 break;
2820 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
2821 p->valid_functions = number;
2822 break;
2823 case I40E_AQ_CAP_ID_SRIOV:
2824 if (number == 1)
2825 p->sr_iov_1_1 = true;
2826 break;
2827 case I40E_AQ_CAP_ID_VF:
2828 p->num_vfs = number;
2829 p->vf_base_id = logical_id;
2830 break;
2831 case I40E_AQ_CAP_ID_VMDQ:
2832 if (number == 1)
2833 p->vmdq = true;
2834 break;
2835 case I40E_AQ_CAP_ID_8021QBG:
2836 if (number == 1)
2837 p->evb_802_1_qbg = true;
2838 break;
2839 case I40E_AQ_CAP_ID_8021QBR:
2840 if (number == 1)
2841 p->evb_802_1_qbh = true;
2842 break;
2843 case I40E_AQ_CAP_ID_VSI:
2844 p->num_vsis = number;
2845 break;
2846 case I40E_AQ_CAP_ID_DCB:
2847 if (number == 1) {
2848 p->dcb = true;
2849 p->enabled_tcmap = logical_id;
2850 p->maxtc = phys_id;
2851 }
2852 break;
2853 case I40E_AQ_CAP_ID_FCOE:
2854 if (number == 1)
2855 p->fcoe = true;
2856 break;
2857 case I40E_AQ_CAP_ID_ISCSI:
2858 if (number == 1)
2859 p->iscsi = true;
2860 break;
2861 case I40E_AQ_CAP_ID_RSS:
2862 p->rss = true;
2863 p->rss_table_size = number;
2864 p->rss_table_entry_width = logical_id;
2865 break;
2866 case I40E_AQ_CAP_ID_RXQ:
2867 p->num_rx_qp = number;
2868 p->base_queue = phys_id;
2869 break;
2870 case I40E_AQ_CAP_ID_TXQ:
2871 p->num_tx_qp = number;
2872 p->base_queue = phys_id;
2873 break;
2874 case I40E_AQ_CAP_ID_MSIX:
2875 p->num_msix_vectors = number;
2876 break;
2877 case I40E_AQ_CAP_ID_VF_MSIX:
2878 p->num_msix_vectors_vf = number;
2879 break;
2880 case I40E_AQ_CAP_ID_FLEX10:
2881 if (major_rev == 1) {
2882 if (number == 1) {
2883 p->flex10_enable = true;
2884 p->flex10_capable = true;
2885 }
2886 } else {
2887 /* Capability revision >= 2 */
2888 if (number & 1)
2889 p->flex10_enable = true;
2890 if (number & 2)
2891 p->flex10_capable = true;
2892 }
2893 p->flex10_mode = logical_id;
2894 p->flex10_status = phys_id;
2895 break;
2896 case I40E_AQ_CAP_ID_CEM:
2897 if (number == 1)
2898 p->mgmt_cem = true;
2899 break;
2900 case I40E_AQ_CAP_ID_IWARP:
2901 if (number == 1)
2902 p->iwarp = true;
2903 break;
2904 case I40E_AQ_CAP_ID_LED:
2905 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2906 p->led[phys_id] = true;
2907 break;
2908 case I40E_AQ_CAP_ID_SDP:
2909 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2910 p->sdp[phys_id] = true;
2911 break;
2912 case I40E_AQ_CAP_ID_MDIO:
2913 if (number == 1) {
2914 p->mdio_port_num = phys_id;
2915 p->mdio_port_mode = logical_id;
2916 }
2917 break;
2918 case I40E_AQ_CAP_ID_1588:
2919 if (number == 1)
2920 p->ieee_1588 = true;
2921 break;
2922 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
2923 p->fd = true;
2924 p->fd_filters_guaranteed = number;
2925 p->fd_filters_best_effort = logical_id;
2926 break;
2927 case I40E_AQ_CAP_ID_WSR_PROT:
2928 p->wr_csr_prot = (u64)number;
2929 p->wr_csr_prot |= (u64)logical_id << 32;
2930 break;
2931 default:
2932 break;
2933 }
2934 }
2935
2936 if (p->fcoe)
2937 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
2938
2939 /* Software override ensuring FCoE is disabled if npar or mfp
2940 * mode because it is not supported in these modes.
2941 */
2942 if (p->npar_enable || p->flex10_enable)
2943 p->fcoe = false;
2944
2945 /* count the enabled ports (aka the "not disabled" ports) */
2946 hw->num_ports = 0;
2947 for (i = 0; i < 4; i++) {
2948 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
2949 u64 port_cfg = 0;
2950
2951 /* use AQ read to get the physical register offset instead
2952 * of the port relative offset
2953 */
2954 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
2955 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
2956 hw->num_ports++;
2957 }
2958
2959 valid_functions = p->valid_functions;
2960 num_functions = 0;
2961 while (valid_functions) {
2962 if (valid_functions & 1)
2963 num_functions++;
2964 valid_functions >>= 1;
2965 }
2966
2967 /* partition id is 1-based, and functions are evenly spread
2968 * across the ports as partitions
2969 */
2970 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
2971 hw->num_partitions = num_functions / hw->num_ports;
2972
2973 /* additional HW specific goodies that might
2974 * someday be HW version specific
2975 */
2976 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2977 }
2978
2979 /**
2980 * i40e_aq_discover_capabilities
2981 * @hw: pointer to the hw struct
2982 * @buff: a virtual buffer to hold the capabilities
2983 * @buff_size: Size of the virtual buffer
2984 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2985 * @list_type_opc: capabilities type to discover - pass in the command opcode
2986 * @cmd_details: pointer to command details structure or NULL
2987 *
2988 * Get the device capabilities descriptions from the firmware
2989 **/
2990 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
2991 void *buff, u16 buff_size, u16 *data_size,
2992 enum i40e_admin_queue_opc list_type_opc,
2993 struct i40e_asq_cmd_details *cmd_details)
2994 {
2995 struct i40e_aqc_list_capabilites *cmd;
2996 struct i40e_aq_desc desc;
2997 i40e_status status = 0;
2998
2999 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3000
3001 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3002 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3003 status = I40E_ERR_PARAM;
3004 goto exit;
3005 }
3006
3007 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3008
3009 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3010 if (buff_size > I40E_AQ_LARGE_BUF)
3011 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3012
3013 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3014 *data_size = le16_to_cpu(desc.datalen);
3015
3016 if (status)
3017 goto exit;
3018
3019 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3020 list_type_opc);
3021
3022 exit:
3023 return status;
3024 }
3025
3026 /**
3027 * i40e_aq_update_nvm
3028 * @hw: pointer to the hw struct
3029 * @module_pointer: module pointer location in words from the NVM beginning
3030 * @offset: byte offset from the module beginning
3031 * @length: length of the section to be written (in bytes from the offset)
3032 * @data: command buffer (size [bytes] = length)
3033 * @last_command: tells if this is the last command in a series
3034 * @cmd_details: pointer to command details structure or NULL
3035 *
3036 * Update the NVM using the admin queue commands
3037 **/
3038 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3039 u32 offset, u16 length, void *data,
3040 bool last_command,
3041 struct i40e_asq_cmd_details *cmd_details)
3042 {
3043 struct i40e_aq_desc desc;
3044 struct i40e_aqc_nvm_update *cmd =
3045 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3046 i40e_status status;
3047
3048 /* In offset the highest byte must be zeroed. */
3049 if (offset & 0xFF000000) {
3050 status = I40E_ERR_PARAM;
3051 goto i40e_aq_update_nvm_exit;
3052 }
3053
3054 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3055
3056 /* If this is the last command in a series, set the proper flag. */
3057 if (last_command)
3058 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3059 cmd->module_pointer = module_pointer;
3060 cmd->offset = cpu_to_le32(offset);
3061 cmd->length = cpu_to_le16(length);
3062
3063 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3064 if (length > I40E_AQ_LARGE_BUF)
3065 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3066
3067 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3068
3069 i40e_aq_update_nvm_exit:
3070 return status;
3071 }
3072
3073 /**
3074 * i40e_aq_get_lldp_mib
3075 * @hw: pointer to the hw struct
3076 * @bridge_type: type of bridge requested
3077 * @mib_type: Local, Remote or both Local and Remote MIBs
3078 * @buff: pointer to a user supplied buffer to store the MIB block
3079 * @buff_size: size of the buffer (in bytes)
3080 * @local_len : length of the returned Local LLDP MIB
3081 * @remote_len: length of the returned Remote LLDP MIB
3082 * @cmd_details: pointer to command details structure or NULL
3083 *
3084 * Requests the complete LLDP MIB (entire packet).
3085 **/
3086 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3087 u8 mib_type, void *buff, u16 buff_size,
3088 u16 *local_len, u16 *remote_len,
3089 struct i40e_asq_cmd_details *cmd_details)
3090 {
3091 struct i40e_aq_desc desc;
3092 struct i40e_aqc_lldp_get_mib *cmd =
3093 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3094 struct i40e_aqc_lldp_get_mib *resp =
3095 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3096 i40e_status status;
3097
3098 if (buff_size == 0 || !buff)
3099 return I40E_ERR_PARAM;
3100
3101 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3102 /* Indirect Command */
3103 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3104
3105 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3106 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3107 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3108
3109 desc.datalen = cpu_to_le16(buff_size);
3110
3111 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3112 if (buff_size > I40E_AQ_LARGE_BUF)
3113 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3114
3115 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3116 if (!status) {
3117 if (local_len != NULL)
3118 *local_len = le16_to_cpu(resp->local_len);
3119 if (remote_len != NULL)
3120 *remote_len = le16_to_cpu(resp->remote_len);
3121 }
3122
3123 return status;
3124 }
3125
3126 /**
3127 * i40e_aq_cfg_lldp_mib_change_event
3128 * @hw: pointer to the hw struct
3129 * @enable_update: Enable or Disable event posting
3130 * @cmd_details: pointer to command details structure or NULL
3131 *
3132 * Enable or Disable posting of an event on ARQ when LLDP MIB
3133 * associated with the interface changes
3134 **/
3135 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3136 bool enable_update,
3137 struct i40e_asq_cmd_details *cmd_details)
3138 {
3139 struct i40e_aq_desc desc;
3140 struct i40e_aqc_lldp_update_mib *cmd =
3141 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3142 i40e_status status;
3143
3144 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3145
3146 if (!enable_update)
3147 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3148
3149 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3150
3151 return status;
3152 }
3153
3154 /**
3155 * i40e_aq_stop_lldp
3156 * @hw: pointer to the hw struct
3157 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3158 * @cmd_details: pointer to command details structure or NULL
3159 *
3160 * Stop or Shutdown the embedded LLDP Agent
3161 **/
3162 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3163 struct i40e_asq_cmd_details *cmd_details)
3164 {
3165 struct i40e_aq_desc desc;
3166 struct i40e_aqc_lldp_stop *cmd =
3167 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3168 i40e_status status;
3169
3170 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3171
3172 if (shutdown_agent)
3173 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3174
3175 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3176
3177 return status;
3178 }
3179
3180 /**
3181 * i40e_aq_start_lldp
3182 * @hw: pointer to the hw struct
3183 * @cmd_details: pointer to command details structure or NULL
3184 *
3185 * Start the embedded LLDP Agent on all ports.
3186 **/
3187 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3188 struct i40e_asq_cmd_details *cmd_details)
3189 {
3190 struct i40e_aq_desc desc;
3191 struct i40e_aqc_lldp_start *cmd =
3192 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3193 i40e_status status;
3194
3195 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3196
3197 cmd->command = I40E_AQ_LLDP_AGENT_START;
3198
3199 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3200
3201 return status;
3202 }
3203
3204 /**
3205 * i40e_aq_get_cee_dcb_config
3206 * @hw: pointer to the hw struct
3207 * @buff: response buffer that stores CEE operational configuration
3208 * @buff_size: size of the buffer passed
3209 * @cmd_details: pointer to command details structure or NULL
3210 *
3211 * Get CEE DCBX mode operational configuration from firmware
3212 **/
3213 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3214 void *buff, u16 buff_size,
3215 struct i40e_asq_cmd_details *cmd_details)
3216 {
3217 struct i40e_aq_desc desc;
3218 i40e_status status;
3219
3220 if (buff_size == 0 || !buff)
3221 return I40E_ERR_PARAM;
3222
3223 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3224
3225 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3226 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3227 cmd_details);
3228
3229 return status;
3230 }
3231
3232 /**
3233 * i40e_aq_add_udp_tunnel
3234 * @hw: pointer to the hw struct
3235 * @udp_port: the UDP port to add
3236 * @header_len: length of the tunneling header length in DWords
3237 * @protocol_index: protocol index type
3238 * @filter_index: pointer to filter index
3239 * @cmd_details: pointer to command details structure or NULL
3240 **/
3241 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3242 u16 udp_port, u8 protocol_index,
3243 u8 *filter_index,
3244 struct i40e_asq_cmd_details *cmd_details)
3245 {
3246 struct i40e_aq_desc desc;
3247 struct i40e_aqc_add_udp_tunnel *cmd =
3248 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3249 struct i40e_aqc_del_udp_tunnel_completion *resp =
3250 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3251 i40e_status status;
3252
3253 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3254
3255 cmd->udp_port = cpu_to_le16(udp_port);
3256 cmd->protocol_type = protocol_index;
3257
3258 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3259
3260 if (!status && filter_index)
3261 *filter_index = resp->index;
3262
3263 return status;
3264 }
3265
3266 /**
3267 * i40e_aq_del_udp_tunnel
3268 * @hw: pointer to the hw struct
3269 * @index: filter index
3270 * @cmd_details: pointer to command details structure or NULL
3271 **/
3272 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3273 struct i40e_asq_cmd_details *cmd_details)
3274 {
3275 struct i40e_aq_desc desc;
3276 struct i40e_aqc_remove_udp_tunnel *cmd =
3277 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3278 i40e_status status;
3279
3280 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3281
3282 cmd->index = index;
3283
3284 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3285
3286 return status;
3287 }
3288
3289 /**
3290 * i40e_aq_delete_element - Delete switch element
3291 * @hw: pointer to the hw struct
3292 * @seid: the SEID to delete from the switch
3293 * @cmd_details: pointer to command details structure or NULL
3294 *
3295 * This deletes a switch element from the switch.
3296 **/
3297 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3298 struct i40e_asq_cmd_details *cmd_details)
3299 {
3300 struct i40e_aq_desc desc;
3301 struct i40e_aqc_switch_seid *cmd =
3302 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3303 i40e_status status;
3304
3305 if (seid == 0)
3306 return I40E_ERR_PARAM;
3307
3308 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3309
3310 cmd->seid = cpu_to_le16(seid);
3311
3312 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3313
3314 return status;
3315 }
3316
3317 /**
3318 * i40e_aq_dcb_updated - DCB Updated Command
3319 * @hw: pointer to the hw struct
3320 * @cmd_details: pointer to command details structure or NULL
3321 *
3322 * EMP will return when the shared RPB settings have been
3323 * recomputed and modified. The retval field in the descriptor
3324 * will be set to 0 when RPB is modified.
3325 **/
3326 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3327 struct i40e_asq_cmd_details *cmd_details)
3328 {
3329 struct i40e_aq_desc desc;
3330 i40e_status status;
3331
3332 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3333
3334 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3335
3336 return status;
3337 }
3338
3339 /**
3340 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3341 * @hw: pointer to the hw struct
3342 * @seid: seid for the physical port/switching component/vsi
3343 * @buff: Indirect buffer to hold data parameters and response
3344 * @buff_size: Indirect buffer size
3345 * @opcode: Tx scheduler AQ command opcode
3346 * @cmd_details: pointer to command details structure or NULL
3347 *
3348 * Generic command handler for Tx scheduler AQ commands
3349 **/
3350 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3351 void *buff, u16 buff_size,
3352 enum i40e_admin_queue_opc opcode,
3353 struct i40e_asq_cmd_details *cmd_details)
3354 {
3355 struct i40e_aq_desc desc;
3356 struct i40e_aqc_tx_sched_ind *cmd =
3357 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3358 i40e_status status;
3359 bool cmd_param_flag = false;
3360
3361 switch (opcode) {
3362 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3363 case i40e_aqc_opc_configure_vsi_tc_bw:
3364 case i40e_aqc_opc_enable_switching_comp_ets:
3365 case i40e_aqc_opc_modify_switching_comp_ets:
3366 case i40e_aqc_opc_disable_switching_comp_ets:
3367 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3368 case i40e_aqc_opc_configure_switching_comp_bw_config:
3369 cmd_param_flag = true;
3370 break;
3371 case i40e_aqc_opc_query_vsi_bw_config:
3372 case i40e_aqc_opc_query_vsi_ets_sla_config:
3373 case i40e_aqc_opc_query_switching_comp_ets_config:
3374 case i40e_aqc_opc_query_port_ets_config:
3375 case i40e_aqc_opc_query_switching_comp_bw_config:
3376 cmd_param_flag = false;
3377 break;
3378 default:
3379 return I40E_ERR_PARAM;
3380 }
3381
3382 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3383
3384 /* Indirect command */
3385 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3386 if (cmd_param_flag)
3387 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3388 if (buff_size > I40E_AQ_LARGE_BUF)
3389 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3390
3391 desc.datalen = cpu_to_le16(buff_size);
3392
3393 cmd->vsi_seid = cpu_to_le16(seid);
3394
3395 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3396
3397 return status;
3398 }
3399
3400 /**
3401 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3402 * @hw: pointer to the hw struct
3403 * @seid: VSI seid
3404 * @credit: BW limit credits (0 = disabled)
3405 * @max_credit: Max BW limit credits
3406 * @cmd_details: pointer to command details structure or NULL
3407 **/
3408 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3409 u16 seid, u16 credit, u8 max_credit,
3410 struct i40e_asq_cmd_details *cmd_details)
3411 {
3412 struct i40e_aq_desc desc;
3413 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3414 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3415 i40e_status status;
3416
3417 i40e_fill_default_direct_cmd_desc(&desc,
3418 i40e_aqc_opc_configure_vsi_bw_limit);
3419
3420 cmd->vsi_seid = cpu_to_le16(seid);
3421 cmd->credit = cpu_to_le16(credit);
3422 cmd->max_credit = max_credit;
3423
3424 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3425
3426 return status;
3427 }
3428
3429 /**
3430 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3431 * @hw: pointer to the hw struct
3432 * @seid: VSI seid
3433 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3434 * @cmd_details: pointer to command details structure or NULL
3435 **/
3436 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3437 u16 seid,
3438 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3439 struct i40e_asq_cmd_details *cmd_details)
3440 {
3441 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3442 i40e_aqc_opc_configure_vsi_tc_bw,
3443 cmd_details);
3444 }
3445
3446 /**
3447 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3448 * @hw: pointer to the hw struct
3449 * @seid: seid of the switching component connected to Physical Port
3450 * @ets_data: Buffer holding ETS parameters
3451 * @cmd_details: pointer to command details structure or NULL
3452 **/
3453 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3454 u16 seid,
3455 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3456 enum i40e_admin_queue_opc opcode,
3457 struct i40e_asq_cmd_details *cmd_details)
3458 {
3459 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3460 sizeof(*ets_data), opcode, cmd_details);
3461 }
3462
3463 /**
3464 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3465 * @hw: pointer to the hw struct
3466 * @seid: seid of the switching component
3467 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3468 * @cmd_details: pointer to command details structure or NULL
3469 **/
3470 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3471 u16 seid,
3472 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3473 struct i40e_asq_cmd_details *cmd_details)
3474 {
3475 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3476 i40e_aqc_opc_configure_switching_comp_bw_config,
3477 cmd_details);
3478 }
3479
3480 /**
3481 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3482 * @hw: pointer to the hw struct
3483 * @seid: seid of the VSI
3484 * @bw_data: Buffer to hold VSI BW configuration
3485 * @cmd_details: pointer to command details structure or NULL
3486 **/
3487 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3488 u16 seid,
3489 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3490 struct i40e_asq_cmd_details *cmd_details)
3491 {
3492 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3493 i40e_aqc_opc_query_vsi_bw_config,
3494 cmd_details);
3495 }
3496
3497 /**
3498 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3499 * @hw: pointer to the hw struct
3500 * @seid: seid of the VSI
3501 * @bw_data: Buffer to hold VSI BW configuration per TC
3502 * @cmd_details: pointer to command details structure or NULL
3503 **/
3504 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3505 u16 seid,
3506 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3507 struct i40e_asq_cmd_details *cmd_details)
3508 {
3509 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3510 i40e_aqc_opc_query_vsi_ets_sla_config,
3511 cmd_details);
3512 }
3513
3514 /**
3515 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3516 * @hw: pointer to the hw struct
3517 * @seid: seid of the switching component
3518 * @bw_data: Buffer to hold switching component's per TC BW config
3519 * @cmd_details: pointer to command details structure or NULL
3520 **/
3521 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3522 u16 seid,
3523 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3524 struct i40e_asq_cmd_details *cmd_details)
3525 {
3526 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3527 i40e_aqc_opc_query_switching_comp_ets_config,
3528 cmd_details);
3529 }
3530
3531 /**
3532 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3533 * @hw: pointer to the hw struct
3534 * @seid: seid of the VSI or switching component connected to Physical Port
3535 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3536 * @cmd_details: pointer to command details structure or NULL
3537 **/
3538 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3539 u16 seid,
3540 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3541 struct i40e_asq_cmd_details *cmd_details)
3542 {
3543 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3544 i40e_aqc_opc_query_port_ets_config,
3545 cmd_details);
3546 }
3547
3548 /**
3549 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3550 * @hw: pointer to the hw struct
3551 * @seid: seid of the switching component
3552 * @bw_data: Buffer to hold switching component's BW configuration
3553 * @cmd_details: pointer to command details structure or NULL
3554 **/
3555 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3556 u16 seid,
3557 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3558 struct i40e_asq_cmd_details *cmd_details)
3559 {
3560 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3561 i40e_aqc_opc_query_switching_comp_bw_config,
3562 cmd_details);
3563 }
3564
3565 /**
3566 * i40e_validate_filter_settings
3567 * @hw: pointer to the hardware structure
3568 * @settings: Filter control settings
3569 *
3570 * Check and validate the filter control settings passed.
3571 * The function checks for the valid filter/context sizes being
3572 * passed for FCoE and PE.
3573 *
3574 * Returns 0 if the values passed are valid and within
3575 * range else returns an error.
3576 **/
3577 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3578 struct i40e_filter_control_settings *settings)
3579 {
3580 u32 fcoe_cntx_size, fcoe_filt_size;
3581 u32 pe_cntx_size, pe_filt_size;
3582 u32 fcoe_fmax;
3583 u32 val;
3584
3585 /* Validate FCoE settings passed */
3586 switch (settings->fcoe_filt_num) {
3587 case I40E_HASH_FILTER_SIZE_1K:
3588 case I40E_HASH_FILTER_SIZE_2K:
3589 case I40E_HASH_FILTER_SIZE_4K:
3590 case I40E_HASH_FILTER_SIZE_8K:
3591 case I40E_HASH_FILTER_SIZE_16K:
3592 case I40E_HASH_FILTER_SIZE_32K:
3593 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3594 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3595 break;
3596 default:
3597 return I40E_ERR_PARAM;
3598 }
3599
3600 switch (settings->fcoe_cntx_num) {
3601 case I40E_DMA_CNTX_SIZE_512:
3602 case I40E_DMA_CNTX_SIZE_1K:
3603 case I40E_DMA_CNTX_SIZE_2K:
3604 case I40E_DMA_CNTX_SIZE_4K:
3605 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3606 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3607 break;
3608 default:
3609 return I40E_ERR_PARAM;
3610 }
3611
3612 /* Validate PE settings passed */
3613 switch (settings->pe_filt_num) {
3614 case I40E_HASH_FILTER_SIZE_1K:
3615 case I40E_HASH_FILTER_SIZE_2K:
3616 case I40E_HASH_FILTER_SIZE_4K:
3617 case I40E_HASH_FILTER_SIZE_8K:
3618 case I40E_HASH_FILTER_SIZE_16K:
3619 case I40E_HASH_FILTER_SIZE_32K:
3620 case I40E_HASH_FILTER_SIZE_64K:
3621 case I40E_HASH_FILTER_SIZE_128K:
3622 case I40E_HASH_FILTER_SIZE_256K:
3623 case I40E_HASH_FILTER_SIZE_512K:
3624 case I40E_HASH_FILTER_SIZE_1M:
3625 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3626 pe_filt_size <<= (u32)settings->pe_filt_num;
3627 break;
3628 default:
3629 return I40E_ERR_PARAM;
3630 }
3631
3632 switch (settings->pe_cntx_num) {
3633 case I40E_DMA_CNTX_SIZE_512:
3634 case I40E_DMA_CNTX_SIZE_1K:
3635 case I40E_DMA_CNTX_SIZE_2K:
3636 case I40E_DMA_CNTX_SIZE_4K:
3637 case I40E_DMA_CNTX_SIZE_8K:
3638 case I40E_DMA_CNTX_SIZE_16K:
3639 case I40E_DMA_CNTX_SIZE_32K:
3640 case I40E_DMA_CNTX_SIZE_64K:
3641 case I40E_DMA_CNTX_SIZE_128K:
3642 case I40E_DMA_CNTX_SIZE_256K:
3643 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3644 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3645 break;
3646 default:
3647 return I40E_ERR_PARAM;
3648 }
3649
3650 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3651 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3652 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3653 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3654 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3655 return I40E_ERR_INVALID_SIZE;
3656
3657 return 0;
3658 }
3659
3660 /**
3661 * i40e_set_filter_control
3662 * @hw: pointer to the hardware structure
3663 * @settings: Filter control settings
3664 *
3665 * Set the Queue Filters for PE/FCoE and enable filters required
3666 * for a single PF. It is expected that these settings are programmed
3667 * at the driver initialization time.
3668 **/
3669 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3670 struct i40e_filter_control_settings *settings)
3671 {
3672 i40e_status ret = 0;
3673 u32 hash_lut_size = 0;
3674 u32 val;
3675
3676 if (!settings)
3677 return I40E_ERR_PARAM;
3678
3679 /* Validate the input settings */
3680 ret = i40e_validate_filter_settings(hw, settings);
3681 if (ret)
3682 return ret;
3683
3684 /* Read the PF Queue Filter control register */
3685 val = rd32(hw, I40E_PFQF_CTL_0);
3686
3687 /* Program required PE hash buckets for the PF */
3688 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3689 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3690 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3691 /* Program required PE contexts for the PF */
3692 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3693 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3694 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3695
3696 /* Program required FCoE hash buckets for the PF */
3697 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3698 val |= ((u32)settings->fcoe_filt_num <<
3699 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3700 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3701 /* Program required FCoE DDP contexts for the PF */
3702 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3703 val |= ((u32)settings->fcoe_cntx_num <<
3704 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3705 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3706
3707 /* Program Hash LUT size for the PF */
3708 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3709 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3710 hash_lut_size = 1;
3711 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3712 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3713
3714 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3715 if (settings->enable_fdir)
3716 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3717 if (settings->enable_ethtype)
3718 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3719 if (settings->enable_macvlan)
3720 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3721
3722 wr32(hw, I40E_PFQF_CTL_0, val);
3723
3724 return 0;
3725 }
3726
3727 /**
3728 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3729 * @hw: pointer to the hw struct
3730 * @mac_addr: MAC address to use in the filter
3731 * @ethtype: Ethertype to use in the filter
3732 * @flags: Flags that needs to be applied to the filter
3733 * @vsi_seid: seid of the control VSI
3734 * @queue: VSI queue number to send the packet to
3735 * @is_add: Add control packet filter if True else remove
3736 * @stats: Structure to hold information on control filter counts
3737 * @cmd_details: pointer to command details structure or NULL
3738 *
3739 * This command will Add or Remove control packet filter for a control VSI.
3740 * In return it will update the total number of perfect filter count in
3741 * the stats member.
3742 **/
3743 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3744 u8 *mac_addr, u16 ethtype, u16 flags,
3745 u16 vsi_seid, u16 queue, bool is_add,
3746 struct i40e_control_filter_stats *stats,
3747 struct i40e_asq_cmd_details *cmd_details)
3748 {
3749 struct i40e_aq_desc desc;
3750 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3751 (struct i40e_aqc_add_remove_control_packet_filter *)
3752 &desc.params.raw;
3753 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3754 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3755 &desc.params.raw;
3756 i40e_status status;
3757
3758 if (vsi_seid == 0)
3759 return I40E_ERR_PARAM;
3760
3761 if (is_add) {
3762 i40e_fill_default_direct_cmd_desc(&desc,
3763 i40e_aqc_opc_add_control_packet_filter);
3764 cmd->queue = cpu_to_le16(queue);
3765 } else {
3766 i40e_fill_default_direct_cmd_desc(&desc,
3767 i40e_aqc_opc_remove_control_packet_filter);
3768 }
3769
3770 if (mac_addr)
3771 ether_addr_copy(cmd->mac, mac_addr);
3772
3773 cmd->etype = cpu_to_le16(ethtype);
3774 cmd->flags = cpu_to_le16(flags);
3775 cmd->seid = cpu_to_le16(vsi_seid);
3776
3777 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3778
3779 if (!status && stats) {
3780 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3781 stats->etype_used = le16_to_cpu(resp->etype_used);
3782 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3783 stats->etype_free = le16_to_cpu(resp->etype_free);
3784 }
3785
3786 return status;
3787 }
3788
3789 /**
3790 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
3791 * @hw: pointer to the hw struct
3792 * @seid: VSI seid to add ethertype filter from
3793 **/
3794 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
3795 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
3796 u16 seid)
3797 {
3798 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
3799 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
3800 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
3801 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
3802 i40e_status status;
3803
3804 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
3805 seid, 0, true, NULL,
3806 NULL);
3807 if (status)
3808 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
3809 }
3810
3811 /**
3812 * i40e_aq_alternate_read
3813 * @hw: pointer to the hardware structure
3814 * @reg_addr0: address of first dword to be read
3815 * @reg_val0: pointer for data read from 'reg_addr0'
3816 * @reg_addr1: address of second dword to be read
3817 * @reg_val1: pointer for data read from 'reg_addr1'
3818 *
3819 * Read one or two dwords from alternate structure. Fields are indicated
3820 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
3821 * is not passed then only register at 'reg_addr0' is read.
3822 *
3823 **/
3824 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
3825 u32 reg_addr0, u32 *reg_val0,
3826 u32 reg_addr1, u32 *reg_val1)
3827 {
3828 struct i40e_aq_desc desc;
3829 struct i40e_aqc_alternate_write *cmd_resp =
3830 (struct i40e_aqc_alternate_write *)&desc.params.raw;
3831 i40e_status status;
3832
3833 if (!reg_val0)
3834 return I40E_ERR_PARAM;
3835
3836 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
3837 cmd_resp->address0 = cpu_to_le32(reg_addr0);
3838 cmd_resp->address1 = cpu_to_le32(reg_addr1);
3839
3840 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3841
3842 if (!status) {
3843 *reg_val0 = le32_to_cpu(cmd_resp->data0);
3844
3845 if (reg_val1)
3846 *reg_val1 = le32_to_cpu(cmd_resp->data1);
3847 }
3848
3849 return status;
3850 }
3851
3852 /**
3853 * i40e_aq_resume_port_tx
3854 * @hw: pointer to the hardware structure
3855 * @cmd_details: pointer to command details structure or NULL
3856 *
3857 * Resume port's Tx traffic
3858 **/
3859 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
3860 struct i40e_asq_cmd_details *cmd_details)
3861 {
3862 struct i40e_aq_desc desc;
3863 i40e_status status;
3864
3865 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
3866
3867 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3868
3869 return status;
3870 }
3871
3872 /**
3873 * i40e_set_pci_config_data - store PCI bus info
3874 * @hw: pointer to hardware structure
3875 * @link_status: the link status word from PCI config space
3876 *
3877 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3878 **/
3879 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
3880 {
3881 hw->bus.type = i40e_bus_type_pci_express;
3882
3883 switch (link_status & PCI_EXP_LNKSTA_NLW) {
3884 case PCI_EXP_LNKSTA_NLW_X1:
3885 hw->bus.width = i40e_bus_width_pcie_x1;
3886 break;
3887 case PCI_EXP_LNKSTA_NLW_X2:
3888 hw->bus.width = i40e_bus_width_pcie_x2;
3889 break;
3890 case PCI_EXP_LNKSTA_NLW_X4:
3891 hw->bus.width = i40e_bus_width_pcie_x4;
3892 break;
3893 case PCI_EXP_LNKSTA_NLW_X8:
3894 hw->bus.width = i40e_bus_width_pcie_x8;
3895 break;
3896 default:
3897 hw->bus.width = i40e_bus_width_unknown;
3898 break;
3899 }
3900
3901 switch (link_status & PCI_EXP_LNKSTA_CLS) {
3902 case PCI_EXP_LNKSTA_CLS_2_5GB:
3903 hw->bus.speed = i40e_bus_speed_2500;
3904 break;
3905 case PCI_EXP_LNKSTA_CLS_5_0GB:
3906 hw->bus.speed = i40e_bus_speed_5000;
3907 break;
3908 case PCI_EXP_LNKSTA_CLS_8_0GB:
3909 hw->bus.speed = i40e_bus_speed_8000;
3910 break;
3911 default:
3912 hw->bus.speed = i40e_bus_speed_unknown;
3913 break;
3914 }
3915 }
3916
3917 /**
3918 * i40e_aq_debug_dump
3919 * @hw: pointer to the hardware structure
3920 * @cluster_id: specific cluster to dump
3921 * @table_id: table id within cluster
3922 * @start_index: index of line in the block to read
3923 * @buff_size: dump buffer size
3924 * @buff: dump buffer
3925 * @ret_buff_size: actual buffer size returned
3926 * @ret_next_table: next block to read
3927 * @ret_next_index: next index to read
3928 *
3929 * Dump internal FW/HW data for debug purposes.
3930 *
3931 **/
3932 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
3933 u8 table_id, u32 start_index, u16 buff_size,
3934 void *buff, u16 *ret_buff_size,
3935 u8 *ret_next_table, u32 *ret_next_index,
3936 struct i40e_asq_cmd_details *cmd_details)
3937 {
3938 struct i40e_aq_desc desc;
3939 struct i40e_aqc_debug_dump_internals *cmd =
3940 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
3941 struct i40e_aqc_debug_dump_internals *resp =
3942 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
3943 i40e_status status;
3944
3945 if (buff_size == 0 || !buff)
3946 return I40E_ERR_PARAM;
3947
3948 i40e_fill_default_direct_cmd_desc(&desc,
3949 i40e_aqc_opc_debug_dump_internals);
3950 /* Indirect Command */
3951 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3952 if (buff_size > I40E_AQ_LARGE_BUF)
3953 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3954
3955 cmd->cluster_id = cluster_id;
3956 cmd->table_id = table_id;
3957 cmd->idx = cpu_to_le32(start_index);
3958
3959 desc.datalen = cpu_to_le16(buff_size);
3960
3961 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3962 if (!status) {
3963 if (ret_buff_size)
3964 *ret_buff_size = le16_to_cpu(desc.datalen);
3965 if (ret_next_table)
3966 *ret_next_table = resp->table_id;
3967 if (ret_next_index)
3968 *ret_next_index = le32_to_cpu(resp->idx);
3969 }
3970
3971 return status;
3972 }
3973
3974 /**
3975 * i40e_read_bw_from_alt_ram
3976 * @hw: pointer to the hardware structure
3977 * @max_bw: pointer for max_bw read
3978 * @min_bw: pointer for min_bw read
3979 * @min_valid: pointer for bool that is true if min_bw is a valid value
3980 * @max_valid: pointer for bool that is true if max_bw is a valid value
3981 *
3982 * Read bw from the alternate ram for the given pf
3983 **/
3984 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
3985 u32 *max_bw, u32 *min_bw,
3986 bool *min_valid, bool *max_valid)
3987 {
3988 i40e_status status;
3989 u32 max_bw_addr, min_bw_addr;
3990
3991 /* Calculate the address of the min/max bw registers */
3992 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
3993 I40E_ALT_STRUCT_MAX_BW_OFFSET +
3994 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
3995 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
3996 I40E_ALT_STRUCT_MIN_BW_OFFSET +
3997 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
3998
3999 /* Read the bandwidths from alt ram */
4000 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4001 min_bw_addr, min_bw);
4002
4003 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4004 *min_valid = true;
4005 else
4006 *min_valid = false;
4007
4008 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4009 *max_valid = true;
4010 else
4011 *max_valid = false;
4012
4013 return status;
4014 }
4015
4016 /**
4017 * i40e_aq_configure_partition_bw
4018 * @hw: pointer to the hardware structure
4019 * @bw_data: Buffer holding valid pfs and bw limits
4020 * @cmd_details: pointer to command details
4021 *
4022 * Configure partitions guaranteed/max bw
4023 **/
4024 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4025 struct i40e_aqc_configure_partition_bw_data *bw_data,
4026 struct i40e_asq_cmd_details *cmd_details)
4027 {
4028 i40e_status status;
4029 struct i40e_aq_desc desc;
4030 u16 bwd_size = sizeof(*bw_data);
4031
4032 i40e_fill_default_direct_cmd_desc(&desc,
4033 i40e_aqc_opc_configure_partition_bw);
4034
4035 /* Indirect command */
4036 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4037 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4038
4039 if (bwd_size > I40E_AQ_LARGE_BUF)
4040 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4041
4042 desc.datalen = cpu_to_le16(bwd_size);
4043
4044 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4045 cmd_details);
4046
4047 return status;
4048 }
Linux kernel - Deliverables
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