1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
39 static i40e_status
i40e_set_mac_type(struct i40e_hw
*hw
)
41 i40e_status status
= 0;
43 if (hw
->vendor_id
== PCI_VENDOR_ID_INTEL
) {
44 switch (hw
->device_id
) {
45 case I40E_DEV_ID_SFP_XL710
:
46 case I40E_DEV_ID_QEMU
:
47 case I40E_DEV_ID_KX_A
:
48 case I40E_DEV_ID_KX_B
:
49 case I40E_DEV_ID_KX_C
:
50 case I40E_DEV_ID_QSFP_A
:
51 case I40E_DEV_ID_QSFP_B
:
52 case I40E_DEV_ID_QSFP_C
:
53 case I40E_DEV_ID_10G_BASE_T
:
54 case I40E_DEV_ID_20G_KR2
:
55 hw
->mac
.type
= I40E_MAC_XL710
;
58 case I40E_DEV_ID_VF_HV
:
59 hw
->mac
.type
= I40E_MAC_VF
;
62 hw
->mac
.type
= I40E_MAC_GENERIC
;
66 status
= I40E_ERR_DEVICE_NOT_SUPPORTED
;
69 hw_dbg(hw
, "i40e_set_mac_type found mac: %d, returns: %d\n",
70 hw
->mac
.type
, status
);
75 * i40e_aq_str - convert AQ err code to a string
76 * @hw: pointer to the HW structure
77 * @aq_err: the AQ error code to convert
79 char *i40e_aq_str(struct i40e_hw
*hw
, enum i40e_admin_queue_err aq_err
)
84 case I40E_AQ_RC_EPERM
:
85 return "I40E_AQ_RC_EPERM";
86 case I40E_AQ_RC_ENOENT
:
87 return "I40E_AQ_RC_ENOENT";
88 case I40E_AQ_RC_ESRCH
:
89 return "I40E_AQ_RC_ESRCH";
90 case I40E_AQ_RC_EINTR
:
91 return "I40E_AQ_RC_EINTR";
93 return "I40E_AQ_RC_EIO";
94 case I40E_AQ_RC_ENXIO
:
95 return "I40E_AQ_RC_ENXIO";
96 case I40E_AQ_RC_E2BIG
:
97 return "I40E_AQ_RC_E2BIG";
98 case I40E_AQ_RC_EAGAIN
:
99 return "I40E_AQ_RC_EAGAIN";
100 case I40E_AQ_RC_ENOMEM
:
101 return "I40E_AQ_RC_ENOMEM";
102 case I40E_AQ_RC_EACCES
:
103 return "I40E_AQ_RC_EACCES";
104 case I40E_AQ_RC_EFAULT
:
105 return "I40E_AQ_RC_EFAULT";
106 case I40E_AQ_RC_EBUSY
:
107 return "I40E_AQ_RC_EBUSY";
108 case I40E_AQ_RC_EEXIST
:
109 return "I40E_AQ_RC_EEXIST";
110 case I40E_AQ_RC_EINVAL
:
111 return "I40E_AQ_RC_EINVAL";
112 case I40E_AQ_RC_ENOTTY
:
113 return "I40E_AQ_RC_ENOTTY";
114 case I40E_AQ_RC_ENOSPC
:
115 return "I40E_AQ_RC_ENOSPC";
116 case I40E_AQ_RC_ENOSYS
:
117 return "I40E_AQ_RC_ENOSYS";
118 case I40E_AQ_RC_ERANGE
:
119 return "I40E_AQ_RC_ERANGE";
120 case I40E_AQ_RC_EFLUSHED
:
121 return "I40E_AQ_RC_EFLUSHED";
122 case I40E_AQ_RC_BAD_ADDR
:
123 return "I40E_AQ_RC_BAD_ADDR";
124 case I40E_AQ_RC_EMODE
:
125 return "I40E_AQ_RC_EMODE";
126 case I40E_AQ_RC_EFBIG
:
127 return "I40E_AQ_RC_EFBIG";
130 snprintf(hw
->err_str
, sizeof(hw
->err_str
), "%d", aq_err
);
135 * i40e_stat_str - convert status err code to a string
136 * @hw: pointer to the HW structure
137 * @stat_err: the status error code to convert
139 char *i40e_stat_str(struct i40e_hw
*hw
, i40e_status stat_err
)
145 return "I40E_ERR_NVM";
146 case I40E_ERR_NVM_CHECKSUM
:
147 return "I40E_ERR_NVM_CHECKSUM";
149 return "I40E_ERR_PHY";
150 case I40E_ERR_CONFIG
:
151 return "I40E_ERR_CONFIG";
153 return "I40E_ERR_PARAM";
154 case I40E_ERR_MAC_TYPE
:
155 return "I40E_ERR_MAC_TYPE";
156 case I40E_ERR_UNKNOWN_PHY
:
157 return "I40E_ERR_UNKNOWN_PHY";
158 case I40E_ERR_LINK_SETUP
:
159 return "I40E_ERR_LINK_SETUP";
160 case I40E_ERR_ADAPTER_STOPPED
:
161 return "I40E_ERR_ADAPTER_STOPPED";
162 case I40E_ERR_INVALID_MAC_ADDR
:
163 return "I40E_ERR_INVALID_MAC_ADDR";
164 case I40E_ERR_DEVICE_NOT_SUPPORTED
:
165 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
166 case I40E_ERR_MASTER_REQUESTS_PENDING
:
167 return "I40E_ERR_MASTER_REQUESTS_PENDING";
168 case I40E_ERR_INVALID_LINK_SETTINGS
:
169 return "I40E_ERR_INVALID_LINK_SETTINGS";
170 case I40E_ERR_AUTONEG_NOT_COMPLETE
:
171 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
172 case I40E_ERR_RESET_FAILED
:
173 return "I40E_ERR_RESET_FAILED";
174 case I40E_ERR_SWFW_SYNC
:
175 return "I40E_ERR_SWFW_SYNC";
176 case I40E_ERR_NO_AVAILABLE_VSI
:
177 return "I40E_ERR_NO_AVAILABLE_VSI";
178 case I40E_ERR_NO_MEMORY
:
179 return "I40E_ERR_NO_MEMORY";
180 case I40E_ERR_BAD_PTR
:
181 return "I40E_ERR_BAD_PTR";
182 case I40E_ERR_RING_FULL
:
183 return "I40E_ERR_RING_FULL";
184 case I40E_ERR_INVALID_PD_ID
:
185 return "I40E_ERR_INVALID_PD_ID";
186 case I40E_ERR_INVALID_QP_ID
:
187 return "I40E_ERR_INVALID_QP_ID";
188 case I40E_ERR_INVALID_CQ_ID
:
189 return "I40E_ERR_INVALID_CQ_ID";
190 case I40E_ERR_INVALID_CEQ_ID
:
191 return "I40E_ERR_INVALID_CEQ_ID";
192 case I40E_ERR_INVALID_AEQ_ID
:
193 return "I40E_ERR_INVALID_AEQ_ID";
194 case I40E_ERR_INVALID_SIZE
:
195 return "I40E_ERR_INVALID_SIZE";
196 case I40E_ERR_INVALID_ARP_INDEX
:
197 return "I40E_ERR_INVALID_ARP_INDEX";
198 case I40E_ERR_INVALID_FPM_FUNC_ID
:
199 return "I40E_ERR_INVALID_FPM_FUNC_ID";
200 case I40E_ERR_QP_INVALID_MSG_SIZE
:
201 return "I40E_ERR_QP_INVALID_MSG_SIZE";
202 case I40E_ERR_QP_TOOMANY_WRS_POSTED
:
203 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
204 case I40E_ERR_INVALID_FRAG_COUNT
:
205 return "I40E_ERR_INVALID_FRAG_COUNT";
206 case I40E_ERR_QUEUE_EMPTY
:
207 return "I40E_ERR_QUEUE_EMPTY";
208 case I40E_ERR_INVALID_ALIGNMENT
:
209 return "I40E_ERR_INVALID_ALIGNMENT";
210 case I40E_ERR_FLUSHED_QUEUE
:
211 return "I40E_ERR_FLUSHED_QUEUE";
212 case I40E_ERR_INVALID_PUSH_PAGE_INDEX
:
213 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
214 case I40E_ERR_INVALID_IMM_DATA_SIZE
:
215 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
216 case I40E_ERR_TIMEOUT
:
217 return "I40E_ERR_TIMEOUT";
218 case I40E_ERR_OPCODE_MISMATCH
:
219 return "I40E_ERR_OPCODE_MISMATCH";
220 case I40E_ERR_CQP_COMPL_ERROR
:
221 return "I40E_ERR_CQP_COMPL_ERROR";
222 case I40E_ERR_INVALID_VF_ID
:
223 return "I40E_ERR_INVALID_VF_ID";
224 case I40E_ERR_INVALID_HMCFN_ID
:
225 return "I40E_ERR_INVALID_HMCFN_ID";
226 case I40E_ERR_BACKING_PAGE_ERROR
:
227 return "I40E_ERR_BACKING_PAGE_ERROR";
228 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE
:
229 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
230 case I40E_ERR_INVALID_PBLE_INDEX
:
231 return "I40E_ERR_INVALID_PBLE_INDEX";
232 case I40E_ERR_INVALID_SD_INDEX
:
233 return "I40E_ERR_INVALID_SD_INDEX";
234 case I40E_ERR_INVALID_PAGE_DESC_INDEX
:
235 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
236 case I40E_ERR_INVALID_SD_TYPE
:
237 return "I40E_ERR_INVALID_SD_TYPE";
238 case I40E_ERR_MEMCPY_FAILED
:
239 return "I40E_ERR_MEMCPY_FAILED";
240 case I40E_ERR_INVALID_HMC_OBJ_INDEX
:
241 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
242 case I40E_ERR_INVALID_HMC_OBJ_COUNT
:
243 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
244 case I40E_ERR_INVALID_SRQ_ARM_LIMIT
:
245 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
246 case I40E_ERR_SRQ_ENABLED
:
247 return "I40E_ERR_SRQ_ENABLED";
248 case I40E_ERR_ADMIN_QUEUE_ERROR
:
249 return "I40E_ERR_ADMIN_QUEUE_ERROR";
250 case I40E_ERR_ADMIN_QUEUE_TIMEOUT
:
251 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
252 case I40E_ERR_BUF_TOO_SHORT
:
253 return "I40E_ERR_BUF_TOO_SHORT";
254 case I40E_ERR_ADMIN_QUEUE_FULL
:
255 return "I40E_ERR_ADMIN_QUEUE_FULL";
256 case I40E_ERR_ADMIN_QUEUE_NO_WORK
:
257 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
258 case I40E_ERR_BAD_IWARP_CQE
:
259 return "I40E_ERR_BAD_IWARP_CQE";
260 case I40E_ERR_NVM_BLANK_MODE
:
261 return "I40E_ERR_NVM_BLANK_MODE";
262 case I40E_ERR_NOT_IMPLEMENTED
:
263 return "I40E_ERR_NOT_IMPLEMENTED";
264 case I40E_ERR_PE_DOORBELL_NOT_ENABLED
:
265 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
266 case I40E_ERR_DIAG_TEST_FAILED
:
267 return "I40E_ERR_DIAG_TEST_FAILED";
268 case I40E_ERR_NOT_READY
:
269 return "I40E_ERR_NOT_READY";
270 case I40E_NOT_SUPPORTED
:
271 return "I40E_NOT_SUPPORTED";
272 case I40E_ERR_FIRMWARE_API_VERSION
:
273 return "I40E_ERR_FIRMWARE_API_VERSION";
276 snprintf(hw
->err_str
, sizeof(hw
->err_str
), "%d", stat_err
);
282 * @hw: debug mask related to admin queue
284 * @desc: pointer to admin queue descriptor
285 * @buffer: pointer to command buffer
286 * @buf_len: max length of buffer
288 * Dumps debug log about adminq command with descriptor contents.
290 void i40e_debug_aq(struct i40e_hw
*hw
, enum i40e_debug_mask mask
, void *desc
,
291 void *buffer
, u16 buf_len
)
293 struct i40e_aq_desc
*aq_desc
= (struct i40e_aq_desc
*)desc
;
294 u16 len
= le16_to_cpu(aq_desc
->datalen
);
295 u8
*buf
= (u8
*)buffer
;
298 if ((!(mask
& hw
->debug_mask
)) || (desc
== NULL
))
302 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
303 le16_to_cpu(aq_desc
->opcode
),
304 le16_to_cpu(aq_desc
->flags
),
305 le16_to_cpu(aq_desc
->datalen
),
306 le16_to_cpu(aq_desc
->retval
));
307 i40e_debug(hw
, mask
, "\tcookie (h,l) 0x%08X 0x%08X\n",
308 le32_to_cpu(aq_desc
->cookie_high
),
309 le32_to_cpu(aq_desc
->cookie_low
));
310 i40e_debug(hw
, mask
, "\tparam (0,1) 0x%08X 0x%08X\n",
311 le32_to_cpu(aq_desc
->params
.internal
.param0
),
312 le32_to_cpu(aq_desc
->params
.internal
.param1
));
313 i40e_debug(hw
, mask
, "\taddr (h,l) 0x%08X 0x%08X\n",
314 le32_to_cpu(aq_desc
->params
.external
.addr_high
),
315 le32_to_cpu(aq_desc
->params
.external
.addr_low
));
317 if ((buffer
!= NULL
) && (aq_desc
->datalen
!= 0)) {
318 i40e_debug(hw
, mask
, "AQ CMD Buffer:\n");
321 /* write the full 16-byte chunks */
322 for (i
= 0; i
< (len
- 16); i
+= 16)
324 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
325 i
, buf
[i
], buf
[i
+ 1], buf
[i
+ 2],
326 buf
[i
+ 3], buf
[i
+ 4], buf
[i
+ 5],
327 buf
[i
+ 6], buf
[i
+ 7], buf
[i
+ 8],
328 buf
[i
+ 9], buf
[i
+ 10], buf
[i
+ 11],
329 buf
[i
+ 12], buf
[i
+ 13], buf
[i
+ 14],
331 /* write whatever's left over without overrunning the buffer */
336 memset(d_buf
, 0, sizeof(d_buf
));
337 j
+= sprintf(d_buf
, "\t0x%04X ", i
);
339 j
+= sprintf(&d_buf
[j
], " %02X", buf
[i
++]);
340 i40e_debug(hw
, mask
, "%s\n", d_buf
);
346 * i40e_check_asq_alive
347 * @hw: pointer to the hw struct
349 * Returns true if Queue is enabled else false.
351 bool i40e_check_asq_alive(struct i40e_hw
*hw
)
354 return !!(rd32(hw
, hw
->aq
.asq
.len
) &
355 I40E_PF_ATQLEN_ATQENABLE_MASK
);
361 * i40e_aq_queue_shutdown
362 * @hw: pointer to the hw struct
363 * @unloading: is the driver unloading itself
365 * Tell the Firmware that we're shutting down the AdminQ and whether
366 * or not the driver is unloading as well.
368 i40e_status
i40e_aq_queue_shutdown(struct i40e_hw
*hw
,
371 struct i40e_aq_desc desc
;
372 struct i40e_aqc_queue_shutdown
*cmd
=
373 (struct i40e_aqc_queue_shutdown
*)&desc
.params
.raw
;
376 i40e_fill_default_direct_cmd_desc(&desc
,
377 i40e_aqc_opc_queue_shutdown
);
380 cmd
->driver_unloading
= cpu_to_le32(I40E_AQ_DRIVER_UNLOADING
);
381 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, NULL
);
386 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
387 * hardware to a bit-field that can be used by SW to more easily determine the
390 * Macros are used to shorten the table lines and make this table human
393 * We store the PTYPE in the top byte of the bit field - this is just so that
394 * we can check that the table doesn't have a row missing, as the index into
395 * the table should be the PTYPE.
399 * IF NOT i40e_ptype_lookup[ptype].known
402 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
403 * Use the rest of the fields to look at the tunnels, inner protocols, etc
405 * Use the enum i40e_rx_l2_ptype to decode the packet type
409 /* macro to make the table lines short */
410 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
413 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
414 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
415 I40E_RX_PTYPE_##OUTER_FRAG, \
416 I40E_RX_PTYPE_TUNNEL_##T, \
417 I40E_RX_PTYPE_TUNNEL_END_##TE, \
418 I40E_RX_PTYPE_##TEF, \
419 I40E_RX_PTYPE_INNER_PROT_##I, \
420 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
422 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
423 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
425 /* shorter macros makes the table fit but are terse */
426 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
427 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
428 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
430 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
431 struct i40e_rx_ptype_decoded i40e_ptype_lookup
[] = {
432 /* L2 Packet types */
433 I40E_PTT_UNUSED_ENTRY(0),
434 I40E_PTT(1, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
435 I40E_PTT(2, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, TS
, PAY2
),
436 I40E_PTT(3, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
437 I40E_PTT_UNUSED_ENTRY(4),
438 I40E_PTT_UNUSED_ENTRY(5),
439 I40E_PTT(6, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
440 I40E_PTT(7, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
441 I40E_PTT_UNUSED_ENTRY(8),
442 I40E_PTT_UNUSED_ENTRY(9),
443 I40E_PTT(10, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
444 I40E_PTT(11, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, NONE
),
445 I40E_PTT(12, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
446 I40E_PTT(13, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
447 I40E_PTT(14, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
448 I40E_PTT(15, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
449 I40E_PTT(16, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
450 I40E_PTT(17, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
451 I40E_PTT(18, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
452 I40E_PTT(19, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
453 I40E_PTT(20, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
454 I40E_PTT(21, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
456 /* Non Tunneled IPv4 */
457 I40E_PTT(22, IP
, IPV4
, FRG
, NONE
, NONE
, NOF
, NONE
, PAY3
),
458 I40E_PTT(23, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
459 I40E_PTT(24, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, UDP
, PAY4
),
460 I40E_PTT_UNUSED_ENTRY(25),
461 I40E_PTT(26, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, TCP
, PAY4
),
462 I40E_PTT(27, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, SCTP
, PAY4
),
463 I40E_PTT(28, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, ICMP
, PAY4
),
466 I40E_PTT(29, IP
, IPV4
, NOF
, IP_IP
, IPV4
, FRG
, NONE
, PAY3
),
467 I40E_PTT(30, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, NONE
, PAY3
),
468 I40E_PTT(31, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, UDP
, PAY4
),
469 I40E_PTT_UNUSED_ENTRY(32),
470 I40E_PTT(33, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, TCP
, PAY4
),
471 I40E_PTT(34, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, SCTP
, PAY4
),
472 I40E_PTT(35, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, ICMP
, PAY4
),
475 I40E_PTT(36, IP
, IPV4
, NOF
, IP_IP
, IPV6
, FRG
, NONE
, PAY3
),
476 I40E_PTT(37, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, NONE
, PAY3
),
477 I40E_PTT(38, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, UDP
, PAY4
),
478 I40E_PTT_UNUSED_ENTRY(39),
479 I40E_PTT(40, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, TCP
, PAY4
),
480 I40E_PTT(41, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, SCTP
, PAY4
),
481 I40E_PTT(42, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, ICMP
, PAY4
),
483 /* IPv4 --> GRE/NAT */
484 I40E_PTT(43, IP
, IPV4
, NOF
, IP_GRENAT
, NONE
, NOF
, NONE
, PAY3
),
486 /* IPv4 --> GRE/NAT --> IPv4 */
487 I40E_PTT(44, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, FRG
, NONE
, PAY3
),
488 I40E_PTT(45, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, NONE
, PAY3
),
489 I40E_PTT(46, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, UDP
, PAY4
),
490 I40E_PTT_UNUSED_ENTRY(47),
491 I40E_PTT(48, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, TCP
, PAY4
),
492 I40E_PTT(49, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, SCTP
, PAY4
),
493 I40E_PTT(50, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, ICMP
, PAY4
),
495 /* IPv4 --> GRE/NAT --> IPv6 */
496 I40E_PTT(51, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, FRG
, NONE
, PAY3
),
497 I40E_PTT(52, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, NONE
, PAY3
),
498 I40E_PTT(53, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, UDP
, PAY4
),
499 I40E_PTT_UNUSED_ENTRY(54),
500 I40E_PTT(55, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, TCP
, PAY4
),
501 I40E_PTT(56, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, SCTP
, PAY4
),
502 I40E_PTT(57, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, ICMP
, PAY4
),
504 /* IPv4 --> GRE/NAT --> MAC */
505 I40E_PTT(58, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, NONE
, NOF
, NONE
, PAY3
),
507 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
508 I40E_PTT(59, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, FRG
, NONE
, PAY3
),
509 I40E_PTT(60, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, NONE
, PAY3
),
510 I40E_PTT(61, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, UDP
, PAY4
),
511 I40E_PTT_UNUSED_ENTRY(62),
512 I40E_PTT(63, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, TCP
, PAY4
),
513 I40E_PTT(64, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, SCTP
, PAY4
),
514 I40E_PTT(65, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, ICMP
, PAY4
),
516 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
517 I40E_PTT(66, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, FRG
, NONE
, PAY3
),
518 I40E_PTT(67, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, NONE
, PAY3
),
519 I40E_PTT(68, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, UDP
, PAY4
),
520 I40E_PTT_UNUSED_ENTRY(69),
521 I40E_PTT(70, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, TCP
, PAY4
),
522 I40E_PTT(71, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, SCTP
, PAY4
),
523 I40E_PTT(72, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, ICMP
, PAY4
),
525 /* IPv4 --> GRE/NAT --> MAC/VLAN */
526 I40E_PTT(73, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, NONE
, NOF
, NONE
, PAY3
),
528 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
529 I40E_PTT(74, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, FRG
, NONE
, PAY3
),
530 I40E_PTT(75, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, NONE
, PAY3
),
531 I40E_PTT(76, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, UDP
, PAY4
),
532 I40E_PTT_UNUSED_ENTRY(77),
533 I40E_PTT(78, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, TCP
, PAY4
),
534 I40E_PTT(79, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, SCTP
, PAY4
),
535 I40E_PTT(80, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, ICMP
, PAY4
),
537 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
538 I40E_PTT(81, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, FRG
, NONE
, PAY3
),
539 I40E_PTT(82, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, NONE
, PAY3
),
540 I40E_PTT(83, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, UDP
, PAY4
),
541 I40E_PTT_UNUSED_ENTRY(84),
542 I40E_PTT(85, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, TCP
, PAY4
),
543 I40E_PTT(86, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, SCTP
, PAY4
),
544 I40E_PTT(87, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, ICMP
, PAY4
),
546 /* Non Tunneled IPv6 */
547 I40E_PTT(88, IP
, IPV6
, FRG
, NONE
, NONE
, NOF
, NONE
, PAY3
),
548 I40E_PTT(89, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
549 I40E_PTT(90, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, UDP
, PAY3
),
550 I40E_PTT_UNUSED_ENTRY(91),
551 I40E_PTT(92, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, TCP
, PAY4
),
552 I40E_PTT(93, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, SCTP
, PAY4
),
553 I40E_PTT(94, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, ICMP
, PAY4
),
556 I40E_PTT(95, IP
, IPV6
, NOF
, IP_IP
, IPV4
, FRG
, NONE
, PAY3
),
557 I40E_PTT(96, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, NONE
, PAY3
),
558 I40E_PTT(97, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, UDP
, PAY4
),
559 I40E_PTT_UNUSED_ENTRY(98),
560 I40E_PTT(99, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, TCP
, PAY4
),
561 I40E_PTT(100, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, SCTP
, PAY4
),
562 I40E_PTT(101, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, ICMP
, PAY4
),
565 I40E_PTT(102, IP
, IPV6
, NOF
, IP_IP
, IPV6
, FRG
, NONE
, PAY3
),
566 I40E_PTT(103, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, NONE
, PAY3
),
567 I40E_PTT(104, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, UDP
, PAY4
),
568 I40E_PTT_UNUSED_ENTRY(105),
569 I40E_PTT(106, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, TCP
, PAY4
),
570 I40E_PTT(107, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, SCTP
, PAY4
),
571 I40E_PTT(108, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, ICMP
, PAY4
),
573 /* IPv6 --> GRE/NAT */
574 I40E_PTT(109, IP
, IPV6
, NOF
, IP_GRENAT
, NONE
, NOF
, NONE
, PAY3
),
576 /* IPv6 --> GRE/NAT -> IPv4 */
577 I40E_PTT(110, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, FRG
, NONE
, PAY3
),
578 I40E_PTT(111, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, NONE
, PAY3
),
579 I40E_PTT(112, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, UDP
, PAY4
),
580 I40E_PTT_UNUSED_ENTRY(113),
581 I40E_PTT(114, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, TCP
, PAY4
),
582 I40E_PTT(115, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, SCTP
, PAY4
),
583 I40E_PTT(116, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, ICMP
, PAY4
),
585 /* IPv6 --> GRE/NAT -> IPv6 */
586 I40E_PTT(117, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, FRG
, NONE
, PAY3
),
587 I40E_PTT(118, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, NONE
, PAY3
),
588 I40E_PTT(119, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, UDP
, PAY4
),
589 I40E_PTT_UNUSED_ENTRY(120),
590 I40E_PTT(121, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, TCP
, PAY4
),
591 I40E_PTT(122, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, SCTP
, PAY4
),
592 I40E_PTT(123, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, ICMP
, PAY4
),
594 /* IPv6 --> GRE/NAT -> MAC */
595 I40E_PTT(124, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, NONE
, NOF
, NONE
, PAY3
),
597 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
598 I40E_PTT(125, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, FRG
, NONE
, PAY3
),
599 I40E_PTT(126, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, NONE
, PAY3
),
600 I40E_PTT(127, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, UDP
, PAY4
),
601 I40E_PTT_UNUSED_ENTRY(128),
602 I40E_PTT(129, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, TCP
, PAY4
),
603 I40E_PTT(130, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, SCTP
, PAY4
),
604 I40E_PTT(131, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, ICMP
, PAY4
),
606 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
607 I40E_PTT(132, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, FRG
, NONE
, PAY3
),
608 I40E_PTT(133, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, NONE
, PAY3
),
609 I40E_PTT(134, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, UDP
, PAY4
),
610 I40E_PTT_UNUSED_ENTRY(135),
611 I40E_PTT(136, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, TCP
, PAY4
),
612 I40E_PTT(137, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, SCTP
, PAY4
),
613 I40E_PTT(138, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, ICMP
, PAY4
),
615 /* IPv6 --> GRE/NAT -> MAC/VLAN */
616 I40E_PTT(139, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, NONE
, NOF
, NONE
, PAY3
),
618 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
619 I40E_PTT(140, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, FRG
, NONE
, PAY3
),
620 I40E_PTT(141, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, NONE
, PAY3
),
621 I40E_PTT(142, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, UDP
, PAY4
),
622 I40E_PTT_UNUSED_ENTRY(143),
623 I40E_PTT(144, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, TCP
, PAY4
),
624 I40E_PTT(145, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, SCTP
, PAY4
),
625 I40E_PTT(146, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, ICMP
, PAY4
),
627 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
628 I40E_PTT(147, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, FRG
, NONE
, PAY3
),
629 I40E_PTT(148, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, NONE
, PAY3
),
630 I40E_PTT(149, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, UDP
, PAY4
),
631 I40E_PTT_UNUSED_ENTRY(150),
632 I40E_PTT(151, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, TCP
, PAY4
),
633 I40E_PTT(152, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, SCTP
, PAY4
),
634 I40E_PTT(153, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, ICMP
, PAY4
),
637 I40E_PTT_UNUSED_ENTRY(154),
638 I40E_PTT_UNUSED_ENTRY(155),
639 I40E_PTT_UNUSED_ENTRY(156),
640 I40E_PTT_UNUSED_ENTRY(157),
641 I40E_PTT_UNUSED_ENTRY(158),
642 I40E_PTT_UNUSED_ENTRY(159),
644 I40E_PTT_UNUSED_ENTRY(160),
645 I40E_PTT_UNUSED_ENTRY(161),
646 I40E_PTT_UNUSED_ENTRY(162),
647 I40E_PTT_UNUSED_ENTRY(163),
648 I40E_PTT_UNUSED_ENTRY(164),
649 I40E_PTT_UNUSED_ENTRY(165),
650 I40E_PTT_UNUSED_ENTRY(166),
651 I40E_PTT_UNUSED_ENTRY(167),
652 I40E_PTT_UNUSED_ENTRY(168),
653 I40E_PTT_UNUSED_ENTRY(169),
655 I40E_PTT_UNUSED_ENTRY(170),
656 I40E_PTT_UNUSED_ENTRY(171),
657 I40E_PTT_UNUSED_ENTRY(172),
658 I40E_PTT_UNUSED_ENTRY(173),
659 I40E_PTT_UNUSED_ENTRY(174),
660 I40E_PTT_UNUSED_ENTRY(175),
661 I40E_PTT_UNUSED_ENTRY(176),
662 I40E_PTT_UNUSED_ENTRY(177),
663 I40E_PTT_UNUSED_ENTRY(178),
664 I40E_PTT_UNUSED_ENTRY(179),
666 I40E_PTT_UNUSED_ENTRY(180),
667 I40E_PTT_UNUSED_ENTRY(181),
668 I40E_PTT_UNUSED_ENTRY(182),
669 I40E_PTT_UNUSED_ENTRY(183),
670 I40E_PTT_UNUSED_ENTRY(184),
671 I40E_PTT_UNUSED_ENTRY(185),
672 I40E_PTT_UNUSED_ENTRY(186),
673 I40E_PTT_UNUSED_ENTRY(187),
674 I40E_PTT_UNUSED_ENTRY(188),
675 I40E_PTT_UNUSED_ENTRY(189),
677 I40E_PTT_UNUSED_ENTRY(190),
678 I40E_PTT_UNUSED_ENTRY(191),
679 I40E_PTT_UNUSED_ENTRY(192),
680 I40E_PTT_UNUSED_ENTRY(193),
681 I40E_PTT_UNUSED_ENTRY(194),
682 I40E_PTT_UNUSED_ENTRY(195),
683 I40E_PTT_UNUSED_ENTRY(196),
684 I40E_PTT_UNUSED_ENTRY(197),
685 I40E_PTT_UNUSED_ENTRY(198),
686 I40E_PTT_UNUSED_ENTRY(199),
688 I40E_PTT_UNUSED_ENTRY(200),
689 I40E_PTT_UNUSED_ENTRY(201),
690 I40E_PTT_UNUSED_ENTRY(202),
691 I40E_PTT_UNUSED_ENTRY(203),
692 I40E_PTT_UNUSED_ENTRY(204),
693 I40E_PTT_UNUSED_ENTRY(205),
694 I40E_PTT_UNUSED_ENTRY(206),
695 I40E_PTT_UNUSED_ENTRY(207),
696 I40E_PTT_UNUSED_ENTRY(208),
697 I40E_PTT_UNUSED_ENTRY(209),
699 I40E_PTT_UNUSED_ENTRY(210),
700 I40E_PTT_UNUSED_ENTRY(211),
701 I40E_PTT_UNUSED_ENTRY(212),
702 I40E_PTT_UNUSED_ENTRY(213),
703 I40E_PTT_UNUSED_ENTRY(214),
704 I40E_PTT_UNUSED_ENTRY(215),
705 I40E_PTT_UNUSED_ENTRY(216),
706 I40E_PTT_UNUSED_ENTRY(217),
707 I40E_PTT_UNUSED_ENTRY(218),
708 I40E_PTT_UNUSED_ENTRY(219),
710 I40E_PTT_UNUSED_ENTRY(220),
711 I40E_PTT_UNUSED_ENTRY(221),
712 I40E_PTT_UNUSED_ENTRY(222),
713 I40E_PTT_UNUSED_ENTRY(223),
714 I40E_PTT_UNUSED_ENTRY(224),
715 I40E_PTT_UNUSED_ENTRY(225),
716 I40E_PTT_UNUSED_ENTRY(226),
717 I40E_PTT_UNUSED_ENTRY(227),
718 I40E_PTT_UNUSED_ENTRY(228),
719 I40E_PTT_UNUSED_ENTRY(229),
721 I40E_PTT_UNUSED_ENTRY(230),
722 I40E_PTT_UNUSED_ENTRY(231),
723 I40E_PTT_UNUSED_ENTRY(232),
724 I40E_PTT_UNUSED_ENTRY(233),
725 I40E_PTT_UNUSED_ENTRY(234),
726 I40E_PTT_UNUSED_ENTRY(235),
727 I40E_PTT_UNUSED_ENTRY(236),
728 I40E_PTT_UNUSED_ENTRY(237),
729 I40E_PTT_UNUSED_ENTRY(238),
730 I40E_PTT_UNUSED_ENTRY(239),
732 I40E_PTT_UNUSED_ENTRY(240),
733 I40E_PTT_UNUSED_ENTRY(241),
734 I40E_PTT_UNUSED_ENTRY(242),
735 I40E_PTT_UNUSED_ENTRY(243),
736 I40E_PTT_UNUSED_ENTRY(244),
737 I40E_PTT_UNUSED_ENTRY(245),
738 I40E_PTT_UNUSED_ENTRY(246),
739 I40E_PTT_UNUSED_ENTRY(247),
740 I40E_PTT_UNUSED_ENTRY(248),
741 I40E_PTT_UNUSED_ENTRY(249),
743 I40E_PTT_UNUSED_ENTRY(250),
744 I40E_PTT_UNUSED_ENTRY(251),
745 I40E_PTT_UNUSED_ENTRY(252),
746 I40E_PTT_UNUSED_ENTRY(253),
747 I40E_PTT_UNUSED_ENTRY(254),
748 I40E_PTT_UNUSED_ENTRY(255)
752 * i40e_init_shared_code - Initialize the shared code
753 * @hw: pointer to hardware structure
755 * This assigns the MAC type and PHY code and inits the NVM.
756 * Does not touch the hardware. This function must be called prior to any
757 * other function in the shared code. The i40e_hw structure should be
758 * memset to 0 prior to calling this function. The following fields in
759 * hw structure should be filled in prior to calling this function:
760 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
761 * subsystem_vendor_id, and revision_id
763 i40e_status
i40e_init_shared_code(struct i40e_hw
*hw
)
765 i40e_status status
= 0;
766 u32 port
, ari
, func_rid
;
768 i40e_set_mac_type(hw
);
770 switch (hw
->mac
.type
) {
774 return I40E_ERR_DEVICE_NOT_SUPPORTED
;
777 hw
->phy
.get_link_info
= true;
779 /* Determine port number and PF number*/
780 port
= (rd32(hw
, I40E_PFGEN_PORTNUM
) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK
)
781 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT
;
783 ari
= (rd32(hw
, I40E_GLPCI_CAPSUP
) & I40E_GLPCI_CAPSUP_ARI_EN_MASK
) >>
784 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT
;
785 func_rid
= rd32(hw
, I40E_PF_FUNC_RID
);
787 hw
->pf_id
= (u8
)(func_rid
& 0xff);
789 hw
->pf_id
= (u8
)(func_rid
& 0x7);
791 status
= i40e_init_nvm(hw
);
796 * i40e_aq_mac_address_read - Retrieve the MAC addresses
797 * @hw: pointer to the hw struct
798 * @flags: a return indicator of what addresses were added to the addr store
799 * @addrs: the requestor's mac addr store
800 * @cmd_details: pointer to command details structure or NULL
802 static i40e_status
i40e_aq_mac_address_read(struct i40e_hw
*hw
,
804 struct i40e_aqc_mac_address_read_data
*addrs
,
805 struct i40e_asq_cmd_details
*cmd_details
)
807 struct i40e_aq_desc desc
;
808 struct i40e_aqc_mac_address_read
*cmd_data
=
809 (struct i40e_aqc_mac_address_read
*)&desc
.params
.raw
;
812 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_mac_address_read
);
813 desc
.flags
|= cpu_to_le16(I40E_AQ_FLAG_BUF
);
815 status
= i40e_asq_send_command(hw
, &desc
, addrs
,
816 sizeof(*addrs
), cmd_details
);
817 *flags
= le16_to_cpu(cmd_data
->command_flags
);
823 * i40e_aq_mac_address_write - Change the MAC addresses
824 * @hw: pointer to the hw struct
825 * @flags: indicates which MAC to be written
826 * @mac_addr: address to write
827 * @cmd_details: pointer to command details structure or NULL
829 i40e_status
i40e_aq_mac_address_write(struct i40e_hw
*hw
,
830 u16 flags
, u8
*mac_addr
,
831 struct i40e_asq_cmd_details
*cmd_details
)
833 struct i40e_aq_desc desc
;
834 struct i40e_aqc_mac_address_write
*cmd_data
=
835 (struct i40e_aqc_mac_address_write
*)&desc
.params
.raw
;
838 i40e_fill_default_direct_cmd_desc(&desc
,
839 i40e_aqc_opc_mac_address_write
);
840 cmd_data
->command_flags
= cpu_to_le16(flags
);
841 cmd_data
->mac_sah
= cpu_to_le16((u16
)mac_addr
[0] << 8 | mac_addr
[1]);
842 cmd_data
->mac_sal
= cpu_to_le32(((u32
)mac_addr
[2] << 24) |
843 ((u32
)mac_addr
[3] << 16) |
844 ((u32
)mac_addr
[4] << 8) |
847 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
853 * i40e_get_mac_addr - get MAC address
854 * @hw: pointer to the HW structure
855 * @mac_addr: pointer to MAC address
857 * Reads the adapter's MAC address from register
859 i40e_status
i40e_get_mac_addr(struct i40e_hw
*hw
, u8
*mac_addr
)
861 struct i40e_aqc_mac_address_read_data addrs
;
865 status
= i40e_aq_mac_address_read(hw
, &flags
, &addrs
, NULL
);
867 if (flags
& I40E_AQC_LAN_ADDR_VALID
)
868 memcpy(mac_addr
, &addrs
.pf_lan_mac
, sizeof(addrs
.pf_lan_mac
));
874 * i40e_get_port_mac_addr - get Port MAC address
875 * @hw: pointer to the HW structure
876 * @mac_addr: pointer to Port MAC address
878 * Reads the adapter's Port MAC address
880 i40e_status
i40e_get_port_mac_addr(struct i40e_hw
*hw
, u8
*mac_addr
)
882 struct i40e_aqc_mac_address_read_data addrs
;
886 status
= i40e_aq_mac_address_read(hw
, &flags
, &addrs
, NULL
);
890 if (flags
& I40E_AQC_PORT_ADDR_VALID
)
891 memcpy(mac_addr
, &addrs
.port_mac
, sizeof(addrs
.port_mac
));
893 status
= I40E_ERR_INVALID_MAC_ADDR
;
899 * i40e_pre_tx_queue_cfg - pre tx queue configure
900 * @hw: pointer to the HW structure
901 * @queue: target PF queue index
902 * @enable: state change request
904 * Handles hw requirement to indicate intention to enable
905 * or disable target queue.
907 void i40e_pre_tx_queue_cfg(struct i40e_hw
*hw
, u32 queue
, bool enable
)
909 u32 abs_queue_idx
= hw
->func_caps
.base_queue
+ queue
;
913 if (abs_queue_idx
>= 128) {
914 reg_block
= abs_queue_idx
/ 128;
915 abs_queue_idx
%= 128;
918 reg_val
= rd32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
));
919 reg_val
&= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK
;
920 reg_val
|= (abs_queue_idx
<< I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT
);
923 reg_val
|= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK
;
925 reg_val
|= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK
;
927 wr32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
), reg_val
);
932 * i40e_get_san_mac_addr - get SAN MAC address
933 * @hw: pointer to the HW structure
934 * @mac_addr: pointer to SAN MAC address
936 * Reads the adapter's SAN MAC address from NVM
938 i40e_status
i40e_get_san_mac_addr(struct i40e_hw
*hw
, u8
*mac_addr
)
940 struct i40e_aqc_mac_address_read_data addrs
;
944 status
= i40e_aq_mac_address_read(hw
, &flags
, &addrs
, NULL
);
948 if (flags
& I40E_AQC_SAN_ADDR_VALID
)
949 memcpy(mac_addr
, &addrs
.pf_san_mac
, sizeof(addrs
.pf_san_mac
));
951 status
= I40E_ERR_INVALID_MAC_ADDR
;
958 * i40e_read_pba_string - Reads part number string from EEPROM
959 * @hw: pointer to hardware structure
960 * @pba_num: stores the part number string from the EEPROM
961 * @pba_num_size: part number string buffer length
963 * Reads the part number string from the EEPROM.
965 i40e_status
i40e_read_pba_string(struct i40e_hw
*hw
, u8
*pba_num
,
968 i40e_status status
= 0;
974 status
= i40e_read_nvm_word(hw
, I40E_SR_PBA_FLAGS
, &pba_word
);
975 if (status
|| (pba_word
!= 0xFAFA)) {
976 hw_dbg(hw
, "Failed to read PBA flags or flag is invalid.\n");
980 status
= i40e_read_nvm_word(hw
, I40E_SR_PBA_BLOCK_PTR
, &pba_ptr
);
982 hw_dbg(hw
, "Failed to read PBA Block pointer.\n");
986 status
= i40e_read_nvm_word(hw
, pba_ptr
, &pba_size
);
988 hw_dbg(hw
, "Failed to read PBA Block size.\n");
992 /* Subtract one to get PBA word count (PBA Size word is included in
996 if (pba_num_size
< (((u32
)pba_size
* 2) + 1)) {
997 hw_dbg(hw
, "Buffer to small for PBA data.\n");
998 return I40E_ERR_PARAM
;
1001 for (i
= 0; i
< pba_size
; i
++) {
1002 status
= i40e_read_nvm_word(hw
, (pba_ptr
+ 1) + i
, &pba_word
);
1004 hw_dbg(hw
, "Failed to read PBA Block word %d.\n", i
);
1008 pba_num
[(i
* 2)] = (pba_word
>> 8) & 0xFF;
1009 pba_num
[(i
* 2) + 1] = pba_word
& 0xFF;
1011 pba_num
[(pba_size
* 2)] = '\0';
1017 * i40e_get_media_type - Gets media type
1018 * @hw: pointer to the hardware structure
1020 static enum i40e_media_type
i40e_get_media_type(struct i40e_hw
*hw
)
1022 enum i40e_media_type media
;
1024 switch (hw
->phy
.link_info
.phy_type
) {
1025 case I40E_PHY_TYPE_10GBASE_SR
:
1026 case I40E_PHY_TYPE_10GBASE_LR
:
1027 case I40E_PHY_TYPE_1000BASE_SX
:
1028 case I40E_PHY_TYPE_1000BASE_LX
:
1029 case I40E_PHY_TYPE_40GBASE_SR4
:
1030 case I40E_PHY_TYPE_40GBASE_LR4
:
1031 media
= I40E_MEDIA_TYPE_FIBER
;
1033 case I40E_PHY_TYPE_100BASE_TX
:
1034 case I40E_PHY_TYPE_1000BASE_T
:
1035 case I40E_PHY_TYPE_10GBASE_T
:
1036 media
= I40E_MEDIA_TYPE_BASET
;
1038 case I40E_PHY_TYPE_10GBASE_CR1_CU
:
1039 case I40E_PHY_TYPE_40GBASE_CR4_CU
:
1040 case I40E_PHY_TYPE_10GBASE_CR1
:
1041 case I40E_PHY_TYPE_40GBASE_CR4
:
1042 case I40E_PHY_TYPE_10GBASE_SFPP_CU
:
1043 case I40E_PHY_TYPE_40GBASE_AOC
:
1044 case I40E_PHY_TYPE_10GBASE_AOC
:
1045 media
= I40E_MEDIA_TYPE_DA
;
1047 case I40E_PHY_TYPE_1000BASE_KX
:
1048 case I40E_PHY_TYPE_10GBASE_KX4
:
1049 case I40E_PHY_TYPE_10GBASE_KR
:
1050 case I40E_PHY_TYPE_40GBASE_KR4
:
1051 case I40E_PHY_TYPE_20GBASE_KR2
:
1052 media
= I40E_MEDIA_TYPE_BACKPLANE
;
1054 case I40E_PHY_TYPE_SGMII
:
1055 case I40E_PHY_TYPE_XAUI
:
1056 case I40E_PHY_TYPE_XFI
:
1057 case I40E_PHY_TYPE_XLAUI
:
1058 case I40E_PHY_TYPE_XLPPI
:
1060 media
= I40E_MEDIA_TYPE_UNKNOWN
;
1067 #define I40E_PF_RESET_WAIT_COUNT_A0 200
1068 #define I40E_PF_RESET_WAIT_COUNT 200
1070 * i40e_pf_reset - Reset the PF
1071 * @hw: pointer to the hardware structure
1073 * Assuming someone else has triggered a global reset,
1074 * assure the global reset is complete and then reset the PF
1076 i40e_status
i40e_pf_reset(struct i40e_hw
*hw
)
1083 /* Poll for Global Reset steady state in case of recent GRST.
1084 * The grst delay value is in 100ms units, and we'll wait a
1085 * couple counts longer to be sure we don't just miss the end.
1087 grst_del
= (rd32(hw
, I40E_GLGEN_RSTCTL
) &
1088 I40E_GLGEN_RSTCTL_GRSTDEL_MASK
) >>
1089 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT
;
1090 for (cnt
= 0; cnt
< grst_del
+ 2; cnt
++) {
1091 reg
= rd32(hw
, I40E_GLGEN_RSTAT
);
1092 if (!(reg
& I40E_GLGEN_RSTAT_DEVSTATE_MASK
))
1096 if (reg
& I40E_GLGEN_RSTAT_DEVSTATE_MASK
) {
1097 hw_dbg(hw
, "Global reset polling failed to complete.\n");
1098 return I40E_ERR_RESET_FAILED
;
1101 /* Now Wait for the FW to be ready */
1102 for (cnt1
= 0; cnt1
< I40E_PF_RESET_WAIT_COUNT
; cnt1
++) {
1103 reg
= rd32(hw
, I40E_GLNVM_ULD
);
1104 reg
&= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
|
1105 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
);
1106 if (reg
== (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
|
1107 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
)) {
1108 hw_dbg(hw
, "Core and Global modules ready %d\n", cnt1
);
1111 usleep_range(10000, 20000);
1113 if (!(reg
& (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
|
1114 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
))) {
1115 hw_dbg(hw
, "wait for FW Reset complete timedout\n");
1116 hw_dbg(hw
, "I40E_GLNVM_ULD = 0x%x\n", reg
);
1117 return I40E_ERR_RESET_FAILED
;
1120 /* If there was a Global Reset in progress when we got here,
1121 * we don't need to do the PF Reset
1124 if (hw
->revision_id
== 0)
1125 cnt
= I40E_PF_RESET_WAIT_COUNT_A0
;
1127 cnt
= I40E_PF_RESET_WAIT_COUNT
;
1128 reg
= rd32(hw
, I40E_PFGEN_CTRL
);
1129 wr32(hw
, I40E_PFGEN_CTRL
,
1130 (reg
| I40E_PFGEN_CTRL_PFSWR_MASK
));
1131 for (; cnt
; cnt
--) {
1132 reg
= rd32(hw
, I40E_PFGEN_CTRL
);
1133 if (!(reg
& I40E_PFGEN_CTRL_PFSWR_MASK
))
1135 usleep_range(1000, 2000);
1137 if (reg
& I40E_PFGEN_CTRL_PFSWR_MASK
) {
1138 hw_dbg(hw
, "PF reset polling failed to complete.\n");
1139 return I40E_ERR_RESET_FAILED
;
1143 i40e_clear_pxe_mode(hw
);
1149 * i40e_clear_hw - clear out any left over hw state
1150 * @hw: pointer to the hw struct
1152 * Clear queues and interrupts, typically called at init time,
1153 * but after the capabilities have been found so we know how many
1154 * queues and msix vectors have been allocated.
1156 void i40e_clear_hw(struct i40e_hw
*hw
)
1158 u32 num_queues
, base_queue
;
1166 /* get number of interrupts, queues, and VFs */
1167 val
= rd32(hw
, I40E_GLPCI_CNF2
);
1168 num_pf_int
= (val
& I40E_GLPCI_CNF2_MSI_X_PF_N_MASK
) >>
1169 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT
;
1170 num_vf_int
= (val
& I40E_GLPCI_CNF2_MSI_X_VF_N_MASK
) >>
1171 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT
;
1173 val
= rd32(hw
, I40E_PFLAN_QALLOC
);
1174 base_queue
= (val
& I40E_PFLAN_QALLOC_FIRSTQ_MASK
) >>
1175 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT
;
1176 j
= (val
& I40E_PFLAN_QALLOC_LASTQ_MASK
) >>
1177 I40E_PFLAN_QALLOC_LASTQ_SHIFT
;
1178 if (val
& I40E_PFLAN_QALLOC_VALID_MASK
)
1179 num_queues
= (j
- base_queue
) + 1;
1183 val
= rd32(hw
, I40E_PF_VT_PFALLOC
);
1184 i
= (val
& I40E_PF_VT_PFALLOC_FIRSTVF_MASK
) >>
1185 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT
;
1186 j
= (val
& I40E_PF_VT_PFALLOC_LASTVF_MASK
) >>
1187 I40E_PF_VT_PFALLOC_LASTVF_SHIFT
;
1188 if (val
& I40E_PF_VT_PFALLOC_VALID_MASK
)
1189 num_vfs
= (j
- i
) + 1;
1193 /* stop all the interrupts */
1194 wr32(hw
, I40E_PFINT_ICR0_ENA
, 0);
1195 val
= 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT
;
1196 for (i
= 0; i
< num_pf_int
- 2; i
++)
1197 wr32(hw
, I40E_PFINT_DYN_CTLN(i
), val
);
1199 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1200 val
= eol
<< I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT
;
1201 wr32(hw
, I40E_PFINT_LNKLST0
, val
);
1202 for (i
= 0; i
< num_pf_int
- 2; i
++)
1203 wr32(hw
, I40E_PFINT_LNKLSTN(i
), val
);
1204 val
= eol
<< I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT
;
1205 for (i
= 0; i
< num_vfs
; i
++)
1206 wr32(hw
, I40E_VPINT_LNKLST0(i
), val
);
1207 for (i
= 0; i
< num_vf_int
- 2; i
++)
1208 wr32(hw
, I40E_VPINT_LNKLSTN(i
), val
);
1210 /* warn the HW of the coming Tx disables */
1211 for (i
= 0; i
< num_queues
; i
++) {
1212 u32 abs_queue_idx
= base_queue
+ i
;
1215 if (abs_queue_idx
>= 128) {
1216 reg_block
= abs_queue_idx
/ 128;
1217 abs_queue_idx
%= 128;
1220 val
= rd32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
));
1221 val
&= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK
;
1222 val
|= (abs_queue_idx
<< I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT
);
1223 val
|= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK
;
1225 wr32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
), val
);
1229 /* stop all the queues */
1230 for (i
= 0; i
< num_queues
; i
++) {
1231 wr32(hw
, I40E_QINT_TQCTL(i
), 0);
1232 wr32(hw
, I40E_QTX_ENA(i
), 0);
1233 wr32(hw
, I40E_QINT_RQCTL(i
), 0);
1234 wr32(hw
, I40E_QRX_ENA(i
), 0);
1237 /* short wait for all queue disables to settle */
1242 * i40e_clear_pxe_mode - clear pxe operations mode
1243 * @hw: pointer to the hw struct
1245 * Make sure all PXE mode settings are cleared, including things
1246 * like descriptor fetch/write-back mode.
1248 void i40e_clear_pxe_mode(struct i40e_hw
*hw
)
1252 if (i40e_check_asq_alive(hw
))
1253 i40e_aq_clear_pxe_mode(hw
, NULL
);
1255 /* Clear single descriptor fetch/write-back mode */
1256 reg
= rd32(hw
, I40E_GLLAN_RCTL_0
);
1258 if (hw
->revision_id
== 0) {
1259 /* As a work around clear PXE_MODE instead of setting it */
1260 wr32(hw
, I40E_GLLAN_RCTL_0
, (reg
& (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK
)));
1262 wr32(hw
, I40E_GLLAN_RCTL_0
, (reg
| I40E_GLLAN_RCTL_0_PXE_MODE_MASK
));
1267 * i40e_led_is_mine - helper to find matching led
1268 * @hw: pointer to the hw struct
1269 * @idx: index into GPIO registers
1271 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1273 static u32
i40e_led_is_mine(struct i40e_hw
*hw
, int idx
)
1278 if (!hw
->func_caps
.led
[idx
])
1281 gpio_val
= rd32(hw
, I40E_GLGEN_GPIO_CTL(idx
));
1282 port
= (gpio_val
& I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK
) >>
1283 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT
;
1285 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1286 * if it is not our port then ignore
1288 if ((gpio_val
& I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK
) ||
1295 #define I40E_COMBINED_ACTIVITY 0xA
1296 #define I40E_FILTER_ACTIVITY 0xE
1297 #define I40E_LINK_ACTIVITY 0xC
1298 #define I40E_MAC_ACTIVITY 0xD
1299 #define I40E_LED0 22
1302 * i40e_led_get - return current on/off mode
1303 * @hw: pointer to the hw struct
1305 * The value returned is the 'mode' field as defined in the
1306 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1307 * values are variations of possible behaviors relating to
1308 * blink, link, and wire.
1310 u32
i40e_led_get(struct i40e_hw
*hw
)
1312 u32 current_mode
= 0;
1316 /* as per the documentation GPIO 22-29 are the LED
1317 * GPIO pins named LED0..LED7
1319 for (i
= I40E_LED0
; i
<= I40E_GLGEN_GPIO_CTL_MAX_INDEX
; i
++) {
1320 u32 gpio_val
= i40e_led_is_mine(hw
, i
);
1325 /* ignore gpio LED src mode entries related to the activity
1328 current_mode
= ((gpio_val
& I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
)
1329 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
);
1330 switch (current_mode
) {
1331 case I40E_COMBINED_ACTIVITY
:
1332 case I40E_FILTER_ACTIVITY
:
1333 case I40E_MAC_ACTIVITY
:
1339 mode
= (gpio_val
& I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
) >>
1340 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
;
1348 * i40e_led_set - set new on/off mode
1349 * @hw: pointer to the hw struct
1350 * @mode: 0=off, 0xf=on (else see manual for mode details)
1351 * @blink: true if the LED should blink when on, false if steady
1353 * if this function is used to turn on the blink it should
1354 * be used to disable the blink when restoring the original state.
1356 void i40e_led_set(struct i40e_hw
*hw
, u32 mode
, bool blink
)
1358 u32 current_mode
= 0;
1361 if (mode
& 0xfffffff0)
1362 hw_dbg(hw
, "invalid mode passed in %X\n", mode
);
1364 /* as per the documentation GPIO 22-29 are the LED
1365 * GPIO pins named LED0..LED7
1367 for (i
= I40E_LED0
; i
<= I40E_GLGEN_GPIO_CTL_MAX_INDEX
; i
++) {
1368 u32 gpio_val
= i40e_led_is_mine(hw
, i
);
1373 /* ignore gpio LED src mode entries related to the activity
1376 current_mode
= ((gpio_val
& I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
)
1377 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
);
1378 switch (current_mode
) {
1379 case I40E_COMBINED_ACTIVITY
:
1380 case I40E_FILTER_ACTIVITY
:
1381 case I40E_MAC_ACTIVITY
:
1387 gpio_val
&= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
;
1388 /* this & is a bit of paranoia, but serves as a range check */
1389 gpio_val
|= ((mode
<< I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
) &
1390 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
);
1392 if (mode
== I40E_LINK_ACTIVITY
)
1396 gpio_val
|= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT
);
1398 gpio_val
&= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT
);
1400 wr32(hw
, I40E_GLGEN_GPIO_CTL(i
), gpio_val
);
1405 /* Admin command wrappers */
1408 * i40e_aq_get_phy_capabilities
1409 * @hw: pointer to the hw struct
1410 * @abilities: structure for PHY capabilities to be filled
1411 * @qualified_modules: report Qualified Modules
1412 * @report_init: report init capabilities (active are default)
1413 * @cmd_details: pointer to command details structure or NULL
1415 * Returns the various PHY abilities supported on the Port.
1417 i40e_status
i40e_aq_get_phy_capabilities(struct i40e_hw
*hw
,
1418 bool qualified_modules
, bool report_init
,
1419 struct i40e_aq_get_phy_abilities_resp
*abilities
,
1420 struct i40e_asq_cmd_details
*cmd_details
)
1422 struct i40e_aq_desc desc
;
1424 u16 abilities_size
= sizeof(struct i40e_aq_get_phy_abilities_resp
);
1427 return I40E_ERR_PARAM
;
1429 i40e_fill_default_direct_cmd_desc(&desc
,
1430 i40e_aqc_opc_get_phy_abilities
);
1432 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
1433 if (abilities_size
> I40E_AQ_LARGE_BUF
)
1434 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
1436 if (qualified_modules
)
1437 desc
.params
.external
.param0
|=
1438 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES
);
1441 desc
.params
.external
.param0
|=
1442 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES
);
1444 status
= i40e_asq_send_command(hw
, &desc
, abilities
, abilities_size
,
1447 if (hw
->aq
.asq_last_status
== I40E_AQ_RC_EIO
)
1448 status
= I40E_ERR_UNKNOWN_PHY
;
1454 * i40e_aq_set_phy_config
1455 * @hw: pointer to the hw struct
1456 * @config: structure with PHY configuration to be set
1457 * @cmd_details: pointer to command details structure or NULL
1459 * Set the various PHY configuration parameters
1460 * supported on the Port.One or more of the Set PHY config parameters may be
1461 * ignored in an MFP mode as the PF may not have the privilege to set some
1462 * of the PHY Config parameters. This status will be indicated by the
1465 enum i40e_status_code
i40e_aq_set_phy_config(struct i40e_hw
*hw
,
1466 struct i40e_aq_set_phy_config
*config
,
1467 struct i40e_asq_cmd_details
*cmd_details
)
1469 struct i40e_aq_desc desc
;
1470 struct i40e_aq_set_phy_config
*cmd
=
1471 (struct i40e_aq_set_phy_config
*)&desc
.params
.raw
;
1472 enum i40e_status_code status
;
1475 return I40E_ERR_PARAM
;
1477 i40e_fill_default_direct_cmd_desc(&desc
,
1478 i40e_aqc_opc_set_phy_config
);
1482 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1489 * @hw: pointer to the hw struct
1491 * Set the requested flow control mode using set_phy_config.
1493 enum i40e_status_code
i40e_set_fc(struct i40e_hw
*hw
, u8
*aq_failures
,
1494 bool atomic_restart
)
1496 enum i40e_fc_mode fc_mode
= hw
->fc
.requested_mode
;
1497 struct i40e_aq_get_phy_abilities_resp abilities
;
1498 struct i40e_aq_set_phy_config config
;
1499 enum i40e_status_code status
;
1500 u8 pause_mask
= 0x0;
1506 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_TX
;
1507 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_RX
;
1509 case I40E_FC_RX_PAUSE
:
1510 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_RX
;
1512 case I40E_FC_TX_PAUSE
:
1513 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_TX
;
1519 /* Get the current phy config */
1520 status
= i40e_aq_get_phy_capabilities(hw
, false, false, &abilities
,
1523 *aq_failures
|= I40E_SET_FC_AQ_FAIL_GET
;
1527 memset(&config
, 0, sizeof(struct i40e_aq_set_phy_config
));
1528 /* clear the old pause settings */
1529 config
.abilities
= abilities
.abilities
& ~(I40E_AQ_PHY_FLAG_PAUSE_TX
) &
1530 ~(I40E_AQ_PHY_FLAG_PAUSE_RX
);
1531 /* set the new abilities */
1532 config
.abilities
|= pause_mask
;
1533 /* If the abilities have changed, then set the new config */
1534 if (config
.abilities
!= abilities
.abilities
) {
1535 /* Auto restart link so settings take effect */
1537 config
.abilities
|= I40E_AQ_PHY_ENABLE_ATOMIC_LINK
;
1538 /* Copy over all the old settings */
1539 config
.phy_type
= abilities
.phy_type
;
1540 config
.link_speed
= abilities
.link_speed
;
1541 config
.eee_capability
= abilities
.eee_capability
;
1542 config
.eeer
= abilities
.eeer_val
;
1543 config
.low_power_ctrl
= abilities
.d3_lpan
;
1544 status
= i40e_aq_set_phy_config(hw
, &config
, NULL
);
1547 *aq_failures
|= I40E_SET_FC_AQ_FAIL_SET
;
1549 /* Update the link info */
1550 status
= i40e_aq_get_link_info(hw
, true, NULL
, NULL
);
1552 /* Wait a little bit (on 40G cards it sometimes takes a really
1553 * long time for link to come back from the atomic reset)
1557 status
= i40e_aq_get_link_info(hw
, true, NULL
, NULL
);
1560 *aq_failures
|= I40E_SET_FC_AQ_FAIL_UPDATE
;
1566 * i40e_aq_clear_pxe_mode
1567 * @hw: pointer to the hw struct
1568 * @cmd_details: pointer to command details structure or NULL
1570 * Tell the firmware that the driver is taking over from PXE
1572 i40e_status
i40e_aq_clear_pxe_mode(struct i40e_hw
*hw
,
1573 struct i40e_asq_cmd_details
*cmd_details
)
1576 struct i40e_aq_desc desc
;
1577 struct i40e_aqc_clear_pxe
*cmd
=
1578 (struct i40e_aqc_clear_pxe
*)&desc
.params
.raw
;
1580 i40e_fill_default_direct_cmd_desc(&desc
,
1581 i40e_aqc_opc_clear_pxe_mode
);
1585 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1587 wr32(hw
, I40E_GLLAN_RCTL_0
, 0x1);
1593 * i40e_aq_set_link_restart_an
1594 * @hw: pointer to the hw struct
1595 * @enable_link: if true: enable link, if false: disable link
1596 * @cmd_details: pointer to command details structure or NULL
1598 * Sets up the link and restarts the Auto-Negotiation over the link.
1600 i40e_status
i40e_aq_set_link_restart_an(struct i40e_hw
*hw
,
1602 struct i40e_asq_cmd_details
*cmd_details
)
1604 struct i40e_aq_desc desc
;
1605 struct i40e_aqc_set_link_restart_an
*cmd
=
1606 (struct i40e_aqc_set_link_restart_an
*)&desc
.params
.raw
;
1609 i40e_fill_default_direct_cmd_desc(&desc
,
1610 i40e_aqc_opc_set_link_restart_an
);
1612 cmd
->command
= I40E_AQ_PHY_RESTART_AN
;
1614 cmd
->command
|= I40E_AQ_PHY_LINK_ENABLE
;
1616 cmd
->command
&= ~I40E_AQ_PHY_LINK_ENABLE
;
1618 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1624 * i40e_aq_get_link_info
1625 * @hw: pointer to the hw struct
1626 * @enable_lse: enable/disable LinkStatusEvent reporting
1627 * @link: pointer to link status structure - optional
1628 * @cmd_details: pointer to command details structure or NULL
1630 * Returns the link status of the adapter.
1632 i40e_status
i40e_aq_get_link_info(struct i40e_hw
*hw
,
1633 bool enable_lse
, struct i40e_link_status
*link
,
1634 struct i40e_asq_cmd_details
*cmd_details
)
1636 struct i40e_aq_desc desc
;
1637 struct i40e_aqc_get_link_status
*resp
=
1638 (struct i40e_aqc_get_link_status
*)&desc
.params
.raw
;
1639 struct i40e_link_status
*hw_link_info
= &hw
->phy
.link_info
;
1641 bool tx_pause
, rx_pause
;
1644 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_get_link_status
);
1647 command_flags
= I40E_AQ_LSE_ENABLE
;
1649 command_flags
= I40E_AQ_LSE_DISABLE
;
1650 resp
->command_flags
= cpu_to_le16(command_flags
);
1652 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1655 goto aq_get_link_info_exit
;
1657 /* save off old link status information */
1658 hw
->phy
.link_info_old
= *hw_link_info
;
1660 /* update link status */
1661 hw_link_info
->phy_type
= (enum i40e_aq_phy_type
)resp
->phy_type
;
1662 hw
->phy
.media_type
= i40e_get_media_type(hw
);
1663 hw_link_info
->link_speed
= (enum i40e_aq_link_speed
)resp
->link_speed
;
1664 hw_link_info
->link_info
= resp
->link_info
;
1665 hw_link_info
->an_info
= resp
->an_info
;
1666 hw_link_info
->ext_info
= resp
->ext_info
;
1667 hw_link_info
->loopback
= resp
->loopback
;
1668 hw_link_info
->max_frame_size
= le16_to_cpu(resp
->max_frame_size
);
1669 hw_link_info
->pacing
= resp
->config
& I40E_AQ_CONFIG_PACING_MASK
;
1671 /* update fc info */
1672 tx_pause
= !!(resp
->an_info
& I40E_AQ_LINK_PAUSE_TX
);
1673 rx_pause
= !!(resp
->an_info
& I40E_AQ_LINK_PAUSE_RX
);
1674 if (tx_pause
& rx_pause
)
1675 hw
->fc
.current_mode
= I40E_FC_FULL
;
1677 hw
->fc
.current_mode
= I40E_FC_TX_PAUSE
;
1679 hw
->fc
.current_mode
= I40E_FC_RX_PAUSE
;
1681 hw
->fc
.current_mode
= I40E_FC_NONE
;
1683 if (resp
->config
& I40E_AQ_CONFIG_CRC_ENA
)
1684 hw_link_info
->crc_enable
= true;
1686 hw_link_info
->crc_enable
= false;
1688 if (resp
->command_flags
& cpu_to_le16(I40E_AQ_LSE_ENABLE
))
1689 hw_link_info
->lse_enable
= true;
1691 hw_link_info
->lse_enable
= false;
1693 if ((hw
->aq
.fw_maj_ver
< 4 || (hw
->aq
.fw_maj_ver
== 4 &&
1694 hw
->aq
.fw_min_ver
< 40)) && hw_link_info
->phy_type
== 0xE)
1695 hw_link_info
->phy_type
= I40E_PHY_TYPE_10GBASE_SFPP_CU
;
1697 /* save link status information */
1699 *link
= *hw_link_info
;
1701 /* flag cleared so helper functions don't call AQ again */
1702 hw
->phy
.get_link_info
= false;
1704 aq_get_link_info_exit
:
1709 * i40e_aq_set_phy_int_mask
1710 * @hw: pointer to the hw struct
1711 * @mask: interrupt mask to be set
1712 * @cmd_details: pointer to command details structure or NULL
1714 * Set link interrupt mask.
1716 i40e_status
i40e_aq_set_phy_int_mask(struct i40e_hw
*hw
,
1718 struct i40e_asq_cmd_details
*cmd_details
)
1720 struct i40e_aq_desc desc
;
1721 struct i40e_aqc_set_phy_int_mask
*cmd
=
1722 (struct i40e_aqc_set_phy_int_mask
*)&desc
.params
.raw
;
1725 i40e_fill_default_direct_cmd_desc(&desc
,
1726 i40e_aqc_opc_set_phy_int_mask
);
1728 cmd
->event_mask
= cpu_to_le16(mask
);
1730 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1737 * @hw: pointer to the hw struct
1738 * @vsi_ctx: pointer to a vsi context struct
1739 * @cmd_details: pointer to command details structure or NULL
1741 * Add a VSI context to the hardware.
1743 i40e_status
i40e_aq_add_vsi(struct i40e_hw
*hw
,
1744 struct i40e_vsi_context
*vsi_ctx
,
1745 struct i40e_asq_cmd_details
*cmd_details
)
1747 struct i40e_aq_desc desc
;
1748 struct i40e_aqc_add_get_update_vsi
*cmd
=
1749 (struct i40e_aqc_add_get_update_vsi
*)&desc
.params
.raw
;
1750 struct i40e_aqc_add_get_update_vsi_completion
*resp
=
1751 (struct i40e_aqc_add_get_update_vsi_completion
*)
1755 i40e_fill_default_direct_cmd_desc(&desc
,
1756 i40e_aqc_opc_add_vsi
);
1758 cmd
->uplink_seid
= cpu_to_le16(vsi_ctx
->uplink_seid
);
1759 cmd
->connection_type
= vsi_ctx
->connection_type
;
1760 cmd
->vf_id
= vsi_ctx
->vf_num
;
1761 cmd
->vsi_flags
= cpu_to_le16(vsi_ctx
->flags
);
1763 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
1765 status
= i40e_asq_send_command(hw
, &desc
, &vsi_ctx
->info
,
1766 sizeof(vsi_ctx
->info
), cmd_details
);
1769 goto aq_add_vsi_exit
;
1771 vsi_ctx
->seid
= le16_to_cpu(resp
->seid
);
1772 vsi_ctx
->vsi_number
= le16_to_cpu(resp
->vsi_number
);
1773 vsi_ctx
->vsis_allocated
= le16_to_cpu(resp
->vsi_used
);
1774 vsi_ctx
->vsis_unallocated
= le16_to_cpu(resp
->vsi_free
);
1781 * i40e_aq_set_vsi_unicast_promiscuous
1782 * @hw: pointer to the hw struct
1784 * @set: set unicast promiscuous enable/disable
1785 * @cmd_details: pointer to command details structure or NULL
1787 i40e_status
i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw
*hw
,
1789 struct i40e_asq_cmd_details
*cmd_details
)
1791 struct i40e_aq_desc desc
;
1792 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
1793 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
1797 i40e_fill_default_direct_cmd_desc(&desc
,
1798 i40e_aqc_opc_set_vsi_promiscuous_modes
);
1801 flags
|= I40E_AQC_SET_VSI_PROMISC_UNICAST
;
1803 cmd
->promiscuous_flags
= cpu_to_le16(flags
);
1805 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST
);
1807 cmd
->seid
= cpu_to_le16(seid
);
1808 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1814 * i40e_aq_set_vsi_multicast_promiscuous
1815 * @hw: pointer to the hw struct
1817 * @set: set multicast promiscuous enable/disable
1818 * @cmd_details: pointer to command details structure or NULL
1820 i40e_status
i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw
*hw
,
1821 u16 seid
, bool set
, struct i40e_asq_cmd_details
*cmd_details
)
1823 struct i40e_aq_desc desc
;
1824 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
1825 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
1829 i40e_fill_default_direct_cmd_desc(&desc
,
1830 i40e_aqc_opc_set_vsi_promiscuous_modes
);
1833 flags
|= I40E_AQC_SET_VSI_PROMISC_MULTICAST
;
1835 cmd
->promiscuous_flags
= cpu_to_le16(flags
);
1837 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST
);
1839 cmd
->seid
= cpu_to_le16(seid
);
1840 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1846 * i40e_aq_set_vsi_broadcast
1847 * @hw: pointer to the hw struct
1849 * @set_filter: true to set filter, false to clear filter
1850 * @cmd_details: pointer to command details structure or NULL
1852 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1854 i40e_status
i40e_aq_set_vsi_broadcast(struct i40e_hw
*hw
,
1855 u16 seid
, bool set_filter
,
1856 struct i40e_asq_cmd_details
*cmd_details
)
1858 struct i40e_aq_desc desc
;
1859 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
1860 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
1863 i40e_fill_default_direct_cmd_desc(&desc
,
1864 i40e_aqc_opc_set_vsi_promiscuous_modes
);
1867 cmd
->promiscuous_flags
1868 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST
);
1870 cmd
->promiscuous_flags
1871 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST
);
1873 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST
);
1874 cmd
->seid
= cpu_to_le16(seid
);
1875 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1881 * i40e_get_vsi_params - get VSI configuration info
1882 * @hw: pointer to the hw struct
1883 * @vsi_ctx: pointer to a vsi context struct
1884 * @cmd_details: pointer to command details structure or NULL
1886 i40e_status
i40e_aq_get_vsi_params(struct i40e_hw
*hw
,
1887 struct i40e_vsi_context
*vsi_ctx
,
1888 struct i40e_asq_cmd_details
*cmd_details
)
1890 struct i40e_aq_desc desc
;
1891 struct i40e_aqc_add_get_update_vsi
*cmd
=
1892 (struct i40e_aqc_add_get_update_vsi
*)&desc
.params
.raw
;
1893 struct i40e_aqc_add_get_update_vsi_completion
*resp
=
1894 (struct i40e_aqc_add_get_update_vsi_completion
*)
1898 i40e_fill_default_direct_cmd_desc(&desc
,
1899 i40e_aqc_opc_get_vsi_parameters
);
1901 cmd
->uplink_seid
= cpu_to_le16(vsi_ctx
->seid
);
1903 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
1905 status
= i40e_asq_send_command(hw
, &desc
, &vsi_ctx
->info
,
1906 sizeof(vsi_ctx
->info
), NULL
);
1909 goto aq_get_vsi_params_exit
;
1911 vsi_ctx
->seid
= le16_to_cpu(resp
->seid
);
1912 vsi_ctx
->vsi_number
= le16_to_cpu(resp
->vsi_number
);
1913 vsi_ctx
->vsis_allocated
= le16_to_cpu(resp
->vsi_used
);
1914 vsi_ctx
->vsis_unallocated
= le16_to_cpu(resp
->vsi_free
);
1916 aq_get_vsi_params_exit
:
1921 * i40e_aq_update_vsi_params
1922 * @hw: pointer to the hw struct
1923 * @vsi_ctx: pointer to a vsi context struct
1924 * @cmd_details: pointer to command details structure or NULL
1926 * Update a VSI context.
1928 i40e_status
i40e_aq_update_vsi_params(struct i40e_hw
*hw
,
1929 struct i40e_vsi_context
*vsi_ctx
,
1930 struct i40e_asq_cmd_details
*cmd_details
)
1932 struct i40e_aq_desc desc
;
1933 struct i40e_aqc_add_get_update_vsi
*cmd
=
1934 (struct i40e_aqc_add_get_update_vsi
*)&desc
.params
.raw
;
1937 i40e_fill_default_direct_cmd_desc(&desc
,
1938 i40e_aqc_opc_update_vsi_parameters
);
1939 cmd
->uplink_seid
= cpu_to_le16(vsi_ctx
->seid
);
1941 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
1943 status
= i40e_asq_send_command(hw
, &desc
, &vsi_ctx
->info
,
1944 sizeof(vsi_ctx
->info
), cmd_details
);
1950 * i40e_aq_get_switch_config
1951 * @hw: pointer to the hardware structure
1952 * @buf: pointer to the result buffer
1953 * @buf_size: length of input buffer
1954 * @start_seid: seid to start for the report, 0 == beginning
1955 * @cmd_details: pointer to command details structure or NULL
1957 * Fill the buf with switch configuration returned from AdminQ command
1959 i40e_status
i40e_aq_get_switch_config(struct i40e_hw
*hw
,
1960 struct i40e_aqc_get_switch_config_resp
*buf
,
1961 u16 buf_size
, u16
*start_seid
,
1962 struct i40e_asq_cmd_details
*cmd_details
)
1964 struct i40e_aq_desc desc
;
1965 struct i40e_aqc_switch_seid
*scfg
=
1966 (struct i40e_aqc_switch_seid
*)&desc
.params
.raw
;
1969 i40e_fill_default_direct_cmd_desc(&desc
,
1970 i40e_aqc_opc_get_switch_config
);
1971 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
1972 if (buf_size
> I40E_AQ_LARGE_BUF
)
1973 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
1974 scfg
->seid
= cpu_to_le16(*start_seid
);
1976 status
= i40e_asq_send_command(hw
, &desc
, buf
, buf_size
, cmd_details
);
1977 *start_seid
= le16_to_cpu(scfg
->seid
);
1983 * i40e_aq_get_firmware_version
1984 * @hw: pointer to the hw struct
1985 * @fw_major_version: firmware major version
1986 * @fw_minor_version: firmware minor version
1987 * @fw_build: firmware build number
1988 * @api_major_version: major queue version
1989 * @api_minor_version: minor queue version
1990 * @cmd_details: pointer to command details structure or NULL
1992 * Get the firmware version from the admin queue commands
1994 i40e_status
i40e_aq_get_firmware_version(struct i40e_hw
*hw
,
1995 u16
*fw_major_version
, u16
*fw_minor_version
,
1997 u16
*api_major_version
, u16
*api_minor_version
,
1998 struct i40e_asq_cmd_details
*cmd_details
)
2000 struct i40e_aq_desc desc
;
2001 struct i40e_aqc_get_version
*resp
=
2002 (struct i40e_aqc_get_version
*)&desc
.params
.raw
;
2005 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_get_version
);
2007 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2010 if (fw_major_version
)
2011 *fw_major_version
= le16_to_cpu(resp
->fw_major
);
2012 if (fw_minor_version
)
2013 *fw_minor_version
= le16_to_cpu(resp
->fw_minor
);
2015 *fw_build
= le32_to_cpu(resp
->fw_build
);
2016 if (api_major_version
)
2017 *api_major_version
= le16_to_cpu(resp
->api_major
);
2018 if (api_minor_version
)
2019 *api_minor_version
= le16_to_cpu(resp
->api_minor
);
2026 * i40e_aq_send_driver_version
2027 * @hw: pointer to the hw struct
2028 * @dv: driver's major, minor version
2029 * @cmd_details: pointer to command details structure or NULL
2031 * Send the driver version to the firmware
2033 i40e_status
i40e_aq_send_driver_version(struct i40e_hw
*hw
,
2034 struct i40e_driver_version
*dv
,
2035 struct i40e_asq_cmd_details
*cmd_details
)
2037 struct i40e_aq_desc desc
;
2038 struct i40e_aqc_driver_version
*cmd
=
2039 (struct i40e_aqc_driver_version
*)&desc
.params
.raw
;
2044 return I40E_ERR_PARAM
;
2046 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_driver_version
);
2048 desc
.flags
|= cpu_to_le16(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
);
2049 cmd
->driver_major_ver
= dv
->major_version
;
2050 cmd
->driver_minor_ver
= dv
->minor_version
;
2051 cmd
->driver_build_ver
= dv
->build_version
;
2052 cmd
->driver_subbuild_ver
= dv
->subbuild_version
;
2055 while (len
< sizeof(dv
->driver_string
) &&
2056 (dv
->driver_string
[len
] < 0x80) &&
2057 dv
->driver_string
[len
])
2059 status
= i40e_asq_send_command(hw
, &desc
, dv
->driver_string
,
2066 * i40e_get_link_status - get status of the HW network link
2067 * @hw: pointer to the hw struct
2069 * Returns true if link is up, false if link is down.
2071 * Side effect: LinkStatusEvent reporting becomes enabled
2073 bool i40e_get_link_status(struct i40e_hw
*hw
)
2075 i40e_status status
= 0;
2076 bool link_status
= false;
2078 if (hw
->phy
.get_link_info
) {
2079 status
= i40e_aq_get_link_info(hw
, true, NULL
, NULL
);
2082 goto i40e_get_link_status_exit
;
2085 link_status
= hw
->phy
.link_info
.link_info
& I40E_AQ_LINK_UP
;
2087 i40e_get_link_status_exit
:
2092 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2093 * @hw: pointer to the hw struct
2094 * @uplink_seid: the MAC or other gizmo SEID
2095 * @downlink_seid: the VSI SEID
2096 * @enabled_tc: bitmap of TCs to be enabled
2097 * @default_port: true for default port VSI, false for control port
2098 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2099 * @veb_seid: pointer to where to put the resulting VEB SEID
2100 * @cmd_details: pointer to command details structure or NULL
2102 * This asks the FW to add a VEB between the uplink and downlink
2103 * elements. If the uplink SEID is 0, this will be a floating VEB.
2105 i40e_status
i40e_aq_add_veb(struct i40e_hw
*hw
, u16 uplink_seid
,
2106 u16 downlink_seid
, u8 enabled_tc
,
2107 bool default_port
, bool enable_l2_filtering
,
2109 struct i40e_asq_cmd_details
*cmd_details
)
2111 struct i40e_aq_desc desc
;
2112 struct i40e_aqc_add_veb
*cmd
=
2113 (struct i40e_aqc_add_veb
*)&desc
.params
.raw
;
2114 struct i40e_aqc_add_veb_completion
*resp
=
2115 (struct i40e_aqc_add_veb_completion
*)&desc
.params
.raw
;
2119 /* SEIDs need to either both be set or both be 0 for floating VEB */
2120 if (!!uplink_seid
!= !!downlink_seid
)
2121 return I40E_ERR_PARAM
;
2123 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_add_veb
);
2125 cmd
->uplink_seid
= cpu_to_le16(uplink_seid
);
2126 cmd
->downlink_seid
= cpu_to_le16(downlink_seid
);
2127 cmd
->enable_tcs
= enabled_tc
;
2129 veb_flags
|= I40E_AQC_ADD_VEB_FLOATING
;
2131 veb_flags
|= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT
;
2133 veb_flags
|= I40E_AQC_ADD_VEB_PORT_TYPE_DATA
;
2135 if (enable_l2_filtering
)
2136 veb_flags
|= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER
;
2138 cmd
->veb_flags
= cpu_to_le16(veb_flags
);
2140 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2142 if (!status
&& veb_seid
)
2143 *veb_seid
= le16_to_cpu(resp
->veb_seid
);
2149 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2150 * @hw: pointer to the hw struct
2151 * @veb_seid: the SEID of the VEB to query
2152 * @switch_id: the uplink switch id
2153 * @floating: set to true if the VEB is floating
2154 * @statistic_index: index of the stats counter block for this VEB
2155 * @vebs_used: number of VEB's used by function
2156 * @vebs_free: total VEB's not reserved by any function
2157 * @cmd_details: pointer to command details structure or NULL
2159 * This retrieves the parameters for a particular VEB, specified by
2160 * uplink_seid, and returns them to the caller.
2162 i40e_status
i40e_aq_get_veb_parameters(struct i40e_hw
*hw
,
2163 u16 veb_seid
, u16
*switch_id
,
2164 bool *floating
, u16
*statistic_index
,
2165 u16
*vebs_used
, u16
*vebs_free
,
2166 struct i40e_asq_cmd_details
*cmd_details
)
2168 struct i40e_aq_desc desc
;
2169 struct i40e_aqc_get_veb_parameters_completion
*cmd_resp
=
2170 (struct i40e_aqc_get_veb_parameters_completion
*)
2175 return I40E_ERR_PARAM
;
2177 i40e_fill_default_direct_cmd_desc(&desc
,
2178 i40e_aqc_opc_get_veb_parameters
);
2179 cmd_resp
->seid
= cpu_to_le16(veb_seid
);
2181 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2186 *switch_id
= le16_to_cpu(cmd_resp
->switch_id
);
2187 if (statistic_index
)
2188 *statistic_index
= le16_to_cpu(cmd_resp
->statistic_index
);
2190 *vebs_used
= le16_to_cpu(cmd_resp
->vebs_used
);
2192 *vebs_free
= le16_to_cpu(cmd_resp
->vebs_free
);
2194 u16 flags
= le16_to_cpu(cmd_resp
->veb_flags
);
2195 if (flags
& I40E_AQC_ADD_VEB_FLOATING
)
2206 * i40e_aq_add_macvlan
2207 * @hw: pointer to the hw struct
2208 * @seid: VSI for the mac address
2209 * @mv_list: list of macvlans to be added
2210 * @count: length of the list
2211 * @cmd_details: pointer to command details structure or NULL
2213 * Add MAC/VLAN addresses to the HW filtering
2215 i40e_status
i40e_aq_add_macvlan(struct i40e_hw
*hw
, u16 seid
,
2216 struct i40e_aqc_add_macvlan_element_data
*mv_list
,
2217 u16 count
, struct i40e_asq_cmd_details
*cmd_details
)
2219 struct i40e_aq_desc desc
;
2220 struct i40e_aqc_macvlan
*cmd
=
2221 (struct i40e_aqc_macvlan
*)&desc
.params
.raw
;
2225 if (count
== 0 || !mv_list
|| !hw
)
2226 return I40E_ERR_PARAM
;
2228 buf_size
= count
* sizeof(*mv_list
);
2230 /* prep the rest of the request */
2231 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_add_macvlan
);
2232 cmd
->num_addresses
= cpu_to_le16(count
);
2233 cmd
->seid
[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID
| seid
);
2237 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
2238 if (buf_size
> I40E_AQ_LARGE_BUF
)
2239 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2241 status
= i40e_asq_send_command(hw
, &desc
, mv_list
, buf_size
,
2248 * i40e_aq_remove_macvlan
2249 * @hw: pointer to the hw struct
2250 * @seid: VSI for the mac address
2251 * @mv_list: list of macvlans to be removed
2252 * @count: length of the list
2253 * @cmd_details: pointer to command details structure or NULL
2255 * Remove MAC/VLAN addresses from the HW filtering
2257 i40e_status
i40e_aq_remove_macvlan(struct i40e_hw
*hw
, u16 seid
,
2258 struct i40e_aqc_remove_macvlan_element_data
*mv_list
,
2259 u16 count
, struct i40e_asq_cmd_details
*cmd_details
)
2261 struct i40e_aq_desc desc
;
2262 struct i40e_aqc_macvlan
*cmd
=
2263 (struct i40e_aqc_macvlan
*)&desc
.params
.raw
;
2267 if (count
== 0 || !mv_list
|| !hw
)
2268 return I40E_ERR_PARAM
;
2270 buf_size
= count
* sizeof(*mv_list
);
2272 /* prep the rest of the request */
2273 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_remove_macvlan
);
2274 cmd
->num_addresses
= cpu_to_le16(count
);
2275 cmd
->seid
[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID
| seid
);
2279 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
2280 if (buf_size
> I40E_AQ_LARGE_BUF
)
2281 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2283 status
= i40e_asq_send_command(hw
, &desc
, mv_list
, buf_size
,
2290 * i40e_aq_send_msg_to_vf
2291 * @hw: pointer to the hardware structure
2292 * @vfid: VF id to send msg
2293 * @v_opcode: opcodes for VF-PF communication
2294 * @v_retval: return error code
2295 * @msg: pointer to the msg buffer
2296 * @msglen: msg length
2297 * @cmd_details: pointer to command details
2301 i40e_status
i40e_aq_send_msg_to_vf(struct i40e_hw
*hw
, u16 vfid
,
2302 u32 v_opcode
, u32 v_retval
, u8
*msg
, u16 msglen
,
2303 struct i40e_asq_cmd_details
*cmd_details
)
2305 struct i40e_aq_desc desc
;
2306 struct i40e_aqc_pf_vf_message
*cmd
=
2307 (struct i40e_aqc_pf_vf_message
*)&desc
.params
.raw
;
2310 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_send_msg_to_vf
);
2311 cmd
->id
= cpu_to_le32(vfid
);
2312 desc
.cookie_high
= cpu_to_le32(v_opcode
);
2313 desc
.cookie_low
= cpu_to_le32(v_retval
);
2314 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_SI
);
2316 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
|
2318 if (msglen
> I40E_AQ_LARGE_BUF
)
2319 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2320 desc
.datalen
= cpu_to_le16(msglen
);
2322 status
= i40e_asq_send_command(hw
, &desc
, msg
, msglen
, cmd_details
);
2328 * i40e_aq_debug_read_register
2329 * @hw: pointer to the hw struct
2330 * @reg_addr: register address
2331 * @reg_val: register value
2332 * @cmd_details: pointer to command details structure or NULL
2334 * Read the register using the admin queue commands
2336 i40e_status
i40e_aq_debug_read_register(struct i40e_hw
*hw
,
2337 u32 reg_addr
, u64
*reg_val
,
2338 struct i40e_asq_cmd_details
*cmd_details
)
2340 struct i40e_aq_desc desc
;
2341 struct i40e_aqc_debug_reg_read_write
*cmd_resp
=
2342 (struct i40e_aqc_debug_reg_read_write
*)&desc
.params
.raw
;
2345 if (reg_val
== NULL
)
2346 return I40E_ERR_PARAM
;
2348 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_debug_read_reg
);
2350 cmd_resp
->address
= cpu_to_le32(reg_addr
);
2352 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2355 *reg_val
= ((u64
)le32_to_cpu(cmd_resp
->value_high
) << 32) |
2356 (u64
)le32_to_cpu(cmd_resp
->value_low
);
2363 * i40e_aq_debug_write_register
2364 * @hw: pointer to the hw struct
2365 * @reg_addr: register address
2366 * @reg_val: register value
2367 * @cmd_details: pointer to command details structure or NULL
2369 * Write to a register using the admin queue commands
2371 i40e_status
i40e_aq_debug_write_register(struct i40e_hw
*hw
,
2372 u32 reg_addr
, u64 reg_val
,
2373 struct i40e_asq_cmd_details
*cmd_details
)
2375 struct i40e_aq_desc desc
;
2376 struct i40e_aqc_debug_reg_read_write
*cmd
=
2377 (struct i40e_aqc_debug_reg_read_write
*)&desc
.params
.raw
;
2380 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_debug_write_reg
);
2382 cmd
->address
= cpu_to_le32(reg_addr
);
2383 cmd
->value_high
= cpu_to_le32((u32
)(reg_val
>> 32));
2384 cmd
->value_low
= cpu_to_le32((u32
)(reg_val
& 0xFFFFFFFF));
2386 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2392 * i40e_aq_set_hmc_resource_profile
2393 * @hw: pointer to the hw struct
2394 * @profile: type of profile the HMC is to be set as
2395 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2396 * @cmd_details: pointer to command details structure or NULL
2398 * set the HMC profile of the device.
2400 i40e_status
i40e_aq_set_hmc_resource_profile(struct i40e_hw
*hw
,
2401 enum i40e_aq_hmc_profile profile
,
2402 u8 pe_vf_enabled_count
,
2403 struct i40e_asq_cmd_details
*cmd_details
)
2405 struct i40e_aq_desc desc
;
2406 struct i40e_aq_get_set_hmc_resource_profile
*cmd
=
2407 (struct i40e_aq_get_set_hmc_resource_profile
*)&desc
.params
.raw
;
2410 i40e_fill_default_direct_cmd_desc(&desc
,
2411 i40e_aqc_opc_set_hmc_resource_profile
);
2413 cmd
->pm_profile
= (u8
)profile
;
2414 cmd
->pe_vf_enabled
= pe_vf_enabled_count
;
2416 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2422 * i40e_aq_request_resource
2423 * @hw: pointer to the hw struct
2424 * @resource: resource id
2425 * @access: access type
2426 * @sdp_number: resource number
2427 * @timeout: the maximum time in ms that the driver may hold the resource
2428 * @cmd_details: pointer to command details structure or NULL
2430 * requests common resource using the admin queue commands
2432 i40e_status
i40e_aq_request_resource(struct i40e_hw
*hw
,
2433 enum i40e_aq_resources_ids resource
,
2434 enum i40e_aq_resource_access_type access
,
2435 u8 sdp_number
, u64
*timeout
,
2436 struct i40e_asq_cmd_details
*cmd_details
)
2438 struct i40e_aq_desc desc
;
2439 struct i40e_aqc_request_resource
*cmd_resp
=
2440 (struct i40e_aqc_request_resource
*)&desc
.params
.raw
;
2443 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_request_resource
);
2445 cmd_resp
->resource_id
= cpu_to_le16(resource
);
2446 cmd_resp
->access_type
= cpu_to_le16(access
);
2447 cmd_resp
->resource_number
= cpu_to_le32(sdp_number
);
2449 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2450 /* The completion specifies the maximum time in ms that the driver
2451 * may hold the resource in the Timeout field.
2452 * If the resource is held by someone else, the command completes with
2453 * busy return value and the timeout field indicates the maximum time
2454 * the current owner of the resource has to free it.
2456 if (!status
|| hw
->aq
.asq_last_status
== I40E_AQ_RC_EBUSY
)
2457 *timeout
= le32_to_cpu(cmd_resp
->timeout
);
2463 * i40e_aq_release_resource
2464 * @hw: pointer to the hw struct
2465 * @resource: resource id
2466 * @sdp_number: resource number
2467 * @cmd_details: pointer to command details structure or NULL
2469 * release common resource using the admin queue commands
2471 i40e_status
i40e_aq_release_resource(struct i40e_hw
*hw
,
2472 enum i40e_aq_resources_ids resource
,
2474 struct i40e_asq_cmd_details
*cmd_details
)
2476 struct i40e_aq_desc desc
;
2477 struct i40e_aqc_request_resource
*cmd
=
2478 (struct i40e_aqc_request_resource
*)&desc
.params
.raw
;
2481 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_release_resource
);
2483 cmd
->resource_id
= cpu_to_le16(resource
);
2484 cmd
->resource_number
= cpu_to_le32(sdp_number
);
2486 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2493 * @hw: pointer to the hw struct
2494 * @module_pointer: module pointer location in words from the NVM beginning
2495 * @offset: byte offset from the module beginning
2496 * @length: length of the section to be read (in bytes from the offset)
2497 * @data: command buffer (size [bytes] = length)
2498 * @last_command: tells if this is the last command in a series
2499 * @cmd_details: pointer to command details structure or NULL
2501 * Read the NVM using the admin queue commands
2503 i40e_status
i40e_aq_read_nvm(struct i40e_hw
*hw
, u8 module_pointer
,
2504 u32 offset
, u16 length
, void *data
,
2506 struct i40e_asq_cmd_details
*cmd_details
)
2508 struct i40e_aq_desc desc
;
2509 struct i40e_aqc_nvm_update
*cmd
=
2510 (struct i40e_aqc_nvm_update
*)&desc
.params
.raw
;
2513 /* In offset the highest byte must be zeroed. */
2514 if (offset
& 0xFF000000) {
2515 status
= I40E_ERR_PARAM
;
2516 goto i40e_aq_read_nvm_exit
;
2519 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_nvm_read
);
2521 /* If this is the last command in a series, set the proper flag. */
2523 cmd
->command_flags
|= I40E_AQ_NVM_LAST_CMD
;
2524 cmd
->module_pointer
= module_pointer
;
2525 cmd
->offset
= cpu_to_le32(offset
);
2526 cmd
->length
= cpu_to_le16(length
);
2528 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2529 if (length
> I40E_AQ_LARGE_BUF
)
2530 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2532 status
= i40e_asq_send_command(hw
, &desc
, data
, length
, cmd_details
);
2534 i40e_aq_read_nvm_exit
:
2540 * @hw: pointer to the hw struct
2541 * @module_pointer: module pointer location in words from the NVM beginning
2542 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2543 * @length: length of the section to be erased (expressed in 4 KB)
2544 * @last_command: tells if this is the last command in a series
2545 * @cmd_details: pointer to command details structure or NULL
2547 * Erase the NVM sector using the admin queue commands
2549 i40e_status
i40e_aq_erase_nvm(struct i40e_hw
*hw
, u8 module_pointer
,
2550 u32 offset
, u16 length
, bool last_command
,
2551 struct i40e_asq_cmd_details
*cmd_details
)
2553 struct i40e_aq_desc desc
;
2554 struct i40e_aqc_nvm_update
*cmd
=
2555 (struct i40e_aqc_nvm_update
*)&desc
.params
.raw
;
2558 /* In offset the highest byte must be zeroed. */
2559 if (offset
& 0xFF000000) {
2560 status
= I40E_ERR_PARAM
;
2561 goto i40e_aq_erase_nvm_exit
;
2564 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_nvm_erase
);
2566 /* If this is the last command in a series, set the proper flag. */
2568 cmd
->command_flags
|= I40E_AQ_NVM_LAST_CMD
;
2569 cmd
->module_pointer
= module_pointer
;
2570 cmd
->offset
= cpu_to_le32(offset
);
2571 cmd
->length
= cpu_to_le16(length
);
2573 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2575 i40e_aq_erase_nvm_exit
:
2579 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2580 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2581 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2582 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2583 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2584 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2585 #define I40E_DEV_FUNC_CAP_VF 0x13
2586 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2587 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2588 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2589 #define I40E_DEV_FUNC_CAP_VSI 0x17
2590 #define I40E_DEV_FUNC_CAP_DCB 0x18
2591 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2592 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
2593 #define I40E_DEV_FUNC_CAP_RSS 0x40
2594 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2595 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2596 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2597 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2598 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2599 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2600 #define I40E_DEV_FUNC_CAP_FLEX10 0xF1
2601 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2602 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2603 #define I40E_DEV_FUNC_CAP_LED 0x61
2604 #define I40E_DEV_FUNC_CAP_SDP 0x62
2605 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2606 #define I40E_DEV_FUNC_CAP_WR_CSR_PROT 0x64
2609 * i40e_parse_discover_capabilities
2610 * @hw: pointer to the hw struct
2611 * @buff: pointer to a buffer containing device/function capability records
2612 * @cap_count: number of capability records in the list
2613 * @list_type_opc: type of capabilities list to parse
2615 * Parse the device/function capabilities list.
2617 static void i40e_parse_discover_capabilities(struct i40e_hw
*hw
, void *buff
,
2619 enum i40e_admin_queue_opc list_type_opc
)
2621 struct i40e_aqc_list_capabilities_element_resp
*cap
;
2622 u32 valid_functions
, num_functions
;
2623 u32 number
, logical_id
, phys_id
;
2624 struct i40e_hw_capabilities
*p
;
2629 cap
= (struct i40e_aqc_list_capabilities_element_resp
*) buff
;
2631 if (list_type_opc
== i40e_aqc_opc_list_dev_capabilities
)
2633 else if (list_type_opc
== i40e_aqc_opc_list_func_capabilities
)
2638 for (i
= 0; i
< cap_count
; i
++, cap
++) {
2639 id
= le16_to_cpu(cap
->id
);
2640 number
= le32_to_cpu(cap
->number
);
2641 logical_id
= le32_to_cpu(cap
->logical_id
);
2642 phys_id
= le32_to_cpu(cap
->phys_id
);
2643 major_rev
= cap
->major_rev
;
2646 case I40E_DEV_FUNC_CAP_SWITCH_MODE
:
2647 p
->switch_mode
= number
;
2649 case I40E_DEV_FUNC_CAP_MGMT_MODE
:
2650 p
->management_mode
= number
;
2652 case I40E_DEV_FUNC_CAP_NPAR
:
2653 p
->npar_enable
= number
;
2655 case I40E_DEV_FUNC_CAP_OS2BMC
:
2658 case I40E_DEV_FUNC_CAP_VALID_FUNC
:
2659 p
->valid_functions
= number
;
2661 case I40E_DEV_FUNC_CAP_SRIOV_1_1
:
2663 p
->sr_iov_1_1
= true;
2665 case I40E_DEV_FUNC_CAP_VF
:
2666 p
->num_vfs
= number
;
2667 p
->vf_base_id
= logical_id
;
2669 case I40E_DEV_FUNC_CAP_VMDQ
:
2673 case I40E_DEV_FUNC_CAP_802_1_QBG
:
2675 p
->evb_802_1_qbg
= true;
2677 case I40E_DEV_FUNC_CAP_802_1_QBH
:
2679 p
->evb_802_1_qbh
= true;
2681 case I40E_DEV_FUNC_CAP_VSI
:
2682 p
->num_vsis
= number
;
2684 case I40E_DEV_FUNC_CAP_DCB
:
2687 p
->enabled_tcmap
= logical_id
;
2691 case I40E_DEV_FUNC_CAP_FCOE
:
2695 case I40E_DEV_FUNC_CAP_ISCSI
:
2699 case I40E_DEV_FUNC_CAP_RSS
:
2701 p
->rss_table_size
= number
;
2702 p
->rss_table_entry_width
= logical_id
;
2704 case I40E_DEV_FUNC_CAP_RX_QUEUES
:
2705 p
->num_rx_qp
= number
;
2706 p
->base_queue
= phys_id
;
2708 case I40E_DEV_FUNC_CAP_TX_QUEUES
:
2709 p
->num_tx_qp
= number
;
2710 p
->base_queue
= phys_id
;
2712 case I40E_DEV_FUNC_CAP_MSIX
:
2713 p
->num_msix_vectors
= number
;
2715 case I40E_DEV_FUNC_CAP_MSIX_VF
:
2716 p
->num_msix_vectors_vf
= number
;
2718 case I40E_DEV_FUNC_CAP_FLEX10
:
2719 if (major_rev
== 1) {
2721 p
->flex10_enable
= true;
2722 p
->flex10_capable
= true;
2725 /* Capability revision >= 2 */
2727 p
->flex10_enable
= true;
2729 p
->flex10_capable
= true;
2731 p
->flex10_mode
= logical_id
;
2732 p
->flex10_status
= phys_id
;
2734 case I40E_DEV_FUNC_CAP_CEM
:
2738 case I40E_DEV_FUNC_CAP_IWARP
:
2742 case I40E_DEV_FUNC_CAP_LED
:
2743 if (phys_id
< I40E_HW_CAP_MAX_GPIO
)
2744 p
->led
[phys_id
] = true;
2746 case I40E_DEV_FUNC_CAP_SDP
:
2747 if (phys_id
< I40E_HW_CAP_MAX_GPIO
)
2748 p
->sdp
[phys_id
] = true;
2750 case I40E_DEV_FUNC_CAP_MDIO
:
2752 p
->mdio_port_num
= phys_id
;
2753 p
->mdio_port_mode
= logical_id
;
2756 case I40E_DEV_FUNC_CAP_IEEE_1588
:
2758 p
->ieee_1588
= true;
2760 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR
:
2762 p
->fd_filters_guaranteed
= number
;
2763 p
->fd_filters_best_effort
= logical_id
;
2765 case I40E_DEV_FUNC_CAP_WR_CSR_PROT
:
2766 p
->wr_csr_prot
= (u64
)number
;
2767 p
->wr_csr_prot
|= (u64
)logical_id
<< 32;
2775 i40e_debug(hw
, I40E_DEBUG_ALL
, "device is FCoE capable\n");
2777 /* Software override ensuring FCoE is disabled if npar or mfp
2778 * mode because it is not supported in these modes.
2780 if (p
->npar_enable
|| p
->flex10_enable
)
2783 /* count the enabled ports (aka the "not disabled" ports) */
2785 for (i
= 0; i
< 4; i
++) {
2786 u32 port_cfg_reg
= I40E_PRTGEN_CNF
+ (4 * i
);
2789 /* use AQ read to get the physical register offset instead
2790 * of the port relative offset
2792 i40e_aq_debug_read_register(hw
, port_cfg_reg
, &port_cfg
, NULL
);
2793 if (!(port_cfg
& I40E_PRTGEN_CNF_PORT_DIS_MASK
))
2797 valid_functions
= p
->valid_functions
;
2799 while (valid_functions
) {
2800 if (valid_functions
& 1)
2802 valid_functions
>>= 1;
2805 /* partition id is 1-based, and functions are evenly spread
2806 * across the ports as partitions
2808 hw
->partition_id
= (hw
->pf_id
/ hw
->num_ports
) + 1;
2809 hw
->num_partitions
= num_functions
/ hw
->num_ports
;
2811 /* additional HW specific goodies that might
2812 * someday be HW version specific
2814 p
->rx_buf_chain_len
= I40E_MAX_CHAINED_RX_BUFFERS
;
2818 * i40e_aq_discover_capabilities
2819 * @hw: pointer to the hw struct
2820 * @buff: a virtual buffer to hold the capabilities
2821 * @buff_size: Size of the virtual buffer
2822 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2823 * @list_type_opc: capabilities type to discover - pass in the command opcode
2824 * @cmd_details: pointer to command details structure or NULL
2826 * Get the device capabilities descriptions from the firmware
2828 i40e_status
i40e_aq_discover_capabilities(struct i40e_hw
*hw
,
2829 void *buff
, u16 buff_size
, u16
*data_size
,
2830 enum i40e_admin_queue_opc list_type_opc
,
2831 struct i40e_asq_cmd_details
*cmd_details
)
2833 struct i40e_aqc_list_capabilites
*cmd
;
2834 struct i40e_aq_desc desc
;
2835 i40e_status status
= 0;
2837 cmd
= (struct i40e_aqc_list_capabilites
*)&desc
.params
.raw
;
2839 if (list_type_opc
!= i40e_aqc_opc_list_func_capabilities
&&
2840 list_type_opc
!= i40e_aqc_opc_list_dev_capabilities
) {
2841 status
= I40E_ERR_PARAM
;
2845 i40e_fill_default_direct_cmd_desc(&desc
, list_type_opc
);
2847 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2848 if (buff_size
> I40E_AQ_LARGE_BUF
)
2849 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2851 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
2852 *data_size
= le16_to_cpu(desc
.datalen
);
2857 i40e_parse_discover_capabilities(hw
, buff
, le32_to_cpu(cmd
->count
),
2865 * i40e_aq_update_nvm
2866 * @hw: pointer to the hw struct
2867 * @module_pointer: module pointer location in words from the NVM beginning
2868 * @offset: byte offset from the module beginning
2869 * @length: length of the section to be written (in bytes from the offset)
2870 * @data: command buffer (size [bytes] = length)
2871 * @last_command: tells if this is the last command in a series
2872 * @cmd_details: pointer to command details structure or NULL
2874 * Update the NVM using the admin queue commands
2876 i40e_status
i40e_aq_update_nvm(struct i40e_hw
*hw
, u8 module_pointer
,
2877 u32 offset
, u16 length
, void *data
,
2879 struct i40e_asq_cmd_details
*cmd_details
)
2881 struct i40e_aq_desc desc
;
2882 struct i40e_aqc_nvm_update
*cmd
=
2883 (struct i40e_aqc_nvm_update
*)&desc
.params
.raw
;
2886 /* In offset the highest byte must be zeroed. */
2887 if (offset
& 0xFF000000) {
2888 status
= I40E_ERR_PARAM
;
2889 goto i40e_aq_update_nvm_exit
;
2892 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_nvm_update
);
2894 /* If this is the last command in a series, set the proper flag. */
2896 cmd
->command_flags
|= I40E_AQ_NVM_LAST_CMD
;
2897 cmd
->module_pointer
= module_pointer
;
2898 cmd
->offset
= cpu_to_le32(offset
);
2899 cmd
->length
= cpu_to_le16(length
);
2901 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
2902 if (length
> I40E_AQ_LARGE_BUF
)
2903 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2905 status
= i40e_asq_send_command(hw
, &desc
, data
, length
, cmd_details
);
2907 i40e_aq_update_nvm_exit
:
2912 * i40e_aq_get_lldp_mib
2913 * @hw: pointer to the hw struct
2914 * @bridge_type: type of bridge requested
2915 * @mib_type: Local, Remote or both Local and Remote MIBs
2916 * @buff: pointer to a user supplied buffer to store the MIB block
2917 * @buff_size: size of the buffer (in bytes)
2918 * @local_len : length of the returned Local LLDP MIB
2919 * @remote_len: length of the returned Remote LLDP MIB
2920 * @cmd_details: pointer to command details structure or NULL
2922 * Requests the complete LLDP MIB (entire packet).
2924 i40e_status
i40e_aq_get_lldp_mib(struct i40e_hw
*hw
, u8 bridge_type
,
2925 u8 mib_type
, void *buff
, u16 buff_size
,
2926 u16
*local_len
, u16
*remote_len
,
2927 struct i40e_asq_cmd_details
*cmd_details
)
2929 struct i40e_aq_desc desc
;
2930 struct i40e_aqc_lldp_get_mib
*cmd
=
2931 (struct i40e_aqc_lldp_get_mib
*)&desc
.params
.raw
;
2932 struct i40e_aqc_lldp_get_mib
*resp
=
2933 (struct i40e_aqc_lldp_get_mib
*)&desc
.params
.raw
;
2936 if (buff_size
== 0 || !buff
)
2937 return I40E_ERR_PARAM
;
2939 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_get_mib
);
2940 /* Indirect Command */
2941 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2943 cmd
->type
= mib_type
& I40E_AQ_LLDP_MIB_TYPE_MASK
;
2944 cmd
->type
|= ((bridge_type
<< I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT
) &
2945 I40E_AQ_LLDP_BRIDGE_TYPE_MASK
);
2947 desc
.datalen
= cpu_to_le16(buff_size
);
2949 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2950 if (buff_size
> I40E_AQ_LARGE_BUF
)
2951 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2953 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
2955 if (local_len
!= NULL
)
2956 *local_len
= le16_to_cpu(resp
->local_len
);
2957 if (remote_len
!= NULL
)
2958 *remote_len
= le16_to_cpu(resp
->remote_len
);
2965 * i40e_aq_cfg_lldp_mib_change_event
2966 * @hw: pointer to the hw struct
2967 * @enable_update: Enable or Disable event posting
2968 * @cmd_details: pointer to command details structure or NULL
2970 * Enable or Disable posting of an event on ARQ when LLDP MIB
2971 * associated with the interface changes
2973 i40e_status
i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw
*hw
,
2975 struct i40e_asq_cmd_details
*cmd_details
)
2977 struct i40e_aq_desc desc
;
2978 struct i40e_aqc_lldp_update_mib
*cmd
=
2979 (struct i40e_aqc_lldp_update_mib
*)&desc
.params
.raw
;
2982 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_update_mib
);
2985 cmd
->command
|= I40E_AQ_LLDP_MIB_UPDATE_DISABLE
;
2987 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2994 * @hw: pointer to the hw struct
2995 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2996 * @cmd_details: pointer to command details structure or NULL
2998 * Stop or Shutdown the embedded LLDP Agent
3000 i40e_status
i40e_aq_stop_lldp(struct i40e_hw
*hw
, bool shutdown_agent
,
3001 struct i40e_asq_cmd_details
*cmd_details
)
3003 struct i40e_aq_desc desc
;
3004 struct i40e_aqc_lldp_stop
*cmd
=
3005 (struct i40e_aqc_lldp_stop
*)&desc
.params
.raw
;
3008 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_stop
);
3011 cmd
->command
|= I40E_AQ_LLDP_AGENT_SHUTDOWN
;
3013 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3019 * i40e_aq_start_lldp
3020 * @hw: pointer to the hw struct
3021 * @cmd_details: pointer to command details structure or NULL
3023 * Start the embedded LLDP Agent on all ports.
3025 i40e_status
i40e_aq_start_lldp(struct i40e_hw
*hw
,
3026 struct i40e_asq_cmd_details
*cmd_details
)
3028 struct i40e_aq_desc desc
;
3029 struct i40e_aqc_lldp_start
*cmd
=
3030 (struct i40e_aqc_lldp_start
*)&desc
.params
.raw
;
3033 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_start
);
3035 cmd
->command
= I40E_AQ_LLDP_AGENT_START
;
3037 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3043 * i40e_aq_get_cee_dcb_config
3044 * @hw: pointer to the hw struct
3045 * @buff: response buffer that stores CEE operational configuration
3046 * @buff_size: size of the buffer passed
3047 * @cmd_details: pointer to command details structure or NULL
3049 * Get CEE DCBX mode operational configuration from firmware
3051 i40e_status
i40e_aq_get_cee_dcb_config(struct i40e_hw
*hw
,
3052 void *buff
, u16 buff_size
,
3053 struct i40e_asq_cmd_details
*cmd_details
)
3055 struct i40e_aq_desc desc
;
3058 if (buff_size
== 0 || !buff
)
3059 return I40E_ERR_PARAM
;
3061 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_get_cee_dcb_cfg
);
3063 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
3064 status
= i40e_asq_send_command(hw
, &desc
, (void *)buff
, buff_size
,
3071 * i40e_aq_add_udp_tunnel
3072 * @hw: pointer to the hw struct
3073 * @udp_port: the UDP port to add
3074 * @header_len: length of the tunneling header length in DWords
3075 * @protocol_index: protocol index type
3076 * @filter_index: pointer to filter index
3077 * @cmd_details: pointer to command details structure or NULL
3079 i40e_status
i40e_aq_add_udp_tunnel(struct i40e_hw
*hw
,
3080 u16 udp_port
, u8 protocol_index
,
3082 struct i40e_asq_cmd_details
*cmd_details
)
3084 struct i40e_aq_desc desc
;
3085 struct i40e_aqc_add_udp_tunnel
*cmd
=
3086 (struct i40e_aqc_add_udp_tunnel
*)&desc
.params
.raw
;
3087 struct i40e_aqc_del_udp_tunnel_completion
*resp
=
3088 (struct i40e_aqc_del_udp_tunnel_completion
*)&desc
.params
.raw
;
3091 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_add_udp_tunnel
);
3093 cmd
->udp_port
= cpu_to_le16(udp_port
);
3094 cmd
->protocol_type
= protocol_index
;
3096 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3098 if (!status
&& filter_index
)
3099 *filter_index
= resp
->index
;
3105 * i40e_aq_del_udp_tunnel
3106 * @hw: pointer to the hw struct
3107 * @index: filter index
3108 * @cmd_details: pointer to command details structure or NULL
3110 i40e_status
i40e_aq_del_udp_tunnel(struct i40e_hw
*hw
, u8 index
,
3111 struct i40e_asq_cmd_details
*cmd_details
)
3113 struct i40e_aq_desc desc
;
3114 struct i40e_aqc_remove_udp_tunnel
*cmd
=
3115 (struct i40e_aqc_remove_udp_tunnel
*)&desc
.params
.raw
;
3118 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_del_udp_tunnel
);
3122 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3128 * i40e_aq_delete_element - Delete switch element
3129 * @hw: pointer to the hw struct
3130 * @seid: the SEID to delete from the switch
3131 * @cmd_details: pointer to command details structure or NULL
3133 * This deletes a switch element from the switch.
3135 i40e_status
i40e_aq_delete_element(struct i40e_hw
*hw
, u16 seid
,
3136 struct i40e_asq_cmd_details
*cmd_details
)
3138 struct i40e_aq_desc desc
;
3139 struct i40e_aqc_switch_seid
*cmd
=
3140 (struct i40e_aqc_switch_seid
*)&desc
.params
.raw
;
3144 return I40E_ERR_PARAM
;
3146 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_delete_element
);
3148 cmd
->seid
= cpu_to_le16(seid
);
3150 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3156 * i40e_aq_dcb_updated - DCB Updated Command
3157 * @hw: pointer to the hw struct
3158 * @cmd_details: pointer to command details structure or NULL
3160 * EMP will return when the shared RPB settings have been
3161 * recomputed and modified. The retval field in the descriptor
3162 * will be set to 0 when RPB is modified.
3164 i40e_status
i40e_aq_dcb_updated(struct i40e_hw
*hw
,
3165 struct i40e_asq_cmd_details
*cmd_details
)
3167 struct i40e_aq_desc desc
;
3170 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_dcb_updated
);
3172 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3178 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3179 * @hw: pointer to the hw struct
3180 * @seid: seid for the physical port/switching component/vsi
3181 * @buff: Indirect buffer to hold data parameters and response
3182 * @buff_size: Indirect buffer size
3183 * @opcode: Tx scheduler AQ command opcode
3184 * @cmd_details: pointer to command details structure or NULL
3186 * Generic command handler for Tx scheduler AQ commands
3188 static i40e_status
i40e_aq_tx_sched_cmd(struct i40e_hw
*hw
, u16 seid
,
3189 void *buff
, u16 buff_size
,
3190 enum i40e_admin_queue_opc opcode
,
3191 struct i40e_asq_cmd_details
*cmd_details
)
3193 struct i40e_aq_desc desc
;
3194 struct i40e_aqc_tx_sched_ind
*cmd
=
3195 (struct i40e_aqc_tx_sched_ind
*)&desc
.params
.raw
;
3197 bool cmd_param_flag
= false;
3200 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit
:
3201 case i40e_aqc_opc_configure_vsi_tc_bw
:
3202 case i40e_aqc_opc_enable_switching_comp_ets
:
3203 case i40e_aqc_opc_modify_switching_comp_ets
:
3204 case i40e_aqc_opc_disable_switching_comp_ets
:
3205 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit
:
3206 case i40e_aqc_opc_configure_switching_comp_bw_config
:
3207 cmd_param_flag
= true;
3209 case i40e_aqc_opc_query_vsi_bw_config
:
3210 case i40e_aqc_opc_query_vsi_ets_sla_config
:
3211 case i40e_aqc_opc_query_switching_comp_ets_config
:
3212 case i40e_aqc_opc_query_port_ets_config
:
3213 case i40e_aqc_opc_query_switching_comp_bw_config
:
3214 cmd_param_flag
= false;
3217 return I40E_ERR_PARAM
;
3220 i40e_fill_default_direct_cmd_desc(&desc
, opcode
);
3222 /* Indirect command */
3223 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
3225 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_RD
);
3226 if (buff_size
> I40E_AQ_LARGE_BUF
)
3227 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
3229 desc
.datalen
= cpu_to_le16(buff_size
);
3231 cmd
->vsi_seid
= cpu_to_le16(seid
);
3233 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
3239 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3240 * @hw: pointer to the hw struct
3242 * @credit: BW limit credits (0 = disabled)
3243 * @max_credit: Max BW limit credits
3244 * @cmd_details: pointer to command details structure or NULL
3246 i40e_status
i40e_aq_config_vsi_bw_limit(struct i40e_hw
*hw
,
3247 u16 seid
, u16 credit
, u8 max_credit
,
3248 struct i40e_asq_cmd_details
*cmd_details
)
3250 struct i40e_aq_desc desc
;
3251 struct i40e_aqc_configure_vsi_bw_limit
*cmd
=
3252 (struct i40e_aqc_configure_vsi_bw_limit
*)&desc
.params
.raw
;
3255 i40e_fill_default_direct_cmd_desc(&desc
,
3256 i40e_aqc_opc_configure_vsi_bw_limit
);
3258 cmd
->vsi_seid
= cpu_to_le16(seid
);
3259 cmd
->credit
= cpu_to_le16(credit
);
3260 cmd
->max_credit
= max_credit
;
3262 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3268 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3269 * @hw: pointer to the hw struct
3271 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3272 * @cmd_details: pointer to command details structure or NULL
3274 i40e_status
i40e_aq_config_vsi_tc_bw(struct i40e_hw
*hw
,
3276 struct i40e_aqc_configure_vsi_tc_bw_data
*bw_data
,
3277 struct i40e_asq_cmd_details
*cmd_details
)
3279 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3280 i40e_aqc_opc_configure_vsi_tc_bw
,
3285 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3286 * @hw: pointer to the hw struct
3287 * @seid: seid of the switching component connected to Physical Port
3288 * @ets_data: Buffer holding ETS parameters
3289 * @cmd_details: pointer to command details structure or NULL
3291 i40e_status
i40e_aq_config_switch_comp_ets(struct i40e_hw
*hw
,
3293 struct i40e_aqc_configure_switching_comp_ets_data
*ets_data
,
3294 enum i40e_admin_queue_opc opcode
,
3295 struct i40e_asq_cmd_details
*cmd_details
)
3297 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)ets_data
,
3298 sizeof(*ets_data
), opcode
, cmd_details
);
3302 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3303 * @hw: pointer to the hw struct
3304 * @seid: seid of the switching component
3305 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3306 * @cmd_details: pointer to command details structure or NULL
3308 i40e_status
i40e_aq_config_switch_comp_bw_config(struct i40e_hw
*hw
,
3310 struct i40e_aqc_configure_switching_comp_bw_config_data
*bw_data
,
3311 struct i40e_asq_cmd_details
*cmd_details
)
3313 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3314 i40e_aqc_opc_configure_switching_comp_bw_config
,
3319 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3320 * @hw: pointer to the hw struct
3321 * @seid: seid of the VSI
3322 * @bw_data: Buffer to hold VSI BW configuration
3323 * @cmd_details: pointer to command details structure or NULL
3325 i40e_status
i40e_aq_query_vsi_bw_config(struct i40e_hw
*hw
,
3327 struct i40e_aqc_query_vsi_bw_config_resp
*bw_data
,
3328 struct i40e_asq_cmd_details
*cmd_details
)
3330 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3331 i40e_aqc_opc_query_vsi_bw_config
,
3336 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3337 * @hw: pointer to the hw struct
3338 * @seid: seid of the VSI
3339 * @bw_data: Buffer to hold VSI BW configuration per TC
3340 * @cmd_details: pointer to command details structure or NULL
3342 i40e_status
i40e_aq_query_vsi_ets_sla_config(struct i40e_hw
*hw
,
3344 struct i40e_aqc_query_vsi_ets_sla_config_resp
*bw_data
,
3345 struct i40e_asq_cmd_details
*cmd_details
)
3347 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3348 i40e_aqc_opc_query_vsi_ets_sla_config
,
3353 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3354 * @hw: pointer to the hw struct
3355 * @seid: seid of the switching component
3356 * @bw_data: Buffer to hold switching component's per TC BW config
3357 * @cmd_details: pointer to command details structure or NULL
3359 i40e_status
i40e_aq_query_switch_comp_ets_config(struct i40e_hw
*hw
,
3361 struct i40e_aqc_query_switching_comp_ets_config_resp
*bw_data
,
3362 struct i40e_asq_cmd_details
*cmd_details
)
3364 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3365 i40e_aqc_opc_query_switching_comp_ets_config
,
3370 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3371 * @hw: pointer to the hw struct
3372 * @seid: seid of the VSI or switching component connected to Physical Port
3373 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3374 * @cmd_details: pointer to command details structure or NULL
3376 i40e_status
i40e_aq_query_port_ets_config(struct i40e_hw
*hw
,
3378 struct i40e_aqc_query_port_ets_config_resp
*bw_data
,
3379 struct i40e_asq_cmd_details
*cmd_details
)
3381 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3382 i40e_aqc_opc_query_port_ets_config
,
3387 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3388 * @hw: pointer to the hw struct
3389 * @seid: seid of the switching component
3390 * @bw_data: Buffer to hold switching component's BW configuration
3391 * @cmd_details: pointer to command details structure or NULL
3393 i40e_status
i40e_aq_query_switch_comp_bw_config(struct i40e_hw
*hw
,
3395 struct i40e_aqc_query_switching_comp_bw_config_resp
*bw_data
,
3396 struct i40e_asq_cmd_details
*cmd_details
)
3398 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3399 i40e_aqc_opc_query_switching_comp_bw_config
,
3404 * i40e_validate_filter_settings
3405 * @hw: pointer to the hardware structure
3406 * @settings: Filter control settings
3408 * Check and validate the filter control settings passed.
3409 * The function checks for the valid filter/context sizes being
3410 * passed for FCoE and PE.
3412 * Returns 0 if the values passed are valid and within
3413 * range else returns an error.
3415 static i40e_status
i40e_validate_filter_settings(struct i40e_hw
*hw
,
3416 struct i40e_filter_control_settings
*settings
)
3418 u32 fcoe_cntx_size
, fcoe_filt_size
;
3419 u32 pe_cntx_size
, pe_filt_size
;
3423 /* Validate FCoE settings passed */
3424 switch (settings
->fcoe_filt_num
) {
3425 case I40E_HASH_FILTER_SIZE_1K
:
3426 case I40E_HASH_FILTER_SIZE_2K
:
3427 case I40E_HASH_FILTER_SIZE_4K
:
3428 case I40E_HASH_FILTER_SIZE_8K
:
3429 case I40E_HASH_FILTER_SIZE_16K
:
3430 case I40E_HASH_FILTER_SIZE_32K
:
3431 fcoe_filt_size
= I40E_HASH_FILTER_BASE_SIZE
;
3432 fcoe_filt_size
<<= (u32
)settings
->fcoe_filt_num
;
3435 return I40E_ERR_PARAM
;
3438 switch (settings
->fcoe_cntx_num
) {
3439 case I40E_DMA_CNTX_SIZE_512
:
3440 case I40E_DMA_CNTX_SIZE_1K
:
3441 case I40E_DMA_CNTX_SIZE_2K
:
3442 case I40E_DMA_CNTX_SIZE_4K
:
3443 fcoe_cntx_size
= I40E_DMA_CNTX_BASE_SIZE
;
3444 fcoe_cntx_size
<<= (u32
)settings
->fcoe_cntx_num
;
3447 return I40E_ERR_PARAM
;
3450 /* Validate PE settings passed */
3451 switch (settings
->pe_filt_num
) {
3452 case I40E_HASH_FILTER_SIZE_1K
:
3453 case I40E_HASH_FILTER_SIZE_2K
:
3454 case I40E_HASH_FILTER_SIZE_4K
:
3455 case I40E_HASH_FILTER_SIZE_8K
:
3456 case I40E_HASH_FILTER_SIZE_16K
:
3457 case I40E_HASH_FILTER_SIZE_32K
:
3458 case I40E_HASH_FILTER_SIZE_64K
:
3459 case I40E_HASH_FILTER_SIZE_128K
:
3460 case I40E_HASH_FILTER_SIZE_256K
:
3461 case I40E_HASH_FILTER_SIZE_512K
:
3462 case I40E_HASH_FILTER_SIZE_1M
:
3463 pe_filt_size
= I40E_HASH_FILTER_BASE_SIZE
;
3464 pe_filt_size
<<= (u32
)settings
->pe_filt_num
;
3467 return I40E_ERR_PARAM
;
3470 switch (settings
->pe_cntx_num
) {
3471 case I40E_DMA_CNTX_SIZE_512
:
3472 case I40E_DMA_CNTX_SIZE_1K
:
3473 case I40E_DMA_CNTX_SIZE_2K
:
3474 case I40E_DMA_CNTX_SIZE_4K
:
3475 case I40E_DMA_CNTX_SIZE_8K
:
3476 case I40E_DMA_CNTX_SIZE_16K
:
3477 case I40E_DMA_CNTX_SIZE_32K
:
3478 case I40E_DMA_CNTX_SIZE_64K
:
3479 case I40E_DMA_CNTX_SIZE_128K
:
3480 case I40E_DMA_CNTX_SIZE_256K
:
3481 pe_cntx_size
= I40E_DMA_CNTX_BASE_SIZE
;
3482 pe_cntx_size
<<= (u32
)settings
->pe_cntx_num
;
3485 return I40E_ERR_PARAM
;
3488 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3489 val
= rd32(hw
, I40E_GLHMC_FCOEFMAX
);
3490 fcoe_fmax
= (val
& I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK
)
3491 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT
;
3492 if (fcoe_filt_size
+ fcoe_cntx_size
> fcoe_fmax
)
3493 return I40E_ERR_INVALID_SIZE
;
3499 * i40e_set_filter_control
3500 * @hw: pointer to the hardware structure
3501 * @settings: Filter control settings
3503 * Set the Queue Filters for PE/FCoE and enable filters required
3504 * for a single PF. It is expected that these settings are programmed
3505 * at the driver initialization time.
3507 i40e_status
i40e_set_filter_control(struct i40e_hw
*hw
,
3508 struct i40e_filter_control_settings
*settings
)
3510 i40e_status ret
= 0;
3511 u32 hash_lut_size
= 0;
3515 return I40E_ERR_PARAM
;
3517 /* Validate the input settings */
3518 ret
= i40e_validate_filter_settings(hw
, settings
);
3522 /* Read the PF Queue Filter control register */
3523 val
= rd32(hw
, I40E_PFQF_CTL_0
);
3525 /* Program required PE hash buckets for the PF */
3526 val
&= ~I40E_PFQF_CTL_0_PEHSIZE_MASK
;
3527 val
|= ((u32
)settings
->pe_filt_num
<< I40E_PFQF_CTL_0_PEHSIZE_SHIFT
) &
3528 I40E_PFQF_CTL_0_PEHSIZE_MASK
;
3529 /* Program required PE contexts for the PF */
3530 val
&= ~I40E_PFQF_CTL_0_PEDSIZE_MASK
;
3531 val
|= ((u32
)settings
->pe_cntx_num
<< I40E_PFQF_CTL_0_PEDSIZE_SHIFT
) &
3532 I40E_PFQF_CTL_0_PEDSIZE_MASK
;
3534 /* Program required FCoE hash buckets for the PF */
3535 val
&= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK
;
3536 val
|= ((u32
)settings
->fcoe_filt_num
<<
3537 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT
) &
3538 I40E_PFQF_CTL_0_PFFCHSIZE_MASK
;
3539 /* Program required FCoE DDP contexts for the PF */
3540 val
&= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK
;
3541 val
|= ((u32
)settings
->fcoe_cntx_num
<<
3542 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT
) &
3543 I40E_PFQF_CTL_0_PFFCDSIZE_MASK
;
3545 /* Program Hash LUT size for the PF */
3546 val
&= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK
;
3547 if (settings
->hash_lut_size
== I40E_HASH_LUT_SIZE_512
)
3549 val
|= (hash_lut_size
<< I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT
) &
3550 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK
;
3552 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3553 if (settings
->enable_fdir
)
3554 val
|= I40E_PFQF_CTL_0_FD_ENA_MASK
;
3555 if (settings
->enable_ethtype
)
3556 val
|= I40E_PFQF_CTL_0_ETYPE_ENA_MASK
;
3557 if (settings
->enable_macvlan
)
3558 val
|= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK
;
3560 wr32(hw
, I40E_PFQF_CTL_0
, val
);
3566 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3567 * @hw: pointer to the hw struct
3568 * @mac_addr: MAC address to use in the filter
3569 * @ethtype: Ethertype to use in the filter
3570 * @flags: Flags that needs to be applied to the filter
3571 * @vsi_seid: seid of the control VSI
3572 * @queue: VSI queue number to send the packet to
3573 * @is_add: Add control packet filter if True else remove
3574 * @stats: Structure to hold information on control filter counts
3575 * @cmd_details: pointer to command details structure or NULL
3577 * This command will Add or Remove control packet filter for a control VSI.
3578 * In return it will update the total number of perfect filter count in
3581 i40e_status
i40e_aq_add_rem_control_packet_filter(struct i40e_hw
*hw
,
3582 u8
*mac_addr
, u16 ethtype
, u16 flags
,
3583 u16 vsi_seid
, u16 queue
, bool is_add
,
3584 struct i40e_control_filter_stats
*stats
,
3585 struct i40e_asq_cmd_details
*cmd_details
)
3587 struct i40e_aq_desc desc
;
3588 struct i40e_aqc_add_remove_control_packet_filter
*cmd
=
3589 (struct i40e_aqc_add_remove_control_packet_filter
*)
3591 struct i40e_aqc_add_remove_control_packet_filter_completion
*resp
=
3592 (struct i40e_aqc_add_remove_control_packet_filter_completion
*)
3597 return I40E_ERR_PARAM
;
3600 i40e_fill_default_direct_cmd_desc(&desc
,
3601 i40e_aqc_opc_add_control_packet_filter
);
3602 cmd
->queue
= cpu_to_le16(queue
);
3604 i40e_fill_default_direct_cmd_desc(&desc
,
3605 i40e_aqc_opc_remove_control_packet_filter
);
3609 memcpy(cmd
->mac
, mac_addr
, ETH_ALEN
);
3611 cmd
->etype
= cpu_to_le16(ethtype
);
3612 cmd
->flags
= cpu_to_le16(flags
);
3613 cmd
->seid
= cpu_to_le16(vsi_seid
);
3615 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3617 if (!status
&& stats
) {
3618 stats
->mac_etype_used
= le16_to_cpu(resp
->mac_etype_used
);
3619 stats
->etype_used
= le16_to_cpu(resp
->etype_used
);
3620 stats
->mac_etype_free
= le16_to_cpu(resp
->mac_etype_free
);
3621 stats
->etype_free
= le16_to_cpu(resp
->etype_free
);
3628 * i40e_aq_alternate_read
3629 * @hw: pointer to the hardware structure
3630 * @reg_addr0: address of first dword to be read
3631 * @reg_val0: pointer for data read from 'reg_addr0'
3632 * @reg_addr1: address of second dword to be read
3633 * @reg_val1: pointer for data read from 'reg_addr1'
3635 * Read one or two dwords from alternate structure. Fields are indicated
3636 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
3637 * is not passed then only register at 'reg_addr0' is read.
3640 static i40e_status
i40e_aq_alternate_read(struct i40e_hw
*hw
,
3641 u32 reg_addr0
, u32
*reg_val0
,
3642 u32 reg_addr1
, u32
*reg_val1
)
3644 struct i40e_aq_desc desc
;
3645 struct i40e_aqc_alternate_write
*cmd_resp
=
3646 (struct i40e_aqc_alternate_write
*)&desc
.params
.raw
;
3650 return I40E_ERR_PARAM
;
3652 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_alternate_read
);
3653 cmd_resp
->address0
= cpu_to_le32(reg_addr0
);
3654 cmd_resp
->address1
= cpu_to_le32(reg_addr1
);
3656 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, NULL
);
3659 *reg_val0
= le32_to_cpu(cmd_resp
->data0
);
3662 *reg_val1
= le32_to_cpu(cmd_resp
->data1
);
3669 * i40e_aq_resume_port_tx
3670 * @hw: pointer to the hardware structure
3671 * @cmd_details: pointer to command details structure or NULL
3673 * Resume port's Tx traffic
3675 i40e_status
i40e_aq_resume_port_tx(struct i40e_hw
*hw
,
3676 struct i40e_asq_cmd_details
*cmd_details
)
3678 struct i40e_aq_desc desc
;
3681 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_resume_port_tx
);
3683 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3689 * i40e_set_pci_config_data - store PCI bus info
3690 * @hw: pointer to hardware structure
3691 * @link_status: the link status word from PCI config space
3693 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3695 void i40e_set_pci_config_data(struct i40e_hw
*hw
, u16 link_status
)
3697 hw
->bus
.type
= i40e_bus_type_pci_express
;
3699 switch (link_status
& PCI_EXP_LNKSTA_NLW
) {
3700 case PCI_EXP_LNKSTA_NLW_X1
:
3701 hw
->bus
.width
= i40e_bus_width_pcie_x1
;
3703 case PCI_EXP_LNKSTA_NLW_X2
:
3704 hw
->bus
.width
= i40e_bus_width_pcie_x2
;
3706 case PCI_EXP_LNKSTA_NLW_X4
:
3707 hw
->bus
.width
= i40e_bus_width_pcie_x4
;
3709 case PCI_EXP_LNKSTA_NLW_X8
:
3710 hw
->bus
.width
= i40e_bus_width_pcie_x8
;
3713 hw
->bus
.width
= i40e_bus_width_unknown
;
3717 switch (link_status
& PCI_EXP_LNKSTA_CLS
) {
3718 case PCI_EXP_LNKSTA_CLS_2_5GB
:
3719 hw
->bus
.speed
= i40e_bus_speed_2500
;
3721 case PCI_EXP_LNKSTA_CLS_5_0GB
:
3722 hw
->bus
.speed
= i40e_bus_speed_5000
;
3724 case PCI_EXP_LNKSTA_CLS_8_0GB
:
3725 hw
->bus
.speed
= i40e_bus_speed_8000
;
3728 hw
->bus
.speed
= i40e_bus_speed_unknown
;
3734 * i40e_aq_debug_dump
3735 * @hw: pointer to the hardware structure
3736 * @cluster_id: specific cluster to dump
3737 * @table_id: table id within cluster
3738 * @start_index: index of line in the block to read
3739 * @buff_size: dump buffer size
3740 * @buff: dump buffer
3741 * @ret_buff_size: actual buffer size returned
3742 * @ret_next_table: next block to read
3743 * @ret_next_index: next index to read
3745 * Dump internal FW/HW data for debug purposes.
3748 i40e_status
i40e_aq_debug_dump(struct i40e_hw
*hw
, u8 cluster_id
,
3749 u8 table_id
, u32 start_index
, u16 buff_size
,
3750 void *buff
, u16
*ret_buff_size
,
3751 u8
*ret_next_table
, u32
*ret_next_index
,
3752 struct i40e_asq_cmd_details
*cmd_details
)
3754 struct i40e_aq_desc desc
;
3755 struct i40e_aqc_debug_dump_internals
*cmd
=
3756 (struct i40e_aqc_debug_dump_internals
*)&desc
.params
.raw
;
3757 struct i40e_aqc_debug_dump_internals
*resp
=
3758 (struct i40e_aqc_debug_dump_internals
*)&desc
.params
.raw
;
3761 if (buff_size
== 0 || !buff
)
3762 return I40E_ERR_PARAM
;
3764 i40e_fill_default_direct_cmd_desc(&desc
,
3765 i40e_aqc_opc_debug_dump_internals
);
3766 /* Indirect Command */
3767 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
3768 if (buff_size
> I40E_AQ_LARGE_BUF
)
3769 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
3771 cmd
->cluster_id
= cluster_id
;
3772 cmd
->table_id
= table_id
;
3773 cmd
->idx
= cpu_to_le32(start_index
);
3775 desc
.datalen
= cpu_to_le16(buff_size
);
3777 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
3780 *ret_buff_size
= le16_to_cpu(desc
.datalen
);
3782 *ret_next_table
= resp
->table_id
;
3784 *ret_next_index
= le32_to_cpu(resp
->idx
);
3791 * i40e_read_bw_from_alt_ram
3792 * @hw: pointer to the hardware structure
3793 * @max_bw: pointer for max_bw read
3794 * @min_bw: pointer for min_bw read
3795 * @min_valid: pointer for bool that is true if min_bw is a valid value
3796 * @max_valid: pointer for bool that is true if max_bw is a valid value
3798 * Read bw from the alternate ram for the given pf
3800 i40e_status
i40e_read_bw_from_alt_ram(struct i40e_hw
*hw
,
3801 u32
*max_bw
, u32
*min_bw
,
3802 bool *min_valid
, bool *max_valid
)
3805 u32 max_bw_addr
, min_bw_addr
;
3807 /* Calculate the address of the min/max bw registers */
3808 max_bw_addr
= I40E_ALT_STRUCT_FIRST_PF_OFFSET
+
3809 I40E_ALT_STRUCT_MAX_BW_OFFSET
+
3810 (I40E_ALT_STRUCT_DWORDS_PER_PF
* hw
->pf_id
);
3811 min_bw_addr
= I40E_ALT_STRUCT_FIRST_PF_OFFSET
+
3812 I40E_ALT_STRUCT_MIN_BW_OFFSET
+
3813 (I40E_ALT_STRUCT_DWORDS_PER_PF
* hw
->pf_id
);
3815 /* Read the bandwidths from alt ram */
3816 status
= i40e_aq_alternate_read(hw
, max_bw_addr
, max_bw
,
3817 min_bw_addr
, min_bw
);
3819 if (*min_bw
& I40E_ALT_BW_VALID_MASK
)
3824 if (*max_bw
& I40E_ALT_BW_VALID_MASK
)
3833 * i40e_aq_configure_partition_bw
3834 * @hw: pointer to the hardware structure
3835 * @bw_data: Buffer holding valid pfs and bw limits
3836 * @cmd_details: pointer to command details
3838 * Configure partitions guaranteed/max bw
3840 i40e_status
i40e_aq_configure_partition_bw(struct i40e_hw
*hw
,
3841 struct i40e_aqc_configure_partition_bw_data
*bw_data
,
3842 struct i40e_asq_cmd_details
*cmd_details
)
3845 struct i40e_aq_desc desc
;
3846 u16 bwd_size
= sizeof(*bw_data
);
3848 i40e_fill_default_direct_cmd_desc(&desc
,
3849 i40e_aqc_opc_configure_partition_bw
);
3851 /* Indirect command */
3852 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
3853 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_RD
);
3855 if (bwd_size
> I40E_AQ_LARGE_BUF
)
3856 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
3858 desc
.datalen
= cpu_to_le16(bwd_size
);
3860 status
= i40e_asq_send_command(hw
, &desc
, bw_data
, bwd_size
,