1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
39 static i40e_status
i40e_set_mac_type(struct i40e_hw
*hw
)
41 i40e_status status
= 0;
43 if (hw
->vendor_id
== PCI_VENDOR_ID_INTEL
) {
44 switch (hw
->device_id
) {
45 case I40E_DEV_ID_SFP_XL710
:
46 case I40E_DEV_ID_QEMU
:
47 case I40E_DEV_ID_KX_A
:
48 case I40E_DEV_ID_KX_B
:
49 case I40E_DEV_ID_KX_C
:
50 case I40E_DEV_ID_QSFP_A
:
51 case I40E_DEV_ID_QSFP_B
:
52 case I40E_DEV_ID_QSFP_C
:
53 hw
->mac
.type
= I40E_MAC_XL710
;
56 case I40E_DEV_ID_VF_HV
:
57 hw
->mac
.type
= I40E_MAC_VF
;
60 hw
->mac
.type
= I40E_MAC_GENERIC
;
64 status
= I40E_ERR_DEVICE_NOT_SUPPORTED
;
67 hw_dbg(hw
, "i40e_set_mac_type found mac: %d, returns: %d\n",
68 hw
->mac
.type
, status
);
74 * @hw: debug mask related to admin queue
76 * @desc: pointer to admin queue descriptor
77 * @buffer: pointer to command buffer
79 * Dumps debug log about adminq command with descriptor contents.
81 void i40e_debug_aq(struct i40e_hw
*hw
, enum i40e_debug_mask mask
, void *desc
,
84 struct i40e_aq_desc
*aq_desc
= (struct i40e_aq_desc
*)desc
;
85 u8
*aq_buffer
= (u8
*)buffer
;
89 if ((!(mask
& hw
->debug_mask
)) || (desc
== NULL
))
93 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
94 aq_desc
->opcode
, aq_desc
->flags
, aq_desc
->datalen
,
96 i40e_debug(hw
, mask
, "\tcookie (h,l) 0x%08X 0x%08X\n",
97 aq_desc
->cookie_high
, aq_desc
->cookie_low
);
98 i40e_debug(hw
, mask
, "\tparam (0,1) 0x%08X 0x%08X\n",
99 aq_desc
->params
.internal
.param0
,
100 aq_desc
->params
.internal
.param1
);
101 i40e_debug(hw
, mask
, "\taddr (h,l) 0x%08X 0x%08X\n",
102 aq_desc
->params
.external
.addr_high
,
103 aq_desc
->params
.external
.addr_low
);
105 if ((buffer
!= NULL
) && (aq_desc
->datalen
!= 0)) {
106 memset(data
, 0, sizeof(data
));
107 i40e_debug(hw
, mask
, "AQ CMD Buffer:\n");
108 for (i
= 0; i
< le16_to_cpu(aq_desc
->datalen
); i
++) {
109 data
[((i
% 16) / 4)] |=
110 ((u32
)aq_buffer
[i
]) << (8 * (i
% 4));
111 if ((i
% 16) == 15) {
113 "\t0x%04X %08X %08X %08X %08X\n",
114 i
- 15, data
[0], data
[1], data
[2],
116 memset(data
, 0, sizeof(data
));
120 i40e_debug(hw
, mask
, "\t0x%04X %08X %08X %08X %08X\n",
121 i
- (i
% 16), data
[0], data
[1], data
[2],
127 * i40e_check_asq_alive
128 * @hw: pointer to the hw struct
130 * Returns true if Queue is enabled else false.
132 bool i40e_check_asq_alive(struct i40e_hw
*hw
)
135 return !!(rd32(hw
, hw
->aq
.asq
.len
) &
136 I40E_PF_ATQLEN_ATQENABLE_MASK
);
142 * i40e_aq_queue_shutdown
143 * @hw: pointer to the hw struct
144 * @unloading: is the driver unloading itself
146 * Tell the Firmware that we're shutting down the AdminQ and whether
147 * or not the driver is unloading as well.
149 i40e_status
i40e_aq_queue_shutdown(struct i40e_hw
*hw
,
152 struct i40e_aq_desc desc
;
153 struct i40e_aqc_queue_shutdown
*cmd
=
154 (struct i40e_aqc_queue_shutdown
*)&desc
.params
.raw
;
157 i40e_fill_default_direct_cmd_desc(&desc
,
158 i40e_aqc_opc_queue_shutdown
);
161 cmd
->driver_unloading
= cpu_to_le32(I40E_AQ_DRIVER_UNLOADING
);
162 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, NULL
);
167 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
168 * hardware to a bit-field that can be used by SW to more easily determine the
171 * Macros are used to shorten the table lines and make this table human
174 * We store the PTYPE in the top byte of the bit field - this is just so that
175 * we can check that the table doesn't have a row missing, as the index into
176 * the table should be the PTYPE.
180 * IF NOT i40e_ptype_lookup[ptype].known
183 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
184 * Use the rest of the fields to look at the tunnels, inner protocols, etc
186 * Use the enum i40e_rx_l2_ptype to decode the packet type
190 /* macro to make the table lines short */
191 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
194 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
195 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
196 I40E_RX_PTYPE_##OUTER_FRAG, \
197 I40E_RX_PTYPE_TUNNEL_##T, \
198 I40E_RX_PTYPE_TUNNEL_END_##TE, \
199 I40E_RX_PTYPE_##TEF, \
200 I40E_RX_PTYPE_INNER_PROT_##I, \
201 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
203 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
204 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
206 /* shorter macros makes the table fit but are terse */
207 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
208 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
209 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
211 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
212 struct i40e_rx_ptype_decoded i40e_ptype_lookup
[] = {
213 /* L2 Packet types */
214 I40E_PTT_UNUSED_ENTRY(0),
215 I40E_PTT(1, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
216 I40E_PTT(2, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, TS
, PAY2
),
217 I40E_PTT(3, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
218 I40E_PTT_UNUSED_ENTRY(4),
219 I40E_PTT_UNUSED_ENTRY(5),
220 I40E_PTT(6, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
221 I40E_PTT(7, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
222 I40E_PTT_UNUSED_ENTRY(8),
223 I40E_PTT_UNUSED_ENTRY(9),
224 I40E_PTT(10, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
225 I40E_PTT(11, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, NONE
),
226 I40E_PTT(12, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
227 I40E_PTT(13, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
228 I40E_PTT(14, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
229 I40E_PTT(15, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
230 I40E_PTT(16, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
231 I40E_PTT(17, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
232 I40E_PTT(18, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
233 I40E_PTT(19, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
234 I40E_PTT(20, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
235 I40E_PTT(21, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
237 /* Non Tunneled IPv4 */
238 I40E_PTT(22, IP
, IPV4
, FRG
, NONE
, NONE
, NOF
, NONE
, PAY3
),
239 I40E_PTT(23, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
240 I40E_PTT(24, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, UDP
, PAY4
),
241 I40E_PTT_UNUSED_ENTRY(25),
242 I40E_PTT(26, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, TCP
, PAY4
),
243 I40E_PTT(27, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, SCTP
, PAY4
),
244 I40E_PTT(28, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, ICMP
, PAY4
),
247 I40E_PTT(29, IP
, IPV4
, NOF
, IP_IP
, IPV4
, FRG
, NONE
, PAY3
),
248 I40E_PTT(30, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, NONE
, PAY3
),
249 I40E_PTT(31, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, UDP
, PAY4
),
250 I40E_PTT_UNUSED_ENTRY(32),
251 I40E_PTT(33, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, TCP
, PAY4
),
252 I40E_PTT(34, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, SCTP
, PAY4
),
253 I40E_PTT(35, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, ICMP
, PAY4
),
256 I40E_PTT(36, IP
, IPV4
, NOF
, IP_IP
, IPV6
, FRG
, NONE
, PAY3
),
257 I40E_PTT(37, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, NONE
, PAY3
),
258 I40E_PTT(38, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, UDP
, PAY4
),
259 I40E_PTT_UNUSED_ENTRY(39),
260 I40E_PTT(40, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, TCP
, PAY4
),
261 I40E_PTT(41, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, SCTP
, PAY4
),
262 I40E_PTT(42, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, ICMP
, PAY4
),
264 /* IPv4 --> GRE/NAT */
265 I40E_PTT(43, IP
, IPV4
, NOF
, IP_GRENAT
, NONE
, NOF
, NONE
, PAY3
),
267 /* IPv4 --> GRE/NAT --> IPv4 */
268 I40E_PTT(44, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, FRG
, NONE
, PAY3
),
269 I40E_PTT(45, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, NONE
, PAY3
),
270 I40E_PTT(46, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, UDP
, PAY4
),
271 I40E_PTT_UNUSED_ENTRY(47),
272 I40E_PTT(48, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, TCP
, PAY4
),
273 I40E_PTT(49, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, SCTP
, PAY4
),
274 I40E_PTT(50, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, ICMP
, PAY4
),
276 /* IPv4 --> GRE/NAT --> IPv6 */
277 I40E_PTT(51, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, FRG
, NONE
, PAY3
),
278 I40E_PTT(52, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, NONE
, PAY3
),
279 I40E_PTT(53, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, UDP
, PAY4
),
280 I40E_PTT_UNUSED_ENTRY(54),
281 I40E_PTT(55, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, TCP
, PAY4
),
282 I40E_PTT(56, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, SCTP
, PAY4
),
283 I40E_PTT(57, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, ICMP
, PAY4
),
285 /* IPv4 --> GRE/NAT --> MAC */
286 I40E_PTT(58, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, NONE
, NOF
, NONE
, PAY3
),
288 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
289 I40E_PTT(59, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, FRG
, NONE
, PAY3
),
290 I40E_PTT(60, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, NONE
, PAY3
),
291 I40E_PTT(61, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, UDP
, PAY4
),
292 I40E_PTT_UNUSED_ENTRY(62),
293 I40E_PTT(63, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, TCP
, PAY4
),
294 I40E_PTT(64, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, SCTP
, PAY4
),
295 I40E_PTT(65, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, ICMP
, PAY4
),
297 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
298 I40E_PTT(66, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, FRG
, NONE
, PAY3
),
299 I40E_PTT(67, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, NONE
, PAY3
),
300 I40E_PTT(68, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, UDP
, PAY4
),
301 I40E_PTT_UNUSED_ENTRY(69),
302 I40E_PTT(70, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, TCP
, PAY4
),
303 I40E_PTT(71, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, SCTP
, PAY4
),
304 I40E_PTT(72, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, ICMP
, PAY4
),
306 /* IPv4 --> GRE/NAT --> MAC/VLAN */
307 I40E_PTT(73, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, NONE
, NOF
, NONE
, PAY3
),
309 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
310 I40E_PTT(74, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, FRG
, NONE
, PAY3
),
311 I40E_PTT(75, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, NONE
, PAY3
),
312 I40E_PTT(76, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, UDP
, PAY4
),
313 I40E_PTT_UNUSED_ENTRY(77),
314 I40E_PTT(78, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, TCP
, PAY4
),
315 I40E_PTT(79, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, SCTP
, PAY4
),
316 I40E_PTT(80, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, ICMP
, PAY4
),
318 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
319 I40E_PTT(81, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, FRG
, NONE
, PAY3
),
320 I40E_PTT(82, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, NONE
, PAY3
),
321 I40E_PTT(83, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, UDP
, PAY4
),
322 I40E_PTT_UNUSED_ENTRY(84),
323 I40E_PTT(85, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, TCP
, PAY4
),
324 I40E_PTT(86, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, SCTP
, PAY4
),
325 I40E_PTT(87, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, ICMP
, PAY4
),
327 /* Non Tunneled IPv6 */
328 I40E_PTT(88, IP
, IPV6
, FRG
, NONE
, NONE
, NOF
, NONE
, PAY3
),
329 I40E_PTT(89, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
330 I40E_PTT(90, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, UDP
, PAY3
),
331 I40E_PTT_UNUSED_ENTRY(91),
332 I40E_PTT(92, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, TCP
, PAY4
),
333 I40E_PTT(93, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, SCTP
, PAY4
),
334 I40E_PTT(94, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, ICMP
, PAY4
),
337 I40E_PTT(95, IP
, IPV6
, NOF
, IP_IP
, IPV4
, FRG
, NONE
, PAY3
),
338 I40E_PTT(96, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, NONE
, PAY3
),
339 I40E_PTT(97, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, UDP
, PAY4
),
340 I40E_PTT_UNUSED_ENTRY(98),
341 I40E_PTT(99, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, TCP
, PAY4
),
342 I40E_PTT(100, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, SCTP
, PAY4
),
343 I40E_PTT(101, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, ICMP
, PAY4
),
346 I40E_PTT(102, IP
, IPV6
, NOF
, IP_IP
, IPV6
, FRG
, NONE
, PAY3
),
347 I40E_PTT(103, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, NONE
, PAY3
),
348 I40E_PTT(104, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, UDP
, PAY4
),
349 I40E_PTT_UNUSED_ENTRY(105),
350 I40E_PTT(106, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, TCP
, PAY4
),
351 I40E_PTT(107, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, SCTP
, PAY4
),
352 I40E_PTT(108, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, ICMP
, PAY4
),
354 /* IPv6 --> GRE/NAT */
355 I40E_PTT(109, IP
, IPV6
, NOF
, IP_GRENAT
, NONE
, NOF
, NONE
, PAY3
),
357 /* IPv6 --> GRE/NAT -> IPv4 */
358 I40E_PTT(110, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, FRG
, NONE
, PAY3
),
359 I40E_PTT(111, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, NONE
, PAY3
),
360 I40E_PTT(112, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, UDP
, PAY4
),
361 I40E_PTT_UNUSED_ENTRY(113),
362 I40E_PTT(114, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, TCP
, PAY4
),
363 I40E_PTT(115, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, SCTP
, PAY4
),
364 I40E_PTT(116, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, ICMP
, PAY4
),
366 /* IPv6 --> GRE/NAT -> IPv6 */
367 I40E_PTT(117, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, FRG
, NONE
, PAY3
),
368 I40E_PTT(118, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, NONE
, PAY3
),
369 I40E_PTT(119, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, UDP
, PAY4
),
370 I40E_PTT_UNUSED_ENTRY(120),
371 I40E_PTT(121, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, TCP
, PAY4
),
372 I40E_PTT(122, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, SCTP
, PAY4
),
373 I40E_PTT(123, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, ICMP
, PAY4
),
375 /* IPv6 --> GRE/NAT -> MAC */
376 I40E_PTT(124, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, NONE
, NOF
, NONE
, PAY3
),
378 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
379 I40E_PTT(125, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, FRG
, NONE
, PAY3
),
380 I40E_PTT(126, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, NONE
, PAY3
),
381 I40E_PTT(127, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, UDP
, PAY4
),
382 I40E_PTT_UNUSED_ENTRY(128),
383 I40E_PTT(129, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, TCP
, PAY4
),
384 I40E_PTT(130, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, SCTP
, PAY4
),
385 I40E_PTT(131, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, ICMP
, PAY4
),
387 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
388 I40E_PTT(132, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, FRG
, NONE
, PAY3
),
389 I40E_PTT(133, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, NONE
, PAY3
),
390 I40E_PTT(134, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, UDP
, PAY4
),
391 I40E_PTT_UNUSED_ENTRY(135),
392 I40E_PTT(136, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, TCP
, PAY4
),
393 I40E_PTT(137, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, SCTP
, PAY4
),
394 I40E_PTT(138, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, ICMP
, PAY4
),
396 /* IPv6 --> GRE/NAT -> MAC/VLAN */
397 I40E_PTT(139, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, NONE
, NOF
, NONE
, PAY3
),
399 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
400 I40E_PTT(140, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, FRG
, NONE
, PAY3
),
401 I40E_PTT(141, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, NONE
, PAY3
),
402 I40E_PTT(142, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, UDP
, PAY4
),
403 I40E_PTT_UNUSED_ENTRY(143),
404 I40E_PTT(144, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, TCP
, PAY4
),
405 I40E_PTT(145, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, SCTP
, PAY4
),
406 I40E_PTT(146, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, ICMP
, PAY4
),
408 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
409 I40E_PTT(147, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, FRG
, NONE
, PAY3
),
410 I40E_PTT(148, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, NONE
, PAY3
),
411 I40E_PTT(149, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, UDP
, PAY4
),
412 I40E_PTT_UNUSED_ENTRY(150),
413 I40E_PTT(151, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, TCP
, PAY4
),
414 I40E_PTT(152, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, SCTP
, PAY4
),
415 I40E_PTT(153, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, ICMP
, PAY4
),
418 I40E_PTT_UNUSED_ENTRY(154),
419 I40E_PTT_UNUSED_ENTRY(155),
420 I40E_PTT_UNUSED_ENTRY(156),
421 I40E_PTT_UNUSED_ENTRY(157),
422 I40E_PTT_UNUSED_ENTRY(158),
423 I40E_PTT_UNUSED_ENTRY(159),
425 I40E_PTT_UNUSED_ENTRY(160),
426 I40E_PTT_UNUSED_ENTRY(161),
427 I40E_PTT_UNUSED_ENTRY(162),
428 I40E_PTT_UNUSED_ENTRY(163),
429 I40E_PTT_UNUSED_ENTRY(164),
430 I40E_PTT_UNUSED_ENTRY(165),
431 I40E_PTT_UNUSED_ENTRY(166),
432 I40E_PTT_UNUSED_ENTRY(167),
433 I40E_PTT_UNUSED_ENTRY(168),
434 I40E_PTT_UNUSED_ENTRY(169),
436 I40E_PTT_UNUSED_ENTRY(170),
437 I40E_PTT_UNUSED_ENTRY(171),
438 I40E_PTT_UNUSED_ENTRY(172),
439 I40E_PTT_UNUSED_ENTRY(173),
440 I40E_PTT_UNUSED_ENTRY(174),
441 I40E_PTT_UNUSED_ENTRY(175),
442 I40E_PTT_UNUSED_ENTRY(176),
443 I40E_PTT_UNUSED_ENTRY(177),
444 I40E_PTT_UNUSED_ENTRY(178),
445 I40E_PTT_UNUSED_ENTRY(179),
447 I40E_PTT_UNUSED_ENTRY(180),
448 I40E_PTT_UNUSED_ENTRY(181),
449 I40E_PTT_UNUSED_ENTRY(182),
450 I40E_PTT_UNUSED_ENTRY(183),
451 I40E_PTT_UNUSED_ENTRY(184),
452 I40E_PTT_UNUSED_ENTRY(185),
453 I40E_PTT_UNUSED_ENTRY(186),
454 I40E_PTT_UNUSED_ENTRY(187),
455 I40E_PTT_UNUSED_ENTRY(188),
456 I40E_PTT_UNUSED_ENTRY(189),
458 I40E_PTT_UNUSED_ENTRY(190),
459 I40E_PTT_UNUSED_ENTRY(191),
460 I40E_PTT_UNUSED_ENTRY(192),
461 I40E_PTT_UNUSED_ENTRY(193),
462 I40E_PTT_UNUSED_ENTRY(194),
463 I40E_PTT_UNUSED_ENTRY(195),
464 I40E_PTT_UNUSED_ENTRY(196),
465 I40E_PTT_UNUSED_ENTRY(197),
466 I40E_PTT_UNUSED_ENTRY(198),
467 I40E_PTT_UNUSED_ENTRY(199),
469 I40E_PTT_UNUSED_ENTRY(200),
470 I40E_PTT_UNUSED_ENTRY(201),
471 I40E_PTT_UNUSED_ENTRY(202),
472 I40E_PTT_UNUSED_ENTRY(203),
473 I40E_PTT_UNUSED_ENTRY(204),
474 I40E_PTT_UNUSED_ENTRY(205),
475 I40E_PTT_UNUSED_ENTRY(206),
476 I40E_PTT_UNUSED_ENTRY(207),
477 I40E_PTT_UNUSED_ENTRY(208),
478 I40E_PTT_UNUSED_ENTRY(209),
480 I40E_PTT_UNUSED_ENTRY(210),
481 I40E_PTT_UNUSED_ENTRY(211),
482 I40E_PTT_UNUSED_ENTRY(212),
483 I40E_PTT_UNUSED_ENTRY(213),
484 I40E_PTT_UNUSED_ENTRY(214),
485 I40E_PTT_UNUSED_ENTRY(215),
486 I40E_PTT_UNUSED_ENTRY(216),
487 I40E_PTT_UNUSED_ENTRY(217),
488 I40E_PTT_UNUSED_ENTRY(218),
489 I40E_PTT_UNUSED_ENTRY(219),
491 I40E_PTT_UNUSED_ENTRY(220),
492 I40E_PTT_UNUSED_ENTRY(221),
493 I40E_PTT_UNUSED_ENTRY(222),
494 I40E_PTT_UNUSED_ENTRY(223),
495 I40E_PTT_UNUSED_ENTRY(224),
496 I40E_PTT_UNUSED_ENTRY(225),
497 I40E_PTT_UNUSED_ENTRY(226),
498 I40E_PTT_UNUSED_ENTRY(227),
499 I40E_PTT_UNUSED_ENTRY(228),
500 I40E_PTT_UNUSED_ENTRY(229),
502 I40E_PTT_UNUSED_ENTRY(230),
503 I40E_PTT_UNUSED_ENTRY(231),
504 I40E_PTT_UNUSED_ENTRY(232),
505 I40E_PTT_UNUSED_ENTRY(233),
506 I40E_PTT_UNUSED_ENTRY(234),
507 I40E_PTT_UNUSED_ENTRY(235),
508 I40E_PTT_UNUSED_ENTRY(236),
509 I40E_PTT_UNUSED_ENTRY(237),
510 I40E_PTT_UNUSED_ENTRY(238),
511 I40E_PTT_UNUSED_ENTRY(239),
513 I40E_PTT_UNUSED_ENTRY(240),
514 I40E_PTT_UNUSED_ENTRY(241),
515 I40E_PTT_UNUSED_ENTRY(242),
516 I40E_PTT_UNUSED_ENTRY(243),
517 I40E_PTT_UNUSED_ENTRY(244),
518 I40E_PTT_UNUSED_ENTRY(245),
519 I40E_PTT_UNUSED_ENTRY(246),
520 I40E_PTT_UNUSED_ENTRY(247),
521 I40E_PTT_UNUSED_ENTRY(248),
522 I40E_PTT_UNUSED_ENTRY(249),
524 I40E_PTT_UNUSED_ENTRY(250),
525 I40E_PTT_UNUSED_ENTRY(251),
526 I40E_PTT_UNUSED_ENTRY(252),
527 I40E_PTT_UNUSED_ENTRY(253),
528 I40E_PTT_UNUSED_ENTRY(254),
529 I40E_PTT_UNUSED_ENTRY(255)
534 * i40e_init_shared_code - Initialize the shared code
535 * @hw: pointer to hardware structure
537 * This assigns the MAC type and PHY code and inits the NVM.
538 * Does not touch the hardware. This function must be called prior to any
539 * other function in the shared code. The i40e_hw structure should be
540 * memset to 0 prior to calling this function. The following fields in
541 * hw structure should be filled in prior to calling this function:
542 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
543 * subsystem_vendor_id, and revision_id
545 i40e_status
i40e_init_shared_code(struct i40e_hw
*hw
)
547 i40e_status status
= 0;
550 i40e_set_mac_type(hw
);
552 switch (hw
->mac
.type
) {
556 return I40E_ERR_DEVICE_NOT_SUPPORTED
;
559 hw
->phy
.get_link_info
= true;
561 /* Determine port number */
562 reg
= rd32(hw
, I40E_PFGEN_PORTNUM
);
563 reg
= ((reg
& I40E_PFGEN_PORTNUM_PORT_NUM_MASK
) >>
564 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT
);
567 /* Determine the PF number based on the PCI fn */
568 reg
= rd32(hw
, I40E_GLPCI_CAPSUP
);
569 if (reg
& I40E_GLPCI_CAPSUP_ARI_EN_MASK
)
570 hw
->pf_id
= (u8
)((hw
->bus
.device
<< 3) | hw
->bus
.func
);
572 hw
->pf_id
= (u8
)hw
->bus
.func
;
574 status
= i40e_init_nvm(hw
);
579 * i40e_aq_mac_address_read - Retrieve the MAC addresses
580 * @hw: pointer to the hw struct
581 * @flags: a return indicator of what addresses were added to the addr store
582 * @addrs: the requestor's mac addr store
583 * @cmd_details: pointer to command details structure or NULL
585 static i40e_status
i40e_aq_mac_address_read(struct i40e_hw
*hw
,
587 struct i40e_aqc_mac_address_read_data
*addrs
,
588 struct i40e_asq_cmd_details
*cmd_details
)
590 struct i40e_aq_desc desc
;
591 struct i40e_aqc_mac_address_read
*cmd_data
=
592 (struct i40e_aqc_mac_address_read
*)&desc
.params
.raw
;
595 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_mac_address_read
);
596 desc
.flags
|= cpu_to_le16(I40E_AQ_FLAG_BUF
);
598 status
= i40e_asq_send_command(hw
, &desc
, addrs
,
599 sizeof(*addrs
), cmd_details
);
600 *flags
= le16_to_cpu(cmd_data
->command_flags
);
606 * i40e_aq_mac_address_write - Change the MAC addresses
607 * @hw: pointer to the hw struct
608 * @flags: indicates which MAC to be written
609 * @mac_addr: address to write
610 * @cmd_details: pointer to command details structure or NULL
612 i40e_status
i40e_aq_mac_address_write(struct i40e_hw
*hw
,
613 u16 flags
, u8
*mac_addr
,
614 struct i40e_asq_cmd_details
*cmd_details
)
616 struct i40e_aq_desc desc
;
617 struct i40e_aqc_mac_address_write
*cmd_data
=
618 (struct i40e_aqc_mac_address_write
*)&desc
.params
.raw
;
621 i40e_fill_default_direct_cmd_desc(&desc
,
622 i40e_aqc_opc_mac_address_write
);
623 cmd_data
->command_flags
= cpu_to_le16(flags
);
624 cmd_data
->mac_sah
= cpu_to_le16((u16
)mac_addr
[0] << 8 | mac_addr
[1]);
625 cmd_data
->mac_sal
= cpu_to_le32(((u32
)mac_addr
[2] << 24) |
626 ((u32
)mac_addr
[3] << 16) |
627 ((u32
)mac_addr
[4] << 8) |
630 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
636 * i40e_get_mac_addr - get MAC address
637 * @hw: pointer to the HW structure
638 * @mac_addr: pointer to MAC address
640 * Reads the adapter's MAC address from register
642 i40e_status
i40e_get_mac_addr(struct i40e_hw
*hw
, u8
*mac_addr
)
644 struct i40e_aqc_mac_address_read_data addrs
;
648 status
= i40e_aq_mac_address_read(hw
, &flags
, &addrs
, NULL
);
650 if (flags
& I40E_AQC_LAN_ADDR_VALID
)
651 memcpy(mac_addr
, &addrs
.pf_lan_mac
, sizeof(addrs
.pf_lan_mac
));
657 * i40e_get_port_mac_addr - get Port MAC address
658 * @hw: pointer to the HW structure
659 * @mac_addr: pointer to Port MAC address
661 * Reads the adapter's Port MAC address
663 i40e_status
i40e_get_port_mac_addr(struct i40e_hw
*hw
, u8
*mac_addr
)
665 struct i40e_aqc_mac_address_read_data addrs
;
669 status
= i40e_aq_mac_address_read(hw
, &flags
, &addrs
, NULL
);
673 if (flags
& I40E_AQC_PORT_ADDR_VALID
)
674 memcpy(mac_addr
, &addrs
.port_mac
, sizeof(addrs
.port_mac
));
676 status
= I40E_ERR_INVALID_MAC_ADDR
;
682 * i40e_pre_tx_queue_cfg - pre tx queue configure
683 * @hw: pointer to the HW structure
684 * @queue: target pf queue index
685 * @enable: state change request
687 * Handles hw requirement to indicate intention to enable
688 * or disable target queue.
690 void i40e_pre_tx_queue_cfg(struct i40e_hw
*hw
, u32 queue
, bool enable
)
692 u32 abs_queue_idx
= hw
->func_caps
.base_queue
+ queue
;
696 if (abs_queue_idx
>= 128) {
697 reg_block
= abs_queue_idx
/ 128;
698 abs_queue_idx
%= 128;
701 reg_val
= rd32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
));
702 reg_val
&= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK
;
703 reg_val
|= (abs_queue_idx
<< I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT
);
706 reg_val
|= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK
;
708 reg_val
|= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK
;
710 wr32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
), reg_val
);
715 * i40e_get_san_mac_addr - get SAN MAC address
716 * @hw: pointer to the HW structure
717 * @mac_addr: pointer to SAN MAC address
719 * Reads the adapter's SAN MAC address from NVM
721 i40e_status
i40e_get_san_mac_addr(struct i40e_hw
*hw
, u8
*mac_addr
)
723 struct i40e_aqc_mac_address_read_data addrs
;
727 status
= i40e_aq_mac_address_read(hw
, &flags
, &addrs
, NULL
);
731 if (flags
& I40E_AQC_SAN_ADDR_VALID
)
732 memcpy(mac_addr
, &addrs
.pf_san_mac
, sizeof(addrs
.pf_san_mac
));
734 status
= I40E_ERR_INVALID_MAC_ADDR
;
741 * i40e_get_media_type - Gets media type
742 * @hw: pointer to the hardware structure
744 static enum i40e_media_type
i40e_get_media_type(struct i40e_hw
*hw
)
746 enum i40e_media_type media
;
748 switch (hw
->phy
.link_info
.phy_type
) {
749 case I40E_PHY_TYPE_10GBASE_SR
:
750 case I40E_PHY_TYPE_10GBASE_LR
:
751 case I40E_PHY_TYPE_40GBASE_SR4
:
752 case I40E_PHY_TYPE_40GBASE_LR4
:
753 media
= I40E_MEDIA_TYPE_FIBER
;
755 case I40E_PHY_TYPE_100BASE_TX
:
756 case I40E_PHY_TYPE_1000BASE_T
:
757 case I40E_PHY_TYPE_10GBASE_T
:
758 media
= I40E_MEDIA_TYPE_BASET
;
760 case I40E_PHY_TYPE_10GBASE_CR1_CU
:
761 case I40E_PHY_TYPE_40GBASE_CR4_CU
:
762 case I40E_PHY_TYPE_10GBASE_CR1
:
763 case I40E_PHY_TYPE_40GBASE_CR4
:
764 case I40E_PHY_TYPE_10GBASE_SFPP_CU
:
765 media
= I40E_MEDIA_TYPE_DA
;
767 case I40E_PHY_TYPE_1000BASE_KX
:
768 case I40E_PHY_TYPE_10GBASE_KX4
:
769 case I40E_PHY_TYPE_10GBASE_KR
:
770 case I40E_PHY_TYPE_40GBASE_KR4
:
771 media
= I40E_MEDIA_TYPE_BACKPLANE
;
773 case I40E_PHY_TYPE_SGMII
:
774 case I40E_PHY_TYPE_XAUI
:
775 case I40E_PHY_TYPE_XFI
:
776 case I40E_PHY_TYPE_XLAUI
:
777 case I40E_PHY_TYPE_XLPPI
:
779 media
= I40E_MEDIA_TYPE_UNKNOWN
;
786 #define I40E_PF_RESET_WAIT_COUNT_A0 200
787 #define I40E_PF_RESET_WAIT_COUNT 100
789 * i40e_pf_reset - Reset the PF
790 * @hw: pointer to the hardware structure
792 * Assuming someone else has triggered a global reset,
793 * assure the global reset is complete and then reset the PF
795 i40e_status
i40e_pf_reset(struct i40e_hw
*hw
)
802 /* Poll for Global Reset steady state in case of recent GRST.
803 * The grst delay value is in 100ms units, and we'll wait a
804 * couple counts longer to be sure we don't just miss the end.
806 grst_del
= rd32(hw
, I40E_GLGEN_RSTCTL
) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
807 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT
;
808 for (cnt
= 0; cnt
< grst_del
+ 2; cnt
++) {
809 reg
= rd32(hw
, I40E_GLGEN_RSTAT
);
810 if (!(reg
& I40E_GLGEN_RSTAT_DEVSTATE_MASK
))
814 if (reg
& I40E_GLGEN_RSTAT_DEVSTATE_MASK
) {
815 hw_dbg(hw
, "Global reset polling failed to complete.\n");
816 return I40E_ERR_RESET_FAILED
;
819 /* Now Wait for the FW to be ready */
820 for (cnt1
= 0; cnt1
< I40E_PF_RESET_WAIT_COUNT
; cnt1
++) {
821 reg
= rd32(hw
, I40E_GLNVM_ULD
);
822 reg
&= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
|
823 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
);
824 if (reg
== (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
|
825 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
)) {
826 hw_dbg(hw
, "Core and Global modules ready %d\n", cnt1
);
829 usleep_range(10000, 20000);
831 if (!(reg
& (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
|
832 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
))) {
833 hw_dbg(hw
, "wait for FW Reset complete timedout\n");
834 hw_dbg(hw
, "I40E_GLNVM_ULD = 0x%x\n", reg
);
835 return I40E_ERR_RESET_FAILED
;
838 /* If there was a Global Reset in progress when we got here,
839 * we don't need to do the PF Reset
842 if (hw
->revision_id
== 0)
843 cnt
= I40E_PF_RESET_WAIT_COUNT_A0
;
845 cnt
= I40E_PF_RESET_WAIT_COUNT
;
846 reg
= rd32(hw
, I40E_PFGEN_CTRL
);
847 wr32(hw
, I40E_PFGEN_CTRL
,
848 (reg
| I40E_PFGEN_CTRL_PFSWR_MASK
));
850 reg
= rd32(hw
, I40E_PFGEN_CTRL
);
851 if (!(reg
& I40E_PFGEN_CTRL_PFSWR_MASK
))
853 usleep_range(1000, 2000);
855 if (reg
& I40E_PFGEN_CTRL_PFSWR_MASK
) {
856 hw_dbg(hw
, "PF reset polling failed to complete.\n");
857 return I40E_ERR_RESET_FAILED
;
861 i40e_clear_pxe_mode(hw
);
867 * i40e_clear_hw - clear out any left over hw state
868 * @hw: pointer to the hw struct
870 * Clear queues and interrupts, typically called at init time,
871 * but after the capabilities have been found so we know how many
872 * queues and msix vectors have been allocated.
874 void i40e_clear_hw(struct i40e_hw
*hw
)
876 u32 num_queues
, base_queue
;
884 /* get number of interrupts, queues, and vfs */
885 val
= rd32(hw
, I40E_GLPCI_CNF2
);
886 num_pf_int
= (val
& I40E_GLPCI_CNF2_MSI_X_PF_N_MASK
) >>
887 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT
;
888 num_vf_int
= (val
& I40E_GLPCI_CNF2_MSI_X_VF_N_MASK
) >>
889 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT
;
891 val
= rd32(hw
, I40E_PFLAN_QALLOC
);
892 base_queue
= (val
& I40E_PFLAN_QALLOC_FIRSTQ_MASK
) >>
893 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT
;
894 j
= (val
& I40E_PFLAN_QALLOC_LASTQ_MASK
) >>
895 I40E_PFLAN_QALLOC_LASTQ_SHIFT
;
896 if (val
& I40E_PFLAN_QALLOC_VALID_MASK
)
897 num_queues
= (j
- base_queue
) + 1;
901 val
= rd32(hw
, I40E_PF_VT_PFALLOC
);
902 i
= (val
& I40E_PF_VT_PFALLOC_FIRSTVF_MASK
) >>
903 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT
;
904 j
= (val
& I40E_PF_VT_PFALLOC_LASTVF_MASK
) >>
905 I40E_PF_VT_PFALLOC_LASTVF_SHIFT
;
906 if (val
& I40E_PF_VT_PFALLOC_VALID_MASK
)
907 num_vfs
= (j
- i
) + 1;
911 /* stop all the interrupts */
912 wr32(hw
, I40E_PFINT_ICR0_ENA
, 0);
913 val
= 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT
;
914 for (i
= 0; i
< num_pf_int
- 2; i
++)
915 wr32(hw
, I40E_PFINT_DYN_CTLN(i
), val
);
917 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
918 val
= eol
<< I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT
;
919 wr32(hw
, I40E_PFINT_LNKLST0
, val
);
920 for (i
= 0; i
< num_pf_int
- 2; i
++)
921 wr32(hw
, I40E_PFINT_LNKLSTN(i
), val
);
922 val
= eol
<< I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT
;
923 for (i
= 0; i
< num_vfs
; i
++)
924 wr32(hw
, I40E_VPINT_LNKLST0(i
), val
);
925 for (i
= 0; i
< num_vf_int
- 2; i
++)
926 wr32(hw
, I40E_VPINT_LNKLSTN(i
), val
);
928 /* warn the HW of the coming Tx disables */
929 for (i
= 0; i
< num_queues
; i
++) {
930 u32 abs_queue_idx
= base_queue
+ i
;
933 if (abs_queue_idx
>= 128) {
934 reg_block
= abs_queue_idx
/ 128;
935 abs_queue_idx
%= 128;
938 val
= rd32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
));
939 val
&= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK
;
940 val
|= (abs_queue_idx
<< I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT
);
941 val
|= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK
;
943 wr32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
), val
);
947 /* stop all the queues */
948 for (i
= 0; i
< num_queues
; i
++) {
949 wr32(hw
, I40E_QINT_TQCTL(i
), 0);
950 wr32(hw
, I40E_QTX_ENA(i
), 0);
951 wr32(hw
, I40E_QINT_RQCTL(i
), 0);
952 wr32(hw
, I40E_QRX_ENA(i
), 0);
955 /* short wait for all queue disables to settle */
960 * i40e_clear_pxe_mode - clear pxe operations mode
961 * @hw: pointer to the hw struct
963 * Make sure all PXE mode settings are cleared, including things
964 * like descriptor fetch/write-back mode.
966 void i40e_clear_pxe_mode(struct i40e_hw
*hw
)
970 if (i40e_check_asq_alive(hw
))
971 i40e_aq_clear_pxe_mode(hw
, NULL
);
973 /* Clear single descriptor fetch/write-back mode */
974 reg
= rd32(hw
, I40E_GLLAN_RCTL_0
);
976 if (hw
->revision_id
== 0) {
977 /* As a work around clear PXE_MODE instead of setting it */
978 wr32(hw
, I40E_GLLAN_RCTL_0
, (reg
& (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK
)));
980 wr32(hw
, I40E_GLLAN_RCTL_0
, (reg
| I40E_GLLAN_RCTL_0_PXE_MODE_MASK
));
985 * i40e_led_is_mine - helper to find matching led
986 * @hw: pointer to the hw struct
987 * @idx: index into GPIO registers
989 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
991 static u32
i40e_led_is_mine(struct i40e_hw
*hw
, int idx
)
996 if (!hw
->func_caps
.led
[idx
])
999 gpio_val
= rd32(hw
, I40E_GLGEN_GPIO_CTL(idx
));
1000 port
= (gpio_val
& I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK
) >>
1001 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT
;
1003 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1004 * if it is not our port then ignore
1006 if ((gpio_val
& I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK
) ||
1013 #define I40E_LED0 22
1014 #define I40E_LINK_ACTIVITY 0xC
1017 * i40e_led_get - return current on/off mode
1018 * @hw: pointer to the hw struct
1020 * The value returned is the 'mode' field as defined in the
1021 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1022 * values are variations of possible behaviors relating to
1023 * blink, link, and wire.
1025 u32
i40e_led_get(struct i40e_hw
*hw
)
1030 /* as per the documentation GPIO 22-29 are the LED
1031 * GPIO pins named LED0..LED7
1033 for (i
= I40E_LED0
; i
<= I40E_GLGEN_GPIO_CTL_MAX_INDEX
; i
++) {
1034 u32 gpio_val
= i40e_led_is_mine(hw
, i
);
1039 mode
= (gpio_val
& I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
) >>
1040 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
;
1048 * i40e_led_set - set new on/off mode
1049 * @hw: pointer to the hw struct
1050 * @mode: 0=off, 0xf=on (else see manual for mode details)
1051 * @blink: true if the LED should blink when on, false if steady
1053 * if this function is used to turn on the blink it should
1054 * be used to disable the blink when restoring the original state.
1056 void i40e_led_set(struct i40e_hw
*hw
, u32 mode
, bool blink
)
1060 if (mode
& 0xfffffff0)
1061 hw_dbg(hw
, "invalid mode passed in %X\n", mode
);
1063 /* as per the documentation GPIO 22-29 are the LED
1064 * GPIO pins named LED0..LED7
1066 for (i
= I40E_LED0
; i
<= I40E_GLGEN_GPIO_CTL_MAX_INDEX
; i
++) {
1067 u32 gpio_val
= i40e_led_is_mine(hw
, i
);
1072 gpio_val
&= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
;
1073 /* this & is a bit of paranoia, but serves as a range check */
1074 gpio_val
|= ((mode
<< I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
) &
1075 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
);
1077 if (mode
== I40E_LINK_ACTIVITY
)
1080 gpio_val
|= (blink
? 1 : 0) <<
1081 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT
;
1083 wr32(hw
, I40E_GLGEN_GPIO_CTL(i
), gpio_val
);
1088 /* Admin command wrappers */
1091 * i40e_aq_get_phy_capabilities
1092 * @hw: pointer to the hw struct
1093 * @abilities: structure for PHY capabilities to be filled
1094 * @qualified_modules: report Qualified Modules
1095 * @report_init: report init capabilities (active are default)
1096 * @cmd_details: pointer to command details structure or NULL
1098 * Returns the various PHY abilities supported on the Port.
1100 i40e_status
i40e_aq_get_phy_capabilities(struct i40e_hw
*hw
,
1101 bool qualified_modules
, bool report_init
,
1102 struct i40e_aq_get_phy_abilities_resp
*abilities
,
1103 struct i40e_asq_cmd_details
*cmd_details
)
1105 struct i40e_aq_desc desc
;
1107 u16 abilities_size
= sizeof(struct i40e_aq_get_phy_abilities_resp
);
1110 return I40E_ERR_PARAM
;
1112 i40e_fill_default_direct_cmd_desc(&desc
,
1113 i40e_aqc_opc_get_phy_abilities
);
1115 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
1116 if (abilities_size
> I40E_AQ_LARGE_BUF
)
1117 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
1119 if (qualified_modules
)
1120 desc
.params
.external
.param0
|=
1121 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES
);
1124 desc
.params
.external
.param0
|=
1125 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES
);
1127 status
= i40e_asq_send_command(hw
, &desc
, abilities
, abilities_size
,
1130 if (hw
->aq
.asq_last_status
== I40E_AQ_RC_EIO
)
1131 status
= I40E_ERR_UNKNOWN_PHY
;
1137 * i40e_aq_set_phy_config
1138 * @hw: pointer to the hw struct
1139 * @config: structure with PHY configuration to be set
1140 * @cmd_details: pointer to command details structure or NULL
1142 * Set the various PHY configuration parameters
1143 * supported on the Port.One or more of the Set PHY config parameters may be
1144 * ignored in an MFP mode as the PF may not have the privilege to set some
1145 * of the PHY Config parameters. This status will be indicated by the
1148 enum i40e_status_code
i40e_aq_set_phy_config(struct i40e_hw
*hw
,
1149 struct i40e_aq_set_phy_config
*config
,
1150 struct i40e_asq_cmd_details
*cmd_details
)
1152 struct i40e_aq_desc desc
;
1153 struct i40e_aq_set_phy_config
*cmd
=
1154 (struct i40e_aq_set_phy_config
*)&desc
.params
.raw
;
1155 enum i40e_status_code status
;
1158 return I40E_ERR_PARAM
;
1160 i40e_fill_default_direct_cmd_desc(&desc
,
1161 i40e_aqc_opc_set_phy_config
);
1165 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1172 * @hw: pointer to the hw struct
1174 * Set the requested flow control mode using set_phy_config.
1176 enum i40e_status_code
i40e_set_fc(struct i40e_hw
*hw
, u8
*aq_failures
,
1177 bool atomic_restart
)
1179 enum i40e_fc_mode fc_mode
= hw
->fc
.requested_mode
;
1180 struct i40e_aq_get_phy_abilities_resp abilities
;
1181 struct i40e_aq_set_phy_config config
;
1182 enum i40e_status_code status
;
1183 u8 pause_mask
= 0x0;
1189 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_TX
;
1190 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_RX
;
1192 case I40E_FC_RX_PAUSE
:
1193 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_RX
;
1195 case I40E_FC_TX_PAUSE
:
1196 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_TX
;
1202 /* Get the current phy config */
1203 status
= i40e_aq_get_phy_capabilities(hw
, false, false, &abilities
,
1206 *aq_failures
|= I40E_SET_FC_AQ_FAIL_GET
;
1210 memset(&config
, 0, sizeof(struct i40e_aq_set_phy_config
));
1211 /* clear the old pause settings */
1212 config
.abilities
= abilities
.abilities
& ~(I40E_AQ_PHY_FLAG_PAUSE_TX
) &
1213 ~(I40E_AQ_PHY_FLAG_PAUSE_RX
);
1214 /* set the new abilities */
1215 config
.abilities
|= pause_mask
;
1216 /* If the abilities have changed, then set the new config */
1217 if (config
.abilities
!= abilities
.abilities
) {
1218 /* Auto restart link so settings take effect */
1220 config
.abilities
|= I40E_AQ_PHY_ENABLE_ATOMIC_LINK
;
1221 /* Copy over all the old settings */
1222 config
.phy_type
= abilities
.phy_type
;
1223 config
.link_speed
= abilities
.link_speed
;
1224 config
.eee_capability
= abilities
.eee_capability
;
1225 config
.eeer
= abilities
.eeer_val
;
1226 config
.low_power_ctrl
= abilities
.d3_lpan
;
1227 status
= i40e_aq_set_phy_config(hw
, &config
, NULL
);
1230 *aq_failures
|= I40E_SET_FC_AQ_FAIL_SET
;
1232 /* Update the link info */
1233 status
= i40e_update_link_info(hw
, true);
1235 /* Wait a little bit (on 40G cards it sometimes takes a really
1236 * long time for link to come back from the atomic reset)
1240 status
= i40e_update_link_info(hw
, true);
1243 *aq_failures
|= I40E_SET_FC_AQ_FAIL_UPDATE
;
1249 * i40e_aq_clear_pxe_mode
1250 * @hw: pointer to the hw struct
1251 * @cmd_details: pointer to command details structure or NULL
1253 * Tell the firmware that the driver is taking over from PXE
1255 i40e_status
i40e_aq_clear_pxe_mode(struct i40e_hw
*hw
,
1256 struct i40e_asq_cmd_details
*cmd_details
)
1259 struct i40e_aq_desc desc
;
1260 struct i40e_aqc_clear_pxe
*cmd
=
1261 (struct i40e_aqc_clear_pxe
*)&desc
.params
.raw
;
1263 i40e_fill_default_direct_cmd_desc(&desc
,
1264 i40e_aqc_opc_clear_pxe_mode
);
1268 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1270 wr32(hw
, I40E_GLLAN_RCTL_0
, 0x1);
1276 * i40e_aq_set_link_restart_an
1277 * @hw: pointer to the hw struct
1278 * @enable_link: if true: enable link, if false: disable link
1279 * @cmd_details: pointer to command details structure or NULL
1281 * Sets up the link and restarts the Auto-Negotiation over the link.
1283 i40e_status
i40e_aq_set_link_restart_an(struct i40e_hw
*hw
,
1285 struct i40e_asq_cmd_details
*cmd_details
)
1287 struct i40e_aq_desc desc
;
1288 struct i40e_aqc_set_link_restart_an
*cmd
=
1289 (struct i40e_aqc_set_link_restart_an
*)&desc
.params
.raw
;
1292 i40e_fill_default_direct_cmd_desc(&desc
,
1293 i40e_aqc_opc_set_link_restart_an
);
1295 cmd
->command
= I40E_AQ_PHY_RESTART_AN
;
1297 cmd
->command
|= I40E_AQ_PHY_LINK_ENABLE
;
1299 cmd
->command
&= ~I40E_AQ_PHY_LINK_ENABLE
;
1301 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1307 * i40e_aq_get_link_info
1308 * @hw: pointer to the hw struct
1309 * @enable_lse: enable/disable LinkStatusEvent reporting
1310 * @link: pointer to link status structure - optional
1311 * @cmd_details: pointer to command details structure or NULL
1313 * Returns the link status of the adapter.
1315 i40e_status
i40e_aq_get_link_info(struct i40e_hw
*hw
,
1316 bool enable_lse
, struct i40e_link_status
*link
,
1317 struct i40e_asq_cmd_details
*cmd_details
)
1319 struct i40e_aq_desc desc
;
1320 struct i40e_aqc_get_link_status
*resp
=
1321 (struct i40e_aqc_get_link_status
*)&desc
.params
.raw
;
1322 struct i40e_link_status
*hw_link_info
= &hw
->phy
.link_info
;
1324 bool tx_pause
, rx_pause
;
1327 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_get_link_status
);
1330 command_flags
= I40E_AQ_LSE_ENABLE
;
1332 command_flags
= I40E_AQ_LSE_DISABLE
;
1333 resp
->command_flags
= cpu_to_le16(command_flags
);
1335 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1338 goto aq_get_link_info_exit
;
1340 /* save off old link status information */
1341 hw
->phy
.link_info_old
= *hw_link_info
;
1343 /* update link status */
1344 hw_link_info
->phy_type
= (enum i40e_aq_phy_type
)resp
->phy_type
;
1345 hw
->phy
.media_type
= i40e_get_media_type(hw
);
1346 hw_link_info
->link_speed
= (enum i40e_aq_link_speed
)resp
->link_speed
;
1347 hw_link_info
->link_info
= resp
->link_info
;
1348 hw_link_info
->an_info
= resp
->an_info
;
1349 hw_link_info
->ext_info
= resp
->ext_info
;
1350 hw_link_info
->loopback
= resp
->loopback
;
1351 hw_link_info
->max_frame_size
= le16_to_cpu(resp
->max_frame_size
);
1352 hw_link_info
->pacing
= resp
->config
& I40E_AQ_CONFIG_PACING_MASK
;
1354 /* update fc info */
1355 tx_pause
= !!(resp
->an_info
& I40E_AQ_LINK_PAUSE_TX
);
1356 rx_pause
= !!(resp
->an_info
& I40E_AQ_LINK_PAUSE_RX
);
1357 if (tx_pause
& rx_pause
)
1358 hw
->fc
.current_mode
= I40E_FC_FULL
;
1360 hw
->fc
.current_mode
= I40E_FC_TX_PAUSE
;
1362 hw
->fc
.current_mode
= I40E_FC_RX_PAUSE
;
1364 hw
->fc
.current_mode
= I40E_FC_NONE
;
1366 if (resp
->config
& I40E_AQ_CONFIG_CRC_ENA
)
1367 hw_link_info
->crc_enable
= true;
1369 hw_link_info
->crc_enable
= false;
1371 if (resp
->command_flags
& cpu_to_le16(I40E_AQ_LSE_ENABLE
))
1372 hw_link_info
->lse_enable
= true;
1374 hw_link_info
->lse_enable
= false;
1376 /* save link status information */
1378 *link
= *hw_link_info
;
1380 /* flag cleared so helper functions don't call AQ again */
1381 hw
->phy
.get_link_info
= false;
1383 aq_get_link_info_exit
:
1388 * i40e_update_link_info
1389 * @hw: pointer to the hw struct
1390 * @enable_lse: enable/disable LinkStatusEvent reporting
1392 * Returns the link status of the adapter
1394 i40e_status
i40e_update_link_info(struct i40e_hw
*hw
, bool enable_lse
)
1396 struct i40e_aq_get_phy_abilities_resp abilities
;
1399 status
= i40e_aq_get_link_info(hw
, enable_lse
, NULL
, NULL
);
1403 status
= i40e_aq_get_phy_capabilities(hw
, false, false,
1408 if (abilities
.abilities
& I40E_AQ_PHY_AN_ENABLED
)
1409 hw
->phy
.link_info
.an_enabled
= true;
1411 hw
->phy
.link_info
.an_enabled
= false;
1418 * @hw: pointer to the hw struct
1419 * @vsi_ctx: pointer to a vsi context struct
1420 * @cmd_details: pointer to command details structure or NULL
1422 * Add a VSI context to the hardware.
1424 i40e_status
i40e_aq_add_vsi(struct i40e_hw
*hw
,
1425 struct i40e_vsi_context
*vsi_ctx
,
1426 struct i40e_asq_cmd_details
*cmd_details
)
1428 struct i40e_aq_desc desc
;
1429 struct i40e_aqc_add_get_update_vsi
*cmd
=
1430 (struct i40e_aqc_add_get_update_vsi
*)&desc
.params
.raw
;
1431 struct i40e_aqc_add_get_update_vsi_completion
*resp
=
1432 (struct i40e_aqc_add_get_update_vsi_completion
*)
1436 i40e_fill_default_direct_cmd_desc(&desc
,
1437 i40e_aqc_opc_add_vsi
);
1439 cmd
->uplink_seid
= cpu_to_le16(vsi_ctx
->uplink_seid
);
1440 cmd
->connection_type
= vsi_ctx
->connection_type
;
1441 cmd
->vf_id
= vsi_ctx
->vf_num
;
1442 cmd
->vsi_flags
= cpu_to_le16(vsi_ctx
->flags
);
1444 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
1446 status
= i40e_asq_send_command(hw
, &desc
, &vsi_ctx
->info
,
1447 sizeof(vsi_ctx
->info
), cmd_details
);
1450 goto aq_add_vsi_exit
;
1452 vsi_ctx
->seid
= le16_to_cpu(resp
->seid
);
1453 vsi_ctx
->vsi_number
= le16_to_cpu(resp
->vsi_number
);
1454 vsi_ctx
->vsis_allocated
= le16_to_cpu(resp
->vsi_used
);
1455 vsi_ctx
->vsis_unallocated
= le16_to_cpu(resp
->vsi_free
);
1462 * i40e_aq_set_vsi_unicast_promiscuous
1463 * @hw: pointer to the hw struct
1465 * @set: set unicast promiscuous enable/disable
1466 * @cmd_details: pointer to command details structure or NULL
1468 i40e_status
i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw
*hw
,
1470 struct i40e_asq_cmd_details
*cmd_details
)
1472 struct i40e_aq_desc desc
;
1473 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
1474 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
1478 i40e_fill_default_direct_cmd_desc(&desc
,
1479 i40e_aqc_opc_set_vsi_promiscuous_modes
);
1482 flags
|= I40E_AQC_SET_VSI_PROMISC_UNICAST
;
1484 cmd
->promiscuous_flags
= cpu_to_le16(flags
);
1486 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST
);
1488 cmd
->seid
= cpu_to_le16(seid
);
1489 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1495 * i40e_aq_set_vsi_multicast_promiscuous
1496 * @hw: pointer to the hw struct
1498 * @set: set multicast promiscuous enable/disable
1499 * @cmd_details: pointer to command details structure or NULL
1501 i40e_status
i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw
*hw
,
1502 u16 seid
, bool set
, struct i40e_asq_cmd_details
*cmd_details
)
1504 struct i40e_aq_desc desc
;
1505 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
1506 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
1510 i40e_fill_default_direct_cmd_desc(&desc
,
1511 i40e_aqc_opc_set_vsi_promiscuous_modes
);
1514 flags
|= I40E_AQC_SET_VSI_PROMISC_MULTICAST
;
1516 cmd
->promiscuous_flags
= cpu_to_le16(flags
);
1518 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST
);
1520 cmd
->seid
= cpu_to_le16(seid
);
1521 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1527 * i40e_aq_set_vsi_broadcast
1528 * @hw: pointer to the hw struct
1530 * @set_filter: true to set filter, false to clear filter
1531 * @cmd_details: pointer to command details structure or NULL
1533 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1535 i40e_status
i40e_aq_set_vsi_broadcast(struct i40e_hw
*hw
,
1536 u16 seid
, bool set_filter
,
1537 struct i40e_asq_cmd_details
*cmd_details
)
1539 struct i40e_aq_desc desc
;
1540 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
1541 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
1544 i40e_fill_default_direct_cmd_desc(&desc
,
1545 i40e_aqc_opc_set_vsi_promiscuous_modes
);
1548 cmd
->promiscuous_flags
1549 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST
);
1551 cmd
->promiscuous_flags
1552 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST
);
1554 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST
);
1555 cmd
->seid
= cpu_to_le16(seid
);
1556 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1562 * i40e_get_vsi_params - get VSI configuration info
1563 * @hw: pointer to the hw struct
1564 * @vsi_ctx: pointer to a vsi context struct
1565 * @cmd_details: pointer to command details structure or NULL
1567 i40e_status
i40e_aq_get_vsi_params(struct i40e_hw
*hw
,
1568 struct i40e_vsi_context
*vsi_ctx
,
1569 struct i40e_asq_cmd_details
*cmd_details
)
1571 struct i40e_aq_desc desc
;
1572 struct i40e_aqc_add_get_update_vsi
*cmd
=
1573 (struct i40e_aqc_add_get_update_vsi
*)&desc
.params
.raw
;
1574 struct i40e_aqc_add_get_update_vsi_completion
*resp
=
1575 (struct i40e_aqc_add_get_update_vsi_completion
*)
1579 i40e_fill_default_direct_cmd_desc(&desc
,
1580 i40e_aqc_opc_get_vsi_parameters
);
1582 cmd
->uplink_seid
= cpu_to_le16(vsi_ctx
->seid
);
1584 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
1586 status
= i40e_asq_send_command(hw
, &desc
, &vsi_ctx
->info
,
1587 sizeof(vsi_ctx
->info
), NULL
);
1590 goto aq_get_vsi_params_exit
;
1592 vsi_ctx
->seid
= le16_to_cpu(resp
->seid
);
1593 vsi_ctx
->vsi_number
= le16_to_cpu(resp
->vsi_number
);
1594 vsi_ctx
->vsis_allocated
= le16_to_cpu(resp
->vsi_used
);
1595 vsi_ctx
->vsis_unallocated
= le16_to_cpu(resp
->vsi_free
);
1597 aq_get_vsi_params_exit
:
1602 * i40e_aq_update_vsi_params
1603 * @hw: pointer to the hw struct
1604 * @vsi_ctx: pointer to a vsi context struct
1605 * @cmd_details: pointer to command details structure or NULL
1607 * Update a VSI context.
1609 i40e_status
i40e_aq_update_vsi_params(struct i40e_hw
*hw
,
1610 struct i40e_vsi_context
*vsi_ctx
,
1611 struct i40e_asq_cmd_details
*cmd_details
)
1613 struct i40e_aq_desc desc
;
1614 struct i40e_aqc_add_get_update_vsi
*cmd
=
1615 (struct i40e_aqc_add_get_update_vsi
*)&desc
.params
.raw
;
1618 i40e_fill_default_direct_cmd_desc(&desc
,
1619 i40e_aqc_opc_update_vsi_parameters
);
1620 cmd
->uplink_seid
= cpu_to_le16(vsi_ctx
->seid
);
1622 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
1624 status
= i40e_asq_send_command(hw
, &desc
, &vsi_ctx
->info
,
1625 sizeof(vsi_ctx
->info
), cmd_details
);
1631 * i40e_aq_get_switch_config
1632 * @hw: pointer to the hardware structure
1633 * @buf: pointer to the result buffer
1634 * @buf_size: length of input buffer
1635 * @start_seid: seid to start for the report, 0 == beginning
1636 * @cmd_details: pointer to command details structure or NULL
1638 * Fill the buf with switch configuration returned from AdminQ command
1640 i40e_status
i40e_aq_get_switch_config(struct i40e_hw
*hw
,
1641 struct i40e_aqc_get_switch_config_resp
*buf
,
1642 u16 buf_size
, u16
*start_seid
,
1643 struct i40e_asq_cmd_details
*cmd_details
)
1645 struct i40e_aq_desc desc
;
1646 struct i40e_aqc_switch_seid
*scfg
=
1647 (struct i40e_aqc_switch_seid
*)&desc
.params
.raw
;
1650 i40e_fill_default_direct_cmd_desc(&desc
,
1651 i40e_aqc_opc_get_switch_config
);
1652 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
1653 if (buf_size
> I40E_AQ_LARGE_BUF
)
1654 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
1655 scfg
->seid
= cpu_to_le16(*start_seid
);
1657 status
= i40e_asq_send_command(hw
, &desc
, buf
, buf_size
, cmd_details
);
1658 *start_seid
= le16_to_cpu(scfg
->seid
);
1664 * i40e_aq_get_firmware_version
1665 * @hw: pointer to the hw struct
1666 * @fw_major_version: firmware major version
1667 * @fw_minor_version: firmware minor version
1668 * @api_major_version: major queue version
1669 * @api_minor_version: minor queue version
1670 * @cmd_details: pointer to command details structure or NULL
1672 * Get the firmware version from the admin queue commands
1674 i40e_status
i40e_aq_get_firmware_version(struct i40e_hw
*hw
,
1675 u16
*fw_major_version
, u16
*fw_minor_version
,
1676 u16
*api_major_version
, u16
*api_minor_version
,
1677 struct i40e_asq_cmd_details
*cmd_details
)
1679 struct i40e_aq_desc desc
;
1680 struct i40e_aqc_get_version
*resp
=
1681 (struct i40e_aqc_get_version
*)&desc
.params
.raw
;
1684 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_get_version
);
1686 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1689 if (fw_major_version
!= NULL
)
1690 *fw_major_version
= le16_to_cpu(resp
->fw_major
);
1691 if (fw_minor_version
!= NULL
)
1692 *fw_minor_version
= le16_to_cpu(resp
->fw_minor
);
1693 if (api_major_version
!= NULL
)
1694 *api_major_version
= le16_to_cpu(resp
->api_major
);
1695 if (api_minor_version
!= NULL
)
1696 *api_minor_version
= le16_to_cpu(resp
->api_minor
);
1703 * i40e_aq_send_driver_version
1704 * @hw: pointer to the hw struct
1705 * @dv: driver's major, minor version
1706 * @cmd_details: pointer to command details structure or NULL
1708 * Send the driver version to the firmware
1710 i40e_status
i40e_aq_send_driver_version(struct i40e_hw
*hw
,
1711 struct i40e_driver_version
*dv
,
1712 struct i40e_asq_cmd_details
*cmd_details
)
1714 struct i40e_aq_desc desc
;
1715 struct i40e_aqc_driver_version
*cmd
=
1716 (struct i40e_aqc_driver_version
*)&desc
.params
.raw
;
1721 return I40E_ERR_PARAM
;
1723 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_driver_version
);
1725 desc
.flags
|= cpu_to_le16(I40E_AQ_FLAG_SI
);
1726 cmd
->driver_major_ver
= dv
->major_version
;
1727 cmd
->driver_minor_ver
= dv
->minor_version
;
1728 cmd
->driver_build_ver
= dv
->build_version
;
1729 cmd
->driver_subbuild_ver
= dv
->subbuild_version
;
1732 while (len
< sizeof(dv
->driver_string
) &&
1733 (dv
->driver_string
[len
] < 0x80) &&
1734 dv
->driver_string
[len
])
1736 status
= i40e_asq_send_command(hw
, &desc
, dv
->driver_string
,
1743 * i40e_get_link_status - get status of the HW network link
1744 * @hw: pointer to the hw struct
1746 * Returns true if link is up, false if link is down.
1748 * Side effect: LinkStatusEvent reporting becomes enabled
1750 bool i40e_get_link_status(struct i40e_hw
*hw
)
1752 i40e_status status
= 0;
1753 bool link_status
= false;
1755 if (hw
->phy
.get_link_info
) {
1756 status
= i40e_aq_get_link_info(hw
, true, NULL
, NULL
);
1759 goto i40e_get_link_status_exit
;
1762 link_status
= hw
->phy
.link_info
.link_info
& I40E_AQ_LINK_UP
;
1764 i40e_get_link_status_exit
:
1769 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1770 * @hw: pointer to the hw struct
1771 * @uplink_seid: the MAC or other gizmo SEID
1772 * @downlink_seid: the VSI SEID
1773 * @enabled_tc: bitmap of TCs to be enabled
1774 * @default_port: true for default port VSI, false for control port
1775 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
1776 * @veb_seid: pointer to where to put the resulting VEB SEID
1777 * @cmd_details: pointer to command details structure or NULL
1779 * This asks the FW to add a VEB between the uplink and downlink
1780 * elements. If the uplink SEID is 0, this will be a floating VEB.
1782 i40e_status
i40e_aq_add_veb(struct i40e_hw
*hw
, u16 uplink_seid
,
1783 u16 downlink_seid
, u8 enabled_tc
,
1784 bool default_port
, bool enable_l2_filtering
,
1786 struct i40e_asq_cmd_details
*cmd_details
)
1788 struct i40e_aq_desc desc
;
1789 struct i40e_aqc_add_veb
*cmd
=
1790 (struct i40e_aqc_add_veb
*)&desc
.params
.raw
;
1791 struct i40e_aqc_add_veb_completion
*resp
=
1792 (struct i40e_aqc_add_veb_completion
*)&desc
.params
.raw
;
1796 /* SEIDs need to either both be set or both be 0 for floating VEB */
1797 if (!!uplink_seid
!= !!downlink_seid
)
1798 return I40E_ERR_PARAM
;
1800 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_add_veb
);
1802 cmd
->uplink_seid
= cpu_to_le16(uplink_seid
);
1803 cmd
->downlink_seid
= cpu_to_le16(downlink_seid
);
1804 cmd
->enable_tcs
= enabled_tc
;
1806 veb_flags
|= I40E_AQC_ADD_VEB_FLOATING
;
1808 veb_flags
|= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT
;
1810 veb_flags
|= I40E_AQC_ADD_VEB_PORT_TYPE_DATA
;
1812 if (enable_l2_filtering
)
1813 veb_flags
|= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER
;
1815 cmd
->veb_flags
= cpu_to_le16(veb_flags
);
1817 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1819 if (!status
&& veb_seid
)
1820 *veb_seid
= le16_to_cpu(resp
->veb_seid
);
1826 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1827 * @hw: pointer to the hw struct
1828 * @veb_seid: the SEID of the VEB to query
1829 * @switch_id: the uplink switch id
1830 * @floating: set to true if the VEB is floating
1831 * @statistic_index: index of the stats counter block for this VEB
1832 * @vebs_used: number of VEB's used by function
1833 * @vebs_free: total VEB's not reserved by any function
1834 * @cmd_details: pointer to command details structure or NULL
1836 * This retrieves the parameters for a particular VEB, specified by
1837 * uplink_seid, and returns them to the caller.
1839 i40e_status
i40e_aq_get_veb_parameters(struct i40e_hw
*hw
,
1840 u16 veb_seid
, u16
*switch_id
,
1841 bool *floating
, u16
*statistic_index
,
1842 u16
*vebs_used
, u16
*vebs_free
,
1843 struct i40e_asq_cmd_details
*cmd_details
)
1845 struct i40e_aq_desc desc
;
1846 struct i40e_aqc_get_veb_parameters_completion
*cmd_resp
=
1847 (struct i40e_aqc_get_veb_parameters_completion
*)
1852 return I40E_ERR_PARAM
;
1854 i40e_fill_default_direct_cmd_desc(&desc
,
1855 i40e_aqc_opc_get_veb_parameters
);
1856 cmd_resp
->seid
= cpu_to_le16(veb_seid
);
1858 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1863 *switch_id
= le16_to_cpu(cmd_resp
->switch_id
);
1864 if (statistic_index
)
1865 *statistic_index
= le16_to_cpu(cmd_resp
->statistic_index
);
1867 *vebs_used
= le16_to_cpu(cmd_resp
->vebs_used
);
1869 *vebs_free
= le16_to_cpu(cmd_resp
->vebs_free
);
1871 u16 flags
= le16_to_cpu(cmd_resp
->veb_flags
);
1872 if (flags
& I40E_AQC_ADD_VEB_FLOATING
)
1883 * i40e_aq_add_macvlan
1884 * @hw: pointer to the hw struct
1885 * @seid: VSI for the mac address
1886 * @mv_list: list of macvlans to be added
1887 * @count: length of the list
1888 * @cmd_details: pointer to command details structure or NULL
1890 * Add MAC/VLAN addresses to the HW filtering
1892 i40e_status
i40e_aq_add_macvlan(struct i40e_hw
*hw
, u16 seid
,
1893 struct i40e_aqc_add_macvlan_element_data
*mv_list
,
1894 u16 count
, struct i40e_asq_cmd_details
*cmd_details
)
1896 struct i40e_aq_desc desc
;
1897 struct i40e_aqc_macvlan
*cmd
=
1898 (struct i40e_aqc_macvlan
*)&desc
.params
.raw
;
1902 if (count
== 0 || !mv_list
|| !hw
)
1903 return I40E_ERR_PARAM
;
1905 buf_size
= count
* sizeof(struct i40e_aqc_add_macvlan_element_data
);
1907 /* prep the rest of the request */
1908 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_add_macvlan
);
1909 cmd
->num_addresses
= cpu_to_le16(count
);
1910 cmd
->seid
[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID
| seid
);
1914 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
1915 if (buf_size
> I40E_AQ_LARGE_BUF
)
1916 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
1918 status
= i40e_asq_send_command(hw
, &desc
, mv_list
, buf_size
,
1925 * i40e_aq_remove_macvlan
1926 * @hw: pointer to the hw struct
1927 * @seid: VSI for the mac address
1928 * @mv_list: list of macvlans to be removed
1929 * @count: length of the list
1930 * @cmd_details: pointer to command details structure or NULL
1932 * Remove MAC/VLAN addresses from the HW filtering
1934 i40e_status
i40e_aq_remove_macvlan(struct i40e_hw
*hw
, u16 seid
,
1935 struct i40e_aqc_remove_macvlan_element_data
*mv_list
,
1936 u16 count
, struct i40e_asq_cmd_details
*cmd_details
)
1938 struct i40e_aq_desc desc
;
1939 struct i40e_aqc_macvlan
*cmd
=
1940 (struct i40e_aqc_macvlan
*)&desc
.params
.raw
;
1944 if (count
== 0 || !mv_list
|| !hw
)
1945 return I40E_ERR_PARAM
;
1947 buf_size
= count
* sizeof(struct i40e_aqc_remove_macvlan_element_data
);
1949 /* prep the rest of the request */
1950 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_remove_macvlan
);
1951 cmd
->num_addresses
= cpu_to_le16(count
);
1952 cmd
->seid
[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID
| seid
);
1956 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
1957 if (buf_size
> I40E_AQ_LARGE_BUF
)
1958 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
1960 status
= i40e_asq_send_command(hw
, &desc
, mv_list
, buf_size
,
1967 * i40e_aq_send_msg_to_vf
1968 * @hw: pointer to the hardware structure
1969 * @vfid: vf id to send msg
1970 * @v_opcode: opcodes for VF-PF communication
1971 * @v_retval: return error code
1972 * @msg: pointer to the msg buffer
1973 * @msglen: msg length
1974 * @cmd_details: pointer to command details
1978 i40e_status
i40e_aq_send_msg_to_vf(struct i40e_hw
*hw
, u16 vfid
,
1979 u32 v_opcode
, u32 v_retval
, u8
*msg
, u16 msglen
,
1980 struct i40e_asq_cmd_details
*cmd_details
)
1982 struct i40e_aq_desc desc
;
1983 struct i40e_aqc_pf_vf_message
*cmd
=
1984 (struct i40e_aqc_pf_vf_message
*)&desc
.params
.raw
;
1987 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_send_msg_to_vf
);
1988 cmd
->id
= cpu_to_le32(vfid
);
1989 desc
.cookie_high
= cpu_to_le32(v_opcode
);
1990 desc
.cookie_low
= cpu_to_le32(v_retval
);
1991 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_SI
);
1993 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
|
1995 if (msglen
> I40E_AQ_LARGE_BUF
)
1996 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
1997 desc
.datalen
= cpu_to_le16(msglen
);
1999 status
= i40e_asq_send_command(hw
, &desc
, msg
, msglen
, cmd_details
);
2005 * i40e_aq_debug_write_register
2006 * @hw: pointer to the hw struct
2007 * @reg_addr: register address
2008 * @reg_val: register value
2009 * @cmd_details: pointer to command details structure or NULL
2011 * Write to a register using the admin queue commands
2013 i40e_status
i40e_aq_debug_write_register(struct i40e_hw
*hw
,
2014 u32 reg_addr
, u64 reg_val
,
2015 struct i40e_asq_cmd_details
*cmd_details
)
2017 struct i40e_aq_desc desc
;
2018 struct i40e_aqc_debug_reg_read_write
*cmd
=
2019 (struct i40e_aqc_debug_reg_read_write
*)&desc
.params
.raw
;
2022 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_debug_write_reg
);
2024 cmd
->address
= cpu_to_le32(reg_addr
);
2025 cmd
->value_high
= cpu_to_le32((u32
)(reg_val
>> 32));
2026 cmd
->value_low
= cpu_to_le32((u32
)(reg_val
& 0xFFFFFFFF));
2028 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2034 * i40e_aq_set_hmc_resource_profile
2035 * @hw: pointer to the hw struct
2036 * @profile: type of profile the HMC is to be set as
2037 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2038 * @cmd_details: pointer to command details structure or NULL
2040 * set the HMC profile of the device.
2042 i40e_status
i40e_aq_set_hmc_resource_profile(struct i40e_hw
*hw
,
2043 enum i40e_aq_hmc_profile profile
,
2044 u8 pe_vf_enabled_count
,
2045 struct i40e_asq_cmd_details
*cmd_details
)
2047 struct i40e_aq_desc desc
;
2048 struct i40e_aq_get_set_hmc_resource_profile
*cmd
=
2049 (struct i40e_aq_get_set_hmc_resource_profile
*)&desc
.params
.raw
;
2052 i40e_fill_default_direct_cmd_desc(&desc
,
2053 i40e_aqc_opc_set_hmc_resource_profile
);
2055 cmd
->pm_profile
= (u8
)profile
;
2056 cmd
->pe_vf_enabled
= pe_vf_enabled_count
;
2058 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2064 * i40e_aq_request_resource
2065 * @hw: pointer to the hw struct
2066 * @resource: resource id
2067 * @access: access type
2068 * @sdp_number: resource number
2069 * @timeout: the maximum time in ms that the driver may hold the resource
2070 * @cmd_details: pointer to command details structure or NULL
2072 * requests common resource using the admin queue commands
2074 i40e_status
i40e_aq_request_resource(struct i40e_hw
*hw
,
2075 enum i40e_aq_resources_ids resource
,
2076 enum i40e_aq_resource_access_type access
,
2077 u8 sdp_number
, u64
*timeout
,
2078 struct i40e_asq_cmd_details
*cmd_details
)
2080 struct i40e_aq_desc desc
;
2081 struct i40e_aqc_request_resource
*cmd_resp
=
2082 (struct i40e_aqc_request_resource
*)&desc
.params
.raw
;
2085 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_request_resource
);
2087 cmd_resp
->resource_id
= cpu_to_le16(resource
);
2088 cmd_resp
->access_type
= cpu_to_le16(access
);
2089 cmd_resp
->resource_number
= cpu_to_le32(sdp_number
);
2091 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2092 /* The completion specifies the maximum time in ms that the driver
2093 * may hold the resource in the Timeout field.
2094 * If the resource is held by someone else, the command completes with
2095 * busy return value and the timeout field indicates the maximum time
2096 * the current owner of the resource has to free it.
2098 if (!status
|| hw
->aq
.asq_last_status
== I40E_AQ_RC_EBUSY
)
2099 *timeout
= le32_to_cpu(cmd_resp
->timeout
);
2105 * i40e_aq_release_resource
2106 * @hw: pointer to the hw struct
2107 * @resource: resource id
2108 * @sdp_number: resource number
2109 * @cmd_details: pointer to command details structure or NULL
2111 * release common resource using the admin queue commands
2113 i40e_status
i40e_aq_release_resource(struct i40e_hw
*hw
,
2114 enum i40e_aq_resources_ids resource
,
2116 struct i40e_asq_cmd_details
*cmd_details
)
2118 struct i40e_aq_desc desc
;
2119 struct i40e_aqc_request_resource
*cmd
=
2120 (struct i40e_aqc_request_resource
*)&desc
.params
.raw
;
2123 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_release_resource
);
2125 cmd
->resource_id
= cpu_to_le16(resource
);
2126 cmd
->resource_number
= cpu_to_le32(sdp_number
);
2128 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2135 * @hw: pointer to the hw struct
2136 * @module_pointer: module pointer location in words from the NVM beginning
2137 * @offset: byte offset from the module beginning
2138 * @length: length of the section to be read (in bytes from the offset)
2139 * @data: command buffer (size [bytes] = length)
2140 * @last_command: tells if this is the last command in a series
2141 * @cmd_details: pointer to command details structure or NULL
2143 * Read the NVM using the admin queue commands
2145 i40e_status
i40e_aq_read_nvm(struct i40e_hw
*hw
, u8 module_pointer
,
2146 u32 offset
, u16 length
, void *data
,
2148 struct i40e_asq_cmd_details
*cmd_details
)
2150 struct i40e_aq_desc desc
;
2151 struct i40e_aqc_nvm_update
*cmd
=
2152 (struct i40e_aqc_nvm_update
*)&desc
.params
.raw
;
2155 /* In offset the highest byte must be zeroed. */
2156 if (offset
& 0xFF000000) {
2157 status
= I40E_ERR_PARAM
;
2158 goto i40e_aq_read_nvm_exit
;
2161 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_nvm_read
);
2163 /* If this is the last command in a series, set the proper flag. */
2165 cmd
->command_flags
|= I40E_AQ_NVM_LAST_CMD
;
2166 cmd
->module_pointer
= module_pointer
;
2167 cmd
->offset
= cpu_to_le32(offset
);
2168 cmd
->length
= cpu_to_le16(length
);
2170 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2171 if (length
> I40E_AQ_LARGE_BUF
)
2172 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2174 status
= i40e_asq_send_command(hw
, &desc
, data
, length
, cmd_details
);
2176 i40e_aq_read_nvm_exit
:
2182 * @hw: pointer to the hw struct
2183 * @module_pointer: module pointer location in words from the NVM beginning
2184 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2185 * @length: length of the section to be erased (expressed in 4 KB)
2186 * @last_command: tells if this is the last command in a series
2187 * @cmd_details: pointer to command details structure or NULL
2189 * Erase the NVM sector using the admin queue commands
2191 i40e_status
i40e_aq_erase_nvm(struct i40e_hw
*hw
, u8 module_pointer
,
2192 u32 offset
, u16 length
, bool last_command
,
2193 struct i40e_asq_cmd_details
*cmd_details
)
2195 struct i40e_aq_desc desc
;
2196 struct i40e_aqc_nvm_update
*cmd
=
2197 (struct i40e_aqc_nvm_update
*)&desc
.params
.raw
;
2200 /* In offset the highest byte must be zeroed. */
2201 if (offset
& 0xFF000000) {
2202 status
= I40E_ERR_PARAM
;
2203 goto i40e_aq_erase_nvm_exit
;
2206 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_nvm_erase
);
2208 /* If this is the last command in a series, set the proper flag. */
2210 cmd
->command_flags
|= I40E_AQ_NVM_LAST_CMD
;
2211 cmd
->module_pointer
= module_pointer
;
2212 cmd
->offset
= cpu_to_le32(offset
);
2213 cmd
->length
= cpu_to_le16(length
);
2215 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2217 i40e_aq_erase_nvm_exit
:
2221 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2222 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2223 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2224 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2225 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2226 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2227 #define I40E_DEV_FUNC_CAP_VF 0x13
2228 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2229 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2230 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2231 #define I40E_DEV_FUNC_CAP_VSI 0x17
2232 #define I40E_DEV_FUNC_CAP_DCB 0x18
2233 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2234 #define I40E_DEV_FUNC_CAP_RSS 0x40
2235 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2236 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2237 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2238 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2239 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2240 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2241 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2242 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2243 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2244 #define I40E_DEV_FUNC_CAP_LED 0x61
2245 #define I40E_DEV_FUNC_CAP_SDP 0x62
2246 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2249 * i40e_parse_discover_capabilities
2250 * @hw: pointer to the hw struct
2251 * @buff: pointer to a buffer containing device/function capability records
2252 * @cap_count: number of capability records in the list
2253 * @list_type_opc: type of capabilities list to parse
2255 * Parse the device/function capabilities list.
2257 static void i40e_parse_discover_capabilities(struct i40e_hw
*hw
, void *buff
,
2259 enum i40e_admin_queue_opc list_type_opc
)
2261 struct i40e_aqc_list_capabilities_element_resp
*cap
;
2262 u32 number
, logical_id
, phys_id
;
2263 struct i40e_hw_capabilities
*p
;
2267 cap
= (struct i40e_aqc_list_capabilities_element_resp
*) buff
;
2269 if (list_type_opc
== i40e_aqc_opc_list_dev_capabilities
)
2271 else if (list_type_opc
== i40e_aqc_opc_list_func_capabilities
)
2276 for (i
= 0; i
< cap_count
; i
++, cap
++) {
2277 id
= le16_to_cpu(cap
->id
);
2278 number
= le32_to_cpu(cap
->number
);
2279 logical_id
= le32_to_cpu(cap
->logical_id
);
2280 phys_id
= le32_to_cpu(cap
->phys_id
);
2283 case I40E_DEV_FUNC_CAP_SWITCH_MODE
:
2284 p
->switch_mode
= number
;
2286 case I40E_DEV_FUNC_CAP_MGMT_MODE
:
2287 p
->management_mode
= number
;
2289 case I40E_DEV_FUNC_CAP_NPAR
:
2290 p
->npar_enable
= number
;
2292 case I40E_DEV_FUNC_CAP_OS2BMC
:
2295 case I40E_DEV_FUNC_CAP_VALID_FUNC
:
2296 p
->valid_functions
= number
;
2298 case I40E_DEV_FUNC_CAP_SRIOV_1_1
:
2300 p
->sr_iov_1_1
= true;
2302 case I40E_DEV_FUNC_CAP_VF
:
2303 p
->num_vfs
= number
;
2304 p
->vf_base_id
= logical_id
;
2306 case I40E_DEV_FUNC_CAP_VMDQ
:
2310 case I40E_DEV_FUNC_CAP_802_1_QBG
:
2312 p
->evb_802_1_qbg
= true;
2314 case I40E_DEV_FUNC_CAP_802_1_QBH
:
2316 p
->evb_802_1_qbh
= true;
2318 case I40E_DEV_FUNC_CAP_VSI
:
2319 p
->num_vsis
= number
;
2321 case I40E_DEV_FUNC_CAP_DCB
:
2324 p
->enabled_tcmap
= logical_id
;
2328 case I40E_DEV_FUNC_CAP_FCOE
:
2332 case I40E_DEV_FUNC_CAP_RSS
:
2334 p
->rss_table_size
= number
;
2335 p
->rss_table_entry_width
= logical_id
;
2337 case I40E_DEV_FUNC_CAP_RX_QUEUES
:
2338 p
->num_rx_qp
= number
;
2339 p
->base_queue
= phys_id
;
2341 case I40E_DEV_FUNC_CAP_TX_QUEUES
:
2342 p
->num_tx_qp
= number
;
2343 p
->base_queue
= phys_id
;
2345 case I40E_DEV_FUNC_CAP_MSIX
:
2346 p
->num_msix_vectors
= number
;
2348 case I40E_DEV_FUNC_CAP_MSIX_VF
:
2349 p
->num_msix_vectors_vf
= number
;
2351 case I40E_DEV_FUNC_CAP_MFP_MODE_1
:
2353 p
->mfp_mode_1
= true;
2355 case I40E_DEV_FUNC_CAP_CEM
:
2359 case I40E_DEV_FUNC_CAP_IWARP
:
2363 case I40E_DEV_FUNC_CAP_LED
:
2364 if (phys_id
< I40E_HW_CAP_MAX_GPIO
)
2365 p
->led
[phys_id
] = true;
2367 case I40E_DEV_FUNC_CAP_SDP
:
2368 if (phys_id
< I40E_HW_CAP_MAX_GPIO
)
2369 p
->sdp
[phys_id
] = true;
2371 case I40E_DEV_FUNC_CAP_MDIO
:
2373 p
->mdio_port_num
= phys_id
;
2374 p
->mdio_port_mode
= logical_id
;
2377 case I40E_DEV_FUNC_CAP_IEEE_1588
:
2379 p
->ieee_1588
= true;
2381 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR
:
2383 p
->fd_filters_guaranteed
= number
;
2384 p
->fd_filters_best_effort
= logical_id
;
2391 /* Software override ensuring FCoE is disabled if npar or mfp
2392 * mode because it is not supported in these modes.
2394 if (p
->npar_enable
|| p
->mfp_mode_1
)
2397 /* additional HW specific goodies that might
2398 * someday be HW version specific
2400 p
->rx_buf_chain_len
= I40E_MAX_CHAINED_RX_BUFFERS
;
2404 * i40e_aq_discover_capabilities
2405 * @hw: pointer to the hw struct
2406 * @buff: a virtual buffer to hold the capabilities
2407 * @buff_size: Size of the virtual buffer
2408 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2409 * @list_type_opc: capabilities type to discover - pass in the command opcode
2410 * @cmd_details: pointer to command details structure or NULL
2412 * Get the device capabilities descriptions from the firmware
2414 i40e_status
i40e_aq_discover_capabilities(struct i40e_hw
*hw
,
2415 void *buff
, u16 buff_size
, u16
*data_size
,
2416 enum i40e_admin_queue_opc list_type_opc
,
2417 struct i40e_asq_cmd_details
*cmd_details
)
2419 struct i40e_aqc_list_capabilites
*cmd
;
2420 struct i40e_aq_desc desc
;
2421 i40e_status status
= 0;
2423 cmd
= (struct i40e_aqc_list_capabilites
*)&desc
.params
.raw
;
2425 if (list_type_opc
!= i40e_aqc_opc_list_func_capabilities
&&
2426 list_type_opc
!= i40e_aqc_opc_list_dev_capabilities
) {
2427 status
= I40E_ERR_PARAM
;
2431 i40e_fill_default_direct_cmd_desc(&desc
, list_type_opc
);
2433 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2434 if (buff_size
> I40E_AQ_LARGE_BUF
)
2435 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2437 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
2438 *data_size
= le16_to_cpu(desc
.datalen
);
2443 i40e_parse_discover_capabilities(hw
, buff
, le32_to_cpu(cmd
->count
),
2451 * i40e_aq_update_nvm
2452 * @hw: pointer to the hw struct
2453 * @module_pointer: module pointer location in words from the NVM beginning
2454 * @offset: byte offset from the module beginning
2455 * @length: length of the section to be written (in bytes from the offset)
2456 * @data: command buffer (size [bytes] = length)
2457 * @last_command: tells if this is the last command in a series
2458 * @cmd_details: pointer to command details structure or NULL
2460 * Update the NVM using the admin queue commands
2462 i40e_status
i40e_aq_update_nvm(struct i40e_hw
*hw
, u8 module_pointer
,
2463 u32 offset
, u16 length
, void *data
,
2465 struct i40e_asq_cmd_details
*cmd_details
)
2467 struct i40e_aq_desc desc
;
2468 struct i40e_aqc_nvm_update
*cmd
=
2469 (struct i40e_aqc_nvm_update
*)&desc
.params
.raw
;
2472 /* In offset the highest byte must be zeroed. */
2473 if (offset
& 0xFF000000) {
2474 status
= I40E_ERR_PARAM
;
2475 goto i40e_aq_update_nvm_exit
;
2478 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_nvm_update
);
2480 /* If this is the last command in a series, set the proper flag. */
2482 cmd
->command_flags
|= I40E_AQ_NVM_LAST_CMD
;
2483 cmd
->module_pointer
= module_pointer
;
2484 cmd
->offset
= cpu_to_le32(offset
);
2485 cmd
->length
= cpu_to_le16(length
);
2487 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
2488 if (length
> I40E_AQ_LARGE_BUF
)
2489 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2491 status
= i40e_asq_send_command(hw
, &desc
, data
, length
, cmd_details
);
2493 i40e_aq_update_nvm_exit
:
2498 * i40e_aq_get_lldp_mib
2499 * @hw: pointer to the hw struct
2500 * @bridge_type: type of bridge requested
2501 * @mib_type: Local, Remote or both Local and Remote MIBs
2502 * @buff: pointer to a user supplied buffer to store the MIB block
2503 * @buff_size: size of the buffer (in bytes)
2504 * @local_len : length of the returned Local LLDP MIB
2505 * @remote_len: length of the returned Remote LLDP MIB
2506 * @cmd_details: pointer to command details structure or NULL
2508 * Requests the complete LLDP MIB (entire packet).
2510 i40e_status
i40e_aq_get_lldp_mib(struct i40e_hw
*hw
, u8 bridge_type
,
2511 u8 mib_type
, void *buff
, u16 buff_size
,
2512 u16
*local_len
, u16
*remote_len
,
2513 struct i40e_asq_cmd_details
*cmd_details
)
2515 struct i40e_aq_desc desc
;
2516 struct i40e_aqc_lldp_get_mib
*cmd
=
2517 (struct i40e_aqc_lldp_get_mib
*)&desc
.params
.raw
;
2518 struct i40e_aqc_lldp_get_mib
*resp
=
2519 (struct i40e_aqc_lldp_get_mib
*)&desc
.params
.raw
;
2522 if (buff_size
== 0 || !buff
)
2523 return I40E_ERR_PARAM
;
2525 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_get_mib
);
2526 /* Indirect Command */
2527 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2529 cmd
->type
= mib_type
& I40E_AQ_LLDP_MIB_TYPE_MASK
;
2530 cmd
->type
|= ((bridge_type
<< I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT
) &
2531 I40E_AQ_LLDP_BRIDGE_TYPE_MASK
);
2533 desc
.datalen
= cpu_to_le16(buff_size
);
2535 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2536 if (buff_size
> I40E_AQ_LARGE_BUF
)
2537 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2539 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
2541 if (local_len
!= NULL
)
2542 *local_len
= le16_to_cpu(resp
->local_len
);
2543 if (remote_len
!= NULL
)
2544 *remote_len
= le16_to_cpu(resp
->remote_len
);
2551 * i40e_aq_cfg_lldp_mib_change_event
2552 * @hw: pointer to the hw struct
2553 * @enable_update: Enable or Disable event posting
2554 * @cmd_details: pointer to command details structure or NULL
2556 * Enable or Disable posting of an event on ARQ when LLDP MIB
2557 * associated with the interface changes
2559 i40e_status
i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw
*hw
,
2561 struct i40e_asq_cmd_details
*cmd_details
)
2563 struct i40e_aq_desc desc
;
2564 struct i40e_aqc_lldp_update_mib
*cmd
=
2565 (struct i40e_aqc_lldp_update_mib
*)&desc
.params
.raw
;
2568 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_update_mib
);
2571 cmd
->command
|= I40E_AQ_LLDP_MIB_UPDATE_DISABLE
;
2573 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2580 * @hw: pointer to the hw struct
2581 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2582 * @cmd_details: pointer to command details structure or NULL
2584 * Stop or Shutdown the embedded LLDP Agent
2586 i40e_status
i40e_aq_stop_lldp(struct i40e_hw
*hw
, bool shutdown_agent
,
2587 struct i40e_asq_cmd_details
*cmd_details
)
2589 struct i40e_aq_desc desc
;
2590 struct i40e_aqc_lldp_stop
*cmd
=
2591 (struct i40e_aqc_lldp_stop
*)&desc
.params
.raw
;
2594 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_stop
);
2597 cmd
->command
|= I40E_AQ_LLDP_AGENT_SHUTDOWN
;
2599 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2605 * i40e_aq_start_lldp
2606 * @hw: pointer to the hw struct
2607 * @cmd_details: pointer to command details structure or NULL
2609 * Start the embedded LLDP Agent on all ports.
2611 i40e_status
i40e_aq_start_lldp(struct i40e_hw
*hw
,
2612 struct i40e_asq_cmd_details
*cmd_details
)
2614 struct i40e_aq_desc desc
;
2615 struct i40e_aqc_lldp_start
*cmd
=
2616 (struct i40e_aqc_lldp_start
*)&desc
.params
.raw
;
2619 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_start
);
2621 cmd
->command
= I40E_AQ_LLDP_AGENT_START
;
2623 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2629 * i40e_aq_add_udp_tunnel
2630 * @hw: pointer to the hw struct
2631 * @udp_port: the UDP port to add
2632 * @header_len: length of the tunneling header length in DWords
2633 * @protocol_index: protocol index type
2634 * @filter_index: pointer to filter index
2635 * @cmd_details: pointer to command details structure or NULL
2637 i40e_status
i40e_aq_add_udp_tunnel(struct i40e_hw
*hw
,
2638 u16 udp_port
, u8 protocol_index
,
2640 struct i40e_asq_cmd_details
*cmd_details
)
2642 struct i40e_aq_desc desc
;
2643 struct i40e_aqc_add_udp_tunnel
*cmd
=
2644 (struct i40e_aqc_add_udp_tunnel
*)&desc
.params
.raw
;
2645 struct i40e_aqc_del_udp_tunnel_completion
*resp
=
2646 (struct i40e_aqc_del_udp_tunnel_completion
*)&desc
.params
.raw
;
2649 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_add_udp_tunnel
);
2651 cmd
->udp_port
= cpu_to_le16(udp_port
);
2652 cmd
->protocol_type
= protocol_index
;
2654 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2657 *filter_index
= resp
->index
;
2663 * i40e_aq_del_udp_tunnel
2664 * @hw: pointer to the hw struct
2665 * @index: filter index
2666 * @cmd_details: pointer to command details structure or NULL
2668 i40e_status
i40e_aq_del_udp_tunnel(struct i40e_hw
*hw
, u8 index
,
2669 struct i40e_asq_cmd_details
*cmd_details
)
2671 struct i40e_aq_desc desc
;
2672 struct i40e_aqc_remove_udp_tunnel
*cmd
=
2673 (struct i40e_aqc_remove_udp_tunnel
*)&desc
.params
.raw
;
2676 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_del_udp_tunnel
);
2680 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2686 * i40e_aq_delete_element - Delete switch element
2687 * @hw: pointer to the hw struct
2688 * @seid: the SEID to delete from the switch
2689 * @cmd_details: pointer to command details structure or NULL
2691 * This deletes a switch element from the switch.
2693 i40e_status
i40e_aq_delete_element(struct i40e_hw
*hw
, u16 seid
,
2694 struct i40e_asq_cmd_details
*cmd_details
)
2696 struct i40e_aq_desc desc
;
2697 struct i40e_aqc_switch_seid
*cmd
=
2698 (struct i40e_aqc_switch_seid
*)&desc
.params
.raw
;
2702 return I40E_ERR_PARAM
;
2704 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_delete_element
);
2706 cmd
->seid
= cpu_to_le16(seid
);
2708 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2714 * i40e_aq_dcb_updated - DCB Updated Command
2715 * @hw: pointer to the hw struct
2716 * @cmd_details: pointer to command details structure or NULL
2718 * EMP will return when the shared RPB settings have been
2719 * recomputed and modified. The retval field in the descriptor
2720 * will be set to 0 when RPB is modified.
2722 i40e_status
i40e_aq_dcb_updated(struct i40e_hw
*hw
,
2723 struct i40e_asq_cmd_details
*cmd_details
)
2725 struct i40e_aq_desc desc
;
2728 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_dcb_updated
);
2730 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2736 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2737 * @hw: pointer to the hw struct
2738 * @seid: seid for the physical port/switching component/vsi
2739 * @buff: Indirect buffer to hold data parameters and response
2740 * @buff_size: Indirect buffer size
2741 * @opcode: Tx scheduler AQ command opcode
2742 * @cmd_details: pointer to command details structure or NULL
2744 * Generic command handler for Tx scheduler AQ commands
2746 static i40e_status
i40e_aq_tx_sched_cmd(struct i40e_hw
*hw
, u16 seid
,
2747 void *buff
, u16 buff_size
,
2748 enum i40e_admin_queue_opc opcode
,
2749 struct i40e_asq_cmd_details
*cmd_details
)
2751 struct i40e_aq_desc desc
;
2752 struct i40e_aqc_tx_sched_ind
*cmd
=
2753 (struct i40e_aqc_tx_sched_ind
*)&desc
.params
.raw
;
2755 bool cmd_param_flag
= false;
2758 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit
:
2759 case i40e_aqc_opc_configure_vsi_tc_bw
:
2760 case i40e_aqc_opc_enable_switching_comp_ets
:
2761 case i40e_aqc_opc_modify_switching_comp_ets
:
2762 case i40e_aqc_opc_disable_switching_comp_ets
:
2763 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit
:
2764 case i40e_aqc_opc_configure_switching_comp_bw_config
:
2765 cmd_param_flag
= true;
2767 case i40e_aqc_opc_query_vsi_bw_config
:
2768 case i40e_aqc_opc_query_vsi_ets_sla_config
:
2769 case i40e_aqc_opc_query_switching_comp_ets_config
:
2770 case i40e_aqc_opc_query_port_ets_config
:
2771 case i40e_aqc_opc_query_switching_comp_bw_config
:
2772 cmd_param_flag
= false;
2775 return I40E_ERR_PARAM
;
2778 i40e_fill_default_direct_cmd_desc(&desc
, opcode
);
2780 /* Indirect command */
2781 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2783 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_RD
);
2784 if (buff_size
> I40E_AQ_LARGE_BUF
)
2785 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2787 desc
.datalen
= cpu_to_le16(buff_size
);
2789 cmd
->vsi_seid
= cpu_to_le16(seid
);
2791 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
2797 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
2798 * @hw: pointer to the hw struct
2800 * @credit: BW limit credits (0 = disabled)
2801 * @max_credit: Max BW limit credits
2802 * @cmd_details: pointer to command details structure or NULL
2804 i40e_status
i40e_aq_config_vsi_bw_limit(struct i40e_hw
*hw
,
2805 u16 seid
, u16 credit
, u8 max_credit
,
2806 struct i40e_asq_cmd_details
*cmd_details
)
2808 struct i40e_aq_desc desc
;
2809 struct i40e_aqc_configure_vsi_bw_limit
*cmd
=
2810 (struct i40e_aqc_configure_vsi_bw_limit
*)&desc
.params
.raw
;
2813 i40e_fill_default_direct_cmd_desc(&desc
,
2814 i40e_aqc_opc_configure_vsi_bw_limit
);
2816 cmd
->vsi_seid
= cpu_to_le16(seid
);
2817 cmd
->credit
= cpu_to_le16(credit
);
2818 cmd
->max_credit
= max_credit
;
2820 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2826 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
2827 * @hw: pointer to the hw struct
2829 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
2830 * @cmd_details: pointer to command details structure or NULL
2832 i40e_status
i40e_aq_config_vsi_tc_bw(struct i40e_hw
*hw
,
2834 struct i40e_aqc_configure_vsi_tc_bw_data
*bw_data
,
2835 struct i40e_asq_cmd_details
*cmd_details
)
2837 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2838 i40e_aqc_opc_configure_vsi_tc_bw
,
2843 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
2844 * @hw: pointer to the hw struct
2845 * @seid: seid of the switching component connected to Physical Port
2846 * @ets_data: Buffer holding ETS parameters
2847 * @cmd_details: pointer to command details structure or NULL
2849 i40e_status
i40e_aq_config_switch_comp_ets(struct i40e_hw
*hw
,
2851 struct i40e_aqc_configure_switching_comp_ets_data
*ets_data
,
2852 enum i40e_admin_queue_opc opcode
,
2853 struct i40e_asq_cmd_details
*cmd_details
)
2855 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)ets_data
,
2856 sizeof(*ets_data
), opcode
, cmd_details
);
2860 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
2861 * @hw: pointer to the hw struct
2862 * @seid: seid of the switching component
2863 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
2864 * @cmd_details: pointer to command details structure or NULL
2866 i40e_status
i40e_aq_config_switch_comp_bw_config(struct i40e_hw
*hw
,
2868 struct i40e_aqc_configure_switching_comp_bw_config_data
*bw_data
,
2869 struct i40e_asq_cmd_details
*cmd_details
)
2871 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2872 i40e_aqc_opc_configure_switching_comp_bw_config
,
2877 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
2878 * @hw: pointer to the hw struct
2879 * @seid: seid of the VSI
2880 * @bw_data: Buffer to hold VSI BW configuration
2881 * @cmd_details: pointer to command details structure or NULL
2883 i40e_status
i40e_aq_query_vsi_bw_config(struct i40e_hw
*hw
,
2885 struct i40e_aqc_query_vsi_bw_config_resp
*bw_data
,
2886 struct i40e_asq_cmd_details
*cmd_details
)
2888 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2889 i40e_aqc_opc_query_vsi_bw_config
,
2894 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
2895 * @hw: pointer to the hw struct
2896 * @seid: seid of the VSI
2897 * @bw_data: Buffer to hold VSI BW configuration per TC
2898 * @cmd_details: pointer to command details structure or NULL
2900 i40e_status
i40e_aq_query_vsi_ets_sla_config(struct i40e_hw
*hw
,
2902 struct i40e_aqc_query_vsi_ets_sla_config_resp
*bw_data
,
2903 struct i40e_asq_cmd_details
*cmd_details
)
2905 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2906 i40e_aqc_opc_query_vsi_ets_sla_config
,
2911 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
2912 * @hw: pointer to the hw struct
2913 * @seid: seid of the switching component
2914 * @bw_data: Buffer to hold switching component's per TC BW config
2915 * @cmd_details: pointer to command details structure or NULL
2917 i40e_status
i40e_aq_query_switch_comp_ets_config(struct i40e_hw
*hw
,
2919 struct i40e_aqc_query_switching_comp_ets_config_resp
*bw_data
,
2920 struct i40e_asq_cmd_details
*cmd_details
)
2922 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2923 i40e_aqc_opc_query_switching_comp_ets_config
,
2928 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
2929 * @hw: pointer to the hw struct
2930 * @seid: seid of the VSI or switching component connected to Physical Port
2931 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
2932 * @cmd_details: pointer to command details structure or NULL
2934 i40e_status
i40e_aq_query_port_ets_config(struct i40e_hw
*hw
,
2936 struct i40e_aqc_query_port_ets_config_resp
*bw_data
,
2937 struct i40e_asq_cmd_details
*cmd_details
)
2939 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2940 i40e_aqc_opc_query_port_ets_config
,
2945 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
2946 * @hw: pointer to the hw struct
2947 * @seid: seid of the switching component
2948 * @bw_data: Buffer to hold switching component's BW configuration
2949 * @cmd_details: pointer to command details structure or NULL
2951 i40e_status
i40e_aq_query_switch_comp_bw_config(struct i40e_hw
*hw
,
2953 struct i40e_aqc_query_switching_comp_bw_config_resp
*bw_data
,
2954 struct i40e_asq_cmd_details
*cmd_details
)
2956 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
2957 i40e_aqc_opc_query_switching_comp_bw_config
,
2962 * i40e_validate_filter_settings
2963 * @hw: pointer to the hardware structure
2964 * @settings: Filter control settings
2966 * Check and validate the filter control settings passed.
2967 * The function checks for the valid filter/context sizes being
2968 * passed for FCoE and PE.
2970 * Returns 0 if the values passed are valid and within
2971 * range else returns an error.
2973 static i40e_status
i40e_validate_filter_settings(struct i40e_hw
*hw
,
2974 struct i40e_filter_control_settings
*settings
)
2976 u32 fcoe_cntx_size
, fcoe_filt_size
;
2977 u32 pe_cntx_size
, pe_filt_size
;
2981 /* Validate FCoE settings passed */
2982 switch (settings
->fcoe_filt_num
) {
2983 case I40E_HASH_FILTER_SIZE_1K
:
2984 case I40E_HASH_FILTER_SIZE_2K
:
2985 case I40E_HASH_FILTER_SIZE_4K
:
2986 case I40E_HASH_FILTER_SIZE_8K
:
2987 case I40E_HASH_FILTER_SIZE_16K
:
2988 case I40E_HASH_FILTER_SIZE_32K
:
2989 fcoe_filt_size
= I40E_HASH_FILTER_BASE_SIZE
;
2990 fcoe_filt_size
<<= (u32
)settings
->fcoe_filt_num
;
2993 return I40E_ERR_PARAM
;
2996 switch (settings
->fcoe_cntx_num
) {
2997 case I40E_DMA_CNTX_SIZE_512
:
2998 case I40E_DMA_CNTX_SIZE_1K
:
2999 case I40E_DMA_CNTX_SIZE_2K
:
3000 case I40E_DMA_CNTX_SIZE_4K
:
3001 fcoe_cntx_size
= I40E_DMA_CNTX_BASE_SIZE
;
3002 fcoe_cntx_size
<<= (u32
)settings
->fcoe_cntx_num
;
3005 return I40E_ERR_PARAM
;
3008 /* Validate PE settings passed */
3009 switch (settings
->pe_filt_num
) {
3010 case I40E_HASH_FILTER_SIZE_1K
:
3011 case I40E_HASH_FILTER_SIZE_2K
:
3012 case I40E_HASH_FILTER_SIZE_4K
:
3013 case I40E_HASH_FILTER_SIZE_8K
:
3014 case I40E_HASH_FILTER_SIZE_16K
:
3015 case I40E_HASH_FILTER_SIZE_32K
:
3016 case I40E_HASH_FILTER_SIZE_64K
:
3017 case I40E_HASH_FILTER_SIZE_128K
:
3018 case I40E_HASH_FILTER_SIZE_256K
:
3019 case I40E_HASH_FILTER_SIZE_512K
:
3020 case I40E_HASH_FILTER_SIZE_1M
:
3021 pe_filt_size
= I40E_HASH_FILTER_BASE_SIZE
;
3022 pe_filt_size
<<= (u32
)settings
->pe_filt_num
;
3025 return I40E_ERR_PARAM
;
3028 switch (settings
->pe_cntx_num
) {
3029 case I40E_DMA_CNTX_SIZE_512
:
3030 case I40E_DMA_CNTX_SIZE_1K
:
3031 case I40E_DMA_CNTX_SIZE_2K
:
3032 case I40E_DMA_CNTX_SIZE_4K
:
3033 case I40E_DMA_CNTX_SIZE_8K
:
3034 case I40E_DMA_CNTX_SIZE_16K
:
3035 case I40E_DMA_CNTX_SIZE_32K
:
3036 case I40E_DMA_CNTX_SIZE_64K
:
3037 case I40E_DMA_CNTX_SIZE_128K
:
3038 case I40E_DMA_CNTX_SIZE_256K
:
3039 pe_cntx_size
= I40E_DMA_CNTX_BASE_SIZE
;
3040 pe_cntx_size
<<= (u32
)settings
->pe_cntx_num
;
3043 return I40E_ERR_PARAM
;
3046 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3047 val
= rd32(hw
, I40E_GLHMC_FCOEFMAX
);
3048 fcoe_fmax
= (val
& I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK
)
3049 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT
;
3050 if (fcoe_filt_size
+ fcoe_cntx_size
> fcoe_fmax
)
3051 return I40E_ERR_INVALID_SIZE
;
3057 * i40e_set_filter_control
3058 * @hw: pointer to the hardware structure
3059 * @settings: Filter control settings
3061 * Set the Queue Filters for PE/FCoE and enable filters required
3062 * for a single PF. It is expected that these settings are programmed
3063 * at the driver initialization time.
3065 i40e_status
i40e_set_filter_control(struct i40e_hw
*hw
,
3066 struct i40e_filter_control_settings
*settings
)
3068 i40e_status ret
= 0;
3069 u32 hash_lut_size
= 0;
3073 return I40E_ERR_PARAM
;
3075 /* Validate the input settings */
3076 ret
= i40e_validate_filter_settings(hw
, settings
);
3080 /* Read the PF Queue Filter control register */
3081 val
= rd32(hw
, I40E_PFQF_CTL_0
);
3083 /* Program required PE hash buckets for the PF */
3084 val
&= ~I40E_PFQF_CTL_0_PEHSIZE_MASK
;
3085 val
|= ((u32
)settings
->pe_filt_num
<< I40E_PFQF_CTL_0_PEHSIZE_SHIFT
) &
3086 I40E_PFQF_CTL_0_PEHSIZE_MASK
;
3087 /* Program required PE contexts for the PF */
3088 val
&= ~I40E_PFQF_CTL_0_PEDSIZE_MASK
;
3089 val
|= ((u32
)settings
->pe_cntx_num
<< I40E_PFQF_CTL_0_PEDSIZE_SHIFT
) &
3090 I40E_PFQF_CTL_0_PEDSIZE_MASK
;
3092 /* Program required FCoE hash buckets for the PF */
3093 val
&= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK
;
3094 val
|= ((u32
)settings
->fcoe_filt_num
<<
3095 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT
) &
3096 I40E_PFQF_CTL_0_PFFCHSIZE_MASK
;
3097 /* Program required FCoE DDP contexts for the PF */
3098 val
&= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK
;
3099 val
|= ((u32
)settings
->fcoe_cntx_num
<<
3100 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT
) &
3101 I40E_PFQF_CTL_0_PFFCDSIZE_MASK
;
3103 /* Program Hash LUT size for the PF */
3104 val
&= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK
;
3105 if (settings
->hash_lut_size
== I40E_HASH_LUT_SIZE_512
)
3107 val
|= (hash_lut_size
<< I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT
) &
3108 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK
;
3110 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3111 if (settings
->enable_fdir
)
3112 val
|= I40E_PFQF_CTL_0_FD_ENA_MASK
;
3113 if (settings
->enable_ethtype
)
3114 val
|= I40E_PFQF_CTL_0_ETYPE_ENA_MASK
;
3115 if (settings
->enable_macvlan
)
3116 val
|= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK
;
3118 wr32(hw
, I40E_PFQF_CTL_0
, val
);
3124 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3125 * @hw: pointer to the hw struct
3126 * @mac_addr: MAC address to use in the filter
3127 * @ethtype: Ethertype to use in the filter
3128 * @flags: Flags that needs to be applied to the filter
3129 * @vsi_seid: seid of the control VSI
3130 * @queue: VSI queue number to send the packet to
3131 * @is_add: Add control packet filter if True else remove
3132 * @stats: Structure to hold information on control filter counts
3133 * @cmd_details: pointer to command details structure or NULL
3135 * This command will Add or Remove control packet filter for a control VSI.
3136 * In return it will update the total number of perfect filter count in
3139 i40e_status
i40e_aq_add_rem_control_packet_filter(struct i40e_hw
*hw
,
3140 u8
*mac_addr
, u16 ethtype
, u16 flags
,
3141 u16 vsi_seid
, u16 queue
, bool is_add
,
3142 struct i40e_control_filter_stats
*stats
,
3143 struct i40e_asq_cmd_details
*cmd_details
)
3145 struct i40e_aq_desc desc
;
3146 struct i40e_aqc_add_remove_control_packet_filter
*cmd
=
3147 (struct i40e_aqc_add_remove_control_packet_filter
*)
3149 struct i40e_aqc_add_remove_control_packet_filter_completion
*resp
=
3150 (struct i40e_aqc_add_remove_control_packet_filter_completion
*)
3155 return I40E_ERR_PARAM
;
3158 i40e_fill_default_direct_cmd_desc(&desc
,
3159 i40e_aqc_opc_add_control_packet_filter
);
3160 cmd
->queue
= cpu_to_le16(queue
);
3162 i40e_fill_default_direct_cmd_desc(&desc
,
3163 i40e_aqc_opc_remove_control_packet_filter
);
3167 memcpy(cmd
->mac
, mac_addr
, ETH_ALEN
);
3169 cmd
->etype
= cpu_to_le16(ethtype
);
3170 cmd
->flags
= cpu_to_le16(flags
);
3171 cmd
->seid
= cpu_to_le16(vsi_seid
);
3173 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3175 if (!status
&& stats
) {
3176 stats
->mac_etype_used
= le16_to_cpu(resp
->mac_etype_used
);
3177 stats
->etype_used
= le16_to_cpu(resp
->etype_used
);
3178 stats
->mac_etype_free
= le16_to_cpu(resp
->mac_etype_free
);
3179 stats
->etype_free
= le16_to_cpu(resp
->etype_free
);
3186 * i40e_set_pci_config_data - store PCI bus info
3187 * @hw: pointer to hardware structure
3188 * @link_status: the link status word from PCI config space
3190 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3192 void i40e_set_pci_config_data(struct i40e_hw
*hw
, u16 link_status
)
3194 hw
->bus
.type
= i40e_bus_type_pci_express
;
3196 switch (link_status
& PCI_EXP_LNKSTA_NLW
) {
3197 case PCI_EXP_LNKSTA_NLW_X1
:
3198 hw
->bus
.width
= i40e_bus_width_pcie_x1
;
3200 case PCI_EXP_LNKSTA_NLW_X2
:
3201 hw
->bus
.width
= i40e_bus_width_pcie_x2
;
3203 case PCI_EXP_LNKSTA_NLW_X4
:
3204 hw
->bus
.width
= i40e_bus_width_pcie_x4
;
3206 case PCI_EXP_LNKSTA_NLW_X8
:
3207 hw
->bus
.width
= i40e_bus_width_pcie_x8
;
3210 hw
->bus
.width
= i40e_bus_width_unknown
;
3214 switch (link_status
& PCI_EXP_LNKSTA_CLS
) {
3215 case PCI_EXP_LNKSTA_CLS_2_5GB
:
3216 hw
->bus
.speed
= i40e_bus_speed_2500
;
3218 case PCI_EXP_LNKSTA_CLS_5_0GB
:
3219 hw
->bus
.speed
= i40e_bus_speed_5000
;
3221 case PCI_EXP_LNKSTA_CLS_8_0GB
:
3222 hw
->bus
.speed
= i40e_bus_speed_8000
;
3225 hw
->bus
.speed
= i40e_bus_speed_unknown
;