projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
31
32 /**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40 {
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
45 case I40E_DEV_ID_SFP_XL710:
46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_A:
48 case I40E_DEV_ID_KX_B:
49 case I40E_DEV_ID_KX_C:
50 case I40E_DEV_ID_QSFP_A:
51 case I40E_DEV_ID_QSFP_B:
52 case I40E_DEV_ID_QSFP_C:
53 case I40E_DEV_ID_10G_BASE_T:
54 hw->mac.type = I40E_MAC_XL710;
55 break;
56 case I40E_DEV_ID_VF:
57 case I40E_DEV_ID_VF_HV:
58 hw->mac.type = I40E_MAC_VF;
59 break;
60 default:
61 hw->mac.type = I40E_MAC_GENERIC;
62 break;
63 }
64 } else {
65 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
66 }
67
68 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
69 hw->mac.type, status);
70 return status;
71 }
72
73 /**
74 * i40e_debug_aq
75 * @hw: debug mask related to admin queue
76 * @mask: debug mask
77 * @desc: pointer to admin queue descriptor
78 * @buffer: pointer to command buffer
79 * @buf_len: max length of buffer
80 *
81 * Dumps debug log about adminq command with descriptor contents.
82 **/
83 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
84 void *buffer, u16 buf_len)
85 {
86 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
87 u16 len = le16_to_cpu(aq_desc->datalen);
88 u8 *aq_buffer = (u8 *)buffer;
89 u32 data[4];
90 u32 i = 0;
91
92 if ((!(mask & hw->debug_mask)) || (desc == NULL))
93 return;
94
95 i40e_debug(hw, mask,
96 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
97 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
98 aq_desc->retval);
99 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
100 aq_desc->cookie_high, aq_desc->cookie_low);
101 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
102 aq_desc->params.internal.param0,
103 aq_desc->params.internal.param1);
104 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
105 aq_desc->params.external.addr_high,
106 aq_desc->params.external.addr_low);
107
108 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
109 memset(data, 0, sizeof(data));
110 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
111 if (buf_len < len)
112 len = buf_len;
113 for (i = 0; i < len; i++) {
114 data[((i % 16) / 4)] |=
115 ((u32)aq_buffer[i]) << (8 * (i % 4));
116 if ((i % 16) == 15) {
117 i40e_debug(hw, mask,
118 "\t0x%04X %08X %08X %08X %08X\n",
119 i - 15, data[0], data[1], data[2],
120 data[3]);
121 memset(data, 0, sizeof(data));
122 }
123 }
124 if ((i % 16) != 0)
125 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
126 i - (i % 16), data[0], data[1], data[2],
127 data[3]);
128 }
129 }
130
131 /**
132 * i40e_check_asq_alive
133 * @hw: pointer to the hw struct
134 *
135 * Returns true if Queue is enabled else false.
136 **/
137 bool i40e_check_asq_alive(struct i40e_hw *hw)
138 {
139 if (hw->aq.asq.len)
140 return !!(rd32(hw, hw->aq.asq.len) &
141 I40E_PF_ATQLEN_ATQENABLE_MASK);
142 else
143 return false;
144 }
145
146 /**
147 * i40e_aq_queue_shutdown
148 * @hw: pointer to the hw struct
149 * @unloading: is the driver unloading itself
150 *
151 * Tell the Firmware that we're shutting down the AdminQ and whether
152 * or not the driver is unloading as well.
153 **/
154 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
155 bool unloading)
156 {
157 struct i40e_aq_desc desc;
158 struct i40e_aqc_queue_shutdown *cmd =
159 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
160 i40e_status status;
161
162 i40e_fill_default_direct_cmd_desc(&desc,
163 i40e_aqc_opc_queue_shutdown);
164
165 if (unloading)
166 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
167 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
168
169 return status;
170 }
171
172 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
173 * hardware to a bit-field that can be used by SW to more easily determine the
174 * packet type.
175 *
176 * Macros are used to shorten the table lines and make this table human
177 * readable.
178 *
179 * We store the PTYPE in the top byte of the bit field - this is just so that
180 * we can check that the table doesn't have a row missing, as the index into
181 * the table should be the PTYPE.
182 *
183 * Typical work flow:
184 *
185 * IF NOT i40e_ptype_lookup[ptype].known
186 * THEN
187 * Packet is unknown
188 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
189 * Use the rest of the fields to look at the tunnels, inner protocols, etc
190 * ELSE
191 * Use the enum i40e_rx_l2_ptype to decode the packet type
192 * ENDIF
193 */
194
195 /* macro to make the table lines short */
196 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
197 { PTYPE, \
198 1, \
199 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
200 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
201 I40E_RX_PTYPE_##OUTER_FRAG, \
202 I40E_RX_PTYPE_TUNNEL_##T, \
203 I40E_RX_PTYPE_TUNNEL_END_##TE, \
204 I40E_RX_PTYPE_##TEF, \
205 I40E_RX_PTYPE_INNER_PROT_##I, \
206 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
207
208 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
209 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
210
211 /* shorter macros makes the table fit but are terse */
212 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
213 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
214 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
215
216 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
217 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
218 /* L2 Packet types */
219 I40E_PTT_UNUSED_ENTRY(0),
220 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
221 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
222 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
223 I40E_PTT_UNUSED_ENTRY(4),
224 I40E_PTT_UNUSED_ENTRY(5),
225 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
226 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
227 I40E_PTT_UNUSED_ENTRY(8),
228 I40E_PTT_UNUSED_ENTRY(9),
229 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
230 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
231 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
232 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
233 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
234 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
235 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
236 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
237 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
238 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
239 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
240 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
241
242 /* Non Tunneled IPv4 */
243 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
244 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
245 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
246 I40E_PTT_UNUSED_ENTRY(25),
247 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
248 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
249 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
250
251 /* IPv4 --> IPv4 */
252 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
253 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
254 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
255 I40E_PTT_UNUSED_ENTRY(32),
256 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
257 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
258 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
259
260 /* IPv4 --> IPv6 */
261 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
262 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
263 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
264 I40E_PTT_UNUSED_ENTRY(39),
265 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
266 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
267 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
268
269 /* IPv4 --> GRE/NAT */
270 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
271
272 /* IPv4 --> GRE/NAT --> IPv4 */
273 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
274 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
275 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
276 I40E_PTT_UNUSED_ENTRY(47),
277 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
278 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
279 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
280
281 /* IPv4 --> GRE/NAT --> IPv6 */
282 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
283 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
284 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
285 I40E_PTT_UNUSED_ENTRY(54),
286 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
287 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
288 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
289
290 /* IPv4 --> GRE/NAT --> MAC */
291 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
292
293 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
294 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
295 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
296 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
297 I40E_PTT_UNUSED_ENTRY(62),
298 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
299 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
300 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
301
302 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
303 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
304 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
305 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
306 I40E_PTT_UNUSED_ENTRY(69),
307 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
308 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
309 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
310
311 /* IPv4 --> GRE/NAT --> MAC/VLAN */
312 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
313
314 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
315 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
316 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
317 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
318 I40E_PTT_UNUSED_ENTRY(77),
319 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
320 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
321 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
322
323 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
324 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
325 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
326 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
327 I40E_PTT_UNUSED_ENTRY(84),
328 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
329 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
330 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
331
332 /* Non Tunneled IPv6 */
333 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
334 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
335 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
336 I40E_PTT_UNUSED_ENTRY(91),
337 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
338 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
339 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
340
341 /* IPv6 --> IPv4 */
342 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
343 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
344 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
345 I40E_PTT_UNUSED_ENTRY(98),
346 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
347 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
348 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
349
350 /* IPv6 --> IPv6 */
351 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
352 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
353 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
354 I40E_PTT_UNUSED_ENTRY(105),
355 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
356 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
357 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
358
359 /* IPv6 --> GRE/NAT */
360 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
361
362 /* IPv6 --> GRE/NAT -> IPv4 */
363 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
364 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
365 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
366 I40E_PTT_UNUSED_ENTRY(113),
367 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
368 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
369 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
370
371 /* IPv6 --> GRE/NAT -> IPv6 */
372 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
373 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
374 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
375 I40E_PTT_UNUSED_ENTRY(120),
376 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
377 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
378 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
379
380 /* IPv6 --> GRE/NAT -> MAC */
381 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
382
383 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
384 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
385 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
386 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
387 I40E_PTT_UNUSED_ENTRY(128),
388 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
389 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
390 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
391
392 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
393 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
394 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
395 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
396 I40E_PTT_UNUSED_ENTRY(135),
397 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
398 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
399 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
400
401 /* IPv6 --> GRE/NAT -> MAC/VLAN */
402 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
403
404 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
405 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
406 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
407 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
408 I40E_PTT_UNUSED_ENTRY(143),
409 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
410 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
411 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
412
413 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
414 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
415 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
416 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
417 I40E_PTT_UNUSED_ENTRY(150),
418 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
419 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
420 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
421
422 /* unused entries */
423 I40E_PTT_UNUSED_ENTRY(154),
424 I40E_PTT_UNUSED_ENTRY(155),
425 I40E_PTT_UNUSED_ENTRY(156),
426 I40E_PTT_UNUSED_ENTRY(157),
427 I40E_PTT_UNUSED_ENTRY(158),
428 I40E_PTT_UNUSED_ENTRY(159),
429
430 I40E_PTT_UNUSED_ENTRY(160),
431 I40E_PTT_UNUSED_ENTRY(161),
432 I40E_PTT_UNUSED_ENTRY(162),
433 I40E_PTT_UNUSED_ENTRY(163),
434 I40E_PTT_UNUSED_ENTRY(164),
435 I40E_PTT_UNUSED_ENTRY(165),
436 I40E_PTT_UNUSED_ENTRY(166),
437 I40E_PTT_UNUSED_ENTRY(167),
438 I40E_PTT_UNUSED_ENTRY(168),
439 I40E_PTT_UNUSED_ENTRY(169),
440
441 I40E_PTT_UNUSED_ENTRY(170),
442 I40E_PTT_UNUSED_ENTRY(171),
443 I40E_PTT_UNUSED_ENTRY(172),
444 I40E_PTT_UNUSED_ENTRY(173),
445 I40E_PTT_UNUSED_ENTRY(174),
446 I40E_PTT_UNUSED_ENTRY(175),
447 I40E_PTT_UNUSED_ENTRY(176),
448 I40E_PTT_UNUSED_ENTRY(177),
449 I40E_PTT_UNUSED_ENTRY(178),
450 I40E_PTT_UNUSED_ENTRY(179),
451
452 I40E_PTT_UNUSED_ENTRY(180),
453 I40E_PTT_UNUSED_ENTRY(181),
454 I40E_PTT_UNUSED_ENTRY(182),
455 I40E_PTT_UNUSED_ENTRY(183),
456 I40E_PTT_UNUSED_ENTRY(184),
457 I40E_PTT_UNUSED_ENTRY(185),
458 I40E_PTT_UNUSED_ENTRY(186),
459 I40E_PTT_UNUSED_ENTRY(187),
460 I40E_PTT_UNUSED_ENTRY(188),
461 I40E_PTT_UNUSED_ENTRY(189),
462
463 I40E_PTT_UNUSED_ENTRY(190),
464 I40E_PTT_UNUSED_ENTRY(191),
465 I40E_PTT_UNUSED_ENTRY(192),
466 I40E_PTT_UNUSED_ENTRY(193),
467 I40E_PTT_UNUSED_ENTRY(194),
468 I40E_PTT_UNUSED_ENTRY(195),
469 I40E_PTT_UNUSED_ENTRY(196),
470 I40E_PTT_UNUSED_ENTRY(197),
471 I40E_PTT_UNUSED_ENTRY(198),
472 I40E_PTT_UNUSED_ENTRY(199),
473
474 I40E_PTT_UNUSED_ENTRY(200),
475 I40E_PTT_UNUSED_ENTRY(201),
476 I40E_PTT_UNUSED_ENTRY(202),
477 I40E_PTT_UNUSED_ENTRY(203),
478 I40E_PTT_UNUSED_ENTRY(204),
479 I40E_PTT_UNUSED_ENTRY(205),
480 I40E_PTT_UNUSED_ENTRY(206),
481 I40E_PTT_UNUSED_ENTRY(207),
482 I40E_PTT_UNUSED_ENTRY(208),
483 I40E_PTT_UNUSED_ENTRY(209),
484
485 I40E_PTT_UNUSED_ENTRY(210),
486 I40E_PTT_UNUSED_ENTRY(211),
487 I40E_PTT_UNUSED_ENTRY(212),
488 I40E_PTT_UNUSED_ENTRY(213),
489 I40E_PTT_UNUSED_ENTRY(214),
490 I40E_PTT_UNUSED_ENTRY(215),
491 I40E_PTT_UNUSED_ENTRY(216),
492 I40E_PTT_UNUSED_ENTRY(217),
493 I40E_PTT_UNUSED_ENTRY(218),
494 I40E_PTT_UNUSED_ENTRY(219),
495
496 I40E_PTT_UNUSED_ENTRY(220),
497 I40E_PTT_UNUSED_ENTRY(221),
498 I40E_PTT_UNUSED_ENTRY(222),
499 I40E_PTT_UNUSED_ENTRY(223),
500 I40E_PTT_UNUSED_ENTRY(224),
501 I40E_PTT_UNUSED_ENTRY(225),
502 I40E_PTT_UNUSED_ENTRY(226),
503 I40E_PTT_UNUSED_ENTRY(227),
504 I40E_PTT_UNUSED_ENTRY(228),
505 I40E_PTT_UNUSED_ENTRY(229),
506
507 I40E_PTT_UNUSED_ENTRY(230),
508 I40E_PTT_UNUSED_ENTRY(231),
509 I40E_PTT_UNUSED_ENTRY(232),
510 I40E_PTT_UNUSED_ENTRY(233),
511 I40E_PTT_UNUSED_ENTRY(234),
512 I40E_PTT_UNUSED_ENTRY(235),
513 I40E_PTT_UNUSED_ENTRY(236),
514 I40E_PTT_UNUSED_ENTRY(237),
515 I40E_PTT_UNUSED_ENTRY(238),
516 I40E_PTT_UNUSED_ENTRY(239),
517
518 I40E_PTT_UNUSED_ENTRY(240),
519 I40E_PTT_UNUSED_ENTRY(241),
520 I40E_PTT_UNUSED_ENTRY(242),
521 I40E_PTT_UNUSED_ENTRY(243),
522 I40E_PTT_UNUSED_ENTRY(244),
523 I40E_PTT_UNUSED_ENTRY(245),
524 I40E_PTT_UNUSED_ENTRY(246),
525 I40E_PTT_UNUSED_ENTRY(247),
526 I40E_PTT_UNUSED_ENTRY(248),
527 I40E_PTT_UNUSED_ENTRY(249),
528
529 I40E_PTT_UNUSED_ENTRY(250),
530 I40E_PTT_UNUSED_ENTRY(251),
531 I40E_PTT_UNUSED_ENTRY(252),
532 I40E_PTT_UNUSED_ENTRY(253),
533 I40E_PTT_UNUSED_ENTRY(254),
534 I40E_PTT_UNUSED_ENTRY(255)
535 };
536
537
538 /**
539 * i40e_init_shared_code - Initialize the shared code
540 * @hw: pointer to hardware structure
541 *
542 * This assigns the MAC type and PHY code and inits the NVM.
543 * Does not touch the hardware. This function must be called prior to any
544 * other function in the shared code. The i40e_hw structure should be
545 * memset to 0 prior to calling this function. The following fields in
546 * hw structure should be filled in prior to calling this function:
547 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
548 * subsystem_vendor_id, and revision_id
549 **/
550 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
551 {
552 i40e_status status = 0;
553 u32 port, ari, func_rid;
554
555 i40e_set_mac_type(hw);
556
557 switch (hw->mac.type) {
558 case I40E_MAC_XL710:
559 break;
560 default:
561 return I40E_ERR_DEVICE_NOT_SUPPORTED;
562 }
563
564 hw->phy.get_link_info = true;
565
566 /* Determine port number and PF number*/
567 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
568 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
569 hw->port = (u8)port;
570 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
571 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
572 func_rid = rd32(hw, I40E_PF_FUNC_RID);
573 if (ari)
574 hw->pf_id = (u8)(func_rid & 0xff);
575 else
576 hw->pf_id = (u8)(func_rid & 0x7);
577
578 status = i40e_init_nvm(hw);
579 return status;
580 }
581
582 /**
583 * i40e_aq_mac_address_read - Retrieve the MAC addresses
584 * @hw: pointer to the hw struct
585 * @flags: a return indicator of what addresses were added to the addr store
586 * @addrs: the requestor's mac addr store
587 * @cmd_details: pointer to command details structure or NULL
588 **/
589 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
590 u16 *flags,
591 struct i40e_aqc_mac_address_read_data *addrs,
592 struct i40e_asq_cmd_details *cmd_details)
593 {
594 struct i40e_aq_desc desc;
595 struct i40e_aqc_mac_address_read *cmd_data =
596 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
597 i40e_status status;
598
599 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
600 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
601
602 status = i40e_asq_send_command(hw, &desc, addrs,
603 sizeof(*addrs), cmd_details);
604 *flags = le16_to_cpu(cmd_data->command_flags);
605
606 return status;
607 }
608
609 /**
610 * i40e_aq_mac_address_write - Change the MAC addresses
611 * @hw: pointer to the hw struct
612 * @flags: indicates which MAC to be written
613 * @mac_addr: address to write
614 * @cmd_details: pointer to command details structure or NULL
615 **/
616 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
617 u16 flags, u8 *mac_addr,
618 struct i40e_asq_cmd_details *cmd_details)
619 {
620 struct i40e_aq_desc desc;
621 struct i40e_aqc_mac_address_write *cmd_data =
622 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
623 i40e_status status;
624
625 i40e_fill_default_direct_cmd_desc(&desc,
626 i40e_aqc_opc_mac_address_write);
627 cmd_data->command_flags = cpu_to_le16(flags);
628 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
629 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
630 ((u32)mac_addr[3] << 16) |
631 ((u32)mac_addr[4] << 8) |
632 mac_addr[5]);
633
634 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
635
636 return status;
637 }
638
639 /**
640 * i40e_get_mac_addr - get MAC address
641 * @hw: pointer to the HW structure
642 * @mac_addr: pointer to MAC address
643 *
644 * Reads the adapter's MAC address from register
645 **/
646 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
647 {
648 struct i40e_aqc_mac_address_read_data addrs;
649 i40e_status status;
650 u16 flags = 0;
651
652 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
653
654 if (flags & I40E_AQC_LAN_ADDR_VALID)
655 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
656
657 return status;
658 }
659
660 /**
661 * i40e_get_port_mac_addr - get Port MAC address
662 * @hw: pointer to the HW structure
663 * @mac_addr: pointer to Port MAC address
664 *
665 * Reads the adapter's Port MAC address
666 **/
667 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
668 {
669 struct i40e_aqc_mac_address_read_data addrs;
670 i40e_status status;
671 u16 flags = 0;
672
673 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
674 if (status)
675 return status;
676
677 if (flags & I40E_AQC_PORT_ADDR_VALID)
678 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
679 else
680 status = I40E_ERR_INVALID_MAC_ADDR;
681
682 return status;
683 }
684
685 /**
686 * i40e_pre_tx_queue_cfg - pre tx queue configure
687 * @hw: pointer to the HW structure
688 * @queue: target pf queue index
689 * @enable: state change request
690 *
691 * Handles hw requirement to indicate intention to enable
692 * or disable target queue.
693 **/
694 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
695 {
696 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
697 u32 reg_block = 0;
698 u32 reg_val;
699
700 if (abs_queue_idx >= 128) {
701 reg_block = abs_queue_idx / 128;
702 abs_queue_idx %= 128;
703 }
704
705 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
706 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
707 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
708
709 if (enable)
710 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
711 else
712 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
713
714 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
715 }
716 #ifdef I40E_FCOE
717
718 /**
719 * i40e_get_san_mac_addr - get SAN MAC address
720 * @hw: pointer to the HW structure
721 * @mac_addr: pointer to SAN MAC address
722 *
723 * Reads the adapter's SAN MAC address from NVM
724 **/
725 i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
726 {
727 struct i40e_aqc_mac_address_read_data addrs;
728 i40e_status status;
729 u16 flags = 0;
730
731 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
732 if (status)
733 return status;
734
735 if (flags & I40E_AQC_SAN_ADDR_VALID)
736 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac));
737 else
738 status = I40E_ERR_INVALID_MAC_ADDR;
739
740 return status;
741 }
742 #endif
743
744 /**
745 * i40e_read_pba_string - Reads part number string from EEPROM
746 * @hw: pointer to hardware structure
747 * @pba_num: stores the part number string from the EEPROM
748 * @pba_num_size: part number string buffer length
749 *
750 * Reads the part number string from the EEPROM.
751 **/
752 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
753 u32 pba_num_size)
754 {
755 i40e_status status = 0;
756 u16 pba_word = 0;
757 u16 pba_size = 0;
758 u16 pba_ptr = 0;
759 u16 i = 0;
760
761 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
762 if (status || (pba_word != 0xFAFA)) {
763 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
764 return status;
765 }
766
767 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
768 if (status) {
769 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
770 return status;
771 }
772
773 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
774 if (status) {
775 hw_dbg(hw, "Failed to read PBA Block size.\n");
776 return status;
777 }
778
779 /* Subtract one to get PBA word count (PBA Size word is included in
780 * total size)
781 */
782 pba_size--;
783 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
784 hw_dbg(hw, "Buffer to small for PBA data.\n");
785 return I40E_ERR_PARAM;
786 }
787
788 for (i = 0; i < pba_size; i++) {
789 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
790 if (status) {
791 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
792 return status;
793 }
794
795 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
796 pba_num[(i * 2) + 1] = pba_word & 0xFF;
797 }
798 pba_num[(pba_size * 2)] = '\0';
799
800 return status;
801 }
802
803 /**
804 * i40e_get_media_type - Gets media type
805 * @hw: pointer to the hardware structure
806 **/
807 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
808 {
809 enum i40e_media_type media;
810
811 switch (hw->phy.link_info.phy_type) {
812 case I40E_PHY_TYPE_10GBASE_SR:
813 case I40E_PHY_TYPE_10GBASE_LR:
814 case I40E_PHY_TYPE_1000BASE_SX:
815 case I40E_PHY_TYPE_1000BASE_LX:
816 case I40E_PHY_TYPE_40GBASE_SR4:
817 case I40E_PHY_TYPE_40GBASE_LR4:
818 media = I40E_MEDIA_TYPE_FIBER;
819 break;
820 case I40E_PHY_TYPE_100BASE_TX:
821 case I40E_PHY_TYPE_1000BASE_T:
822 case I40E_PHY_TYPE_10GBASE_T:
823 media = I40E_MEDIA_TYPE_BASET;
824 break;
825 case I40E_PHY_TYPE_10GBASE_CR1_CU:
826 case I40E_PHY_TYPE_40GBASE_CR4_CU:
827 case I40E_PHY_TYPE_10GBASE_CR1:
828 case I40E_PHY_TYPE_40GBASE_CR4:
829 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
830 media = I40E_MEDIA_TYPE_DA;
831 break;
832 case I40E_PHY_TYPE_1000BASE_KX:
833 case I40E_PHY_TYPE_10GBASE_KX4:
834 case I40E_PHY_TYPE_10GBASE_KR:
835 case I40E_PHY_TYPE_40GBASE_KR4:
836 media = I40E_MEDIA_TYPE_BACKPLANE;
837 break;
838 case I40E_PHY_TYPE_SGMII:
839 case I40E_PHY_TYPE_XAUI:
840 case I40E_PHY_TYPE_XFI:
841 case I40E_PHY_TYPE_XLAUI:
842 case I40E_PHY_TYPE_XLPPI:
843 default:
844 media = I40E_MEDIA_TYPE_UNKNOWN;
845 break;
846 }
847
848 return media;
849 }
850
851 #define I40E_PF_RESET_WAIT_COUNT_A0 200
852 #define I40E_PF_RESET_WAIT_COUNT 110
853 /**
854 * i40e_pf_reset - Reset the PF
855 * @hw: pointer to the hardware structure
856 *
857 * Assuming someone else has triggered a global reset,
858 * assure the global reset is complete and then reset the PF
859 **/
860 i40e_status i40e_pf_reset(struct i40e_hw *hw)
861 {
862 u32 cnt = 0;
863 u32 cnt1 = 0;
864 u32 reg = 0;
865 u32 grst_del;
866
867 /* Poll for Global Reset steady state in case of recent GRST.
868 * The grst delay value is in 100ms units, and we'll wait a
869 * couple counts longer to be sure we don't just miss the end.
870 */
871 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
872 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
873 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
874 for (cnt = 0; cnt < grst_del + 2; cnt++) {
875 reg = rd32(hw, I40E_GLGEN_RSTAT);
876 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
877 break;
878 msleep(100);
879 }
880 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
881 hw_dbg(hw, "Global reset polling failed to complete.\n");
882 return I40E_ERR_RESET_FAILED;
883 }
884
885 /* Now Wait for the FW to be ready */
886 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
887 reg = rd32(hw, I40E_GLNVM_ULD);
888 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
889 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
890 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
891 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
892 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
893 break;
894 }
895 usleep_range(10000, 20000);
896 }
897 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
898 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
899 hw_dbg(hw, "wait for FW Reset complete timedout\n");
900 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
901 return I40E_ERR_RESET_FAILED;
902 }
903
904 /* If there was a Global Reset in progress when we got here,
905 * we don't need to do the PF Reset
906 */
907 if (!cnt) {
908 if (hw->revision_id == 0)
909 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
910 else
911 cnt = I40E_PF_RESET_WAIT_COUNT;
912 reg = rd32(hw, I40E_PFGEN_CTRL);
913 wr32(hw, I40E_PFGEN_CTRL,
914 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
915 for (; cnt; cnt--) {
916 reg = rd32(hw, I40E_PFGEN_CTRL);
917 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
918 break;
919 usleep_range(1000, 2000);
920 }
921 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
922 hw_dbg(hw, "PF reset polling failed to complete.\n");
923 return I40E_ERR_RESET_FAILED;
924 }
925 }
926
927 i40e_clear_pxe_mode(hw);
928
929 return 0;
930 }
931
932 /**
933 * i40e_clear_hw - clear out any left over hw state
934 * @hw: pointer to the hw struct
935 *
936 * Clear queues and interrupts, typically called at init time,
937 * but after the capabilities have been found so we know how many
938 * queues and msix vectors have been allocated.
939 **/
940 void i40e_clear_hw(struct i40e_hw *hw)
941 {
942 u32 num_queues, base_queue;
943 u32 num_pf_int;
944 u32 num_vf_int;
945 u32 num_vfs;
946 u32 i, j;
947 u32 val;
948 u32 eol = 0x7ff;
949
950 /* get number of interrupts, queues, and vfs */
951 val = rd32(hw, I40E_GLPCI_CNF2);
952 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
953 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
954 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
955 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
956
957 val = rd32(hw, I40E_PFLAN_QALLOC);
958 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
959 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
960 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
961 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
962 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
963 num_queues = (j - base_queue) + 1;
964 else
965 num_queues = 0;
966
967 val = rd32(hw, I40E_PF_VT_PFALLOC);
968 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
969 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
970 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
971 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
972 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
973 num_vfs = (j - i) + 1;
974 else
975 num_vfs = 0;
976
977 /* stop all the interrupts */
978 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
979 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
980 for (i = 0; i < num_pf_int - 2; i++)
981 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
982
983 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
984 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
985 wr32(hw, I40E_PFINT_LNKLST0, val);
986 for (i = 0; i < num_pf_int - 2; i++)
987 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
988 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
989 for (i = 0; i < num_vfs; i++)
990 wr32(hw, I40E_VPINT_LNKLST0(i), val);
991 for (i = 0; i < num_vf_int - 2; i++)
992 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
993
994 /* warn the HW of the coming Tx disables */
995 for (i = 0; i < num_queues; i++) {
996 u32 abs_queue_idx = base_queue + i;
997 u32 reg_block = 0;
998
999 if (abs_queue_idx >= 128) {
1000 reg_block = abs_queue_idx / 128;
1001 abs_queue_idx %= 128;
1002 }
1003
1004 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1005 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1006 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1007 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1008
1009 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1010 }
1011 udelay(400);
1012
1013 /* stop all the queues */
1014 for (i = 0; i < num_queues; i++) {
1015 wr32(hw, I40E_QINT_TQCTL(i), 0);
1016 wr32(hw, I40E_QTX_ENA(i), 0);
1017 wr32(hw, I40E_QINT_RQCTL(i), 0);
1018 wr32(hw, I40E_QRX_ENA(i), 0);
1019 }
1020
1021 /* short wait for all queue disables to settle */
1022 udelay(50);
1023 }
1024
1025 /**
1026 * i40e_clear_pxe_mode - clear pxe operations mode
1027 * @hw: pointer to the hw struct
1028 *
1029 * Make sure all PXE mode settings are cleared, including things
1030 * like descriptor fetch/write-back mode.
1031 **/
1032 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1033 {
1034 u32 reg;
1035
1036 if (i40e_check_asq_alive(hw))
1037 i40e_aq_clear_pxe_mode(hw, NULL);
1038
1039 /* Clear single descriptor fetch/write-back mode */
1040 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1041
1042 if (hw->revision_id == 0) {
1043 /* As a work around clear PXE_MODE instead of setting it */
1044 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1045 } else {
1046 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1047 }
1048 }
1049
1050 /**
1051 * i40e_led_is_mine - helper to find matching led
1052 * @hw: pointer to the hw struct
1053 * @idx: index into GPIO registers
1054 *
1055 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1056 */
1057 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1058 {
1059 u32 gpio_val = 0;
1060 u32 port;
1061
1062 if (!hw->func_caps.led[idx])
1063 return 0;
1064
1065 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1066 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1067 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1068
1069 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1070 * if it is not our port then ignore
1071 */
1072 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1073 (port != hw->port))
1074 return 0;
1075
1076 return gpio_val;
1077 }
1078
1079 #define I40E_LED0 22
1080 #define I40E_LINK_ACTIVITY 0xC
1081
1082 /**
1083 * i40e_led_get - return current on/off mode
1084 * @hw: pointer to the hw struct
1085 *
1086 * The value returned is the 'mode' field as defined in the
1087 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1088 * values are variations of possible behaviors relating to
1089 * blink, link, and wire.
1090 **/
1091 u32 i40e_led_get(struct i40e_hw *hw)
1092 {
1093 u32 mode = 0;
1094 int i;
1095
1096 /* as per the documentation GPIO 22-29 are the LED
1097 * GPIO pins named LED0..LED7
1098 */
1099 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1100 u32 gpio_val = i40e_led_is_mine(hw, i);
1101
1102 if (!gpio_val)
1103 continue;
1104
1105 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1106 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1107 break;
1108 }
1109
1110 return mode;
1111 }
1112
1113 /**
1114 * i40e_led_set - set new on/off mode
1115 * @hw: pointer to the hw struct
1116 * @mode: 0=off, 0xf=on (else see manual for mode details)
1117 * @blink: true if the LED should blink when on, false if steady
1118 *
1119 * if this function is used to turn on the blink it should
1120 * be used to disable the blink when restoring the original state.
1121 **/
1122 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1123 {
1124 int i;
1125
1126 if (mode & 0xfffffff0)
1127 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1128
1129 /* as per the documentation GPIO 22-29 are the LED
1130 * GPIO pins named LED0..LED7
1131 */
1132 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1133 u32 gpio_val = i40e_led_is_mine(hw, i);
1134
1135 if (!gpio_val)
1136 continue;
1137
1138 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1139 /* this & is a bit of paranoia, but serves as a range check */
1140 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1141 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1142
1143 if (mode == I40E_LINK_ACTIVITY)
1144 blink = false;
1145
1146 if (blink)
1147 gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1148 else
1149 gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1150
1151 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1152 break;
1153 }
1154 }
1155
1156 /* Admin command wrappers */
1157
1158 /**
1159 * i40e_aq_get_phy_capabilities
1160 * @hw: pointer to the hw struct
1161 * @abilities: structure for PHY capabilities to be filled
1162 * @qualified_modules: report Qualified Modules
1163 * @report_init: report init capabilities (active are default)
1164 * @cmd_details: pointer to command details structure or NULL
1165 *
1166 * Returns the various PHY abilities supported on the Port.
1167 **/
1168 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1169 bool qualified_modules, bool report_init,
1170 struct i40e_aq_get_phy_abilities_resp *abilities,
1171 struct i40e_asq_cmd_details *cmd_details)
1172 {
1173 struct i40e_aq_desc desc;
1174 i40e_status status;
1175 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1176
1177 if (!abilities)
1178 return I40E_ERR_PARAM;
1179
1180 i40e_fill_default_direct_cmd_desc(&desc,
1181 i40e_aqc_opc_get_phy_abilities);
1182
1183 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1184 if (abilities_size > I40E_AQ_LARGE_BUF)
1185 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1186
1187 if (qualified_modules)
1188 desc.params.external.param0 |=
1189 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1190
1191 if (report_init)
1192 desc.params.external.param0 |=
1193 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1194
1195 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1196 cmd_details);
1197
1198 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1199 status = I40E_ERR_UNKNOWN_PHY;
1200
1201 return status;
1202 }
1203
1204 /**
1205 * i40e_aq_set_phy_config
1206 * @hw: pointer to the hw struct
1207 * @config: structure with PHY configuration to be set
1208 * @cmd_details: pointer to command details structure or NULL
1209 *
1210 * Set the various PHY configuration parameters
1211 * supported on the Port.One or more of the Set PHY config parameters may be
1212 * ignored in an MFP mode as the PF may not have the privilege to set some
1213 * of the PHY Config parameters. This status will be indicated by the
1214 * command response.
1215 **/
1216 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1217 struct i40e_aq_set_phy_config *config,
1218 struct i40e_asq_cmd_details *cmd_details)
1219 {
1220 struct i40e_aq_desc desc;
1221 struct i40e_aq_set_phy_config *cmd =
1222 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1223 enum i40e_status_code status;
1224
1225 if (!config)
1226 return I40E_ERR_PARAM;
1227
1228 i40e_fill_default_direct_cmd_desc(&desc,
1229 i40e_aqc_opc_set_phy_config);
1230
1231 *cmd = *config;
1232
1233 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1234
1235 return status;
1236 }
1237
1238 /**
1239 * i40e_set_fc
1240 * @hw: pointer to the hw struct
1241 *
1242 * Set the requested flow control mode using set_phy_config.
1243 **/
1244 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1245 bool atomic_restart)
1246 {
1247 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1248 struct i40e_aq_get_phy_abilities_resp abilities;
1249 struct i40e_aq_set_phy_config config;
1250 enum i40e_status_code status;
1251 u8 pause_mask = 0x0;
1252
1253 *aq_failures = 0x0;
1254
1255 switch (fc_mode) {
1256 case I40E_FC_FULL:
1257 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1258 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1259 break;
1260 case I40E_FC_RX_PAUSE:
1261 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1262 break;
1263 case I40E_FC_TX_PAUSE:
1264 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1265 break;
1266 default:
1267 break;
1268 }
1269
1270 /* Get the current phy config */
1271 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1272 NULL);
1273 if (status) {
1274 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1275 return status;
1276 }
1277
1278 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1279 /* clear the old pause settings */
1280 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1281 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1282 /* set the new abilities */
1283 config.abilities |= pause_mask;
1284 /* If the abilities have changed, then set the new config */
1285 if (config.abilities != abilities.abilities) {
1286 /* Auto restart link so settings take effect */
1287 if (atomic_restart)
1288 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1289 /* Copy over all the old settings */
1290 config.phy_type = abilities.phy_type;
1291 config.link_speed = abilities.link_speed;
1292 config.eee_capability = abilities.eee_capability;
1293 config.eeer = abilities.eeer_val;
1294 config.low_power_ctrl = abilities.d3_lpan;
1295 status = i40e_aq_set_phy_config(hw, &config, NULL);
1296
1297 if (status)
1298 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1299 }
1300 /* Update the link info */
1301 status = i40e_update_link_info(hw, true);
1302 if (status) {
1303 /* Wait a little bit (on 40G cards it sometimes takes a really
1304 * long time for link to come back from the atomic reset)
1305 * and try once more
1306 */
1307 msleep(1000);
1308 status = i40e_update_link_info(hw, true);
1309 }
1310 if (status)
1311 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1312
1313 return status;
1314 }
1315
1316 /**
1317 * i40e_aq_clear_pxe_mode
1318 * @hw: pointer to the hw struct
1319 * @cmd_details: pointer to command details structure or NULL
1320 *
1321 * Tell the firmware that the driver is taking over from PXE
1322 **/
1323 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1324 struct i40e_asq_cmd_details *cmd_details)
1325 {
1326 i40e_status status;
1327 struct i40e_aq_desc desc;
1328 struct i40e_aqc_clear_pxe *cmd =
1329 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1330
1331 i40e_fill_default_direct_cmd_desc(&desc,
1332 i40e_aqc_opc_clear_pxe_mode);
1333
1334 cmd->rx_cnt = 0x2;
1335
1336 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1337
1338 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1339
1340 return status;
1341 }
1342
1343 /**
1344 * i40e_aq_set_link_restart_an
1345 * @hw: pointer to the hw struct
1346 * @enable_link: if true: enable link, if false: disable link
1347 * @cmd_details: pointer to command details structure or NULL
1348 *
1349 * Sets up the link and restarts the Auto-Negotiation over the link.
1350 **/
1351 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1352 bool enable_link,
1353 struct i40e_asq_cmd_details *cmd_details)
1354 {
1355 struct i40e_aq_desc desc;
1356 struct i40e_aqc_set_link_restart_an *cmd =
1357 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1358 i40e_status status;
1359
1360 i40e_fill_default_direct_cmd_desc(&desc,
1361 i40e_aqc_opc_set_link_restart_an);
1362
1363 cmd->command = I40E_AQ_PHY_RESTART_AN;
1364 if (enable_link)
1365 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1366 else
1367 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1368
1369 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1370
1371 return status;
1372 }
1373
1374 /**
1375 * i40e_aq_get_link_info
1376 * @hw: pointer to the hw struct
1377 * @enable_lse: enable/disable LinkStatusEvent reporting
1378 * @link: pointer to link status structure - optional
1379 * @cmd_details: pointer to command details structure or NULL
1380 *
1381 * Returns the link status of the adapter.
1382 **/
1383 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1384 bool enable_lse, struct i40e_link_status *link,
1385 struct i40e_asq_cmd_details *cmd_details)
1386 {
1387 struct i40e_aq_desc desc;
1388 struct i40e_aqc_get_link_status *resp =
1389 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1390 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1391 i40e_status status;
1392 bool tx_pause, rx_pause;
1393 u16 command_flags;
1394
1395 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1396
1397 if (enable_lse)
1398 command_flags = I40E_AQ_LSE_ENABLE;
1399 else
1400 command_flags = I40E_AQ_LSE_DISABLE;
1401 resp->command_flags = cpu_to_le16(command_flags);
1402
1403 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1404
1405 if (status)
1406 goto aq_get_link_info_exit;
1407
1408 /* save off old link status information */
1409 hw->phy.link_info_old = *hw_link_info;
1410
1411 /* update link status */
1412 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1413 hw->phy.media_type = i40e_get_media_type(hw);
1414 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1415 hw_link_info->link_info = resp->link_info;
1416 hw_link_info->an_info = resp->an_info;
1417 hw_link_info->ext_info = resp->ext_info;
1418 hw_link_info->loopback = resp->loopback;
1419 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1420 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1421
1422 /* update fc info */
1423 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1424 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1425 if (tx_pause & rx_pause)
1426 hw->fc.current_mode = I40E_FC_FULL;
1427 else if (tx_pause)
1428 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1429 else if (rx_pause)
1430 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1431 else
1432 hw->fc.current_mode = I40E_FC_NONE;
1433
1434 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1435 hw_link_info->crc_enable = true;
1436 else
1437 hw_link_info->crc_enable = false;
1438
1439 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1440 hw_link_info->lse_enable = true;
1441 else
1442 hw_link_info->lse_enable = false;
1443
1444 /* save link status information */
1445 if (link)
1446 *link = *hw_link_info;
1447
1448 /* flag cleared so helper functions don't call AQ again */
1449 hw->phy.get_link_info = false;
1450
1451 aq_get_link_info_exit:
1452 return status;
1453 }
1454
1455 /**
1456 * i40e_update_link_info
1457 * @hw: pointer to the hw struct
1458 * @enable_lse: enable/disable LinkStatusEvent reporting
1459 *
1460 * Returns the link status of the adapter
1461 **/
1462 i40e_status i40e_update_link_info(struct i40e_hw *hw, bool enable_lse)
1463 {
1464 struct i40e_aq_get_phy_abilities_resp abilities;
1465 i40e_status status;
1466
1467 status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL);
1468 if (status)
1469 return status;
1470
1471 status = i40e_aq_get_phy_capabilities(hw, false, false,
1472 &abilities, NULL);
1473 if (status)
1474 return status;
1475
1476 if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED)
1477 hw->phy.link_info.an_enabled = true;
1478 else
1479 hw->phy.link_info.an_enabled = false;
1480
1481 return status;
1482 }
1483
1484 /**
1485 * i40e_aq_set_phy_int_mask
1486 * @hw: pointer to the hw struct
1487 * @mask: interrupt mask to be set
1488 * @cmd_details: pointer to command details structure or NULL
1489 *
1490 * Set link interrupt mask.
1491 **/
1492 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1493 u16 mask,
1494 struct i40e_asq_cmd_details *cmd_details)
1495 {
1496 struct i40e_aq_desc desc;
1497 struct i40e_aqc_set_phy_int_mask *cmd =
1498 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1499 i40e_status status;
1500
1501 i40e_fill_default_direct_cmd_desc(&desc,
1502 i40e_aqc_opc_set_phy_int_mask);
1503
1504 cmd->event_mask = cpu_to_le16(mask);
1505
1506 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1507
1508 return status;
1509 }
1510
1511 /**
1512 * i40e_aq_add_vsi
1513 * @hw: pointer to the hw struct
1514 * @vsi_ctx: pointer to a vsi context struct
1515 * @cmd_details: pointer to command details structure or NULL
1516 *
1517 * Add a VSI context to the hardware.
1518 **/
1519 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1520 struct i40e_vsi_context *vsi_ctx,
1521 struct i40e_asq_cmd_details *cmd_details)
1522 {
1523 struct i40e_aq_desc desc;
1524 struct i40e_aqc_add_get_update_vsi *cmd =
1525 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1526 struct i40e_aqc_add_get_update_vsi_completion *resp =
1527 (struct i40e_aqc_add_get_update_vsi_completion *)
1528 &desc.params.raw;
1529 i40e_status status;
1530
1531 i40e_fill_default_direct_cmd_desc(&desc,
1532 i40e_aqc_opc_add_vsi);
1533
1534 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1535 cmd->connection_type = vsi_ctx->connection_type;
1536 cmd->vf_id = vsi_ctx->vf_num;
1537 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1538
1539 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1540
1541 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1542 sizeof(vsi_ctx->info), cmd_details);
1543
1544 if (status)
1545 goto aq_add_vsi_exit;
1546
1547 vsi_ctx->seid = le16_to_cpu(resp->seid);
1548 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1549 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1550 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1551
1552 aq_add_vsi_exit:
1553 return status;
1554 }
1555
1556 /**
1557 * i40e_aq_set_vsi_unicast_promiscuous
1558 * @hw: pointer to the hw struct
1559 * @seid: vsi number
1560 * @set: set unicast promiscuous enable/disable
1561 * @cmd_details: pointer to command details structure or NULL
1562 **/
1563 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1564 u16 seid, bool set,
1565 struct i40e_asq_cmd_details *cmd_details)
1566 {
1567 struct i40e_aq_desc desc;
1568 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1569 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1570 i40e_status status;
1571 u16 flags = 0;
1572
1573 i40e_fill_default_direct_cmd_desc(&desc,
1574 i40e_aqc_opc_set_vsi_promiscuous_modes);
1575
1576 if (set)
1577 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1578
1579 cmd->promiscuous_flags = cpu_to_le16(flags);
1580
1581 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1582
1583 cmd->seid = cpu_to_le16(seid);
1584 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1585
1586 return status;
1587 }
1588
1589 /**
1590 * i40e_aq_set_vsi_multicast_promiscuous
1591 * @hw: pointer to the hw struct
1592 * @seid: vsi number
1593 * @set: set multicast promiscuous enable/disable
1594 * @cmd_details: pointer to command details structure or NULL
1595 **/
1596 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1597 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1598 {
1599 struct i40e_aq_desc desc;
1600 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1601 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1602 i40e_status status;
1603 u16 flags = 0;
1604
1605 i40e_fill_default_direct_cmd_desc(&desc,
1606 i40e_aqc_opc_set_vsi_promiscuous_modes);
1607
1608 if (set)
1609 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1610
1611 cmd->promiscuous_flags = cpu_to_le16(flags);
1612
1613 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1614
1615 cmd->seid = cpu_to_le16(seid);
1616 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1617
1618 return status;
1619 }
1620
1621 /**
1622 * i40e_aq_set_vsi_broadcast
1623 * @hw: pointer to the hw struct
1624 * @seid: vsi number
1625 * @set_filter: true to set filter, false to clear filter
1626 * @cmd_details: pointer to command details structure or NULL
1627 *
1628 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1629 **/
1630 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1631 u16 seid, bool set_filter,
1632 struct i40e_asq_cmd_details *cmd_details)
1633 {
1634 struct i40e_aq_desc desc;
1635 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1636 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1637 i40e_status status;
1638
1639 i40e_fill_default_direct_cmd_desc(&desc,
1640 i40e_aqc_opc_set_vsi_promiscuous_modes);
1641
1642 if (set_filter)
1643 cmd->promiscuous_flags
1644 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1645 else
1646 cmd->promiscuous_flags
1647 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1648
1649 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1650 cmd->seid = cpu_to_le16(seid);
1651 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1652
1653 return status;
1654 }
1655
1656 /**
1657 * i40e_get_vsi_params - get VSI configuration info
1658 * @hw: pointer to the hw struct
1659 * @vsi_ctx: pointer to a vsi context struct
1660 * @cmd_details: pointer to command details structure or NULL
1661 **/
1662 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
1663 struct i40e_vsi_context *vsi_ctx,
1664 struct i40e_asq_cmd_details *cmd_details)
1665 {
1666 struct i40e_aq_desc desc;
1667 struct i40e_aqc_add_get_update_vsi *cmd =
1668 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1669 struct i40e_aqc_add_get_update_vsi_completion *resp =
1670 (struct i40e_aqc_add_get_update_vsi_completion *)
1671 &desc.params.raw;
1672 i40e_status status;
1673
1674 i40e_fill_default_direct_cmd_desc(&desc,
1675 i40e_aqc_opc_get_vsi_parameters);
1676
1677 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
1678
1679 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1680
1681 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1682 sizeof(vsi_ctx->info), NULL);
1683
1684 if (status)
1685 goto aq_get_vsi_params_exit;
1686
1687 vsi_ctx->seid = le16_to_cpu(resp->seid);
1688 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1689 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1690 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1691
1692 aq_get_vsi_params_exit:
1693 return status;
1694 }
1695
1696 /**
1697 * i40e_aq_update_vsi_params
1698 * @hw: pointer to the hw struct
1699 * @vsi_ctx: pointer to a vsi context struct
1700 * @cmd_details: pointer to command details structure or NULL
1701 *
1702 * Update a VSI context.
1703 **/
1704 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
1705 struct i40e_vsi_context *vsi_ctx,
1706 struct i40e_asq_cmd_details *cmd_details)
1707 {
1708 struct i40e_aq_desc desc;
1709 struct i40e_aqc_add_get_update_vsi *cmd =
1710 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1711 i40e_status status;
1712
1713 i40e_fill_default_direct_cmd_desc(&desc,
1714 i40e_aqc_opc_update_vsi_parameters);
1715 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
1716
1717 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1718
1719 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1720 sizeof(vsi_ctx->info), cmd_details);
1721
1722 return status;
1723 }
1724
1725 /**
1726 * i40e_aq_get_switch_config
1727 * @hw: pointer to the hardware structure
1728 * @buf: pointer to the result buffer
1729 * @buf_size: length of input buffer
1730 * @start_seid: seid to start for the report, 0 == beginning
1731 * @cmd_details: pointer to command details structure or NULL
1732 *
1733 * Fill the buf with switch configuration returned from AdminQ command
1734 **/
1735 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
1736 struct i40e_aqc_get_switch_config_resp *buf,
1737 u16 buf_size, u16 *start_seid,
1738 struct i40e_asq_cmd_details *cmd_details)
1739 {
1740 struct i40e_aq_desc desc;
1741 struct i40e_aqc_switch_seid *scfg =
1742 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1743 i40e_status status;
1744
1745 i40e_fill_default_direct_cmd_desc(&desc,
1746 i40e_aqc_opc_get_switch_config);
1747 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1748 if (buf_size > I40E_AQ_LARGE_BUF)
1749 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1750 scfg->seid = cpu_to_le16(*start_seid);
1751
1752 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1753 *start_seid = le16_to_cpu(scfg->seid);
1754
1755 return status;
1756 }
1757
1758 /**
1759 * i40e_aq_get_firmware_version
1760 * @hw: pointer to the hw struct
1761 * @fw_major_version: firmware major version
1762 * @fw_minor_version: firmware minor version
1763 * @api_major_version: major queue version
1764 * @api_minor_version: minor queue version
1765 * @cmd_details: pointer to command details structure or NULL
1766 *
1767 * Get the firmware version from the admin queue commands
1768 **/
1769 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
1770 u16 *fw_major_version, u16 *fw_minor_version,
1771 u16 *api_major_version, u16 *api_minor_version,
1772 struct i40e_asq_cmd_details *cmd_details)
1773 {
1774 struct i40e_aq_desc desc;
1775 struct i40e_aqc_get_version *resp =
1776 (struct i40e_aqc_get_version *)&desc.params.raw;
1777 i40e_status status;
1778
1779 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1780
1781 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1782
1783 if (!status) {
1784 if (fw_major_version != NULL)
1785 *fw_major_version = le16_to_cpu(resp->fw_major);
1786 if (fw_minor_version != NULL)
1787 *fw_minor_version = le16_to_cpu(resp->fw_minor);
1788 if (api_major_version != NULL)
1789 *api_major_version = le16_to_cpu(resp->api_major);
1790 if (api_minor_version != NULL)
1791 *api_minor_version = le16_to_cpu(resp->api_minor);
1792 }
1793
1794 return status;
1795 }
1796
1797 /**
1798 * i40e_aq_send_driver_version
1799 * @hw: pointer to the hw struct
1800 * @dv: driver's major, minor version
1801 * @cmd_details: pointer to command details structure or NULL
1802 *
1803 * Send the driver version to the firmware
1804 **/
1805 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
1806 struct i40e_driver_version *dv,
1807 struct i40e_asq_cmd_details *cmd_details)
1808 {
1809 struct i40e_aq_desc desc;
1810 struct i40e_aqc_driver_version *cmd =
1811 (struct i40e_aqc_driver_version *)&desc.params.raw;
1812 i40e_status status;
1813 u16 len;
1814
1815 if (dv == NULL)
1816 return I40E_ERR_PARAM;
1817
1818 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1819
1820 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
1821 cmd->driver_major_ver = dv->major_version;
1822 cmd->driver_minor_ver = dv->minor_version;
1823 cmd->driver_build_ver = dv->build_version;
1824 cmd->driver_subbuild_ver = dv->subbuild_version;
1825
1826 len = 0;
1827 while (len < sizeof(dv->driver_string) &&
1828 (dv->driver_string[len] < 0x80) &&
1829 dv->driver_string[len])
1830 len++;
1831 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1832 len, cmd_details);
1833
1834 return status;
1835 }
1836
1837 /**
1838 * i40e_get_link_status - get status of the HW network link
1839 * @hw: pointer to the hw struct
1840 *
1841 * Returns true if link is up, false if link is down.
1842 *
1843 * Side effect: LinkStatusEvent reporting becomes enabled
1844 **/
1845 bool i40e_get_link_status(struct i40e_hw *hw)
1846 {
1847 i40e_status status = 0;
1848 bool link_status = false;
1849
1850 if (hw->phy.get_link_info) {
1851 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1852
1853 if (status)
1854 goto i40e_get_link_status_exit;
1855 }
1856
1857 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1858
1859 i40e_get_link_status_exit:
1860 return link_status;
1861 }
1862
1863 /**
1864 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1865 * @hw: pointer to the hw struct
1866 * @uplink_seid: the MAC or other gizmo SEID
1867 * @downlink_seid: the VSI SEID
1868 * @enabled_tc: bitmap of TCs to be enabled
1869 * @default_port: true for default port VSI, false for control port
1870 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
1871 * @veb_seid: pointer to where to put the resulting VEB SEID
1872 * @cmd_details: pointer to command details structure or NULL
1873 *
1874 * This asks the FW to add a VEB between the uplink and downlink
1875 * elements. If the uplink SEID is 0, this will be a floating VEB.
1876 **/
1877 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
1878 u16 downlink_seid, u8 enabled_tc,
1879 bool default_port, bool enable_l2_filtering,
1880 u16 *veb_seid,
1881 struct i40e_asq_cmd_details *cmd_details)
1882 {
1883 struct i40e_aq_desc desc;
1884 struct i40e_aqc_add_veb *cmd =
1885 (struct i40e_aqc_add_veb *)&desc.params.raw;
1886 struct i40e_aqc_add_veb_completion *resp =
1887 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1888 i40e_status status;
1889 u16 veb_flags = 0;
1890
1891 /* SEIDs need to either both be set or both be 0 for floating VEB */
1892 if (!!uplink_seid != !!downlink_seid)
1893 return I40E_ERR_PARAM;
1894
1895 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1896
1897 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1898 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1899 cmd->enable_tcs = enabled_tc;
1900 if (!uplink_seid)
1901 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1902 if (default_port)
1903 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1904 else
1905 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
1906
1907 if (enable_l2_filtering)
1908 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1909
1910 cmd->veb_flags = cpu_to_le16(veb_flags);
1911
1912 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1913
1914 if (!status && veb_seid)
1915 *veb_seid = le16_to_cpu(resp->veb_seid);
1916
1917 return status;
1918 }
1919
1920 /**
1921 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1922 * @hw: pointer to the hw struct
1923 * @veb_seid: the SEID of the VEB to query
1924 * @switch_id: the uplink switch id
1925 * @floating: set to true if the VEB is floating
1926 * @statistic_index: index of the stats counter block for this VEB
1927 * @vebs_used: number of VEB's used by function
1928 * @vebs_free: total VEB's not reserved by any function
1929 * @cmd_details: pointer to command details structure or NULL
1930 *
1931 * This retrieves the parameters for a particular VEB, specified by
1932 * uplink_seid, and returns them to the caller.
1933 **/
1934 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1935 u16 veb_seid, u16 *switch_id,
1936 bool *floating, u16 *statistic_index,
1937 u16 *vebs_used, u16 *vebs_free,
1938 struct i40e_asq_cmd_details *cmd_details)
1939 {
1940 struct i40e_aq_desc desc;
1941 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1942 (struct i40e_aqc_get_veb_parameters_completion *)
1943 &desc.params.raw;
1944 i40e_status status;
1945
1946 if (veb_seid == 0)
1947 return I40E_ERR_PARAM;
1948
1949 i40e_fill_default_direct_cmd_desc(&desc,
1950 i40e_aqc_opc_get_veb_parameters);
1951 cmd_resp->seid = cpu_to_le16(veb_seid);
1952
1953 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1954 if (status)
1955 goto get_veb_exit;
1956
1957 if (switch_id)
1958 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1959 if (statistic_index)
1960 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1961 if (vebs_used)
1962 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1963 if (vebs_free)
1964 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1965 if (floating) {
1966 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1967 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1968 *floating = true;
1969 else
1970 *floating = false;
1971 }
1972
1973 get_veb_exit:
1974 return status;
1975 }
1976
1977 /**
1978 * i40e_aq_add_macvlan
1979 * @hw: pointer to the hw struct
1980 * @seid: VSI for the mac address
1981 * @mv_list: list of macvlans to be added
1982 * @count: length of the list
1983 * @cmd_details: pointer to command details structure or NULL
1984 *
1985 * Add MAC/VLAN addresses to the HW filtering
1986 **/
1987 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1988 struct i40e_aqc_add_macvlan_element_data *mv_list,
1989 u16 count, struct i40e_asq_cmd_details *cmd_details)
1990 {
1991 struct i40e_aq_desc desc;
1992 struct i40e_aqc_macvlan *cmd =
1993 (struct i40e_aqc_macvlan *)&desc.params.raw;
1994 i40e_status status;
1995 u16 buf_size;
1996
1997 if (count == 0 || !mv_list || !hw)
1998 return I40E_ERR_PARAM;
1999
2000 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
2001
2002 /* prep the rest of the request */
2003 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2004 cmd->num_addresses = cpu_to_le16(count);
2005 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2006 cmd->seid[1] = 0;
2007 cmd->seid[2] = 0;
2008
2009 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2010 if (buf_size > I40E_AQ_LARGE_BUF)
2011 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2012
2013 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2014 cmd_details);
2015
2016 return status;
2017 }
2018
2019 /**
2020 * i40e_aq_remove_macvlan
2021 * @hw: pointer to the hw struct
2022 * @seid: VSI for the mac address
2023 * @mv_list: list of macvlans to be removed
2024 * @count: length of the list
2025 * @cmd_details: pointer to command details structure or NULL
2026 *
2027 * Remove MAC/VLAN addresses from the HW filtering
2028 **/
2029 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2030 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2031 u16 count, struct i40e_asq_cmd_details *cmd_details)
2032 {
2033 struct i40e_aq_desc desc;
2034 struct i40e_aqc_macvlan *cmd =
2035 (struct i40e_aqc_macvlan *)&desc.params.raw;
2036 i40e_status status;
2037 u16 buf_size;
2038
2039 if (count == 0 || !mv_list || !hw)
2040 return I40E_ERR_PARAM;
2041
2042 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
2043
2044 /* prep the rest of the request */
2045 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2046 cmd->num_addresses = cpu_to_le16(count);
2047 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2048 cmd->seid[1] = 0;
2049 cmd->seid[2] = 0;
2050
2051 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2052 if (buf_size > I40E_AQ_LARGE_BUF)
2053 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2054
2055 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2056 cmd_details);
2057
2058 return status;
2059 }
2060
2061 /**
2062 * i40e_aq_send_msg_to_vf
2063 * @hw: pointer to the hardware structure
2064 * @vfid: vf id to send msg
2065 * @v_opcode: opcodes for VF-PF communication
2066 * @v_retval: return error code
2067 * @msg: pointer to the msg buffer
2068 * @msglen: msg length
2069 * @cmd_details: pointer to command details
2070 *
2071 * send msg to vf
2072 **/
2073 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2074 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2075 struct i40e_asq_cmd_details *cmd_details)
2076 {
2077 struct i40e_aq_desc desc;
2078 struct i40e_aqc_pf_vf_message *cmd =
2079 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2080 i40e_status status;
2081
2082 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2083 cmd->id = cpu_to_le32(vfid);
2084 desc.cookie_high = cpu_to_le32(v_opcode);
2085 desc.cookie_low = cpu_to_le32(v_retval);
2086 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2087 if (msglen) {
2088 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2089 I40E_AQ_FLAG_RD));
2090 if (msglen > I40E_AQ_LARGE_BUF)
2091 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2092 desc.datalen = cpu_to_le16(msglen);
2093 }
2094 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2095
2096 return status;
2097 }
2098
2099 /**
2100 * i40e_aq_debug_read_register
2101 * @hw: pointer to the hw struct
2102 * @reg_addr: register address
2103 * @reg_val: register value
2104 * @cmd_details: pointer to command details structure or NULL
2105 *
2106 * Read the register using the admin queue commands
2107 **/
2108 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2109 u32 reg_addr, u64 *reg_val,
2110 struct i40e_asq_cmd_details *cmd_details)
2111 {
2112 struct i40e_aq_desc desc;
2113 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2114 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2115 i40e_status status;
2116
2117 if (reg_val == NULL)
2118 return I40E_ERR_PARAM;
2119
2120 i40e_fill_default_direct_cmd_desc(&desc,
2121 i40e_aqc_opc_debug_read_reg);
2122
2123 cmd_resp->address = cpu_to_le32(reg_addr);
2124
2125 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2126
2127 if (!status) {
2128 *reg_val = ((u64)cmd_resp->value_high << 32) |
2129 (u64)cmd_resp->value_low;
2130 *reg_val = le64_to_cpu(*reg_val);
2131 }
2132
2133 return status;
2134 }
2135
2136 /**
2137 * i40e_aq_debug_write_register
2138 * @hw: pointer to the hw struct
2139 * @reg_addr: register address
2140 * @reg_val: register value
2141 * @cmd_details: pointer to command details structure or NULL
2142 *
2143 * Write to a register using the admin queue commands
2144 **/
2145 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2146 u32 reg_addr, u64 reg_val,
2147 struct i40e_asq_cmd_details *cmd_details)
2148 {
2149 struct i40e_aq_desc desc;
2150 struct i40e_aqc_debug_reg_read_write *cmd =
2151 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2152 i40e_status status;
2153
2154 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2155
2156 cmd->address = cpu_to_le32(reg_addr);
2157 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2158 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2159
2160 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2161
2162 return status;
2163 }
2164
2165 /**
2166 * i40e_aq_set_hmc_resource_profile
2167 * @hw: pointer to the hw struct
2168 * @profile: type of profile the HMC is to be set as
2169 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2170 * @cmd_details: pointer to command details structure or NULL
2171 *
2172 * set the HMC profile of the device.
2173 **/
2174 i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2175 enum i40e_aq_hmc_profile profile,
2176 u8 pe_vf_enabled_count,
2177 struct i40e_asq_cmd_details *cmd_details)
2178 {
2179 struct i40e_aq_desc desc;
2180 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2181 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2182 i40e_status status;
2183
2184 i40e_fill_default_direct_cmd_desc(&desc,
2185 i40e_aqc_opc_set_hmc_resource_profile);
2186
2187 cmd->pm_profile = (u8)profile;
2188 cmd->pe_vf_enabled = pe_vf_enabled_count;
2189
2190 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2191
2192 return status;
2193 }
2194
2195 /**
2196 * i40e_aq_request_resource
2197 * @hw: pointer to the hw struct
2198 * @resource: resource id
2199 * @access: access type
2200 * @sdp_number: resource number
2201 * @timeout: the maximum time in ms that the driver may hold the resource
2202 * @cmd_details: pointer to command details structure or NULL
2203 *
2204 * requests common resource using the admin queue commands
2205 **/
2206 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2207 enum i40e_aq_resources_ids resource,
2208 enum i40e_aq_resource_access_type access,
2209 u8 sdp_number, u64 *timeout,
2210 struct i40e_asq_cmd_details *cmd_details)
2211 {
2212 struct i40e_aq_desc desc;
2213 struct i40e_aqc_request_resource *cmd_resp =
2214 (struct i40e_aqc_request_resource *)&desc.params.raw;
2215 i40e_status status;
2216
2217 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2218
2219 cmd_resp->resource_id = cpu_to_le16(resource);
2220 cmd_resp->access_type = cpu_to_le16(access);
2221 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2222
2223 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2224 /* The completion specifies the maximum time in ms that the driver
2225 * may hold the resource in the Timeout field.
2226 * If the resource is held by someone else, the command completes with
2227 * busy return value and the timeout field indicates the maximum time
2228 * the current owner of the resource has to free it.
2229 */
2230 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2231 *timeout = le32_to_cpu(cmd_resp->timeout);
2232
2233 return status;
2234 }
2235
2236 /**
2237 * i40e_aq_release_resource
2238 * @hw: pointer to the hw struct
2239 * @resource: resource id
2240 * @sdp_number: resource number
2241 * @cmd_details: pointer to command details structure or NULL
2242 *
2243 * release common resource using the admin queue commands
2244 **/
2245 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2246 enum i40e_aq_resources_ids resource,
2247 u8 sdp_number,
2248 struct i40e_asq_cmd_details *cmd_details)
2249 {
2250 struct i40e_aq_desc desc;
2251 struct i40e_aqc_request_resource *cmd =
2252 (struct i40e_aqc_request_resource *)&desc.params.raw;
2253 i40e_status status;
2254
2255 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2256
2257 cmd->resource_id = cpu_to_le16(resource);
2258 cmd->resource_number = cpu_to_le32(sdp_number);
2259
2260 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2261
2262 return status;
2263 }
2264
2265 /**
2266 * i40e_aq_read_nvm
2267 * @hw: pointer to the hw struct
2268 * @module_pointer: module pointer location in words from the NVM beginning
2269 * @offset: byte offset from the module beginning
2270 * @length: length of the section to be read (in bytes from the offset)
2271 * @data: command buffer (size [bytes] = length)
2272 * @last_command: tells if this is the last command in a series
2273 * @cmd_details: pointer to command details structure or NULL
2274 *
2275 * Read the NVM using the admin queue commands
2276 **/
2277 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2278 u32 offset, u16 length, void *data,
2279 bool last_command,
2280 struct i40e_asq_cmd_details *cmd_details)
2281 {
2282 struct i40e_aq_desc desc;
2283 struct i40e_aqc_nvm_update *cmd =
2284 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2285 i40e_status status;
2286
2287 /* In offset the highest byte must be zeroed. */
2288 if (offset & 0xFF000000) {
2289 status = I40E_ERR_PARAM;
2290 goto i40e_aq_read_nvm_exit;
2291 }
2292
2293 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2294
2295 /* If this is the last command in a series, set the proper flag. */
2296 if (last_command)
2297 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2298 cmd->module_pointer = module_pointer;
2299 cmd->offset = cpu_to_le32(offset);
2300 cmd->length = cpu_to_le16(length);
2301
2302 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2303 if (length > I40E_AQ_LARGE_BUF)
2304 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2305
2306 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2307
2308 i40e_aq_read_nvm_exit:
2309 return status;
2310 }
2311
2312 /**
2313 * i40e_aq_erase_nvm
2314 * @hw: pointer to the hw struct
2315 * @module_pointer: module pointer location in words from the NVM beginning
2316 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2317 * @length: length of the section to be erased (expressed in 4 KB)
2318 * @last_command: tells if this is the last command in a series
2319 * @cmd_details: pointer to command details structure or NULL
2320 *
2321 * Erase the NVM sector using the admin queue commands
2322 **/
2323 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2324 u32 offset, u16 length, bool last_command,
2325 struct i40e_asq_cmd_details *cmd_details)
2326 {
2327 struct i40e_aq_desc desc;
2328 struct i40e_aqc_nvm_update *cmd =
2329 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2330 i40e_status status;
2331
2332 /* In offset the highest byte must be zeroed. */
2333 if (offset & 0xFF000000) {
2334 status = I40E_ERR_PARAM;
2335 goto i40e_aq_erase_nvm_exit;
2336 }
2337
2338 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2339
2340 /* If this is the last command in a series, set the proper flag. */
2341 if (last_command)
2342 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2343 cmd->module_pointer = module_pointer;
2344 cmd->offset = cpu_to_le32(offset);
2345 cmd->length = cpu_to_le16(length);
2346
2347 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2348
2349 i40e_aq_erase_nvm_exit:
2350 return status;
2351 }
2352
2353 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2354 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2355 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2356 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2357 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2358 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2359 #define I40E_DEV_FUNC_CAP_VF 0x13
2360 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2361 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2362 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2363 #define I40E_DEV_FUNC_CAP_VSI 0x17
2364 #define I40E_DEV_FUNC_CAP_DCB 0x18
2365 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2366 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
2367 #define I40E_DEV_FUNC_CAP_RSS 0x40
2368 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2369 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2370 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2371 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2372 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2373 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2374 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2375 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2376 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2377 #define I40E_DEV_FUNC_CAP_LED 0x61
2378 #define I40E_DEV_FUNC_CAP_SDP 0x62
2379 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2380
2381 /**
2382 * i40e_parse_discover_capabilities
2383 * @hw: pointer to the hw struct
2384 * @buff: pointer to a buffer containing device/function capability records
2385 * @cap_count: number of capability records in the list
2386 * @list_type_opc: type of capabilities list to parse
2387 *
2388 * Parse the device/function capabilities list.
2389 **/
2390 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2391 u32 cap_count,
2392 enum i40e_admin_queue_opc list_type_opc)
2393 {
2394 struct i40e_aqc_list_capabilities_element_resp *cap;
2395 u32 valid_functions, num_functions;
2396 u32 number, logical_id, phys_id;
2397 struct i40e_hw_capabilities *p;
2398 u32 i = 0;
2399 u16 id;
2400
2401 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2402
2403 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2404 p = &hw->dev_caps;
2405 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2406 p = &hw->func_caps;
2407 else
2408 return;
2409
2410 for (i = 0; i < cap_count; i++, cap++) {
2411 id = le16_to_cpu(cap->id);
2412 number = le32_to_cpu(cap->number);
2413 logical_id = le32_to_cpu(cap->logical_id);
2414 phys_id = le32_to_cpu(cap->phys_id);
2415
2416 switch (id) {
2417 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2418 p->switch_mode = number;
2419 break;
2420 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2421 p->management_mode = number;
2422 break;
2423 case I40E_DEV_FUNC_CAP_NPAR:
2424 p->npar_enable = number;
2425 break;
2426 case I40E_DEV_FUNC_CAP_OS2BMC:
2427 p->os2bmc = number;
2428 break;
2429 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2430 p->valid_functions = number;
2431 break;
2432 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2433 if (number == 1)
2434 p->sr_iov_1_1 = true;
2435 break;
2436 case I40E_DEV_FUNC_CAP_VF:
2437 p->num_vfs = number;
2438 p->vf_base_id = logical_id;
2439 break;
2440 case I40E_DEV_FUNC_CAP_VMDQ:
2441 if (number == 1)
2442 p->vmdq = true;
2443 break;
2444 case I40E_DEV_FUNC_CAP_802_1_QBG:
2445 if (number == 1)
2446 p->evb_802_1_qbg = true;
2447 break;
2448 case I40E_DEV_FUNC_CAP_802_1_QBH:
2449 if (number == 1)
2450 p->evb_802_1_qbh = true;
2451 break;
2452 case I40E_DEV_FUNC_CAP_VSI:
2453 p->num_vsis = number;
2454 break;
2455 case I40E_DEV_FUNC_CAP_DCB:
2456 if (number == 1) {
2457 p->dcb = true;
2458 p->enabled_tcmap = logical_id;
2459 p->maxtc = phys_id;
2460 }
2461 break;
2462 case I40E_DEV_FUNC_CAP_FCOE:
2463 if (number == 1)
2464 p->fcoe = true;
2465 break;
2466 case I40E_DEV_FUNC_CAP_ISCSI:
2467 if (number == 1)
2468 p->iscsi = true;
2469 break;
2470 case I40E_DEV_FUNC_CAP_RSS:
2471 p->rss = true;
2472 p->rss_table_size = number;
2473 p->rss_table_entry_width = logical_id;
2474 break;
2475 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2476 p->num_rx_qp = number;
2477 p->base_queue = phys_id;
2478 break;
2479 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2480 p->num_tx_qp = number;
2481 p->base_queue = phys_id;
2482 break;
2483 case I40E_DEV_FUNC_CAP_MSIX:
2484 p->num_msix_vectors = number;
2485 break;
2486 case I40E_DEV_FUNC_CAP_MSIX_VF:
2487 p->num_msix_vectors_vf = number;
2488 break;
2489 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2490 if (number == 1)
2491 p->mfp_mode_1 = true;
2492 break;
2493 case I40E_DEV_FUNC_CAP_CEM:
2494 if (number == 1)
2495 p->mgmt_cem = true;
2496 break;
2497 case I40E_DEV_FUNC_CAP_IWARP:
2498 if (number == 1)
2499 p->iwarp = true;
2500 break;
2501 case I40E_DEV_FUNC_CAP_LED:
2502 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2503 p->led[phys_id] = true;
2504 break;
2505 case I40E_DEV_FUNC_CAP_SDP:
2506 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2507 p->sdp[phys_id] = true;
2508 break;
2509 case I40E_DEV_FUNC_CAP_MDIO:
2510 if (number == 1) {
2511 p->mdio_port_num = phys_id;
2512 p->mdio_port_mode = logical_id;
2513 }
2514 break;
2515 case I40E_DEV_FUNC_CAP_IEEE_1588:
2516 if (number == 1)
2517 p->ieee_1588 = true;
2518 break;
2519 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2520 p->fd = true;
2521 p->fd_filters_guaranteed = number;
2522 p->fd_filters_best_effort = logical_id;
2523 break;
2524 default:
2525 break;
2526 }
2527 }
2528
2529 /* Software override ensuring FCoE is disabled if npar or mfp
2530 * mode because it is not supported in these modes.
2531 */
2532 if (p->npar_enable || p->mfp_mode_1)
2533 p->fcoe = false;
2534
2535 /* count the enabled ports (aka the "not disabled" ports) */
2536 hw->num_ports = 0;
2537 for (i = 0; i < 4; i++) {
2538 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
2539 u64 port_cfg = 0;
2540
2541 /* use AQ read to get the physical register offset instead
2542 * of the port relative offset
2543 */
2544 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
2545 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
2546 hw->num_ports++;
2547 }
2548
2549 valid_functions = p->valid_functions;
2550 num_functions = 0;
2551 while (valid_functions) {
2552 if (valid_functions & 1)
2553 num_functions++;
2554 valid_functions >>= 1;
2555 }
2556
2557 /* partition id is 1-based, and functions are evenly spread
2558 * across the ports as partitions
2559 */
2560 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
2561 hw->num_partitions = num_functions / hw->num_ports;
2562
2563 /* additional HW specific goodies that might
2564 * someday be HW version specific
2565 */
2566 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2567 }
2568
2569 /**
2570 * i40e_aq_discover_capabilities
2571 * @hw: pointer to the hw struct
2572 * @buff: a virtual buffer to hold the capabilities
2573 * @buff_size: Size of the virtual buffer
2574 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2575 * @list_type_opc: capabilities type to discover - pass in the command opcode
2576 * @cmd_details: pointer to command details structure or NULL
2577 *
2578 * Get the device capabilities descriptions from the firmware
2579 **/
2580 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
2581 void *buff, u16 buff_size, u16 *data_size,
2582 enum i40e_admin_queue_opc list_type_opc,
2583 struct i40e_asq_cmd_details *cmd_details)
2584 {
2585 struct i40e_aqc_list_capabilites *cmd;
2586 struct i40e_aq_desc desc;
2587 i40e_status status = 0;
2588
2589 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2590
2591 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2592 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2593 status = I40E_ERR_PARAM;
2594 goto exit;
2595 }
2596
2597 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2598
2599 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2600 if (buff_size > I40E_AQ_LARGE_BUF)
2601 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2602
2603 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2604 *data_size = le16_to_cpu(desc.datalen);
2605
2606 if (status)
2607 goto exit;
2608
2609 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
2610 list_type_opc);
2611
2612 exit:
2613 return status;
2614 }
2615
2616 /**
2617 * i40e_aq_update_nvm
2618 * @hw: pointer to the hw struct
2619 * @module_pointer: module pointer location in words from the NVM beginning
2620 * @offset: byte offset from the module beginning
2621 * @length: length of the section to be written (in bytes from the offset)
2622 * @data: command buffer (size [bytes] = length)
2623 * @last_command: tells if this is the last command in a series
2624 * @cmd_details: pointer to command details structure or NULL
2625 *
2626 * Update the NVM using the admin queue commands
2627 **/
2628 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2629 u32 offset, u16 length, void *data,
2630 bool last_command,
2631 struct i40e_asq_cmd_details *cmd_details)
2632 {
2633 struct i40e_aq_desc desc;
2634 struct i40e_aqc_nvm_update *cmd =
2635 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2636 i40e_status status;
2637
2638 /* In offset the highest byte must be zeroed. */
2639 if (offset & 0xFF000000) {
2640 status = I40E_ERR_PARAM;
2641 goto i40e_aq_update_nvm_exit;
2642 }
2643
2644 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2645
2646 /* If this is the last command in a series, set the proper flag. */
2647 if (last_command)
2648 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2649 cmd->module_pointer = module_pointer;
2650 cmd->offset = cpu_to_le32(offset);
2651 cmd->length = cpu_to_le16(length);
2652
2653 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2654 if (length > I40E_AQ_LARGE_BUF)
2655 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2656
2657 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2658
2659 i40e_aq_update_nvm_exit:
2660 return status;
2661 }
2662
2663 /**
2664 * i40e_aq_get_lldp_mib
2665 * @hw: pointer to the hw struct
2666 * @bridge_type: type of bridge requested
2667 * @mib_type: Local, Remote or both Local and Remote MIBs
2668 * @buff: pointer to a user supplied buffer to store the MIB block
2669 * @buff_size: size of the buffer (in bytes)
2670 * @local_len : length of the returned Local LLDP MIB
2671 * @remote_len: length of the returned Remote LLDP MIB
2672 * @cmd_details: pointer to command details structure or NULL
2673 *
2674 * Requests the complete LLDP MIB (entire packet).
2675 **/
2676 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2677 u8 mib_type, void *buff, u16 buff_size,
2678 u16 *local_len, u16 *remote_len,
2679 struct i40e_asq_cmd_details *cmd_details)
2680 {
2681 struct i40e_aq_desc desc;
2682 struct i40e_aqc_lldp_get_mib *cmd =
2683 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2684 struct i40e_aqc_lldp_get_mib *resp =
2685 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2686 i40e_status status;
2687
2688 if (buff_size == 0 || !buff)
2689 return I40E_ERR_PARAM;
2690
2691 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2692 /* Indirect Command */
2693 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2694
2695 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2696 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2697 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2698
2699 desc.datalen = cpu_to_le16(buff_size);
2700
2701 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2702 if (buff_size > I40E_AQ_LARGE_BUF)
2703 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2704
2705 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2706 if (!status) {
2707 if (local_len != NULL)
2708 *local_len = le16_to_cpu(resp->local_len);
2709 if (remote_len != NULL)
2710 *remote_len = le16_to_cpu(resp->remote_len);
2711 }
2712
2713 return status;
2714 }
2715
2716 /**
2717 * i40e_aq_cfg_lldp_mib_change_event
2718 * @hw: pointer to the hw struct
2719 * @enable_update: Enable or Disable event posting
2720 * @cmd_details: pointer to command details structure or NULL
2721 *
2722 * Enable or Disable posting of an event on ARQ when LLDP MIB
2723 * associated with the interface changes
2724 **/
2725 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2726 bool enable_update,
2727 struct i40e_asq_cmd_details *cmd_details)
2728 {
2729 struct i40e_aq_desc desc;
2730 struct i40e_aqc_lldp_update_mib *cmd =
2731 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2732 i40e_status status;
2733
2734 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2735
2736 if (!enable_update)
2737 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2738
2739 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2740
2741 return status;
2742 }
2743
2744 /**
2745 * i40e_aq_stop_lldp
2746 * @hw: pointer to the hw struct
2747 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2748 * @cmd_details: pointer to command details structure or NULL
2749 *
2750 * Stop or Shutdown the embedded LLDP Agent
2751 **/
2752 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
2753 struct i40e_asq_cmd_details *cmd_details)
2754 {
2755 struct i40e_aq_desc desc;
2756 struct i40e_aqc_lldp_stop *cmd =
2757 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
2758 i40e_status status;
2759
2760 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
2761
2762 if (shutdown_agent)
2763 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
2764
2765 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2766
2767 return status;
2768 }
2769
2770 /**
2771 * i40e_aq_start_lldp
2772 * @hw: pointer to the hw struct
2773 * @cmd_details: pointer to command details structure or NULL
2774 *
2775 * Start the embedded LLDP Agent on all ports.
2776 **/
2777 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
2778 struct i40e_asq_cmd_details *cmd_details)
2779 {
2780 struct i40e_aq_desc desc;
2781 struct i40e_aqc_lldp_start *cmd =
2782 (struct i40e_aqc_lldp_start *)&desc.params.raw;
2783 i40e_status status;
2784
2785 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
2786
2787 cmd->command = I40E_AQ_LLDP_AGENT_START;
2788
2789 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2790
2791 return status;
2792 }
2793
2794 /**
2795 * i40e_aq_get_cee_dcb_config
2796 * @hw: pointer to the hw struct
2797 * @buff: response buffer that stores CEE operational configuration
2798 * @buff_size: size of the buffer passed
2799 * @cmd_details: pointer to command details structure or NULL
2800 *
2801 * Get CEE DCBX mode operational configuration from firmware
2802 **/
2803 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
2804 void *buff, u16 buff_size,
2805 struct i40e_asq_cmd_details *cmd_details)
2806 {
2807 struct i40e_aq_desc desc;
2808 i40e_status status;
2809
2810 if (buff_size == 0 || !buff)
2811 return I40E_ERR_PARAM;
2812
2813 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
2814
2815 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2816 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
2817 cmd_details);
2818
2819 return status;
2820 }
2821
2822 /**
2823 * i40e_aq_add_udp_tunnel
2824 * @hw: pointer to the hw struct
2825 * @udp_port: the UDP port to add
2826 * @header_len: length of the tunneling header length in DWords
2827 * @protocol_index: protocol index type
2828 * @filter_index: pointer to filter index
2829 * @cmd_details: pointer to command details structure or NULL
2830 **/
2831 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
2832 u16 udp_port, u8 protocol_index,
2833 u8 *filter_index,
2834 struct i40e_asq_cmd_details *cmd_details)
2835 {
2836 struct i40e_aq_desc desc;
2837 struct i40e_aqc_add_udp_tunnel *cmd =
2838 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
2839 struct i40e_aqc_del_udp_tunnel_completion *resp =
2840 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
2841 i40e_status status;
2842
2843 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
2844
2845 cmd->udp_port = cpu_to_le16(udp_port);
2846 cmd->protocol_type = protocol_index;
2847
2848 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2849
2850 if (!status && filter_index)
2851 *filter_index = resp->index;
2852
2853 return status;
2854 }
2855
2856 /**
2857 * i40e_aq_del_udp_tunnel
2858 * @hw: pointer to the hw struct
2859 * @index: filter index
2860 * @cmd_details: pointer to command details structure or NULL
2861 **/
2862 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
2863 struct i40e_asq_cmd_details *cmd_details)
2864 {
2865 struct i40e_aq_desc desc;
2866 struct i40e_aqc_remove_udp_tunnel *cmd =
2867 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
2868 i40e_status status;
2869
2870 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
2871
2872 cmd->index = index;
2873
2874 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2875
2876 return status;
2877 }
2878
2879 /**
2880 * i40e_aq_delete_element - Delete switch element
2881 * @hw: pointer to the hw struct
2882 * @seid: the SEID to delete from the switch
2883 * @cmd_details: pointer to command details structure or NULL
2884 *
2885 * This deletes a switch element from the switch.
2886 **/
2887 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
2888 struct i40e_asq_cmd_details *cmd_details)
2889 {
2890 struct i40e_aq_desc desc;
2891 struct i40e_aqc_switch_seid *cmd =
2892 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2893 i40e_status status;
2894
2895 if (seid == 0)
2896 return I40E_ERR_PARAM;
2897
2898 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
2899
2900 cmd->seid = cpu_to_le16(seid);
2901
2902 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2903
2904 return status;
2905 }
2906
2907 /**
2908 * i40e_aq_dcb_updated - DCB Updated Command
2909 * @hw: pointer to the hw struct
2910 * @cmd_details: pointer to command details structure or NULL
2911 *
2912 * EMP will return when the shared RPB settings have been
2913 * recomputed and modified. The retval field in the descriptor
2914 * will be set to 0 when RPB is modified.
2915 **/
2916 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
2917 struct i40e_asq_cmd_details *cmd_details)
2918 {
2919 struct i40e_aq_desc desc;
2920 i40e_status status;
2921
2922 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
2923
2924 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2925
2926 return status;
2927 }
2928
2929 /**
2930 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2931 * @hw: pointer to the hw struct
2932 * @seid: seid for the physical port/switching component/vsi
2933 * @buff: Indirect buffer to hold data parameters and response
2934 * @buff_size: Indirect buffer size
2935 * @opcode: Tx scheduler AQ command opcode
2936 * @cmd_details: pointer to command details structure or NULL
2937 *
2938 * Generic command handler for Tx scheduler AQ commands
2939 **/
2940 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
2941 void *buff, u16 buff_size,
2942 enum i40e_admin_queue_opc opcode,
2943 struct i40e_asq_cmd_details *cmd_details)
2944 {
2945 struct i40e_aq_desc desc;
2946 struct i40e_aqc_tx_sched_ind *cmd =
2947 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
2948 i40e_status status;
2949 bool cmd_param_flag = false;
2950
2951 switch (opcode) {
2952 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
2953 case i40e_aqc_opc_configure_vsi_tc_bw:
2954 case i40e_aqc_opc_enable_switching_comp_ets:
2955 case i40e_aqc_opc_modify_switching_comp_ets:
2956 case i40e_aqc_opc_disable_switching_comp_ets:
2957 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
2958 case i40e_aqc_opc_configure_switching_comp_bw_config:
2959 cmd_param_flag = true;
2960 break;
2961 case i40e_aqc_opc_query_vsi_bw_config:
2962 case i40e_aqc_opc_query_vsi_ets_sla_config:
2963 case i40e_aqc_opc_query_switching_comp_ets_config:
2964 case i40e_aqc_opc_query_port_ets_config:
2965 case i40e_aqc_opc_query_switching_comp_bw_config:
2966 cmd_param_flag = false;
2967 break;
2968 default:
2969 return I40E_ERR_PARAM;
2970 }
2971
2972 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2973
2974 /* Indirect command */
2975 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2976 if (cmd_param_flag)
2977 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
2978 if (buff_size > I40E_AQ_LARGE_BUF)
2979 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2980
2981 desc.datalen = cpu_to_le16(buff_size);
2982
2983 cmd->vsi_seid = cpu_to_le16(seid);
2984
2985 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2986
2987 return status;
2988 }
2989
2990 /**
2991 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
2992 * @hw: pointer to the hw struct
2993 * @seid: VSI seid
2994 * @credit: BW limit credits (0 = disabled)
2995 * @max_credit: Max BW limit credits
2996 * @cmd_details: pointer to command details structure or NULL
2997 **/
2998 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
2999 u16 seid, u16 credit, u8 max_credit,
3000 struct i40e_asq_cmd_details *cmd_details)
3001 {
3002 struct i40e_aq_desc desc;
3003 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3004 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3005 i40e_status status;
3006
3007 i40e_fill_default_direct_cmd_desc(&desc,
3008 i40e_aqc_opc_configure_vsi_bw_limit);
3009
3010 cmd->vsi_seid = cpu_to_le16(seid);
3011 cmd->credit = cpu_to_le16(credit);
3012 cmd->max_credit = max_credit;
3013
3014 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3015
3016 return status;
3017 }
3018
3019 /**
3020 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3021 * @hw: pointer to the hw struct
3022 * @seid: VSI seid
3023 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3024 * @cmd_details: pointer to command details structure or NULL
3025 **/
3026 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3027 u16 seid,
3028 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3029 struct i40e_asq_cmd_details *cmd_details)
3030 {
3031 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3032 i40e_aqc_opc_configure_vsi_tc_bw,
3033 cmd_details);
3034 }
3035
3036 /**
3037 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3038 * @hw: pointer to the hw struct
3039 * @seid: seid of the switching component connected to Physical Port
3040 * @ets_data: Buffer holding ETS parameters
3041 * @cmd_details: pointer to command details structure or NULL
3042 **/
3043 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3044 u16 seid,
3045 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3046 enum i40e_admin_queue_opc opcode,
3047 struct i40e_asq_cmd_details *cmd_details)
3048 {
3049 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3050 sizeof(*ets_data), opcode, cmd_details);
3051 }
3052
3053 /**
3054 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3055 * @hw: pointer to the hw struct
3056 * @seid: seid of the switching component
3057 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3058 * @cmd_details: pointer to command details structure or NULL
3059 **/
3060 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3061 u16 seid,
3062 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3063 struct i40e_asq_cmd_details *cmd_details)
3064 {
3065 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3066 i40e_aqc_opc_configure_switching_comp_bw_config,
3067 cmd_details);
3068 }
3069
3070 /**
3071 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3072 * @hw: pointer to the hw struct
3073 * @seid: seid of the VSI
3074 * @bw_data: Buffer to hold VSI BW configuration
3075 * @cmd_details: pointer to command details structure or NULL
3076 **/
3077 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3078 u16 seid,
3079 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3080 struct i40e_asq_cmd_details *cmd_details)
3081 {
3082 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3083 i40e_aqc_opc_query_vsi_bw_config,
3084 cmd_details);
3085 }
3086
3087 /**
3088 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3089 * @hw: pointer to the hw struct
3090 * @seid: seid of the VSI
3091 * @bw_data: Buffer to hold VSI BW configuration per TC
3092 * @cmd_details: pointer to command details structure or NULL
3093 **/
3094 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3095 u16 seid,
3096 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3097 struct i40e_asq_cmd_details *cmd_details)
3098 {
3099 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3100 i40e_aqc_opc_query_vsi_ets_sla_config,
3101 cmd_details);
3102 }
3103
3104 /**
3105 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3106 * @hw: pointer to the hw struct
3107 * @seid: seid of the switching component
3108 * @bw_data: Buffer to hold switching component's per TC BW config
3109 * @cmd_details: pointer to command details structure or NULL
3110 **/
3111 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3112 u16 seid,
3113 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3114 struct i40e_asq_cmd_details *cmd_details)
3115 {
3116 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3117 i40e_aqc_opc_query_switching_comp_ets_config,
3118 cmd_details);
3119 }
3120
3121 /**
3122 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3123 * @hw: pointer to the hw struct
3124 * @seid: seid of the VSI or switching component connected to Physical Port
3125 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3126 * @cmd_details: pointer to command details structure or NULL
3127 **/
3128 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3129 u16 seid,
3130 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3131 struct i40e_asq_cmd_details *cmd_details)
3132 {
3133 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3134 i40e_aqc_opc_query_port_ets_config,
3135 cmd_details);
3136 }
3137
3138 /**
3139 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3140 * @hw: pointer to the hw struct
3141 * @seid: seid of the switching component
3142 * @bw_data: Buffer to hold switching component's BW configuration
3143 * @cmd_details: pointer to command details structure or NULL
3144 **/
3145 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3146 u16 seid,
3147 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3148 struct i40e_asq_cmd_details *cmd_details)
3149 {
3150 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3151 i40e_aqc_opc_query_switching_comp_bw_config,
3152 cmd_details);
3153 }
3154
3155 /**
3156 * i40e_validate_filter_settings
3157 * @hw: pointer to the hardware structure
3158 * @settings: Filter control settings
3159 *
3160 * Check and validate the filter control settings passed.
3161 * The function checks for the valid filter/context sizes being
3162 * passed for FCoE and PE.
3163 *
3164 * Returns 0 if the values passed are valid and within
3165 * range else returns an error.
3166 **/
3167 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3168 struct i40e_filter_control_settings *settings)
3169 {
3170 u32 fcoe_cntx_size, fcoe_filt_size;
3171 u32 pe_cntx_size, pe_filt_size;
3172 u32 fcoe_fmax;
3173 u32 val;
3174
3175 /* Validate FCoE settings passed */
3176 switch (settings->fcoe_filt_num) {
3177 case I40E_HASH_FILTER_SIZE_1K:
3178 case I40E_HASH_FILTER_SIZE_2K:
3179 case I40E_HASH_FILTER_SIZE_4K:
3180 case I40E_HASH_FILTER_SIZE_8K:
3181 case I40E_HASH_FILTER_SIZE_16K:
3182 case I40E_HASH_FILTER_SIZE_32K:
3183 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3184 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3185 break;
3186 default:
3187 return I40E_ERR_PARAM;
3188 }
3189
3190 switch (settings->fcoe_cntx_num) {
3191 case I40E_DMA_CNTX_SIZE_512:
3192 case I40E_DMA_CNTX_SIZE_1K:
3193 case I40E_DMA_CNTX_SIZE_2K:
3194 case I40E_DMA_CNTX_SIZE_4K:
3195 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3196 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3197 break;
3198 default:
3199 return I40E_ERR_PARAM;
3200 }
3201
3202 /* Validate PE settings passed */
3203 switch (settings->pe_filt_num) {
3204 case I40E_HASH_FILTER_SIZE_1K:
3205 case I40E_HASH_FILTER_SIZE_2K:
3206 case I40E_HASH_FILTER_SIZE_4K:
3207 case I40E_HASH_FILTER_SIZE_8K:
3208 case I40E_HASH_FILTER_SIZE_16K:
3209 case I40E_HASH_FILTER_SIZE_32K:
3210 case I40E_HASH_FILTER_SIZE_64K:
3211 case I40E_HASH_FILTER_SIZE_128K:
3212 case I40E_HASH_FILTER_SIZE_256K:
3213 case I40E_HASH_FILTER_SIZE_512K:
3214 case I40E_HASH_FILTER_SIZE_1M:
3215 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3216 pe_filt_size <<= (u32)settings->pe_filt_num;
3217 break;
3218 default:
3219 return I40E_ERR_PARAM;
3220 }
3221
3222 switch (settings->pe_cntx_num) {
3223 case I40E_DMA_CNTX_SIZE_512:
3224 case I40E_DMA_CNTX_SIZE_1K:
3225 case I40E_DMA_CNTX_SIZE_2K:
3226 case I40E_DMA_CNTX_SIZE_4K:
3227 case I40E_DMA_CNTX_SIZE_8K:
3228 case I40E_DMA_CNTX_SIZE_16K:
3229 case I40E_DMA_CNTX_SIZE_32K:
3230 case I40E_DMA_CNTX_SIZE_64K:
3231 case I40E_DMA_CNTX_SIZE_128K:
3232 case I40E_DMA_CNTX_SIZE_256K:
3233 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3234 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3235 break;
3236 default:
3237 return I40E_ERR_PARAM;
3238 }
3239
3240 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3241 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3242 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3243 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3244 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3245 return I40E_ERR_INVALID_SIZE;
3246
3247 return 0;
3248 }
3249
3250 /**
3251 * i40e_set_filter_control
3252 * @hw: pointer to the hardware structure
3253 * @settings: Filter control settings
3254 *
3255 * Set the Queue Filters for PE/FCoE and enable filters required
3256 * for a single PF. It is expected that these settings are programmed
3257 * at the driver initialization time.
3258 **/
3259 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3260 struct i40e_filter_control_settings *settings)
3261 {
3262 i40e_status ret = 0;
3263 u32 hash_lut_size = 0;
3264 u32 val;
3265
3266 if (!settings)
3267 return I40E_ERR_PARAM;
3268
3269 /* Validate the input settings */
3270 ret = i40e_validate_filter_settings(hw, settings);
3271 if (ret)
3272 return ret;
3273
3274 /* Read the PF Queue Filter control register */
3275 val = rd32(hw, I40E_PFQF_CTL_0);
3276
3277 /* Program required PE hash buckets for the PF */
3278 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3279 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3280 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3281 /* Program required PE contexts for the PF */
3282 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3283 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3284 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3285
3286 /* Program required FCoE hash buckets for the PF */
3287 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3288 val |= ((u32)settings->fcoe_filt_num <<
3289 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3290 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3291 /* Program required FCoE DDP contexts for the PF */
3292 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3293 val |= ((u32)settings->fcoe_cntx_num <<
3294 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3295 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3296
3297 /* Program Hash LUT size for the PF */
3298 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3299 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3300 hash_lut_size = 1;
3301 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3302 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3303
3304 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3305 if (settings->enable_fdir)
3306 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3307 if (settings->enable_ethtype)
3308 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3309 if (settings->enable_macvlan)
3310 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3311
3312 wr32(hw, I40E_PFQF_CTL_0, val);
3313
3314 return 0;
3315 }
3316
3317 /**
3318 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3319 * @hw: pointer to the hw struct
3320 * @mac_addr: MAC address to use in the filter
3321 * @ethtype: Ethertype to use in the filter
3322 * @flags: Flags that needs to be applied to the filter
3323 * @vsi_seid: seid of the control VSI
3324 * @queue: VSI queue number to send the packet to
3325 * @is_add: Add control packet filter if True else remove
3326 * @stats: Structure to hold information on control filter counts
3327 * @cmd_details: pointer to command details structure or NULL
3328 *
3329 * This command will Add or Remove control packet filter for a control VSI.
3330 * In return it will update the total number of perfect filter count in
3331 * the stats member.
3332 **/
3333 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3334 u8 *mac_addr, u16 ethtype, u16 flags,
3335 u16 vsi_seid, u16 queue, bool is_add,
3336 struct i40e_control_filter_stats *stats,
3337 struct i40e_asq_cmd_details *cmd_details)
3338 {
3339 struct i40e_aq_desc desc;
3340 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3341 (struct i40e_aqc_add_remove_control_packet_filter *)
3342 &desc.params.raw;
3343 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3344 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3345 &desc.params.raw;
3346 i40e_status status;
3347
3348 if (vsi_seid == 0)
3349 return I40E_ERR_PARAM;
3350
3351 if (is_add) {
3352 i40e_fill_default_direct_cmd_desc(&desc,
3353 i40e_aqc_opc_add_control_packet_filter);
3354 cmd->queue = cpu_to_le16(queue);
3355 } else {
3356 i40e_fill_default_direct_cmd_desc(&desc,
3357 i40e_aqc_opc_remove_control_packet_filter);
3358 }
3359
3360 if (mac_addr)
3361 memcpy(cmd->mac, mac_addr, ETH_ALEN);
3362
3363 cmd->etype = cpu_to_le16(ethtype);
3364 cmd->flags = cpu_to_le16(flags);
3365 cmd->seid = cpu_to_le16(vsi_seid);
3366
3367 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3368
3369 if (!status && stats) {
3370 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3371 stats->etype_used = le16_to_cpu(resp->etype_used);
3372 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3373 stats->etype_free = le16_to_cpu(resp->etype_free);
3374 }
3375
3376 return status;
3377 }
3378
3379 /**
3380 * i40e_aq_resume_port_tx
3381 * @hw: pointer to the hardware structure
3382 * @cmd_details: pointer to command details structure or NULL
3383 *
3384 * Resume port's Tx traffic
3385 **/
3386 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
3387 struct i40e_asq_cmd_details *cmd_details)
3388 {
3389 struct i40e_aq_desc desc;
3390 i40e_status status;
3391
3392 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
3393
3394 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3395
3396 return status;
3397 }
3398
3399 /**
3400 * i40e_set_pci_config_data - store PCI bus info
3401 * @hw: pointer to hardware structure
3402 * @link_status: the link status word from PCI config space
3403 *
3404 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3405 **/
3406 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
3407 {
3408 hw->bus.type = i40e_bus_type_pci_express;
3409
3410 switch (link_status & PCI_EXP_LNKSTA_NLW) {
3411 case PCI_EXP_LNKSTA_NLW_X1:
3412 hw->bus.width = i40e_bus_width_pcie_x1;
3413 break;
3414 case PCI_EXP_LNKSTA_NLW_X2:
3415 hw->bus.width = i40e_bus_width_pcie_x2;
3416 break;
3417 case PCI_EXP_LNKSTA_NLW_X4:
3418 hw->bus.width = i40e_bus_width_pcie_x4;
3419 break;
3420 case PCI_EXP_LNKSTA_NLW_X8:
3421 hw->bus.width = i40e_bus_width_pcie_x8;
3422 break;
3423 default:
3424 hw->bus.width = i40e_bus_width_unknown;
3425 break;
3426 }
3427
3428 switch (link_status & PCI_EXP_LNKSTA_CLS) {
3429 case PCI_EXP_LNKSTA_CLS_2_5GB:
3430 hw->bus.speed = i40e_bus_speed_2500;
3431 break;
3432 case PCI_EXP_LNKSTA_CLS_5_0GB:
3433 hw->bus.speed = i40e_bus_speed_5000;
3434 break;
3435 case PCI_EXP_LNKSTA_CLS_8_0GB:
3436 hw->bus.speed = i40e_bus_speed_8000;
3437 break;
3438 default:
3439 hw->bus.speed = i40e_bus_speed_unknown;
3440 break;
3441 }
3442 }
Linux kernel - Deliverables
This page took 0.104079 seconds and 6 git commands to generate.