1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
39 static i40e_status
i40e_set_mac_type(struct i40e_hw
*hw
)
41 i40e_status status
= 0;
43 if (hw
->vendor_id
== PCI_VENDOR_ID_INTEL
) {
44 switch (hw
->device_id
) {
45 case I40E_DEV_ID_SFP_XL710
:
46 case I40E_DEV_ID_QEMU
:
47 case I40E_DEV_ID_KX_B
:
48 case I40E_DEV_ID_KX_C
:
49 case I40E_DEV_ID_QSFP_A
:
50 case I40E_DEV_ID_QSFP_B
:
51 case I40E_DEV_ID_QSFP_C
:
52 case I40E_DEV_ID_10G_BASE_T
:
53 case I40E_DEV_ID_10G_BASE_T4
:
54 case I40E_DEV_ID_20G_KR2
:
55 case I40E_DEV_ID_20G_KR2_A
:
56 hw
->mac
.type
= I40E_MAC_XL710
;
58 case I40E_DEV_ID_KX_X722
:
59 case I40E_DEV_ID_QSFP_X722
:
60 case I40E_DEV_ID_SFP_X722
:
61 case I40E_DEV_ID_1G_BASE_T_X722
:
62 case I40E_DEV_ID_10G_BASE_T_X722
:
63 hw
->mac
.type
= I40E_MAC_X722
;
66 hw
->mac
.type
= I40E_MAC_GENERIC
;
70 status
= I40E_ERR_DEVICE_NOT_SUPPORTED
;
73 hw_dbg(hw
, "i40e_set_mac_type found mac: %d, returns: %d\n",
74 hw
->mac
.type
, status
);
79 * i40e_aq_str - convert AQ err code to a string
80 * @hw: pointer to the HW structure
81 * @aq_err: the AQ error code to convert
83 const char *i40e_aq_str(struct i40e_hw
*hw
, enum i40e_admin_queue_err aq_err
)
88 case I40E_AQ_RC_EPERM
:
89 return "I40E_AQ_RC_EPERM";
90 case I40E_AQ_RC_ENOENT
:
91 return "I40E_AQ_RC_ENOENT";
92 case I40E_AQ_RC_ESRCH
:
93 return "I40E_AQ_RC_ESRCH";
94 case I40E_AQ_RC_EINTR
:
95 return "I40E_AQ_RC_EINTR";
97 return "I40E_AQ_RC_EIO";
98 case I40E_AQ_RC_ENXIO
:
99 return "I40E_AQ_RC_ENXIO";
100 case I40E_AQ_RC_E2BIG
:
101 return "I40E_AQ_RC_E2BIG";
102 case I40E_AQ_RC_EAGAIN
:
103 return "I40E_AQ_RC_EAGAIN";
104 case I40E_AQ_RC_ENOMEM
:
105 return "I40E_AQ_RC_ENOMEM";
106 case I40E_AQ_RC_EACCES
:
107 return "I40E_AQ_RC_EACCES";
108 case I40E_AQ_RC_EFAULT
:
109 return "I40E_AQ_RC_EFAULT";
110 case I40E_AQ_RC_EBUSY
:
111 return "I40E_AQ_RC_EBUSY";
112 case I40E_AQ_RC_EEXIST
:
113 return "I40E_AQ_RC_EEXIST";
114 case I40E_AQ_RC_EINVAL
:
115 return "I40E_AQ_RC_EINVAL";
116 case I40E_AQ_RC_ENOTTY
:
117 return "I40E_AQ_RC_ENOTTY";
118 case I40E_AQ_RC_ENOSPC
:
119 return "I40E_AQ_RC_ENOSPC";
120 case I40E_AQ_RC_ENOSYS
:
121 return "I40E_AQ_RC_ENOSYS";
122 case I40E_AQ_RC_ERANGE
:
123 return "I40E_AQ_RC_ERANGE";
124 case I40E_AQ_RC_EFLUSHED
:
125 return "I40E_AQ_RC_EFLUSHED";
126 case I40E_AQ_RC_BAD_ADDR
:
127 return "I40E_AQ_RC_BAD_ADDR";
128 case I40E_AQ_RC_EMODE
:
129 return "I40E_AQ_RC_EMODE";
130 case I40E_AQ_RC_EFBIG
:
131 return "I40E_AQ_RC_EFBIG";
134 snprintf(hw
->err_str
, sizeof(hw
->err_str
), "%d", aq_err
);
139 * i40e_stat_str - convert status err code to a string
140 * @hw: pointer to the HW structure
141 * @stat_err: the status error code to convert
143 const char *i40e_stat_str(struct i40e_hw
*hw
, i40e_status stat_err
)
149 return "I40E_ERR_NVM";
150 case I40E_ERR_NVM_CHECKSUM
:
151 return "I40E_ERR_NVM_CHECKSUM";
153 return "I40E_ERR_PHY";
154 case I40E_ERR_CONFIG
:
155 return "I40E_ERR_CONFIG";
157 return "I40E_ERR_PARAM";
158 case I40E_ERR_MAC_TYPE
:
159 return "I40E_ERR_MAC_TYPE";
160 case I40E_ERR_UNKNOWN_PHY
:
161 return "I40E_ERR_UNKNOWN_PHY";
162 case I40E_ERR_LINK_SETUP
:
163 return "I40E_ERR_LINK_SETUP";
164 case I40E_ERR_ADAPTER_STOPPED
:
165 return "I40E_ERR_ADAPTER_STOPPED";
166 case I40E_ERR_INVALID_MAC_ADDR
:
167 return "I40E_ERR_INVALID_MAC_ADDR";
168 case I40E_ERR_DEVICE_NOT_SUPPORTED
:
169 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
170 case I40E_ERR_MASTER_REQUESTS_PENDING
:
171 return "I40E_ERR_MASTER_REQUESTS_PENDING";
172 case I40E_ERR_INVALID_LINK_SETTINGS
:
173 return "I40E_ERR_INVALID_LINK_SETTINGS";
174 case I40E_ERR_AUTONEG_NOT_COMPLETE
:
175 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
176 case I40E_ERR_RESET_FAILED
:
177 return "I40E_ERR_RESET_FAILED";
178 case I40E_ERR_SWFW_SYNC
:
179 return "I40E_ERR_SWFW_SYNC";
180 case I40E_ERR_NO_AVAILABLE_VSI
:
181 return "I40E_ERR_NO_AVAILABLE_VSI";
182 case I40E_ERR_NO_MEMORY
:
183 return "I40E_ERR_NO_MEMORY";
184 case I40E_ERR_BAD_PTR
:
185 return "I40E_ERR_BAD_PTR";
186 case I40E_ERR_RING_FULL
:
187 return "I40E_ERR_RING_FULL";
188 case I40E_ERR_INVALID_PD_ID
:
189 return "I40E_ERR_INVALID_PD_ID";
190 case I40E_ERR_INVALID_QP_ID
:
191 return "I40E_ERR_INVALID_QP_ID";
192 case I40E_ERR_INVALID_CQ_ID
:
193 return "I40E_ERR_INVALID_CQ_ID";
194 case I40E_ERR_INVALID_CEQ_ID
:
195 return "I40E_ERR_INVALID_CEQ_ID";
196 case I40E_ERR_INVALID_AEQ_ID
:
197 return "I40E_ERR_INVALID_AEQ_ID";
198 case I40E_ERR_INVALID_SIZE
:
199 return "I40E_ERR_INVALID_SIZE";
200 case I40E_ERR_INVALID_ARP_INDEX
:
201 return "I40E_ERR_INVALID_ARP_INDEX";
202 case I40E_ERR_INVALID_FPM_FUNC_ID
:
203 return "I40E_ERR_INVALID_FPM_FUNC_ID";
204 case I40E_ERR_QP_INVALID_MSG_SIZE
:
205 return "I40E_ERR_QP_INVALID_MSG_SIZE";
206 case I40E_ERR_QP_TOOMANY_WRS_POSTED
:
207 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
208 case I40E_ERR_INVALID_FRAG_COUNT
:
209 return "I40E_ERR_INVALID_FRAG_COUNT";
210 case I40E_ERR_QUEUE_EMPTY
:
211 return "I40E_ERR_QUEUE_EMPTY";
212 case I40E_ERR_INVALID_ALIGNMENT
:
213 return "I40E_ERR_INVALID_ALIGNMENT";
214 case I40E_ERR_FLUSHED_QUEUE
:
215 return "I40E_ERR_FLUSHED_QUEUE";
216 case I40E_ERR_INVALID_PUSH_PAGE_INDEX
:
217 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
218 case I40E_ERR_INVALID_IMM_DATA_SIZE
:
219 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
220 case I40E_ERR_TIMEOUT
:
221 return "I40E_ERR_TIMEOUT";
222 case I40E_ERR_OPCODE_MISMATCH
:
223 return "I40E_ERR_OPCODE_MISMATCH";
224 case I40E_ERR_CQP_COMPL_ERROR
:
225 return "I40E_ERR_CQP_COMPL_ERROR";
226 case I40E_ERR_INVALID_VF_ID
:
227 return "I40E_ERR_INVALID_VF_ID";
228 case I40E_ERR_INVALID_HMCFN_ID
:
229 return "I40E_ERR_INVALID_HMCFN_ID";
230 case I40E_ERR_BACKING_PAGE_ERROR
:
231 return "I40E_ERR_BACKING_PAGE_ERROR";
232 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE
:
233 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
234 case I40E_ERR_INVALID_PBLE_INDEX
:
235 return "I40E_ERR_INVALID_PBLE_INDEX";
236 case I40E_ERR_INVALID_SD_INDEX
:
237 return "I40E_ERR_INVALID_SD_INDEX";
238 case I40E_ERR_INVALID_PAGE_DESC_INDEX
:
239 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
240 case I40E_ERR_INVALID_SD_TYPE
:
241 return "I40E_ERR_INVALID_SD_TYPE";
242 case I40E_ERR_MEMCPY_FAILED
:
243 return "I40E_ERR_MEMCPY_FAILED";
244 case I40E_ERR_INVALID_HMC_OBJ_INDEX
:
245 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
246 case I40E_ERR_INVALID_HMC_OBJ_COUNT
:
247 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
248 case I40E_ERR_INVALID_SRQ_ARM_LIMIT
:
249 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
250 case I40E_ERR_SRQ_ENABLED
:
251 return "I40E_ERR_SRQ_ENABLED";
252 case I40E_ERR_ADMIN_QUEUE_ERROR
:
253 return "I40E_ERR_ADMIN_QUEUE_ERROR";
254 case I40E_ERR_ADMIN_QUEUE_TIMEOUT
:
255 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
256 case I40E_ERR_BUF_TOO_SHORT
:
257 return "I40E_ERR_BUF_TOO_SHORT";
258 case I40E_ERR_ADMIN_QUEUE_FULL
:
259 return "I40E_ERR_ADMIN_QUEUE_FULL";
260 case I40E_ERR_ADMIN_QUEUE_NO_WORK
:
261 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
262 case I40E_ERR_BAD_IWARP_CQE
:
263 return "I40E_ERR_BAD_IWARP_CQE";
264 case I40E_ERR_NVM_BLANK_MODE
:
265 return "I40E_ERR_NVM_BLANK_MODE";
266 case I40E_ERR_NOT_IMPLEMENTED
:
267 return "I40E_ERR_NOT_IMPLEMENTED";
268 case I40E_ERR_PE_DOORBELL_NOT_ENABLED
:
269 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
270 case I40E_ERR_DIAG_TEST_FAILED
:
271 return "I40E_ERR_DIAG_TEST_FAILED";
272 case I40E_ERR_NOT_READY
:
273 return "I40E_ERR_NOT_READY";
274 case I40E_NOT_SUPPORTED
:
275 return "I40E_NOT_SUPPORTED";
276 case I40E_ERR_FIRMWARE_API_VERSION
:
277 return "I40E_ERR_FIRMWARE_API_VERSION";
280 snprintf(hw
->err_str
, sizeof(hw
->err_str
), "%d", stat_err
);
286 * @hw: debug mask related to admin queue
288 * @desc: pointer to admin queue descriptor
289 * @buffer: pointer to command buffer
290 * @buf_len: max length of buffer
292 * Dumps debug log about adminq command with descriptor contents.
294 void i40e_debug_aq(struct i40e_hw
*hw
, enum i40e_debug_mask mask
, void *desc
,
295 void *buffer
, u16 buf_len
)
297 struct i40e_aq_desc
*aq_desc
= (struct i40e_aq_desc
*)desc
;
298 u16 len
= le16_to_cpu(aq_desc
->datalen
);
299 u8
*buf
= (u8
*)buffer
;
302 if ((!(mask
& hw
->debug_mask
)) || (desc
== NULL
))
306 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
307 le16_to_cpu(aq_desc
->opcode
),
308 le16_to_cpu(aq_desc
->flags
),
309 le16_to_cpu(aq_desc
->datalen
),
310 le16_to_cpu(aq_desc
->retval
));
311 i40e_debug(hw
, mask
, "\tcookie (h,l) 0x%08X 0x%08X\n",
312 le32_to_cpu(aq_desc
->cookie_high
),
313 le32_to_cpu(aq_desc
->cookie_low
));
314 i40e_debug(hw
, mask
, "\tparam (0,1) 0x%08X 0x%08X\n",
315 le32_to_cpu(aq_desc
->params
.internal
.param0
),
316 le32_to_cpu(aq_desc
->params
.internal
.param1
));
317 i40e_debug(hw
, mask
, "\taddr (h,l) 0x%08X 0x%08X\n",
318 le32_to_cpu(aq_desc
->params
.external
.addr_high
),
319 le32_to_cpu(aq_desc
->params
.external
.addr_low
));
321 if ((buffer
!= NULL
) && (aq_desc
->datalen
!= 0)) {
322 i40e_debug(hw
, mask
, "AQ CMD Buffer:\n");
325 /* write the full 16-byte chunks */
326 for (i
= 0; i
< (len
- 16); i
+= 16)
327 i40e_debug(hw
, mask
, "\t0x%04X %16ph\n", i
, buf
+ i
);
328 /* write whatever's left over without overrunning the buffer */
330 i40e_debug(hw
, mask
, "\t0x%04X %*ph\n",
331 i
, len
- i
, buf
+ i
);
336 * i40e_check_asq_alive
337 * @hw: pointer to the hw struct
339 * Returns true if Queue is enabled else false.
341 bool i40e_check_asq_alive(struct i40e_hw
*hw
)
344 return !!(rd32(hw
, hw
->aq
.asq
.len
) &
345 I40E_PF_ATQLEN_ATQENABLE_MASK
);
351 * i40e_aq_queue_shutdown
352 * @hw: pointer to the hw struct
353 * @unloading: is the driver unloading itself
355 * Tell the Firmware that we're shutting down the AdminQ and whether
356 * or not the driver is unloading as well.
358 i40e_status
i40e_aq_queue_shutdown(struct i40e_hw
*hw
,
361 struct i40e_aq_desc desc
;
362 struct i40e_aqc_queue_shutdown
*cmd
=
363 (struct i40e_aqc_queue_shutdown
*)&desc
.params
.raw
;
366 i40e_fill_default_direct_cmd_desc(&desc
,
367 i40e_aqc_opc_queue_shutdown
);
370 cmd
->driver_unloading
= cpu_to_le32(I40E_AQ_DRIVER_UNLOADING
);
371 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, NULL
);
377 * i40e_aq_get_set_rss_lut
378 * @hw: pointer to the hardware structure
379 * @vsi_id: vsi fw index
380 * @pf_lut: for PF table set true, for VSI table set false
381 * @lut: pointer to the lut buffer provided by the caller
382 * @lut_size: size of the lut buffer
383 * @set: set true to set the table, false to get the table
385 * Internal function to get or set RSS look up table
387 static i40e_status
i40e_aq_get_set_rss_lut(struct i40e_hw
*hw
,
388 u16 vsi_id
, bool pf_lut
,
389 u8
*lut
, u16 lut_size
,
393 struct i40e_aq_desc desc
;
394 struct i40e_aqc_get_set_rss_lut
*cmd_resp
=
395 (struct i40e_aqc_get_set_rss_lut
*)&desc
.params
.raw
;
398 i40e_fill_default_direct_cmd_desc(&desc
,
399 i40e_aqc_opc_set_rss_lut
);
401 i40e_fill_default_direct_cmd_desc(&desc
,
402 i40e_aqc_opc_get_rss_lut
);
404 /* Indirect command */
405 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
406 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_RD
);
409 cpu_to_le16((u16
)((vsi_id
<<
410 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT
) &
411 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK
));
412 cmd_resp
->vsi_id
|= cpu_to_le16((u16
)I40E_AQC_SET_RSS_LUT_VSI_VALID
);
415 cmd_resp
->flags
|= cpu_to_le16((u16
)
416 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF
<<
417 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT
) &
418 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK
));
420 cmd_resp
->flags
|= cpu_to_le16((u16
)
421 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI
<<
422 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT
) &
423 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK
));
425 status
= i40e_asq_send_command(hw
, &desc
, lut
, lut_size
, NULL
);
431 * i40e_aq_get_rss_lut
432 * @hw: pointer to the hardware structure
433 * @vsi_id: vsi fw index
434 * @pf_lut: for PF table set true, for VSI table set false
435 * @lut: pointer to the lut buffer provided by the caller
436 * @lut_size: size of the lut buffer
438 * get the RSS lookup table, PF or VSI type
440 i40e_status
i40e_aq_get_rss_lut(struct i40e_hw
*hw
, u16 vsi_id
,
441 bool pf_lut
, u8
*lut
, u16 lut_size
)
443 return i40e_aq_get_set_rss_lut(hw
, vsi_id
, pf_lut
, lut
, lut_size
,
448 * i40e_aq_set_rss_lut
449 * @hw: pointer to the hardware structure
450 * @vsi_id: vsi fw index
451 * @pf_lut: for PF table set true, for VSI table set false
452 * @lut: pointer to the lut buffer provided by the caller
453 * @lut_size: size of the lut buffer
455 * set the RSS lookup table, PF or VSI type
457 i40e_status
i40e_aq_set_rss_lut(struct i40e_hw
*hw
, u16 vsi_id
,
458 bool pf_lut
, u8
*lut
, u16 lut_size
)
460 return i40e_aq_get_set_rss_lut(hw
, vsi_id
, pf_lut
, lut
, lut_size
, true);
464 * i40e_aq_get_set_rss_key
465 * @hw: pointer to the hw struct
466 * @vsi_id: vsi fw index
467 * @key: pointer to key info struct
468 * @set: set true to set the key, false to get the key
470 * get the RSS key per VSI
472 static i40e_status
i40e_aq_get_set_rss_key(struct i40e_hw
*hw
,
474 struct i40e_aqc_get_set_rss_key_data
*key
,
478 struct i40e_aq_desc desc
;
479 struct i40e_aqc_get_set_rss_key
*cmd_resp
=
480 (struct i40e_aqc_get_set_rss_key
*)&desc
.params
.raw
;
481 u16 key_size
= sizeof(struct i40e_aqc_get_set_rss_key_data
);
484 i40e_fill_default_direct_cmd_desc(&desc
,
485 i40e_aqc_opc_set_rss_key
);
487 i40e_fill_default_direct_cmd_desc(&desc
,
488 i40e_aqc_opc_get_rss_key
);
490 /* Indirect command */
491 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
492 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_RD
);
495 cpu_to_le16((u16
)((vsi_id
<<
496 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT
) &
497 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK
));
498 cmd_resp
->vsi_id
|= cpu_to_le16((u16
)I40E_AQC_SET_RSS_KEY_VSI_VALID
);
500 status
= i40e_asq_send_command(hw
, &desc
, key
, key_size
, NULL
);
506 * i40e_aq_get_rss_key
507 * @hw: pointer to the hw struct
508 * @vsi_id: vsi fw index
509 * @key: pointer to key info struct
512 i40e_status
i40e_aq_get_rss_key(struct i40e_hw
*hw
,
514 struct i40e_aqc_get_set_rss_key_data
*key
)
516 return i40e_aq_get_set_rss_key(hw
, vsi_id
, key
, false);
520 * i40e_aq_set_rss_key
521 * @hw: pointer to the hw struct
522 * @vsi_id: vsi fw index
523 * @key: pointer to key info struct
525 * set the RSS key per VSI
527 i40e_status
i40e_aq_set_rss_key(struct i40e_hw
*hw
,
529 struct i40e_aqc_get_set_rss_key_data
*key
)
531 return i40e_aq_get_set_rss_key(hw
, vsi_id
, key
, true);
534 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
535 * hardware to a bit-field that can be used by SW to more easily determine the
538 * Macros are used to shorten the table lines and make this table human
541 * We store the PTYPE in the top byte of the bit field - this is just so that
542 * we can check that the table doesn't have a row missing, as the index into
543 * the table should be the PTYPE.
547 * IF NOT i40e_ptype_lookup[ptype].known
550 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
551 * Use the rest of the fields to look at the tunnels, inner protocols, etc
553 * Use the enum i40e_rx_l2_ptype to decode the packet type
557 /* macro to make the table lines short */
558 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
561 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
562 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
563 I40E_RX_PTYPE_##OUTER_FRAG, \
564 I40E_RX_PTYPE_TUNNEL_##T, \
565 I40E_RX_PTYPE_TUNNEL_END_##TE, \
566 I40E_RX_PTYPE_##TEF, \
567 I40E_RX_PTYPE_INNER_PROT_##I, \
568 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
570 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
571 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
573 /* shorter macros makes the table fit but are terse */
574 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
575 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
576 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
578 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
579 struct i40e_rx_ptype_decoded i40e_ptype_lookup
[] = {
580 /* L2 Packet types */
581 I40E_PTT_UNUSED_ENTRY(0),
582 I40E_PTT(1, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
583 I40E_PTT(2, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, TS
, PAY2
),
584 I40E_PTT(3, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
585 I40E_PTT_UNUSED_ENTRY(4),
586 I40E_PTT_UNUSED_ENTRY(5),
587 I40E_PTT(6, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
588 I40E_PTT(7, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
589 I40E_PTT_UNUSED_ENTRY(8),
590 I40E_PTT_UNUSED_ENTRY(9),
591 I40E_PTT(10, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
592 I40E_PTT(11, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, NONE
),
593 I40E_PTT(12, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
594 I40E_PTT(13, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
595 I40E_PTT(14, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
596 I40E_PTT(15, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
597 I40E_PTT(16, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
598 I40E_PTT(17, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
599 I40E_PTT(18, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
600 I40E_PTT(19, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
601 I40E_PTT(20, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
602 I40E_PTT(21, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
604 /* Non Tunneled IPv4 */
605 I40E_PTT(22, IP
, IPV4
, FRG
, NONE
, NONE
, NOF
, NONE
, PAY3
),
606 I40E_PTT(23, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
607 I40E_PTT(24, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, UDP
, PAY4
),
608 I40E_PTT_UNUSED_ENTRY(25),
609 I40E_PTT(26, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, TCP
, PAY4
),
610 I40E_PTT(27, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, SCTP
, PAY4
),
611 I40E_PTT(28, IP
, IPV4
, NOF
, NONE
, NONE
, NOF
, ICMP
, PAY4
),
614 I40E_PTT(29, IP
, IPV4
, NOF
, IP_IP
, IPV4
, FRG
, NONE
, PAY3
),
615 I40E_PTT(30, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, NONE
, PAY3
),
616 I40E_PTT(31, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, UDP
, PAY4
),
617 I40E_PTT_UNUSED_ENTRY(32),
618 I40E_PTT(33, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, TCP
, PAY4
),
619 I40E_PTT(34, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, SCTP
, PAY4
),
620 I40E_PTT(35, IP
, IPV4
, NOF
, IP_IP
, IPV4
, NOF
, ICMP
, PAY4
),
623 I40E_PTT(36, IP
, IPV4
, NOF
, IP_IP
, IPV6
, FRG
, NONE
, PAY3
),
624 I40E_PTT(37, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, NONE
, PAY3
),
625 I40E_PTT(38, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, UDP
, PAY4
),
626 I40E_PTT_UNUSED_ENTRY(39),
627 I40E_PTT(40, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, TCP
, PAY4
),
628 I40E_PTT(41, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, SCTP
, PAY4
),
629 I40E_PTT(42, IP
, IPV4
, NOF
, IP_IP
, IPV6
, NOF
, ICMP
, PAY4
),
631 /* IPv4 --> GRE/NAT */
632 I40E_PTT(43, IP
, IPV4
, NOF
, IP_GRENAT
, NONE
, NOF
, NONE
, PAY3
),
634 /* IPv4 --> GRE/NAT --> IPv4 */
635 I40E_PTT(44, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, FRG
, NONE
, PAY3
),
636 I40E_PTT(45, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, NONE
, PAY3
),
637 I40E_PTT(46, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, UDP
, PAY4
),
638 I40E_PTT_UNUSED_ENTRY(47),
639 I40E_PTT(48, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, TCP
, PAY4
),
640 I40E_PTT(49, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, SCTP
, PAY4
),
641 I40E_PTT(50, IP
, IPV4
, NOF
, IP_GRENAT
, IPV4
, NOF
, ICMP
, PAY4
),
643 /* IPv4 --> GRE/NAT --> IPv6 */
644 I40E_PTT(51, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, FRG
, NONE
, PAY3
),
645 I40E_PTT(52, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, NONE
, PAY3
),
646 I40E_PTT(53, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, UDP
, PAY4
),
647 I40E_PTT_UNUSED_ENTRY(54),
648 I40E_PTT(55, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, TCP
, PAY4
),
649 I40E_PTT(56, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, SCTP
, PAY4
),
650 I40E_PTT(57, IP
, IPV4
, NOF
, IP_GRENAT
, IPV6
, NOF
, ICMP
, PAY4
),
652 /* IPv4 --> GRE/NAT --> MAC */
653 I40E_PTT(58, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, NONE
, NOF
, NONE
, PAY3
),
655 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
656 I40E_PTT(59, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, FRG
, NONE
, PAY3
),
657 I40E_PTT(60, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, NONE
, PAY3
),
658 I40E_PTT(61, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, UDP
, PAY4
),
659 I40E_PTT_UNUSED_ENTRY(62),
660 I40E_PTT(63, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, TCP
, PAY4
),
661 I40E_PTT(64, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, SCTP
, PAY4
),
662 I40E_PTT(65, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, ICMP
, PAY4
),
664 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
665 I40E_PTT(66, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, FRG
, NONE
, PAY3
),
666 I40E_PTT(67, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, NONE
, PAY3
),
667 I40E_PTT(68, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, UDP
, PAY4
),
668 I40E_PTT_UNUSED_ENTRY(69),
669 I40E_PTT(70, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, TCP
, PAY4
),
670 I40E_PTT(71, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, SCTP
, PAY4
),
671 I40E_PTT(72, IP
, IPV4
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, ICMP
, PAY4
),
673 /* IPv4 --> GRE/NAT --> MAC/VLAN */
674 I40E_PTT(73, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, NONE
, NOF
, NONE
, PAY3
),
676 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
677 I40E_PTT(74, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, FRG
, NONE
, PAY3
),
678 I40E_PTT(75, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, NONE
, PAY3
),
679 I40E_PTT(76, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, UDP
, PAY4
),
680 I40E_PTT_UNUSED_ENTRY(77),
681 I40E_PTT(78, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, TCP
, PAY4
),
682 I40E_PTT(79, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, SCTP
, PAY4
),
683 I40E_PTT(80, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, ICMP
, PAY4
),
685 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
686 I40E_PTT(81, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, FRG
, NONE
, PAY3
),
687 I40E_PTT(82, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, NONE
, PAY3
),
688 I40E_PTT(83, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, UDP
, PAY4
),
689 I40E_PTT_UNUSED_ENTRY(84),
690 I40E_PTT(85, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, TCP
, PAY4
),
691 I40E_PTT(86, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, SCTP
, PAY4
),
692 I40E_PTT(87, IP
, IPV4
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, ICMP
, PAY4
),
694 /* Non Tunneled IPv6 */
695 I40E_PTT(88, IP
, IPV6
, FRG
, NONE
, NONE
, NOF
, NONE
, PAY3
),
696 I40E_PTT(89, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY3
),
697 I40E_PTT(90, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, UDP
, PAY3
),
698 I40E_PTT_UNUSED_ENTRY(91),
699 I40E_PTT(92, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, TCP
, PAY4
),
700 I40E_PTT(93, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, SCTP
, PAY4
),
701 I40E_PTT(94, IP
, IPV6
, NOF
, NONE
, NONE
, NOF
, ICMP
, PAY4
),
704 I40E_PTT(95, IP
, IPV6
, NOF
, IP_IP
, IPV4
, FRG
, NONE
, PAY3
),
705 I40E_PTT(96, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, NONE
, PAY3
),
706 I40E_PTT(97, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, UDP
, PAY4
),
707 I40E_PTT_UNUSED_ENTRY(98),
708 I40E_PTT(99, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, TCP
, PAY4
),
709 I40E_PTT(100, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, SCTP
, PAY4
),
710 I40E_PTT(101, IP
, IPV6
, NOF
, IP_IP
, IPV4
, NOF
, ICMP
, PAY4
),
713 I40E_PTT(102, IP
, IPV6
, NOF
, IP_IP
, IPV6
, FRG
, NONE
, PAY3
),
714 I40E_PTT(103, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, NONE
, PAY3
),
715 I40E_PTT(104, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, UDP
, PAY4
),
716 I40E_PTT_UNUSED_ENTRY(105),
717 I40E_PTT(106, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, TCP
, PAY4
),
718 I40E_PTT(107, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, SCTP
, PAY4
),
719 I40E_PTT(108, IP
, IPV6
, NOF
, IP_IP
, IPV6
, NOF
, ICMP
, PAY4
),
721 /* IPv6 --> GRE/NAT */
722 I40E_PTT(109, IP
, IPV6
, NOF
, IP_GRENAT
, NONE
, NOF
, NONE
, PAY3
),
724 /* IPv6 --> GRE/NAT -> IPv4 */
725 I40E_PTT(110, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, FRG
, NONE
, PAY3
),
726 I40E_PTT(111, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, NONE
, PAY3
),
727 I40E_PTT(112, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, UDP
, PAY4
),
728 I40E_PTT_UNUSED_ENTRY(113),
729 I40E_PTT(114, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, TCP
, PAY4
),
730 I40E_PTT(115, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, SCTP
, PAY4
),
731 I40E_PTT(116, IP
, IPV6
, NOF
, IP_GRENAT
, IPV4
, NOF
, ICMP
, PAY4
),
733 /* IPv6 --> GRE/NAT -> IPv6 */
734 I40E_PTT(117, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, FRG
, NONE
, PAY3
),
735 I40E_PTT(118, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, NONE
, PAY3
),
736 I40E_PTT(119, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, UDP
, PAY4
),
737 I40E_PTT_UNUSED_ENTRY(120),
738 I40E_PTT(121, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, TCP
, PAY4
),
739 I40E_PTT(122, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, SCTP
, PAY4
),
740 I40E_PTT(123, IP
, IPV6
, NOF
, IP_GRENAT
, IPV6
, NOF
, ICMP
, PAY4
),
742 /* IPv6 --> GRE/NAT -> MAC */
743 I40E_PTT(124, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, NONE
, NOF
, NONE
, PAY3
),
745 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
746 I40E_PTT(125, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, FRG
, NONE
, PAY3
),
747 I40E_PTT(126, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, NONE
, PAY3
),
748 I40E_PTT(127, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, UDP
, PAY4
),
749 I40E_PTT_UNUSED_ENTRY(128),
750 I40E_PTT(129, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, TCP
, PAY4
),
751 I40E_PTT(130, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, SCTP
, PAY4
),
752 I40E_PTT(131, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV4
, NOF
, ICMP
, PAY4
),
754 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
755 I40E_PTT(132, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, FRG
, NONE
, PAY3
),
756 I40E_PTT(133, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, NONE
, PAY3
),
757 I40E_PTT(134, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, UDP
, PAY4
),
758 I40E_PTT_UNUSED_ENTRY(135),
759 I40E_PTT(136, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, TCP
, PAY4
),
760 I40E_PTT(137, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, SCTP
, PAY4
),
761 I40E_PTT(138, IP
, IPV6
, NOF
, IP_GRENAT_MAC
, IPV6
, NOF
, ICMP
, PAY4
),
763 /* IPv6 --> GRE/NAT -> MAC/VLAN */
764 I40E_PTT(139, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, NONE
, NOF
, NONE
, PAY3
),
766 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
767 I40E_PTT(140, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, FRG
, NONE
, PAY3
),
768 I40E_PTT(141, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, NONE
, PAY3
),
769 I40E_PTT(142, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, UDP
, PAY4
),
770 I40E_PTT_UNUSED_ENTRY(143),
771 I40E_PTT(144, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, TCP
, PAY4
),
772 I40E_PTT(145, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, SCTP
, PAY4
),
773 I40E_PTT(146, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV4
, NOF
, ICMP
, PAY4
),
775 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
776 I40E_PTT(147, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, FRG
, NONE
, PAY3
),
777 I40E_PTT(148, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, NONE
, PAY3
),
778 I40E_PTT(149, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, UDP
, PAY4
),
779 I40E_PTT_UNUSED_ENTRY(150),
780 I40E_PTT(151, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, TCP
, PAY4
),
781 I40E_PTT(152, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, SCTP
, PAY4
),
782 I40E_PTT(153, IP
, IPV6
, NOF
, IP_GRENAT_MAC_VLAN
, IPV6
, NOF
, ICMP
, PAY4
),
785 I40E_PTT_UNUSED_ENTRY(154),
786 I40E_PTT_UNUSED_ENTRY(155),
787 I40E_PTT_UNUSED_ENTRY(156),
788 I40E_PTT_UNUSED_ENTRY(157),
789 I40E_PTT_UNUSED_ENTRY(158),
790 I40E_PTT_UNUSED_ENTRY(159),
792 I40E_PTT_UNUSED_ENTRY(160),
793 I40E_PTT_UNUSED_ENTRY(161),
794 I40E_PTT_UNUSED_ENTRY(162),
795 I40E_PTT_UNUSED_ENTRY(163),
796 I40E_PTT_UNUSED_ENTRY(164),
797 I40E_PTT_UNUSED_ENTRY(165),
798 I40E_PTT_UNUSED_ENTRY(166),
799 I40E_PTT_UNUSED_ENTRY(167),
800 I40E_PTT_UNUSED_ENTRY(168),
801 I40E_PTT_UNUSED_ENTRY(169),
803 I40E_PTT_UNUSED_ENTRY(170),
804 I40E_PTT_UNUSED_ENTRY(171),
805 I40E_PTT_UNUSED_ENTRY(172),
806 I40E_PTT_UNUSED_ENTRY(173),
807 I40E_PTT_UNUSED_ENTRY(174),
808 I40E_PTT_UNUSED_ENTRY(175),
809 I40E_PTT_UNUSED_ENTRY(176),
810 I40E_PTT_UNUSED_ENTRY(177),
811 I40E_PTT_UNUSED_ENTRY(178),
812 I40E_PTT_UNUSED_ENTRY(179),
814 I40E_PTT_UNUSED_ENTRY(180),
815 I40E_PTT_UNUSED_ENTRY(181),
816 I40E_PTT_UNUSED_ENTRY(182),
817 I40E_PTT_UNUSED_ENTRY(183),
818 I40E_PTT_UNUSED_ENTRY(184),
819 I40E_PTT_UNUSED_ENTRY(185),
820 I40E_PTT_UNUSED_ENTRY(186),
821 I40E_PTT_UNUSED_ENTRY(187),
822 I40E_PTT_UNUSED_ENTRY(188),
823 I40E_PTT_UNUSED_ENTRY(189),
825 I40E_PTT_UNUSED_ENTRY(190),
826 I40E_PTT_UNUSED_ENTRY(191),
827 I40E_PTT_UNUSED_ENTRY(192),
828 I40E_PTT_UNUSED_ENTRY(193),
829 I40E_PTT_UNUSED_ENTRY(194),
830 I40E_PTT_UNUSED_ENTRY(195),
831 I40E_PTT_UNUSED_ENTRY(196),
832 I40E_PTT_UNUSED_ENTRY(197),
833 I40E_PTT_UNUSED_ENTRY(198),
834 I40E_PTT_UNUSED_ENTRY(199),
836 I40E_PTT_UNUSED_ENTRY(200),
837 I40E_PTT_UNUSED_ENTRY(201),
838 I40E_PTT_UNUSED_ENTRY(202),
839 I40E_PTT_UNUSED_ENTRY(203),
840 I40E_PTT_UNUSED_ENTRY(204),
841 I40E_PTT_UNUSED_ENTRY(205),
842 I40E_PTT_UNUSED_ENTRY(206),
843 I40E_PTT_UNUSED_ENTRY(207),
844 I40E_PTT_UNUSED_ENTRY(208),
845 I40E_PTT_UNUSED_ENTRY(209),
847 I40E_PTT_UNUSED_ENTRY(210),
848 I40E_PTT_UNUSED_ENTRY(211),
849 I40E_PTT_UNUSED_ENTRY(212),
850 I40E_PTT_UNUSED_ENTRY(213),
851 I40E_PTT_UNUSED_ENTRY(214),
852 I40E_PTT_UNUSED_ENTRY(215),
853 I40E_PTT_UNUSED_ENTRY(216),
854 I40E_PTT_UNUSED_ENTRY(217),
855 I40E_PTT_UNUSED_ENTRY(218),
856 I40E_PTT_UNUSED_ENTRY(219),
858 I40E_PTT_UNUSED_ENTRY(220),
859 I40E_PTT_UNUSED_ENTRY(221),
860 I40E_PTT_UNUSED_ENTRY(222),
861 I40E_PTT_UNUSED_ENTRY(223),
862 I40E_PTT_UNUSED_ENTRY(224),
863 I40E_PTT_UNUSED_ENTRY(225),
864 I40E_PTT_UNUSED_ENTRY(226),
865 I40E_PTT_UNUSED_ENTRY(227),
866 I40E_PTT_UNUSED_ENTRY(228),
867 I40E_PTT_UNUSED_ENTRY(229),
869 I40E_PTT_UNUSED_ENTRY(230),
870 I40E_PTT_UNUSED_ENTRY(231),
871 I40E_PTT_UNUSED_ENTRY(232),
872 I40E_PTT_UNUSED_ENTRY(233),
873 I40E_PTT_UNUSED_ENTRY(234),
874 I40E_PTT_UNUSED_ENTRY(235),
875 I40E_PTT_UNUSED_ENTRY(236),
876 I40E_PTT_UNUSED_ENTRY(237),
877 I40E_PTT_UNUSED_ENTRY(238),
878 I40E_PTT_UNUSED_ENTRY(239),
880 I40E_PTT_UNUSED_ENTRY(240),
881 I40E_PTT_UNUSED_ENTRY(241),
882 I40E_PTT_UNUSED_ENTRY(242),
883 I40E_PTT_UNUSED_ENTRY(243),
884 I40E_PTT_UNUSED_ENTRY(244),
885 I40E_PTT_UNUSED_ENTRY(245),
886 I40E_PTT_UNUSED_ENTRY(246),
887 I40E_PTT_UNUSED_ENTRY(247),
888 I40E_PTT_UNUSED_ENTRY(248),
889 I40E_PTT_UNUSED_ENTRY(249),
891 I40E_PTT_UNUSED_ENTRY(250),
892 I40E_PTT_UNUSED_ENTRY(251),
893 I40E_PTT_UNUSED_ENTRY(252),
894 I40E_PTT_UNUSED_ENTRY(253),
895 I40E_PTT_UNUSED_ENTRY(254),
896 I40E_PTT_UNUSED_ENTRY(255)
900 * i40e_init_shared_code - Initialize the shared code
901 * @hw: pointer to hardware structure
903 * This assigns the MAC type and PHY code and inits the NVM.
904 * Does not touch the hardware. This function must be called prior to any
905 * other function in the shared code. The i40e_hw structure should be
906 * memset to 0 prior to calling this function. The following fields in
907 * hw structure should be filled in prior to calling this function:
908 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
909 * subsystem_vendor_id, and revision_id
911 i40e_status
i40e_init_shared_code(struct i40e_hw
*hw
)
913 i40e_status status
= 0;
914 u32 port
, ari
, func_rid
;
916 i40e_set_mac_type(hw
);
918 switch (hw
->mac
.type
) {
923 return I40E_ERR_DEVICE_NOT_SUPPORTED
;
926 hw
->phy
.get_link_info
= true;
928 /* Determine port number and PF number*/
929 port
= (rd32(hw
, I40E_PFGEN_PORTNUM
) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK
)
930 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT
;
932 ari
= (rd32(hw
, I40E_GLPCI_CAPSUP
) & I40E_GLPCI_CAPSUP_ARI_EN_MASK
) >>
933 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT
;
934 func_rid
= rd32(hw
, I40E_PF_FUNC_RID
);
936 hw
->pf_id
= (u8
)(func_rid
& 0xff);
938 hw
->pf_id
= (u8
)(func_rid
& 0x7);
940 if (hw
->mac
.type
== I40E_MAC_X722
)
941 hw
->flags
|= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE
;
943 status
= i40e_init_nvm(hw
);
948 * i40e_aq_mac_address_read - Retrieve the MAC addresses
949 * @hw: pointer to the hw struct
950 * @flags: a return indicator of what addresses were added to the addr store
951 * @addrs: the requestor's mac addr store
952 * @cmd_details: pointer to command details structure or NULL
954 static i40e_status
i40e_aq_mac_address_read(struct i40e_hw
*hw
,
956 struct i40e_aqc_mac_address_read_data
*addrs
,
957 struct i40e_asq_cmd_details
*cmd_details
)
959 struct i40e_aq_desc desc
;
960 struct i40e_aqc_mac_address_read
*cmd_data
=
961 (struct i40e_aqc_mac_address_read
*)&desc
.params
.raw
;
964 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_mac_address_read
);
965 desc
.flags
|= cpu_to_le16(I40E_AQ_FLAG_BUF
);
967 status
= i40e_asq_send_command(hw
, &desc
, addrs
,
968 sizeof(*addrs
), cmd_details
);
969 *flags
= le16_to_cpu(cmd_data
->command_flags
);
975 * i40e_aq_mac_address_write - Change the MAC addresses
976 * @hw: pointer to the hw struct
977 * @flags: indicates which MAC to be written
978 * @mac_addr: address to write
979 * @cmd_details: pointer to command details structure or NULL
981 i40e_status
i40e_aq_mac_address_write(struct i40e_hw
*hw
,
982 u16 flags
, u8
*mac_addr
,
983 struct i40e_asq_cmd_details
*cmd_details
)
985 struct i40e_aq_desc desc
;
986 struct i40e_aqc_mac_address_write
*cmd_data
=
987 (struct i40e_aqc_mac_address_write
*)&desc
.params
.raw
;
990 i40e_fill_default_direct_cmd_desc(&desc
,
991 i40e_aqc_opc_mac_address_write
);
992 cmd_data
->command_flags
= cpu_to_le16(flags
);
993 cmd_data
->mac_sah
= cpu_to_le16((u16
)mac_addr
[0] << 8 | mac_addr
[1]);
994 cmd_data
->mac_sal
= cpu_to_le32(((u32
)mac_addr
[2] << 24) |
995 ((u32
)mac_addr
[3] << 16) |
996 ((u32
)mac_addr
[4] << 8) |
999 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1005 * i40e_get_mac_addr - get MAC address
1006 * @hw: pointer to the HW structure
1007 * @mac_addr: pointer to MAC address
1009 * Reads the adapter's MAC address from register
1011 i40e_status
i40e_get_mac_addr(struct i40e_hw
*hw
, u8
*mac_addr
)
1013 struct i40e_aqc_mac_address_read_data addrs
;
1017 status
= i40e_aq_mac_address_read(hw
, &flags
, &addrs
, NULL
);
1019 if (flags
& I40E_AQC_LAN_ADDR_VALID
)
1020 ether_addr_copy(mac_addr
, addrs
.pf_lan_mac
);
1026 * i40e_get_port_mac_addr - get Port MAC address
1027 * @hw: pointer to the HW structure
1028 * @mac_addr: pointer to Port MAC address
1030 * Reads the adapter's Port MAC address
1032 i40e_status
i40e_get_port_mac_addr(struct i40e_hw
*hw
, u8
*mac_addr
)
1034 struct i40e_aqc_mac_address_read_data addrs
;
1038 status
= i40e_aq_mac_address_read(hw
, &flags
, &addrs
, NULL
);
1042 if (flags
& I40E_AQC_PORT_ADDR_VALID
)
1043 ether_addr_copy(mac_addr
, addrs
.port_mac
);
1045 status
= I40E_ERR_INVALID_MAC_ADDR
;
1051 * i40e_pre_tx_queue_cfg - pre tx queue configure
1052 * @hw: pointer to the HW structure
1053 * @queue: target PF queue index
1054 * @enable: state change request
1056 * Handles hw requirement to indicate intention to enable
1057 * or disable target queue.
1059 void i40e_pre_tx_queue_cfg(struct i40e_hw
*hw
, u32 queue
, bool enable
)
1061 u32 abs_queue_idx
= hw
->func_caps
.base_queue
+ queue
;
1065 if (abs_queue_idx
>= 128) {
1066 reg_block
= abs_queue_idx
/ 128;
1067 abs_queue_idx
%= 128;
1070 reg_val
= rd32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
));
1071 reg_val
&= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK
;
1072 reg_val
|= (abs_queue_idx
<< I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT
);
1075 reg_val
|= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK
;
1077 reg_val
|= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK
;
1079 wr32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
), reg_val
);
1084 * i40e_get_san_mac_addr - get SAN MAC address
1085 * @hw: pointer to the HW structure
1086 * @mac_addr: pointer to SAN MAC address
1088 * Reads the adapter's SAN MAC address from NVM
1090 i40e_status
i40e_get_san_mac_addr(struct i40e_hw
*hw
, u8
*mac_addr
)
1092 struct i40e_aqc_mac_address_read_data addrs
;
1096 status
= i40e_aq_mac_address_read(hw
, &flags
, &addrs
, NULL
);
1100 if (flags
& I40E_AQC_SAN_ADDR_VALID
)
1101 ether_addr_copy(mac_addr
, addrs
.pf_san_mac
);
1103 status
= I40E_ERR_INVALID_MAC_ADDR
;
1110 * i40e_read_pba_string - Reads part number string from EEPROM
1111 * @hw: pointer to hardware structure
1112 * @pba_num: stores the part number string from the EEPROM
1113 * @pba_num_size: part number string buffer length
1115 * Reads the part number string from the EEPROM.
1117 i40e_status
i40e_read_pba_string(struct i40e_hw
*hw
, u8
*pba_num
,
1120 i40e_status status
= 0;
1126 status
= i40e_read_nvm_word(hw
, I40E_SR_PBA_FLAGS
, &pba_word
);
1127 if (status
|| (pba_word
!= 0xFAFA)) {
1128 hw_dbg(hw
, "Failed to read PBA flags or flag is invalid.\n");
1132 status
= i40e_read_nvm_word(hw
, I40E_SR_PBA_BLOCK_PTR
, &pba_ptr
);
1134 hw_dbg(hw
, "Failed to read PBA Block pointer.\n");
1138 status
= i40e_read_nvm_word(hw
, pba_ptr
, &pba_size
);
1140 hw_dbg(hw
, "Failed to read PBA Block size.\n");
1144 /* Subtract one to get PBA word count (PBA Size word is included in
1148 if (pba_num_size
< (((u32
)pba_size
* 2) + 1)) {
1149 hw_dbg(hw
, "Buffer to small for PBA data.\n");
1150 return I40E_ERR_PARAM
;
1153 for (i
= 0; i
< pba_size
; i
++) {
1154 status
= i40e_read_nvm_word(hw
, (pba_ptr
+ 1) + i
, &pba_word
);
1156 hw_dbg(hw
, "Failed to read PBA Block word %d.\n", i
);
1160 pba_num
[(i
* 2)] = (pba_word
>> 8) & 0xFF;
1161 pba_num
[(i
* 2) + 1] = pba_word
& 0xFF;
1163 pba_num
[(pba_size
* 2)] = '\0';
1169 * i40e_get_media_type - Gets media type
1170 * @hw: pointer to the hardware structure
1172 static enum i40e_media_type
i40e_get_media_type(struct i40e_hw
*hw
)
1174 enum i40e_media_type media
;
1176 switch (hw
->phy
.link_info
.phy_type
) {
1177 case I40E_PHY_TYPE_10GBASE_SR
:
1178 case I40E_PHY_TYPE_10GBASE_LR
:
1179 case I40E_PHY_TYPE_1000BASE_SX
:
1180 case I40E_PHY_TYPE_1000BASE_LX
:
1181 case I40E_PHY_TYPE_40GBASE_SR4
:
1182 case I40E_PHY_TYPE_40GBASE_LR4
:
1183 media
= I40E_MEDIA_TYPE_FIBER
;
1185 case I40E_PHY_TYPE_100BASE_TX
:
1186 case I40E_PHY_TYPE_1000BASE_T
:
1187 case I40E_PHY_TYPE_10GBASE_T
:
1188 media
= I40E_MEDIA_TYPE_BASET
;
1190 case I40E_PHY_TYPE_10GBASE_CR1_CU
:
1191 case I40E_PHY_TYPE_40GBASE_CR4_CU
:
1192 case I40E_PHY_TYPE_10GBASE_CR1
:
1193 case I40E_PHY_TYPE_40GBASE_CR4
:
1194 case I40E_PHY_TYPE_10GBASE_SFPP_CU
:
1195 case I40E_PHY_TYPE_40GBASE_AOC
:
1196 case I40E_PHY_TYPE_10GBASE_AOC
:
1197 media
= I40E_MEDIA_TYPE_DA
;
1199 case I40E_PHY_TYPE_1000BASE_KX
:
1200 case I40E_PHY_TYPE_10GBASE_KX4
:
1201 case I40E_PHY_TYPE_10GBASE_KR
:
1202 case I40E_PHY_TYPE_40GBASE_KR4
:
1203 case I40E_PHY_TYPE_20GBASE_KR2
:
1204 media
= I40E_MEDIA_TYPE_BACKPLANE
;
1206 case I40E_PHY_TYPE_SGMII
:
1207 case I40E_PHY_TYPE_XAUI
:
1208 case I40E_PHY_TYPE_XFI
:
1209 case I40E_PHY_TYPE_XLAUI
:
1210 case I40E_PHY_TYPE_XLPPI
:
1212 media
= I40E_MEDIA_TYPE_UNKNOWN
;
1219 #define I40E_PF_RESET_WAIT_COUNT_A0 200
1220 #define I40E_PF_RESET_WAIT_COUNT 200
1222 * i40e_pf_reset - Reset the PF
1223 * @hw: pointer to the hardware structure
1225 * Assuming someone else has triggered a global reset,
1226 * assure the global reset is complete and then reset the PF
1228 i40e_status
i40e_pf_reset(struct i40e_hw
*hw
)
1235 /* Poll for Global Reset steady state in case of recent GRST.
1236 * The grst delay value is in 100ms units, and we'll wait a
1237 * couple counts longer to be sure we don't just miss the end.
1239 grst_del
= (rd32(hw
, I40E_GLGEN_RSTCTL
) &
1240 I40E_GLGEN_RSTCTL_GRSTDEL_MASK
) >>
1241 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT
;
1242 for (cnt
= 0; cnt
< grst_del
+ 10; cnt
++) {
1243 reg
= rd32(hw
, I40E_GLGEN_RSTAT
);
1244 if (!(reg
& I40E_GLGEN_RSTAT_DEVSTATE_MASK
))
1248 if (reg
& I40E_GLGEN_RSTAT_DEVSTATE_MASK
) {
1249 hw_dbg(hw
, "Global reset polling failed to complete.\n");
1250 return I40E_ERR_RESET_FAILED
;
1253 /* Now Wait for the FW to be ready */
1254 for (cnt1
= 0; cnt1
< I40E_PF_RESET_WAIT_COUNT
; cnt1
++) {
1255 reg
= rd32(hw
, I40E_GLNVM_ULD
);
1256 reg
&= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
|
1257 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
);
1258 if (reg
== (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
|
1259 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
)) {
1260 hw_dbg(hw
, "Core and Global modules ready %d\n", cnt1
);
1263 usleep_range(10000, 20000);
1265 if (!(reg
& (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
|
1266 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
))) {
1267 hw_dbg(hw
, "wait for FW Reset complete timedout\n");
1268 hw_dbg(hw
, "I40E_GLNVM_ULD = 0x%x\n", reg
);
1269 return I40E_ERR_RESET_FAILED
;
1272 /* If there was a Global Reset in progress when we got here,
1273 * we don't need to do the PF Reset
1276 if (hw
->revision_id
== 0)
1277 cnt
= I40E_PF_RESET_WAIT_COUNT_A0
;
1279 cnt
= I40E_PF_RESET_WAIT_COUNT
;
1280 reg
= rd32(hw
, I40E_PFGEN_CTRL
);
1281 wr32(hw
, I40E_PFGEN_CTRL
,
1282 (reg
| I40E_PFGEN_CTRL_PFSWR_MASK
));
1283 for (; cnt
; cnt
--) {
1284 reg
= rd32(hw
, I40E_PFGEN_CTRL
);
1285 if (!(reg
& I40E_PFGEN_CTRL_PFSWR_MASK
))
1287 usleep_range(1000, 2000);
1289 if (reg
& I40E_PFGEN_CTRL_PFSWR_MASK
) {
1290 hw_dbg(hw
, "PF reset polling failed to complete.\n");
1291 return I40E_ERR_RESET_FAILED
;
1295 i40e_clear_pxe_mode(hw
);
1301 * i40e_clear_hw - clear out any left over hw state
1302 * @hw: pointer to the hw struct
1304 * Clear queues and interrupts, typically called at init time,
1305 * but after the capabilities have been found so we know how many
1306 * queues and msix vectors have been allocated.
1308 void i40e_clear_hw(struct i40e_hw
*hw
)
1310 u32 num_queues
, base_queue
;
1318 /* get number of interrupts, queues, and VFs */
1319 val
= rd32(hw
, I40E_GLPCI_CNF2
);
1320 num_pf_int
= (val
& I40E_GLPCI_CNF2_MSI_X_PF_N_MASK
) >>
1321 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT
;
1322 num_vf_int
= (val
& I40E_GLPCI_CNF2_MSI_X_VF_N_MASK
) >>
1323 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT
;
1325 val
= rd32(hw
, I40E_PFLAN_QALLOC
);
1326 base_queue
= (val
& I40E_PFLAN_QALLOC_FIRSTQ_MASK
) >>
1327 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT
;
1328 j
= (val
& I40E_PFLAN_QALLOC_LASTQ_MASK
) >>
1329 I40E_PFLAN_QALLOC_LASTQ_SHIFT
;
1330 if (val
& I40E_PFLAN_QALLOC_VALID_MASK
)
1331 num_queues
= (j
- base_queue
) + 1;
1335 val
= rd32(hw
, I40E_PF_VT_PFALLOC
);
1336 i
= (val
& I40E_PF_VT_PFALLOC_FIRSTVF_MASK
) >>
1337 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT
;
1338 j
= (val
& I40E_PF_VT_PFALLOC_LASTVF_MASK
) >>
1339 I40E_PF_VT_PFALLOC_LASTVF_SHIFT
;
1340 if (val
& I40E_PF_VT_PFALLOC_VALID_MASK
)
1341 num_vfs
= (j
- i
) + 1;
1345 /* stop all the interrupts */
1346 wr32(hw
, I40E_PFINT_ICR0_ENA
, 0);
1347 val
= 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT
;
1348 for (i
= 0; i
< num_pf_int
- 2; i
++)
1349 wr32(hw
, I40E_PFINT_DYN_CTLN(i
), val
);
1351 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1352 val
= eol
<< I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT
;
1353 wr32(hw
, I40E_PFINT_LNKLST0
, val
);
1354 for (i
= 0; i
< num_pf_int
- 2; i
++)
1355 wr32(hw
, I40E_PFINT_LNKLSTN(i
), val
);
1356 val
= eol
<< I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT
;
1357 for (i
= 0; i
< num_vfs
; i
++)
1358 wr32(hw
, I40E_VPINT_LNKLST0(i
), val
);
1359 for (i
= 0; i
< num_vf_int
- 2; i
++)
1360 wr32(hw
, I40E_VPINT_LNKLSTN(i
), val
);
1362 /* warn the HW of the coming Tx disables */
1363 for (i
= 0; i
< num_queues
; i
++) {
1364 u32 abs_queue_idx
= base_queue
+ i
;
1367 if (abs_queue_idx
>= 128) {
1368 reg_block
= abs_queue_idx
/ 128;
1369 abs_queue_idx
%= 128;
1372 val
= rd32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
));
1373 val
&= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK
;
1374 val
|= (abs_queue_idx
<< I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT
);
1375 val
|= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK
;
1377 wr32(hw
, I40E_GLLAN_TXPRE_QDIS(reg_block
), val
);
1381 /* stop all the queues */
1382 for (i
= 0; i
< num_queues
; i
++) {
1383 wr32(hw
, I40E_QINT_TQCTL(i
), 0);
1384 wr32(hw
, I40E_QTX_ENA(i
), 0);
1385 wr32(hw
, I40E_QINT_RQCTL(i
), 0);
1386 wr32(hw
, I40E_QRX_ENA(i
), 0);
1389 /* short wait for all queue disables to settle */
1394 * i40e_clear_pxe_mode - clear pxe operations mode
1395 * @hw: pointer to the hw struct
1397 * Make sure all PXE mode settings are cleared, including things
1398 * like descriptor fetch/write-back mode.
1400 void i40e_clear_pxe_mode(struct i40e_hw
*hw
)
1404 if (i40e_check_asq_alive(hw
))
1405 i40e_aq_clear_pxe_mode(hw
, NULL
);
1407 /* Clear single descriptor fetch/write-back mode */
1408 reg
= rd32(hw
, I40E_GLLAN_RCTL_0
);
1410 if (hw
->revision_id
== 0) {
1411 /* As a work around clear PXE_MODE instead of setting it */
1412 wr32(hw
, I40E_GLLAN_RCTL_0
, (reg
& (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK
)));
1414 wr32(hw
, I40E_GLLAN_RCTL_0
, (reg
| I40E_GLLAN_RCTL_0_PXE_MODE_MASK
));
1419 * i40e_led_is_mine - helper to find matching led
1420 * @hw: pointer to the hw struct
1421 * @idx: index into GPIO registers
1423 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1425 static u32
i40e_led_is_mine(struct i40e_hw
*hw
, int idx
)
1430 if (!hw
->func_caps
.led
[idx
])
1433 gpio_val
= rd32(hw
, I40E_GLGEN_GPIO_CTL(idx
));
1434 port
= (gpio_val
& I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK
) >>
1435 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT
;
1437 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1438 * if it is not our port then ignore
1440 if ((gpio_val
& I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK
) ||
1447 #define I40E_COMBINED_ACTIVITY 0xA
1448 #define I40E_FILTER_ACTIVITY 0xE
1449 #define I40E_LINK_ACTIVITY 0xC
1450 #define I40E_MAC_ACTIVITY 0xD
1451 #define I40E_LED0 22
1454 * i40e_led_get - return current on/off mode
1455 * @hw: pointer to the hw struct
1457 * The value returned is the 'mode' field as defined in the
1458 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1459 * values are variations of possible behaviors relating to
1460 * blink, link, and wire.
1462 u32
i40e_led_get(struct i40e_hw
*hw
)
1464 u32 current_mode
= 0;
1468 /* as per the documentation GPIO 22-29 are the LED
1469 * GPIO pins named LED0..LED7
1471 for (i
= I40E_LED0
; i
<= I40E_GLGEN_GPIO_CTL_MAX_INDEX
; i
++) {
1472 u32 gpio_val
= i40e_led_is_mine(hw
, i
);
1477 /* ignore gpio LED src mode entries related to the activity
1480 current_mode
= ((gpio_val
& I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
)
1481 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
);
1482 switch (current_mode
) {
1483 case I40E_COMBINED_ACTIVITY
:
1484 case I40E_FILTER_ACTIVITY
:
1485 case I40E_MAC_ACTIVITY
:
1491 mode
= (gpio_val
& I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
) >>
1492 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
;
1500 * i40e_led_set - set new on/off mode
1501 * @hw: pointer to the hw struct
1502 * @mode: 0=off, 0xf=on (else see manual for mode details)
1503 * @blink: true if the LED should blink when on, false if steady
1505 * if this function is used to turn on the blink it should
1506 * be used to disable the blink when restoring the original state.
1508 void i40e_led_set(struct i40e_hw
*hw
, u32 mode
, bool blink
)
1510 u32 current_mode
= 0;
1513 if (mode
& 0xfffffff0)
1514 hw_dbg(hw
, "invalid mode passed in %X\n", mode
);
1516 /* as per the documentation GPIO 22-29 are the LED
1517 * GPIO pins named LED0..LED7
1519 for (i
= I40E_LED0
; i
<= I40E_GLGEN_GPIO_CTL_MAX_INDEX
; i
++) {
1520 u32 gpio_val
= i40e_led_is_mine(hw
, i
);
1525 /* ignore gpio LED src mode entries related to the activity
1528 current_mode
= ((gpio_val
& I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
)
1529 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
);
1530 switch (current_mode
) {
1531 case I40E_COMBINED_ACTIVITY
:
1532 case I40E_FILTER_ACTIVITY
:
1533 case I40E_MAC_ACTIVITY
:
1539 gpio_val
&= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
;
1540 /* this & is a bit of paranoia, but serves as a range check */
1541 gpio_val
|= ((mode
<< I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
) &
1542 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
);
1544 if (mode
== I40E_LINK_ACTIVITY
)
1548 gpio_val
|= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT
);
1550 gpio_val
&= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT
);
1552 wr32(hw
, I40E_GLGEN_GPIO_CTL(i
), gpio_val
);
1557 /* Admin command wrappers */
1560 * i40e_aq_get_phy_capabilities
1561 * @hw: pointer to the hw struct
1562 * @abilities: structure for PHY capabilities to be filled
1563 * @qualified_modules: report Qualified Modules
1564 * @report_init: report init capabilities (active are default)
1565 * @cmd_details: pointer to command details structure or NULL
1567 * Returns the various PHY abilities supported on the Port.
1569 i40e_status
i40e_aq_get_phy_capabilities(struct i40e_hw
*hw
,
1570 bool qualified_modules
, bool report_init
,
1571 struct i40e_aq_get_phy_abilities_resp
*abilities
,
1572 struct i40e_asq_cmd_details
*cmd_details
)
1574 struct i40e_aq_desc desc
;
1576 u16 abilities_size
= sizeof(struct i40e_aq_get_phy_abilities_resp
);
1579 return I40E_ERR_PARAM
;
1581 i40e_fill_default_direct_cmd_desc(&desc
,
1582 i40e_aqc_opc_get_phy_abilities
);
1584 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
1585 if (abilities_size
> I40E_AQ_LARGE_BUF
)
1586 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
1588 if (qualified_modules
)
1589 desc
.params
.external
.param0
|=
1590 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES
);
1593 desc
.params
.external
.param0
|=
1594 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES
);
1596 status
= i40e_asq_send_command(hw
, &desc
, abilities
, abilities_size
,
1599 if (hw
->aq
.asq_last_status
== I40E_AQ_RC_EIO
)
1600 status
= I40E_ERR_UNKNOWN_PHY
;
1603 hw
->phy
.phy_types
= le32_to_cpu(abilities
->phy_type
);
1609 * i40e_aq_set_phy_config
1610 * @hw: pointer to the hw struct
1611 * @config: structure with PHY configuration to be set
1612 * @cmd_details: pointer to command details structure or NULL
1614 * Set the various PHY configuration parameters
1615 * supported on the Port.One or more of the Set PHY config parameters may be
1616 * ignored in an MFP mode as the PF may not have the privilege to set some
1617 * of the PHY Config parameters. This status will be indicated by the
1620 enum i40e_status_code
i40e_aq_set_phy_config(struct i40e_hw
*hw
,
1621 struct i40e_aq_set_phy_config
*config
,
1622 struct i40e_asq_cmd_details
*cmd_details
)
1624 struct i40e_aq_desc desc
;
1625 struct i40e_aq_set_phy_config
*cmd
=
1626 (struct i40e_aq_set_phy_config
*)&desc
.params
.raw
;
1627 enum i40e_status_code status
;
1630 return I40E_ERR_PARAM
;
1632 i40e_fill_default_direct_cmd_desc(&desc
,
1633 i40e_aqc_opc_set_phy_config
);
1637 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1644 * @hw: pointer to the hw struct
1646 * Set the requested flow control mode using set_phy_config.
1648 enum i40e_status_code
i40e_set_fc(struct i40e_hw
*hw
, u8
*aq_failures
,
1649 bool atomic_restart
)
1651 enum i40e_fc_mode fc_mode
= hw
->fc
.requested_mode
;
1652 struct i40e_aq_get_phy_abilities_resp abilities
;
1653 struct i40e_aq_set_phy_config config
;
1654 enum i40e_status_code status
;
1655 u8 pause_mask
= 0x0;
1661 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_TX
;
1662 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_RX
;
1664 case I40E_FC_RX_PAUSE
:
1665 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_RX
;
1667 case I40E_FC_TX_PAUSE
:
1668 pause_mask
|= I40E_AQ_PHY_FLAG_PAUSE_TX
;
1674 /* Get the current phy config */
1675 status
= i40e_aq_get_phy_capabilities(hw
, false, false, &abilities
,
1678 *aq_failures
|= I40E_SET_FC_AQ_FAIL_GET
;
1682 memset(&config
, 0, sizeof(struct i40e_aq_set_phy_config
));
1683 /* clear the old pause settings */
1684 config
.abilities
= abilities
.abilities
& ~(I40E_AQ_PHY_FLAG_PAUSE_TX
) &
1685 ~(I40E_AQ_PHY_FLAG_PAUSE_RX
);
1686 /* set the new abilities */
1687 config
.abilities
|= pause_mask
;
1688 /* If the abilities have changed, then set the new config */
1689 if (config
.abilities
!= abilities
.abilities
) {
1690 /* Auto restart link so settings take effect */
1692 config
.abilities
|= I40E_AQ_PHY_ENABLE_ATOMIC_LINK
;
1693 /* Copy over all the old settings */
1694 config
.phy_type
= abilities
.phy_type
;
1695 config
.link_speed
= abilities
.link_speed
;
1696 config
.eee_capability
= abilities
.eee_capability
;
1697 config
.eeer
= abilities
.eeer_val
;
1698 config
.low_power_ctrl
= abilities
.d3_lpan
;
1699 status
= i40e_aq_set_phy_config(hw
, &config
, NULL
);
1702 *aq_failures
|= I40E_SET_FC_AQ_FAIL_SET
;
1704 /* Update the link info */
1705 status
= i40e_update_link_info(hw
);
1707 /* Wait a little bit (on 40G cards it sometimes takes a really
1708 * long time for link to come back from the atomic reset)
1712 status
= i40e_update_link_info(hw
);
1715 *aq_failures
|= I40E_SET_FC_AQ_FAIL_UPDATE
;
1721 * i40e_aq_clear_pxe_mode
1722 * @hw: pointer to the hw struct
1723 * @cmd_details: pointer to command details structure or NULL
1725 * Tell the firmware that the driver is taking over from PXE
1727 i40e_status
i40e_aq_clear_pxe_mode(struct i40e_hw
*hw
,
1728 struct i40e_asq_cmd_details
*cmd_details
)
1731 struct i40e_aq_desc desc
;
1732 struct i40e_aqc_clear_pxe
*cmd
=
1733 (struct i40e_aqc_clear_pxe
*)&desc
.params
.raw
;
1735 i40e_fill_default_direct_cmd_desc(&desc
,
1736 i40e_aqc_opc_clear_pxe_mode
);
1740 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1742 wr32(hw
, I40E_GLLAN_RCTL_0
, 0x1);
1748 * i40e_aq_set_link_restart_an
1749 * @hw: pointer to the hw struct
1750 * @enable_link: if true: enable link, if false: disable link
1751 * @cmd_details: pointer to command details structure or NULL
1753 * Sets up the link and restarts the Auto-Negotiation over the link.
1755 i40e_status
i40e_aq_set_link_restart_an(struct i40e_hw
*hw
,
1757 struct i40e_asq_cmd_details
*cmd_details
)
1759 struct i40e_aq_desc desc
;
1760 struct i40e_aqc_set_link_restart_an
*cmd
=
1761 (struct i40e_aqc_set_link_restart_an
*)&desc
.params
.raw
;
1764 i40e_fill_default_direct_cmd_desc(&desc
,
1765 i40e_aqc_opc_set_link_restart_an
);
1767 cmd
->command
= I40E_AQ_PHY_RESTART_AN
;
1769 cmd
->command
|= I40E_AQ_PHY_LINK_ENABLE
;
1771 cmd
->command
&= ~I40E_AQ_PHY_LINK_ENABLE
;
1773 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1779 * i40e_aq_get_link_info
1780 * @hw: pointer to the hw struct
1781 * @enable_lse: enable/disable LinkStatusEvent reporting
1782 * @link: pointer to link status structure - optional
1783 * @cmd_details: pointer to command details structure or NULL
1785 * Returns the link status of the adapter.
1787 i40e_status
i40e_aq_get_link_info(struct i40e_hw
*hw
,
1788 bool enable_lse
, struct i40e_link_status
*link
,
1789 struct i40e_asq_cmd_details
*cmd_details
)
1791 struct i40e_aq_desc desc
;
1792 struct i40e_aqc_get_link_status
*resp
=
1793 (struct i40e_aqc_get_link_status
*)&desc
.params
.raw
;
1794 struct i40e_link_status
*hw_link_info
= &hw
->phy
.link_info
;
1796 bool tx_pause
, rx_pause
;
1799 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_get_link_status
);
1802 command_flags
= I40E_AQ_LSE_ENABLE
;
1804 command_flags
= I40E_AQ_LSE_DISABLE
;
1805 resp
->command_flags
= cpu_to_le16(command_flags
);
1807 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1810 goto aq_get_link_info_exit
;
1812 /* save off old link status information */
1813 hw
->phy
.link_info_old
= *hw_link_info
;
1815 /* update link status */
1816 hw_link_info
->phy_type
= (enum i40e_aq_phy_type
)resp
->phy_type
;
1817 hw
->phy
.media_type
= i40e_get_media_type(hw
);
1818 hw_link_info
->link_speed
= (enum i40e_aq_link_speed
)resp
->link_speed
;
1819 hw_link_info
->link_info
= resp
->link_info
;
1820 hw_link_info
->an_info
= resp
->an_info
;
1821 hw_link_info
->ext_info
= resp
->ext_info
;
1822 hw_link_info
->loopback
= resp
->loopback
;
1823 hw_link_info
->max_frame_size
= le16_to_cpu(resp
->max_frame_size
);
1824 hw_link_info
->pacing
= resp
->config
& I40E_AQ_CONFIG_PACING_MASK
;
1826 /* update fc info */
1827 tx_pause
= !!(resp
->an_info
& I40E_AQ_LINK_PAUSE_TX
);
1828 rx_pause
= !!(resp
->an_info
& I40E_AQ_LINK_PAUSE_RX
);
1829 if (tx_pause
& rx_pause
)
1830 hw
->fc
.current_mode
= I40E_FC_FULL
;
1832 hw
->fc
.current_mode
= I40E_FC_TX_PAUSE
;
1834 hw
->fc
.current_mode
= I40E_FC_RX_PAUSE
;
1836 hw
->fc
.current_mode
= I40E_FC_NONE
;
1838 if (resp
->config
& I40E_AQ_CONFIG_CRC_ENA
)
1839 hw_link_info
->crc_enable
= true;
1841 hw_link_info
->crc_enable
= false;
1843 if (resp
->command_flags
& cpu_to_le16(I40E_AQ_LSE_ENABLE
))
1844 hw_link_info
->lse_enable
= true;
1846 hw_link_info
->lse_enable
= false;
1848 if ((hw
->aq
.fw_maj_ver
< 4 || (hw
->aq
.fw_maj_ver
== 4 &&
1849 hw
->aq
.fw_min_ver
< 40)) && hw_link_info
->phy_type
== 0xE)
1850 hw_link_info
->phy_type
= I40E_PHY_TYPE_10GBASE_SFPP_CU
;
1852 /* save link status information */
1854 *link
= *hw_link_info
;
1856 /* flag cleared so helper functions don't call AQ again */
1857 hw
->phy
.get_link_info
= false;
1859 aq_get_link_info_exit
:
1864 * i40e_aq_set_phy_int_mask
1865 * @hw: pointer to the hw struct
1866 * @mask: interrupt mask to be set
1867 * @cmd_details: pointer to command details structure or NULL
1869 * Set link interrupt mask.
1871 i40e_status
i40e_aq_set_phy_int_mask(struct i40e_hw
*hw
,
1873 struct i40e_asq_cmd_details
*cmd_details
)
1875 struct i40e_aq_desc desc
;
1876 struct i40e_aqc_set_phy_int_mask
*cmd
=
1877 (struct i40e_aqc_set_phy_int_mask
*)&desc
.params
.raw
;
1880 i40e_fill_default_direct_cmd_desc(&desc
,
1881 i40e_aqc_opc_set_phy_int_mask
);
1883 cmd
->event_mask
= cpu_to_le16(mask
);
1885 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1892 * @hw: pointer to the hw struct
1893 * @vsi_ctx: pointer to a vsi context struct
1894 * @cmd_details: pointer to command details structure or NULL
1896 * Add a VSI context to the hardware.
1898 i40e_status
i40e_aq_add_vsi(struct i40e_hw
*hw
,
1899 struct i40e_vsi_context
*vsi_ctx
,
1900 struct i40e_asq_cmd_details
*cmd_details
)
1902 struct i40e_aq_desc desc
;
1903 struct i40e_aqc_add_get_update_vsi
*cmd
=
1904 (struct i40e_aqc_add_get_update_vsi
*)&desc
.params
.raw
;
1905 struct i40e_aqc_add_get_update_vsi_completion
*resp
=
1906 (struct i40e_aqc_add_get_update_vsi_completion
*)
1910 i40e_fill_default_direct_cmd_desc(&desc
,
1911 i40e_aqc_opc_add_vsi
);
1913 cmd
->uplink_seid
= cpu_to_le16(vsi_ctx
->uplink_seid
);
1914 cmd
->connection_type
= vsi_ctx
->connection_type
;
1915 cmd
->vf_id
= vsi_ctx
->vf_num
;
1916 cmd
->vsi_flags
= cpu_to_le16(vsi_ctx
->flags
);
1918 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
1920 status
= i40e_asq_send_command(hw
, &desc
, &vsi_ctx
->info
,
1921 sizeof(vsi_ctx
->info
), cmd_details
);
1924 goto aq_add_vsi_exit
;
1926 vsi_ctx
->seid
= le16_to_cpu(resp
->seid
);
1927 vsi_ctx
->vsi_number
= le16_to_cpu(resp
->vsi_number
);
1928 vsi_ctx
->vsis_allocated
= le16_to_cpu(resp
->vsi_used
);
1929 vsi_ctx
->vsis_unallocated
= le16_to_cpu(resp
->vsi_free
);
1936 * i40e_aq_set_vsi_unicast_promiscuous
1937 * @hw: pointer to the hw struct
1939 * @set: set unicast promiscuous enable/disable
1940 * @cmd_details: pointer to command details structure or NULL
1942 i40e_status
i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw
*hw
,
1944 struct i40e_asq_cmd_details
*cmd_details
)
1946 struct i40e_aq_desc desc
;
1947 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
1948 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
1952 i40e_fill_default_direct_cmd_desc(&desc
,
1953 i40e_aqc_opc_set_vsi_promiscuous_modes
);
1956 flags
|= I40E_AQC_SET_VSI_PROMISC_UNICAST
;
1958 cmd
->promiscuous_flags
= cpu_to_le16(flags
);
1960 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST
);
1962 cmd
->seid
= cpu_to_le16(seid
);
1963 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
1969 * i40e_aq_set_vsi_multicast_promiscuous
1970 * @hw: pointer to the hw struct
1972 * @set: set multicast promiscuous enable/disable
1973 * @cmd_details: pointer to command details structure or NULL
1975 i40e_status
i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw
*hw
,
1976 u16 seid
, bool set
, struct i40e_asq_cmd_details
*cmd_details
)
1978 struct i40e_aq_desc desc
;
1979 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
1980 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
1984 i40e_fill_default_direct_cmd_desc(&desc
,
1985 i40e_aqc_opc_set_vsi_promiscuous_modes
);
1988 flags
|= I40E_AQC_SET_VSI_PROMISC_MULTICAST
;
1990 cmd
->promiscuous_flags
= cpu_to_le16(flags
);
1992 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST
);
1994 cmd
->seid
= cpu_to_le16(seid
);
1995 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2001 * i40e_aq_set_vsi_broadcast
2002 * @hw: pointer to the hw struct
2004 * @set_filter: true to set filter, false to clear filter
2005 * @cmd_details: pointer to command details structure or NULL
2007 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2009 i40e_status
i40e_aq_set_vsi_broadcast(struct i40e_hw
*hw
,
2010 u16 seid
, bool set_filter
,
2011 struct i40e_asq_cmd_details
*cmd_details
)
2013 struct i40e_aq_desc desc
;
2014 struct i40e_aqc_set_vsi_promiscuous_modes
*cmd
=
2015 (struct i40e_aqc_set_vsi_promiscuous_modes
*)&desc
.params
.raw
;
2018 i40e_fill_default_direct_cmd_desc(&desc
,
2019 i40e_aqc_opc_set_vsi_promiscuous_modes
);
2022 cmd
->promiscuous_flags
2023 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST
);
2025 cmd
->promiscuous_flags
2026 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST
);
2028 cmd
->valid_flags
= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST
);
2029 cmd
->seid
= cpu_to_le16(seid
);
2030 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2036 * i40e_get_vsi_params - get VSI configuration info
2037 * @hw: pointer to the hw struct
2038 * @vsi_ctx: pointer to a vsi context struct
2039 * @cmd_details: pointer to command details structure or NULL
2041 i40e_status
i40e_aq_get_vsi_params(struct i40e_hw
*hw
,
2042 struct i40e_vsi_context
*vsi_ctx
,
2043 struct i40e_asq_cmd_details
*cmd_details
)
2045 struct i40e_aq_desc desc
;
2046 struct i40e_aqc_add_get_update_vsi
*cmd
=
2047 (struct i40e_aqc_add_get_update_vsi
*)&desc
.params
.raw
;
2048 struct i40e_aqc_add_get_update_vsi_completion
*resp
=
2049 (struct i40e_aqc_add_get_update_vsi_completion
*)
2053 i40e_fill_default_direct_cmd_desc(&desc
,
2054 i40e_aqc_opc_get_vsi_parameters
);
2056 cmd
->uplink_seid
= cpu_to_le16(vsi_ctx
->seid
);
2058 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2060 status
= i40e_asq_send_command(hw
, &desc
, &vsi_ctx
->info
,
2061 sizeof(vsi_ctx
->info
), NULL
);
2064 goto aq_get_vsi_params_exit
;
2066 vsi_ctx
->seid
= le16_to_cpu(resp
->seid
);
2067 vsi_ctx
->vsi_number
= le16_to_cpu(resp
->vsi_number
);
2068 vsi_ctx
->vsis_allocated
= le16_to_cpu(resp
->vsi_used
);
2069 vsi_ctx
->vsis_unallocated
= le16_to_cpu(resp
->vsi_free
);
2071 aq_get_vsi_params_exit
:
2076 * i40e_aq_update_vsi_params
2077 * @hw: pointer to the hw struct
2078 * @vsi_ctx: pointer to a vsi context struct
2079 * @cmd_details: pointer to command details structure or NULL
2081 * Update a VSI context.
2083 i40e_status
i40e_aq_update_vsi_params(struct i40e_hw
*hw
,
2084 struct i40e_vsi_context
*vsi_ctx
,
2085 struct i40e_asq_cmd_details
*cmd_details
)
2087 struct i40e_aq_desc desc
;
2088 struct i40e_aqc_add_get_update_vsi
*cmd
=
2089 (struct i40e_aqc_add_get_update_vsi
*)&desc
.params
.raw
;
2092 i40e_fill_default_direct_cmd_desc(&desc
,
2093 i40e_aqc_opc_update_vsi_parameters
);
2094 cmd
->uplink_seid
= cpu_to_le16(vsi_ctx
->seid
);
2096 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
2098 status
= i40e_asq_send_command(hw
, &desc
, &vsi_ctx
->info
,
2099 sizeof(vsi_ctx
->info
), cmd_details
);
2105 * i40e_aq_get_switch_config
2106 * @hw: pointer to the hardware structure
2107 * @buf: pointer to the result buffer
2108 * @buf_size: length of input buffer
2109 * @start_seid: seid to start for the report, 0 == beginning
2110 * @cmd_details: pointer to command details structure or NULL
2112 * Fill the buf with switch configuration returned from AdminQ command
2114 i40e_status
i40e_aq_get_switch_config(struct i40e_hw
*hw
,
2115 struct i40e_aqc_get_switch_config_resp
*buf
,
2116 u16 buf_size
, u16
*start_seid
,
2117 struct i40e_asq_cmd_details
*cmd_details
)
2119 struct i40e_aq_desc desc
;
2120 struct i40e_aqc_switch_seid
*scfg
=
2121 (struct i40e_aqc_switch_seid
*)&desc
.params
.raw
;
2124 i40e_fill_default_direct_cmd_desc(&desc
,
2125 i40e_aqc_opc_get_switch_config
);
2126 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2127 if (buf_size
> I40E_AQ_LARGE_BUF
)
2128 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2129 scfg
->seid
= cpu_to_le16(*start_seid
);
2131 status
= i40e_asq_send_command(hw
, &desc
, buf
, buf_size
, cmd_details
);
2132 *start_seid
= le16_to_cpu(scfg
->seid
);
2138 * i40e_aq_get_firmware_version
2139 * @hw: pointer to the hw struct
2140 * @fw_major_version: firmware major version
2141 * @fw_minor_version: firmware minor version
2142 * @fw_build: firmware build number
2143 * @api_major_version: major queue version
2144 * @api_minor_version: minor queue version
2145 * @cmd_details: pointer to command details structure or NULL
2147 * Get the firmware version from the admin queue commands
2149 i40e_status
i40e_aq_get_firmware_version(struct i40e_hw
*hw
,
2150 u16
*fw_major_version
, u16
*fw_minor_version
,
2152 u16
*api_major_version
, u16
*api_minor_version
,
2153 struct i40e_asq_cmd_details
*cmd_details
)
2155 struct i40e_aq_desc desc
;
2156 struct i40e_aqc_get_version
*resp
=
2157 (struct i40e_aqc_get_version
*)&desc
.params
.raw
;
2160 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_get_version
);
2162 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2165 if (fw_major_version
)
2166 *fw_major_version
= le16_to_cpu(resp
->fw_major
);
2167 if (fw_minor_version
)
2168 *fw_minor_version
= le16_to_cpu(resp
->fw_minor
);
2170 *fw_build
= le32_to_cpu(resp
->fw_build
);
2171 if (api_major_version
)
2172 *api_major_version
= le16_to_cpu(resp
->api_major
);
2173 if (api_minor_version
)
2174 *api_minor_version
= le16_to_cpu(resp
->api_minor
);
2181 * i40e_aq_send_driver_version
2182 * @hw: pointer to the hw struct
2183 * @dv: driver's major, minor version
2184 * @cmd_details: pointer to command details structure or NULL
2186 * Send the driver version to the firmware
2188 i40e_status
i40e_aq_send_driver_version(struct i40e_hw
*hw
,
2189 struct i40e_driver_version
*dv
,
2190 struct i40e_asq_cmd_details
*cmd_details
)
2192 struct i40e_aq_desc desc
;
2193 struct i40e_aqc_driver_version
*cmd
=
2194 (struct i40e_aqc_driver_version
*)&desc
.params
.raw
;
2199 return I40E_ERR_PARAM
;
2201 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_driver_version
);
2203 desc
.flags
|= cpu_to_le16(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
);
2204 cmd
->driver_major_ver
= dv
->major_version
;
2205 cmd
->driver_minor_ver
= dv
->minor_version
;
2206 cmd
->driver_build_ver
= dv
->build_version
;
2207 cmd
->driver_subbuild_ver
= dv
->subbuild_version
;
2210 while (len
< sizeof(dv
->driver_string
) &&
2211 (dv
->driver_string
[len
] < 0x80) &&
2212 dv
->driver_string
[len
])
2214 status
= i40e_asq_send_command(hw
, &desc
, dv
->driver_string
,
2221 * i40e_get_link_status - get status of the HW network link
2222 * @hw: pointer to the hw struct
2223 * @link_up: pointer to bool (true/false = linkup/linkdown)
2225 * Variable link_up true if link is up, false if link is down.
2226 * The variable link_up is invalid if returned value of status != 0
2228 * Side effect: LinkStatusEvent reporting becomes enabled
2230 i40e_status
i40e_get_link_status(struct i40e_hw
*hw
, bool *link_up
)
2232 i40e_status status
= 0;
2234 if (hw
->phy
.get_link_info
) {
2235 status
= i40e_update_link_info(hw
);
2238 i40e_debug(hw
, I40E_DEBUG_LINK
, "get link failed: status %d\n",
2242 *link_up
= hw
->phy
.link_info
.link_info
& I40E_AQ_LINK_UP
;
2248 * i40e_updatelink_status - update status of the HW network link
2249 * @hw: pointer to the hw struct
2251 i40e_status
i40e_update_link_info(struct i40e_hw
*hw
)
2253 struct i40e_aq_get_phy_abilities_resp abilities
;
2254 i40e_status status
= 0;
2256 status
= i40e_aq_get_link_info(hw
, true, NULL
, NULL
);
2260 if (hw
->phy
.link_info
.link_info
& I40E_AQ_MEDIA_AVAILABLE
) {
2261 status
= i40e_aq_get_phy_capabilities(hw
, false, false,
2266 memcpy(hw
->phy
.link_info
.module_type
, &abilities
.module_type
,
2267 sizeof(hw
->phy
.link_info
.module_type
));
2274 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2275 * @hw: pointer to the hw struct
2276 * @uplink_seid: the MAC or other gizmo SEID
2277 * @downlink_seid: the VSI SEID
2278 * @enabled_tc: bitmap of TCs to be enabled
2279 * @default_port: true for default port VSI, false for control port
2280 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2281 * @veb_seid: pointer to where to put the resulting VEB SEID
2282 * @cmd_details: pointer to command details structure or NULL
2284 * This asks the FW to add a VEB between the uplink and downlink
2285 * elements. If the uplink SEID is 0, this will be a floating VEB.
2287 i40e_status
i40e_aq_add_veb(struct i40e_hw
*hw
, u16 uplink_seid
,
2288 u16 downlink_seid
, u8 enabled_tc
,
2289 bool default_port
, bool enable_l2_filtering
,
2291 struct i40e_asq_cmd_details
*cmd_details
)
2293 struct i40e_aq_desc desc
;
2294 struct i40e_aqc_add_veb
*cmd
=
2295 (struct i40e_aqc_add_veb
*)&desc
.params
.raw
;
2296 struct i40e_aqc_add_veb_completion
*resp
=
2297 (struct i40e_aqc_add_veb_completion
*)&desc
.params
.raw
;
2301 /* SEIDs need to either both be set or both be 0 for floating VEB */
2302 if (!!uplink_seid
!= !!downlink_seid
)
2303 return I40E_ERR_PARAM
;
2305 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_add_veb
);
2307 cmd
->uplink_seid
= cpu_to_le16(uplink_seid
);
2308 cmd
->downlink_seid
= cpu_to_le16(downlink_seid
);
2309 cmd
->enable_tcs
= enabled_tc
;
2311 veb_flags
|= I40E_AQC_ADD_VEB_FLOATING
;
2313 veb_flags
|= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT
;
2315 veb_flags
|= I40E_AQC_ADD_VEB_PORT_TYPE_DATA
;
2317 if (enable_l2_filtering
)
2318 veb_flags
|= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER
;
2320 cmd
->veb_flags
= cpu_to_le16(veb_flags
);
2322 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2324 if (!status
&& veb_seid
)
2325 *veb_seid
= le16_to_cpu(resp
->veb_seid
);
2331 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2332 * @hw: pointer to the hw struct
2333 * @veb_seid: the SEID of the VEB to query
2334 * @switch_id: the uplink switch id
2335 * @floating: set to true if the VEB is floating
2336 * @statistic_index: index of the stats counter block for this VEB
2337 * @vebs_used: number of VEB's used by function
2338 * @vebs_free: total VEB's not reserved by any function
2339 * @cmd_details: pointer to command details structure or NULL
2341 * This retrieves the parameters for a particular VEB, specified by
2342 * uplink_seid, and returns them to the caller.
2344 i40e_status
i40e_aq_get_veb_parameters(struct i40e_hw
*hw
,
2345 u16 veb_seid
, u16
*switch_id
,
2346 bool *floating
, u16
*statistic_index
,
2347 u16
*vebs_used
, u16
*vebs_free
,
2348 struct i40e_asq_cmd_details
*cmd_details
)
2350 struct i40e_aq_desc desc
;
2351 struct i40e_aqc_get_veb_parameters_completion
*cmd_resp
=
2352 (struct i40e_aqc_get_veb_parameters_completion
*)
2357 return I40E_ERR_PARAM
;
2359 i40e_fill_default_direct_cmd_desc(&desc
,
2360 i40e_aqc_opc_get_veb_parameters
);
2361 cmd_resp
->seid
= cpu_to_le16(veb_seid
);
2363 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2368 *switch_id
= le16_to_cpu(cmd_resp
->switch_id
);
2369 if (statistic_index
)
2370 *statistic_index
= le16_to_cpu(cmd_resp
->statistic_index
);
2372 *vebs_used
= le16_to_cpu(cmd_resp
->vebs_used
);
2374 *vebs_free
= le16_to_cpu(cmd_resp
->vebs_free
);
2376 u16 flags
= le16_to_cpu(cmd_resp
->veb_flags
);
2378 if (flags
& I40E_AQC_ADD_VEB_FLOATING
)
2389 * i40e_aq_add_macvlan
2390 * @hw: pointer to the hw struct
2391 * @seid: VSI for the mac address
2392 * @mv_list: list of macvlans to be added
2393 * @count: length of the list
2394 * @cmd_details: pointer to command details structure or NULL
2396 * Add MAC/VLAN addresses to the HW filtering
2398 i40e_status
i40e_aq_add_macvlan(struct i40e_hw
*hw
, u16 seid
,
2399 struct i40e_aqc_add_macvlan_element_data
*mv_list
,
2400 u16 count
, struct i40e_asq_cmd_details
*cmd_details
)
2402 struct i40e_aq_desc desc
;
2403 struct i40e_aqc_macvlan
*cmd
=
2404 (struct i40e_aqc_macvlan
*)&desc
.params
.raw
;
2408 if (count
== 0 || !mv_list
|| !hw
)
2409 return I40E_ERR_PARAM
;
2411 buf_size
= count
* sizeof(*mv_list
);
2413 /* prep the rest of the request */
2414 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_add_macvlan
);
2415 cmd
->num_addresses
= cpu_to_le16(count
);
2416 cmd
->seid
[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID
| seid
);
2420 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
2421 if (buf_size
> I40E_AQ_LARGE_BUF
)
2422 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2424 status
= i40e_asq_send_command(hw
, &desc
, mv_list
, buf_size
,
2431 * i40e_aq_remove_macvlan
2432 * @hw: pointer to the hw struct
2433 * @seid: VSI for the mac address
2434 * @mv_list: list of macvlans to be removed
2435 * @count: length of the list
2436 * @cmd_details: pointer to command details structure or NULL
2438 * Remove MAC/VLAN addresses from the HW filtering
2440 i40e_status
i40e_aq_remove_macvlan(struct i40e_hw
*hw
, u16 seid
,
2441 struct i40e_aqc_remove_macvlan_element_data
*mv_list
,
2442 u16 count
, struct i40e_asq_cmd_details
*cmd_details
)
2444 struct i40e_aq_desc desc
;
2445 struct i40e_aqc_macvlan
*cmd
=
2446 (struct i40e_aqc_macvlan
*)&desc
.params
.raw
;
2450 if (count
== 0 || !mv_list
|| !hw
)
2451 return I40E_ERR_PARAM
;
2453 buf_size
= count
* sizeof(*mv_list
);
2455 /* prep the rest of the request */
2456 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_remove_macvlan
);
2457 cmd
->num_addresses
= cpu_to_le16(count
);
2458 cmd
->seid
[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID
| seid
);
2462 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
2463 if (buf_size
> I40E_AQ_LARGE_BUF
)
2464 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2466 status
= i40e_asq_send_command(hw
, &desc
, mv_list
, buf_size
,
2473 * i40e_aq_send_msg_to_vf
2474 * @hw: pointer to the hardware structure
2475 * @vfid: VF id to send msg
2476 * @v_opcode: opcodes for VF-PF communication
2477 * @v_retval: return error code
2478 * @msg: pointer to the msg buffer
2479 * @msglen: msg length
2480 * @cmd_details: pointer to command details
2484 i40e_status
i40e_aq_send_msg_to_vf(struct i40e_hw
*hw
, u16 vfid
,
2485 u32 v_opcode
, u32 v_retval
, u8
*msg
, u16 msglen
,
2486 struct i40e_asq_cmd_details
*cmd_details
)
2488 struct i40e_aq_desc desc
;
2489 struct i40e_aqc_pf_vf_message
*cmd
=
2490 (struct i40e_aqc_pf_vf_message
*)&desc
.params
.raw
;
2493 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_send_msg_to_vf
);
2494 cmd
->id
= cpu_to_le32(vfid
);
2495 desc
.cookie_high
= cpu_to_le32(v_opcode
);
2496 desc
.cookie_low
= cpu_to_le32(v_retval
);
2497 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_SI
);
2499 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
|
2501 if (msglen
> I40E_AQ_LARGE_BUF
)
2502 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2503 desc
.datalen
= cpu_to_le16(msglen
);
2505 status
= i40e_asq_send_command(hw
, &desc
, msg
, msglen
, cmd_details
);
2511 * i40e_aq_debug_read_register
2512 * @hw: pointer to the hw struct
2513 * @reg_addr: register address
2514 * @reg_val: register value
2515 * @cmd_details: pointer to command details structure or NULL
2517 * Read the register using the admin queue commands
2519 i40e_status
i40e_aq_debug_read_register(struct i40e_hw
*hw
,
2520 u32 reg_addr
, u64
*reg_val
,
2521 struct i40e_asq_cmd_details
*cmd_details
)
2523 struct i40e_aq_desc desc
;
2524 struct i40e_aqc_debug_reg_read_write
*cmd_resp
=
2525 (struct i40e_aqc_debug_reg_read_write
*)&desc
.params
.raw
;
2528 if (reg_val
== NULL
)
2529 return I40E_ERR_PARAM
;
2531 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_debug_read_reg
);
2533 cmd_resp
->address
= cpu_to_le32(reg_addr
);
2535 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2538 *reg_val
= ((u64
)le32_to_cpu(cmd_resp
->value_high
) << 32) |
2539 (u64
)le32_to_cpu(cmd_resp
->value_low
);
2546 * i40e_aq_debug_write_register
2547 * @hw: pointer to the hw struct
2548 * @reg_addr: register address
2549 * @reg_val: register value
2550 * @cmd_details: pointer to command details structure or NULL
2552 * Write to a register using the admin queue commands
2554 i40e_status
i40e_aq_debug_write_register(struct i40e_hw
*hw
,
2555 u32 reg_addr
, u64 reg_val
,
2556 struct i40e_asq_cmd_details
*cmd_details
)
2558 struct i40e_aq_desc desc
;
2559 struct i40e_aqc_debug_reg_read_write
*cmd
=
2560 (struct i40e_aqc_debug_reg_read_write
*)&desc
.params
.raw
;
2563 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_debug_write_reg
);
2565 cmd
->address
= cpu_to_le32(reg_addr
);
2566 cmd
->value_high
= cpu_to_le32((u32
)(reg_val
>> 32));
2567 cmd
->value_low
= cpu_to_le32((u32
)(reg_val
& 0xFFFFFFFF));
2569 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2575 * i40e_aq_set_hmc_resource_profile
2576 * @hw: pointer to the hw struct
2577 * @profile: type of profile the HMC is to be set as
2578 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2579 * @cmd_details: pointer to command details structure or NULL
2581 * set the HMC profile of the device.
2583 i40e_status
i40e_aq_set_hmc_resource_profile(struct i40e_hw
*hw
,
2584 enum i40e_aq_hmc_profile profile
,
2585 u8 pe_vf_enabled_count
,
2586 struct i40e_asq_cmd_details
*cmd_details
)
2588 struct i40e_aq_desc desc
;
2589 struct i40e_aq_get_set_hmc_resource_profile
*cmd
=
2590 (struct i40e_aq_get_set_hmc_resource_profile
*)&desc
.params
.raw
;
2593 i40e_fill_default_direct_cmd_desc(&desc
,
2594 i40e_aqc_opc_set_hmc_resource_profile
);
2596 cmd
->pm_profile
= (u8
)profile
;
2597 cmd
->pe_vf_enabled
= pe_vf_enabled_count
;
2599 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2605 * i40e_aq_request_resource
2606 * @hw: pointer to the hw struct
2607 * @resource: resource id
2608 * @access: access type
2609 * @sdp_number: resource number
2610 * @timeout: the maximum time in ms that the driver may hold the resource
2611 * @cmd_details: pointer to command details structure or NULL
2613 * requests common resource using the admin queue commands
2615 i40e_status
i40e_aq_request_resource(struct i40e_hw
*hw
,
2616 enum i40e_aq_resources_ids resource
,
2617 enum i40e_aq_resource_access_type access
,
2618 u8 sdp_number
, u64
*timeout
,
2619 struct i40e_asq_cmd_details
*cmd_details
)
2621 struct i40e_aq_desc desc
;
2622 struct i40e_aqc_request_resource
*cmd_resp
=
2623 (struct i40e_aqc_request_resource
*)&desc
.params
.raw
;
2626 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_request_resource
);
2628 cmd_resp
->resource_id
= cpu_to_le16(resource
);
2629 cmd_resp
->access_type
= cpu_to_le16(access
);
2630 cmd_resp
->resource_number
= cpu_to_le32(sdp_number
);
2632 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2633 /* The completion specifies the maximum time in ms that the driver
2634 * may hold the resource in the Timeout field.
2635 * If the resource is held by someone else, the command completes with
2636 * busy return value and the timeout field indicates the maximum time
2637 * the current owner of the resource has to free it.
2639 if (!status
|| hw
->aq
.asq_last_status
== I40E_AQ_RC_EBUSY
)
2640 *timeout
= le32_to_cpu(cmd_resp
->timeout
);
2646 * i40e_aq_release_resource
2647 * @hw: pointer to the hw struct
2648 * @resource: resource id
2649 * @sdp_number: resource number
2650 * @cmd_details: pointer to command details structure or NULL
2652 * release common resource using the admin queue commands
2654 i40e_status
i40e_aq_release_resource(struct i40e_hw
*hw
,
2655 enum i40e_aq_resources_ids resource
,
2657 struct i40e_asq_cmd_details
*cmd_details
)
2659 struct i40e_aq_desc desc
;
2660 struct i40e_aqc_request_resource
*cmd
=
2661 (struct i40e_aqc_request_resource
*)&desc
.params
.raw
;
2664 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_release_resource
);
2666 cmd
->resource_id
= cpu_to_le16(resource
);
2667 cmd
->resource_number
= cpu_to_le32(sdp_number
);
2669 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2676 * @hw: pointer to the hw struct
2677 * @module_pointer: module pointer location in words from the NVM beginning
2678 * @offset: byte offset from the module beginning
2679 * @length: length of the section to be read (in bytes from the offset)
2680 * @data: command buffer (size [bytes] = length)
2681 * @last_command: tells if this is the last command in a series
2682 * @cmd_details: pointer to command details structure or NULL
2684 * Read the NVM using the admin queue commands
2686 i40e_status
i40e_aq_read_nvm(struct i40e_hw
*hw
, u8 module_pointer
,
2687 u32 offset
, u16 length
, void *data
,
2689 struct i40e_asq_cmd_details
*cmd_details
)
2691 struct i40e_aq_desc desc
;
2692 struct i40e_aqc_nvm_update
*cmd
=
2693 (struct i40e_aqc_nvm_update
*)&desc
.params
.raw
;
2696 /* In offset the highest byte must be zeroed. */
2697 if (offset
& 0xFF000000) {
2698 status
= I40E_ERR_PARAM
;
2699 goto i40e_aq_read_nvm_exit
;
2702 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_nvm_read
);
2704 /* If this is the last command in a series, set the proper flag. */
2706 cmd
->command_flags
|= I40E_AQ_NVM_LAST_CMD
;
2707 cmd
->module_pointer
= module_pointer
;
2708 cmd
->offset
= cpu_to_le32(offset
);
2709 cmd
->length
= cpu_to_le16(length
);
2711 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
2712 if (length
> I40E_AQ_LARGE_BUF
)
2713 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
2715 status
= i40e_asq_send_command(hw
, &desc
, data
, length
, cmd_details
);
2717 i40e_aq_read_nvm_exit
:
2723 * @hw: pointer to the hw struct
2724 * @module_pointer: module pointer location in words from the NVM beginning
2725 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2726 * @length: length of the section to be erased (expressed in 4 KB)
2727 * @last_command: tells if this is the last command in a series
2728 * @cmd_details: pointer to command details structure or NULL
2730 * Erase the NVM sector using the admin queue commands
2732 i40e_status
i40e_aq_erase_nvm(struct i40e_hw
*hw
, u8 module_pointer
,
2733 u32 offset
, u16 length
, bool last_command
,
2734 struct i40e_asq_cmd_details
*cmd_details
)
2736 struct i40e_aq_desc desc
;
2737 struct i40e_aqc_nvm_update
*cmd
=
2738 (struct i40e_aqc_nvm_update
*)&desc
.params
.raw
;
2741 /* In offset the highest byte must be zeroed. */
2742 if (offset
& 0xFF000000) {
2743 status
= I40E_ERR_PARAM
;
2744 goto i40e_aq_erase_nvm_exit
;
2747 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_nvm_erase
);
2749 /* If this is the last command in a series, set the proper flag. */
2751 cmd
->command_flags
|= I40E_AQ_NVM_LAST_CMD
;
2752 cmd
->module_pointer
= module_pointer
;
2753 cmd
->offset
= cpu_to_le32(offset
);
2754 cmd
->length
= cpu_to_le16(length
);
2756 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
2758 i40e_aq_erase_nvm_exit
:
2763 * i40e_parse_discover_capabilities
2764 * @hw: pointer to the hw struct
2765 * @buff: pointer to a buffer containing device/function capability records
2766 * @cap_count: number of capability records in the list
2767 * @list_type_opc: type of capabilities list to parse
2769 * Parse the device/function capabilities list.
2771 static void i40e_parse_discover_capabilities(struct i40e_hw
*hw
, void *buff
,
2773 enum i40e_admin_queue_opc list_type_opc
)
2775 struct i40e_aqc_list_capabilities_element_resp
*cap
;
2776 u32 valid_functions
, num_functions
;
2777 u32 number
, logical_id
, phys_id
;
2778 struct i40e_hw_capabilities
*p
;
2783 cap
= (struct i40e_aqc_list_capabilities_element_resp
*) buff
;
2785 if (list_type_opc
== i40e_aqc_opc_list_dev_capabilities
)
2787 else if (list_type_opc
== i40e_aqc_opc_list_func_capabilities
)
2792 for (i
= 0; i
< cap_count
; i
++, cap
++) {
2793 id
= le16_to_cpu(cap
->id
);
2794 number
= le32_to_cpu(cap
->number
);
2795 logical_id
= le32_to_cpu(cap
->logical_id
);
2796 phys_id
= le32_to_cpu(cap
->phys_id
);
2797 major_rev
= cap
->major_rev
;
2800 case I40E_AQ_CAP_ID_SWITCH_MODE
:
2801 p
->switch_mode
= number
;
2803 case I40E_AQ_CAP_ID_MNG_MODE
:
2804 p
->management_mode
= number
;
2806 case I40E_AQ_CAP_ID_NPAR_ACTIVE
:
2807 p
->npar_enable
= number
;
2809 case I40E_AQ_CAP_ID_OS2BMC_CAP
:
2812 case I40E_AQ_CAP_ID_FUNCTIONS_VALID
:
2813 p
->valid_functions
= number
;
2815 case I40E_AQ_CAP_ID_SRIOV
:
2817 p
->sr_iov_1_1
= true;
2819 case I40E_AQ_CAP_ID_VF
:
2820 p
->num_vfs
= number
;
2821 p
->vf_base_id
= logical_id
;
2823 case I40E_AQ_CAP_ID_VMDQ
:
2827 case I40E_AQ_CAP_ID_8021QBG
:
2829 p
->evb_802_1_qbg
= true;
2831 case I40E_AQ_CAP_ID_8021QBR
:
2833 p
->evb_802_1_qbh
= true;
2835 case I40E_AQ_CAP_ID_VSI
:
2836 p
->num_vsis
= number
;
2838 case I40E_AQ_CAP_ID_DCB
:
2841 p
->enabled_tcmap
= logical_id
;
2845 case I40E_AQ_CAP_ID_FCOE
:
2849 case I40E_AQ_CAP_ID_ISCSI
:
2853 case I40E_AQ_CAP_ID_RSS
:
2855 p
->rss_table_size
= number
;
2856 p
->rss_table_entry_width
= logical_id
;
2858 case I40E_AQ_CAP_ID_RXQ
:
2859 p
->num_rx_qp
= number
;
2860 p
->base_queue
= phys_id
;
2862 case I40E_AQ_CAP_ID_TXQ
:
2863 p
->num_tx_qp
= number
;
2864 p
->base_queue
= phys_id
;
2866 case I40E_AQ_CAP_ID_MSIX
:
2867 p
->num_msix_vectors
= number
;
2869 case I40E_AQ_CAP_ID_VF_MSIX
:
2870 p
->num_msix_vectors_vf
= number
;
2872 case I40E_AQ_CAP_ID_FLEX10
:
2873 if (major_rev
== 1) {
2875 p
->flex10_enable
= true;
2876 p
->flex10_capable
= true;
2879 /* Capability revision >= 2 */
2881 p
->flex10_enable
= true;
2883 p
->flex10_capable
= true;
2885 p
->flex10_mode
= logical_id
;
2886 p
->flex10_status
= phys_id
;
2888 case I40E_AQ_CAP_ID_CEM
:
2892 case I40E_AQ_CAP_ID_IWARP
:
2896 case I40E_AQ_CAP_ID_LED
:
2897 if (phys_id
< I40E_HW_CAP_MAX_GPIO
)
2898 p
->led
[phys_id
] = true;
2900 case I40E_AQ_CAP_ID_SDP
:
2901 if (phys_id
< I40E_HW_CAP_MAX_GPIO
)
2902 p
->sdp
[phys_id
] = true;
2904 case I40E_AQ_CAP_ID_MDIO
:
2906 p
->mdio_port_num
= phys_id
;
2907 p
->mdio_port_mode
= logical_id
;
2910 case I40E_AQ_CAP_ID_1588
:
2912 p
->ieee_1588
= true;
2914 case I40E_AQ_CAP_ID_FLOW_DIRECTOR
:
2916 p
->fd_filters_guaranteed
= number
;
2917 p
->fd_filters_best_effort
= logical_id
;
2919 case I40E_AQ_CAP_ID_WSR_PROT
:
2920 p
->wr_csr_prot
= (u64
)number
;
2921 p
->wr_csr_prot
|= (u64
)logical_id
<< 32;
2929 i40e_debug(hw
, I40E_DEBUG_ALL
, "device is FCoE capable\n");
2931 /* Software override ensuring FCoE is disabled if npar or mfp
2932 * mode because it is not supported in these modes.
2934 if (p
->npar_enable
|| p
->flex10_enable
)
2937 /* count the enabled ports (aka the "not disabled" ports) */
2939 for (i
= 0; i
< 4; i
++) {
2940 u32 port_cfg_reg
= I40E_PRTGEN_CNF
+ (4 * i
);
2943 /* use AQ read to get the physical register offset instead
2944 * of the port relative offset
2946 i40e_aq_debug_read_register(hw
, port_cfg_reg
, &port_cfg
, NULL
);
2947 if (!(port_cfg
& I40E_PRTGEN_CNF_PORT_DIS_MASK
))
2951 valid_functions
= p
->valid_functions
;
2953 while (valid_functions
) {
2954 if (valid_functions
& 1)
2956 valid_functions
>>= 1;
2959 /* partition id is 1-based, and functions are evenly spread
2960 * across the ports as partitions
2962 hw
->partition_id
= (hw
->pf_id
/ hw
->num_ports
) + 1;
2963 hw
->num_partitions
= num_functions
/ hw
->num_ports
;
2965 /* additional HW specific goodies that might
2966 * someday be HW version specific
2968 p
->rx_buf_chain_len
= I40E_MAX_CHAINED_RX_BUFFERS
;
2972 * i40e_aq_discover_capabilities
2973 * @hw: pointer to the hw struct
2974 * @buff: a virtual buffer to hold the capabilities
2975 * @buff_size: Size of the virtual buffer
2976 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2977 * @list_type_opc: capabilities type to discover - pass in the command opcode
2978 * @cmd_details: pointer to command details structure or NULL
2980 * Get the device capabilities descriptions from the firmware
2982 i40e_status
i40e_aq_discover_capabilities(struct i40e_hw
*hw
,
2983 void *buff
, u16 buff_size
, u16
*data_size
,
2984 enum i40e_admin_queue_opc list_type_opc
,
2985 struct i40e_asq_cmd_details
*cmd_details
)
2987 struct i40e_aqc_list_capabilites
*cmd
;
2988 struct i40e_aq_desc desc
;
2989 i40e_status status
= 0;
2991 cmd
= (struct i40e_aqc_list_capabilites
*)&desc
.params
.raw
;
2993 if (list_type_opc
!= i40e_aqc_opc_list_func_capabilities
&&
2994 list_type_opc
!= i40e_aqc_opc_list_dev_capabilities
) {
2995 status
= I40E_ERR_PARAM
;
2999 i40e_fill_default_direct_cmd_desc(&desc
, list_type_opc
);
3001 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
3002 if (buff_size
> I40E_AQ_LARGE_BUF
)
3003 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
3005 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
3006 *data_size
= le16_to_cpu(desc
.datalen
);
3011 i40e_parse_discover_capabilities(hw
, buff
, le32_to_cpu(cmd
->count
),
3019 * i40e_aq_update_nvm
3020 * @hw: pointer to the hw struct
3021 * @module_pointer: module pointer location in words from the NVM beginning
3022 * @offset: byte offset from the module beginning
3023 * @length: length of the section to be written (in bytes from the offset)
3024 * @data: command buffer (size [bytes] = length)
3025 * @last_command: tells if this is the last command in a series
3026 * @cmd_details: pointer to command details structure or NULL
3028 * Update the NVM using the admin queue commands
3030 i40e_status
i40e_aq_update_nvm(struct i40e_hw
*hw
, u8 module_pointer
,
3031 u32 offset
, u16 length
, void *data
,
3033 struct i40e_asq_cmd_details
*cmd_details
)
3035 struct i40e_aq_desc desc
;
3036 struct i40e_aqc_nvm_update
*cmd
=
3037 (struct i40e_aqc_nvm_update
*)&desc
.params
.raw
;
3040 /* In offset the highest byte must be zeroed. */
3041 if (offset
& 0xFF000000) {
3042 status
= I40E_ERR_PARAM
;
3043 goto i40e_aq_update_nvm_exit
;
3046 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_nvm_update
);
3048 /* If this is the last command in a series, set the proper flag. */
3050 cmd
->command_flags
|= I40E_AQ_NVM_LAST_CMD
;
3051 cmd
->module_pointer
= module_pointer
;
3052 cmd
->offset
= cpu_to_le32(offset
);
3053 cmd
->length
= cpu_to_le16(length
);
3055 desc
.flags
|= cpu_to_le16((u16
)(I40E_AQ_FLAG_BUF
| I40E_AQ_FLAG_RD
));
3056 if (length
> I40E_AQ_LARGE_BUF
)
3057 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
3059 status
= i40e_asq_send_command(hw
, &desc
, data
, length
, cmd_details
);
3061 i40e_aq_update_nvm_exit
:
3066 * i40e_aq_get_lldp_mib
3067 * @hw: pointer to the hw struct
3068 * @bridge_type: type of bridge requested
3069 * @mib_type: Local, Remote or both Local and Remote MIBs
3070 * @buff: pointer to a user supplied buffer to store the MIB block
3071 * @buff_size: size of the buffer (in bytes)
3072 * @local_len : length of the returned Local LLDP MIB
3073 * @remote_len: length of the returned Remote LLDP MIB
3074 * @cmd_details: pointer to command details structure or NULL
3076 * Requests the complete LLDP MIB (entire packet).
3078 i40e_status
i40e_aq_get_lldp_mib(struct i40e_hw
*hw
, u8 bridge_type
,
3079 u8 mib_type
, void *buff
, u16 buff_size
,
3080 u16
*local_len
, u16
*remote_len
,
3081 struct i40e_asq_cmd_details
*cmd_details
)
3083 struct i40e_aq_desc desc
;
3084 struct i40e_aqc_lldp_get_mib
*cmd
=
3085 (struct i40e_aqc_lldp_get_mib
*)&desc
.params
.raw
;
3086 struct i40e_aqc_lldp_get_mib
*resp
=
3087 (struct i40e_aqc_lldp_get_mib
*)&desc
.params
.raw
;
3090 if (buff_size
== 0 || !buff
)
3091 return I40E_ERR_PARAM
;
3093 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_get_mib
);
3094 /* Indirect Command */
3095 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
3097 cmd
->type
= mib_type
& I40E_AQ_LLDP_MIB_TYPE_MASK
;
3098 cmd
->type
|= ((bridge_type
<< I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT
) &
3099 I40E_AQ_LLDP_BRIDGE_TYPE_MASK
);
3101 desc
.datalen
= cpu_to_le16(buff_size
);
3103 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
3104 if (buff_size
> I40E_AQ_LARGE_BUF
)
3105 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
3107 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
3109 if (local_len
!= NULL
)
3110 *local_len
= le16_to_cpu(resp
->local_len
);
3111 if (remote_len
!= NULL
)
3112 *remote_len
= le16_to_cpu(resp
->remote_len
);
3119 * i40e_aq_cfg_lldp_mib_change_event
3120 * @hw: pointer to the hw struct
3121 * @enable_update: Enable or Disable event posting
3122 * @cmd_details: pointer to command details structure or NULL
3124 * Enable or Disable posting of an event on ARQ when LLDP MIB
3125 * associated with the interface changes
3127 i40e_status
i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw
*hw
,
3129 struct i40e_asq_cmd_details
*cmd_details
)
3131 struct i40e_aq_desc desc
;
3132 struct i40e_aqc_lldp_update_mib
*cmd
=
3133 (struct i40e_aqc_lldp_update_mib
*)&desc
.params
.raw
;
3136 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_update_mib
);
3139 cmd
->command
|= I40E_AQ_LLDP_MIB_UPDATE_DISABLE
;
3141 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3148 * @hw: pointer to the hw struct
3149 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3150 * @cmd_details: pointer to command details structure or NULL
3152 * Stop or Shutdown the embedded LLDP Agent
3154 i40e_status
i40e_aq_stop_lldp(struct i40e_hw
*hw
, bool shutdown_agent
,
3155 struct i40e_asq_cmd_details
*cmd_details
)
3157 struct i40e_aq_desc desc
;
3158 struct i40e_aqc_lldp_stop
*cmd
=
3159 (struct i40e_aqc_lldp_stop
*)&desc
.params
.raw
;
3162 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_stop
);
3165 cmd
->command
|= I40E_AQ_LLDP_AGENT_SHUTDOWN
;
3167 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3173 * i40e_aq_start_lldp
3174 * @hw: pointer to the hw struct
3175 * @cmd_details: pointer to command details structure or NULL
3177 * Start the embedded LLDP Agent on all ports.
3179 i40e_status
i40e_aq_start_lldp(struct i40e_hw
*hw
,
3180 struct i40e_asq_cmd_details
*cmd_details
)
3182 struct i40e_aq_desc desc
;
3183 struct i40e_aqc_lldp_start
*cmd
=
3184 (struct i40e_aqc_lldp_start
*)&desc
.params
.raw
;
3187 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_lldp_start
);
3189 cmd
->command
= I40E_AQ_LLDP_AGENT_START
;
3191 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3197 * i40e_aq_get_cee_dcb_config
3198 * @hw: pointer to the hw struct
3199 * @buff: response buffer that stores CEE operational configuration
3200 * @buff_size: size of the buffer passed
3201 * @cmd_details: pointer to command details structure or NULL
3203 * Get CEE DCBX mode operational configuration from firmware
3205 i40e_status
i40e_aq_get_cee_dcb_config(struct i40e_hw
*hw
,
3206 void *buff
, u16 buff_size
,
3207 struct i40e_asq_cmd_details
*cmd_details
)
3209 struct i40e_aq_desc desc
;
3212 if (buff_size
== 0 || !buff
)
3213 return I40E_ERR_PARAM
;
3215 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_get_cee_dcb_cfg
);
3217 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
3218 status
= i40e_asq_send_command(hw
, &desc
, (void *)buff
, buff_size
,
3225 * i40e_aq_add_udp_tunnel
3226 * @hw: pointer to the hw struct
3227 * @udp_port: the UDP port to add
3228 * @header_len: length of the tunneling header length in DWords
3229 * @protocol_index: protocol index type
3230 * @filter_index: pointer to filter index
3231 * @cmd_details: pointer to command details structure or NULL
3233 i40e_status
i40e_aq_add_udp_tunnel(struct i40e_hw
*hw
,
3234 u16 udp_port
, u8 protocol_index
,
3236 struct i40e_asq_cmd_details
*cmd_details
)
3238 struct i40e_aq_desc desc
;
3239 struct i40e_aqc_add_udp_tunnel
*cmd
=
3240 (struct i40e_aqc_add_udp_tunnel
*)&desc
.params
.raw
;
3241 struct i40e_aqc_del_udp_tunnel_completion
*resp
=
3242 (struct i40e_aqc_del_udp_tunnel_completion
*)&desc
.params
.raw
;
3245 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_add_udp_tunnel
);
3247 cmd
->udp_port
= cpu_to_le16(udp_port
);
3248 cmd
->protocol_type
= protocol_index
;
3250 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3252 if (!status
&& filter_index
)
3253 *filter_index
= resp
->index
;
3259 * i40e_aq_del_udp_tunnel
3260 * @hw: pointer to the hw struct
3261 * @index: filter index
3262 * @cmd_details: pointer to command details structure or NULL
3264 i40e_status
i40e_aq_del_udp_tunnel(struct i40e_hw
*hw
, u8 index
,
3265 struct i40e_asq_cmd_details
*cmd_details
)
3267 struct i40e_aq_desc desc
;
3268 struct i40e_aqc_remove_udp_tunnel
*cmd
=
3269 (struct i40e_aqc_remove_udp_tunnel
*)&desc
.params
.raw
;
3272 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_del_udp_tunnel
);
3276 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3282 * i40e_aq_delete_element - Delete switch element
3283 * @hw: pointer to the hw struct
3284 * @seid: the SEID to delete from the switch
3285 * @cmd_details: pointer to command details structure or NULL
3287 * This deletes a switch element from the switch.
3289 i40e_status
i40e_aq_delete_element(struct i40e_hw
*hw
, u16 seid
,
3290 struct i40e_asq_cmd_details
*cmd_details
)
3292 struct i40e_aq_desc desc
;
3293 struct i40e_aqc_switch_seid
*cmd
=
3294 (struct i40e_aqc_switch_seid
*)&desc
.params
.raw
;
3298 return I40E_ERR_PARAM
;
3300 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_delete_element
);
3302 cmd
->seid
= cpu_to_le16(seid
);
3304 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3310 * i40e_aq_dcb_updated - DCB Updated Command
3311 * @hw: pointer to the hw struct
3312 * @cmd_details: pointer to command details structure or NULL
3314 * EMP will return when the shared RPB settings have been
3315 * recomputed and modified. The retval field in the descriptor
3316 * will be set to 0 when RPB is modified.
3318 i40e_status
i40e_aq_dcb_updated(struct i40e_hw
*hw
,
3319 struct i40e_asq_cmd_details
*cmd_details
)
3321 struct i40e_aq_desc desc
;
3324 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_dcb_updated
);
3326 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3332 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3333 * @hw: pointer to the hw struct
3334 * @seid: seid for the physical port/switching component/vsi
3335 * @buff: Indirect buffer to hold data parameters and response
3336 * @buff_size: Indirect buffer size
3337 * @opcode: Tx scheduler AQ command opcode
3338 * @cmd_details: pointer to command details structure or NULL
3340 * Generic command handler for Tx scheduler AQ commands
3342 static i40e_status
i40e_aq_tx_sched_cmd(struct i40e_hw
*hw
, u16 seid
,
3343 void *buff
, u16 buff_size
,
3344 enum i40e_admin_queue_opc opcode
,
3345 struct i40e_asq_cmd_details
*cmd_details
)
3347 struct i40e_aq_desc desc
;
3348 struct i40e_aqc_tx_sched_ind
*cmd
=
3349 (struct i40e_aqc_tx_sched_ind
*)&desc
.params
.raw
;
3351 bool cmd_param_flag
= false;
3354 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit
:
3355 case i40e_aqc_opc_configure_vsi_tc_bw
:
3356 case i40e_aqc_opc_enable_switching_comp_ets
:
3357 case i40e_aqc_opc_modify_switching_comp_ets
:
3358 case i40e_aqc_opc_disable_switching_comp_ets
:
3359 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit
:
3360 case i40e_aqc_opc_configure_switching_comp_bw_config
:
3361 cmd_param_flag
= true;
3363 case i40e_aqc_opc_query_vsi_bw_config
:
3364 case i40e_aqc_opc_query_vsi_ets_sla_config
:
3365 case i40e_aqc_opc_query_switching_comp_ets_config
:
3366 case i40e_aqc_opc_query_port_ets_config
:
3367 case i40e_aqc_opc_query_switching_comp_bw_config
:
3368 cmd_param_flag
= false;
3371 return I40E_ERR_PARAM
;
3374 i40e_fill_default_direct_cmd_desc(&desc
, opcode
);
3376 /* Indirect command */
3377 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
3379 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_RD
);
3380 if (buff_size
> I40E_AQ_LARGE_BUF
)
3381 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
3383 desc
.datalen
= cpu_to_le16(buff_size
);
3385 cmd
->vsi_seid
= cpu_to_le16(seid
);
3387 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
3393 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3394 * @hw: pointer to the hw struct
3396 * @credit: BW limit credits (0 = disabled)
3397 * @max_credit: Max BW limit credits
3398 * @cmd_details: pointer to command details structure or NULL
3400 i40e_status
i40e_aq_config_vsi_bw_limit(struct i40e_hw
*hw
,
3401 u16 seid
, u16 credit
, u8 max_credit
,
3402 struct i40e_asq_cmd_details
*cmd_details
)
3404 struct i40e_aq_desc desc
;
3405 struct i40e_aqc_configure_vsi_bw_limit
*cmd
=
3406 (struct i40e_aqc_configure_vsi_bw_limit
*)&desc
.params
.raw
;
3409 i40e_fill_default_direct_cmd_desc(&desc
,
3410 i40e_aqc_opc_configure_vsi_bw_limit
);
3412 cmd
->vsi_seid
= cpu_to_le16(seid
);
3413 cmd
->credit
= cpu_to_le16(credit
);
3414 cmd
->max_credit
= max_credit
;
3416 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3422 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3423 * @hw: pointer to the hw struct
3425 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3426 * @cmd_details: pointer to command details structure or NULL
3428 i40e_status
i40e_aq_config_vsi_tc_bw(struct i40e_hw
*hw
,
3430 struct i40e_aqc_configure_vsi_tc_bw_data
*bw_data
,
3431 struct i40e_asq_cmd_details
*cmd_details
)
3433 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3434 i40e_aqc_opc_configure_vsi_tc_bw
,
3439 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3440 * @hw: pointer to the hw struct
3441 * @seid: seid of the switching component connected to Physical Port
3442 * @ets_data: Buffer holding ETS parameters
3443 * @cmd_details: pointer to command details structure or NULL
3445 i40e_status
i40e_aq_config_switch_comp_ets(struct i40e_hw
*hw
,
3447 struct i40e_aqc_configure_switching_comp_ets_data
*ets_data
,
3448 enum i40e_admin_queue_opc opcode
,
3449 struct i40e_asq_cmd_details
*cmd_details
)
3451 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)ets_data
,
3452 sizeof(*ets_data
), opcode
, cmd_details
);
3456 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3457 * @hw: pointer to the hw struct
3458 * @seid: seid of the switching component
3459 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3460 * @cmd_details: pointer to command details structure or NULL
3462 i40e_status
i40e_aq_config_switch_comp_bw_config(struct i40e_hw
*hw
,
3464 struct i40e_aqc_configure_switching_comp_bw_config_data
*bw_data
,
3465 struct i40e_asq_cmd_details
*cmd_details
)
3467 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3468 i40e_aqc_opc_configure_switching_comp_bw_config
,
3473 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3474 * @hw: pointer to the hw struct
3475 * @seid: seid of the VSI
3476 * @bw_data: Buffer to hold VSI BW configuration
3477 * @cmd_details: pointer to command details structure or NULL
3479 i40e_status
i40e_aq_query_vsi_bw_config(struct i40e_hw
*hw
,
3481 struct i40e_aqc_query_vsi_bw_config_resp
*bw_data
,
3482 struct i40e_asq_cmd_details
*cmd_details
)
3484 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3485 i40e_aqc_opc_query_vsi_bw_config
,
3490 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3491 * @hw: pointer to the hw struct
3492 * @seid: seid of the VSI
3493 * @bw_data: Buffer to hold VSI BW configuration per TC
3494 * @cmd_details: pointer to command details structure or NULL
3496 i40e_status
i40e_aq_query_vsi_ets_sla_config(struct i40e_hw
*hw
,
3498 struct i40e_aqc_query_vsi_ets_sla_config_resp
*bw_data
,
3499 struct i40e_asq_cmd_details
*cmd_details
)
3501 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3502 i40e_aqc_opc_query_vsi_ets_sla_config
,
3507 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3508 * @hw: pointer to the hw struct
3509 * @seid: seid of the switching component
3510 * @bw_data: Buffer to hold switching component's per TC BW config
3511 * @cmd_details: pointer to command details structure or NULL
3513 i40e_status
i40e_aq_query_switch_comp_ets_config(struct i40e_hw
*hw
,
3515 struct i40e_aqc_query_switching_comp_ets_config_resp
*bw_data
,
3516 struct i40e_asq_cmd_details
*cmd_details
)
3518 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3519 i40e_aqc_opc_query_switching_comp_ets_config
,
3524 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3525 * @hw: pointer to the hw struct
3526 * @seid: seid of the VSI or switching component connected to Physical Port
3527 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3528 * @cmd_details: pointer to command details structure or NULL
3530 i40e_status
i40e_aq_query_port_ets_config(struct i40e_hw
*hw
,
3532 struct i40e_aqc_query_port_ets_config_resp
*bw_data
,
3533 struct i40e_asq_cmd_details
*cmd_details
)
3535 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3536 i40e_aqc_opc_query_port_ets_config
,
3541 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3542 * @hw: pointer to the hw struct
3543 * @seid: seid of the switching component
3544 * @bw_data: Buffer to hold switching component's BW configuration
3545 * @cmd_details: pointer to command details structure or NULL
3547 i40e_status
i40e_aq_query_switch_comp_bw_config(struct i40e_hw
*hw
,
3549 struct i40e_aqc_query_switching_comp_bw_config_resp
*bw_data
,
3550 struct i40e_asq_cmd_details
*cmd_details
)
3552 return i40e_aq_tx_sched_cmd(hw
, seid
, (void *)bw_data
, sizeof(*bw_data
),
3553 i40e_aqc_opc_query_switching_comp_bw_config
,
3558 * i40e_validate_filter_settings
3559 * @hw: pointer to the hardware structure
3560 * @settings: Filter control settings
3562 * Check and validate the filter control settings passed.
3563 * The function checks for the valid filter/context sizes being
3564 * passed for FCoE and PE.
3566 * Returns 0 if the values passed are valid and within
3567 * range else returns an error.
3569 static i40e_status
i40e_validate_filter_settings(struct i40e_hw
*hw
,
3570 struct i40e_filter_control_settings
*settings
)
3572 u32 fcoe_cntx_size
, fcoe_filt_size
;
3573 u32 pe_cntx_size
, pe_filt_size
;
3577 /* Validate FCoE settings passed */
3578 switch (settings
->fcoe_filt_num
) {
3579 case I40E_HASH_FILTER_SIZE_1K
:
3580 case I40E_HASH_FILTER_SIZE_2K
:
3581 case I40E_HASH_FILTER_SIZE_4K
:
3582 case I40E_HASH_FILTER_SIZE_8K
:
3583 case I40E_HASH_FILTER_SIZE_16K
:
3584 case I40E_HASH_FILTER_SIZE_32K
:
3585 fcoe_filt_size
= I40E_HASH_FILTER_BASE_SIZE
;
3586 fcoe_filt_size
<<= (u32
)settings
->fcoe_filt_num
;
3589 return I40E_ERR_PARAM
;
3592 switch (settings
->fcoe_cntx_num
) {
3593 case I40E_DMA_CNTX_SIZE_512
:
3594 case I40E_DMA_CNTX_SIZE_1K
:
3595 case I40E_DMA_CNTX_SIZE_2K
:
3596 case I40E_DMA_CNTX_SIZE_4K
:
3597 fcoe_cntx_size
= I40E_DMA_CNTX_BASE_SIZE
;
3598 fcoe_cntx_size
<<= (u32
)settings
->fcoe_cntx_num
;
3601 return I40E_ERR_PARAM
;
3604 /* Validate PE settings passed */
3605 switch (settings
->pe_filt_num
) {
3606 case I40E_HASH_FILTER_SIZE_1K
:
3607 case I40E_HASH_FILTER_SIZE_2K
:
3608 case I40E_HASH_FILTER_SIZE_4K
:
3609 case I40E_HASH_FILTER_SIZE_8K
:
3610 case I40E_HASH_FILTER_SIZE_16K
:
3611 case I40E_HASH_FILTER_SIZE_32K
:
3612 case I40E_HASH_FILTER_SIZE_64K
:
3613 case I40E_HASH_FILTER_SIZE_128K
:
3614 case I40E_HASH_FILTER_SIZE_256K
:
3615 case I40E_HASH_FILTER_SIZE_512K
:
3616 case I40E_HASH_FILTER_SIZE_1M
:
3617 pe_filt_size
= I40E_HASH_FILTER_BASE_SIZE
;
3618 pe_filt_size
<<= (u32
)settings
->pe_filt_num
;
3621 return I40E_ERR_PARAM
;
3624 switch (settings
->pe_cntx_num
) {
3625 case I40E_DMA_CNTX_SIZE_512
:
3626 case I40E_DMA_CNTX_SIZE_1K
:
3627 case I40E_DMA_CNTX_SIZE_2K
:
3628 case I40E_DMA_CNTX_SIZE_4K
:
3629 case I40E_DMA_CNTX_SIZE_8K
:
3630 case I40E_DMA_CNTX_SIZE_16K
:
3631 case I40E_DMA_CNTX_SIZE_32K
:
3632 case I40E_DMA_CNTX_SIZE_64K
:
3633 case I40E_DMA_CNTX_SIZE_128K
:
3634 case I40E_DMA_CNTX_SIZE_256K
:
3635 pe_cntx_size
= I40E_DMA_CNTX_BASE_SIZE
;
3636 pe_cntx_size
<<= (u32
)settings
->pe_cntx_num
;
3639 return I40E_ERR_PARAM
;
3642 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3643 val
= rd32(hw
, I40E_GLHMC_FCOEFMAX
);
3644 fcoe_fmax
= (val
& I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK
)
3645 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT
;
3646 if (fcoe_filt_size
+ fcoe_cntx_size
> fcoe_fmax
)
3647 return I40E_ERR_INVALID_SIZE
;
3653 * i40e_set_filter_control
3654 * @hw: pointer to the hardware structure
3655 * @settings: Filter control settings
3657 * Set the Queue Filters for PE/FCoE and enable filters required
3658 * for a single PF. It is expected that these settings are programmed
3659 * at the driver initialization time.
3661 i40e_status
i40e_set_filter_control(struct i40e_hw
*hw
,
3662 struct i40e_filter_control_settings
*settings
)
3664 i40e_status ret
= 0;
3665 u32 hash_lut_size
= 0;
3669 return I40E_ERR_PARAM
;
3671 /* Validate the input settings */
3672 ret
= i40e_validate_filter_settings(hw
, settings
);
3676 /* Read the PF Queue Filter control register */
3677 val
= rd32(hw
, I40E_PFQF_CTL_0
);
3679 /* Program required PE hash buckets for the PF */
3680 val
&= ~I40E_PFQF_CTL_0_PEHSIZE_MASK
;
3681 val
|= ((u32
)settings
->pe_filt_num
<< I40E_PFQF_CTL_0_PEHSIZE_SHIFT
) &
3682 I40E_PFQF_CTL_0_PEHSIZE_MASK
;
3683 /* Program required PE contexts for the PF */
3684 val
&= ~I40E_PFQF_CTL_0_PEDSIZE_MASK
;
3685 val
|= ((u32
)settings
->pe_cntx_num
<< I40E_PFQF_CTL_0_PEDSIZE_SHIFT
) &
3686 I40E_PFQF_CTL_0_PEDSIZE_MASK
;
3688 /* Program required FCoE hash buckets for the PF */
3689 val
&= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK
;
3690 val
|= ((u32
)settings
->fcoe_filt_num
<<
3691 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT
) &
3692 I40E_PFQF_CTL_0_PFFCHSIZE_MASK
;
3693 /* Program required FCoE DDP contexts for the PF */
3694 val
&= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK
;
3695 val
|= ((u32
)settings
->fcoe_cntx_num
<<
3696 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT
) &
3697 I40E_PFQF_CTL_0_PFFCDSIZE_MASK
;
3699 /* Program Hash LUT size for the PF */
3700 val
&= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK
;
3701 if (settings
->hash_lut_size
== I40E_HASH_LUT_SIZE_512
)
3703 val
|= (hash_lut_size
<< I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT
) &
3704 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK
;
3706 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3707 if (settings
->enable_fdir
)
3708 val
|= I40E_PFQF_CTL_0_FD_ENA_MASK
;
3709 if (settings
->enable_ethtype
)
3710 val
|= I40E_PFQF_CTL_0_ETYPE_ENA_MASK
;
3711 if (settings
->enable_macvlan
)
3712 val
|= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK
;
3714 wr32(hw
, I40E_PFQF_CTL_0
, val
);
3720 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3721 * @hw: pointer to the hw struct
3722 * @mac_addr: MAC address to use in the filter
3723 * @ethtype: Ethertype to use in the filter
3724 * @flags: Flags that needs to be applied to the filter
3725 * @vsi_seid: seid of the control VSI
3726 * @queue: VSI queue number to send the packet to
3727 * @is_add: Add control packet filter if True else remove
3728 * @stats: Structure to hold information on control filter counts
3729 * @cmd_details: pointer to command details structure or NULL
3731 * This command will Add or Remove control packet filter for a control VSI.
3732 * In return it will update the total number of perfect filter count in
3735 i40e_status
i40e_aq_add_rem_control_packet_filter(struct i40e_hw
*hw
,
3736 u8
*mac_addr
, u16 ethtype
, u16 flags
,
3737 u16 vsi_seid
, u16 queue
, bool is_add
,
3738 struct i40e_control_filter_stats
*stats
,
3739 struct i40e_asq_cmd_details
*cmd_details
)
3741 struct i40e_aq_desc desc
;
3742 struct i40e_aqc_add_remove_control_packet_filter
*cmd
=
3743 (struct i40e_aqc_add_remove_control_packet_filter
*)
3745 struct i40e_aqc_add_remove_control_packet_filter_completion
*resp
=
3746 (struct i40e_aqc_add_remove_control_packet_filter_completion
*)
3751 return I40E_ERR_PARAM
;
3754 i40e_fill_default_direct_cmd_desc(&desc
,
3755 i40e_aqc_opc_add_control_packet_filter
);
3756 cmd
->queue
= cpu_to_le16(queue
);
3758 i40e_fill_default_direct_cmd_desc(&desc
,
3759 i40e_aqc_opc_remove_control_packet_filter
);
3763 ether_addr_copy(cmd
->mac
, mac_addr
);
3765 cmd
->etype
= cpu_to_le16(ethtype
);
3766 cmd
->flags
= cpu_to_le16(flags
);
3767 cmd
->seid
= cpu_to_le16(vsi_seid
);
3769 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3771 if (!status
&& stats
) {
3772 stats
->mac_etype_used
= le16_to_cpu(resp
->mac_etype_used
);
3773 stats
->etype_used
= le16_to_cpu(resp
->etype_used
);
3774 stats
->mac_etype_free
= le16_to_cpu(resp
->mac_etype_free
);
3775 stats
->etype_free
= le16_to_cpu(resp
->etype_free
);
3782 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
3783 * @hw: pointer to the hw struct
3784 * @seid: VSI seid to add ethertype filter from
3786 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
3787 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw
*hw
,
3790 u16 flag
= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC
|
3791 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP
|
3792 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX
;
3793 u16 ethtype
= I40E_FLOW_CONTROL_ETHTYPE
;
3796 status
= i40e_aq_add_rem_control_packet_filter(hw
, NULL
, ethtype
, flag
,
3797 seid
, 0, true, NULL
,
3800 hw_dbg(hw
, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
3804 * i40e_aq_alternate_read
3805 * @hw: pointer to the hardware structure
3806 * @reg_addr0: address of first dword to be read
3807 * @reg_val0: pointer for data read from 'reg_addr0'
3808 * @reg_addr1: address of second dword to be read
3809 * @reg_val1: pointer for data read from 'reg_addr1'
3811 * Read one or two dwords from alternate structure. Fields are indicated
3812 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
3813 * is not passed then only register at 'reg_addr0' is read.
3816 static i40e_status
i40e_aq_alternate_read(struct i40e_hw
*hw
,
3817 u32 reg_addr0
, u32
*reg_val0
,
3818 u32 reg_addr1
, u32
*reg_val1
)
3820 struct i40e_aq_desc desc
;
3821 struct i40e_aqc_alternate_write
*cmd_resp
=
3822 (struct i40e_aqc_alternate_write
*)&desc
.params
.raw
;
3826 return I40E_ERR_PARAM
;
3828 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_alternate_read
);
3829 cmd_resp
->address0
= cpu_to_le32(reg_addr0
);
3830 cmd_resp
->address1
= cpu_to_le32(reg_addr1
);
3832 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, NULL
);
3835 *reg_val0
= le32_to_cpu(cmd_resp
->data0
);
3838 *reg_val1
= le32_to_cpu(cmd_resp
->data1
);
3845 * i40e_aq_resume_port_tx
3846 * @hw: pointer to the hardware structure
3847 * @cmd_details: pointer to command details structure or NULL
3849 * Resume port's Tx traffic
3851 i40e_status
i40e_aq_resume_port_tx(struct i40e_hw
*hw
,
3852 struct i40e_asq_cmd_details
*cmd_details
)
3854 struct i40e_aq_desc desc
;
3857 i40e_fill_default_direct_cmd_desc(&desc
, i40e_aqc_opc_resume_port_tx
);
3859 status
= i40e_asq_send_command(hw
, &desc
, NULL
, 0, cmd_details
);
3865 * i40e_set_pci_config_data - store PCI bus info
3866 * @hw: pointer to hardware structure
3867 * @link_status: the link status word from PCI config space
3869 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3871 void i40e_set_pci_config_data(struct i40e_hw
*hw
, u16 link_status
)
3873 hw
->bus
.type
= i40e_bus_type_pci_express
;
3875 switch (link_status
& PCI_EXP_LNKSTA_NLW
) {
3876 case PCI_EXP_LNKSTA_NLW_X1
:
3877 hw
->bus
.width
= i40e_bus_width_pcie_x1
;
3879 case PCI_EXP_LNKSTA_NLW_X2
:
3880 hw
->bus
.width
= i40e_bus_width_pcie_x2
;
3882 case PCI_EXP_LNKSTA_NLW_X4
:
3883 hw
->bus
.width
= i40e_bus_width_pcie_x4
;
3885 case PCI_EXP_LNKSTA_NLW_X8
:
3886 hw
->bus
.width
= i40e_bus_width_pcie_x8
;
3889 hw
->bus
.width
= i40e_bus_width_unknown
;
3893 switch (link_status
& PCI_EXP_LNKSTA_CLS
) {
3894 case PCI_EXP_LNKSTA_CLS_2_5GB
:
3895 hw
->bus
.speed
= i40e_bus_speed_2500
;
3897 case PCI_EXP_LNKSTA_CLS_5_0GB
:
3898 hw
->bus
.speed
= i40e_bus_speed_5000
;
3900 case PCI_EXP_LNKSTA_CLS_8_0GB
:
3901 hw
->bus
.speed
= i40e_bus_speed_8000
;
3904 hw
->bus
.speed
= i40e_bus_speed_unknown
;
3910 * i40e_aq_debug_dump
3911 * @hw: pointer to the hardware structure
3912 * @cluster_id: specific cluster to dump
3913 * @table_id: table id within cluster
3914 * @start_index: index of line in the block to read
3915 * @buff_size: dump buffer size
3916 * @buff: dump buffer
3917 * @ret_buff_size: actual buffer size returned
3918 * @ret_next_table: next block to read
3919 * @ret_next_index: next index to read
3921 * Dump internal FW/HW data for debug purposes.
3924 i40e_status
i40e_aq_debug_dump(struct i40e_hw
*hw
, u8 cluster_id
,
3925 u8 table_id
, u32 start_index
, u16 buff_size
,
3926 void *buff
, u16
*ret_buff_size
,
3927 u8
*ret_next_table
, u32
*ret_next_index
,
3928 struct i40e_asq_cmd_details
*cmd_details
)
3930 struct i40e_aq_desc desc
;
3931 struct i40e_aqc_debug_dump_internals
*cmd
=
3932 (struct i40e_aqc_debug_dump_internals
*)&desc
.params
.raw
;
3933 struct i40e_aqc_debug_dump_internals
*resp
=
3934 (struct i40e_aqc_debug_dump_internals
*)&desc
.params
.raw
;
3937 if (buff_size
== 0 || !buff
)
3938 return I40E_ERR_PARAM
;
3940 i40e_fill_default_direct_cmd_desc(&desc
,
3941 i40e_aqc_opc_debug_dump_internals
);
3942 /* Indirect Command */
3943 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
3944 if (buff_size
> I40E_AQ_LARGE_BUF
)
3945 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
3947 cmd
->cluster_id
= cluster_id
;
3948 cmd
->table_id
= table_id
;
3949 cmd
->idx
= cpu_to_le32(start_index
);
3951 desc
.datalen
= cpu_to_le16(buff_size
);
3953 status
= i40e_asq_send_command(hw
, &desc
, buff
, buff_size
, cmd_details
);
3956 *ret_buff_size
= le16_to_cpu(desc
.datalen
);
3958 *ret_next_table
= resp
->table_id
;
3960 *ret_next_index
= le32_to_cpu(resp
->idx
);
3967 * i40e_read_bw_from_alt_ram
3968 * @hw: pointer to the hardware structure
3969 * @max_bw: pointer for max_bw read
3970 * @min_bw: pointer for min_bw read
3971 * @min_valid: pointer for bool that is true if min_bw is a valid value
3972 * @max_valid: pointer for bool that is true if max_bw is a valid value
3974 * Read bw from the alternate ram for the given pf
3976 i40e_status
i40e_read_bw_from_alt_ram(struct i40e_hw
*hw
,
3977 u32
*max_bw
, u32
*min_bw
,
3978 bool *min_valid
, bool *max_valid
)
3981 u32 max_bw_addr
, min_bw_addr
;
3983 /* Calculate the address of the min/max bw registers */
3984 max_bw_addr
= I40E_ALT_STRUCT_FIRST_PF_OFFSET
+
3985 I40E_ALT_STRUCT_MAX_BW_OFFSET
+
3986 (I40E_ALT_STRUCT_DWORDS_PER_PF
* hw
->pf_id
);
3987 min_bw_addr
= I40E_ALT_STRUCT_FIRST_PF_OFFSET
+
3988 I40E_ALT_STRUCT_MIN_BW_OFFSET
+
3989 (I40E_ALT_STRUCT_DWORDS_PER_PF
* hw
->pf_id
);
3991 /* Read the bandwidths from alt ram */
3992 status
= i40e_aq_alternate_read(hw
, max_bw_addr
, max_bw
,
3993 min_bw_addr
, min_bw
);
3995 if (*min_bw
& I40E_ALT_BW_VALID_MASK
)
4000 if (*max_bw
& I40E_ALT_BW_VALID_MASK
)
4009 * i40e_aq_configure_partition_bw
4010 * @hw: pointer to the hardware structure
4011 * @bw_data: Buffer holding valid pfs and bw limits
4012 * @cmd_details: pointer to command details
4014 * Configure partitions guaranteed/max bw
4016 i40e_status
i40e_aq_configure_partition_bw(struct i40e_hw
*hw
,
4017 struct i40e_aqc_configure_partition_bw_data
*bw_data
,
4018 struct i40e_asq_cmd_details
*cmd_details
)
4021 struct i40e_aq_desc desc
;
4022 u16 bwd_size
= sizeof(*bw_data
);
4024 i40e_fill_default_direct_cmd_desc(&desc
,
4025 i40e_aqc_opc_configure_partition_bw
);
4027 /* Indirect command */
4028 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_BUF
);
4029 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_RD
);
4031 if (bwd_size
> I40E_AQ_LARGE_BUF
)
4032 desc
.flags
|= cpu_to_le16((u16
)I40E_AQ_FLAG_LB
);
4034 desc
.datalen
= cpu_to_le16(bwd_size
);
4036 status
= i40e_asq_send_command(hw
, &desc
, bw_data
, bwd_size
,