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Merge branch 'pm-devfreq'
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
31
32 /**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40 {
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
45 case I40E_DEV_ID_SFP_XL710:
46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_B:
48 case I40E_DEV_ID_KX_C:
49 case I40E_DEV_ID_QSFP_A:
50 case I40E_DEV_ID_QSFP_B:
51 case I40E_DEV_ID_QSFP_C:
52 case I40E_DEV_ID_10G_BASE_T:
53 case I40E_DEV_ID_10G_BASE_T4:
54 case I40E_DEV_ID_20G_KR2:
55 case I40E_DEV_ID_20G_KR2_A:
56 hw->mac.type = I40E_MAC_XL710;
57 break;
58 case I40E_DEV_ID_SFP_X722:
59 case I40E_DEV_ID_1G_BASE_T_X722:
60 case I40E_DEV_ID_10G_BASE_T_X722:
61 hw->mac.type = I40E_MAC_X722;
62 break;
63 case I40E_DEV_ID_X722_VF:
64 case I40E_DEV_ID_X722_VF_HV:
65 hw->mac.type = I40E_MAC_X722_VF;
66 break;
67 case I40E_DEV_ID_VF:
68 case I40E_DEV_ID_VF_HV:
69 hw->mac.type = I40E_MAC_VF;
70 break;
71 default:
72 hw->mac.type = I40E_MAC_GENERIC;
73 break;
74 }
75 } else {
76 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
77 }
78
79 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
80 hw->mac.type, status);
81 return status;
82 }
83
84 /**
85 * i40e_aq_str - convert AQ err code to a string
86 * @hw: pointer to the HW structure
87 * @aq_err: the AQ error code to convert
88 **/
89 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
90 {
91 switch (aq_err) {
92 case I40E_AQ_RC_OK:
93 return "OK";
94 case I40E_AQ_RC_EPERM:
95 return "I40E_AQ_RC_EPERM";
96 case I40E_AQ_RC_ENOENT:
97 return "I40E_AQ_RC_ENOENT";
98 case I40E_AQ_RC_ESRCH:
99 return "I40E_AQ_RC_ESRCH";
100 case I40E_AQ_RC_EINTR:
101 return "I40E_AQ_RC_EINTR";
102 case I40E_AQ_RC_EIO:
103 return "I40E_AQ_RC_EIO";
104 case I40E_AQ_RC_ENXIO:
105 return "I40E_AQ_RC_ENXIO";
106 case I40E_AQ_RC_E2BIG:
107 return "I40E_AQ_RC_E2BIG";
108 case I40E_AQ_RC_EAGAIN:
109 return "I40E_AQ_RC_EAGAIN";
110 case I40E_AQ_RC_ENOMEM:
111 return "I40E_AQ_RC_ENOMEM";
112 case I40E_AQ_RC_EACCES:
113 return "I40E_AQ_RC_EACCES";
114 case I40E_AQ_RC_EFAULT:
115 return "I40E_AQ_RC_EFAULT";
116 case I40E_AQ_RC_EBUSY:
117 return "I40E_AQ_RC_EBUSY";
118 case I40E_AQ_RC_EEXIST:
119 return "I40E_AQ_RC_EEXIST";
120 case I40E_AQ_RC_EINVAL:
121 return "I40E_AQ_RC_EINVAL";
122 case I40E_AQ_RC_ENOTTY:
123 return "I40E_AQ_RC_ENOTTY";
124 case I40E_AQ_RC_ENOSPC:
125 return "I40E_AQ_RC_ENOSPC";
126 case I40E_AQ_RC_ENOSYS:
127 return "I40E_AQ_RC_ENOSYS";
128 case I40E_AQ_RC_ERANGE:
129 return "I40E_AQ_RC_ERANGE";
130 case I40E_AQ_RC_EFLUSHED:
131 return "I40E_AQ_RC_EFLUSHED";
132 case I40E_AQ_RC_BAD_ADDR:
133 return "I40E_AQ_RC_BAD_ADDR";
134 case I40E_AQ_RC_EMODE:
135 return "I40E_AQ_RC_EMODE";
136 case I40E_AQ_RC_EFBIG:
137 return "I40E_AQ_RC_EFBIG";
138 }
139
140 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
141 return hw->err_str;
142 }
143
144 /**
145 * i40e_stat_str - convert status err code to a string
146 * @hw: pointer to the HW structure
147 * @stat_err: the status error code to convert
148 **/
149 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
150 {
151 switch (stat_err) {
152 case 0:
153 return "OK";
154 case I40E_ERR_NVM:
155 return "I40E_ERR_NVM";
156 case I40E_ERR_NVM_CHECKSUM:
157 return "I40E_ERR_NVM_CHECKSUM";
158 case I40E_ERR_PHY:
159 return "I40E_ERR_PHY";
160 case I40E_ERR_CONFIG:
161 return "I40E_ERR_CONFIG";
162 case I40E_ERR_PARAM:
163 return "I40E_ERR_PARAM";
164 case I40E_ERR_MAC_TYPE:
165 return "I40E_ERR_MAC_TYPE";
166 case I40E_ERR_UNKNOWN_PHY:
167 return "I40E_ERR_UNKNOWN_PHY";
168 case I40E_ERR_LINK_SETUP:
169 return "I40E_ERR_LINK_SETUP";
170 case I40E_ERR_ADAPTER_STOPPED:
171 return "I40E_ERR_ADAPTER_STOPPED";
172 case I40E_ERR_INVALID_MAC_ADDR:
173 return "I40E_ERR_INVALID_MAC_ADDR";
174 case I40E_ERR_DEVICE_NOT_SUPPORTED:
175 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
176 case I40E_ERR_MASTER_REQUESTS_PENDING:
177 return "I40E_ERR_MASTER_REQUESTS_PENDING";
178 case I40E_ERR_INVALID_LINK_SETTINGS:
179 return "I40E_ERR_INVALID_LINK_SETTINGS";
180 case I40E_ERR_AUTONEG_NOT_COMPLETE:
181 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
182 case I40E_ERR_RESET_FAILED:
183 return "I40E_ERR_RESET_FAILED";
184 case I40E_ERR_SWFW_SYNC:
185 return "I40E_ERR_SWFW_SYNC";
186 case I40E_ERR_NO_AVAILABLE_VSI:
187 return "I40E_ERR_NO_AVAILABLE_VSI";
188 case I40E_ERR_NO_MEMORY:
189 return "I40E_ERR_NO_MEMORY";
190 case I40E_ERR_BAD_PTR:
191 return "I40E_ERR_BAD_PTR";
192 case I40E_ERR_RING_FULL:
193 return "I40E_ERR_RING_FULL";
194 case I40E_ERR_INVALID_PD_ID:
195 return "I40E_ERR_INVALID_PD_ID";
196 case I40E_ERR_INVALID_QP_ID:
197 return "I40E_ERR_INVALID_QP_ID";
198 case I40E_ERR_INVALID_CQ_ID:
199 return "I40E_ERR_INVALID_CQ_ID";
200 case I40E_ERR_INVALID_CEQ_ID:
201 return "I40E_ERR_INVALID_CEQ_ID";
202 case I40E_ERR_INVALID_AEQ_ID:
203 return "I40E_ERR_INVALID_AEQ_ID";
204 case I40E_ERR_INVALID_SIZE:
205 return "I40E_ERR_INVALID_SIZE";
206 case I40E_ERR_INVALID_ARP_INDEX:
207 return "I40E_ERR_INVALID_ARP_INDEX";
208 case I40E_ERR_INVALID_FPM_FUNC_ID:
209 return "I40E_ERR_INVALID_FPM_FUNC_ID";
210 case I40E_ERR_QP_INVALID_MSG_SIZE:
211 return "I40E_ERR_QP_INVALID_MSG_SIZE";
212 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
213 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
214 case I40E_ERR_INVALID_FRAG_COUNT:
215 return "I40E_ERR_INVALID_FRAG_COUNT";
216 case I40E_ERR_QUEUE_EMPTY:
217 return "I40E_ERR_QUEUE_EMPTY";
218 case I40E_ERR_INVALID_ALIGNMENT:
219 return "I40E_ERR_INVALID_ALIGNMENT";
220 case I40E_ERR_FLUSHED_QUEUE:
221 return "I40E_ERR_FLUSHED_QUEUE";
222 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
223 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
224 case I40E_ERR_INVALID_IMM_DATA_SIZE:
225 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
226 case I40E_ERR_TIMEOUT:
227 return "I40E_ERR_TIMEOUT";
228 case I40E_ERR_OPCODE_MISMATCH:
229 return "I40E_ERR_OPCODE_MISMATCH";
230 case I40E_ERR_CQP_COMPL_ERROR:
231 return "I40E_ERR_CQP_COMPL_ERROR";
232 case I40E_ERR_INVALID_VF_ID:
233 return "I40E_ERR_INVALID_VF_ID";
234 case I40E_ERR_INVALID_HMCFN_ID:
235 return "I40E_ERR_INVALID_HMCFN_ID";
236 case I40E_ERR_BACKING_PAGE_ERROR:
237 return "I40E_ERR_BACKING_PAGE_ERROR";
238 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
239 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
240 case I40E_ERR_INVALID_PBLE_INDEX:
241 return "I40E_ERR_INVALID_PBLE_INDEX";
242 case I40E_ERR_INVALID_SD_INDEX:
243 return "I40E_ERR_INVALID_SD_INDEX";
244 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
245 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
246 case I40E_ERR_INVALID_SD_TYPE:
247 return "I40E_ERR_INVALID_SD_TYPE";
248 case I40E_ERR_MEMCPY_FAILED:
249 return "I40E_ERR_MEMCPY_FAILED";
250 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
251 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
252 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
253 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
254 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
255 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
256 case I40E_ERR_SRQ_ENABLED:
257 return "I40E_ERR_SRQ_ENABLED";
258 case I40E_ERR_ADMIN_QUEUE_ERROR:
259 return "I40E_ERR_ADMIN_QUEUE_ERROR";
260 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
261 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
262 case I40E_ERR_BUF_TOO_SHORT:
263 return "I40E_ERR_BUF_TOO_SHORT";
264 case I40E_ERR_ADMIN_QUEUE_FULL:
265 return "I40E_ERR_ADMIN_QUEUE_FULL";
266 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
267 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
268 case I40E_ERR_BAD_IWARP_CQE:
269 return "I40E_ERR_BAD_IWARP_CQE";
270 case I40E_ERR_NVM_BLANK_MODE:
271 return "I40E_ERR_NVM_BLANK_MODE";
272 case I40E_ERR_NOT_IMPLEMENTED:
273 return "I40E_ERR_NOT_IMPLEMENTED";
274 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
275 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
276 case I40E_ERR_DIAG_TEST_FAILED:
277 return "I40E_ERR_DIAG_TEST_FAILED";
278 case I40E_ERR_NOT_READY:
279 return "I40E_ERR_NOT_READY";
280 case I40E_NOT_SUPPORTED:
281 return "I40E_NOT_SUPPORTED";
282 case I40E_ERR_FIRMWARE_API_VERSION:
283 return "I40E_ERR_FIRMWARE_API_VERSION";
284 }
285
286 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
287 return hw->err_str;
288 }
289
290 /**
291 * i40e_debug_aq
292 * @hw: debug mask related to admin queue
293 * @mask: debug mask
294 * @desc: pointer to admin queue descriptor
295 * @buffer: pointer to command buffer
296 * @buf_len: max length of buffer
297 *
298 * Dumps debug log about adminq command with descriptor contents.
299 **/
300 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
301 void *buffer, u16 buf_len)
302 {
303 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
304 u16 len = le16_to_cpu(aq_desc->datalen);
305 u8 *buf = (u8 *)buffer;
306 u16 i = 0;
307
308 if ((!(mask & hw->debug_mask)) || (desc == NULL))
309 return;
310
311 i40e_debug(hw, mask,
312 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
313 le16_to_cpu(aq_desc->opcode),
314 le16_to_cpu(aq_desc->flags),
315 le16_to_cpu(aq_desc->datalen),
316 le16_to_cpu(aq_desc->retval));
317 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
318 le32_to_cpu(aq_desc->cookie_high),
319 le32_to_cpu(aq_desc->cookie_low));
320 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
321 le32_to_cpu(aq_desc->params.internal.param0),
322 le32_to_cpu(aq_desc->params.internal.param1));
323 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
324 le32_to_cpu(aq_desc->params.external.addr_high),
325 le32_to_cpu(aq_desc->params.external.addr_low));
326
327 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
328 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
329 if (buf_len < len)
330 len = buf_len;
331 /* write the full 16-byte chunks */
332 for (i = 0; i < (len - 16); i += 16)
333 i40e_debug(hw, mask, "\t0x%04X %16ph\n", i, buf + i);
334 /* write whatever's left over without overrunning the buffer */
335 if (i < len)
336 i40e_debug(hw, mask, "\t0x%04X %*ph\n",
337 i, len - i, buf + i);
338 }
339 }
340
341 /**
342 * i40e_check_asq_alive
343 * @hw: pointer to the hw struct
344 *
345 * Returns true if Queue is enabled else false.
346 **/
347 bool i40e_check_asq_alive(struct i40e_hw *hw)
348 {
349 if (hw->aq.asq.len)
350 return !!(rd32(hw, hw->aq.asq.len) &
351 I40E_PF_ATQLEN_ATQENABLE_MASK);
352 else
353 return false;
354 }
355
356 /**
357 * i40e_aq_queue_shutdown
358 * @hw: pointer to the hw struct
359 * @unloading: is the driver unloading itself
360 *
361 * Tell the Firmware that we're shutting down the AdminQ and whether
362 * or not the driver is unloading as well.
363 **/
364 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
365 bool unloading)
366 {
367 struct i40e_aq_desc desc;
368 struct i40e_aqc_queue_shutdown *cmd =
369 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
370 i40e_status status;
371
372 i40e_fill_default_direct_cmd_desc(&desc,
373 i40e_aqc_opc_queue_shutdown);
374
375 if (unloading)
376 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
377 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
378
379 return status;
380 }
381
382 /**
383 * i40e_aq_get_set_rss_lut
384 * @hw: pointer to the hardware structure
385 * @vsi_id: vsi fw index
386 * @pf_lut: for PF table set true, for VSI table set false
387 * @lut: pointer to the lut buffer provided by the caller
388 * @lut_size: size of the lut buffer
389 * @set: set true to set the table, false to get the table
390 *
391 * Internal function to get or set RSS look up table
392 **/
393 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
394 u16 vsi_id, bool pf_lut,
395 u8 *lut, u16 lut_size,
396 bool set)
397 {
398 i40e_status status;
399 struct i40e_aq_desc desc;
400 struct i40e_aqc_get_set_rss_lut *cmd_resp =
401 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
402
403 if (set)
404 i40e_fill_default_direct_cmd_desc(&desc,
405 i40e_aqc_opc_set_rss_lut);
406 else
407 i40e_fill_default_direct_cmd_desc(&desc,
408 i40e_aqc_opc_get_rss_lut);
409
410 /* Indirect command */
411 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
412 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
413
414 cmd_resp->vsi_id =
415 cpu_to_le16((u16)((vsi_id <<
416 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
417 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
418 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
419
420 if (pf_lut)
421 cmd_resp->flags |= cpu_to_le16((u16)
422 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
423 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
424 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
425 else
426 cmd_resp->flags |= cpu_to_le16((u16)
427 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
428 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
429 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
430
431 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
432
433 return status;
434 }
435
436 /**
437 * i40e_aq_get_rss_lut
438 * @hw: pointer to the hardware structure
439 * @vsi_id: vsi fw index
440 * @pf_lut: for PF table set true, for VSI table set false
441 * @lut: pointer to the lut buffer provided by the caller
442 * @lut_size: size of the lut buffer
443 *
444 * get the RSS lookup table, PF or VSI type
445 **/
446 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
447 bool pf_lut, u8 *lut, u16 lut_size)
448 {
449 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
450 false);
451 }
452
453 /**
454 * i40e_aq_set_rss_lut
455 * @hw: pointer to the hardware structure
456 * @vsi_id: vsi fw index
457 * @pf_lut: for PF table set true, for VSI table set false
458 * @lut: pointer to the lut buffer provided by the caller
459 * @lut_size: size of the lut buffer
460 *
461 * set the RSS lookup table, PF or VSI type
462 **/
463 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
464 bool pf_lut, u8 *lut, u16 lut_size)
465 {
466 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
467 }
468
469 /**
470 * i40e_aq_get_set_rss_key
471 * @hw: pointer to the hw struct
472 * @vsi_id: vsi fw index
473 * @key: pointer to key info struct
474 * @set: set true to set the key, false to get the key
475 *
476 * get the RSS key per VSI
477 **/
478 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
479 u16 vsi_id,
480 struct i40e_aqc_get_set_rss_key_data *key,
481 bool set)
482 {
483 i40e_status status;
484 struct i40e_aq_desc desc;
485 struct i40e_aqc_get_set_rss_key *cmd_resp =
486 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
487 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
488
489 if (set)
490 i40e_fill_default_direct_cmd_desc(&desc,
491 i40e_aqc_opc_set_rss_key);
492 else
493 i40e_fill_default_direct_cmd_desc(&desc,
494 i40e_aqc_opc_get_rss_key);
495
496 /* Indirect command */
497 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
498 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
499
500 cmd_resp->vsi_id =
501 cpu_to_le16((u16)((vsi_id <<
502 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
503 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
504 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
505
506 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
507
508 return status;
509 }
510
511 /**
512 * i40e_aq_get_rss_key
513 * @hw: pointer to the hw struct
514 * @vsi_id: vsi fw index
515 * @key: pointer to key info struct
516 *
517 **/
518 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
519 u16 vsi_id,
520 struct i40e_aqc_get_set_rss_key_data *key)
521 {
522 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
523 }
524
525 /**
526 * i40e_aq_set_rss_key
527 * @hw: pointer to the hw struct
528 * @vsi_id: vsi fw index
529 * @key: pointer to key info struct
530 *
531 * set the RSS key per VSI
532 **/
533 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
534 u16 vsi_id,
535 struct i40e_aqc_get_set_rss_key_data *key)
536 {
537 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
538 }
539
540 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
541 * hardware to a bit-field that can be used by SW to more easily determine the
542 * packet type.
543 *
544 * Macros are used to shorten the table lines and make this table human
545 * readable.
546 *
547 * We store the PTYPE in the top byte of the bit field - this is just so that
548 * we can check that the table doesn't have a row missing, as the index into
549 * the table should be the PTYPE.
550 *
551 * Typical work flow:
552 *
553 * IF NOT i40e_ptype_lookup[ptype].known
554 * THEN
555 * Packet is unknown
556 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
557 * Use the rest of the fields to look at the tunnels, inner protocols, etc
558 * ELSE
559 * Use the enum i40e_rx_l2_ptype to decode the packet type
560 * ENDIF
561 */
562
563 /* macro to make the table lines short */
564 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
565 { PTYPE, \
566 1, \
567 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
568 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
569 I40E_RX_PTYPE_##OUTER_FRAG, \
570 I40E_RX_PTYPE_TUNNEL_##T, \
571 I40E_RX_PTYPE_TUNNEL_END_##TE, \
572 I40E_RX_PTYPE_##TEF, \
573 I40E_RX_PTYPE_INNER_PROT_##I, \
574 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
575
576 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
577 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
578
579 /* shorter macros makes the table fit but are terse */
580 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
581 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
582 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
583
584 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
585 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
586 /* L2 Packet types */
587 I40E_PTT_UNUSED_ENTRY(0),
588 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
589 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
590 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
591 I40E_PTT_UNUSED_ENTRY(4),
592 I40E_PTT_UNUSED_ENTRY(5),
593 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
594 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
595 I40E_PTT_UNUSED_ENTRY(8),
596 I40E_PTT_UNUSED_ENTRY(9),
597 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
598 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
599 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
600 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
601 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
602 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
603 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
604 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
605 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
606 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
607 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
608 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
609
610 /* Non Tunneled IPv4 */
611 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
612 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
613 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
614 I40E_PTT_UNUSED_ENTRY(25),
615 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
616 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
617 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
618
619 /* IPv4 --> IPv4 */
620 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
621 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
622 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
623 I40E_PTT_UNUSED_ENTRY(32),
624 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
625 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
626 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
627
628 /* IPv4 --> IPv6 */
629 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
630 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
631 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
632 I40E_PTT_UNUSED_ENTRY(39),
633 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
634 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
635 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
636
637 /* IPv4 --> GRE/NAT */
638 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
639
640 /* IPv4 --> GRE/NAT --> IPv4 */
641 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
642 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
643 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
644 I40E_PTT_UNUSED_ENTRY(47),
645 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
646 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
647 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
648
649 /* IPv4 --> GRE/NAT --> IPv6 */
650 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
651 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
652 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
653 I40E_PTT_UNUSED_ENTRY(54),
654 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
655 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
656 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
657
658 /* IPv4 --> GRE/NAT --> MAC */
659 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
660
661 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
662 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
663 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
664 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
665 I40E_PTT_UNUSED_ENTRY(62),
666 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
667 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
668 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
669
670 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
671 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
672 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
673 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
674 I40E_PTT_UNUSED_ENTRY(69),
675 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
676 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
677 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
678
679 /* IPv4 --> GRE/NAT --> MAC/VLAN */
680 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
681
682 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
683 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
684 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
685 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
686 I40E_PTT_UNUSED_ENTRY(77),
687 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
688 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
689 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
690
691 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
692 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
693 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
694 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
695 I40E_PTT_UNUSED_ENTRY(84),
696 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
697 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
698 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
699
700 /* Non Tunneled IPv6 */
701 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
702 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
703 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
704 I40E_PTT_UNUSED_ENTRY(91),
705 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
706 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
707 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
708
709 /* IPv6 --> IPv4 */
710 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
711 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
712 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
713 I40E_PTT_UNUSED_ENTRY(98),
714 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
715 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
716 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
717
718 /* IPv6 --> IPv6 */
719 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
720 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
721 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
722 I40E_PTT_UNUSED_ENTRY(105),
723 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
724 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
725 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
726
727 /* IPv6 --> GRE/NAT */
728 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
729
730 /* IPv6 --> GRE/NAT -> IPv4 */
731 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
732 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
733 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
734 I40E_PTT_UNUSED_ENTRY(113),
735 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
736 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
737 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
738
739 /* IPv6 --> GRE/NAT -> IPv6 */
740 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
741 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
742 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
743 I40E_PTT_UNUSED_ENTRY(120),
744 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
745 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
746 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
747
748 /* IPv6 --> GRE/NAT -> MAC */
749 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
750
751 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
752 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
753 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
754 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
755 I40E_PTT_UNUSED_ENTRY(128),
756 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
757 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
758 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
759
760 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
761 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
762 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
763 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
764 I40E_PTT_UNUSED_ENTRY(135),
765 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
766 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
767 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
768
769 /* IPv6 --> GRE/NAT -> MAC/VLAN */
770 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
771
772 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
773 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
774 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
775 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
776 I40E_PTT_UNUSED_ENTRY(143),
777 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
778 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
779 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
780
781 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
782 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
783 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
784 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
785 I40E_PTT_UNUSED_ENTRY(150),
786 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
787 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
788 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
789
790 /* unused entries */
791 I40E_PTT_UNUSED_ENTRY(154),
792 I40E_PTT_UNUSED_ENTRY(155),
793 I40E_PTT_UNUSED_ENTRY(156),
794 I40E_PTT_UNUSED_ENTRY(157),
795 I40E_PTT_UNUSED_ENTRY(158),
796 I40E_PTT_UNUSED_ENTRY(159),
797
798 I40E_PTT_UNUSED_ENTRY(160),
799 I40E_PTT_UNUSED_ENTRY(161),
800 I40E_PTT_UNUSED_ENTRY(162),
801 I40E_PTT_UNUSED_ENTRY(163),
802 I40E_PTT_UNUSED_ENTRY(164),
803 I40E_PTT_UNUSED_ENTRY(165),
804 I40E_PTT_UNUSED_ENTRY(166),
805 I40E_PTT_UNUSED_ENTRY(167),
806 I40E_PTT_UNUSED_ENTRY(168),
807 I40E_PTT_UNUSED_ENTRY(169),
808
809 I40E_PTT_UNUSED_ENTRY(170),
810 I40E_PTT_UNUSED_ENTRY(171),
811 I40E_PTT_UNUSED_ENTRY(172),
812 I40E_PTT_UNUSED_ENTRY(173),
813 I40E_PTT_UNUSED_ENTRY(174),
814 I40E_PTT_UNUSED_ENTRY(175),
815 I40E_PTT_UNUSED_ENTRY(176),
816 I40E_PTT_UNUSED_ENTRY(177),
817 I40E_PTT_UNUSED_ENTRY(178),
818 I40E_PTT_UNUSED_ENTRY(179),
819
820 I40E_PTT_UNUSED_ENTRY(180),
821 I40E_PTT_UNUSED_ENTRY(181),
822 I40E_PTT_UNUSED_ENTRY(182),
823 I40E_PTT_UNUSED_ENTRY(183),
824 I40E_PTT_UNUSED_ENTRY(184),
825 I40E_PTT_UNUSED_ENTRY(185),
826 I40E_PTT_UNUSED_ENTRY(186),
827 I40E_PTT_UNUSED_ENTRY(187),
828 I40E_PTT_UNUSED_ENTRY(188),
829 I40E_PTT_UNUSED_ENTRY(189),
830
831 I40E_PTT_UNUSED_ENTRY(190),
832 I40E_PTT_UNUSED_ENTRY(191),
833 I40E_PTT_UNUSED_ENTRY(192),
834 I40E_PTT_UNUSED_ENTRY(193),
835 I40E_PTT_UNUSED_ENTRY(194),
836 I40E_PTT_UNUSED_ENTRY(195),
837 I40E_PTT_UNUSED_ENTRY(196),
838 I40E_PTT_UNUSED_ENTRY(197),
839 I40E_PTT_UNUSED_ENTRY(198),
840 I40E_PTT_UNUSED_ENTRY(199),
841
842 I40E_PTT_UNUSED_ENTRY(200),
843 I40E_PTT_UNUSED_ENTRY(201),
844 I40E_PTT_UNUSED_ENTRY(202),
845 I40E_PTT_UNUSED_ENTRY(203),
846 I40E_PTT_UNUSED_ENTRY(204),
847 I40E_PTT_UNUSED_ENTRY(205),
848 I40E_PTT_UNUSED_ENTRY(206),
849 I40E_PTT_UNUSED_ENTRY(207),
850 I40E_PTT_UNUSED_ENTRY(208),
851 I40E_PTT_UNUSED_ENTRY(209),
852
853 I40E_PTT_UNUSED_ENTRY(210),
854 I40E_PTT_UNUSED_ENTRY(211),
855 I40E_PTT_UNUSED_ENTRY(212),
856 I40E_PTT_UNUSED_ENTRY(213),
857 I40E_PTT_UNUSED_ENTRY(214),
858 I40E_PTT_UNUSED_ENTRY(215),
859 I40E_PTT_UNUSED_ENTRY(216),
860 I40E_PTT_UNUSED_ENTRY(217),
861 I40E_PTT_UNUSED_ENTRY(218),
862 I40E_PTT_UNUSED_ENTRY(219),
863
864 I40E_PTT_UNUSED_ENTRY(220),
865 I40E_PTT_UNUSED_ENTRY(221),
866 I40E_PTT_UNUSED_ENTRY(222),
867 I40E_PTT_UNUSED_ENTRY(223),
868 I40E_PTT_UNUSED_ENTRY(224),
869 I40E_PTT_UNUSED_ENTRY(225),
870 I40E_PTT_UNUSED_ENTRY(226),
871 I40E_PTT_UNUSED_ENTRY(227),
872 I40E_PTT_UNUSED_ENTRY(228),
873 I40E_PTT_UNUSED_ENTRY(229),
874
875 I40E_PTT_UNUSED_ENTRY(230),
876 I40E_PTT_UNUSED_ENTRY(231),
877 I40E_PTT_UNUSED_ENTRY(232),
878 I40E_PTT_UNUSED_ENTRY(233),
879 I40E_PTT_UNUSED_ENTRY(234),
880 I40E_PTT_UNUSED_ENTRY(235),
881 I40E_PTT_UNUSED_ENTRY(236),
882 I40E_PTT_UNUSED_ENTRY(237),
883 I40E_PTT_UNUSED_ENTRY(238),
884 I40E_PTT_UNUSED_ENTRY(239),
885
886 I40E_PTT_UNUSED_ENTRY(240),
887 I40E_PTT_UNUSED_ENTRY(241),
888 I40E_PTT_UNUSED_ENTRY(242),
889 I40E_PTT_UNUSED_ENTRY(243),
890 I40E_PTT_UNUSED_ENTRY(244),
891 I40E_PTT_UNUSED_ENTRY(245),
892 I40E_PTT_UNUSED_ENTRY(246),
893 I40E_PTT_UNUSED_ENTRY(247),
894 I40E_PTT_UNUSED_ENTRY(248),
895 I40E_PTT_UNUSED_ENTRY(249),
896
897 I40E_PTT_UNUSED_ENTRY(250),
898 I40E_PTT_UNUSED_ENTRY(251),
899 I40E_PTT_UNUSED_ENTRY(252),
900 I40E_PTT_UNUSED_ENTRY(253),
901 I40E_PTT_UNUSED_ENTRY(254),
902 I40E_PTT_UNUSED_ENTRY(255)
903 };
904
905 /**
906 * i40e_init_shared_code - Initialize the shared code
907 * @hw: pointer to hardware structure
908 *
909 * This assigns the MAC type and PHY code and inits the NVM.
910 * Does not touch the hardware. This function must be called prior to any
911 * other function in the shared code. The i40e_hw structure should be
912 * memset to 0 prior to calling this function. The following fields in
913 * hw structure should be filled in prior to calling this function:
914 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
915 * subsystem_vendor_id, and revision_id
916 **/
917 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
918 {
919 i40e_status status = 0;
920 u32 port, ari, func_rid;
921
922 i40e_set_mac_type(hw);
923
924 switch (hw->mac.type) {
925 case I40E_MAC_XL710:
926 case I40E_MAC_X722:
927 break;
928 default:
929 return I40E_ERR_DEVICE_NOT_SUPPORTED;
930 }
931
932 hw->phy.get_link_info = true;
933
934 /* Determine port number and PF number*/
935 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
936 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
937 hw->port = (u8)port;
938 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
939 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
940 func_rid = rd32(hw, I40E_PF_FUNC_RID);
941 if (ari)
942 hw->pf_id = (u8)(func_rid & 0xff);
943 else
944 hw->pf_id = (u8)(func_rid & 0x7);
945
946 if (hw->mac.type == I40E_MAC_X722)
947 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
948
949 status = i40e_init_nvm(hw);
950 return status;
951 }
952
953 /**
954 * i40e_aq_mac_address_read - Retrieve the MAC addresses
955 * @hw: pointer to the hw struct
956 * @flags: a return indicator of what addresses were added to the addr store
957 * @addrs: the requestor's mac addr store
958 * @cmd_details: pointer to command details structure or NULL
959 **/
960 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
961 u16 *flags,
962 struct i40e_aqc_mac_address_read_data *addrs,
963 struct i40e_asq_cmd_details *cmd_details)
964 {
965 struct i40e_aq_desc desc;
966 struct i40e_aqc_mac_address_read *cmd_data =
967 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
968 i40e_status status;
969
970 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
971 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
972
973 status = i40e_asq_send_command(hw, &desc, addrs,
974 sizeof(*addrs), cmd_details);
975 *flags = le16_to_cpu(cmd_data->command_flags);
976
977 return status;
978 }
979
980 /**
981 * i40e_aq_mac_address_write - Change the MAC addresses
982 * @hw: pointer to the hw struct
983 * @flags: indicates which MAC to be written
984 * @mac_addr: address to write
985 * @cmd_details: pointer to command details structure or NULL
986 **/
987 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
988 u16 flags, u8 *mac_addr,
989 struct i40e_asq_cmd_details *cmd_details)
990 {
991 struct i40e_aq_desc desc;
992 struct i40e_aqc_mac_address_write *cmd_data =
993 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
994 i40e_status status;
995
996 i40e_fill_default_direct_cmd_desc(&desc,
997 i40e_aqc_opc_mac_address_write);
998 cmd_data->command_flags = cpu_to_le16(flags);
999 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
1000 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
1001 ((u32)mac_addr[3] << 16) |
1002 ((u32)mac_addr[4] << 8) |
1003 mac_addr[5]);
1004
1005 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1006
1007 return status;
1008 }
1009
1010 /**
1011 * i40e_get_mac_addr - get MAC address
1012 * @hw: pointer to the HW structure
1013 * @mac_addr: pointer to MAC address
1014 *
1015 * Reads the adapter's MAC address from register
1016 **/
1017 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1018 {
1019 struct i40e_aqc_mac_address_read_data addrs;
1020 i40e_status status;
1021 u16 flags = 0;
1022
1023 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1024
1025 if (flags & I40E_AQC_LAN_ADDR_VALID)
1026 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
1027
1028 return status;
1029 }
1030
1031 /**
1032 * i40e_get_port_mac_addr - get Port MAC address
1033 * @hw: pointer to the HW structure
1034 * @mac_addr: pointer to Port MAC address
1035 *
1036 * Reads the adapter's Port MAC address
1037 **/
1038 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1039 {
1040 struct i40e_aqc_mac_address_read_data addrs;
1041 i40e_status status;
1042 u16 flags = 0;
1043
1044 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1045 if (status)
1046 return status;
1047
1048 if (flags & I40E_AQC_PORT_ADDR_VALID)
1049 ether_addr_copy(mac_addr, addrs.port_mac);
1050 else
1051 status = I40E_ERR_INVALID_MAC_ADDR;
1052
1053 return status;
1054 }
1055
1056 /**
1057 * i40e_pre_tx_queue_cfg - pre tx queue configure
1058 * @hw: pointer to the HW structure
1059 * @queue: target PF queue index
1060 * @enable: state change request
1061 *
1062 * Handles hw requirement to indicate intention to enable
1063 * or disable target queue.
1064 **/
1065 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1066 {
1067 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1068 u32 reg_block = 0;
1069 u32 reg_val;
1070
1071 if (abs_queue_idx >= 128) {
1072 reg_block = abs_queue_idx / 128;
1073 abs_queue_idx %= 128;
1074 }
1075
1076 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1077 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1078 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1079
1080 if (enable)
1081 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1082 else
1083 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1084
1085 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1086 }
1087 #ifdef I40E_FCOE
1088
1089 /**
1090 * i40e_get_san_mac_addr - get SAN MAC address
1091 * @hw: pointer to the HW structure
1092 * @mac_addr: pointer to SAN MAC address
1093 *
1094 * Reads the adapter's SAN MAC address from NVM
1095 **/
1096 i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1097 {
1098 struct i40e_aqc_mac_address_read_data addrs;
1099 i40e_status status;
1100 u16 flags = 0;
1101
1102 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1103 if (status)
1104 return status;
1105
1106 if (flags & I40E_AQC_SAN_ADDR_VALID)
1107 ether_addr_copy(mac_addr, addrs.pf_san_mac);
1108 else
1109 status = I40E_ERR_INVALID_MAC_ADDR;
1110
1111 return status;
1112 }
1113 #endif
1114
1115 /**
1116 * i40e_read_pba_string - Reads part number string from EEPROM
1117 * @hw: pointer to hardware structure
1118 * @pba_num: stores the part number string from the EEPROM
1119 * @pba_num_size: part number string buffer length
1120 *
1121 * Reads the part number string from the EEPROM.
1122 **/
1123 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1124 u32 pba_num_size)
1125 {
1126 i40e_status status = 0;
1127 u16 pba_word = 0;
1128 u16 pba_size = 0;
1129 u16 pba_ptr = 0;
1130 u16 i = 0;
1131
1132 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1133 if (status || (pba_word != 0xFAFA)) {
1134 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1135 return status;
1136 }
1137
1138 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1139 if (status) {
1140 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1141 return status;
1142 }
1143
1144 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1145 if (status) {
1146 hw_dbg(hw, "Failed to read PBA Block size.\n");
1147 return status;
1148 }
1149
1150 /* Subtract one to get PBA word count (PBA Size word is included in
1151 * total size)
1152 */
1153 pba_size--;
1154 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1155 hw_dbg(hw, "Buffer to small for PBA data.\n");
1156 return I40E_ERR_PARAM;
1157 }
1158
1159 for (i = 0; i < pba_size; i++) {
1160 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1161 if (status) {
1162 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1163 return status;
1164 }
1165
1166 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1167 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1168 }
1169 pba_num[(pba_size * 2)] = '\0';
1170
1171 return status;
1172 }
1173
1174 /**
1175 * i40e_get_media_type - Gets media type
1176 * @hw: pointer to the hardware structure
1177 **/
1178 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1179 {
1180 enum i40e_media_type media;
1181
1182 switch (hw->phy.link_info.phy_type) {
1183 case I40E_PHY_TYPE_10GBASE_SR:
1184 case I40E_PHY_TYPE_10GBASE_LR:
1185 case I40E_PHY_TYPE_1000BASE_SX:
1186 case I40E_PHY_TYPE_1000BASE_LX:
1187 case I40E_PHY_TYPE_40GBASE_SR4:
1188 case I40E_PHY_TYPE_40GBASE_LR4:
1189 media = I40E_MEDIA_TYPE_FIBER;
1190 break;
1191 case I40E_PHY_TYPE_100BASE_TX:
1192 case I40E_PHY_TYPE_1000BASE_T:
1193 case I40E_PHY_TYPE_10GBASE_T:
1194 media = I40E_MEDIA_TYPE_BASET;
1195 break;
1196 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1197 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1198 case I40E_PHY_TYPE_10GBASE_CR1:
1199 case I40E_PHY_TYPE_40GBASE_CR4:
1200 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1201 case I40E_PHY_TYPE_40GBASE_AOC:
1202 case I40E_PHY_TYPE_10GBASE_AOC:
1203 media = I40E_MEDIA_TYPE_DA;
1204 break;
1205 case I40E_PHY_TYPE_1000BASE_KX:
1206 case I40E_PHY_TYPE_10GBASE_KX4:
1207 case I40E_PHY_TYPE_10GBASE_KR:
1208 case I40E_PHY_TYPE_40GBASE_KR4:
1209 case I40E_PHY_TYPE_20GBASE_KR2:
1210 media = I40E_MEDIA_TYPE_BACKPLANE;
1211 break;
1212 case I40E_PHY_TYPE_SGMII:
1213 case I40E_PHY_TYPE_XAUI:
1214 case I40E_PHY_TYPE_XFI:
1215 case I40E_PHY_TYPE_XLAUI:
1216 case I40E_PHY_TYPE_XLPPI:
1217 default:
1218 media = I40E_MEDIA_TYPE_UNKNOWN;
1219 break;
1220 }
1221
1222 return media;
1223 }
1224
1225 #define I40E_PF_RESET_WAIT_COUNT_A0 200
1226 #define I40E_PF_RESET_WAIT_COUNT 200
1227 /**
1228 * i40e_pf_reset - Reset the PF
1229 * @hw: pointer to the hardware structure
1230 *
1231 * Assuming someone else has triggered a global reset,
1232 * assure the global reset is complete and then reset the PF
1233 **/
1234 i40e_status i40e_pf_reset(struct i40e_hw *hw)
1235 {
1236 u32 cnt = 0;
1237 u32 cnt1 = 0;
1238 u32 reg = 0;
1239 u32 grst_del;
1240
1241 /* Poll for Global Reset steady state in case of recent GRST.
1242 * The grst delay value is in 100ms units, and we'll wait a
1243 * couple counts longer to be sure we don't just miss the end.
1244 */
1245 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1246 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1247 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1248 for (cnt = 0; cnt < grst_del + 10; cnt++) {
1249 reg = rd32(hw, I40E_GLGEN_RSTAT);
1250 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1251 break;
1252 msleep(100);
1253 }
1254 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1255 hw_dbg(hw, "Global reset polling failed to complete.\n");
1256 return I40E_ERR_RESET_FAILED;
1257 }
1258
1259 /* Now Wait for the FW to be ready */
1260 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1261 reg = rd32(hw, I40E_GLNVM_ULD);
1262 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1263 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1264 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1265 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1266 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1267 break;
1268 }
1269 usleep_range(10000, 20000);
1270 }
1271 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1272 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1273 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1274 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1275 return I40E_ERR_RESET_FAILED;
1276 }
1277
1278 /* If there was a Global Reset in progress when we got here,
1279 * we don't need to do the PF Reset
1280 */
1281 if (!cnt) {
1282 if (hw->revision_id == 0)
1283 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1284 else
1285 cnt = I40E_PF_RESET_WAIT_COUNT;
1286 reg = rd32(hw, I40E_PFGEN_CTRL);
1287 wr32(hw, I40E_PFGEN_CTRL,
1288 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1289 for (; cnt; cnt--) {
1290 reg = rd32(hw, I40E_PFGEN_CTRL);
1291 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1292 break;
1293 usleep_range(1000, 2000);
1294 }
1295 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1296 hw_dbg(hw, "PF reset polling failed to complete.\n");
1297 return I40E_ERR_RESET_FAILED;
1298 }
1299 }
1300
1301 i40e_clear_pxe_mode(hw);
1302
1303 return 0;
1304 }
1305
1306 /**
1307 * i40e_clear_hw - clear out any left over hw state
1308 * @hw: pointer to the hw struct
1309 *
1310 * Clear queues and interrupts, typically called at init time,
1311 * but after the capabilities have been found so we know how many
1312 * queues and msix vectors have been allocated.
1313 **/
1314 void i40e_clear_hw(struct i40e_hw *hw)
1315 {
1316 u32 num_queues, base_queue;
1317 u32 num_pf_int;
1318 u32 num_vf_int;
1319 u32 num_vfs;
1320 u32 i, j;
1321 u32 val;
1322 u32 eol = 0x7ff;
1323
1324 /* get number of interrupts, queues, and VFs */
1325 val = rd32(hw, I40E_GLPCI_CNF2);
1326 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1327 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1328 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1329 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1330
1331 val = rd32(hw, I40E_PFLAN_QALLOC);
1332 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1333 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1334 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1335 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1336 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1337 num_queues = (j - base_queue) + 1;
1338 else
1339 num_queues = 0;
1340
1341 val = rd32(hw, I40E_PF_VT_PFALLOC);
1342 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1343 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1344 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1345 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1346 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1347 num_vfs = (j - i) + 1;
1348 else
1349 num_vfs = 0;
1350
1351 /* stop all the interrupts */
1352 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1353 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1354 for (i = 0; i < num_pf_int - 2; i++)
1355 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1356
1357 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1358 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1359 wr32(hw, I40E_PFINT_LNKLST0, val);
1360 for (i = 0; i < num_pf_int - 2; i++)
1361 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1362 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1363 for (i = 0; i < num_vfs; i++)
1364 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1365 for (i = 0; i < num_vf_int - 2; i++)
1366 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1367
1368 /* warn the HW of the coming Tx disables */
1369 for (i = 0; i < num_queues; i++) {
1370 u32 abs_queue_idx = base_queue + i;
1371 u32 reg_block = 0;
1372
1373 if (abs_queue_idx >= 128) {
1374 reg_block = abs_queue_idx / 128;
1375 abs_queue_idx %= 128;
1376 }
1377
1378 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1379 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1380 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1381 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1382
1383 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1384 }
1385 udelay(400);
1386
1387 /* stop all the queues */
1388 for (i = 0; i < num_queues; i++) {
1389 wr32(hw, I40E_QINT_TQCTL(i), 0);
1390 wr32(hw, I40E_QTX_ENA(i), 0);
1391 wr32(hw, I40E_QINT_RQCTL(i), 0);
1392 wr32(hw, I40E_QRX_ENA(i), 0);
1393 }
1394
1395 /* short wait for all queue disables to settle */
1396 udelay(50);
1397 }
1398
1399 /**
1400 * i40e_clear_pxe_mode - clear pxe operations mode
1401 * @hw: pointer to the hw struct
1402 *
1403 * Make sure all PXE mode settings are cleared, including things
1404 * like descriptor fetch/write-back mode.
1405 **/
1406 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1407 {
1408 u32 reg;
1409
1410 if (i40e_check_asq_alive(hw))
1411 i40e_aq_clear_pxe_mode(hw, NULL);
1412
1413 /* Clear single descriptor fetch/write-back mode */
1414 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1415
1416 if (hw->revision_id == 0) {
1417 /* As a work around clear PXE_MODE instead of setting it */
1418 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1419 } else {
1420 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1421 }
1422 }
1423
1424 /**
1425 * i40e_led_is_mine - helper to find matching led
1426 * @hw: pointer to the hw struct
1427 * @idx: index into GPIO registers
1428 *
1429 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1430 */
1431 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1432 {
1433 u32 gpio_val = 0;
1434 u32 port;
1435
1436 if (!hw->func_caps.led[idx])
1437 return 0;
1438
1439 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1440 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1441 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1442
1443 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1444 * if it is not our port then ignore
1445 */
1446 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1447 (port != hw->port))
1448 return 0;
1449
1450 return gpio_val;
1451 }
1452
1453 #define I40E_COMBINED_ACTIVITY 0xA
1454 #define I40E_FILTER_ACTIVITY 0xE
1455 #define I40E_LINK_ACTIVITY 0xC
1456 #define I40E_MAC_ACTIVITY 0xD
1457 #define I40E_LED0 22
1458
1459 /**
1460 * i40e_led_get - return current on/off mode
1461 * @hw: pointer to the hw struct
1462 *
1463 * The value returned is the 'mode' field as defined in the
1464 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1465 * values are variations of possible behaviors relating to
1466 * blink, link, and wire.
1467 **/
1468 u32 i40e_led_get(struct i40e_hw *hw)
1469 {
1470 u32 current_mode = 0;
1471 u32 mode = 0;
1472 int i;
1473
1474 /* as per the documentation GPIO 22-29 are the LED
1475 * GPIO pins named LED0..LED7
1476 */
1477 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1478 u32 gpio_val = i40e_led_is_mine(hw, i);
1479
1480 if (!gpio_val)
1481 continue;
1482
1483 /* ignore gpio LED src mode entries related to the activity
1484 * LEDs
1485 */
1486 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1487 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1488 switch (current_mode) {
1489 case I40E_COMBINED_ACTIVITY:
1490 case I40E_FILTER_ACTIVITY:
1491 case I40E_MAC_ACTIVITY:
1492 continue;
1493 default:
1494 break;
1495 }
1496
1497 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1498 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1499 break;
1500 }
1501
1502 return mode;
1503 }
1504
1505 /**
1506 * i40e_led_set - set new on/off mode
1507 * @hw: pointer to the hw struct
1508 * @mode: 0=off, 0xf=on (else see manual for mode details)
1509 * @blink: true if the LED should blink when on, false if steady
1510 *
1511 * if this function is used to turn on the blink it should
1512 * be used to disable the blink when restoring the original state.
1513 **/
1514 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1515 {
1516 u32 current_mode = 0;
1517 int i;
1518
1519 if (mode & 0xfffffff0)
1520 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1521
1522 /* as per the documentation GPIO 22-29 are the LED
1523 * GPIO pins named LED0..LED7
1524 */
1525 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1526 u32 gpio_val = i40e_led_is_mine(hw, i);
1527
1528 if (!gpio_val)
1529 continue;
1530
1531 /* ignore gpio LED src mode entries related to the activity
1532 * LEDs
1533 */
1534 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1535 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1536 switch (current_mode) {
1537 case I40E_COMBINED_ACTIVITY:
1538 case I40E_FILTER_ACTIVITY:
1539 case I40E_MAC_ACTIVITY:
1540 continue;
1541 default:
1542 break;
1543 }
1544
1545 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1546 /* this & is a bit of paranoia, but serves as a range check */
1547 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1548 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1549
1550 if (mode == I40E_LINK_ACTIVITY)
1551 blink = false;
1552
1553 if (blink)
1554 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1555 else
1556 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1557
1558 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1559 break;
1560 }
1561 }
1562
1563 /* Admin command wrappers */
1564
1565 /**
1566 * i40e_aq_get_phy_capabilities
1567 * @hw: pointer to the hw struct
1568 * @abilities: structure for PHY capabilities to be filled
1569 * @qualified_modules: report Qualified Modules
1570 * @report_init: report init capabilities (active are default)
1571 * @cmd_details: pointer to command details structure or NULL
1572 *
1573 * Returns the various PHY abilities supported on the Port.
1574 **/
1575 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1576 bool qualified_modules, bool report_init,
1577 struct i40e_aq_get_phy_abilities_resp *abilities,
1578 struct i40e_asq_cmd_details *cmd_details)
1579 {
1580 struct i40e_aq_desc desc;
1581 i40e_status status;
1582 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1583
1584 if (!abilities)
1585 return I40E_ERR_PARAM;
1586
1587 i40e_fill_default_direct_cmd_desc(&desc,
1588 i40e_aqc_opc_get_phy_abilities);
1589
1590 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1591 if (abilities_size > I40E_AQ_LARGE_BUF)
1592 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1593
1594 if (qualified_modules)
1595 desc.params.external.param0 |=
1596 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1597
1598 if (report_init)
1599 desc.params.external.param0 |=
1600 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1601
1602 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1603 cmd_details);
1604
1605 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1606 status = I40E_ERR_UNKNOWN_PHY;
1607
1608 if (report_init)
1609 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1610
1611 return status;
1612 }
1613
1614 /**
1615 * i40e_aq_set_phy_config
1616 * @hw: pointer to the hw struct
1617 * @config: structure with PHY configuration to be set
1618 * @cmd_details: pointer to command details structure or NULL
1619 *
1620 * Set the various PHY configuration parameters
1621 * supported on the Port.One or more of the Set PHY config parameters may be
1622 * ignored in an MFP mode as the PF may not have the privilege to set some
1623 * of the PHY Config parameters. This status will be indicated by the
1624 * command response.
1625 **/
1626 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1627 struct i40e_aq_set_phy_config *config,
1628 struct i40e_asq_cmd_details *cmd_details)
1629 {
1630 struct i40e_aq_desc desc;
1631 struct i40e_aq_set_phy_config *cmd =
1632 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1633 enum i40e_status_code status;
1634
1635 if (!config)
1636 return I40E_ERR_PARAM;
1637
1638 i40e_fill_default_direct_cmd_desc(&desc,
1639 i40e_aqc_opc_set_phy_config);
1640
1641 *cmd = *config;
1642
1643 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1644
1645 return status;
1646 }
1647
1648 /**
1649 * i40e_set_fc
1650 * @hw: pointer to the hw struct
1651 *
1652 * Set the requested flow control mode using set_phy_config.
1653 **/
1654 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1655 bool atomic_restart)
1656 {
1657 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1658 struct i40e_aq_get_phy_abilities_resp abilities;
1659 struct i40e_aq_set_phy_config config;
1660 enum i40e_status_code status;
1661 u8 pause_mask = 0x0;
1662
1663 *aq_failures = 0x0;
1664
1665 switch (fc_mode) {
1666 case I40E_FC_FULL:
1667 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1668 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1669 break;
1670 case I40E_FC_RX_PAUSE:
1671 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1672 break;
1673 case I40E_FC_TX_PAUSE:
1674 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1675 break;
1676 default:
1677 break;
1678 }
1679
1680 /* Get the current phy config */
1681 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1682 NULL);
1683 if (status) {
1684 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1685 return status;
1686 }
1687
1688 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1689 /* clear the old pause settings */
1690 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1691 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1692 /* set the new abilities */
1693 config.abilities |= pause_mask;
1694 /* If the abilities have changed, then set the new config */
1695 if (config.abilities != abilities.abilities) {
1696 /* Auto restart link so settings take effect */
1697 if (atomic_restart)
1698 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1699 /* Copy over all the old settings */
1700 config.phy_type = abilities.phy_type;
1701 config.link_speed = abilities.link_speed;
1702 config.eee_capability = abilities.eee_capability;
1703 config.eeer = abilities.eeer_val;
1704 config.low_power_ctrl = abilities.d3_lpan;
1705 status = i40e_aq_set_phy_config(hw, &config, NULL);
1706
1707 if (status)
1708 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1709 }
1710 /* Update the link info */
1711 status = i40e_update_link_info(hw);
1712 if (status) {
1713 /* Wait a little bit (on 40G cards it sometimes takes a really
1714 * long time for link to come back from the atomic reset)
1715 * and try once more
1716 */
1717 msleep(1000);
1718 status = i40e_update_link_info(hw);
1719 }
1720 if (status)
1721 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1722
1723 return status;
1724 }
1725
1726 /**
1727 * i40e_aq_clear_pxe_mode
1728 * @hw: pointer to the hw struct
1729 * @cmd_details: pointer to command details structure or NULL
1730 *
1731 * Tell the firmware that the driver is taking over from PXE
1732 **/
1733 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1734 struct i40e_asq_cmd_details *cmd_details)
1735 {
1736 i40e_status status;
1737 struct i40e_aq_desc desc;
1738 struct i40e_aqc_clear_pxe *cmd =
1739 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1740
1741 i40e_fill_default_direct_cmd_desc(&desc,
1742 i40e_aqc_opc_clear_pxe_mode);
1743
1744 cmd->rx_cnt = 0x2;
1745
1746 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1747
1748 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1749
1750 return status;
1751 }
1752
1753 /**
1754 * i40e_aq_set_link_restart_an
1755 * @hw: pointer to the hw struct
1756 * @enable_link: if true: enable link, if false: disable link
1757 * @cmd_details: pointer to command details structure or NULL
1758 *
1759 * Sets up the link and restarts the Auto-Negotiation over the link.
1760 **/
1761 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1762 bool enable_link,
1763 struct i40e_asq_cmd_details *cmd_details)
1764 {
1765 struct i40e_aq_desc desc;
1766 struct i40e_aqc_set_link_restart_an *cmd =
1767 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1768 i40e_status status;
1769
1770 i40e_fill_default_direct_cmd_desc(&desc,
1771 i40e_aqc_opc_set_link_restart_an);
1772
1773 cmd->command = I40E_AQ_PHY_RESTART_AN;
1774 if (enable_link)
1775 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1776 else
1777 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1778
1779 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1780
1781 return status;
1782 }
1783
1784 /**
1785 * i40e_aq_get_link_info
1786 * @hw: pointer to the hw struct
1787 * @enable_lse: enable/disable LinkStatusEvent reporting
1788 * @link: pointer to link status structure - optional
1789 * @cmd_details: pointer to command details structure or NULL
1790 *
1791 * Returns the link status of the adapter.
1792 **/
1793 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1794 bool enable_lse, struct i40e_link_status *link,
1795 struct i40e_asq_cmd_details *cmd_details)
1796 {
1797 struct i40e_aq_desc desc;
1798 struct i40e_aqc_get_link_status *resp =
1799 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1800 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1801 i40e_status status;
1802 bool tx_pause, rx_pause;
1803 u16 command_flags;
1804
1805 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1806
1807 if (enable_lse)
1808 command_flags = I40E_AQ_LSE_ENABLE;
1809 else
1810 command_flags = I40E_AQ_LSE_DISABLE;
1811 resp->command_flags = cpu_to_le16(command_flags);
1812
1813 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1814
1815 if (status)
1816 goto aq_get_link_info_exit;
1817
1818 /* save off old link status information */
1819 hw->phy.link_info_old = *hw_link_info;
1820
1821 /* update link status */
1822 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1823 hw->phy.media_type = i40e_get_media_type(hw);
1824 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1825 hw_link_info->link_info = resp->link_info;
1826 hw_link_info->an_info = resp->an_info;
1827 hw_link_info->ext_info = resp->ext_info;
1828 hw_link_info->loopback = resp->loopback;
1829 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1830 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1831
1832 /* update fc info */
1833 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1834 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1835 if (tx_pause & rx_pause)
1836 hw->fc.current_mode = I40E_FC_FULL;
1837 else if (tx_pause)
1838 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1839 else if (rx_pause)
1840 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1841 else
1842 hw->fc.current_mode = I40E_FC_NONE;
1843
1844 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1845 hw_link_info->crc_enable = true;
1846 else
1847 hw_link_info->crc_enable = false;
1848
1849 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1850 hw_link_info->lse_enable = true;
1851 else
1852 hw_link_info->lse_enable = false;
1853
1854 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1855 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1856 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1857
1858 /* save link status information */
1859 if (link)
1860 *link = *hw_link_info;
1861
1862 /* flag cleared so helper functions don't call AQ again */
1863 hw->phy.get_link_info = false;
1864
1865 aq_get_link_info_exit:
1866 return status;
1867 }
1868
1869 /**
1870 * i40e_aq_set_phy_int_mask
1871 * @hw: pointer to the hw struct
1872 * @mask: interrupt mask to be set
1873 * @cmd_details: pointer to command details structure or NULL
1874 *
1875 * Set link interrupt mask.
1876 **/
1877 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1878 u16 mask,
1879 struct i40e_asq_cmd_details *cmd_details)
1880 {
1881 struct i40e_aq_desc desc;
1882 struct i40e_aqc_set_phy_int_mask *cmd =
1883 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1884 i40e_status status;
1885
1886 i40e_fill_default_direct_cmd_desc(&desc,
1887 i40e_aqc_opc_set_phy_int_mask);
1888
1889 cmd->event_mask = cpu_to_le16(mask);
1890
1891 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1892
1893 return status;
1894 }
1895
1896 /**
1897 * i40e_aq_add_vsi
1898 * @hw: pointer to the hw struct
1899 * @vsi_ctx: pointer to a vsi context struct
1900 * @cmd_details: pointer to command details structure or NULL
1901 *
1902 * Add a VSI context to the hardware.
1903 **/
1904 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1905 struct i40e_vsi_context *vsi_ctx,
1906 struct i40e_asq_cmd_details *cmd_details)
1907 {
1908 struct i40e_aq_desc desc;
1909 struct i40e_aqc_add_get_update_vsi *cmd =
1910 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1911 struct i40e_aqc_add_get_update_vsi_completion *resp =
1912 (struct i40e_aqc_add_get_update_vsi_completion *)
1913 &desc.params.raw;
1914 i40e_status status;
1915
1916 i40e_fill_default_direct_cmd_desc(&desc,
1917 i40e_aqc_opc_add_vsi);
1918
1919 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1920 cmd->connection_type = vsi_ctx->connection_type;
1921 cmd->vf_id = vsi_ctx->vf_num;
1922 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1923
1924 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1925
1926 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1927 sizeof(vsi_ctx->info), cmd_details);
1928
1929 if (status)
1930 goto aq_add_vsi_exit;
1931
1932 vsi_ctx->seid = le16_to_cpu(resp->seid);
1933 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1934 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1935 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1936
1937 aq_add_vsi_exit:
1938 return status;
1939 }
1940
1941 /**
1942 * i40e_aq_set_vsi_unicast_promiscuous
1943 * @hw: pointer to the hw struct
1944 * @seid: vsi number
1945 * @set: set unicast promiscuous enable/disable
1946 * @cmd_details: pointer to command details structure or NULL
1947 **/
1948 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1949 u16 seid, bool set,
1950 struct i40e_asq_cmd_details *cmd_details)
1951 {
1952 struct i40e_aq_desc desc;
1953 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1954 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1955 i40e_status status;
1956 u16 flags = 0;
1957
1958 i40e_fill_default_direct_cmd_desc(&desc,
1959 i40e_aqc_opc_set_vsi_promiscuous_modes);
1960
1961 if (set)
1962 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1963
1964 cmd->promiscuous_flags = cpu_to_le16(flags);
1965
1966 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1967
1968 cmd->seid = cpu_to_le16(seid);
1969 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1970
1971 return status;
1972 }
1973
1974 /**
1975 * i40e_aq_set_vsi_multicast_promiscuous
1976 * @hw: pointer to the hw struct
1977 * @seid: vsi number
1978 * @set: set multicast promiscuous enable/disable
1979 * @cmd_details: pointer to command details structure or NULL
1980 **/
1981 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1982 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1983 {
1984 struct i40e_aq_desc desc;
1985 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1986 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1987 i40e_status status;
1988 u16 flags = 0;
1989
1990 i40e_fill_default_direct_cmd_desc(&desc,
1991 i40e_aqc_opc_set_vsi_promiscuous_modes);
1992
1993 if (set)
1994 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1995
1996 cmd->promiscuous_flags = cpu_to_le16(flags);
1997
1998 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1999
2000 cmd->seid = cpu_to_le16(seid);
2001 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2002
2003 return status;
2004 }
2005
2006 /**
2007 * i40e_aq_set_vsi_broadcast
2008 * @hw: pointer to the hw struct
2009 * @seid: vsi number
2010 * @set_filter: true to set filter, false to clear filter
2011 * @cmd_details: pointer to command details structure or NULL
2012 *
2013 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2014 **/
2015 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2016 u16 seid, bool set_filter,
2017 struct i40e_asq_cmd_details *cmd_details)
2018 {
2019 struct i40e_aq_desc desc;
2020 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2021 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2022 i40e_status status;
2023
2024 i40e_fill_default_direct_cmd_desc(&desc,
2025 i40e_aqc_opc_set_vsi_promiscuous_modes);
2026
2027 if (set_filter)
2028 cmd->promiscuous_flags
2029 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2030 else
2031 cmd->promiscuous_flags
2032 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2033
2034 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2035 cmd->seid = cpu_to_le16(seid);
2036 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2037
2038 return status;
2039 }
2040
2041 /**
2042 * i40e_get_vsi_params - get VSI configuration info
2043 * @hw: pointer to the hw struct
2044 * @vsi_ctx: pointer to a vsi context struct
2045 * @cmd_details: pointer to command details structure or NULL
2046 **/
2047 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2048 struct i40e_vsi_context *vsi_ctx,
2049 struct i40e_asq_cmd_details *cmd_details)
2050 {
2051 struct i40e_aq_desc desc;
2052 struct i40e_aqc_add_get_update_vsi *cmd =
2053 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2054 struct i40e_aqc_add_get_update_vsi_completion *resp =
2055 (struct i40e_aqc_add_get_update_vsi_completion *)
2056 &desc.params.raw;
2057 i40e_status status;
2058
2059 i40e_fill_default_direct_cmd_desc(&desc,
2060 i40e_aqc_opc_get_vsi_parameters);
2061
2062 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2063
2064 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2065
2066 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2067 sizeof(vsi_ctx->info), NULL);
2068
2069 if (status)
2070 goto aq_get_vsi_params_exit;
2071
2072 vsi_ctx->seid = le16_to_cpu(resp->seid);
2073 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2074 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2075 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2076
2077 aq_get_vsi_params_exit:
2078 return status;
2079 }
2080
2081 /**
2082 * i40e_aq_update_vsi_params
2083 * @hw: pointer to the hw struct
2084 * @vsi_ctx: pointer to a vsi context struct
2085 * @cmd_details: pointer to command details structure or NULL
2086 *
2087 * Update a VSI context.
2088 **/
2089 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2090 struct i40e_vsi_context *vsi_ctx,
2091 struct i40e_asq_cmd_details *cmd_details)
2092 {
2093 struct i40e_aq_desc desc;
2094 struct i40e_aqc_add_get_update_vsi *cmd =
2095 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2096 i40e_status status;
2097
2098 i40e_fill_default_direct_cmd_desc(&desc,
2099 i40e_aqc_opc_update_vsi_parameters);
2100 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2101
2102 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2103
2104 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2105 sizeof(vsi_ctx->info), cmd_details);
2106
2107 return status;
2108 }
2109
2110 /**
2111 * i40e_aq_get_switch_config
2112 * @hw: pointer to the hardware structure
2113 * @buf: pointer to the result buffer
2114 * @buf_size: length of input buffer
2115 * @start_seid: seid to start for the report, 0 == beginning
2116 * @cmd_details: pointer to command details structure or NULL
2117 *
2118 * Fill the buf with switch configuration returned from AdminQ command
2119 **/
2120 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2121 struct i40e_aqc_get_switch_config_resp *buf,
2122 u16 buf_size, u16 *start_seid,
2123 struct i40e_asq_cmd_details *cmd_details)
2124 {
2125 struct i40e_aq_desc desc;
2126 struct i40e_aqc_switch_seid *scfg =
2127 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2128 i40e_status status;
2129
2130 i40e_fill_default_direct_cmd_desc(&desc,
2131 i40e_aqc_opc_get_switch_config);
2132 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2133 if (buf_size > I40E_AQ_LARGE_BUF)
2134 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2135 scfg->seid = cpu_to_le16(*start_seid);
2136
2137 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2138 *start_seid = le16_to_cpu(scfg->seid);
2139
2140 return status;
2141 }
2142
2143 /**
2144 * i40e_aq_get_firmware_version
2145 * @hw: pointer to the hw struct
2146 * @fw_major_version: firmware major version
2147 * @fw_minor_version: firmware minor version
2148 * @fw_build: firmware build number
2149 * @api_major_version: major queue version
2150 * @api_minor_version: minor queue version
2151 * @cmd_details: pointer to command details structure or NULL
2152 *
2153 * Get the firmware version from the admin queue commands
2154 **/
2155 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2156 u16 *fw_major_version, u16 *fw_minor_version,
2157 u32 *fw_build,
2158 u16 *api_major_version, u16 *api_minor_version,
2159 struct i40e_asq_cmd_details *cmd_details)
2160 {
2161 struct i40e_aq_desc desc;
2162 struct i40e_aqc_get_version *resp =
2163 (struct i40e_aqc_get_version *)&desc.params.raw;
2164 i40e_status status;
2165
2166 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2167
2168 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2169
2170 if (!status) {
2171 if (fw_major_version)
2172 *fw_major_version = le16_to_cpu(resp->fw_major);
2173 if (fw_minor_version)
2174 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2175 if (fw_build)
2176 *fw_build = le32_to_cpu(resp->fw_build);
2177 if (api_major_version)
2178 *api_major_version = le16_to_cpu(resp->api_major);
2179 if (api_minor_version)
2180 *api_minor_version = le16_to_cpu(resp->api_minor);
2181 }
2182
2183 return status;
2184 }
2185
2186 /**
2187 * i40e_aq_send_driver_version
2188 * @hw: pointer to the hw struct
2189 * @dv: driver's major, minor version
2190 * @cmd_details: pointer to command details structure or NULL
2191 *
2192 * Send the driver version to the firmware
2193 **/
2194 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2195 struct i40e_driver_version *dv,
2196 struct i40e_asq_cmd_details *cmd_details)
2197 {
2198 struct i40e_aq_desc desc;
2199 struct i40e_aqc_driver_version *cmd =
2200 (struct i40e_aqc_driver_version *)&desc.params.raw;
2201 i40e_status status;
2202 u16 len;
2203
2204 if (dv == NULL)
2205 return I40E_ERR_PARAM;
2206
2207 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2208
2209 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2210 cmd->driver_major_ver = dv->major_version;
2211 cmd->driver_minor_ver = dv->minor_version;
2212 cmd->driver_build_ver = dv->build_version;
2213 cmd->driver_subbuild_ver = dv->subbuild_version;
2214
2215 len = 0;
2216 while (len < sizeof(dv->driver_string) &&
2217 (dv->driver_string[len] < 0x80) &&
2218 dv->driver_string[len])
2219 len++;
2220 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2221 len, cmd_details);
2222
2223 return status;
2224 }
2225
2226 /**
2227 * i40e_get_link_status - get status of the HW network link
2228 * @hw: pointer to the hw struct
2229 * @link_up: pointer to bool (true/false = linkup/linkdown)
2230 *
2231 * Variable link_up true if link is up, false if link is down.
2232 * The variable link_up is invalid if returned value of status != 0
2233 *
2234 * Side effect: LinkStatusEvent reporting becomes enabled
2235 **/
2236 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2237 {
2238 i40e_status status = 0;
2239
2240 if (hw->phy.get_link_info) {
2241 status = i40e_update_link_info(hw);
2242
2243 if (status)
2244 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2245 status);
2246 }
2247
2248 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2249
2250 return status;
2251 }
2252
2253 /**
2254 * i40e_updatelink_status - update status of the HW network link
2255 * @hw: pointer to the hw struct
2256 **/
2257 i40e_status i40e_update_link_info(struct i40e_hw *hw)
2258 {
2259 struct i40e_aq_get_phy_abilities_resp abilities;
2260 i40e_status status = 0;
2261
2262 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2263 if (status)
2264 return status;
2265
2266 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2267 status = i40e_aq_get_phy_capabilities(hw, false, false,
2268 &abilities, NULL);
2269 if (status)
2270 return status;
2271
2272 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2273 sizeof(hw->phy.link_info.module_type));
2274 }
2275
2276 return status;
2277 }
2278
2279 /**
2280 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2281 * @hw: pointer to the hw struct
2282 * @uplink_seid: the MAC or other gizmo SEID
2283 * @downlink_seid: the VSI SEID
2284 * @enabled_tc: bitmap of TCs to be enabled
2285 * @default_port: true for default port VSI, false for control port
2286 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2287 * @veb_seid: pointer to where to put the resulting VEB SEID
2288 * @cmd_details: pointer to command details structure or NULL
2289 *
2290 * This asks the FW to add a VEB between the uplink and downlink
2291 * elements. If the uplink SEID is 0, this will be a floating VEB.
2292 **/
2293 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2294 u16 downlink_seid, u8 enabled_tc,
2295 bool default_port, bool enable_l2_filtering,
2296 u16 *veb_seid,
2297 struct i40e_asq_cmd_details *cmd_details)
2298 {
2299 struct i40e_aq_desc desc;
2300 struct i40e_aqc_add_veb *cmd =
2301 (struct i40e_aqc_add_veb *)&desc.params.raw;
2302 struct i40e_aqc_add_veb_completion *resp =
2303 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2304 i40e_status status;
2305 u16 veb_flags = 0;
2306
2307 /* SEIDs need to either both be set or both be 0 for floating VEB */
2308 if (!!uplink_seid != !!downlink_seid)
2309 return I40E_ERR_PARAM;
2310
2311 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2312
2313 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2314 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2315 cmd->enable_tcs = enabled_tc;
2316 if (!uplink_seid)
2317 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2318 if (default_port)
2319 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2320 else
2321 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2322
2323 if (enable_l2_filtering)
2324 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2325
2326 cmd->veb_flags = cpu_to_le16(veb_flags);
2327
2328 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2329
2330 if (!status && veb_seid)
2331 *veb_seid = le16_to_cpu(resp->veb_seid);
2332
2333 return status;
2334 }
2335
2336 /**
2337 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2338 * @hw: pointer to the hw struct
2339 * @veb_seid: the SEID of the VEB to query
2340 * @switch_id: the uplink switch id
2341 * @floating: set to true if the VEB is floating
2342 * @statistic_index: index of the stats counter block for this VEB
2343 * @vebs_used: number of VEB's used by function
2344 * @vebs_free: total VEB's not reserved by any function
2345 * @cmd_details: pointer to command details structure or NULL
2346 *
2347 * This retrieves the parameters for a particular VEB, specified by
2348 * uplink_seid, and returns them to the caller.
2349 **/
2350 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2351 u16 veb_seid, u16 *switch_id,
2352 bool *floating, u16 *statistic_index,
2353 u16 *vebs_used, u16 *vebs_free,
2354 struct i40e_asq_cmd_details *cmd_details)
2355 {
2356 struct i40e_aq_desc desc;
2357 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2358 (struct i40e_aqc_get_veb_parameters_completion *)
2359 &desc.params.raw;
2360 i40e_status status;
2361
2362 if (veb_seid == 0)
2363 return I40E_ERR_PARAM;
2364
2365 i40e_fill_default_direct_cmd_desc(&desc,
2366 i40e_aqc_opc_get_veb_parameters);
2367 cmd_resp->seid = cpu_to_le16(veb_seid);
2368
2369 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2370 if (status)
2371 goto get_veb_exit;
2372
2373 if (switch_id)
2374 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2375 if (statistic_index)
2376 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2377 if (vebs_used)
2378 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2379 if (vebs_free)
2380 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2381 if (floating) {
2382 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2383
2384 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2385 *floating = true;
2386 else
2387 *floating = false;
2388 }
2389
2390 get_veb_exit:
2391 return status;
2392 }
2393
2394 /**
2395 * i40e_aq_add_macvlan
2396 * @hw: pointer to the hw struct
2397 * @seid: VSI for the mac address
2398 * @mv_list: list of macvlans to be added
2399 * @count: length of the list
2400 * @cmd_details: pointer to command details structure or NULL
2401 *
2402 * Add MAC/VLAN addresses to the HW filtering
2403 **/
2404 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2405 struct i40e_aqc_add_macvlan_element_data *mv_list,
2406 u16 count, struct i40e_asq_cmd_details *cmd_details)
2407 {
2408 struct i40e_aq_desc desc;
2409 struct i40e_aqc_macvlan *cmd =
2410 (struct i40e_aqc_macvlan *)&desc.params.raw;
2411 i40e_status status;
2412 u16 buf_size;
2413
2414 if (count == 0 || !mv_list || !hw)
2415 return I40E_ERR_PARAM;
2416
2417 buf_size = count * sizeof(*mv_list);
2418
2419 /* prep the rest of the request */
2420 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2421 cmd->num_addresses = cpu_to_le16(count);
2422 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2423 cmd->seid[1] = 0;
2424 cmd->seid[2] = 0;
2425
2426 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2427 if (buf_size > I40E_AQ_LARGE_BUF)
2428 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2429
2430 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2431 cmd_details);
2432
2433 return status;
2434 }
2435
2436 /**
2437 * i40e_aq_remove_macvlan
2438 * @hw: pointer to the hw struct
2439 * @seid: VSI for the mac address
2440 * @mv_list: list of macvlans to be removed
2441 * @count: length of the list
2442 * @cmd_details: pointer to command details structure or NULL
2443 *
2444 * Remove MAC/VLAN addresses from the HW filtering
2445 **/
2446 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2447 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2448 u16 count, struct i40e_asq_cmd_details *cmd_details)
2449 {
2450 struct i40e_aq_desc desc;
2451 struct i40e_aqc_macvlan *cmd =
2452 (struct i40e_aqc_macvlan *)&desc.params.raw;
2453 i40e_status status;
2454 u16 buf_size;
2455
2456 if (count == 0 || !mv_list || !hw)
2457 return I40E_ERR_PARAM;
2458
2459 buf_size = count * sizeof(*mv_list);
2460
2461 /* prep the rest of the request */
2462 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2463 cmd->num_addresses = cpu_to_le16(count);
2464 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2465 cmd->seid[1] = 0;
2466 cmd->seid[2] = 0;
2467
2468 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2469 if (buf_size > I40E_AQ_LARGE_BUF)
2470 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2471
2472 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2473 cmd_details);
2474
2475 return status;
2476 }
2477
2478 /**
2479 * i40e_aq_send_msg_to_vf
2480 * @hw: pointer to the hardware structure
2481 * @vfid: VF id to send msg
2482 * @v_opcode: opcodes for VF-PF communication
2483 * @v_retval: return error code
2484 * @msg: pointer to the msg buffer
2485 * @msglen: msg length
2486 * @cmd_details: pointer to command details
2487 *
2488 * send msg to vf
2489 **/
2490 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2491 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2492 struct i40e_asq_cmd_details *cmd_details)
2493 {
2494 struct i40e_aq_desc desc;
2495 struct i40e_aqc_pf_vf_message *cmd =
2496 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2497 i40e_status status;
2498
2499 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2500 cmd->id = cpu_to_le32(vfid);
2501 desc.cookie_high = cpu_to_le32(v_opcode);
2502 desc.cookie_low = cpu_to_le32(v_retval);
2503 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2504 if (msglen) {
2505 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2506 I40E_AQ_FLAG_RD));
2507 if (msglen > I40E_AQ_LARGE_BUF)
2508 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2509 desc.datalen = cpu_to_le16(msglen);
2510 }
2511 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2512
2513 return status;
2514 }
2515
2516 /**
2517 * i40e_aq_debug_read_register
2518 * @hw: pointer to the hw struct
2519 * @reg_addr: register address
2520 * @reg_val: register value
2521 * @cmd_details: pointer to command details structure or NULL
2522 *
2523 * Read the register using the admin queue commands
2524 **/
2525 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2526 u32 reg_addr, u64 *reg_val,
2527 struct i40e_asq_cmd_details *cmd_details)
2528 {
2529 struct i40e_aq_desc desc;
2530 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2531 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2532 i40e_status status;
2533
2534 if (reg_val == NULL)
2535 return I40E_ERR_PARAM;
2536
2537 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2538
2539 cmd_resp->address = cpu_to_le32(reg_addr);
2540
2541 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2542
2543 if (!status) {
2544 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2545 (u64)le32_to_cpu(cmd_resp->value_low);
2546 }
2547
2548 return status;
2549 }
2550
2551 /**
2552 * i40e_aq_debug_write_register
2553 * @hw: pointer to the hw struct
2554 * @reg_addr: register address
2555 * @reg_val: register value
2556 * @cmd_details: pointer to command details structure or NULL
2557 *
2558 * Write to a register using the admin queue commands
2559 **/
2560 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2561 u32 reg_addr, u64 reg_val,
2562 struct i40e_asq_cmd_details *cmd_details)
2563 {
2564 struct i40e_aq_desc desc;
2565 struct i40e_aqc_debug_reg_read_write *cmd =
2566 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2567 i40e_status status;
2568
2569 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2570
2571 cmd->address = cpu_to_le32(reg_addr);
2572 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2573 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2574
2575 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2576
2577 return status;
2578 }
2579
2580 /**
2581 * i40e_aq_set_hmc_resource_profile
2582 * @hw: pointer to the hw struct
2583 * @profile: type of profile the HMC is to be set as
2584 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2585 * @cmd_details: pointer to command details structure or NULL
2586 *
2587 * set the HMC profile of the device.
2588 **/
2589 i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2590 enum i40e_aq_hmc_profile profile,
2591 u8 pe_vf_enabled_count,
2592 struct i40e_asq_cmd_details *cmd_details)
2593 {
2594 struct i40e_aq_desc desc;
2595 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2596 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2597 i40e_status status;
2598
2599 i40e_fill_default_direct_cmd_desc(&desc,
2600 i40e_aqc_opc_set_hmc_resource_profile);
2601
2602 cmd->pm_profile = (u8)profile;
2603 cmd->pe_vf_enabled = pe_vf_enabled_count;
2604
2605 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2606
2607 return status;
2608 }
2609
2610 /**
2611 * i40e_aq_request_resource
2612 * @hw: pointer to the hw struct
2613 * @resource: resource id
2614 * @access: access type
2615 * @sdp_number: resource number
2616 * @timeout: the maximum time in ms that the driver may hold the resource
2617 * @cmd_details: pointer to command details structure or NULL
2618 *
2619 * requests common resource using the admin queue commands
2620 **/
2621 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2622 enum i40e_aq_resources_ids resource,
2623 enum i40e_aq_resource_access_type access,
2624 u8 sdp_number, u64 *timeout,
2625 struct i40e_asq_cmd_details *cmd_details)
2626 {
2627 struct i40e_aq_desc desc;
2628 struct i40e_aqc_request_resource *cmd_resp =
2629 (struct i40e_aqc_request_resource *)&desc.params.raw;
2630 i40e_status status;
2631
2632 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2633
2634 cmd_resp->resource_id = cpu_to_le16(resource);
2635 cmd_resp->access_type = cpu_to_le16(access);
2636 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2637
2638 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2639 /* The completion specifies the maximum time in ms that the driver
2640 * may hold the resource in the Timeout field.
2641 * If the resource is held by someone else, the command completes with
2642 * busy return value and the timeout field indicates the maximum time
2643 * the current owner of the resource has to free it.
2644 */
2645 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2646 *timeout = le32_to_cpu(cmd_resp->timeout);
2647
2648 return status;
2649 }
2650
2651 /**
2652 * i40e_aq_release_resource
2653 * @hw: pointer to the hw struct
2654 * @resource: resource id
2655 * @sdp_number: resource number
2656 * @cmd_details: pointer to command details structure or NULL
2657 *
2658 * release common resource using the admin queue commands
2659 **/
2660 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2661 enum i40e_aq_resources_ids resource,
2662 u8 sdp_number,
2663 struct i40e_asq_cmd_details *cmd_details)
2664 {
2665 struct i40e_aq_desc desc;
2666 struct i40e_aqc_request_resource *cmd =
2667 (struct i40e_aqc_request_resource *)&desc.params.raw;
2668 i40e_status status;
2669
2670 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2671
2672 cmd->resource_id = cpu_to_le16(resource);
2673 cmd->resource_number = cpu_to_le32(sdp_number);
2674
2675 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2676
2677 return status;
2678 }
2679
2680 /**
2681 * i40e_aq_read_nvm
2682 * @hw: pointer to the hw struct
2683 * @module_pointer: module pointer location in words from the NVM beginning
2684 * @offset: byte offset from the module beginning
2685 * @length: length of the section to be read (in bytes from the offset)
2686 * @data: command buffer (size [bytes] = length)
2687 * @last_command: tells if this is the last command in a series
2688 * @cmd_details: pointer to command details structure or NULL
2689 *
2690 * Read the NVM using the admin queue commands
2691 **/
2692 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2693 u32 offset, u16 length, void *data,
2694 bool last_command,
2695 struct i40e_asq_cmd_details *cmd_details)
2696 {
2697 struct i40e_aq_desc desc;
2698 struct i40e_aqc_nvm_update *cmd =
2699 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2700 i40e_status status;
2701
2702 /* In offset the highest byte must be zeroed. */
2703 if (offset & 0xFF000000) {
2704 status = I40E_ERR_PARAM;
2705 goto i40e_aq_read_nvm_exit;
2706 }
2707
2708 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2709
2710 /* If this is the last command in a series, set the proper flag. */
2711 if (last_command)
2712 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2713 cmd->module_pointer = module_pointer;
2714 cmd->offset = cpu_to_le32(offset);
2715 cmd->length = cpu_to_le16(length);
2716
2717 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2718 if (length > I40E_AQ_LARGE_BUF)
2719 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2720
2721 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2722
2723 i40e_aq_read_nvm_exit:
2724 return status;
2725 }
2726
2727 /**
2728 * i40e_aq_erase_nvm
2729 * @hw: pointer to the hw struct
2730 * @module_pointer: module pointer location in words from the NVM beginning
2731 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2732 * @length: length of the section to be erased (expressed in 4 KB)
2733 * @last_command: tells if this is the last command in a series
2734 * @cmd_details: pointer to command details structure or NULL
2735 *
2736 * Erase the NVM sector using the admin queue commands
2737 **/
2738 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2739 u32 offset, u16 length, bool last_command,
2740 struct i40e_asq_cmd_details *cmd_details)
2741 {
2742 struct i40e_aq_desc desc;
2743 struct i40e_aqc_nvm_update *cmd =
2744 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2745 i40e_status status;
2746
2747 /* In offset the highest byte must be zeroed. */
2748 if (offset & 0xFF000000) {
2749 status = I40E_ERR_PARAM;
2750 goto i40e_aq_erase_nvm_exit;
2751 }
2752
2753 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2754
2755 /* If this is the last command in a series, set the proper flag. */
2756 if (last_command)
2757 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2758 cmd->module_pointer = module_pointer;
2759 cmd->offset = cpu_to_le32(offset);
2760 cmd->length = cpu_to_le16(length);
2761
2762 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2763
2764 i40e_aq_erase_nvm_exit:
2765 return status;
2766 }
2767
2768 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2769 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2770 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2771 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2772 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2773 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2774 #define I40E_DEV_FUNC_CAP_VF 0x13
2775 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2776 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2777 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2778 #define I40E_DEV_FUNC_CAP_VSI 0x17
2779 #define I40E_DEV_FUNC_CAP_DCB 0x18
2780 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2781 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
2782 #define I40E_DEV_FUNC_CAP_RSS 0x40
2783 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2784 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2785 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2786 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2787 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2788 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2789 #define I40E_DEV_FUNC_CAP_FLEX10 0xF1
2790 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2791 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2792 #define I40E_DEV_FUNC_CAP_LED 0x61
2793 #define I40E_DEV_FUNC_CAP_SDP 0x62
2794 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2795 #define I40E_DEV_FUNC_CAP_WR_CSR_PROT 0x64
2796
2797 /**
2798 * i40e_parse_discover_capabilities
2799 * @hw: pointer to the hw struct
2800 * @buff: pointer to a buffer containing device/function capability records
2801 * @cap_count: number of capability records in the list
2802 * @list_type_opc: type of capabilities list to parse
2803 *
2804 * Parse the device/function capabilities list.
2805 **/
2806 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2807 u32 cap_count,
2808 enum i40e_admin_queue_opc list_type_opc)
2809 {
2810 struct i40e_aqc_list_capabilities_element_resp *cap;
2811 u32 valid_functions, num_functions;
2812 u32 number, logical_id, phys_id;
2813 struct i40e_hw_capabilities *p;
2814 u8 major_rev;
2815 u32 i = 0;
2816 u16 id;
2817
2818 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2819
2820 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2821 p = &hw->dev_caps;
2822 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2823 p = &hw->func_caps;
2824 else
2825 return;
2826
2827 for (i = 0; i < cap_count; i++, cap++) {
2828 id = le16_to_cpu(cap->id);
2829 number = le32_to_cpu(cap->number);
2830 logical_id = le32_to_cpu(cap->logical_id);
2831 phys_id = le32_to_cpu(cap->phys_id);
2832 major_rev = cap->major_rev;
2833
2834 switch (id) {
2835 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2836 p->switch_mode = number;
2837 break;
2838 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2839 p->management_mode = number;
2840 break;
2841 case I40E_DEV_FUNC_CAP_NPAR:
2842 p->npar_enable = number;
2843 break;
2844 case I40E_DEV_FUNC_CAP_OS2BMC:
2845 p->os2bmc = number;
2846 break;
2847 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2848 p->valid_functions = number;
2849 break;
2850 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2851 if (number == 1)
2852 p->sr_iov_1_1 = true;
2853 break;
2854 case I40E_DEV_FUNC_CAP_VF:
2855 p->num_vfs = number;
2856 p->vf_base_id = logical_id;
2857 break;
2858 case I40E_DEV_FUNC_CAP_VMDQ:
2859 if (number == 1)
2860 p->vmdq = true;
2861 break;
2862 case I40E_DEV_FUNC_CAP_802_1_QBG:
2863 if (number == 1)
2864 p->evb_802_1_qbg = true;
2865 break;
2866 case I40E_DEV_FUNC_CAP_802_1_QBH:
2867 if (number == 1)
2868 p->evb_802_1_qbh = true;
2869 break;
2870 case I40E_DEV_FUNC_CAP_VSI:
2871 p->num_vsis = number;
2872 break;
2873 case I40E_DEV_FUNC_CAP_DCB:
2874 if (number == 1) {
2875 p->dcb = true;
2876 p->enabled_tcmap = logical_id;
2877 p->maxtc = phys_id;
2878 }
2879 break;
2880 case I40E_DEV_FUNC_CAP_FCOE:
2881 if (number == 1)
2882 p->fcoe = true;
2883 break;
2884 case I40E_DEV_FUNC_CAP_ISCSI:
2885 if (number == 1)
2886 p->iscsi = true;
2887 break;
2888 case I40E_DEV_FUNC_CAP_RSS:
2889 p->rss = true;
2890 p->rss_table_size = number;
2891 p->rss_table_entry_width = logical_id;
2892 break;
2893 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2894 p->num_rx_qp = number;
2895 p->base_queue = phys_id;
2896 break;
2897 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2898 p->num_tx_qp = number;
2899 p->base_queue = phys_id;
2900 break;
2901 case I40E_DEV_FUNC_CAP_MSIX:
2902 p->num_msix_vectors = number;
2903 break;
2904 case I40E_DEV_FUNC_CAP_MSIX_VF:
2905 p->num_msix_vectors_vf = number;
2906 break;
2907 case I40E_DEV_FUNC_CAP_FLEX10:
2908 if (major_rev == 1) {
2909 if (number == 1) {
2910 p->flex10_enable = true;
2911 p->flex10_capable = true;
2912 }
2913 } else {
2914 /* Capability revision >= 2 */
2915 if (number & 1)
2916 p->flex10_enable = true;
2917 if (number & 2)
2918 p->flex10_capable = true;
2919 }
2920 p->flex10_mode = logical_id;
2921 p->flex10_status = phys_id;
2922 break;
2923 case I40E_DEV_FUNC_CAP_CEM:
2924 if (number == 1)
2925 p->mgmt_cem = true;
2926 break;
2927 case I40E_DEV_FUNC_CAP_IWARP:
2928 if (number == 1)
2929 p->iwarp = true;
2930 break;
2931 case I40E_DEV_FUNC_CAP_LED:
2932 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2933 p->led[phys_id] = true;
2934 break;
2935 case I40E_DEV_FUNC_CAP_SDP:
2936 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2937 p->sdp[phys_id] = true;
2938 break;
2939 case I40E_DEV_FUNC_CAP_MDIO:
2940 if (number == 1) {
2941 p->mdio_port_num = phys_id;
2942 p->mdio_port_mode = logical_id;
2943 }
2944 break;
2945 case I40E_DEV_FUNC_CAP_IEEE_1588:
2946 if (number == 1)
2947 p->ieee_1588 = true;
2948 break;
2949 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2950 p->fd = true;
2951 p->fd_filters_guaranteed = number;
2952 p->fd_filters_best_effort = logical_id;
2953 break;
2954 case I40E_DEV_FUNC_CAP_WR_CSR_PROT:
2955 p->wr_csr_prot = (u64)number;
2956 p->wr_csr_prot |= (u64)logical_id << 32;
2957 break;
2958 default:
2959 break;
2960 }
2961 }
2962
2963 if (p->fcoe)
2964 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
2965
2966 /* Software override ensuring FCoE is disabled if npar or mfp
2967 * mode because it is not supported in these modes.
2968 */
2969 if (p->npar_enable || p->flex10_enable)
2970 p->fcoe = false;
2971
2972 /* count the enabled ports (aka the "not disabled" ports) */
2973 hw->num_ports = 0;
2974 for (i = 0; i < 4; i++) {
2975 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
2976 u64 port_cfg = 0;
2977
2978 /* use AQ read to get the physical register offset instead
2979 * of the port relative offset
2980 */
2981 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
2982 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
2983 hw->num_ports++;
2984 }
2985
2986 valid_functions = p->valid_functions;
2987 num_functions = 0;
2988 while (valid_functions) {
2989 if (valid_functions & 1)
2990 num_functions++;
2991 valid_functions >>= 1;
2992 }
2993
2994 /* partition id is 1-based, and functions are evenly spread
2995 * across the ports as partitions
2996 */
2997 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
2998 hw->num_partitions = num_functions / hw->num_ports;
2999
3000 /* additional HW specific goodies that might
3001 * someday be HW version specific
3002 */
3003 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3004 }
3005
3006 /**
3007 * i40e_aq_discover_capabilities
3008 * @hw: pointer to the hw struct
3009 * @buff: a virtual buffer to hold the capabilities
3010 * @buff_size: Size of the virtual buffer
3011 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3012 * @list_type_opc: capabilities type to discover - pass in the command opcode
3013 * @cmd_details: pointer to command details structure or NULL
3014 *
3015 * Get the device capabilities descriptions from the firmware
3016 **/
3017 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3018 void *buff, u16 buff_size, u16 *data_size,
3019 enum i40e_admin_queue_opc list_type_opc,
3020 struct i40e_asq_cmd_details *cmd_details)
3021 {
3022 struct i40e_aqc_list_capabilites *cmd;
3023 struct i40e_aq_desc desc;
3024 i40e_status status = 0;
3025
3026 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3027
3028 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3029 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3030 status = I40E_ERR_PARAM;
3031 goto exit;
3032 }
3033
3034 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3035
3036 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3037 if (buff_size > I40E_AQ_LARGE_BUF)
3038 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3039
3040 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3041 *data_size = le16_to_cpu(desc.datalen);
3042
3043 if (status)
3044 goto exit;
3045
3046 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3047 list_type_opc);
3048
3049 exit:
3050 return status;
3051 }
3052
3053 /**
3054 * i40e_aq_update_nvm
3055 * @hw: pointer to the hw struct
3056 * @module_pointer: module pointer location in words from the NVM beginning
3057 * @offset: byte offset from the module beginning
3058 * @length: length of the section to be written (in bytes from the offset)
3059 * @data: command buffer (size [bytes] = length)
3060 * @last_command: tells if this is the last command in a series
3061 * @cmd_details: pointer to command details structure or NULL
3062 *
3063 * Update the NVM using the admin queue commands
3064 **/
3065 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3066 u32 offset, u16 length, void *data,
3067 bool last_command,
3068 struct i40e_asq_cmd_details *cmd_details)
3069 {
3070 struct i40e_aq_desc desc;
3071 struct i40e_aqc_nvm_update *cmd =
3072 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3073 i40e_status status;
3074
3075 /* In offset the highest byte must be zeroed. */
3076 if (offset & 0xFF000000) {
3077 status = I40E_ERR_PARAM;
3078 goto i40e_aq_update_nvm_exit;
3079 }
3080
3081 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3082
3083 /* If this is the last command in a series, set the proper flag. */
3084 if (last_command)
3085 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3086 cmd->module_pointer = module_pointer;
3087 cmd->offset = cpu_to_le32(offset);
3088 cmd->length = cpu_to_le16(length);
3089
3090 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3091 if (length > I40E_AQ_LARGE_BUF)
3092 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3093
3094 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3095
3096 i40e_aq_update_nvm_exit:
3097 return status;
3098 }
3099
3100 /**
3101 * i40e_aq_get_lldp_mib
3102 * @hw: pointer to the hw struct
3103 * @bridge_type: type of bridge requested
3104 * @mib_type: Local, Remote or both Local and Remote MIBs
3105 * @buff: pointer to a user supplied buffer to store the MIB block
3106 * @buff_size: size of the buffer (in bytes)
3107 * @local_len : length of the returned Local LLDP MIB
3108 * @remote_len: length of the returned Remote LLDP MIB
3109 * @cmd_details: pointer to command details structure or NULL
3110 *
3111 * Requests the complete LLDP MIB (entire packet).
3112 **/
3113 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3114 u8 mib_type, void *buff, u16 buff_size,
3115 u16 *local_len, u16 *remote_len,
3116 struct i40e_asq_cmd_details *cmd_details)
3117 {
3118 struct i40e_aq_desc desc;
3119 struct i40e_aqc_lldp_get_mib *cmd =
3120 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3121 struct i40e_aqc_lldp_get_mib *resp =
3122 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3123 i40e_status status;
3124
3125 if (buff_size == 0 || !buff)
3126 return I40E_ERR_PARAM;
3127
3128 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3129 /* Indirect Command */
3130 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3131
3132 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3133 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3134 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3135
3136 desc.datalen = cpu_to_le16(buff_size);
3137
3138 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3139 if (buff_size > I40E_AQ_LARGE_BUF)
3140 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3141
3142 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3143 if (!status) {
3144 if (local_len != NULL)
3145 *local_len = le16_to_cpu(resp->local_len);
3146 if (remote_len != NULL)
3147 *remote_len = le16_to_cpu(resp->remote_len);
3148 }
3149
3150 return status;
3151 }
3152
3153 /**
3154 * i40e_aq_cfg_lldp_mib_change_event
3155 * @hw: pointer to the hw struct
3156 * @enable_update: Enable or Disable event posting
3157 * @cmd_details: pointer to command details structure or NULL
3158 *
3159 * Enable or Disable posting of an event on ARQ when LLDP MIB
3160 * associated with the interface changes
3161 **/
3162 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3163 bool enable_update,
3164 struct i40e_asq_cmd_details *cmd_details)
3165 {
3166 struct i40e_aq_desc desc;
3167 struct i40e_aqc_lldp_update_mib *cmd =
3168 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3169 i40e_status status;
3170
3171 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3172
3173 if (!enable_update)
3174 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3175
3176 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3177
3178 return status;
3179 }
3180
3181 /**
3182 * i40e_aq_stop_lldp
3183 * @hw: pointer to the hw struct
3184 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3185 * @cmd_details: pointer to command details structure or NULL
3186 *
3187 * Stop or Shutdown the embedded LLDP Agent
3188 **/
3189 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3190 struct i40e_asq_cmd_details *cmd_details)
3191 {
3192 struct i40e_aq_desc desc;
3193 struct i40e_aqc_lldp_stop *cmd =
3194 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3195 i40e_status status;
3196
3197 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3198
3199 if (shutdown_agent)
3200 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3201
3202 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3203
3204 return status;
3205 }
3206
3207 /**
3208 * i40e_aq_start_lldp
3209 * @hw: pointer to the hw struct
3210 * @cmd_details: pointer to command details structure or NULL
3211 *
3212 * Start the embedded LLDP Agent on all ports.
3213 **/
3214 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3215 struct i40e_asq_cmd_details *cmd_details)
3216 {
3217 struct i40e_aq_desc desc;
3218 struct i40e_aqc_lldp_start *cmd =
3219 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3220 i40e_status status;
3221
3222 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3223
3224 cmd->command = I40E_AQ_LLDP_AGENT_START;
3225
3226 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3227
3228 return status;
3229 }
3230
3231 /**
3232 * i40e_aq_get_cee_dcb_config
3233 * @hw: pointer to the hw struct
3234 * @buff: response buffer that stores CEE operational configuration
3235 * @buff_size: size of the buffer passed
3236 * @cmd_details: pointer to command details structure or NULL
3237 *
3238 * Get CEE DCBX mode operational configuration from firmware
3239 **/
3240 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3241 void *buff, u16 buff_size,
3242 struct i40e_asq_cmd_details *cmd_details)
3243 {
3244 struct i40e_aq_desc desc;
3245 i40e_status status;
3246
3247 if (buff_size == 0 || !buff)
3248 return I40E_ERR_PARAM;
3249
3250 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3251
3252 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3253 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3254 cmd_details);
3255
3256 return status;
3257 }
3258
3259 /**
3260 * i40e_aq_add_udp_tunnel
3261 * @hw: pointer to the hw struct
3262 * @udp_port: the UDP port to add
3263 * @header_len: length of the tunneling header length in DWords
3264 * @protocol_index: protocol index type
3265 * @filter_index: pointer to filter index
3266 * @cmd_details: pointer to command details structure or NULL
3267 **/
3268 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3269 u16 udp_port, u8 protocol_index,
3270 u8 *filter_index,
3271 struct i40e_asq_cmd_details *cmd_details)
3272 {
3273 struct i40e_aq_desc desc;
3274 struct i40e_aqc_add_udp_tunnel *cmd =
3275 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3276 struct i40e_aqc_del_udp_tunnel_completion *resp =
3277 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3278 i40e_status status;
3279
3280 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3281
3282 cmd->udp_port = cpu_to_le16(udp_port);
3283 cmd->protocol_type = protocol_index;
3284
3285 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3286
3287 if (!status && filter_index)
3288 *filter_index = resp->index;
3289
3290 return status;
3291 }
3292
3293 /**
3294 * i40e_aq_del_udp_tunnel
3295 * @hw: pointer to the hw struct
3296 * @index: filter index
3297 * @cmd_details: pointer to command details structure or NULL
3298 **/
3299 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3300 struct i40e_asq_cmd_details *cmd_details)
3301 {
3302 struct i40e_aq_desc desc;
3303 struct i40e_aqc_remove_udp_tunnel *cmd =
3304 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3305 i40e_status status;
3306
3307 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3308
3309 cmd->index = index;
3310
3311 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3312
3313 return status;
3314 }
3315
3316 /**
3317 * i40e_aq_delete_element - Delete switch element
3318 * @hw: pointer to the hw struct
3319 * @seid: the SEID to delete from the switch
3320 * @cmd_details: pointer to command details structure or NULL
3321 *
3322 * This deletes a switch element from the switch.
3323 **/
3324 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3325 struct i40e_asq_cmd_details *cmd_details)
3326 {
3327 struct i40e_aq_desc desc;
3328 struct i40e_aqc_switch_seid *cmd =
3329 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3330 i40e_status status;
3331
3332 if (seid == 0)
3333 return I40E_ERR_PARAM;
3334
3335 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3336
3337 cmd->seid = cpu_to_le16(seid);
3338
3339 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3340
3341 return status;
3342 }
3343
3344 /**
3345 * i40e_aq_dcb_updated - DCB Updated Command
3346 * @hw: pointer to the hw struct
3347 * @cmd_details: pointer to command details structure or NULL
3348 *
3349 * EMP will return when the shared RPB settings have been
3350 * recomputed and modified. The retval field in the descriptor
3351 * will be set to 0 when RPB is modified.
3352 **/
3353 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3354 struct i40e_asq_cmd_details *cmd_details)
3355 {
3356 struct i40e_aq_desc desc;
3357 i40e_status status;
3358
3359 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3360
3361 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3362
3363 return status;
3364 }
3365
3366 /**
3367 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3368 * @hw: pointer to the hw struct
3369 * @seid: seid for the physical port/switching component/vsi
3370 * @buff: Indirect buffer to hold data parameters and response
3371 * @buff_size: Indirect buffer size
3372 * @opcode: Tx scheduler AQ command opcode
3373 * @cmd_details: pointer to command details structure or NULL
3374 *
3375 * Generic command handler for Tx scheduler AQ commands
3376 **/
3377 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3378 void *buff, u16 buff_size,
3379 enum i40e_admin_queue_opc opcode,
3380 struct i40e_asq_cmd_details *cmd_details)
3381 {
3382 struct i40e_aq_desc desc;
3383 struct i40e_aqc_tx_sched_ind *cmd =
3384 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3385 i40e_status status;
3386 bool cmd_param_flag = false;
3387
3388 switch (opcode) {
3389 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3390 case i40e_aqc_opc_configure_vsi_tc_bw:
3391 case i40e_aqc_opc_enable_switching_comp_ets:
3392 case i40e_aqc_opc_modify_switching_comp_ets:
3393 case i40e_aqc_opc_disable_switching_comp_ets:
3394 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3395 case i40e_aqc_opc_configure_switching_comp_bw_config:
3396 cmd_param_flag = true;
3397 break;
3398 case i40e_aqc_opc_query_vsi_bw_config:
3399 case i40e_aqc_opc_query_vsi_ets_sla_config:
3400 case i40e_aqc_opc_query_switching_comp_ets_config:
3401 case i40e_aqc_opc_query_port_ets_config:
3402 case i40e_aqc_opc_query_switching_comp_bw_config:
3403 cmd_param_flag = false;
3404 break;
3405 default:
3406 return I40E_ERR_PARAM;
3407 }
3408
3409 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3410
3411 /* Indirect command */
3412 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3413 if (cmd_param_flag)
3414 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3415 if (buff_size > I40E_AQ_LARGE_BUF)
3416 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3417
3418 desc.datalen = cpu_to_le16(buff_size);
3419
3420 cmd->vsi_seid = cpu_to_le16(seid);
3421
3422 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3423
3424 return status;
3425 }
3426
3427 /**
3428 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3429 * @hw: pointer to the hw struct
3430 * @seid: VSI seid
3431 * @credit: BW limit credits (0 = disabled)
3432 * @max_credit: Max BW limit credits
3433 * @cmd_details: pointer to command details structure or NULL
3434 **/
3435 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3436 u16 seid, u16 credit, u8 max_credit,
3437 struct i40e_asq_cmd_details *cmd_details)
3438 {
3439 struct i40e_aq_desc desc;
3440 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3441 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3442 i40e_status status;
3443
3444 i40e_fill_default_direct_cmd_desc(&desc,
3445 i40e_aqc_opc_configure_vsi_bw_limit);
3446
3447 cmd->vsi_seid = cpu_to_le16(seid);
3448 cmd->credit = cpu_to_le16(credit);
3449 cmd->max_credit = max_credit;
3450
3451 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3452
3453 return status;
3454 }
3455
3456 /**
3457 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3458 * @hw: pointer to the hw struct
3459 * @seid: VSI seid
3460 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3461 * @cmd_details: pointer to command details structure or NULL
3462 **/
3463 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3464 u16 seid,
3465 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3466 struct i40e_asq_cmd_details *cmd_details)
3467 {
3468 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3469 i40e_aqc_opc_configure_vsi_tc_bw,
3470 cmd_details);
3471 }
3472
3473 /**
3474 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3475 * @hw: pointer to the hw struct
3476 * @seid: seid of the switching component connected to Physical Port
3477 * @ets_data: Buffer holding ETS parameters
3478 * @cmd_details: pointer to command details structure or NULL
3479 **/
3480 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3481 u16 seid,
3482 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3483 enum i40e_admin_queue_opc opcode,
3484 struct i40e_asq_cmd_details *cmd_details)
3485 {
3486 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3487 sizeof(*ets_data), opcode, cmd_details);
3488 }
3489
3490 /**
3491 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3492 * @hw: pointer to the hw struct
3493 * @seid: seid of the switching component
3494 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3495 * @cmd_details: pointer to command details structure or NULL
3496 **/
3497 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3498 u16 seid,
3499 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3500 struct i40e_asq_cmd_details *cmd_details)
3501 {
3502 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3503 i40e_aqc_opc_configure_switching_comp_bw_config,
3504 cmd_details);
3505 }
3506
3507 /**
3508 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3509 * @hw: pointer to the hw struct
3510 * @seid: seid of the VSI
3511 * @bw_data: Buffer to hold VSI BW configuration
3512 * @cmd_details: pointer to command details structure or NULL
3513 **/
3514 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3515 u16 seid,
3516 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3517 struct i40e_asq_cmd_details *cmd_details)
3518 {
3519 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3520 i40e_aqc_opc_query_vsi_bw_config,
3521 cmd_details);
3522 }
3523
3524 /**
3525 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3526 * @hw: pointer to the hw struct
3527 * @seid: seid of the VSI
3528 * @bw_data: Buffer to hold VSI BW configuration per TC
3529 * @cmd_details: pointer to command details structure or NULL
3530 **/
3531 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3532 u16 seid,
3533 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3534 struct i40e_asq_cmd_details *cmd_details)
3535 {
3536 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3537 i40e_aqc_opc_query_vsi_ets_sla_config,
3538 cmd_details);
3539 }
3540
3541 /**
3542 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3543 * @hw: pointer to the hw struct
3544 * @seid: seid of the switching component
3545 * @bw_data: Buffer to hold switching component's per TC BW config
3546 * @cmd_details: pointer to command details structure or NULL
3547 **/
3548 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3549 u16 seid,
3550 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3551 struct i40e_asq_cmd_details *cmd_details)
3552 {
3553 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3554 i40e_aqc_opc_query_switching_comp_ets_config,
3555 cmd_details);
3556 }
3557
3558 /**
3559 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3560 * @hw: pointer to the hw struct
3561 * @seid: seid of the VSI or switching component connected to Physical Port
3562 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3563 * @cmd_details: pointer to command details structure or NULL
3564 **/
3565 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3566 u16 seid,
3567 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3568 struct i40e_asq_cmd_details *cmd_details)
3569 {
3570 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3571 i40e_aqc_opc_query_port_ets_config,
3572 cmd_details);
3573 }
3574
3575 /**
3576 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3577 * @hw: pointer to the hw struct
3578 * @seid: seid of the switching component
3579 * @bw_data: Buffer to hold switching component's BW configuration
3580 * @cmd_details: pointer to command details structure or NULL
3581 **/
3582 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3583 u16 seid,
3584 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3585 struct i40e_asq_cmd_details *cmd_details)
3586 {
3587 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3588 i40e_aqc_opc_query_switching_comp_bw_config,
3589 cmd_details);
3590 }
3591
3592 /**
3593 * i40e_validate_filter_settings
3594 * @hw: pointer to the hardware structure
3595 * @settings: Filter control settings
3596 *
3597 * Check and validate the filter control settings passed.
3598 * The function checks for the valid filter/context sizes being
3599 * passed for FCoE and PE.
3600 *
3601 * Returns 0 if the values passed are valid and within
3602 * range else returns an error.
3603 **/
3604 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3605 struct i40e_filter_control_settings *settings)
3606 {
3607 u32 fcoe_cntx_size, fcoe_filt_size;
3608 u32 pe_cntx_size, pe_filt_size;
3609 u32 fcoe_fmax;
3610 u32 val;
3611
3612 /* Validate FCoE settings passed */
3613 switch (settings->fcoe_filt_num) {
3614 case I40E_HASH_FILTER_SIZE_1K:
3615 case I40E_HASH_FILTER_SIZE_2K:
3616 case I40E_HASH_FILTER_SIZE_4K:
3617 case I40E_HASH_FILTER_SIZE_8K:
3618 case I40E_HASH_FILTER_SIZE_16K:
3619 case I40E_HASH_FILTER_SIZE_32K:
3620 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3621 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3622 break;
3623 default:
3624 return I40E_ERR_PARAM;
3625 }
3626
3627 switch (settings->fcoe_cntx_num) {
3628 case I40E_DMA_CNTX_SIZE_512:
3629 case I40E_DMA_CNTX_SIZE_1K:
3630 case I40E_DMA_CNTX_SIZE_2K:
3631 case I40E_DMA_CNTX_SIZE_4K:
3632 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3633 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3634 break;
3635 default:
3636 return I40E_ERR_PARAM;
3637 }
3638
3639 /* Validate PE settings passed */
3640 switch (settings->pe_filt_num) {
3641 case I40E_HASH_FILTER_SIZE_1K:
3642 case I40E_HASH_FILTER_SIZE_2K:
3643 case I40E_HASH_FILTER_SIZE_4K:
3644 case I40E_HASH_FILTER_SIZE_8K:
3645 case I40E_HASH_FILTER_SIZE_16K:
3646 case I40E_HASH_FILTER_SIZE_32K:
3647 case I40E_HASH_FILTER_SIZE_64K:
3648 case I40E_HASH_FILTER_SIZE_128K:
3649 case I40E_HASH_FILTER_SIZE_256K:
3650 case I40E_HASH_FILTER_SIZE_512K:
3651 case I40E_HASH_FILTER_SIZE_1M:
3652 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3653 pe_filt_size <<= (u32)settings->pe_filt_num;
3654 break;
3655 default:
3656 return I40E_ERR_PARAM;
3657 }
3658
3659 switch (settings->pe_cntx_num) {
3660 case I40E_DMA_CNTX_SIZE_512:
3661 case I40E_DMA_CNTX_SIZE_1K:
3662 case I40E_DMA_CNTX_SIZE_2K:
3663 case I40E_DMA_CNTX_SIZE_4K:
3664 case I40E_DMA_CNTX_SIZE_8K:
3665 case I40E_DMA_CNTX_SIZE_16K:
3666 case I40E_DMA_CNTX_SIZE_32K:
3667 case I40E_DMA_CNTX_SIZE_64K:
3668 case I40E_DMA_CNTX_SIZE_128K:
3669 case I40E_DMA_CNTX_SIZE_256K:
3670 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3671 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3672 break;
3673 default:
3674 return I40E_ERR_PARAM;
3675 }
3676
3677 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3678 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3679 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3680 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3681 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3682 return I40E_ERR_INVALID_SIZE;
3683
3684 return 0;
3685 }
3686
3687 /**
3688 * i40e_set_filter_control
3689 * @hw: pointer to the hardware structure
3690 * @settings: Filter control settings
3691 *
3692 * Set the Queue Filters for PE/FCoE and enable filters required
3693 * for a single PF. It is expected that these settings are programmed
3694 * at the driver initialization time.
3695 **/
3696 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3697 struct i40e_filter_control_settings *settings)
3698 {
3699 i40e_status ret = 0;
3700 u32 hash_lut_size = 0;
3701 u32 val;
3702
3703 if (!settings)
3704 return I40E_ERR_PARAM;
3705
3706 /* Validate the input settings */
3707 ret = i40e_validate_filter_settings(hw, settings);
3708 if (ret)
3709 return ret;
3710
3711 /* Read the PF Queue Filter control register */
3712 val = rd32(hw, I40E_PFQF_CTL_0);
3713
3714 /* Program required PE hash buckets for the PF */
3715 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3716 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3717 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3718 /* Program required PE contexts for the PF */
3719 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3720 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3721 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3722
3723 /* Program required FCoE hash buckets for the PF */
3724 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3725 val |= ((u32)settings->fcoe_filt_num <<
3726 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3727 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3728 /* Program required FCoE DDP contexts for the PF */
3729 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3730 val |= ((u32)settings->fcoe_cntx_num <<
3731 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3732 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3733
3734 /* Program Hash LUT size for the PF */
3735 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3736 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3737 hash_lut_size = 1;
3738 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3739 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3740
3741 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3742 if (settings->enable_fdir)
3743 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3744 if (settings->enable_ethtype)
3745 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3746 if (settings->enable_macvlan)
3747 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3748
3749 wr32(hw, I40E_PFQF_CTL_0, val);
3750
3751 return 0;
3752 }
3753
3754 /**
3755 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3756 * @hw: pointer to the hw struct
3757 * @mac_addr: MAC address to use in the filter
3758 * @ethtype: Ethertype to use in the filter
3759 * @flags: Flags that needs to be applied to the filter
3760 * @vsi_seid: seid of the control VSI
3761 * @queue: VSI queue number to send the packet to
3762 * @is_add: Add control packet filter if True else remove
3763 * @stats: Structure to hold information on control filter counts
3764 * @cmd_details: pointer to command details structure or NULL
3765 *
3766 * This command will Add or Remove control packet filter for a control VSI.
3767 * In return it will update the total number of perfect filter count in
3768 * the stats member.
3769 **/
3770 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3771 u8 *mac_addr, u16 ethtype, u16 flags,
3772 u16 vsi_seid, u16 queue, bool is_add,
3773 struct i40e_control_filter_stats *stats,
3774 struct i40e_asq_cmd_details *cmd_details)
3775 {
3776 struct i40e_aq_desc desc;
3777 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3778 (struct i40e_aqc_add_remove_control_packet_filter *)
3779 &desc.params.raw;
3780 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3781 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3782 &desc.params.raw;
3783 i40e_status status;
3784
3785 if (vsi_seid == 0)
3786 return I40E_ERR_PARAM;
3787
3788 if (is_add) {
3789 i40e_fill_default_direct_cmd_desc(&desc,
3790 i40e_aqc_opc_add_control_packet_filter);
3791 cmd->queue = cpu_to_le16(queue);
3792 } else {
3793 i40e_fill_default_direct_cmd_desc(&desc,
3794 i40e_aqc_opc_remove_control_packet_filter);
3795 }
3796
3797 if (mac_addr)
3798 ether_addr_copy(cmd->mac, mac_addr);
3799
3800 cmd->etype = cpu_to_le16(ethtype);
3801 cmd->flags = cpu_to_le16(flags);
3802 cmd->seid = cpu_to_le16(vsi_seid);
3803
3804 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3805
3806 if (!status && stats) {
3807 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3808 stats->etype_used = le16_to_cpu(resp->etype_used);
3809 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3810 stats->etype_free = le16_to_cpu(resp->etype_free);
3811 }
3812
3813 return status;
3814 }
3815
3816 /**
3817 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
3818 * @hw: pointer to the hw struct
3819 * @seid: VSI seid to add ethertype filter from
3820 **/
3821 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
3822 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
3823 u16 seid)
3824 {
3825 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
3826 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
3827 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
3828 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
3829 i40e_status status;
3830
3831 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
3832 seid, 0, true, NULL,
3833 NULL);
3834 if (status)
3835 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
3836 }
3837
3838 /**
3839 * i40e_aq_alternate_read
3840 * @hw: pointer to the hardware structure
3841 * @reg_addr0: address of first dword to be read
3842 * @reg_val0: pointer for data read from 'reg_addr0'
3843 * @reg_addr1: address of second dword to be read
3844 * @reg_val1: pointer for data read from 'reg_addr1'
3845 *
3846 * Read one or two dwords from alternate structure. Fields are indicated
3847 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
3848 * is not passed then only register at 'reg_addr0' is read.
3849 *
3850 **/
3851 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
3852 u32 reg_addr0, u32 *reg_val0,
3853 u32 reg_addr1, u32 *reg_val1)
3854 {
3855 struct i40e_aq_desc desc;
3856 struct i40e_aqc_alternate_write *cmd_resp =
3857 (struct i40e_aqc_alternate_write *)&desc.params.raw;
3858 i40e_status status;
3859
3860 if (!reg_val0)
3861 return I40E_ERR_PARAM;
3862
3863 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
3864 cmd_resp->address0 = cpu_to_le32(reg_addr0);
3865 cmd_resp->address1 = cpu_to_le32(reg_addr1);
3866
3867 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3868
3869 if (!status) {
3870 *reg_val0 = le32_to_cpu(cmd_resp->data0);
3871
3872 if (reg_val1)
3873 *reg_val1 = le32_to_cpu(cmd_resp->data1);
3874 }
3875
3876 return status;
3877 }
3878
3879 /**
3880 * i40e_aq_resume_port_tx
3881 * @hw: pointer to the hardware structure
3882 * @cmd_details: pointer to command details structure or NULL
3883 *
3884 * Resume port's Tx traffic
3885 **/
3886 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
3887 struct i40e_asq_cmd_details *cmd_details)
3888 {
3889 struct i40e_aq_desc desc;
3890 i40e_status status;
3891
3892 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
3893
3894 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3895
3896 return status;
3897 }
3898
3899 /**
3900 * i40e_set_pci_config_data - store PCI bus info
3901 * @hw: pointer to hardware structure
3902 * @link_status: the link status word from PCI config space
3903 *
3904 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3905 **/
3906 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
3907 {
3908 hw->bus.type = i40e_bus_type_pci_express;
3909
3910 switch (link_status & PCI_EXP_LNKSTA_NLW) {
3911 case PCI_EXP_LNKSTA_NLW_X1:
3912 hw->bus.width = i40e_bus_width_pcie_x1;
3913 break;
3914 case PCI_EXP_LNKSTA_NLW_X2:
3915 hw->bus.width = i40e_bus_width_pcie_x2;
3916 break;
3917 case PCI_EXP_LNKSTA_NLW_X4:
3918 hw->bus.width = i40e_bus_width_pcie_x4;
3919 break;
3920 case PCI_EXP_LNKSTA_NLW_X8:
3921 hw->bus.width = i40e_bus_width_pcie_x8;
3922 break;
3923 default:
3924 hw->bus.width = i40e_bus_width_unknown;
3925 break;
3926 }
3927
3928 switch (link_status & PCI_EXP_LNKSTA_CLS) {
3929 case PCI_EXP_LNKSTA_CLS_2_5GB:
3930 hw->bus.speed = i40e_bus_speed_2500;
3931 break;
3932 case PCI_EXP_LNKSTA_CLS_5_0GB:
3933 hw->bus.speed = i40e_bus_speed_5000;
3934 break;
3935 case PCI_EXP_LNKSTA_CLS_8_0GB:
3936 hw->bus.speed = i40e_bus_speed_8000;
3937 break;
3938 default:
3939 hw->bus.speed = i40e_bus_speed_unknown;
3940 break;
3941 }
3942 }
3943
3944 /**
3945 * i40e_aq_debug_dump
3946 * @hw: pointer to the hardware structure
3947 * @cluster_id: specific cluster to dump
3948 * @table_id: table id within cluster
3949 * @start_index: index of line in the block to read
3950 * @buff_size: dump buffer size
3951 * @buff: dump buffer
3952 * @ret_buff_size: actual buffer size returned
3953 * @ret_next_table: next block to read
3954 * @ret_next_index: next index to read
3955 *
3956 * Dump internal FW/HW data for debug purposes.
3957 *
3958 **/
3959 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
3960 u8 table_id, u32 start_index, u16 buff_size,
3961 void *buff, u16 *ret_buff_size,
3962 u8 *ret_next_table, u32 *ret_next_index,
3963 struct i40e_asq_cmd_details *cmd_details)
3964 {
3965 struct i40e_aq_desc desc;
3966 struct i40e_aqc_debug_dump_internals *cmd =
3967 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
3968 struct i40e_aqc_debug_dump_internals *resp =
3969 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
3970 i40e_status status;
3971
3972 if (buff_size == 0 || !buff)
3973 return I40E_ERR_PARAM;
3974
3975 i40e_fill_default_direct_cmd_desc(&desc,
3976 i40e_aqc_opc_debug_dump_internals);
3977 /* Indirect Command */
3978 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3979 if (buff_size > I40E_AQ_LARGE_BUF)
3980 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3981
3982 cmd->cluster_id = cluster_id;
3983 cmd->table_id = table_id;
3984 cmd->idx = cpu_to_le32(start_index);
3985
3986 desc.datalen = cpu_to_le16(buff_size);
3987
3988 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3989 if (!status) {
3990 if (ret_buff_size)
3991 *ret_buff_size = le16_to_cpu(desc.datalen);
3992 if (ret_next_table)
3993 *ret_next_table = resp->table_id;
3994 if (ret_next_index)
3995 *ret_next_index = le32_to_cpu(resp->idx);
3996 }
3997
3998 return status;
3999 }
4000
4001 /**
4002 * i40e_read_bw_from_alt_ram
4003 * @hw: pointer to the hardware structure
4004 * @max_bw: pointer for max_bw read
4005 * @min_bw: pointer for min_bw read
4006 * @min_valid: pointer for bool that is true if min_bw is a valid value
4007 * @max_valid: pointer for bool that is true if max_bw is a valid value
4008 *
4009 * Read bw from the alternate ram for the given pf
4010 **/
4011 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4012 u32 *max_bw, u32 *min_bw,
4013 bool *min_valid, bool *max_valid)
4014 {
4015 i40e_status status;
4016 u32 max_bw_addr, min_bw_addr;
4017
4018 /* Calculate the address of the min/max bw registers */
4019 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4020 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4021 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4022 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4023 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4024 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4025
4026 /* Read the bandwidths from alt ram */
4027 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4028 min_bw_addr, min_bw);
4029
4030 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4031 *min_valid = true;
4032 else
4033 *min_valid = false;
4034
4035 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4036 *max_valid = true;
4037 else
4038 *max_valid = false;
4039
4040 return status;
4041 }
4042
4043 /**
4044 * i40e_aq_configure_partition_bw
4045 * @hw: pointer to the hardware structure
4046 * @bw_data: Buffer holding valid pfs and bw limits
4047 * @cmd_details: pointer to command details
4048 *
4049 * Configure partitions guaranteed/max bw
4050 **/
4051 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4052 struct i40e_aqc_configure_partition_bw_data *bw_data,
4053 struct i40e_asq_cmd_details *cmd_details)
4054 {
4055 i40e_status status;
4056 struct i40e_aq_desc desc;
4057 u16 bwd_size = sizeof(*bw_data);
4058
4059 i40e_fill_default_direct_cmd_desc(&desc,
4060 i40e_aqc_opc_configure_partition_bw);
4061
4062 /* Indirect command */
4063 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4064 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4065
4066 if (bwd_size > I40E_AQ_LARGE_BUF)
4067 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4068
4069 desc.datalen = cpu_to_le16(bwd_size);
4070
4071 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4072 cmd_details);
4073
4074 return status;
4075 }
Linux kernel - Deliverables
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