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[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_nvm.c
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include "i40e_prototype.h"
28
29 /**
30 * i40e_init_nvm_ops - Initialize NVM function pointers
31 * @hw: pointer to the HW structure
32 *
33 * Setup the function pointers and the NVM info structure. Should be called
34 * once per NVM initialization, e.g. inside the i40e_init_shared_code().
35 * Please notice that the NVM term is used here (& in all methods covered
36 * in this file) as an equivalent of the FLASH part mapped into the SR.
37 * We are accessing FLASH always thru the Shadow RAM.
38 **/
39 i40e_status i40e_init_nvm(struct i40e_hw *hw)
40 {
41 struct i40e_nvm_info *nvm = &hw->nvm;
42 i40e_status ret_code = 0;
43 u32 fla, gens;
44 u8 sr_size;
45
46 /* The SR size is stored regardless of the nvm programming mode
47 * as the blank mode may be used in the factory line.
48 */
49 gens = rd32(hw, I40E_GLNVM_GENS);
50 sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
51 I40E_GLNVM_GENS_SR_SIZE_SHIFT);
52 /* Switching to words (sr_size contains power of 2KB) */
53 nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB;
54
55 /* Check if we are in the normal or blank NVM programming mode */
56 fla = rd32(hw, I40E_GLNVM_FLA);
57 if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */
58 /* Max NVM timeout */
59 nvm->timeout = I40E_MAX_NVM_TIMEOUT;
60 nvm->blank_nvm_mode = false;
61 } else { /* Blank programming mode */
62 nvm->blank_nvm_mode = true;
63 ret_code = I40E_ERR_NVM_BLANK_MODE;
64 i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n");
65 }
66
67 return ret_code;
68 }
69
70 /**
71 * i40e_acquire_nvm - Generic request for acquiring the NVM ownership
72 * @hw: pointer to the HW structure
73 * @access: NVM access type (read or write)
74 *
75 * This function will request NVM ownership for reading
76 * via the proper Admin Command.
77 **/
78 i40e_status i40e_acquire_nvm(struct i40e_hw *hw,
79 enum i40e_aq_resource_access_type access)
80 {
81 i40e_status ret_code = 0;
82 u64 gtime, timeout;
83 u64 time_left = 0;
84
85 if (hw->nvm.blank_nvm_mode)
86 goto i40e_i40e_acquire_nvm_exit;
87
88 ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,
89 0, &time_left, NULL);
90 /* Reading the Global Device Timer */
91 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
92
93 /* Store the timeout */
94 hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime;
95
96 if (ret_code)
97 i40e_debug(hw, I40E_DEBUG_NVM,
98 "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n",
99 access, time_left, ret_code, hw->aq.asq_last_status);
100
101 if (ret_code && time_left) {
102 /* Poll until the current NVM owner timeouts */
103 timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime;
104 while ((gtime < timeout) && time_left) {
105 usleep_range(10000, 20000);
106 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
107 ret_code = i40e_aq_request_resource(hw,
108 I40E_NVM_RESOURCE_ID,
109 access, 0, &time_left,
110 NULL);
111 if (!ret_code) {
112 hw->nvm.hw_semaphore_timeout =
113 I40E_MS_TO_GTIME(time_left) + gtime;
114 break;
115 }
116 }
117 if (ret_code) {
118 hw->nvm.hw_semaphore_timeout = 0;
119 i40e_debug(hw, I40E_DEBUG_NVM,
120 "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n",
121 time_left, ret_code, hw->aq.asq_last_status);
122 }
123 }
124
125 i40e_i40e_acquire_nvm_exit:
126 return ret_code;
127 }
128
129 /**
130 * i40e_release_nvm - Generic request for releasing the NVM ownership
131 * @hw: pointer to the HW structure
132 *
133 * This function will release NVM resource via the proper Admin Command.
134 **/
135 void i40e_release_nvm(struct i40e_hw *hw)
136 {
137 if (!hw->nvm.blank_nvm_mode)
138 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
139 }
140
141 /**
142 * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit
143 * @hw: pointer to the HW structure
144 *
145 * Polls the SRCTL Shadow RAM register done bit.
146 **/
147 static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
148 {
149 i40e_status ret_code = I40E_ERR_TIMEOUT;
150 u32 srctl, wait_cnt;
151
152 /* Poll the I40E_GLNVM_SRCTL until the done bit is set */
153 for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {
154 srctl = rd32(hw, I40E_GLNVM_SRCTL);
155 if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {
156 ret_code = 0;
157 break;
158 }
159 udelay(5);
160 }
161 if (ret_code == I40E_ERR_TIMEOUT)
162 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set");
163 return ret_code;
164 }
165
166 /**
167 * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register
168 * @hw: pointer to the HW structure
169 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
170 * @data: word read from the Shadow RAM
171 *
172 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
173 **/
174 static i40e_status i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
175 u16 *data)
176 {
177 i40e_status ret_code = I40E_ERR_TIMEOUT;
178 u32 sr_reg;
179
180 if (offset >= hw->nvm.sr_size) {
181 i40e_debug(hw, I40E_DEBUG_NVM,
182 "NVM read error: offset %d beyond Shadow RAM limit %d\n",
183 offset, hw->nvm.sr_size);
184 ret_code = I40E_ERR_PARAM;
185 goto read_nvm_exit;
186 }
187
188 /* Poll the done bit first */
189 ret_code = i40e_poll_sr_srctl_done_bit(hw);
190 if (!ret_code) {
191 /* Write the address and start reading */
192 sr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
193 BIT(I40E_GLNVM_SRCTL_START_SHIFT);
194 wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
195
196 /* Poll I40E_GLNVM_SRCTL until the done bit is set */
197 ret_code = i40e_poll_sr_srctl_done_bit(hw);
198 if (!ret_code) {
199 sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
200 *data = (u16)((sr_reg &
201 I40E_GLNVM_SRDATA_RDDATA_MASK)
202 >> I40E_GLNVM_SRDATA_RDDATA_SHIFT);
203 }
204 }
205 if (ret_code)
206 i40e_debug(hw, I40E_DEBUG_NVM,
207 "NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
208 offset);
209
210 read_nvm_exit:
211 return ret_code;
212 }
213
214 /**
215 * i40e_read_nvm_aq - Read Shadow RAM.
216 * @hw: pointer to the HW structure.
217 * @module_pointer: module pointer location in words from the NVM beginning
218 * @offset: offset in words from module start
219 * @words: number of words to write
220 * @data: buffer with words to write to the Shadow RAM
221 * @last_command: tells the AdminQ that this is the last command
222 *
223 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
224 **/
225 static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
226 u32 offset, u16 words, void *data,
227 bool last_command)
228 {
229 i40e_status ret_code = I40E_ERR_NVM;
230 struct i40e_asq_cmd_details cmd_details;
231
232 memset(&cmd_details, 0, sizeof(cmd_details));
233
234 /* Here we are checking the SR limit only for the flat memory model.
235 * We cannot do it for the module-based model, as we did not acquire
236 * the NVM resource yet (we cannot get the module pointer value).
237 * Firmware will check the module-based model.
238 */
239 if ((offset + words) > hw->nvm.sr_size)
240 i40e_debug(hw, I40E_DEBUG_NVM,
241 "NVM write error: offset %d beyond Shadow RAM limit %d\n",
242 (offset + words), hw->nvm.sr_size);
243 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
244 /* We can write only up to 4KB (one sector), in one AQ write */
245 i40e_debug(hw, I40E_DEBUG_NVM,
246 "NVM write fail error: tried to write %d words, limit is %d.\n",
247 words, I40E_SR_SECTOR_SIZE_IN_WORDS);
248 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
249 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
250 /* A single write cannot spread over two sectors */
251 i40e_debug(hw, I40E_DEBUG_NVM,
252 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
253 offset, words);
254 else
255 ret_code = i40e_aq_read_nvm(hw, module_pointer,
256 2 * offset, /*bytes*/
257 2 * words, /*bytes*/
258 data, last_command, &cmd_details);
259
260 return ret_code;
261 }
262
263 /**
264 * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ
265 * @hw: pointer to the HW structure
266 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
267 * @data: word read from the Shadow RAM
268 *
269 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
270 **/
271 static i40e_status i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
272 u16 *data)
273 {
274 i40e_status ret_code = I40E_ERR_TIMEOUT;
275
276 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true);
277 *data = le16_to_cpu(*(__le16 *)data);
278
279 return ret_code;
280 }
281
282 /**
283 * i40e_read_nvm_word - Reads Shadow RAM
284 * @hw: pointer to the HW structure
285 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
286 * @data: word read from the Shadow RAM
287 *
288 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
289 **/
290 i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
291 u16 *data)
292 {
293 enum i40e_status_code ret_code = 0;
294
295 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) {
296 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
297 if (!ret_code) {
298 ret_code = i40e_read_nvm_word_aq(hw, offset, data);
299 i40e_release_nvm(hw);
300 }
301 } else {
302 ret_code = i40e_read_nvm_word_srctl(hw, offset, data);
303 }
304 return ret_code;
305 }
306
307 /**
308 * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
309 * @hw: pointer to the HW structure
310 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
311 * @words: (in) number of words to read; (out) number of words actually read
312 * @data: words read from the Shadow RAM
313 *
314 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
315 * method. The buffer read is preceded by the NVM ownership take
316 * and followed by the release.
317 **/
318 static i40e_status i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
319 u16 *words, u16 *data)
320 {
321 i40e_status ret_code = 0;
322 u16 index, word;
323
324 /* Loop thru the selected region */
325 for (word = 0; word < *words; word++) {
326 index = offset + word;
327 ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]);
328 if (ret_code)
329 break;
330 }
331
332 /* Update the number of words read from the Shadow RAM */
333 *words = word;
334
335 return ret_code;
336 }
337
338 /**
339 * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ
340 * @hw: pointer to the HW structure
341 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
342 * @words: (in) number of words to read; (out) number of words actually read
343 * @data: words read from the Shadow RAM
344 *
345 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq()
346 * method. The buffer read is preceded by the NVM ownership take
347 * and followed by the release.
348 **/
349 static i40e_status i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
350 u16 *words, u16 *data)
351 {
352 i40e_status ret_code;
353 u16 read_size = *words;
354 bool last_cmd = false;
355 u16 words_read = 0;
356 u16 i = 0;
357
358 do {
359 /* Calculate number of bytes we should read in this step.
360 * FVL AQ do not allow to read more than one page at a time or
361 * to cross page boundaries.
362 */
363 if (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)
364 read_size = min(*words,
365 (u16)(I40E_SR_SECTOR_SIZE_IN_WORDS -
366 (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)));
367 else
368 read_size = min((*words - words_read),
369 I40E_SR_SECTOR_SIZE_IN_WORDS);
370
371 /* Check if this is last command, if so set proper flag */
372 if ((words_read + read_size) >= *words)
373 last_cmd = true;
374
375 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size,
376 data + words_read, last_cmd);
377 if (ret_code)
378 goto read_nvm_buffer_aq_exit;
379
380 /* Increment counter for words already read and move offset to
381 * new read location
382 */
383 words_read += read_size;
384 offset += read_size;
385 } while (words_read < *words);
386
387 for (i = 0; i < *words; i++)
388 data[i] = le16_to_cpu(((__le16 *)data)[i]);
389
390 read_nvm_buffer_aq_exit:
391 *words = words_read;
392 return ret_code;
393 }
394
395 /**
396 * i40e_read_nvm_buffer - Reads Shadow RAM buffer
397 * @hw: pointer to the HW structure
398 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
399 * @words: (in) number of words to read; (out) number of words actually read
400 * @data: words read from the Shadow RAM
401 *
402 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
403 * method. The buffer read is preceded by the NVM ownership take
404 * and followed by the release.
405 **/
406 i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
407 u16 *words, u16 *data)
408 {
409 enum i40e_status_code ret_code = 0;
410
411 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) {
412 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
413 if (!ret_code) {
414 ret_code = i40e_read_nvm_buffer_aq(hw, offset, words,
415 data);
416 i40e_release_nvm(hw);
417 }
418 } else {
419 ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data);
420 }
421 return ret_code;
422 }
423
424 /**
425 * i40e_write_nvm_aq - Writes Shadow RAM.
426 * @hw: pointer to the HW structure.
427 * @module_pointer: module pointer location in words from the NVM beginning
428 * @offset: offset in words from module start
429 * @words: number of words to write
430 * @data: buffer with words to write to the Shadow RAM
431 * @last_command: tells the AdminQ that this is the last command
432 *
433 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
434 **/
435 static i40e_status i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
436 u32 offset, u16 words, void *data,
437 bool last_command)
438 {
439 i40e_status ret_code = I40E_ERR_NVM;
440 struct i40e_asq_cmd_details cmd_details;
441
442 memset(&cmd_details, 0, sizeof(cmd_details));
443 cmd_details.wb_desc = &hw->nvm_wb_desc;
444
445 /* Here we are checking the SR limit only for the flat memory model.
446 * We cannot do it for the module-based model, as we did not acquire
447 * the NVM resource yet (we cannot get the module pointer value).
448 * Firmware will check the module-based model.
449 */
450 if ((offset + words) > hw->nvm.sr_size)
451 i40e_debug(hw, I40E_DEBUG_NVM,
452 "NVM write error: offset %d beyond Shadow RAM limit %d\n",
453 (offset + words), hw->nvm.sr_size);
454 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
455 /* We can write only up to 4KB (one sector), in one AQ write */
456 i40e_debug(hw, I40E_DEBUG_NVM,
457 "NVM write fail error: tried to write %d words, limit is %d.\n",
458 words, I40E_SR_SECTOR_SIZE_IN_WORDS);
459 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
460 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
461 /* A single write cannot spread over two sectors */
462 i40e_debug(hw, I40E_DEBUG_NVM,
463 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
464 offset, words);
465 else
466 ret_code = i40e_aq_update_nvm(hw, module_pointer,
467 2 * offset, /*bytes*/
468 2 * words, /*bytes*/
469 data, last_command, &cmd_details);
470
471 return ret_code;
472 }
473
474 /**
475 * i40e_calc_nvm_checksum - Calculates and returns the checksum
476 * @hw: pointer to hardware structure
477 * @checksum: pointer to the checksum
478 *
479 * This function calculates SW Checksum that covers the whole 64kB shadow RAM
480 * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
481 * is customer specific and unknown. Therefore, this function skips all maximum
482 * possible size of VPD (1kB).
483 **/
484 static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw,
485 u16 *checksum)
486 {
487 i40e_status ret_code;
488 struct i40e_virt_mem vmem;
489 u16 pcie_alt_module = 0;
490 u16 checksum_local = 0;
491 u16 vpd_module = 0;
492 u16 *data;
493 u16 i = 0;
494
495 ret_code = i40e_allocate_virt_mem(hw, &vmem,
496 I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16));
497 if (ret_code)
498 goto i40e_calc_nvm_checksum_exit;
499 data = (u16 *)vmem.va;
500
501 /* read pointer to VPD area */
502 ret_code = i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module);
503 if (ret_code) {
504 ret_code = I40E_ERR_NVM_CHECKSUM;
505 goto i40e_calc_nvm_checksum_exit;
506 }
507
508 /* read pointer to PCIe Alt Auto-load module */
509 ret_code = i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
510 &pcie_alt_module);
511 if (ret_code) {
512 ret_code = I40E_ERR_NVM_CHECKSUM;
513 goto i40e_calc_nvm_checksum_exit;
514 }
515
516 /* Calculate SW checksum that covers the whole 64kB shadow RAM
517 * except the VPD and PCIe ALT Auto-load modules
518 */
519 for (i = 0; i < hw->nvm.sr_size; i++) {
520 /* Read SR page */
521 if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) {
522 u16 words = I40E_SR_SECTOR_SIZE_IN_WORDS;
523
524 ret_code = i40e_read_nvm_buffer(hw, i, &words, data);
525 if (ret_code) {
526 ret_code = I40E_ERR_NVM_CHECKSUM;
527 goto i40e_calc_nvm_checksum_exit;
528 }
529 }
530
531 /* Skip Checksum word */
532 if (i == I40E_SR_SW_CHECKSUM_WORD)
533 continue;
534 /* Skip VPD module (convert byte size to word count) */
535 if ((i >= (u32)vpd_module) &&
536 (i < ((u32)vpd_module +
537 (I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) {
538 continue;
539 }
540 /* Skip PCIe ALT module (convert byte size to word count) */
541 if ((i >= (u32)pcie_alt_module) &&
542 (i < ((u32)pcie_alt_module +
543 (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) {
544 continue;
545 }
546
547 checksum_local += data[i % I40E_SR_SECTOR_SIZE_IN_WORDS];
548 }
549
550 *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local;
551
552 i40e_calc_nvm_checksum_exit:
553 i40e_free_virt_mem(hw, &vmem);
554 return ret_code;
555 }
556
557 /**
558 * i40e_update_nvm_checksum - Updates the NVM checksum
559 * @hw: pointer to hardware structure
560 *
561 * NVM ownership must be acquired before calling this function and released
562 * on ARQ completion event reception by caller.
563 * This function will commit SR to NVM.
564 **/
565 i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw)
566 {
567 i40e_status ret_code;
568 u16 checksum;
569 __le16 le_sum;
570
571 ret_code = i40e_calc_nvm_checksum(hw, &checksum);
572 le_sum = cpu_to_le16(checksum);
573 if (!ret_code)
574 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
575 1, &le_sum, true);
576
577 return ret_code;
578 }
579
580 /**
581 * i40e_validate_nvm_checksum - Validate EEPROM checksum
582 * @hw: pointer to hardware structure
583 * @checksum: calculated checksum
584 *
585 * Performs checksum calculation and validates the NVM SW checksum. If the
586 * caller does not need checksum, the value can be NULL.
587 **/
588 i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw,
589 u16 *checksum)
590 {
591 i40e_status ret_code = 0;
592 u16 checksum_sr = 0;
593 u16 checksum_local = 0;
594
595 ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
596 if (ret_code)
597 goto i40e_validate_nvm_checksum_exit;
598
599 /* Do not use i40e_read_nvm_word() because we do not want to take
600 * the synchronization semaphores twice here.
601 */
602 i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);
603
604 /* Verify read checksum from EEPROM is the same as
605 * calculated checksum
606 */
607 if (checksum_local != checksum_sr)
608 ret_code = I40E_ERR_NVM_CHECKSUM;
609
610 /* If the user cares, return the calculated checksum */
611 if (checksum)
612 *checksum = checksum_local;
613
614 i40e_validate_nvm_checksum_exit:
615 return ret_code;
616 }
617
618 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw,
619 struct i40e_nvm_access *cmd,
620 u8 *bytes, int *perrno);
621 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw,
622 struct i40e_nvm_access *cmd,
623 u8 *bytes, int *perrno);
624 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw,
625 struct i40e_nvm_access *cmd,
626 u8 *bytes, int *errno);
627 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
628 struct i40e_nvm_access *cmd,
629 int *perrno);
630 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
631 struct i40e_nvm_access *cmd,
632 int *perrno);
633 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw,
634 struct i40e_nvm_access *cmd,
635 u8 *bytes, int *perrno);
636 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw,
637 struct i40e_nvm_access *cmd,
638 u8 *bytes, int *perrno);
639 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw,
640 struct i40e_nvm_access *cmd,
641 u8 *bytes, int *perrno);
642 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
643 struct i40e_nvm_access *cmd,
644 u8 *bytes, int *perrno);
645 static inline u8 i40e_nvmupd_get_module(u32 val)
646 {
647 return (u8)(val & I40E_NVM_MOD_PNT_MASK);
648 }
649 static inline u8 i40e_nvmupd_get_transaction(u32 val)
650 {
651 return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT);
652 }
653
654 static const char * const i40e_nvm_update_state_str[] = {
655 "I40E_NVMUPD_INVALID",
656 "I40E_NVMUPD_READ_CON",
657 "I40E_NVMUPD_READ_SNT",
658 "I40E_NVMUPD_READ_LCB",
659 "I40E_NVMUPD_READ_SA",
660 "I40E_NVMUPD_WRITE_ERA",
661 "I40E_NVMUPD_WRITE_CON",
662 "I40E_NVMUPD_WRITE_SNT",
663 "I40E_NVMUPD_WRITE_LCB",
664 "I40E_NVMUPD_WRITE_SA",
665 "I40E_NVMUPD_CSUM_CON",
666 "I40E_NVMUPD_CSUM_SA",
667 "I40E_NVMUPD_CSUM_LCB",
668 "I40E_NVMUPD_STATUS",
669 "I40E_NVMUPD_EXEC_AQ",
670 "I40E_NVMUPD_GET_AQ_RESULT",
671 };
672
673 /**
674 * i40e_nvmupd_command - Process an NVM update command
675 * @hw: pointer to hardware structure
676 * @cmd: pointer to nvm update command
677 * @bytes: pointer to the data buffer
678 * @perrno: pointer to return error code
679 *
680 * Dispatches command depending on what update state is current
681 **/
682 i40e_status i40e_nvmupd_command(struct i40e_hw *hw,
683 struct i40e_nvm_access *cmd,
684 u8 *bytes, int *perrno)
685 {
686 i40e_status status;
687 enum i40e_nvmupd_cmd upd_cmd;
688
689 /* assume success */
690 *perrno = 0;
691
692 /* early check for status command and debug msgs */
693 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
694
695 i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d\n",
696 i40e_nvm_update_state_str[upd_cmd],
697 hw->nvmupd_state,
698 hw->aq.nvm_release_on_done);
699
700 if (upd_cmd == I40E_NVMUPD_INVALID) {
701 *perrno = -EFAULT;
702 i40e_debug(hw, I40E_DEBUG_NVM,
703 "i40e_nvmupd_validate_command returns %d errno %d\n",
704 upd_cmd, *perrno);
705 }
706
707 /* a status request returns immediately rather than
708 * going into the state machine
709 */
710 if (upd_cmd == I40E_NVMUPD_STATUS) {
711 bytes[0] = hw->nvmupd_state;
712 return 0;
713 }
714
715 switch (hw->nvmupd_state) {
716 case I40E_NVMUPD_STATE_INIT:
717 status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno);
718 break;
719
720 case I40E_NVMUPD_STATE_READING:
721 status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno);
722 break;
723
724 case I40E_NVMUPD_STATE_WRITING:
725 status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno);
726 break;
727
728 case I40E_NVMUPD_STATE_INIT_WAIT:
729 case I40E_NVMUPD_STATE_WRITE_WAIT:
730 status = I40E_ERR_NOT_READY;
731 *perrno = -EBUSY;
732 break;
733
734 default:
735 /* invalid state, should never happen */
736 i40e_debug(hw, I40E_DEBUG_NVM,
737 "NVMUPD: no such state %d\n", hw->nvmupd_state);
738 status = I40E_NOT_SUPPORTED;
739 *perrno = -ESRCH;
740 break;
741 }
742 return status;
743 }
744
745 /**
746 * i40e_nvmupd_state_init - Handle NVM update state Init
747 * @hw: pointer to hardware structure
748 * @cmd: pointer to nvm update command buffer
749 * @bytes: pointer to the data buffer
750 * @perrno: pointer to return error code
751 *
752 * Process legitimate commands of the Init state and conditionally set next
753 * state. Reject all other commands.
754 **/
755 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw,
756 struct i40e_nvm_access *cmd,
757 u8 *bytes, int *perrno)
758 {
759 i40e_status status = 0;
760 enum i40e_nvmupd_cmd upd_cmd;
761
762 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
763
764 switch (upd_cmd) {
765 case I40E_NVMUPD_READ_SA:
766 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
767 if (status) {
768 *perrno = i40e_aq_rc_to_posix(status,
769 hw->aq.asq_last_status);
770 } else {
771 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
772 i40e_release_nvm(hw);
773 }
774 break;
775
776 case I40E_NVMUPD_READ_SNT:
777 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
778 if (status) {
779 *perrno = i40e_aq_rc_to_posix(status,
780 hw->aq.asq_last_status);
781 } else {
782 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
783 if (status)
784 i40e_release_nvm(hw);
785 else
786 hw->nvmupd_state = I40E_NVMUPD_STATE_READING;
787 }
788 break;
789
790 case I40E_NVMUPD_WRITE_ERA:
791 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
792 if (status) {
793 *perrno = i40e_aq_rc_to_posix(status,
794 hw->aq.asq_last_status);
795 } else {
796 status = i40e_nvmupd_nvm_erase(hw, cmd, perrno);
797 if (status) {
798 i40e_release_nvm(hw);
799 } else {
800 hw->aq.nvm_release_on_done = true;
801 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
802 }
803 }
804 break;
805
806 case I40E_NVMUPD_WRITE_SA:
807 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
808 if (status) {
809 *perrno = i40e_aq_rc_to_posix(status,
810 hw->aq.asq_last_status);
811 } else {
812 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
813 if (status) {
814 i40e_release_nvm(hw);
815 } else {
816 hw->aq.nvm_release_on_done = true;
817 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
818 }
819 }
820 break;
821
822 case I40E_NVMUPD_WRITE_SNT:
823 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
824 if (status) {
825 *perrno = i40e_aq_rc_to_posix(status,
826 hw->aq.asq_last_status);
827 } else {
828 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
829 if (status)
830 i40e_release_nvm(hw);
831 else
832 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
833 }
834 break;
835
836 case I40E_NVMUPD_CSUM_SA:
837 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
838 if (status) {
839 *perrno = i40e_aq_rc_to_posix(status,
840 hw->aq.asq_last_status);
841 } else {
842 status = i40e_update_nvm_checksum(hw);
843 if (status) {
844 *perrno = hw->aq.asq_last_status ?
845 i40e_aq_rc_to_posix(status,
846 hw->aq.asq_last_status) :
847 -EIO;
848 i40e_release_nvm(hw);
849 } else {
850 hw->aq.nvm_release_on_done = true;
851 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
852 }
853 }
854 break;
855
856 case I40E_NVMUPD_EXEC_AQ:
857 status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno);
858 break;
859
860 case I40E_NVMUPD_GET_AQ_RESULT:
861 status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno);
862 break;
863
864 default:
865 i40e_debug(hw, I40E_DEBUG_NVM,
866 "NVMUPD: bad cmd %s in init state\n",
867 i40e_nvm_update_state_str[upd_cmd]);
868 status = I40E_ERR_NVM;
869 *perrno = -ESRCH;
870 break;
871 }
872 return status;
873 }
874
875 /**
876 * i40e_nvmupd_state_reading - Handle NVM update state Reading
877 * @hw: pointer to hardware structure
878 * @cmd: pointer to nvm update command buffer
879 * @bytes: pointer to the data buffer
880 * @perrno: pointer to return error code
881 *
882 * NVM ownership is already held. Process legitimate commands and set any
883 * change in state; reject all other commands.
884 **/
885 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw,
886 struct i40e_nvm_access *cmd,
887 u8 *bytes, int *perrno)
888 {
889 i40e_status status = 0;
890 enum i40e_nvmupd_cmd upd_cmd;
891
892 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
893
894 switch (upd_cmd) {
895 case I40E_NVMUPD_READ_SA:
896 case I40E_NVMUPD_READ_CON:
897 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
898 break;
899
900 case I40E_NVMUPD_READ_LCB:
901 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
902 i40e_release_nvm(hw);
903 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
904 break;
905
906 default:
907 i40e_debug(hw, I40E_DEBUG_NVM,
908 "NVMUPD: bad cmd %s in reading state.\n",
909 i40e_nvm_update_state_str[upd_cmd]);
910 status = I40E_NOT_SUPPORTED;
911 *perrno = -ESRCH;
912 break;
913 }
914 return status;
915 }
916
917 /**
918 * i40e_nvmupd_state_writing - Handle NVM update state Writing
919 * @hw: pointer to hardware structure
920 * @cmd: pointer to nvm update command buffer
921 * @bytes: pointer to the data buffer
922 * @perrno: pointer to return error code
923 *
924 * NVM ownership is already held. Process legitimate commands and set any
925 * change in state; reject all other commands
926 **/
927 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw,
928 struct i40e_nvm_access *cmd,
929 u8 *bytes, int *perrno)
930 {
931 i40e_status status = 0;
932 enum i40e_nvmupd_cmd upd_cmd;
933 bool retry_attempt = false;
934
935 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
936
937 retry:
938 switch (upd_cmd) {
939 case I40E_NVMUPD_WRITE_CON:
940 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
941 if (!status)
942 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
943 break;
944
945 case I40E_NVMUPD_WRITE_LCB:
946 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
947 if (status) {
948 *perrno = hw->aq.asq_last_status ?
949 i40e_aq_rc_to_posix(status,
950 hw->aq.asq_last_status) :
951 -EIO;
952 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
953 } else {
954 hw->aq.nvm_release_on_done = true;
955 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
956 }
957 break;
958
959 case I40E_NVMUPD_CSUM_CON:
960 status = i40e_update_nvm_checksum(hw);
961 if (status) {
962 *perrno = hw->aq.asq_last_status ?
963 i40e_aq_rc_to_posix(status,
964 hw->aq.asq_last_status) :
965 -EIO;
966 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
967 } else {
968 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
969 }
970 break;
971
972 case I40E_NVMUPD_CSUM_LCB:
973 status = i40e_update_nvm_checksum(hw);
974 if (status) {
975 *perrno = hw->aq.asq_last_status ?
976 i40e_aq_rc_to_posix(status,
977 hw->aq.asq_last_status) :
978 -EIO;
979 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
980 } else {
981 hw->aq.nvm_release_on_done = true;
982 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
983 }
984 break;
985
986 default:
987 i40e_debug(hw, I40E_DEBUG_NVM,
988 "NVMUPD: bad cmd %s in writing state.\n",
989 i40e_nvm_update_state_str[upd_cmd]);
990 status = I40E_NOT_SUPPORTED;
991 *perrno = -ESRCH;
992 break;
993 }
994
995 /* In some circumstances, a multi-write transaction takes longer
996 * than the default 3 minute timeout on the write semaphore. If
997 * the write failed with an EBUSY status, this is likely the problem,
998 * so here we try to reacquire the semaphore then retry the write.
999 * We only do one retry, then give up.
1000 */
1001 if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) &&
1002 !retry_attempt) {
1003 i40e_status old_status = status;
1004 u32 old_asq_status = hw->aq.asq_last_status;
1005 u32 gtime;
1006
1007 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
1008 if (gtime >= hw->nvm.hw_semaphore_timeout) {
1009 i40e_debug(hw, I40E_DEBUG_ALL,
1010 "NVMUPD: write semaphore expired (%d >= %lld), retrying\n",
1011 gtime, hw->nvm.hw_semaphore_timeout);
1012 i40e_release_nvm(hw);
1013 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
1014 if (status) {
1015 i40e_debug(hw, I40E_DEBUG_ALL,
1016 "NVMUPD: write semaphore reacquire failed aq_err = %d\n",
1017 hw->aq.asq_last_status);
1018 status = old_status;
1019 hw->aq.asq_last_status = old_asq_status;
1020 } else {
1021 retry_attempt = true;
1022 goto retry;
1023 }
1024 }
1025 }
1026
1027 return status;
1028 }
1029
1030 /**
1031 * i40e_nvmupd_validate_command - Validate given command
1032 * @hw: pointer to hardware structure
1033 * @cmd: pointer to nvm update command buffer
1034 * @perrno: pointer to return error code
1035 *
1036 * Return one of the valid command types or I40E_NVMUPD_INVALID
1037 **/
1038 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
1039 struct i40e_nvm_access *cmd,
1040 int *perrno)
1041 {
1042 enum i40e_nvmupd_cmd upd_cmd;
1043 u8 module, transaction;
1044
1045 /* anything that doesn't match a recognized case is an error */
1046 upd_cmd = I40E_NVMUPD_INVALID;
1047
1048 transaction = i40e_nvmupd_get_transaction(cmd->config);
1049 module = i40e_nvmupd_get_module(cmd->config);
1050
1051 /* limits on data size */
1052 if ((cmd->data_size < 1) ||
1053 (cmd->data_size > I40E_NVMUPD_MAX_DATA)) {
1054 i40e_debug(hw, I40E_DEBUG_NVM,
1055 "i40e_nvmupd_validate_command data_size %d\n",
1056 cmd->data_size);
1057 *perrno = -EFAULT;
1058 return I40E_NVMUPD_INVALID;
1059 }
1060
1061 switch (cmd->command) {
1062 case I40E_NVM_READ:
1063 switch (transaction) {
1064 case I40E_NVM_CON:
1065 upd_cmd = I40E_NVMUPD_READ_CON;
1066 break;
1067 case I40E_NVM_SNT:
1068 upd_cmd = I40E_NVMUPD_READ_SNT;
1069 break;
1070 case I40E_NVM_LCB:
1071 upd_cmd = I40E_NVMUPD_READ_LCB;
1072 break;
1073 case I40E_NVM_SA:
1074 upd_cmd = I40E_NVMUPD_READ_SA;
1075 break;
1076 case I40E_NVM_EXEC:
1077 if (module == 0xf)
1078 upd_cmd = I40E_NVMUPD_STATUS;
1079 else if (module == 0)
1080 upd_cmd = I40E_NVMUPD_GET_AQ_RESULT;
1081 break;
1082 }
1083 break;
1084
1085 case I40E_NVM_WRITE:
1086 switch (transaction) {
1087 case I40E_NVM_CON:
1088 upd_cmd = I40E_NVMUPD_WRITE_CON;
1089 break;
1090 case I40E_NVM_SNT:
1091 upd_cmd = I40E_NVMUPD_WRITE_SNT;
1092 break;
1093 case I40E_NVM_LCB:
1094 upd_cmd = I40E_NVMUPD_WRITE_LCB;
1095 break;
1096 case I40E_NVM_SA:
1097 upd_cmd = I40E_NVMUPD_WRITE_SA;
1098 break;
1099 case I40E_NVM_ERA:
1100 upd_cmd = I40E_NVMUPD_WRITE_ERA;
1101 break;
1102 case I40E_NVM_CSUM:
1103 upd_cmd = I40E_NVMUPD_CSUM_CON;
1104 break;
1105 case (I40E_NVM_CSUM|I40E_NVM_SA):
1106 upd_cmd = I40E_NVMUPD_CSUM_SA;
1107 break;
1108 case (I40E_NVM_CSUM|I40E_NVM_LCB):
1109 upd_cmd = I40E_NVMUPD_CSUM_LCB;
1110 break;
1111 case I40E_NVM_EXEC:
1112 if (module == 0)
1113 upd_cmd = I40E_NVMUPD_EXEC_AQ;
1114 break;
1115 }
1116 break;
1117 }
1118
1119 return upd_cmd;
1120 }
1121
1122 /**
1123 * i40e_nvmupd_exec_aq - Run an AQ command
1124 * @hw: pointer to hardware structure
1125 * @cmd: pointer to nvm update command buffer
1126 * @bytes: pointer to the data buffer
1127 * @perrno: pointer to return error code
1128 *
1129 * cmd structure contains identifiers and data buffer
1130 **/
1131 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw,
1132 struct i40e_nvm_access *cmd,
1133 u8 *bytes, int *perrno)
1134 {
1135 struct i40e_asq_cmd_details cmd_details;
1136 i40e_status status;
1137 struct i40e_aq_desc *aq_desc;
1138 u32 buff_size = 0;
1139 u8 *buff = NULL;
1140 u32 aq_desc_len;
1141 u32 aq_data_len;
1142
1143 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1144 memset(&cmd_details, 0, sizeof(cmd_details));
1145 cmd_details.wb_desc = &hw->nvm_wb_desc;
1146
1147 aq_desc_len = sizeof(struct i40e_aq_desc);
1148 memset(&hw->nvm_wb_desc, 0, aq_desc_len);
1149
1150 /* get the aq descriptor */
1151 if (cmd->data_size < aq_desc_len) {
1152 i40e_debug(hw, I40E_DEBUG_NVM,
1153 "NVMUPD: not enough aq desc bytes for exec, size %d < %d\n",
1154 cmd->data_size, aq_desc_len);
1155 *perrno = -EINVAL;
1156 return I40E_ERR_PARAM;
1157 }
1158 aq_desc = (struct i40e_aq_desc *)bytes;
1159
1160 /* if data buffer needed, make sure it's ready */
1161 aq_data_len = cmd->data_size - aq_desc_len;
1162 buff_size = max_t(u32, aq_data_len, le16_to_cpu(aq_desc->datalen));
1163 if (buff_size) {
1164 if (!hw->nvm_buff.va) {
1165 status = i40e_allocate_virt_mem(hw, &hw->nvm_buff,
1166 hw->aq.asq_buf_size);
1167 if (status)
1168 i40e_debug(hw, I40E_DEBUG_NVM,
1169 "NVMUPD: i40e_allocate_virt_mem for exec buff failed, %d\n",
1170 status);
1171 }
1172
1173 if (hw->nvm_buff.va) {
1174 buff = hw->nvm_buff.va;
1175 memcpy(buff, &bytes[aq_desc_len], aq_data_len);
1176 }
1177 }
1178
1179 /* and away we go! */
1180 status = i40e_asq_send_command(hw, aq_desc, buff,
1181 buff_size, &cmd_details);
1182 if (status) {
1183 i40e_debug(hw, I40E_DEBUG_NVM,
1184 "i40e_nvmupd_exec_aq err %s aq_err %s\n",
1185 i40e_stat_str(hw, status),
1186 i40e_aq_str(hw, hw->aq.asq_last_status));
1187 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1188 }
1189
1190 return status;
1191 }
1192
1193 /**
1194 * i40e_nvmupd_get_aq_result - Get the results from the previous exec_aq
1195 * @hw: pointer to hardware structure
1196 * @cmd: pointer to nvm update command buffer
1197 * @bytes: pointer to the data buffer
1198 * @perrno: pointer to return error code
1199 *
1200 * cmd structure contains identifiers and data buffer
1201 **/
1202 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
1203 struct i40e_nvm_access *cmd,
1204 u8 *bytes, int *perrno)
1205 {
1206 u32 aq_total_len;
1207 u32 aq_desc_len;
1208 int remainder;
1209 u8 *buff;
1210
1211 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1212
1213 aq_desc_len = sizeof(struct i40e_aq_desc);
1214 aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_wb_desc.datalen);
1215
1216 /* check offset range */
1217 if (cmd->offset > aq_total_len) {
1218 i40e_debug(hw, I40E_DEBUG_NVM, "%s: offset too big %d > %d\n",
1219 __func__, cmd->offset, aq_total_len);
1220 *perrno = -EINVAL;
1221 return I40E_ERR_PARAM;
1222 }
1223
1224 /* check copylength range */
1225 if (cmd->data_size > (aq_total_len - cmd->offset)) {
1226 int new_len = aq_total_len - cmd->offset;
1227
1228 i40e_debug(hw, I40E_DEBUG_NVM, "%s: copy length %d too big, trimming to %d\n",
1229 __func__, cmd->data_size, new_len);
1230 cmd->data_size = new_len;
1231 }
1232
1233 remainder = cmd->data_size;
1234 if (cmd->offset < aq_desc_len) {
1235 u32 len = aq_desc_len - cmd->offset;
1236
1237 len = min(len, cmd->data_size);
1238 i40e_debug(hw, I40E_DEBUG_NVM, "%s: aq_desc bytes %d to %d\n",
1239 __func__, cmd->offset, cmd->offset + len);
1240
1241 buff = ((u8 *)&hw->nvm_wb_desc) + cmd->offset;
1242 memcpy(bytes, buff, len);
1243
1244 bytes += len;
1245 remainder -= len;
1246 buff = hw->nvm_buff.va;
1247 } else {
1248 buff = hw->nvm_buff.va + (cmd->offset - aq_desc_len);
1249 }
1250
1251 if (remainder > 0) {
1252 int start_byte = buff - (u8 *)hw->nvm_buff.va;
1253
1254 i40e_debug(hw, I40E_DEBUG_NVM, "%s: databuf bytes %d to %d\n",
1255 __func__, start_byte, start_byte + remainder);
1256 memcpy(bytes, buff, remainder);
1257 }
1258
1259 return 0;
1260 }
1261
1262 /**
1263 * i40e_nvmupd_nvm_read - Read NVM
1264 * @hw: pointer to hardware structure
1265 * @cmd: pointer to nvm update command buffer
1266 * @bytes: pointer to the data buffer
1267 * @perrno: pointer to return error code
1268 *
1269 * cmd structure contains identifiers and data buffer
1270 **/
1271 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw,
1272 struct i40e_nvm_access *cmd,
1273 u8 *bytes, int *perrno)
1274 {
1275 struct i40e_asq_cmd_details cmd_details;
1276 i40e_status status;
1277 u8 module, transaction;
1278 bool last;
1279
1280 transaction = i40e_nvmupd_get_transaction(cmd->config);
1281 module = i40e_nvmupd_get_module(cmd->config);
1282 last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA);
1283
1284 memset(&cmd_details, 0, sizeof(cmd_details));
1285 cmd_details.wb_desc = &hw->nvm_wb_desc;
1286
1287 status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1288 bytes, last, &cmd_details);
1289 if (status) {
1290 i40e_debug(hw, I40E_DEBUG_NVM,
1291 "i40e_nvmupd_nvm_read mod 0x%x off 0x%x len 0x%x\n",
1292 module, cmd->offset, cmd->data_size);
1293 i40e_debug(hw, I40E_DEBUG_NVM,
1294 "i40e_nvmupd_nvm_read status %d aq %d\n",
1295 status, hw->aq.asq_last_status);
1296 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1297 }
1298
1299 return status;
1300 }
1301
1302 /**
1303 * i40e_nvmupd_nvm_erase - Erase an NVM module
1304 * @hw: pointer to hardware structure
1305 * @cmd: pointer to nvm update command buffer
1306 * @perrno: pointer to return error code
1307 *
1308 * module, offset, data_size and data are in cmd structure
1309 **/
1310 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
1311 struct i40e_nvm_access *cmd,
1312 int *perrno)
1313 {
1314 i40e_status status = 0;
1315 struct i40e_asq_cmd_details cmd_details;
1316 u8 module, transaction;
1317 bool last;
1318
1319 transaction = i40e_nvmupd_get_transaction(cmd->config);
1320 module = i40e_nvmupd_get_module(cmd->config);
1321 last = (transaction & I40E_NVM_LCB);
1322
1323 memset(&cmd_details, 0, sizeof(cmd_details));
1324 cmd_details.wb_desc = &hw->nvm_wb_desc;
1325
1326 status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1327 last, &cmd_details);
1328 if (status) {
1329 i40e_debug(hw, I40E_DEBUG_NVM,
1330 "i40e_nvmupd_nvm_erase mod 0x%x off 0x%x len 0x%x\n",
1331 module, cmd->offset, cmd->data_size);
1332 i40e_debug(hw, I40E_DEBUG_NVM,
1333 "i40e_nvmupd_nvm_erase status %d aq %d\n",
1334 status, hw->aq.asq_last_status);
1335 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1336 }
1337
1338 return status;
1339 }
1340
1341 /**
1342 * i40e_nvmupd_nvm_write - Write NVM
1343 * @hw: pointer to hardware structure
1344 * @cmd: pointer to nvm update command buffer
1345 * @bytes: pointer to the data buffer
1346 * @perrno: pointer to return error code
1347 *
1348 * module, offset, data_size and data are in cmd structure
1349 **/
1350 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw,
1351 struct i40e_nvm_access *cmd,
1352 u8 *bytes, int *perrno)
1353 {
1354 i40e_status status = 0;
1355 struct i40e_asq_cmd_details cmd_details;
1356 u8 module, transaction;
1357 bool last;
1358
1359 transaction = i40e_nvmupd_get_transaction(cmd->config);
1360 module = i40e_nvmupd_get_module(cmd->config);
1361 last = (transaction & I40E_NVM_LCB);
1362
1363 memset(&cmd_details, 0, sizeof(cmd_details));
1364 cmd_details.wb_desc = &hw->nvm_wb_desc;
1365
1366 status = i40e_aq_update_nvm(hw, module, cmd->offset,
1367 (u16)cmd->data_size, bytes, last,
1368 &cmd_details);
1369 if (status) {
1370 i40e_debug(hw, I40E_DEBUG_NVM,
1371 "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n",
1372 module, cmd->offset, cmd->data_size);
1373 i40e_debug(hw, I40E_DEBUG_NVM,
1374 "i40e_nvmupd_nvm_write status %d aq %d\n",
1375 status, hw->aq.asq_last_status);
1376 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1377 }
1378
1379 return status;
1380 }
Linux kernel - Deliverables
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